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gerrit-public.fairphone.software / toolchain / llvm-project / e64a81475c3e705d35cf74c451ced12ee0dc9ffb / . / llvm / lib / Target / AArch64 / Disassembler / AArch64Disassembler.cpp
blob: b2b542bc944c83136cbe30bd07083a140ae07b97 [file] [log] [blame]
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1//===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64Disassembler.h"
14#include "AArch64ExternalSymbolizer.h"
15#include "AArch64Subtarget.h"
16#include "MCTargetDesc/AArch64AddressingModes.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]17#include "MCTargetDesc/AArch64MCTargetDesc.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]18#include "Utils/AArch64BaseInfo.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]19#include "llvm-c/Disassembler.h"
20#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]21#include "llvm/MC/MCFixedLenDisassembler.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]22#include "llvm/MC/MCInst.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]23#include "llvm/Support/Compiler.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]24#include "llvm/Support/Debug.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]25#include "llvm/Support/ErrorHandling.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]26#include "llvm/Support/TargetRegistry.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]27#include <algorithm>
28#include <memory>
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]29
30using namespace llvm;
31
32#define DEBUG_TYPE "aarch64-disassembler"
33
34// Pull DecodeStatus and its enum values into the global namespace.
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]35using DecodeStatus = MCDisassembler::DecodeStatus;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]36
37// Forward declare these because the autogenerated code will reference them.
38// Definitions are further down.
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]39static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]40 unsigned RegNo, uint64_t Address,
41 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]42static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]43 unsigned RegNo,
44 uint64_t Address,
45 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]46static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]47 uint64_t Address,
48 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]49static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]50 uint64_t Address,
51 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]52static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]53 uint64_t Address,
54 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]55static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]56 uint64_t Address,
57 const void *Decoder);
Sander de Smalen367694b2018-04-20 08:54:49 +0000[diff] [blame]58static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
59 uint64_t Address,
60 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]61static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]62 uint64_t Address,
63 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]64static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]65 unsigned RegNo, uint64_t Address,
66 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]67static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]68 uint64_t Address,
69 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]70static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]71 unsigned RegNo, uint64_t Address,
72 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]73static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]74 uint64_t Address,
75 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]76static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]77 uint64_t Address,
78 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]79static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]80 uint64_t Address,
81 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]82static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]83 uint64_t Address,
84 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]85static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]86 uint64_t Address,
87 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]88static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]89 uint64_t Address,
90 const void *Decoder);
Florian Hahn91f11e52017-11-07 16:45:48 +0000[diff] [blame]91static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
92 uint64_t Address,
93 const void *Decode);
Sander de Smalen8cd1f532018-07-03 15:31:04 +0000[diff] [blame]94static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
95 uint64_t Address,
96 const void *Decode);
97static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
98 uint64_t Address,
99 const void *Decode);
Sander de Smalenf836af82018-04-16 07:09:29 +0000[diff] [blame]100static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
101 uint64_t Address,
102 const void *Decode);
Sander de Smalend239eb32018-04-16 10:10:48 +0000[diff] [blame]103static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
104 uint64_t Address,
105 const void *Decode);
Sander de Smalen7a210db2018-04-16 10:46:18 +0000[diff] [blame]106static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
107 uint64_t Address,
108 const void *Decode);
Sander de Smalencd6be962017-12-20 11:02:42 +0000[diff] [blame]109static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
110 uint64_t Address,
111 const void *Decode);
Sander de Smalen906a5de2018-01-09 17:01:27 +0000[diff] [blame]112static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
113 uint64_t Address,
114 const void *Decode);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]115
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]116static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]117 uint64_t Address,
118 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]119static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]120 uint64_t Address,
121 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]122static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]123 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]124static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]125 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]126static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]127 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]128static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]129 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]130static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]131 uint64_t Address,
132 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]133static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]134 uint64_t Address,
135 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]136static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]137 uint64_t Address,
138 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]139static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
140 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]141 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]142static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]143 uint64_t Address,
144 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]145static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]146 uint64_t Address,
147 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]148static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
149 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]150 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]151static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
152 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]153 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]154static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]155 uint64_t Address,
156 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]157static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
158 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]159 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]160static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]161 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]162static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]163 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]164static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]165 uint64_t Address,
166 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]167static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]168 uint64_t Address,
169 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]170static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]171 uint64_t Address, const void *Decoder);
172
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]173static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]174 uint64_t Address,
175 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]176static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]177 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]178static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]179 uint64_t Addr,
180 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]181static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]182 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]183static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]184 uint64_t Addr,
185 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]186static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]187 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]188static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]189 uint64_t Addr,
190 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]191static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]192 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]193static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]194 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]195static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]196 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]197static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]198 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]199static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]200 uint64_t Addr, const void *Decoder);
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]201static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
202 unsigned RegNo,
203 uint64_t Addr,
204 const void *Decoder);
205static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
206 unsigned RegNo,
207 uint64_t Addr,
208 const void *Decoder);
Sander de Smalen81fcf862018-02-06 13:13:21 +0000[diff] [blame]209static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
210 uint32_t insn,
211 uint64_t Address,
212 const void *Decoder);
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]213template<int Bits>
214static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
215 uint64_t Address, const void *Decoder);
Sander de Smalen62770792018-05-25 09:47:52 +0000[diff] [blame]216template <int ElementWidth>
217static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
218 uint64_t Addr, const void *Decoder);
Sander de Smalen18ac8f92018-06-15 15:47:44 +0000[diff] [blame]219static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
220 uint64_t Addr, const void *Decoder);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]221
222static bool Check(DecodeStatus &Out, DecodeStatus In) {
223 switch (In) {
224 case MCDisassembler::Success:
225 // Out stays the same.
226 return true;
227 case MCDisassembler::SoftFail:
228 Out = In;
229 return true;
230 case MCDisassembler::Fail:
231 Out = In;
232 return false;
233 }
234 llvm_unreachable("Invalid DecodeStatus!");
235}
236
237#include "AArch64GenDisassemblerTables.inc"
238#include "AArch64GenInstrInfo.inc"
239
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]240#define Success MCDisassembler::Success
241#define Fail MCDisassembler::Fail
242#define SoftFail MCDisassembler::SoftFail
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]243
244static MCDisassembler *createAArch64Disassembler(const Target &T,
245 const MCSubtargetInfo &STI,
246 MCContext &Ctx) {
247 return new AArch64Disassembler(STI, Ctx);
248}
249
250DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000[diff] [blame]251 ArrayRef<uint8_t> Bytes,
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]252 uint64_t Address,
253 raw_ostream &OS,
254 raw_ostream &CS) const {
255 CommentStream = &CS;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]256
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]257 Size = 0;
258 // We want to read exactly 4 bytes of data.
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000[diff] [blame]259 if (Bytes.size() < 4)
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]260 return Fail;
261 Size = 4;
262
263 // Encoded as a small-endian 32-bit word in the stream.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]264 uint32_t Insn =
265 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]266
267 // Calling the auto-generated decoder function.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]268 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]269}
270
Daniel Sanders50f17232015-09-15 16:17:27 +0000[diff] [blame]271static MCSymbolizer *
272createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
273 LLVMSymbolLookupCallback SymbolLookUp,
274 void *DisInfo, MCContext *Ctx,
275 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]276 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
277 SymbolLookUp, DisInfo);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]278}
279
280extern "C" void LLVMInitializeAArch64Disassembler() {
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]281 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]282 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]283 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]284 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]285 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]286 createAArch64ExternalSymbolizer);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]287 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]288 createAArch64ExternalSymbolizer);
289
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]290 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]291 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]292 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]293 createAArch64ExternalSymbolizer);
294}
295
296static const unsigned FPR128DecoderTable[] = {
297 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
298 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
299 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
300 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
301 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
302 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
303 AArch64::Q30, AArch64::Q31
304};
305
306static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
307 uint64_t Addr,
308 const void *Decoder) {
309 if (RegNo > 31)
310 return Fail;
311
312 unsigned Register = FPR128DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]313 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]314 return Success;
315}
316
317static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
318 uint64_t Addr,
319 const void *Decoder) {
320 if (RegNo > 15)
321 return Fail;
322 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
323}
324
325static const unsigned FPR64DecoderTable[] = {
326 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
327 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
328 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
329 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
330 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24,
331 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29,
332 AArch64::D30, AArch64::D31
333};
334
335static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
336 uint64_t Addr,
337 const void *Decoder) {
338 if (RegNo > 31)
339 return Fail;
340
341 unsigned Register = FPR64DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]342 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]343 return Success;
344}
345
346static const unsigned FPR32DecoderTable[] = {
347 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
348 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9,
349 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14,
350 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19,
351 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24,
352 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29,
353 AArch64::S30, AArch64::S31
354};
355
356static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
357 uint64_t Addr,
358 const void *Decoder) {
359 if (RegNo > 31)
360 return Fail;
361
362 unsigned Register = FPR32DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]363 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]364 return Success;
365}
366
367static const unsigned FPR16DecoderTable[] = {
368 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4,
369 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9,
370 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14,
371 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19,
372 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24,
373 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29,
374 AArch64::H30, AArch64::H31
375};
376
377static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
378 uint64_t Addr,
379 const void *Decoder) {
380 if (RegNo > 31)
381 return Fail;
382
383 unsigned Register = FPR16DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]384 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]385 return Success;
386}
387
388static const unsigned FPR8DecoderTable[] = {
389 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4,
390 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9,
391 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14,
392 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,
393 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24,
394 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29,
395 AArch64::B30, AArch64::B31
396};
397
398static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
399 uint64_t Addr,
400 const void *Decoder) {
401 if (RegNo > 31)
402 return Fail;
403
404 unsigned Register = FPR8DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]405 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]406 return Success;
407}
408
409static const unsigned GPR64DecoderTable[] = {
410 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
411 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9,
412 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14,
413 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19,
414 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24,
415 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
416 AArch64::LR, AArch64::XZR
417};
418
Sander de Smalen367694b2018-04-20 08:54:49 +0000[diff] [blame]419static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
420 uint64_t Addr,
421 const void *Decoder) {
422 if (RegNo > 30)
423 return Fail;
424
425 unsigned Register = GPR64DecoderTable[RegNo];
426 Inst.addOperand(MCOperand::createReg(Register));
427 return Success;
428}
429
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]430static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
431 uint64_t Addr,
432 const void *Decoder) {
433 if (RegNo > 31)
434 return Fail;
435
436 unsigned Register = GPR64DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]437 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]438 return Success;
439}
440
441static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
442 uint64_t Addr,
443 const void *Decoder) {
444 if (RegNo > 31)
445 return Fail;
446 unsigned Register = GPR64DecoderTable[RegNo];
447 if (Register == AArch64::XZR)
448 Register = AArch64::SP;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]449 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]450 return Success;
451}
452
453static const unsigned GPR32DecoderTable[] = {
454 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
455 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9,
456 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14,
457 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19,
458 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24,
459 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29,
460 AArch64::W30, AArch64::WZR
461};
462
463static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
464 uint64_t Addr,
465 const void *Decoder) {
466 if (RegNo > 31)
467 return Fail;
468
469 unsigned Register = GPR32DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]470 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]471 return Success;
472}
473
474static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
475 uint64_t Addr,
476 const void *Decoder) {
477 if (RegNo > 31)
478 return Fail;
479
480 unsigned Register = GPR32DecoderTable[RegNo];
481 if (Register == AArch64::WZR)
482 Register = AArch64::WSP;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]483 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]484 return Success;
485}
Florian Hahn91f11e52017-11-07 16:45:48 +0000[diff] [blame]486static const unsigned ZPRDecoderTable[] = {
487 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3,
488 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7,
489 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11,
490 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15,
491 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19,
492 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23,
493 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27,
494 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31
495};
496
497static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
498 uint64_t Address,
499 const void* Decoder) {
500 if (RegNo > 31)
501 return Fail;
502
503 unsigned Register = ZPRDecoderTable[RegNo];
504 Inst.addOperand(MCOperand::createReg(Register));
505 return Success;
506}
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]507
Sander de Smalen8cd1f532018-07-03 15:31:04 +0000[diff] [blame]508static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
509 uint64_t Address,
510 const void *Decoder) {
511 if (RegNo > 15)
512 return Fail;
513 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
514}
515
516static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
517 uint64_t Address,
518 const void *Decoder) {
519 if (RegNo > 7)
520 return Fail;
521 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
522}
523
Sander de Smalenf836af82018-04-16 07:09:29 +0000[diff] [blame]524static const unsigned ZZDecoderTable[] = {
525 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4,
526 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8,
527 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12,
528 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16,
529 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20,
530 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24,
531 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28,
532 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0
533};
534
535static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
536 uint64_t Address,
537 const void* Decoder) {
538 if (RegNo > 31)
539 return Fail;
540 unsigned Register = ZZDecoderTable[RegNo];
541 Inst.addOperand(MCOperand::createReg(Register));
542 return Success;
543}
544
Sander de Smalend239eb32018-04-16 10:10:48 +0000[diff] [blame]545static const unsigned ZZZDecoderTable[] = {
546 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4,
547 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7,
548 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10,
549 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13,
550 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16,
551 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19,
552 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22,
553 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25,
554 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28,
555 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31,
556 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1
557};
558
559static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
560 uint64_t Address,
561 const void* Decoder) {
562 if (RegNo > 31)
563 return Fail;
564 unsigned Register = ZZZDecoderTable[RegNo];
565 Inst.addOperand(MCOperand::createReg(Register));
566 return Success;
567}
568
Sander de Smalen7a210db2018-04-16 10:46:18 +0000[diff] [blame]569static const unsigned ZZZZDecoderTable[] = {
570 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5,
571 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8,
572 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11,
573 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14,
574 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17,
575 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20,
576 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23,
577 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26,
578 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29,
579 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0,
580 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2
581};
582
583static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
584 uint64_t Address,
585 const void* Decoder) {
586 if (RegNo > 31)
587 return Fail;
588 unsigned Register = ZZZZDecoderTable[RegNo];
589 Inst.addOperand(MCOperand::createReg(Register));
590 return Success;
591}
592
Sander de Smalencd6be962017-12-20 11:02:42 +0000[diff] [blame]593static const unsigned PPRDecoderTable[] = {
594 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3,
595 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7,
596 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11,
597 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15
598};
599
600static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
601 uint64_t Addr, const void *Decoder) {
602 if (RegNo > 15)
603 return Fail;
604
605 unsigned Register = PPRDecoderTable[RegNo];
606 Inst.addOperand(MCOperand::createReg(Register));
607 return Success;
608}
609
Sander de Smalendc5e0812018-01-03 10:15:46 +0000[diff] [blame]610static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
611 uint64_t Addr,
612 const void* Decoder) {
613 if (RegNo > 7)
614 return Fail;
615
616 // Just reuse the PPR decode table
617 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
618}
619
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]620static const unsigned VectorDecoderTable[] = {
621 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
622 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
623 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
624 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
625 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
626 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
627 AArch64::Q30, AArch64::Q31
628};
629
630static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
631 uint64_t Addr,
632 const void *Decoder) {
633 if (RegNo > 31)
634 return Fail;
635
636 unsigned Register = VectorDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]637 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]638 return Success;
639}
640
641static const unsigned QQDecoderTable[] = {
642 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4,
643 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8,
644 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12,
645 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
646 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20,
647 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24,
648 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28,
649 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0
650};
651
652static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
653 uint64_t Addr, const void *Decoder) {
654 if (RegNo > 31)
655 return Fail;
656 unsigned Register = QQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]657 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]658 return Success;
659}
660
661static const unsigned QQQDecoderTable[] = {
662 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4,
663 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7,
664 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10,
665 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13,
666 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
667 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19,
668 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22,
669 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25,
670 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28,
671 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31,
672 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1
673};
674
675static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
676 uint64_t Addr, const void *Decoder) {
677 if (RegNo > 31)
678 return Fail;
679 unsigned Register = QQQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]680 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]681 return Success;
682}
683
684static const unsigned QQQQDecoderTable[] = {
685 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5,
686 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8,
687 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11,
688 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14,
689 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
690 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20,
691 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23,
692 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26,
693 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29,
694 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0,
695 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2
696};
697
698static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
699 uint64_t Addr,
700 const void *Decoder) {
701 if (RegNo > 31)
702 return Fail;
703 unsigned Register = QQQQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]704 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]705 return Success;
706}
707
708static const unsigned DDDecoderTable[] = {
709 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4,
710 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8,
711 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12,
712 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16,
713 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20,
714 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24,
715 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28,
716 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0
717};
718
719static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
720 uint64_t Addr, const void *Decoder) {
721 if (RegNo > 31)
722 return Fail;
723 unsigned Register = DDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]724 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]725 return Success;
726}
727
728static const unsigned DDDDecoderTable[] = {
729 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4,
730 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7,
731 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10,
732 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13,
733 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16,
734 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19,
735 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22,
736 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25,
737 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28,
738 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31,
739 AArch64::D30_D31_D0, AArch64::D31_D0_D1
740};
741
742static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
743 uint64_t Addr, const void *Decoder) {
744 if (RegNo > 31)
745 return Fail;
746 unsigned Register = DDDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]747 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]748 return Success;
749}
750
751static const unsigned DDDDDecoderTable[] = {
752 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5,
753 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8,
754 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11,
755 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14,
756 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17,
757 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20,
758 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23,
759 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26,
760 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29,
761 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0,
762 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2
763};
764
765static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
766 uint64_t Addr,
767 const void *Decoder) {
768 if (RegNo > 31)
769 return Fail;
770 unsigned Register = DDDDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]771 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]772 return Success;
773}
774
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]775static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]776 uint64_t Addr,
777 const void *Decoder) {
778 // scale{5} is asserted as 1 in tblgen.
Tom Coxon2c13e712014-09-30 16:23:16 +0000[diff] [blame]779 Imm |= 0x20;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]780 Inst.addOperand(MCOperand::createImm(64 - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]781 return Success;
782}
783
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]784static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]785 uint64_t Addr,
786 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]787 Inst.addOperand(MCOperand::createImm(64 - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]788 return Success;
789}
790
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]791static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]792 uint64_t Addr, const void *Decoder) {
793 int64_t ImmVal = Imm;
794 const AArch64Disassembler *Dis =
795 static_cast<const AArch64Disassembler *>(Decoder);
796
797 // Sign-extend 19-bit immediate.
798 if (ImmVal & (1 << (19 - 1)))
799 ImmVal |= ~((1LL << 19) - 1);
800
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]801 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]802 Inst.getOpcode() != AArch64::LDRXl, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]803 Inst.addOperand(MCOperand::createImm(ImmVal));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]804 return Success;
805}
806
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]807static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]808 uint64_t Address, const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]809 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
810 Inst.addOperand(MCOperand::createImm(Imm & 1));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]811 return Success;
812}
813
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]814static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]815 uint64_t Address,
816 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]817 Inst.addOperand(MCOperand::createImm(Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]818
Tom Coxone493f172014-10-01 10:13:59 +0000[diff] [blame]819 // Every system register in the encoding space is valid with the syntax
820 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
821 return Success;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]822}
823
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]824static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]825 uint64_t Address,
826 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]827 Inst.addOperand(MCOperand::createImm(Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]828
Tom Coxone493f172014-10-01 10:13:59 +0000[diff] [blame]829 return Success;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]830}
831
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]832static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]833 uint64_t Address,
834 const void *Decoder) {
835 // This decoder exists to add the dummy Lane operand to the MCInst, which must
836 // be 1 in assembly but has no other real manifestation.
837 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
838 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
839 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
840
841 if (IsToVec) {
842 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
843 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
844 } else {
845 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
846 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
847 }
848
849 // Add the lane
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]850 Inst.addOperand(MCOperand::createImm(1));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]851
852 return Success;
853}
854
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]855static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]856 unsigned Add) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]857 Inst.addOperand(MCOperand::createImm(Add - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]858 return Success;
859}
860
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]861static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]862 unsigned Add) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]863 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]864 return Success;
865}
866
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]867static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]868 uint64_t Addr, const void *Decoder) {
869 return DecodeVecShiftRImm(Inst, Imm, 64);
870}
871
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]872static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]873 uint64_t Addr,
874 const void *Decoder) {
875 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
876}
877
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]878static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]879 uint64_t Addr, const void *Decoder) {
880 return DecodeVecShiftRImm(Inst, Imm, 32);
881}
882
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]883static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]884 uint64_t Addr,
885 const void *Decoder) {
886 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
887}
888
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]889static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]890 uint64_t Addr, const void *Decoder) {
891 return DecodeVecShiftRImm(Inst, Imm, 16);
892}
893
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]894static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]895 uint64_t Addr,
896 const void *Decoder) {
897 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
898}
899
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]900static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]901 uint64_t Addr, const void *Decoder) {
902 return DecodeVecShiftRImm(Inst, Imm, 8);
903}
904
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]905static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]906 uint64_t Addr, const void *Decoder) {
907 return DecodeVecShiftLImm(Inst, Imm, 64);
908}
909
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]910static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]911 uint64_t Addr, const void *Decoder) {
912 return DecodeVecShiftLImm(Inst, Imm, 32);
913}
914
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]915static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]916 uint64_t Addr, const void *Decoder) {
917 return DecodeVecShiftLImm(Inst, Imm, 16);
918}
919
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]920static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]921 uint64_t Addr, const void *Decoder) {
922 return DecodeVecShiftLImm(Inst, Imm, 8);
923}
924
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]925static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
926 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]927 const void *Decoder) {
928 unsigned Rd = fieldFromInstruction(insn, 0, 5);
929 unsigned Rn = fieldFromInstruction(insn, 5, 5);
930 unsigned Rm = fieldFromInstruction(insn, 16, 5);
931 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
932 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
933 unsigned shift = (shiftHi << 6) | shiftLo;
934 switch (Inst.getOpcode()) {
935 default:
936 return Fail;
937 case AArch64::ADDWrs:
938 case AArch64::ADDSWrs:
939 case AArch64::SUBWrs:
940 case AArch64::SUBSWrs:
941 // if shift == '11' then ReservedValue()
942 if (shiftHi == 0x3)
943 return Fail;
Simon Pilgrimcb07d672017-07-07 16:40:06 +0000[diff] [blame]944 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]945 case AArch64::ANDWrs:
946 case AArch64::ANDSWrs:
947 case AArch64::BICWrs:
948 case AArch64::BICSWrs:
949 case AArch64::ORRWrs:
950 case AArch64::ORNWrs:
951 case AArch64::EORWrs:
952 case AArch64::EONWrs: {
953 // if sf == '0' and imm6<5> == '1' then ReservedValue()
954 if (shiftLo >> 5 == 1)
955 return Fail;
956 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
957 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
958 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
959 break;
960 }
961 case AArch64::ADDXrs:
962 case AArch64::ADDSXrs:
963 case AArch64::SUBXrs:
964 case AArch64::SUBSXrs:
965 // if shift == '11' then ReservedValue()
966 if (shiftHi == 0x3)
967 return Fail;
Simon Pilgrimcb07d672017-07-07 16:40:06 +0000[diff] [blame]968 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]969 case AArch64::ANDXrs:
970 case AArch64::ANDSXrs:
971 case AArch64::BICXrs:
972 case AArch64::BICSXrs:
973 case AArch64::ORRXrs:
974 case AArch64::ORNXrs:
975 case AArch64::EORXrs:
976 case AArch64::EONXrs:
977 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
978 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
979 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
980 break;
981 }
982
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]983 Inst.addOperand(MCOperand::createImm(shift));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]984 return Success;
985}
986
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]987static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]988 uint64_t Addr,
989 const void *Decoder) {
990 unsigned Rd = fieldFromInstruction(insn, 0, 5);
991 unsigned imm = fieldFromInstruction(insn, 5, 16);
992 unsigned shift = fieldFromInstruction(insn, 21, 2);
993 shift <<= 4;
994 switch (Inst.getOpcode()) {
995 default:
996 return Fail;
997 case AArch64::MOVZWi:
998 case AArch64::MOVNWi:
999 case AArch64::MOVKWi:
1000 if (shift & (1U << 5))
1001 return Fail;
1002 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1003 break;
1004 case AArch64::MOVZXi:
1005 case AArch64::MOVNXi:
1006 case AArch64::MOVKXi:
1007 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1008 break;
1009 }
1010
1011 if (Inst.getOpcode() == AArch64::MOVKWi ||
1012 Inst.getOpcode() == AArch64::MOVKXi)
1013 Inst.addOperand(Inst.getOperand(0));
1014
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1015 Inst.addOperand(MCOperand::createImm(imm));
1016 Inst.addOperand(MCOperand::createImm(shift));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1017 return Success;
1018}
1019
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1020static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
1021 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1022 const void *Decoder) {
1023 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1024 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1025 unsigned offset = fieldFromInstruction(insn, 10, 12);
1026 const AArch64Disassembler *Dis =
1027 static_cast<const AArch64Disassembler *>(Decoder);
1028
1029 switch (Inst.getOpcode()) {
1030 default:
1031 return Fail;
1032 case AArch64::PRFMui:
1033 // Rt is an immediate in prefetch.
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1034 Inst.addOperand(MCOperand::createImm(Rt));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1035 break;
1036 case AArch64::STRBBui:
1037 case AArch64::LDRBBui:
1038 case AArch64::LDRSBWui:
1039 case AArch64::STRHHui:
1040 case AArch64::LDRHHui:
1041 case AArch64::LDRSHWui:
1042 case AArch64::STRWui:
1043 case AArch64::LDRWui:
1044 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1045 break;
1046 case AArch64::LDRSBXui:
1047 case AArch64::LDRSHXui:
1048 case AArch64::LDRSWui:
1049 case AArch64::STRXui:
1050 case AArch64::LDRXui:
1051 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1052 break;
1053 case AArch64::LDRQui:
1054 case AArch64::STRQui:
1055 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1056 break;
1057 case AArch64::LDRDui:
1058 case AArch64::STRDui:
1059 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1060 break;
1061 case AArch64::LDRSui:
1062 case AArch64::STRSui:
1063 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1064 break;
1065 case AArch64::LDRHui:
1066 case AArch64::STRHui:
1067 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1068 break;
1069 case AArch64::LDRBui:
1070 case AArch64::STRBui:
1071 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1072 break;
1073 }
1074
1075 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1076 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1077 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1078 return Success;
1079}
1080
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1081static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
1082 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1083 const void *Decoder) {
1084 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1085 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1086 int64_t offset = fieldFromInstruction(insn, 12, 9);
1087
1088 // offset is a 9-bit signed immediate, so sign extend it to
1089 // fill the unsigned.
1090 if (offset & (1 << (9 - 1)))
1091 offset |= ~((1LL << 9) - 1);
1092
1093 // First operand is always the writeback to the address register, if needed.
1094 switch (Inst.getOpcode()) {
1095 default:
1096 break;
1097 case AArch64::LDRSBWpre:
1098 case AArch64::LDRSHWpre:
1099 case AArch64::STRBBpre:
1100 case AArch64::LDRBBpre:
1101 case AArch64::STRHHpre:
1102 case AArch64::LDRHHpre:
1103 case AArch64::STRWpre:
1104 case AArch64::LDRWpre:
1105 case AArch64::LDRSBWpost:
1106 case AArch64::LDRSHWpost:
1107 case AArch64::STRBBpost:
1108 case AArch64::LDRBBpost:
1109 case AArch64::STRHHpost:
1110 case AArch64::LDRHHpost:
1111 case AArch64::STRWpost:
1112 case AArch64::LDRWpost:
1113 case AArch64::LDRSBXpre:
1114 case AArch64::LDRSHXpre:
1115 case AArch64::STRXpre:
1116 case AArch64::LDRSWpre:
1117 case AArch64::LDRXpre:
1118 case AArch64::LDRSBXpost:
1119 case AArch64::LDRSHXpost:
1120 case AArch64::STRXpost:
1121 case AArch64::LDRSWpost:
1122 case AArch64::LDRXpost:
1123 case AArch64::LDRQpre:
1124 case AArch64::STRQpre:
1125 case AArch64::LDRQpost:
1126 case AArch64::STRQpost:
1127 case AArch64::LDRDpre:
1128 case AArch64::STRDpre:
1129 case AArch64::LDRDpost:
1130 case AArch64::STRDpost:
1131 case AArch64::LDRSpre:
1132 case AArch64::STRSpre:
1133 case AArch64::LDRSpost:
1134 case AArch64::STRSpost:
1135 case AArch64::LDRHpre:
1136 case AArch64::STRHpre:
1137 case AArch64::LDRHpost:
1138 case AArch64::STRHpost:
1139 case AArch64::LDRBpre:
1140 case AArch64::STRBpre:
1141 case AArch64::LDRBpost:
1142 case AArch64::STRBpost:
1143 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1144 break;
1145 }
1146
1147 switch (Inst.getOpcode()) {
1148 default:
1149 return Fail;
1150 case AArch64::PRFUMi:
1151 // Rt is an immediate in prefetch.
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1152 Inst.addOperand(MCOperand::createImm(Rt));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1153 break;
1154 case AArch64::STURBBi:
1155 case AArch64::LDURBBi:
1156 case AArch64::LDURSBWi:
1157 case AArch64::STURHHi:
1158 case AArch64::LDURHHi:
1159 case AArch64::LDURSHWi:
1160 case AArch64::STURWi:
1161 case AArch64::LDURWi:
1162 case AArch64::LDTRSBWi:
1163 case AArch64::LDTRSHWi:
1164 case AArch64::STTRWi:
1165 case AArch64::LDTRWi:
1166 case AArch64::STTRHi:
1167 case AArch64::LDTRHi:
1168 case AArch64::LDTRBi:
1169 case AArch64::STTRBi:
1170 case AArch64::LDRSBWpre:
1171 case AArch64::LDRSHWpre:
1172 case AArch64::STRBBpre:
1173 case AArch64::LDRBBpre:
1174 case AArch64::STRHHpre:
1175 case AArch64::LDRHHpre:
1176 case AArch64::STRWpre:
1177 case AArch64::LDRWpre:
1178 case AArch64::LDRSBWpost:
1179 case AArch64::LDRSHWpost:
1180 case AArch64::STRBBpost:
1181 case AArch64::LDRBBpost:
1182 case AArch64::STRHHpost:
1183 case AArch64::LDRHHpost:
1184 case AArch64::STRWpost:
1185 case AArch64::LDRWpost:
1186 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1187 break;
1188 case AArch64::LDURSBXi:
1189 case AArch64::LDURSHXi:
1190 case AArch64::LDURSWi:
1191 case AArch64::STURXi:
1192 case AArch64::LDURXi:
1193 case AArch64::LDTRSBXi:
1194 case AArch64::LDTRSHXi:
1195 case AArch64::LDTRSWi:
1196 case AArch64::STTRXi:
1197 case AArch64::LDTRXi:
1198 case AArch64::LDRSBXpre:
1199 case AArch64::LDRSHXpre:
1200 case AArch64::STRXpre:
1201 case AArch64::LDRSWpre:
1202 case AArch64::LDRXpre:
1203 case AArch64::LDRSBXpost:
1204 case AArch64::LDRSHXpost:
1205 case AArch64::STRXpost:
1206 case AArch64::LDRSWpost:
1207 case AArch64::LDRXpost:
1208 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1209 break;
1210 case AArch64::LDURQi:
1211 case AArch64::STURQi:
1212 case AArch64::LDRQpre:
1213 case AArch64::STRQpre:
1214 case AArch64::LDRQpost:
1215 case AArch64::STRQpost:
1216 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1217 break;
1218 case AArch64::LDURDi:
1219 case AArch64::STURDi:
1220 case AArch64::LDRDpre:
1221 case AArch64::STRDpre:
1222 case AArch64::LDRDpost:
1223 case AArch64::STRDpost:
1224 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1225 break;
1226 case AArch64::LDURSi:
1227 case AArch64::STURSi:
1228 case AArch64::LDRSpre:
1229 case AArch64::STRSpre:
1230 case AArch64::LDRSpost:
1231 case AArch64::STRSpost:
1232 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1233 break;
1234 case AArch64::LDURHi:
1235 case AArch64::STURHi:
1236 case AArch64::LDRHpre:
1237 case AArch64::STRHpre:
1238 case AArch64::LDRHpost:
1239 case AArch64::STRHpost:
1240 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1241 break;
1242 case AArch64::LDURBi:
1243 case AArch64::STURBi:
1244 case AArch64::LDRBpre:
1245 case AArch64::STRBpre:
1246 case AArch64::LDRBpost:
1247 case AArch64::STRBpost:
1248 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1249 break;
1250 }
1251
1252 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1253 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1254
1255 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1256 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1257 bool IsFP = fieldFromInstruction(insn, 26, 1);
1258
1259 // Cannot write back to a transfer register (but xzr != sp).
1260 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1261 return SoftFail;
1262
1263 return Success;
1264}
1265
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1266static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
1267 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1268 const void *Decoder) {
1269 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1270 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1271 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1272 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1273
1274 unsigned Opcode = Inst.getOpcode();
1275 switch (Opcode) {
1276 default:
1277 return Fail;
1278 case AArch64::STLXRW:
1279 case AArch64::STLXRB:
1280 case AArch64::STLXRH:
1281 case AArch64::STXRW:
1282 case AArch64::STXRB:
1283 case AArch64::STXRH:
1284 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1285 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1286 case AArch64::LDARW:
1287 case AArch64::LDARB:
1288 case AArch64::LDARH:
1289 case AArch64::LDAXRW:
1290 case AArch64::LDAXRB:
1291 case AArch64::LDAXRH:
1292 case AArch64::LDXRW:
1293 case AArch64::LDXRB:
1294 case AArch64::LDXRH:
1295 case AArch64::STLRW:
1296 case AArch64::STLRB:
1297 case AArch64::STLRH:
Vladimir Sukharevd49cb8f2015-04-16 15:30:43 +0000[diff] [blame]1298 case AArch64::STLLRW:
1299 case AArch64::STLLRB:
1300 case AArch64::STLLRH:
1301 case AArch64::LDLARW:
1302 case AArch64::LDLARB:
1303 case AArch64::LDLARH:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1304 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1305 break;
1306 case AArch64::STLXRX:
1307 case AArch64::STXRX:
1308 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1309 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1310 case AArch64::LDARX:
1311 case AArch64::LDAXRX:
1312 case AArch64::LDXRX:
1313 case AArch64::STLRX:
Vladimir Sukharevd49cb8f2015-04-16 15:30:43 +0000[diff] [blame]1314 case AArch64::LDLARX:
1315 case AArch64::STLLRX:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1316 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1317 break;
1318 case AArch64::STLXPW:
1319 case AArch64::STXPW:
1320 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1321 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1322 case AArch64::LDAXPW:
1323 case AArch64::LDXPW:
1324 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1325 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1326 break;
1327 case AArch64::STLXPX:
1328 case AArch64::STXPX:
1329 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1330 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1331 case AArch64::LDAXPX:
1332 case AArch64::LDXPX:
1333 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1334 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1335 break;
1336 }
1337
1338 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1339
1340 // You shouldn't load to the same register twice in an instruction...
1341 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1342 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1343 Rt == Rt2)
1344 return SoftFail;
1345
1346 return Success;
1347}
1348
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1349static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1350 uint64_t Addr,
1351 const void *Decoder) {
1352 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1353 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1354 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1355 int64_t offset = fieldFromInstruction(insn, 15, 7);
1356 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1357
1358 // offset is a 7-bit signed immediate, so sign extend it to
1359 // fill the unsigned.
1360 if (offset & (1 << (7 - 1)))
1361 offset |= ~((1LL << 7) - 1);
1362
1363 unsigned Opcode = Inst.getOpcode();
1364 bool NeedsDisjointWritebackTransfer = false;
1365
1366 // First operand is always writeback of base register.
1367 switch (Opcode) {
1368 default:
1369 break;
1370 case AArch64::LDPXpost:
1371 case AArch64::STPXpost:
1372 case AArch64::LDPSWpost:
1373 case AArch64::LDPXpre:
1374 case AArch64::STPXpre:
1375 case AArch64::LDPSWpre:
1376 case AArch64::LDPWpost:
1377 case AArch64::STPWpost:
1378 case AArch64::LDPWpre:
1379 case AArch64::STPWpre:
1380 case AArch64::LDPQpost:
1381 case AArch64::STPQpost:
1382 case AArch64::LDPQpre:
1383 case AArch64::STPQpre:
1384 case AArch64::LDPDpost:
1385 case AArch64::STPDpost:
1386 case AArch64::LDPDpre:
1387 case AArch64::STPDpre:
1388 case AArch64::LDPSpost:
1389 case AArch64::STPSpost:
1390 case AArch64::LDPSpre:
1391 case AArch64::STPSpre:
1392 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1393 break;
1394 }
1395
1396 switch (Opcode) {
1397 default:
1398 return Fail;
1399 case AArch64::LDPXpost:
1400 case AArch64::STPXpost:
1401 case AArch64::LDPSWpost:
1402 case AArch64::LDPXpre:
1403 case AArch64::STPXpre:
1404 case AArch64::LDPSWpre:
1405 NeedsDisjointWritebackTransfer = true;
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1406 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1407 case AArch64::LDNPXi:
1408 case AArch64::STNPXi:
1409 case AArch64::LDPXi:
1410 case AArch64::STPXi:
1411 case AArch64::LDPSWi:
1412 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1413 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1414 break;
1415 case AArch64::LDPWpost:
1416 case AArch64::STPWpost:
1417 case AArch64::LDPWpre:
1418 case AArch64::STPWpre:
1419 NeedsDisjointWritebackTransfer = true;
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1420 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1421 case AArch64::LDNPWi:
1422 case AArch64::STNPWi:
1423 case AArch64::LDPWi:
1424 case AArch64::STPWi:
1425 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1426 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1427 break;
1428 case AArch64::LDNPQi:
1429 case AArch64::STNPQi:
1430 case AArch64::LDPQpost:
1431 case AArch64::STPQpost:
1432 case AArch64::LDPQi:
1433 case AArch64::STPQi:
1434 case AArch64::LDPQpre:
1435 case AArch64::STPQpre:
1436 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1437 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1438 break;
1439 case AArch64::LDNPDi:
1440 case AArch64::STNPDi:
1441 case AArch64::LDPDpost:
1442 case AArch64::STPDpost:
1443 case AArch64::LDPDi:
1444 case AArch64::STPDi:
1445 case AArch64::LDPDpre:
1446 case AArch64::STPDpre:
1447 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1448 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1449 break;
1450 case AArch64::LDNPSi:
1451 case AArch64::STNPSi:
1452 case AArch64::LDPSpost:
1453 case AArch64::STPSpost:
1454 case AArch64::LDPSi:
1455 case AArch64::STPSi:
1456 case AArch64::LDPSpre:
1457 case AArch64::STPSpre:
1458 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1459 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1460 break;
1461 }
1462
1463 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1464 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1465
1466 // You shouldn't load to the same register twice in an instruction...
1467 if (IsLoad && Rt == Rt2)
1468 return SoftFail;
1469
1470 // ... or do any operation that writes-back to a transfer register. But note
1471 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1472 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1473 return SoftFail;
1474
1475 return Success;
1476}
1477
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1478static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1479 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1480 const void *Decoder) {
1481 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1482 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1483 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1484 unsigned extend = fieldFromInstruction(insn, 10, 6);
1485
1486 unsigned shift = extend & 0x7;
1487 if (shift > 4)
1488 return Fail;
1489
1490 switch (Inst.getOpcode()) {
1491 default:
1492 return Fail;
1493 case AArch64::ADDWrx:
1494 case AArch64::SUBWrx:
1495 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1496 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1497 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1498 break;
1499 case AArch64::ADDSWrx:
1500 case AArch64::SUBSWrx:
1501 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1502 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1503 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1504 break;
1505 case AArch64::ADDXrx:
1506 case AArch64::SUBXrx:
1507 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1508 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1509 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1510 break;
1511 case AArch64::ADDSXrx:
1512 case AArch64::SUBSXrx:
1513 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1514 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1515 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1516 break;
1517 case AArch64::ADDXrx64:
1518 case AArch64::SUBXrx64:
1519 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1520 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1521 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1522 break;
1523 case AArch64::SUBSXrx64:
1524 case AArch64::ADDSXrx64:
1525 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1526 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1527 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1528 break;
1529 }
1530
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1531 Inst.addOperand(MCOperand::createImm(extend));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1532 return Success;
1533}
1534
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1535static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1536 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1537 const void *Decoder) {
1538 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1539 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1540 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1541 unsigned imm;
1542
1543 if (Datasize) {
1544 if (Inst.getOpcode() == AArch64::ANDSXri)
1545 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1546 else
1547 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1548 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1549 imm = fieldFromInstruction(insn, 10, 13);
1550 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1551 return Fail;
1552 } else {
1553 if (Inst.getOpcode() == AArch64::ANDSWri)
1554 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1555 else
1556 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1557 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1558 imm = fieldFromInstruction(insn, 10, 12);
1559 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1560 return Fail;
1561 }
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1562 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1563 return Success;
1564}
1565
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1566static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1567 uint64_t Addr,
1568 const void *Decoder) {
1569 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1570 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1571 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1572 imm |= fieldFromInstruction(insn, 5, 5);
1573
1574 if (Inst.getOpcode() == AArch64::MOVID)
1575 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1576 else
1577 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1578
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1579 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1580
1581 switch (Inst.getOpcode()) {
1582 default:
1583 break;
1584 case AArch64::MOVIv4i16:
1585 case AArch64::MOVIv8i16:
1586 case AArch64::MVNIv4i16:
1587 case AArch64::MVNIv8i16:
1588 case AArch64::MOVIv2i32:
1589 case AArch64::MOVIv4i32:
1590 case AArch64::MVNIv2i32:
1591 case AArch64::MVNIv4i32:
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1592 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1593 break;
1594 case AArch64::MOVIv2s_msl:
1595 case AArch64::MOVIv4s_msl:
1596 case AArch64::MVNIv2s_msl:
1597 case AArch64::MVNIv4s_msl:
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1598 Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1599 break;
1600 }
1601
1602 return Success;
1603}
1604
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1605static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1606 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1607 const void *Decoder) {
1608 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1609 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1610 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1611 imm |= fieldFromInstruction(insn, 5, 5);
1612
1613 // Tied operands added twice.
1614 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1615 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1616
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1617 Inst.addOperand(MCOperand::createImm(imm));
1618 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1619
1620 return Success;
1621}
1622
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1623static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1624 uint64_t Addr, const void *Decoder) {
1625 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1626 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1627 imm |= fieldFromInstruction(insn, 29, 2);
1628 const AArch64Disassembler *Dis =
1629 static_cast<const AArch64Disassembler *>(Decoder);
1630
1631 // Sign-extend the 21-bit immediate.
1632 if (imm & (1 << (21 - 1)))
1633 imm |= ~((1LL << 21) - 1);
1634
1635 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1636 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1637 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1638
1639 return Success;
1640}
1641
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1642static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1643 uint64_t Addr, const void *Decoder) {
1644 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1645 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1646 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1647 unsigned S = fieldFromInstruction(insn, 29, 1);
1648 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1649
1650 unsigned ShifterVal = (Imm >> 12) & 3;
1651 unsigned ImmVal = Imm & 0xFFF;
1652 const AArch64Disassembler *Dis =
1653 static_cast<const AArch64Disassembler *>(Decoder);
1654
1655 if (ShifterVal != 0 && ShifterVal != 1)
1656 return Fail;
1657
1658 if (Datasize) {
1659 if (Rd == 31 && !S)
1660 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1661 else
1662 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1663 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1664 } else {
1665 if (Rd == 31 && !S)
1666 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1667 else
1668 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1669 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1670 }
1671
1672 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1673 Inst.addOperand(MCOperand::createImm(ImmVal));
1674 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1675 return Success;
1676}
1677
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1678static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1679 uint64_t Addr,
1680 const void *Decoder) {
1681 int64_t imm = fieldFromInstruction(insn, 0, 26);
1682 const AArch64Disassembler *Dis =
1683 static_cast<const AArch64Disassembler *>(Decoder);
1684
1685 // Sign-extend the 26-bit immediate.
1686 if (imm & (1 << (26 - 1)))
1687 imm |= ~((1LL << 26) - 1);
1688
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]1689 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1690 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1691
1692 return Success;
1693}
1694
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1695static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
1696 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1697 const void *Decoder) {
1698 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1699 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1700 uint64_t crm = fieldFromInstruction(insn, 8, 4);
1701
1702 uint64_t pstate_field = (op1 << 3) | op2;
1703
Oliver Stannard911ea202015-11-26 15:32:30 +0000[diff] [blame]1704 if ((pstate_field == AArch64PState::PAN ||
1705 pstate_field == AArch64PState::UAO) && crm > 1)
Alexandros Lamprineas1bab1912015-10-05 13:42:31 +0000[diff] [blame]1706 return Fail;
1707
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1708 Inst.addOperand(MCOperand::createImm(pstate_field));
1709 Inst.addOperand(MCOperand::createImm(crm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1710
Tim Northovere6ae6762016-07-05 21:23:04 +0000[diff] [blame]1711 const AArch64Disassembler *Dis =
Vladimir Sukhareva98f6892015-04-16 12:15:27 +0000[diff] [blame]1712 static_cast<const AArch64Disassembler *>(Decoder);
Tim Northovere6ae6762016-07-05 21:23:04 +0000[diff] [blame]1713 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field);
1714 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits()))
1715 return Success;
1716 return Fail;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1717}
1718
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1719static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1720 uint64_t Addr, const void *Decoder) {
1721 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1722 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1723 bit |= fieldFromInstruction(insn, 19, 5);
1724 int64_t dst = fieldFromInstruction(insn, 5, 14);
1725 const AArch64Disassembler *Dis =
1726 static_cast<const AArch64Disassembler *>(Decoder);
1727
1728 // Sign-extend 14-bit immediate.
1729 if (dst & (1 << (14 - 1)))
1730 dst |= ~((1LL << 14) - 1);
1731
1732 if (fieldFromInstruction(insn, 31, 1) == 0)
1733 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1734 else
1735 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1736 Inst.addOperand(MCOperand::createImm(bit));
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]1737 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1738 Inst.addOperand(MCOperand::createImm(dst));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1739
1740 return Success;
1741}
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1742
1743static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst,
1744 unsigned RegClassID,
1745 unsigned RegNo,
1746 uint64_t Addr,
1747 const void *Decoder) {
1748 // Register number must be even (see CASP instruction)
1749 if (RegNo & 0x1)
1750 return Fail;
1751
1752 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo);
1753 Inst.addOperand(MCOperand::createReg(Register));
1754 return Success;
1755}
1756
1757static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
1758 unsigned RegNo,
1759 uint64_t Addr,
1760 const void *Decoder) {
Junmo Park45513a82016-07-15 22:42:52 +0000[diff] [blame]1761 return DecodeGPRSeqPairsClassRegisterClass(Inst,
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1762 AArch64::WSeqPairsClassRegClassID,
1763 RegNo, Addr, Decoder);
1764}
1765
1766static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
1767 unsigned RegNo,
1768 uint64_t Addr,
1769 const void *Decoder) {
Junmo Park45513a82016-07-15 22:42:52 +0000[diff] [blame]1770 return DecodeGPRSeqPairsClassRegisterClass(Inst,
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1771 AArch64::XSeqPairsClassRegClassID,
1772 RegNo, Addr, Decoder);
1773}
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]1774
Sander de Smalen81fcf862018-02-06 13:13:21 +0000[diff] [blame]1775static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
1776 uint32_t insn,
1777 uint64_t Addr,
1778 const void *Decoder) {
1779 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1780 unsigned imm = fieldFromInstruction(insn, 5, 13);
1781 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1782 return Fail;
1783
1784 // The same (tied) operand is added twice to the instruction.
1785 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
Sander de Smalen97ca6b92018-06-01 07:25:46 +0000[diff] [blame]1786 if (Inst.getOpcode() != AArch64::DUPM_ZI)
1787 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
Sander de Smalen81fcf862018-02-06 13:13:21 +0000[diff] [blame]1788 Inst.addOperand(MCOperand::createImm(imm));
1789 return Success;
1790}
1791
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]1792template<int Bits>
1793static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
1794 uint64_t Address, const void *Decoder) {
1795 if (Imm & ~((1LL << Bits) - 1))
1796 return Fail;
1797
1798 // Imm is a signed immediate, so sign extend it.
1799 if (Imm & (1 << (Bits - 1)))
1800 Imm |= ~((1LL << Bits) - 1);
1801
1802 Inst.addOperand(MCOperand::createImm(Imm));
1803 return Success;
1804}
1805
Sander de Smalen62770792018-05-25 09:47:52 +0000[diff] [blame]1806// Decode 8-bit signed/unsigned immediate for a given element width.
1807template <int ElementWidth>
1808static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
1809 uint64_t Addr, const void *Decoder) {
1810 unsigned Val = (uint8_t)Imm;
1811 unsigned Shift = (Imm & 0x100) ? 8 : 0;
1812 if (ElementWidth == 8 && Shift)
1813 return Fail;
1814 Inst.addOperand(MCOperand::createImm(Val));
1815 Inst.addOperand(MCOperand::createImm(Shift));
1816 return Success;
1817}
Sander de Smalen18ac8f92018-06-15 15:47:44 +0000[diff] [blame]1818
1819// Decode uimm4 ranged from 1-16.
1820static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
1821 uint64_t Addr, const void *Decoder) {
1822 Inst.addOperand(MCOperand::createImm(Imm + 1));
1823 return Success;
1824}