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gerrit-public.fairphone.software / toolchain / llvm-project / 62770795a5f8028773339fd57f763c2acebe76d3 / . / llvm / lib / Target / AArch64 / Disassembler / AArch64Disassembler.cpp
blob: ecb51cf695fe2439a72451ce215c9af031db46e6 [file] [log] [blame]
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1//===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64Disassembler.h"
14#include "AArch64ExternalSymbolizer.h"
15#include "AArch64Subtarget.h"
16#include "MCTargetDesc/AArch64AddressingModes.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]17#include "MCTargetDesc/AArch64MCTargetDesc.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]18#include "Utils/AArch64BaseInfo.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]19#include "llvm-c/Disassembler.h"
20#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]21#include "llvm/MC/MCFixedLenDisassembler.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]22#include "llvm/MC/MCInst.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]23#include "llvm/Support/Compiler.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]24#include "llvm/Support/Debug.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]25#include "llvm/Support/ErrorHandling.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]26#include "llvm/Support/TargetRegistry.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]27#include <algorithm>
28#include <memory>
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]29
30using namespace llvm;
31
32#define DEBUG_TYPE "aarch64-disassembler"
33
34// Pull DecodeStatus and its enum values into the global namespace.
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]35using DecodeStatus = MCDisassembler::DecodeStatus;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]36
37// Forward declare these because the autogenerated code will reference them.
38// Definitions are further down.
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]39static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]40 unsigned RegNo, uint64_t Address,
41 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]42static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]43 unsigned RegNo,
44 uint64_t Address,
45 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]46static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]47 uint64_t Address,
48 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]49static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]50 uint64_t Address,
51 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]52static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]53 uint64_t Address,
54 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]55static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]56 uint64_t Address,
57 const void *Decoder);
Sander de Smalen367694b2018-04-20 08:54:49 +0000[diff] [blame]58static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
59 uint64_t Address,
60 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]61static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]62 uint64_t Address,
63 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]64static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]65 unsigned RegNo, uint64_t Address,
66 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]67static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]68 uint64_t Address,
69 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]70static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]71 unsigned RegNo, uint64_t Address,
72 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]73static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]74 uint64_t Address,
75 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]76static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]77 uint64_t Address,
78 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]79static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]80 uint64_t Address,
81 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]82static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]83 uint64_t Address,
84 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]85static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]86 uint64_t Address,
87 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]88static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]89 uint64_t Address,
90 const void *Decoder);
Florian Hahn91f11e52017-11-07 16:45:48 +0000[diff] [blame]91static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
92 uint64_t Address,
93 const void *Decode);
Sander de Smalenf836af82018-04-16 07:09:29 +0000[diff] [blame]94static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
95 uint64_t Address,
96 const void *Decode);
Sander de Smalend239eb32018-04-16 10:10:48 +0000[diff] [blame]97static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
98 uint64_t Address,
99 const void *Decode);
Sander de Smalen7a210db2018-04-16 10:46:18 +0000[diff] [blame]100static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
101 uint64_t Address,
102 const void *Decode);
Sander de Smalencd6be962017-12-20 11:02:42 +0000[diff] [blame]103static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
104 uint64_t Address,
105 const void *Decode);
Sander de Smalen906a5de2018-01-09 17:01:27 +0000[diff] [blame]106static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
107 uint64_t Address,
108 const void *Decode);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]109
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]110static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]111 uint64_t Address,
112 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]113static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]114 uint64_t Address,
115 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]116static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]117 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]118static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]119 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]120static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]121 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]122static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]123 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]124static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]125 uint64_t Address,
126 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]127static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]128 uint64_t Address,
129 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]130static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]131 uint64_t Address,
132 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]133static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
134 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]135 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]136static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]137 uint64_t Address,
138 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]139static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]140 uint64_t Address,
141 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]142static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
143 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]144 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]145static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
146 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]147 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]148static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]149 uint64_t Address,
150 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]151static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
152 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]153 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]154static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]155 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]156static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]157 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]158static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]159 uint64_t Address,
160 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]161static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]162 uint64_t Address,
163 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]164static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]165 uint64_t Address, const void *Decoder);
166
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]167static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]168 uint64_t Address,
169 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]170static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]171 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]172static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]173 uint64_t Addr,
174 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]175static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]176 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]177static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]178 uint64_t Addr,
179 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]180static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]181 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]182static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]183 uint64_t Addr,
184 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]185static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]186 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]187static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]188 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]189static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]190 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]191static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]192 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]193static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]194 uint64_t Addr, const void *Decoder);
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]195static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
196 unsigned RegNo,
197 uint64_t Addr,
198 const void *Decoder);
199static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
200 unsigned RegNo,
201 uint64_t Addr,
202 const void *Decoder);
Sander de Smalen81fcf862018-02-06 13:13:21 +0000[diff] [blame]203static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
204 uint32_t insn,
205 uint64_t Address,
206 const void *Decoder);
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]207template<int Bits>
208static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
209 uint64_t Address, const void *Decoder);
Sander de Smalen62770792018-05-25 09:47:52 +0000[diff] [blame^]210template <int ElementWidth>
211static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
212 uint64_t Addr, const void *Decoder);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]213
214static bool Check(DecodeStatus &Out, DecodeStatus In) {
215 switch (In) {
216 case MCDisassembler::Success:
217 // Out stays the same.
218 return true;
219 case MCDisassembler::SoftFail:
220 Out = In;
221 return true;
222 case MCDisassembler::Fail:
223 Out = In;
224 return false;
225 }
226 llvm_unreachable("Invalid DecodeStatus!");
227}
228
229#include "AArch64GenDisassemblerTables.inc"
230#include "AArch64GenInstrInfo.inc"
231
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]232#define Success MCDisassembler::Success
233#define Fail MCDisassembler::Fail
234#define SoftFail MCDisassembler::SoftFail
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]235
236static MCDisassembler *createAArch64Disassembler(const Target &T,
237 const MCSubtargetInfo &STI,
238 MCContext &Ctx) {
239 return new AArch64Disassembler(STI, Ctx);
240}
241
242DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000[diff] [blame]243 ArrayRef<uint8_t> Bytes,
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]244 uint64_t Address,
245 raw_ostream &OS,
246 raw_ostream &CS) const {
247 CommentStream = &CS;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]248
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]249 Size = 0;
250 // We want to read exactly 4 bytes of data.
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000[diff] [blame]251 if (Bytes.size() < 4)
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]252 return Fail;
253 Size = 4;
254
255 // Encoded as a small-endian 32-bit word in the stream.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]256 uint32_t Insn =
257 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]258
259 // Calling the auto-generated decoder function.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]260 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]261}
262
Daniel Sanders50f17232015-09-15 16:17:27 +0000[diff] [blame]263static MCSymbolizer *
264createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
265 LLVMSymbolLookupCallback SymbolLookUp,
266 void *DisInfo, MCContext *Ctx,
267 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]268 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
269 SymbolLookUp, DisInfo);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]270}
271
272extern "C" void LLVMInitializeAArch64Disassembler() {
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]273 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]274 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]275 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]276 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]277 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]278 createAArch64ExternalSymbolizer);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]279 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]280 createAArch64ExternalSymbolizer);
281
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]282 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]283 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]284 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]285 createAArch64ExternalSymbolizer);
286}
287
288static const unsigned FPR128DecoderTable[] = {
289 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
290 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
291 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
292 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
293 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
294 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
295 AArch64::Q30, AArch64::Q31
296};
297
298static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
299 uint64_t Addr,
300 const void *Decoder) {
301 if (RegNo > 31)
302 return Fail;
303
304 unsigned Register = FPR128DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]305 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]306 return Success;
307}
308
309static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
310 uint64_t Addr,
311 const void *Decoder) {
312 if (RegNo > 15)
313 return Fail;
314 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
315}
316
317static const unsigned FPR64DecoderTable[] = {
318 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
319 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
320 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
321 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
322 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24,
323 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29,
324 AArch64::D30, AArch64::D31
325};
326
327static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
328 uint64_t Addr,
329 const void *Decoder) {
330 if (RegNo > 31)
331 return Fail;
332
333 unsigned Register = FPR64DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]334 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]335 return Success;
336}
337
338static const unsigned FPR32DecoderTable[] = {
339 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
340 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9,
341 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14,
342 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19,
343 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24,
344 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29,
345 AArch64::S30, AArch64::S31
346};
347
348static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
349 uint64_t Addr,
350 const void *Decoder) {
351 if (RegNo > 31)
352 return Fail;
353
354 unsigned Register = FPR32DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]355 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]356 return Success;
357}
358
359static const unsigned FPR16DecoderTable[] = {
360 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4,
361 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9,
362 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14,
363 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19,
364 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24,
365 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29,
366 AArch64::H30, AArch64::H31
367};
368
369static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
370 uint64_t Addr,
371 const void *Decoder) {
372 if (RegNo > 31)
373 return Fail;
374
375 unsigned Register = FPR16DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]376 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]377 return Success;
378}
379
380static const unsigned FPR8DecoderTable[] = {
381 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4,
382 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9,
383 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14,
384 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,
385 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24,
386 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29,
387 AArch64::B30, AArch64::B31
388};
389
390static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
391 uint64_t Addr,
392 const void *Decoder) {
393 if (RegNo > 31)
394 return Fail;
395
396 unsigned Register = FPR8DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]397 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]398 return Success;
399}
400
401static const unsigned GPR64DecoderTable[] = {
402 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
403 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9,
404 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14,
405 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19,
406 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24,
407 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
408 AArch64::LR, AArch64::XZR
409};
410
Sander de Smalen367694b2018-04-20 08:54:49 +0000[diff] [blame]411static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
412 uint64_t Addr,
413 const void *Decoder) {
414 if (RegNo > 30)
415 return Fail;
416
417 unsigned Register = GPR64DecoderTable[RegNo];
418 Inst.addOperand(MCOperand::createReg(Register));
419 return Success;
420}
421
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]422static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
423 uint64_t Addr,
424 const void *Decoder) {
425 if (RegNo > 31)
426 return Fail;
427
428 unsigned Register = GPR64DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]429 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]430 return Success;
431}
432
433static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
434 uint64_t Addr,
435 const void *Decoder) {
436 if (RegNo > 31)
437 return Fail;
438 unsigned Register = GPR64DecoderTable[RegNo];
439 if (Register == AArch64::XZR)
440 Register = AArch64::SP;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]441 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]442 return Success;
443}
444
445static const unsigned GPR32DecoderTable[] = {
446 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
447 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9,
448 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14,
449 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19,
450 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24,
451 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29,
452 AArch64::W30, AArch64::WZR
453};
454
455static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
456 uint64_t Addr,
457 const void *Decoder) {
458 if (RegNo > 31)
459 return Fail;
460
461 unsigned Register = GPR32DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]462 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]463 return Success;
464}
465
466static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
467 uint64_t Addr,
468 const void *Decoder) {
469 if (RegNo > 31)
470 return Fail;
471
472 unsigned Register = GPR32DecoderTable[RegNo];
473 if (Register == AArch64::WZR)
474 Register = AArch64::WSP;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]475 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]476 return Success;
477}
Florian Hahn91f11e52017-11-07 16:45:48 +0000[diff] [blame]478static const unsigned ZPRDecoderTable[] = {
479 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3,
480 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7,
481 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11,
482 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15,
483 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19,
484 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23,
485 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27,
486 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31
487};
488
489static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
490 uint64_t Address,
491 const void* Decoder) {
492 if (RegNo > 31)
493 return Fail;
494
495 unsigned Register = ZPRDecoderTable[RegNo];
496 Inst.addOperand(MCOperand::createReg(Register));
497 return Success;
498}
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]499
Sander de Smalenf836af82018-04-16 07:09:29 +0000[diff] [blame]500static const unsigned ZZDecoderTable[] = {
501 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4,
502 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8,
503 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12,
504 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16,
505 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20,
506 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24,
507 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28,
508 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0
509};
510
511static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
512 uint64_t Address,
513 const void* Decoder) {
514 if (RegNo > 31)
515 return Fail;
516 unsigned Register = ZZDecoderTable[RegNo];
517 Inst.addOperand(MCOperand::createReg(Register));
518 return Success;
519}
520
Sander de Smalend239eb32018-04-16 10:10:48 +0000[diff] [blame]521static const unsigned ZZZDecoderTable[] = {
522 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4,
523 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7,
524 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10,
525 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13,
526 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16,
527 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19,
528 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22,
529 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25,
530 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28,
531 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31,
532 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1
533};
534
535static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
536 uint64_t Address,
537 const void* Decoder) {
538 if (RegNo > 31)
539 return Fail;
540 unsigned Register = ZZZDecoderTable[RegNo];
541 Inst.addOperand(MCOperand::createReg(Register));
542 return Success;
543}
544
Sander de Smalen7a210db2018-04-16 10:46:18 +0000[diff] [blame]545static const unsigned ZZZZDecoderTable[] = {
546 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5,
547 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8,
548 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11,
549 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14,
550 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17,
551 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20,
552 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23,
553 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26,
554 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29,
555 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0,
556 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2
557};
558
559static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
560 uint64_t Address,
561 const void* Decoder) {
562 if (RegNo > 31)
563 return Fail;
564 unsigned Register = ZZZZDecoderTable[RegNo];
565 Inst.addOperand(MCOperand::createReg(Register));
566 return Success;
567}
568
Sander de Smalencd6be962017-12-20 11:02:42 +0000[diff] [blame]569static const unsigned PPRDecoderTable[] = {
570 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3,
571 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7,
572 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11,
573 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15
574};
575
576static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
577 uint64_t Addr, const void *Decoder) {
578 if (RegNo > 15)
579 return Fail;
580
581 unsigned Register = PPRDecoderTable[RegNo];
582 Inst.addOperand(MCOperand::createReg(Register));
583 return Success;
584}
585
Sander de Smalendc5e0812018-01-03 10:15:46 +0000[diff] [blame]586static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
587 uint64_t Addr,
588 const void* Decoder) {
589 if (RegNo > 7)
590 return Fail;
591
592 // Just reuse the PPR decode table
593 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
594}
595
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]596static const unsigned VectorDecoderTable[] = {
597 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
598 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
599 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
600 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
601 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
602 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
603 AArch64::Q30, AArch64::Q31
604};
605
606static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
607 uint64_t Addr,
608 const void *Decoder) {
609 if (RegNo > 31)
610 return Fail;
611
612 unsigned Register = VectorDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]613 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]614 return Success;
615}
616
617static const unsigned QQDecoderTable[] = {
618 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4,
619 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8,
620 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12,
621 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
622 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20,
623 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24,
624 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28,
625 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0
626};
627
628static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
629 uint64_t Addr, const void *Decoder) {
630 if (RegNo > 31)
631 return Fail;
632 unsigned Register = QQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]633 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]634 return Success;
635}
636
637static const unsigned QQQDecoderTable[] = {
638 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4,
639 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7,
640 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10,
641 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13,
642 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
643 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19,
644 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22,
645 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25,
646 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28,
647 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31,
648 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1
649};
650
651static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
652 uint64_t Addr, const void *Decoder) {
653 if (RegNo > 31)
654 return Fail;
655 unsigned Register = QQQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]656 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]657 return Success;
658}
659
660static const unsigned QQQQDecoderTable[] = {
661 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5,
662 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8,
663 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11,
664 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14,
665 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
666 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20,
667 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23,
668 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26,
669 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29,
670 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0,
671 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2
672};
673
674static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
675 uint64_t Addr,
676 const void *Decoder) {
677 if (RegNo > 31)
678 return Fail;
679 unsigned Register = QQQQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]680 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]681 return Success;
682}
683
684static const unsigned DDDecoderTable[] = {
685 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4,
686 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8,
687 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12,
688 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16,
689 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20,
690 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24,
691 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28,
692 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0
693};
694
695static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
696 uint64_t Addr, const void *Decoder) {
697 if (RegNo > 31)
698 return Fail;
699 unsigned Register = DDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]700 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]701 return Success;
702}
703
704static const unsigned DDDDecoderTable[] = {
705 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4,
706 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7,
707 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10,
708 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13,
709 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16,
710 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19,
711 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22,
712 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25,
713 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28,
714 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31,
715 AArch64::D30_D31_D0, AArch64::D31_D0_D1
716};
717
718static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
719 uint64_t Addr, const void *Decoder) {
720 if (RegNo > 31)
721 return Fail;
722 unsigned Register = DDDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]723 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]724 return Success;
725}
726
727static const unsigned DDDDDecoderTable[] = {
728 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5,
729 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8,
730 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11,
731 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14,
732 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17,
733 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20,
734 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23,
735 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26,
736 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29,
737 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0,
738 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2
739};
740
741static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
742 uint64_t Addr,
743 const void *Decoder) {
744 if (RegNo > 31)
745 return Fail;
746 unsigned Register = DDDDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]747 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]748 return Success;
749}
750
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]751static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]752 uint64_t Addr,
753 const void *Decoder) {
754 // scale{5} is asserted as 1 in tblgen.
Tom Coxon2c13e712014-09-30 16:23:16 +0000[diff] [blame]755 Imm |= 0x20;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]756 Inst.addOperand(MCOperand::createImm(64 - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]757 return Success;
758}
759
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]760static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]761 uint64_t Addr,
762 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]763 Inst.addOperand(MCOperand::createImm(64 - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]764 return Success;
765}
766
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]767static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]768 uint64_t Addr, const void *Decoder) {
769 int64_t ImmVal = Imm;
770 const AArch64Disassembler *Dis =
771 static_cast<const AArch64Disassembler *>(Decoder);
772
773 // Sign-extend 19-bit immediate.
774 if (ImmVal & (1 << (19 - 1)))
775 ImmVal |= ~((1LL << 19) - 1);
776
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]777 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]778 Inst.getOpcode() != AArch64::LDRXl, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]779 Inst.addOperand(MCOperand::createImm(ImmVal));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]780 return Success;
781}
782
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]783static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]784 uint64_t Address, const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]785 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
786 Inst.addOperand(MCOperand::createImm(Imm & 1));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]787 return Success;
788}
789
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]790static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]791 uint64_t Address,
792 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]793 Inst.addOperand(MCOperand::createImm(Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]794
Tom Coxone493f172014-10-01 10:13:59 +0000[diff] [blame]795 // Every system register in the encoding space is valid with the syntax
796 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
797 return Success;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]798}
799
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]800static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]801 uint64_t Address,
802 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]803 Inst.addOperand(MCOperand::createImm(Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]804
Tom Coxone493f172014-10-01 10:13:59 +0000[diff] [blame]805 return Success;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]806}
807
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]808static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]809 uint64_t Address,
810 const void *Decoder) {
811 // This decoder exists to add the dummy Lane operand to the MCInst, which must
812 // be 1 in assembly but has no other real manifestation.
813 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
814 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
815 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
816
817 if (IsToVec) {
818 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
819 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
820 } else {
821 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
822 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
823 }
824
825 // Add the lane
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]826 Inst.addOperand(MCOperand::createImm(1));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]827
828 return Success;
829}
830
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]831static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]832 unsigned Add) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]833 Inst.addOperand(MCOperand::createImm(Add - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]834 return Success;
835}
836
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]837static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]838 unsigned Add) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]839 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]840 return Success;
841}
842
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]843static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]844 uint64_t Addr, const void *Decoder) {
845 return DecodeVecShiftRImm(Inst, Imm, 64);
846}
847
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]848static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]849 uint64_t Addr,
850 const void *Decoder) {
851 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
852}
853
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]854static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]855 uint64_t Addr, const void *Decoder) {
856 return DecodeVecShiftRImm(Inst, Imm, 32);
857}
858
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]859static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]860 uint64_t Addr,
861 const void *Decoder) {
862 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
863}
864
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]865static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]866 uint64_t Addr, const void *Decoder) {
867 return DecodeVecShiftRImm(Inst, Imm, 16);
868}
869
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]870static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]871 uint64_t Addr,
872 const void *Decoder) {
873 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
874}
875
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]876static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]877 uint64_t Addr, const void *Decoder) {
878 return DecodeVecShiftRImm(Inst, Imm, 8);
879}
880
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]881static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]882 uint64_t Addr, const void *Decoder) {
883 return DecodeVecShiftLImm(Inst, Imm, 64);
884}
885
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]886static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]887 uint64_t Addr, const void *Decoder) {
888 return DecodeVecShiftLImm(Inst, Imm, 32);
889}
890
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]891static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]892 uint64_t Addr, const void *Decoder) {
893 return DecodeVecShiftLImm(Inst, Imm, 16);
894}
895
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]896static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]897 uint64_t Addr, const void *Decoder) {
898 return DecodeVecShiftLImm(Inst, Imm, 8);
899}
900
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]901static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
902 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]903 const void *Decoder) {
904 unsigned Rd = fieldFromInstruction(insn, 0, 5);
905 unsigned Rn = fieldFromInstruction(insn, 5, 5);
906 unsigned Rm = fieldFromInstruction(insn, 16, 5);
907 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
908 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
909 unsigned shift = (shiftHi << 6) | shiftLo;
910 switch (Inst.getOpcode()) {
911 default:
912 return Fail;
913 case AArch64::ADDWrs:
914 case AArch64::ADDSWrs:
915 case AArch64::SUBWrs:
916 case AArch64::SUBSWrs:
917 // if shift == '11' then ReservedValue()
918 if (shiftHi == 0x3)
919 return Fail;
Simon Pilgrimcb07d672017-07-07 16:40:06 +0000[diff] [blame]920 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]921 case AArch64::ANDWrs:
922 case AArch64::ANDSWrs:
923 case AArch64::BICWrs:
924 case AArch64::BICSWrs:
925 case AArch64::ORRWrs:
926 case AArch64::ORNWrs:
927 case AArch64::EORWrs:
928 case AArch64::EONWrs: {
929 // if sf == '0' and imm6<5> == '1' then ReservedValue()
930 if (shiftLo >> 5 == 1)
931 return Fail;
932 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
933 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
934 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
935 break;
936 }
937 case AArch64::ADDXrs:
938 case AArch64::ADDSXrs:
939 case AArch64::SUBXrs:
940 case AArch64::SUBSXrs:
941 // if shift == '11' then ReservedValue()
942 if (shiftHi == 0x3)
943 return Fail;
Simon Pilgrimcb07d672017-07-07 16:40:06 +0000[diff] [blame]944 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]945 case AArch64::ANDXrs:
946 case AArch64::ANDSXrs:
947 case AArch64::BICXrs:
948 case AArch64::BICSXrs:
949 case AArch64::ORRXrs:
950 case AArch64::ORNXrs:
951 case AArch64::EORXrs:
952 case AArch64::EONXrs:
953 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
954 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
955 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
956 break;
957 }
958
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]959 Inst.addOperand(MCOperand::createImm(shift));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]960 return Success;
961}
962
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]963static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]964 uint64_t Addr,
965 const void *Decoder) {
966 unsigned Rd = fieldFromInstruction(insn, 0, 5);
967 unsigned imm = fieldFromInstruction(insn, 5, 16);
968 unsigned shift = fieldFromInstruction(insn, 21, 2);
969 shift <<= 4;
970 switch (Inst.getOpcode()) {
971 default:
972 return Fail;
973 case AArch64::MOVZWi:
974 case AArch64::MOVNWi:
975 case AArch64::MOVKWi:
976 if (shift & (1U << 5))
977 return Fail;
978 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
979 break;
980 case AArch64::MOVZXi:
981 case AArch64::MOVNXi:
982 case AArch64::MOVKXi:
983 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
984 break;
985 }
986
987 if (Inst.getOpcode() == AArch64::MOVKWi ||
988 Inst.getOpcode() == AArch64::MOVKXi)
989 Inst.addOperand(Inst.getOperand(0));
990
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]991 Inst.addOperand(MCOperand::createImm(imm));
992 Inst.addOperand(MCOperand::createImm(shift));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]993 return Success;
994}
995
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]996static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
997 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]998 const void *Decoder) {
999 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1000 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1001 unsigned offset = fieldFromInstruction(insn, 10, 12);
1002 const AArch64Disassembler *Dis =
1003 static_cast<const AArch64Disassembler *>(Decoder);
1004
1005 switch (Inst.getOpcode()) {
1006 default:
1007 return Fail;
1008 case AArch64::PRFMui:
1009 // Rt is an immediate in prefetch.
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1010 Inst.addOperand(MCOperand::createImm(Rt));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1011 break;
1012 case AArch64::STRBBui:
1013 case AArch64::LDRBBui:
1014 case AArch64::LDRSBWui:
1015 case AArch64::STRHHui:
1016 case AArch64::LDRHHui:
1017 case AArch64::LDRSHWui:
1018 case AArch64::STRWui:
1019 case AArch64::LDRWui:
1020 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1021 break;
1022 case AArch64::LDRSBXui:
1023 case AArch64::LDRSHXui:
1024 case AArch64::LDRSWui:
1025 case AArch64::STRXui:
1026 case AArch64::LDRXui:
1027 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1028 break;
1029 case AArch64::LDRQui:
1030 case AArch64::STRQui:
1031 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1032 break;
1033 case AArch64::LDRDui:
1034 case AArch64::STRDui:
1035 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1036 break;
1037 case AArch64::LDRSui:
1038 case AArch64::STRSui:
1039 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1040 break;
1041 case AArch64::LDRHui:
1042 case AArch64::STRHui:
1043 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1044 break;
1045 case AArch64::LDRBui:
1046 case AArch64::STRBui:
1047 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1048 break;
1049 }
1050
1051 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1052 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1053 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1054 return Success;
1055}
1056
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1057static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
1058 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1059 const void *Decoder) {
1060 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1061 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1062 int64_t offset = fieldFromInstruction(insn, 12, 9);
1063
1064 // offset is a 9-bit signed immediate, so sign extend it to
1065 // fill the unsigned.
1066 if (offset & (1 << (9 - 1)))
1067 offset |= ~((1LL << 9) - 1);
1068
1069 // First operand is always the writeback to the address register, if needed.
1070 switch (Inst.getOpcode()) {
1071 default:
1072 break;
1073 case AArch64::LDRSBWpre:
1074 case AArch64::LDRSHWpre:
1075 case AArch64::STRBBpre:
1076 case AArch64::LDRBBpre:
1077 case AArch64::STRHHpre:
1078 case AArch64::LDRHHpre:
1079 case AArch64::STRWpre:
1080 case AArch64::LDRWpre:
1081 case AArch64::LDRSBWpost:
1082 case AArch64::LDRSHWpost:
1083 case AArch64::STRBBpost:
1084 case AArch64::LDRBBpost:
1085 case AArch64::STRHHpost:
1086 case AArch64::LDRHHpost:
1087 case AArch64::STRWpost:
1088 case AArch64::LDRWpost:
1089 case AArch64::LDRSBXpre:
1090 case AArch64::LDRSHXpre:
1091 case AArch64::STRXpre:
1092 case AArch64::LDRSWpre:
1093 case AArch64::LDRXpre:
1094 case AArch64::LDRSBXpost:
1095 case AArch64::LDRSHXpost:
1096 case AArch64::STRXpost:
1097 case AArch64::LDRSWpost:
1098 case AArch64::LDRXpost:
1099 case AArch64::LDRQpre:
1100 case AArch64::STRQpre:
1101 case AArch64::LDRQpost:
1102 case AArch64::STRQpost:
1103 case AArch64::LDRDpre:
1104 case AArch64::STRDpre:
1105 case AArch64::LDRDpost:
1106 case AArch64::STRDpost:
1107 case AArch64::LDRSpre:
1108 case AArch64::STRSpre:
1109 case AArch64::LDRSpost:
1110 case AArch64::STRSpost:
1111 case AArch64::LDRHpre:
1112 case AArch64::STRHpre:
1113 case AArch64::LDRHpost:
1114 case AArch64::STRHpost:
1115 case AArch64::LDRBpre:
1116 case AArch64::STRBpre:
1117 case AArch64::LDRBpost:
1118 case AArch64::STRBpost:
1119 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1120 break;
1121 }
1122
1123 switch (Inst.getOpcode()) {
1124 default:
1125 return Fail;
1126 case AArch64::PRFUMi:
1127 // Rt is an immediate in prefetch.
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1128 Inst.addOperand(MCOperand::createImm(Rt));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1129 break;
1130 case AArch64::STURBBi:
1131 case AArch64::LDURBBi:
1132 case AArch64::LDURSBWi:
1133 case AArch64::STURHHi:
1134 case AArch64::LDURHHi:
1135 case AArch64::LDURSHWi:
1136 case AArch64::STURWi:
1137 case AArch64::LDURWi:
1138 case AArch64::LDTRSBWi:
1139 case AArch64::LDTRSHWi:
1140 case AArch64::STTRWi:
1141 case AArch64::LDTRWi:
1142 case AArch64::STTRHi:
1143 case AArch64::LDTRHi:
1144 case AArch64::LDTRBi:
1145 case AArch64::STTRBi:
1146 case AArch64::LDRSBWpre:
1147 case AArch64::LDRSHWpre:
1148 case AArch64::STRBBpre:
1149 case AArch64::LDRBBpre:
1150 case AArch64::STRHHpre:
1151 case AArch64::LDRHHpre:
1152 case AArch64::STRWpre:
1153 case AArch64::LDRWpre:
1154 case AArch64::LDRSBWpost:
1155 case AArch64::LDRSHWpost:
1156 case AArch64::STRBBpost:
1157 case AArch64::LDRBBpost:
1158 case AArch64::STRHHpost:
1159 case AArch64::LDRHHpost:
1160 case AArch64::STRWpost:
1161 case AArch64::LDRWpost:
1162 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1163 break;
1164 case AArch64::LDURSBXi:
1165 case AArch64::LDURSHXi:
1166 case AArch64::LDURSWi:
1167 case AArch64::STURXi:
1168 case AArch64::LDURXi:
1169 case AArch64::LDTRSBXi:
1170 case AArch64::LDTRSHXi:
1171 case AArch64::LDTRSWi:
1172 case AArch64::STTRXi:
1173 case AArch64::LDTRXi:
1174 case AArch64::LDRSBXpre:
1175 case AArch64::LDRSHXpre:
1176 case AArch64::STRXpre:
1177 case AArch64::LDRSWpre:
1178 case AArch64::LDRXpre:
1179 case AArch64::LDRSBXpost:
1180 case AArch64::LDRSHXpost:
1181 case AArch64::STRXpost:
1182 case AArch64::LDRSWpost:
1183 case AArch64::LDRXpost:
1184 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1185 break;
1186 case AArch64::LDURQi:
1187 case AArch64::STURQi:
1188 case AArch64::LDRQpre:
1189 case AArch64::STRQpre:
1190 case AArch64::LDRQpost:
1191 case AArch64::STRQpost:
1192 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1193 break;
1194 case AArch64::LDURDi:
1195 case AArch64::STURDi:
1196 case AArch64::LDRDpre:
1197 case AArch64::STRDpre:
1198 case AArch64::LDRDpost:
1199 case AArch64::STRDpost:
1200 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1201 break;
1202 case AArch64::LDURSi:
1203 case AArch64::STURSi:
1204 case AArch64::LDRSpre:
1205 case AArch64::STRSpre:
1206 case AArch64::LDRSpost:
1207 case AArch64::STRSpost:
1208 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1209 break;
1210 case AArch64::LDURHi:
1211 case AArch64::STURHi:
1212 case AArch64::LDRHpre:
1213 case AArch64::STRHpre:
1214 case AArch64::LDRHpost:
1215 case AArch64::STRHpost:
1216 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1217 break;
1218 case AArch64::LDURBi:
1219 case AArch64::STURBi:
1220 case AArch64::LDRBpre:
1221 case AArch64::STRBpre:
1222 case AArch64::LDRBpost:
1223 case AArch64::STRBpost:
1224 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1225 break;
1226 }
1227
1228 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1229 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1230
1231 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1232 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1233 bool IsFP = fieldFromInstruction(insn, 26, 1);
1234
1235 // Cannot write back to a transfer register (but xzr != sp).
1236 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1237 return SoftFail;
1238
1239 return Success;
1240}
1241
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1242static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
1243 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1244 const void *Decoder) {
1245 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1246 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1247 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1248 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1249
1250 unsigned Opcode = Inst.getOpcode();
1251 switch (Opcode) {
1252 default:
1253 return Fail;
1254 case AArch64::STLXRW:
1255 case AArch64::STLXRB:
1256 case AArch64::STLXRH:
1257 case AArch64::STXRW:
1258 case AArch64::STXRB:
1259 case AArch64::STXRH:
1260 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1261 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1262 case AArch64::LDARW:
1263 case AArch64::LDARB:
1264 case AArch64::LDARH:
1265 case AArch64::LDAXRW:
1266 case AArch64::LDAXRB:
1267 case AArch64::LDAXRH:
1268 case AArch64::LDXRW:
1269 case AArch64::LDXRB:
1270 case AArch64::LDXRH:
1271 case AArch64::STLRW:
1272 case AArch64::STLRB:
1273 case AArch64::STLRH:
Vladimir Sukharevd49cb8f2015-04-16 15:30:43 +0000[diff] [blame]1274 case AArch64::STLLRW:
1275 case AArch64::STLLRB:
1276 case AArch64::STLLRH:
1277 case AArch64::LDLARW:
1278 case AArch64::LDLARB:
1279 case AArch64::LDLARH:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1280 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1281 break;
1282 case AArch64::STLXRX:
1283 case AArch64::STXRX:
1284 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1285 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1286 case AArch64::LDARX:
1287 case AArch64::LDAXRX:
1288 case AArch64::LDXRX:
1289 case AArch64::STLRX:
Vladimir Sukharevd49cb8f2015-04-16 15:30:43 +0000[diff] [blame]1290 case AArch64::LDLARX:
1291 case AArch64::STLLRX:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1292 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1293 break;
1294 case AArch64::STLXPW:
1295 case AArch64::STXPW:
1296 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1297 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1298 case AArch64::LDAXPW:
1299 case AArch64::LDXPW:
1300 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1301 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1302 break;
1303 case AArch64::STLXPX:
1304 case AArch64::STXPX:
1305 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1306 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1307 case AArch64::LDAXPX:
1308 case AArch64::LDXPX:
1309 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1310 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1311 break;
1312 }
1313
1314 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1315
1316 // You shouldn't load to the same register twice in an instruction...
1317 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1318 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1319 Rt == Rt2)
1320 return SoftFail;
1321
1322 return Success;
1323}
1324
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1325static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1326 uint64_t Addr,
1327 const void *Decoder) {
1328 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1329 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1330 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1331 int64_t offset = fieldFromInstruction(insn, 15, 7);
1332 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1333
1334 // offset is a 7-bit signed immediate, so sign extend it to
1335 // fill the unsigned.
1336 if (offset & (1 << (7 - 1)))
1337 offset |= ~((1LL << 7) - 1);
1338
1339 unsigned Opcode = Inst.getOpcode();
1340 bool NeedsDisjointWritebackTransfer = false;
1341
1342 // First operand is always writeback of base register.
1343 switch (Opcode) {
1344 default:
1345 break;
1346 case AArch64::LDPXpost:
1347 case AArch64::STPXpost:
1348 case AArch64::LDPSWpost:
1349 case AArch64::LDPXpre:
1350 case AArch64::STPXpre:
1351 case AArch64::LDPSWpre:
1352 case AArch64::LDPWpost:
1353 case AArch64::STPWpost:
1354 case AArch64::LDPWpre:
1355 case AArch64::STPWpre:
1356 case AArch64::LDPQpost:
1357 case AArch64::STPQpost:
1358 case AArch64::LDPQpre:
1359 case AArch64::STPQpre:
1360 case AArch64::LDPDpost:
1361 case AArch64::STPDpost:
1362 case AArch64::LDPDpre:
1363 case AArch64::STPDpre:
1364 case AArch64::LDPSpost:
1365 case AArch64::STPSpost:
1366 case AArch64::LDPSpre:
1367 case AArch64::STPSpre:
1368 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1369 break;
1370 }
1371
1372 switch (Opcode) {
1373 default:
1374 return Fail;
1375 case AArch64::LDPXpost:
1376 case AArch64::STPXpost:
1377 case AArch64::LDPSWpost:
1378 case AArch64::LDPXpre:
1379 case AArch64::STPXpre:
1380 case AArch64::LDPSWpre:
1381 NeedsDisjointWritebackTransfer = true;
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1382 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1383 case AArch64::LDNPXi:
1384 case AArch64::STNPXi:
1385 case AArch64::LDPXi:
1386 case AArch64::STPXi:
1387 case AArch64::LDPSWi:
1388 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1389 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1390 break;
1391 case AArch64::LDPWpost:
1392 case AArch64::STPWpost:
1393 case AArch64::LDPWpre:
1394 case AArch64::STPWpre:
1395 NeedsDisjointWritebackTransfer = true;
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1396 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1397 case AArch64::LDNPWi:
1398 case AArch64::STNPWi:
1399 case AArch64::LDPWi:
1400 case AArch64::STPWi:
1401 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1402 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1403 break;
1404 case AArch64::LDNPQi:
1405 case AArch64::STNPQi:
1406 case AArch64::LDPQpost:
1407 case AArch64::STPQpost:
1408 case AArch64::LDPQi:
1409 case AArch64::STPQi:
1410 case AArch64::LDPQpre:
1411 case AArch64::STPQpre:
1412 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1413 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1414 break;
1415 case AArch64::LDNPDi:
1416 case AArch64::STNPDi:
1417 case AArch64::LDPDpost:
1418 case AArch64::STPDpost:
1419 case AArch64::LDPDi:
1420 case AArch64::STPDi:
1421 case AArch64::LDPDpre:
1422 case AArch64::STPDpre:
1423 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1424 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1425 break;
1426 case AArch64::LDNPSi:
1427 case AArch64::STNPSi:
1428 case AArch64::LDPSpost:
1429 case AArch64::STPSpost:
1430 case AArch64::LDPSi:
1431 case AArch64::STPSi:
1432 case AArch64::LDPSpre:
1433 case AArch64::STPSpre:
1434 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1435 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1436 break;
1437 }
1438
1439 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1440 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1441
1442 // You shouldn't load to the same register twice in an instruction...
1443 if (IsLoad && Rt == Rt2)
1444 return SoftFail;
1445
1446 // ... or do any operation that writes-back to a transfer register. But note
1447 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1448 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1449 return SoftFail;
1450
1451 return Success;
1452}
1453
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1454static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1455 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1456 const void *Decoder) {
1457 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1458 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1459 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1460 unsigned extend = fieldFromInstruction(insn, 10, 6);
1461
1462 unsigned shift = extend & 0x7;
1463 if (shift > 4)
1464 return Fail;
1465
1466 switch (Inst.getOpcode()) {
1467 default:
1468 return Fail;
1469 case AArch64::ADDWrx:
1470 case AArch64::SUBWrx:
1471 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1472 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1473 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1474 break;
1475 case AArch64::ADDSWrx:
1476 case AArch64::SUBSWrx:
1477 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1478 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1479 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1480 break;
1481 case AArch64::ADDXrx:
1482 case AArch64::SUBXrx:
1483 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1484 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1485 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1486 break;
1487 case AArch64::ADDSXrx:
1488 case AArch64::SUBSXrx:
1489 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1490 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1491 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1492 break;
1493 case AArch64::ADDXrx64:
1494 case AArch64::SUBXrx64:
1495 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1496 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1497 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1498 break;
1499 case AArch64::SUBSXrx64:
1500 case AArch64::ADDSXrx64:
1501 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1502 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1503 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1504 break;
1505 }
1506
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1507 Inst.addOperand(MCOperand::createImm(extend));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1508 return Success;
1509}
1510
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1511static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1512 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1513 const void *Decoder) {
1514 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1515 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1516 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1517 unsigned imm;
1518
1519 if (Datasize) {
1520 if (Inst.getOpcode() == AArch64::ANDSXri)
1521 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1522 else
1523 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1524 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1525 imm = fieldFromInstruction(insn, 10, 13);
1526 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1527 return Fail;
1528 } else {
1529 if (Inst.getOpcode() == AArch64::ANDSWri)
1530 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1531 else
1532 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1533 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1534 imm = fieldFromInstruction(insn, 10, 12);
1535 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1536 return Fail;
1537 }
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1538 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1539 return Success;
1540}
1541
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1542static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1543 uint64_t Addr,
1544 const void *Decoder) {
1545 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1546 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1547 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1548 imm |= fieldFromInstruction(insn, 5, 5);
1549
1550 if (Inst.getOpcode() == AArch64::MOVID)
1551 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1552 else
1553 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1554
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1555 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1556
1557 switch (Inst.getOpcode()) {
1558 default:
1559 break;
1560 case AArch64::MOVIv4i16:
1561 case AArch64::MOVIv8i16:
1562 case AArch64::MVNIv4i16:
1563 case AArch64::MVNIv8i16:
1564 case AArch64::MOVIv2i32:
1565 case AArch64::MOVIv4i32:
1566 case AArch64::MVNIv2i32:
1567 case AArch64::MVNIv4i32:
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1568 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1569 break;
1570 case AArch64::MOVIv2s_msl:
1571 case AArch64::MOVIv4s_msl:
1572 case AArch64::MVNIv2s_msl:
1573 case AArch64::MVNIv4s_msl:
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1574 Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1575 break;
1576 }
1577
1578 return Success;
1579}
1580
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1581static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1582 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1583 const void *Decoder) {
1584 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1585 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1586 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1587 imm |= fieldFromInstruction(insn, 5, 5);
1588
1589 // Tied operands added twice.
1590 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1591 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1592
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1593 Inst.addOperand(MCOperand::createImm(imm));
1594 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1595
1596 return Success;
1597}
1598
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1599static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1600 uint64_t Addr, const void *Decoder) {
1601 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1602 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1603 imm |= fieldFromInstruction(insn, 29, 2);
1604 const AArch64Disassembler *Dis =
1605 static_cast<const AArch64Disassembler *>(Decoder);
1606
1607 // Sign-extend the 21-bit immediate.
1608 if (imm & (1 << (21 - 1)))
1609 imm |= ~((1LL << 21) - 1);
1610
1611 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1612 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1613 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1614
1615 return Success;
1616}
1617
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1618static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1619 uint64_t Addr, const void *Decoder) {
1620 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1621 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1622 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1623 unsigned S = fieldFromInstruction(insn, 29, 1);
1624 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1625
1626 unsigned ShifterVal = (Imm >> 12) & 3;
1627 unsigned ImmVal = Imm & 0xFFF;
1628 const AArch64Disassembler *Dis =
1629 static_cast<const AArch64Disassembler *>(Decoder);
1630
1631 if (ShifterVal != 0 && ShifterVal != 1)
1632 return Fail;
1633
1634 if (Datasize) {
1635 if (Rd == 31 && !S)
1636 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1637 else
1638 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1639 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1640 } else {
1641 if (Rd == 31 && !S)
1642 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1643 else
1644 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1645 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1646 }
1647
1648 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1649 Inst.addOperand(MCOperand::createImm(ImmVal));
1650 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1651 return Success;
1652}
1653
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1654static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1655 uint64_t Addr,
1656 const void *Decoder) {
1657 int64_t imm = fieldFromInstruction(insn, 0, 26);
1658 const AArch64Disassembler *Dis =
1659 static_cast<const AArch64Disassembler *>(Decoder);
1660
1661 // Sign-extend the 26-bit immediate.
1662 if (imm & (1 << (26 - 1)))
1663 imm |= ~((1LL << 26) - 1);
1664
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]1665 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1666 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1667
1668 return Success;
1669}
1670
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1671static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
1672 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1673 const void *Decoder) {
1674 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1675 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1676 uint64_t crm = fieldFromInstruction(insn, 8, 4);
1677
1678 uint64_t pstate_field = (op1 << 3) | op2;
1679
Oliver Stannard911ea202015-11-26 15:32:30 +0000[diff] [blame]1680 if ((pstate_field == AArch64PState::PAN ||
1681 pstate_field == AArch64PState::UAO) && crm > 1)
Alexandros Lamprineas1bab1912015-10-05 13:42:31 +0000[diff] [blame]1682 return Fail;
1683
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1684 Inst.addOperand(MCOperand::createImm(pstate_field));
1685 Inst.addOperand(MCOperand::createImm(crm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1686
Tim Northovere6ae6762016-07-05 21:23:04 +0000[diff] [blame]1687 const AArch64Disassembler *Dis =
Vladimir Sukhareva98f6892015-04-16 12:15:27 +0000[diff] [blame]1688 static_cast<const AArch64Disassembler *>(Decoder);
Tim Northovere6ae6762016-07-05 21:23:04 +0000[diff] [blame]1689 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field);
1690 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits()))
1691 return Success;
1692 return Fail;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1693}
1694
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1695static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1696 uint64_t Addr, const void *Decoder) {
1697 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1698 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1699 bit |= fieldFromInstruction(insn, 19, 5);
1700 int64_t dst = fieldFromInstruction(insn, 5, 14);
1701 const AArch64Disassembler *Dis =
1702 static_cast<const AArch64Disassembler *>(Decoder);
1703
1704 // Sign-extend 14-bit immediate.
1705 if (dst & (1 << (14 - 1)))
1706 dst |= ~((1LL << 14) - 1);
1707
1708 if (fieldFromInstruction(insn, 31, 1) == 0)
1709 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1710 else
1711 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1712 Inst.addOperand(MCOperand::createImm(bit));
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]1713 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1714 Inst.addOperand(MCOperand::createImm(dst));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1715
1716 return Success;
1717}
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1718
1719static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst,
1720 unsigned RegClassID,
1721 unsigned RegNo,
1722 uint64_t Addr,
1723 const void *Decoder) {
1724 // Register number must be even (see CASP instruction)
1725 if (RegNo & 0x1)
1726 return Fail;
1727
1728 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo);
1729 Inst.addOperand(MCOperand::createReg(Register));
1730 return Success;
1731}
1732
1733static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
1734 unsigned RegNo,
1735 uint64_t Addr,
1736 const void *Decoder) {
Junmo Park45513a82016-07-15 22:42:52 +0000[diff] [blame]1737 return DecodeGPRSeqPairsClassRegisterClass(Inst,
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1738 AArch64::WSeqPairsClassRegClassID,
1739 RegNo, Addr, Decoder);
1740}
1741
1742static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
1743 unsigned RegNo,
1744 uint64_t Addr,
1745 const void *Decoder) {
Junmo Park45513a82016-07-15 22:42:52 +0000[diff] [blame]1746 return DecodeGPRSeqPairsClassRegisterClass(Inst,
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1747 AArch64::XSeqPairsClassRegClassID,
1748 RegNo, Addr, Decoder);
1749}
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]1750
Sander de Smalen81fcf862018-02-06 13:13:21 +0000[diff] [blame]1751static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
1752 uint32_t insn,
1753 uint64_t Addr,
1754 const void *Decoder) {
1755 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1756 unsigned imm = fieldFromInstruction(insn, 5, 13);
1757 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1758 return Fail;
1759
1760 // The same (tied) operand is added twice to the instruction.
1761 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1762 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1763 Inst.addOperand(MCOperand::createImm(imm));
1764 return Success;
1765}
1766
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]1767template<int Bits>
1768static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
1769 uint64_t Address, const void *Decoder) {
1770 if (Imm & ~((1LL << Bits) - 1))
1771 return Fail;
1772
1773 // Imm is a signed immediate, so sign extend it.
1774 if (Imm & (1 << (Bits - 1)))
1775 Imm |= ~((1LL << Bits) - 1);
1776
1777 Inst.addOperand(MCOperand::createImm(Imm));
1778 return Success;
1779}
1780
Sander de Smalen62770792018-05-25 09:47:52 +0000[diff] [blame^]1781// Decode 8-bit signed/unsigned immediate for a given element width.
1782template <int ElementWidth>
1783static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
1784 uint64_t Addr, const void *Decoder) {
1785 unsigned Val = (uint8_t)Imm;
1786 unsigned Shift = (Imm & 0x100) ? 8 : 0;
1787 if (ElementWidth == 8 && Shift)
1788 return Fail;
1789 Inst.addOperand(MCOperand::createImm(Val));
1790 Inst.addOperand(MCOperand::createImm(Shift));
1791 return Success;
1792}