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gerrit-public.fairphone.software / toolchain / llvm-project / bd2cf96c098ed0020f5178eda12cf30d3980d9bd / . / llvm / lib / Support / X86TargetParser.cpp
blob: 0a803d0a6a3c41e940020ec97b4db5f82156da1c [file] [log] [blame]
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]1//===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise X86 hardware features.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/Support/X86TargetParser.h"
14#include "llvm/ADT/StringSwitch.h"
15#include "llvm/ADT/Triple.h"
16
17using namespace llvm;
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]18using namespace llvm::X86;
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]19
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]20namespace {
21
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]22/// Container class for CPU features.
23/// This is a constexpr reimplementation of a subset of std::bitset. It would be
24/// nice to use std::bitset directly, but it doesn't support constant
25/// initialization.
26class FeatureBitset {
27 static constexpr unsigned NUM_FEATURE_WORDS =
28 (X86::CPU_FEATURE_MAX + 31) / 32;
29
30 // This cannot be a std::array, operator[] is not constexpr until C++17.
31 uint32_t Bits[NUM_FEATURE_WORDS] = {};
32
33public:
34 constexpr FeatureBitset() = default;
35 constexpr FeatureBitset(std::initializer_list<unsigned> Init) {
36 for (auto I : Init)
37 set(I);
38 }
39
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]40 bool any() const {
41 return llvm::any_of(Bits, [](uint64_t V) { return V != 0; });
42 }
43
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]44 constexpr FeatureBitset &set(unsigned I) {
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]45 // GCC <6.2 crashes if this is written in a single statement.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]46 uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32));
47 Bits[I / 32] = NewBits;
48 return *this;
49 }
50
51 constexpr bool operator[](unsigned I) const {
52 uint32_t Mask = uint32_t(1) << (I % 32);
53 return (Bits[I / 32] & Mask) != 0;
54 }
55
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]56 constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
57 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
58 // GCC <6.2 crashes if this is written in a single statement.
59 uint32_t NewBits = Bits[I] & RHS.Bits[I];
60 Bits[I] = NewBits;
61 }
62 return *this;
63 }
64
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]65 constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
66 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]67 // GCC <6.2 crashes if this is written in a single statement.
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]68 uint32_t NewBits = Bits[I] | RHS.Bits[I];
69 Bits[I] = NewBits;
70 }
71 return *this;
72 }
73
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]74 // gcc 5.3 miscompiles this if we try to write this using operator&=.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]75 constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
Hans Wennborg9ecda9a2020-07-09 17:47:35 +0200[diff] [blame]76 FeatureBitset Result;
77 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
78 Result.Bits[I] = Bits[I] & RHS.Bits[I];
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]79 return Result;
80 }
81
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]82 // gcc 5.3 miscompiles this if we try to write this using operator&=.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]83 constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
Hans Wennborg9ecda9a2020-07-09 17:47:35 +0200[diff] [blame]84 FeatureBitset Result;
85 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
86 Result.Bits[I] = Bits[I] | RHS.Bits[I];
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]87 return Result;
88 }
89
90 constexpr FeatureBitset operator~() const {
91 FeatureBitset Result;
92 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
93 Result.Bits[I] = ~Bits[I];
94 return Result;
95 }
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]96
97 constexpr bool operator!=(const FeatureBitset &RHS) const {
98 for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
99 if (Bits[I] != RHS.Bits[I])
100 return true;
101 return false;
102 }
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]103};
104
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]105struct ProcInfo {
106 StringLiteral Name;
107 X86::CPUKind Kind;
108 unsigned KeyFeature;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]109 FeatureBitset Features;
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]110};
111
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]112struct FeatureInfo {
113 StringLiteral Name;
114 FeatureBitset ImpliedFeatures;
115};
116
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]117} // end anonymous namespace
118
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]119#define X86_FEATURE(ENUM, STRING) \
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]120 constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]121#include "llvm/Support/X86TargetParser.def"
122
123// Pentium with MMX.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]124constexpr FeatureBitset FeaturesPentiumMMX =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]125 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
126
127// Pentium 2 and 3.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]128constexpr FeatureBitset FeaturesPentium2 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]129 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]130constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]131
132// Pentium 4 CPUs
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]133constexpr FeatureBitset FeaturesPentium4 = FeaturesPentium3 | FeatureSSE2;
134constexpr FeatureBitset FeaturesPrescott = FeaturesPentium4 | FeatureSSE3;
135constexpr FeatureBitset FeaturesNocona =
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]136 FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]137
138// Basic 64-bit capable CPU.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]139constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
Fangrui Song012dd422020-10-12 09:35:22 -0700[diff] [blame]140constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF |
141 FeaturePOPCNT | FeatureSSE4_2 |
142 FeatureCMPXCHG16B;
143constexpr FeatureBitset FeaturesX86_64_V3 =
144 FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C |
145 FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE;
146constexpr FeatureBitset FeaturesX86_64_V4 = FeaturesX86_64_V3 |
147 FeatureAVX512BW | FeatureAVX512CD |
148 FeatureAVX512DQ | FeatureAVX512VL;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]149
150// Intel Core CPUs
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]151constexpr FeatureBitset FeaturesCore2 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]152 FeaturesNocona | FeatureSAHF | FeatureSSSE3;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]153constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
154constexpr FeatureBitset FeaturesNehalem =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]155 FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]156constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL;
157constexpr FeatureBitset FeaturesSandyBridge =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]158 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]159constexpr FeatureBitset FeaturesIvyBridge =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]160 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]161constexpr FeatureBitset FeaturesHaswell =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]162 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
163 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]164constexpr FeatureBitset FeaturesBroadwell =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]165 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
166
167// Intel Knights Landing and Knights Mill
168// Knights Landing has feature parity with Broadwell.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]169constexpr FeatureBitset FeaturesKNL =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]170 FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD |
171 FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]172constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]173
174// Intel Skylake processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]175constexpr FeatureBitset FeaturesSkylakeClient =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]176 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
177 FeatureXSAVES | FeatureSGX;
178// SkylakeServer inherits all SkylakeClient features except SGX.
179// FIXME: That doesn't match gcc.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]180constexpr FeatureBitset FeaturesSkylakeServer =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]181 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD |
182 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB |
183 FeaturePKU;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]184constexpr FeatureBitset FeaturesCascadeLake =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]185 FeaturesSkylakeServer | FeatureAVX512VNNI;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]186constexpr FeatureBitset FeaturesCooperLake =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]187 FeaturesCascadeLake | FeatureAVX512BF16;
188
189// Intel 10nm processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]190constexpr FeatureBitset FeaturesCannonlake =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]191 FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
192 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
193 FeaturePKU | FeatureSHA;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]194constexpr FeatureBitset FeaturesICLClient =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]195 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
196 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI |
197 FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]198constexpr FeatureBitset FeaturesICLServer =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]199 FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]200constexpr FeatureBitset FeaturesTigerlake =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]201 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
Xiang1 Zhang413577a2020-09-30 18:01:15 +0800[diff] [blame]202 FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]203constexpr FeatureBitset FeaturesSapphireRapids =
Freddy Yee02d0812020-08-25 12:27:02 +0800[diff] [blame]204 FeaturesICLServer | FeatureAMX_TILE | FeatureAMX_INT8 | FeatureAMX_BF16 |
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]205 FeatureAVX512BF16 | FeatureAVX512VP2INTERSECT | FeatureCLDEMOTE |
206 FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
Tianqing Wangbe39a6f2020-10-22 16:46:07 +0800[diff] [blame]207 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
208 FeatureWAITPKG;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]209
210// Intel Atom processors.
211// Bonnell has feature parity with Core2 and adds MOVBE.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]212constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]213// Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]214constexpr FeatureBitset FeaturesSilvermont =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]215 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]216constexpr FeatureBitset FeaturesGoldmont =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]217 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
218 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
219 FeatureXSAVEOPT | FeatureXSAVES;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]220constexpr FeatureBitset FeaturesGoldmontPlus =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]221 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]222constexpr FeatureBitset FeaturesTremont =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]223 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
224
225// Geode Processor.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]226constexpr FeatureBitset FeaturesGeode =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]227 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
228
229// K6 processor.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]230constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]231
232// K7 and K8 architecture processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]233constexpr FeatureBitset FeaturesAthlon =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]234 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]235constexpr FeatureBitset FeaturesAthlonXP =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]236 FeaturesAthlon | FeatureFXSR | FeatureSSE;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]237constexpr FeatureBitset FeaturesK8 =
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]238 FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]239constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
240constexpr FeatureBitset FeaturesAMDFAM10 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]241 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]242 FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]243
244// Bobcat architecture processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]245constexpr FeatureBitset FeaturesBTVER1 =
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]246 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]247 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]248 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]249 FeatureSAHF;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]250constexpr FeatureBitset FeaturesBTVER2 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]251 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C |
252 FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
253
254// AMD Bulldozer architecture processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]255constexpr FeatureBitset FeaturesBDVER1 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]256 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]257 FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP |
Douglas Yung56fc6b92020-06-30 18:10:09 -0700[diff] [blame]258 FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW |
259 FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]260 FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]261constexpr FeatureBitset FeaturesBDVER2 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]262 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]263constexpr FeatureBitset FeaturesBDVER3 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]264 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]265constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 |
266 FeatureBMI2 | FeatureMOVBE |
267 FeatureMWAITX | FeatureRDRND;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]268
269// AMD Zen architecture processors.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]270constexpr FeatureBitset FeaturesZNVER1 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]271 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
272 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]273 FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C |
Douglas Yung56fc6b92020-06-30 18:10:09 -0700[diff] [blame]274 FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX |
275 FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
276 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
277 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
Craig Topper7fb3a842020-07-06 22:11:17 -0700[diff] [blame]278 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
Douglas Yung56fc6b92020-06-30 18:10:09 -0700[diff] [blame]279 FeatureXSAVEOPT | FeatureXSAVES;
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]280constexpr FeatureBitset FeaturesZNVER2 =
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]281 FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD;
Benjamin Kramerbd2cf962020-10-24 18:00:20 +0200[diff] [blame^]282static constexpr FeatureBitset FeaturesZNVER3 = FeaturesZNVER2 |
283 FeatureINVPCID | FeaturePKU |
284 FeatureVAES | FeatureVPCLMULQDQ;
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]285
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]286constexpr ProcInfo Processors[] = {
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]287 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
288 { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]289 // i386-generation processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]290 { {"i386"}, CK_i386, ~0U, FeatureX87 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]291 // i486-generation processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]292 { {"i486"}, CK_i486, ~0U, FeatureX87 },
293 { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX },
294 { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW },
295 { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]296 // i586-generation processors, P5 microarchitecture based.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]297 { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B },
298 { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B },
299 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]300 // i686-generation processors, P6 / Pentium M microarchitecture based.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]301 { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B },
302 { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B },
303 { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 },
304 { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 },
305 { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 },
306 { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 },
307 { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 },
308 { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]309 // Netburst microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]310 { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 },
311 { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 },
312 { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott },
313 { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]314 // Core microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]315 { {"core2"}, CK_Core2, ~0U, FeaturesCore2 },
316 { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]317 // Atom processors
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]318 { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
319 { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
320 { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
321 { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
322 { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont },
323 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus },
324 { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]325 // Nehalem microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]326 { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
327 { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]328 // Westmere microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]329 { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]330 // Sandy Bridge microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]331 { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
332 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]333 // Ivy Bridge microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]334 { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
335 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]336 // Haswell microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]337 { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
338 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]339 // Broadwell microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]340 { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]341 // Skylake client microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]342 { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]343 // Skylake server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]344 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
345 { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]346 // Cascadelake Server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]347 { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]348 // Cooperlake Server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]349 { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]350 // Cannonlake client microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]351 { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]352 // Icelake client microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]353 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]354 // Icelake server microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]355 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]356 // Tigerlake microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]357 { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
Freddy Yee02d0812020-08-25 12:27:02 +0800[diff] [blame]358 // Sapphire Rapids microarchitecture based processors.
359 { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]360 // Knights Landing processor.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]361 { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]362 // Knights Mill processor.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]363 { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]364 // Lakemont microarchitecture based processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]365 { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]366 // K6 architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]367 { {"k6"}, CK_K6, ~0U, FeaturesK6 },
368 { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW },
369 { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]370 // K7 architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]371 { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon },
372 { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon },
373 { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
374 { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
375 { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]376 // K8 architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]377 { {"k8"}, CK_K8, ~0U, FeaturesK8 },
378 { {"athlon64"}, CK_K8, ~0U, FeaturesK8 },
379 { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 },
380 { {"opteron"}, CK_K8, ~0U, FeaturesK8 },
381 { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
382 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
383 { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
384 { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
385 { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]386 // Bobcat architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]387 { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 },
388 { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]389 // Bulldozer architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]390 { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 },
391 { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 },
392 { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 },
393 { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]394 // Zen architecture processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]395 { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 },
396 { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 },
Benjamin Kramerbd2cf962020-10-24 18:00:20 +0200[diff] [blame^]397 { {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]398 // Generic 64-bit processor.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]399 { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 },
Fangrui Song012dd422020-10-12 09:35:22 -0700[diff] [blame]400 { {"x86-64-v2"}, CK_x86_64_v2, ~0U, FeaturesX86_64_V2 },
401 { {"x86-64-v3"}, CK_x86_64_v3, ~0U, FeaturesX86_64_V3 },
402 { {"x86-64-v4"}, CK_x86_64_v4, ~0U, FeaturesX86_64_V4 },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]403 // Geode processors.
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]404 { {"geode"}, CK_Geode, ~0U, FeaturesGeode },
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]405};
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]406
Fangrui Song012dd422020-10-12 09:35:22 -0700[diff] [blame]407constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"};
408
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]409X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]410 for (const auto &P : Processors)
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]411 if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit))
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]412 return P.Kind;
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]413
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]414 return CK_None;
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]415}
416
Fangrui Song012dd422020-10-12 09:35:22 -0700[diff] [blame]417X86::CPUKind llvm::X86::parseTuneCPU(StringRef CPU, bool Only64Bit) {
418 if (llvm::is_contained(NoTuneList, CPU))
419 return CK_None;
420 return parseArchX86(CPU, Only64Bit);
421}
422
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]423void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
424 bool Only64Bit) {
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]425 for (const auto &P : Processors)
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]426 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit))
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]427 Values.emplace_back(P.Name);
428}
429
Fangrui Song012dd422020-10-12 09:35:22 -0700[diff] [blame]430void llvm::X86::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values,
431 bool Only64Bit) {
432 for (const ProcInfo &P : Processors)
433 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit) &&
434 !llvm::is_contained(NoTuneList, P.Name))
435 Values.emplace_back(P.Name);
436}
437
Craig Topper8dc92142020-06-24 10:36:02 -0700[diff] [blame]438ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) {
439 // FIXME: Can we avoid a linear search here? The table might be sorted by
440 // CPUKind so we could binary search?
441 for (const auto &P : Processors) {
442 if (P.Kind == Kind) {
443 assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
444 return static_cast<ProcessorFeatures>(P.KeyFeature);
445 }
446 }
447
448 llvm_unreachable("Unable to find CPU kind!");
Craig Topperd5c28c42020-06-09 12:18:08 -0700[diff] [blame]449}
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]450
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]451// Features with no dependencies.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]452constexpr FeatureBitset ImpliedFeatures64BIT = {};
453constexpr FeatureBitset ImpliedFeaturesADX = {};
454constexpr FeatureBitset ImpliedFeaturesBMI = {};
455constexpr FeatureBitset ImpliedFeaturesBMI2 = {};
456constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {};
457constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {};
458constexpr FeatureBitset ImpliedFeaturesCLWB = {};
459constexpr FeatureBitset ImpliedFeaturesCLZERO = {};
460constexpr FeatureBitset ImpliedFeaturesCMOV = {};
461constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {};
462constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {};
463constexpr FeatureBitset ImpliedFeaturesENQCMD = {};
464constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {};
465constexpr FeatureBitset ImpliedFeaturesFXSR = {};
466constexpr FeatureBitset ImpliedFeaturesINVPCID = {};
467constexpr FeatureBitset ImpliedFeaturesLWP = {};
468constexpr FeatureBitset ImpliedFeaturesLZCNT = {};
469constexpr FeatureBitset ImpliedFeaturesMWAITX = {};
470constexpr FeatureBitset ImpliedFeaturesMOVBE = {};
471constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {};
472constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {};
473constexpr FeatureBitset ImpliedFeaturesPCONFIG = {};
474constexpr FeatureBitset ImpliedFeaturesPOPCNT = {};
475constexpr FeatureBitset ImpliedFeaturesPKU = {};
476constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {};
477constexpr FeatureBitset ImpliedFeaturesPRFCHW = {};
478constexpr FeatureBitset ImpliedFeaturesPTWRITE = {};
479constexpr FeatureBitset ImpliedFeaturesRDPID = {};
480constexpr FeatureBitset ImpliedFeaturesRDRND = {};
481constexpr FeatureBitset ImpliedFeaturesRDSEED = {};
482constexpr FeatureBitset ImpliedFeaturesRTM = {};
483constexpr FeatureBitset ImpliedFeaturesSAHF = {};
484constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {};
485constexpr FeatureBitset ImpliedFeaturesSGX = {};
486constexpr FeatureBitset ImpliedFeaturesSHSTK = {};
487constexpr FeatureBitset ImpliedFeaturesTBM = {};
488constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {};
Tianqing Wangbe39a6f2020-10-22 16:46:07 +0800[diff] [blame]489constexpr FeatureBitset ImpliedFeaturesUINTR = {};
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]490constexpr FeatureBitset ImpliedFeaturesWAITPKG = {};
491constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {};
492constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {};
493constexpr FeatureBitset ImpliedFeaturesX87 = {};
494constexpr FeatureBitset ImpliedFeaturesXSAVE = {};
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]495
496// Not really CPU features, but need to be in the table because clang uses
497// target features to communicate them to the backend.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]498constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {};
499constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {};
500constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {};
501constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {};
502constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {};
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]503
504// XSAVE features are dependent on basic XSAVE.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]505constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
506constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
507constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]508
509// MMX->3DNOW->3DNOWA chain.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]510constexpr FeatureBitset ImpliedFeaturesMMX = {};
511constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX;
512constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]513
514// SSE/AVX/AVX512F chain.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]515constexpr FeatureBitset ImpliedFeaturesSSE = {};
516constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
517constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
518constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
519constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
520constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
521constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
522constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
523constexpr FeatureBitset ImpliedFeaturesAVX512F =
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]524 FeatureAVX2 | FeatureF16C | FeatureFMA;
525
526// Vector extensions that build on SSE or AVX.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]527constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
528constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
529constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
530constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
531constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
532constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
533constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
534constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]535
536// AVX512 features.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]537constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
538constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
539constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
540constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
541constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
542constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]543
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]544constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
545constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
546constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
547constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
548constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F;
549constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
550constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
551constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = FeatureAVX512F;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]552
553// FIXME: These two aren't really implemented and just exist in the feature
554// list for __builtin_cpu_supports. So omit their dependencies.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]555constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {};
556constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {};
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]557
558// SSE4_A->FMA4->XOP chain.
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]559constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
560constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
561constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]562
563// AMX Features
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]564constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {};
565constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
566constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
Wang, Pengfei412cdcf2020-10-13 08:42:46 +0800[diff] [blame]567constexpr FeatureBitset ImpliedFeaturesHRESET = {};
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]568
Xiang1 Zhang413577a2020-09-30 18:01:15 +0800[diff] [blame]569// Key Locker Features
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]570constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
571constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
Xiang1 Zhang413577a2020-09-30 18:01:15 +0800[diff] [blame]572
Fangrui Songa8682552020-10-10 14:05:48 -0700[diff] [blame]573constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]574#define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM},
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]575#include "llvm/Support/X86TargetParser.def"
576};
577
578void llvm::X86::getFeaturesForCPU(StringRef CPU,
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]579 SmallVectorImpl<StringRef> &EnabledFeatures) {
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]580 auto I = llvm::find_if(Processors,
581 [&](const ProcInfo &P) { return P.Name == CPU; });
582 assert(I != std::end(Processors) && "Processor not found!");
583
Craig Topperf40b1132020-07-09 14:52:16 -0700[diff] [blame]584 FeatureBitset Bits = I->Features;
585
586 // Remove the 64-bit feature which we only use to validate if a CPU can
587 // be used with 64-bit mode.
588 Bits &= ~Feature64BIT;
589
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]590 // Add the string version of all set bits.
Craig Topper504a1972020-08-06 00:13:40 -0700[diff] [blame]591 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
592 if (Bits[i] && !FeatureInfos[i].Name.empty())
593 EnabledFeatures.push_back(FeatureInfos[i].Name);
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]594}
595
596// For each feature that is (transitively) implied by this feature, set it.
597static void getImpliedEnabledFeatures(FeatureBitset &Bits,
598 const FeatureBitset &Implies) {
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]599 // Fast path: Implies is often empty.
600 if (!Implies.any())
601 return;
602 FeatureBitset Prev;
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]603 Bits |= Implies;
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]604 do {
605 Prev = Bits;
606 for (unsigned i = CPU_FEATURE_MAX; i;)
607 if (Bits[--i])
608 Bits |= FeatureInfos[i].ImpliedFeatures;
609 } while (Prev != Bits);
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]610}
611
612/// Create bit vector of features that are implied disabled if the feature
613/// passed in Value is disabled.
614static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) {
615 // Check all features looking for any dependent on this feature. If we find
616 // one, mark it and recursively find any feature that depend on it.
Fangrui Song0c7af8c2020-08-04 17:50:06 -0700[diff] [blame]617 FeatureBitset Prev;
618 Bits.set(Value);
619 do {
620 Prev = Bits;
621 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
622 if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
623 Bits.set(i);
624 } while (Prev != Bits);
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]625}
626
Craig Topper504a1972020-08-06 00:13:40 -0700[diff] [blame]627void llvm::X86::updateImpliedFeatures(
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]628 StringRef Feature, bool Enabled,
Craig Topper504a1972020-08-06 00:13:40 -0700[diff] [blame]629 StringMap<bool> &Features) {
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]630 auto I = llvm::find_if(
631 FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; });
632 if (I == std::end(FeatureInfos)) {
Craig Topper44ea81a2020-07-07 00:27:50 -0700[diff] [blame]633 // FIXME: This shouldn't happen, but may not have all features in the table
634 // yet.
Craig Topper16f3d692020-07-06 22:47:54 -0700[diff] [blame]635 return;
636 }
637
638 FeatureBitset ImpliedBits;
639 if (Enabled)
640 getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
641 else
642 getImpliedDisabledFeatures(ImpliedBits,
643 std::distance(std::begin(FeatureInfos), I));
644
Craig Topper504a1972020-08-06 00:13:40 -0700[diff] [blame]645 // Update the map entry for all implied features.
646 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
647 if (ImpliedBits[i] && !FeatureInfos[i].Name.empty())
648 Features[FeatureInfos[i].Name] = Enabled;
Craig Topper35379392020-06-30 11:59:03 -0700[diff] [blame]649}