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gerrit-public.fairphone.software / toolchain / llvm-project / d142ab7d080d2153507693c5c175626e02861ee0 / . / llvm / lib / Target / X86 / X86InstrInfo.cpp
blob: 23e641927e374d03471660e6f4c77464e140a0ab [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]2//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]7//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]9//
Chris Lattnerb4d58d72003-01-14 22:00:31 +0000[diff] [blame]10// This file contains the X86 implementation of the TargetInstrInfo class.
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]11//
12//===----------------------------------------------------------------------===//
13
Chris Lattner27d24792002-10-29 21:05:24 +0000[diff] [blame]14#include "X86InstrInfo.h"
Chris Lattner0d808742002-12-03 05:42:53 +0000[diff] [blame]15#include "X86.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]16#include "X86InstrBuilder.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]17#include "X86MachineFunctionInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
Owen Andersone2f23a32007-09-07 04:06:50 +0000[diff] [blame]20#include "llvm/ADT/STLExtras.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]21#include "llvm/CodeGen/LiveVariables.h"
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]22#include "llvm/CodeGen/MachineConstantPool.h"
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]23#include "llvm/CodeGen/MachineDominators.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]24#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]25#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattnera10fff52007-12-31 04:13:23 +0000[diff] [blame]26#include "llvm/CodeGen/MachineRegisterInfo.h"
Andrew Trick153ebe62013-10-31 22:11:56 +0000[diff] [blame]27#include "llvm/CodeGen/StackMaps.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]28#include "llvm/IR/DerivedTypes.h"
Eric Christopher79cc1e32014-09-02 22:28:02 +0000[diff] [blame]29#include "llvm/IR/Function.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]30#include "llvm/IR/LLVMContext.h"
Craig Topperb25fda92012-03-17 18:46:09 +0000[diff] [blame]31#include "llvm/MC/MCAsmInfo.h"
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]32#include "llvm/MC/MCExpr.h"
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]33#include "llvm/MC/MCInst.h"
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]34#include "llvm/Support/CommandLine.h"
David Greened589daf2010-01-05 01:29:29 +0000[diff] [blame]35#include "llvm/Support/Debug.h"
Torok Edwin6dd27302009-07-08 18:01:40 +0000[diff] [blame]36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
Evan Chenge95f3912007-09-25 01:57:46 +0000[diff] [blame]38#include "llvm/Target/TargetOptions.h"
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]39#include <limits>
40
Chandler Carruthd174b722014-04-22 02:03:14 +0000[diff] [blame]41using namespace llvm;
42
Chandler Carruthe96dd892014-04-21 22:55:11 +0000[diff] [blame]43#define DEBUG_TYPE "x86-instr-info"
44
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]45#define GET_INSTRINFO_CTOR_DTOR
Evan Cheng1e210d02011-06-28 20:07:07 +0000[diff] [blame]46#include "X86GenInstrInfo.inc"
47
Chris Lattnera6f074f2009-08-23 03:41:05 +0000[diff] [blame]48static cl::opt<bool>
49NoFusing("disable-spill-fusing",
50 cl::desc("Disable fusing of spill code into instructions"));
51static cl::opt<bool>
52PrintFailedFusing("print-failed-fuse-candidates",
53 cl::desc("Print instructions that the allocator wants to"
54 " fuse, but the X86 backend currently can't"),
55 cl::Hidden);
56static cl::opt<bool>
57ReMatPICStubLoad("remat-pic-stub-load",
58 cl::desc("Re-materialize load from stub in PIC mode"),
59 cl::init(false), cl::Hidden);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]60
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]61enum {
62 // Select which memory operand is being unfolded.
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]63 // (stored in bits 0 - 3)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]64 TB_INDEX_0 = 0,
65 TB_INDEX_1 = 1,
66 TB_INDEX_2 = 2,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]67 TB_INDEX_3 = 3,
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]68 TB_INDEX_4 = 4,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]69 TB_INDEX_MASK = 0xf,
70
71 // Do not insert the reverse map (MemOp -> RegOp) into the table.
72 // This may be needed because there is a many -> one mapping.
73 TB_NO_REVERSE = 1 << 4,
74
75 // Do not insert the forward map (RegOp -> MemOp) into the table.
76 // This is needed for Native Client, which prohibits branch
77 // instructions from using a memory operand.
78 TB_NO_FORWARD = 1 << 5,
79
80 TB_FOLDED_LOAD = 1 << 6,
81 TB_FOLDED_STORE = 1 << 7,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]82
83 // Minimum alignment required for load/store.
84 // Used for RegOp->MemOp conversion.
85 // (stored in bits 8 - 15)
86 TB_ALIGN_SHIFT = 8,
87 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
88 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
89 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]90 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]91 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]92};
93
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]94struct X86OpTblEntry {
95 uint16_t RegOp;
96 uint16_t MemOp;
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]97 uint16_t Flags;
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]98};
99
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]100// Pin the vtable to this file.
101void X86InstrInfo::anchor() {}
102
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]103X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
104 : X86GenInstrInfo(
Pavel Chupinbe9f1212014-09-22 13:11:35 +0000[diff] [blame]105 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32),
106 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)),
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]107 Subtarget(STI), RI(STI) {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]108
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]109 static const X86OpTblEntry OpTbl2Addr[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]110 { X86::ADC32ri, X86::ADC32mi, 0 },
111 { X86::ADC32ri8, X86::ADC32mi8, 0 },
112 { X86::ADC32rr, X86::ADC32mr, 0 },
113 { X86::ADC64ri32, X86::ADC64mi32, 0 },
114 { X86::ADC64ri8, X86::ADC64mi8, 0 },
115 { X86::ADC64rr, X86::ADC64mr, 0 },
116 { X86::ADD16ri, X86::ADD16mi, 0 },
117 { X86::ADD16ri8, X86::ADD16mi8, 0 },
118 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
119 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
120 { X86::ADD16rr, X86::ADD16mr, 0 },
121 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
122 { X86::ADD32ri, X86::ADD32mi, 0 },
123 { X86::ADD32ri8, X86::ADD32mi8, 0 },
124 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
125 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
126 { X86::ADD32rr, X86::ADD32mr, 0 },
127 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
128 { X86::ADD64ri32, X86::ADD64mi32, 0 },
129 { X86::ADD64ri8, X86::ADD64mi8, 0 },
130 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
131 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
132 { X86::ADD64rr, X86::ADD64mr, 0 },
133 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
134 { X86::ADD8ri, X86::ADD8mi, 0 },
135 { X86::ADD8rr, X86::ADD8mr, 0 },
136 { X86::AND16ri, X86::AND16mi, 0 },
137 { X86::AND16ri8, X86::AND16mi8, 0 },
138 { X86::AND16rr, X86::AND16mr, 0 },
139 { X86::AND32ri, X86::AND32mi, 0 },
140 { X86::AND32ri8, X86::AND32mi8, 0 },
141 { X86::AND32rr, X86::AND32mr, 0 },
142 { X86::AND64ri32, X86::AND64mi32, 0 },
143 { X86::AND64ri8, X86::AND64mi8, 0 },
144 { X86::AND64rr, X86::AND64mr, 0 },
145 { X86::AND8ri, X86::AND8mi, 0 },
146 { X86::AND8rr, X86::AND8mr, 0 },
147 { X86::DEC16r, X86::DEC16m, 0 },
148 { X86::DEC32r, X86::DEC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]149 { X86::DEC64r, X86::DEC64m, 0 },
150 { X86::DEC8r, X86::DEC8m, 0 },
151 { X86::INC16r, X86::INC16m, 0 },
152 { X86::INC32r, X86::INC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]153 { X86::INC64r, X86::INC64m, 0 },
154 { X86::INC8r, X86::INC8m, 0 },
155 { X86::NEG16r, X86::NEG16m, 0 },
156 { X86::NEG32r, X86::NEG32m, 0 },
157 { X86::NEG64r, X86::NEG64m, 0 },
158 { X86::NEG8r, X86::NEG8m, 0 },
159 { X86::NOT16r, X86::NOT16m, 0 },
160 { X86::NOT32r, X86::NOT32m, 0 },
161 { X86::NOT64r, X86::NOT64m, 0 },
162 { X86::NOT8r, X86::NOT8m, 0 },
163 { X86::OR16ri, X86::OR16mi, 0 },
164 { X86::OR16ri8, X86::OR16mi8, 0 },
165 { X86::OR16rr, X86::OR16mr, 0 },
166 { X86::OR32ri, X86::OR32mi, 0 },
167 { X86::OR32ri8, X86::OR32mi8, 0 },
168 { X86::OR32rr, X86::OR32mr, 0 },
169 { X86::OR64ri32, X86::OR64mi32, 0 },
170 { X86::OR64ri8, X86::OR64mi8, 0 },
171 { X86::OR64rr, X86::OR64mr, 0 },
172 { X86::OR8ri, X86::OR8mi, 0 },
173 { X86::OR8rr, X86::OR8mr, 0 },
174 { X86::ROL16r1, X86::ROL16m1, 0 },
175 { X86::ROL16rCL, X86::ROL16mCL, 0 },
176 { X86::ROL16ri, X86::ROL16mi, 0 },
177 { X86::ROL32r1, X86::ROL32m1, 0 },
178 { X86::ROL32rCL, X86::ROL32mCL, 0 },
179 { X86::ROL32ri, X86::ROL32mi, 0 },
180 { X86::ROL64r1, X86::ROL64m1, 0 },
181 { X86::ROL64rCL, X86::ROL64mCL, 0 },
182 { X86::ROL64ri, X86::ROL64mi, 0 },
183 { X86::ROL8r1, X86::ROL8m1, 0 },
184 { X86::ROL8rCL, X86::ROL8mCL, 0 },
185 { X86::ROL8ri, X86::ROL8mi, 0 },
186 { X86::ROR16r1, X86::ROR16m1, 0 },
187 { X86::ROR16rCL, X86::ROR16mCL, 0 },
188 { X86::ROR16ri, X86::ROR16mi, 0 },
189 { X86::ROR32r1, X86::ROR32m1, 0 },
190 { X86::ROR32rCL, X86::ROR32mCL, 0 },
191 { X86::ROR32ri, X86::ROR32mi, 0 },
192 { X86::ROR64r1, X86::ROR64m1, 0 },
193 { X86::ROR64rCL, X86::ROR64mCL, 0 },
194 { X86::ROR64ri, X86::ROR64mi, 0 },
195 { X86::ROR8r1, X86::ROR8m1, 0 },
196 { X86::ROR8rCL, X86::ROR8mCL, 0 },
197 { X86::ROR8ri, X86::ROR8mi, 0 },
198 { X86::SAR16r1, X86::SAR16m1, 0 },
199 { X86::SAR16rCL, X86::SAR16mCL, 0 },
200 { X86::SAR16ri, X86::SAR16mi, 0 },
201 { X86::SAR32r1, X86::SAR32m1, 0 },
202 { X86::SAR32rCL, X86::SAR32mCL, 0 },
203 { X86::SAR32ri, X86::SAR32mi, 0 },
204 { X86::SAR64r1, X86::SAR64m1, 0 },
205 { X86::SAR64rCL, X86::SAR64mCL, 0 },
206 { X86::SAR64ri, X86::SAR64mi, 0 },
207 { X86::SAR8r1, X86::SAR8m1, 0 },
208 { X86::SAR8rCL, X86::SAR8mCL, 0 },
209 { X86::SAR8ri, X86::SAR8mi, 0 },
210 { X86::SBB32ri, X86::SBB32mi, 0 },
211 { X86::SBB32ri8, X86::SBB32mi8, 0 },
212 { X86::SBB32rr, X86::SBB32mr, 0 },
213 { X86::SBB64ri32, X86::SBB64mi32, 0 },
214 { X86::SBB64ri8, X86::SBB64mi8, 0 },
215 { X86::SBB64rr, X86::SBB64mr, 0 },
216 { X86::SHL16rCL, X86::SHL16mCL, 0 },
217 { X86::SHL16ri, X86::SHL16mi, 0 },
218 { X86::SHL32rCL, X86::SHL32mCL, 0 },
219 { X86::SHL32ri, X86::SHL32mi, 0 },
220 { X86::SHL64rCL, X86::SHL64mCL, 0 },
221 { X86::SHL64ri, X86::SHL64mi, 0 },
222 { X86::SHL8rCL, X86::SHL8mCL, 0 },
223 { X86::SHL8ri, X86::SHL8mi, 0 },
224 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
225 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
226 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
227 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
228 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
229 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
230 { X86::SHR16r1, X86::SHR16m1, 0 },
231 { X86::SHR16rCL, X86::SHR16mCL, 0 },
232 { X86::SHR16ri, X86::SHR16mi, 0 },
233 { X86::SHR32r1, X86::SHR32m1, 0 },
234 { X86::SHR32rCL, X86::SHR32mCL, 0 },
235 { X86::SHR32ri, X86::SHR32mi, 0 },
236 { X86::SHR64r1, X86::SHR64m1, 0 },
237 { X86::SHR64rCL, X86::SHR64mCL, 0 },
238 { X86::SHR64ri, X86::SHR64mi, 0 },
239 { X86::SHR8r1, X86::SHR8m1, 0 },
240 { X86::SHR8rCL, X86::SHR8mCL, 0 },
241 { X86::SHR8ri, X86::SHR8mi, 0 },
242 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
243 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
244 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
245 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
246 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
247 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
248 { X86::SUB16ri, X86::SUB16mi, 0 },
249 { X86::SUB16ri8, X86::SUB16mi8, 0 },
250 { X86::SUB16rr, X86::SUB16mr, 0 },
251 { X86::SUB32ri, X86::SUB32mi, 0 },
252 { X86::SUB32ri8, X86::SUB32mi8, 0 },
253 { X86::SUB32rr, X86::SUB32mr, 0 },
254 { X86::SUB64ri32, X86::SUB64mi32, 0 },
255 { X86::SUB64ri8, X86::SUB64mi8, 0 },
256 { X86::SUB64rr, X86::SUB64mr, 0 },
257 { X86::SUB8ri, X86::SUB8mi, 0 },
258 { X86::SUB8rr, X86::SUB8mr, 0 },
259 { X86::XOR16ri, X86::XOR16mi, 0 },
260 { X86::XOR16ri8, X86::XOR16mi8, 0 },
261 { X86::XOR16rr, X86::XOR16mr, 0 },
262 { X86::XOR32ri, X86::XOR32mi, 0 },
263 { X86::XOR32ri8, X86::XOR32mi8, 0 },
264 { X86::XOR32rr, X86::XOR32mr, 0 },
265 { X86::XOR64ri32, X86::XOR64mi32, 0 },
266 { X86::XOR64ri8, X86::XOR64mi8, 0 },
267 { X86::XOR64rr, X86::XOR64mr, 0 },
268 { X86::XOR8ri, X86::XOR8mi, 0 },
269 { X86::XOR8rr, X86::XOR8mr, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]270 };
271
272 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]273 unsigned RegOp = OpTbl2Addr[i].RegOp;
274 unsigned MemOp = OpTbl2Addr[i].MemOp;
275 unsigned Flags = OpTbl2Addr[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]276 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
277 RegOp, MemOp,
278 // Index 0, folded load and store, no alignment requirement.
279 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]280 }
281
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]282 static const X86OpTblEntry OpTbl0[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]283 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
284 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
285 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
286 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
287 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]288 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
289 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
290 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
291 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
292 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
293 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
294 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
295 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
296 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
297 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
298 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
299 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
300 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
301 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
302 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]303 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]304 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
305 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
306 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
307 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
308 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
309 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
310 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
311 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
312 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
313 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
314 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
315 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
316 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
317 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
318 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
319 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
320 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
321 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
322 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
323 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
324 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
325 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]326 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
327 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
328 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
329 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
330 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
331 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]332 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
333 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
334 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
335 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]336 { X86::PEXTRDrr, X86::PEXTRDmr, TB_FOLDED_STORE },
337 { X86::PEXTRQrr, X86::PEXTRQmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]338 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
339 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
340 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
341 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
342 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
343 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
344 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
345 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
346 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
347 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
348 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
349 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
350 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
351 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
352 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
353 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
354 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
355 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
Reid Klecknera580b6e2015-01-30 21:03:31 +0000[diff] [blame]356 { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]357 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
358 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
359 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]360 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame^]361
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]362 // AVX 128-bit versions of foldable instructions
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]363 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]364 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]365 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
366 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
367 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
368 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
369 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
370 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
371 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
372 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
373 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]374 { X86::VPEXTRDrr, X86::VPEXTRDmr, TB_FOLDED_STORE },
375 { X86::VPEXTRQrr, X86::VPEXTRQmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame^]376
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]377 // AVX 256-bit foldable instructions
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]378 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]379 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
380 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
381 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
382 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]383 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame^]384
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]385 // AVX-512 foldable instructions
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]386 { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
387 { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
388 { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
389 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
390 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
391 { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE },
392 { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]393 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE },
394 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]395 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]396 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame^]397
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]398 // AVX-512 foldable instructions (256-bit versions)
399 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
400 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
401 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
402 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
403 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE },
404 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE },
405 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE },
406 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE },
407 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE },
408 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame^]409
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]410 // AVX-512 foldable instructions (128-bit versions)
411 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
412 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
413 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
414 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
415 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE },
416 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE },
417 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE },
418 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE },
419 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]420 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame^]421
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]422 // F16C foldable instructions
423 { X86::VCVTPS2PHrr, X86::VCVTPS2PHmr, TB_FOLDED_STORE },
424 { X86::VCVTPS2PHYrr, X86::VCVTPS2PHYmr, TB_FOLDED_STORE }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]425 };
426
427 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]428 unsigned RegOp = OpTbl0[i].RegOp;
429 unsigned MemOp = OpTbl0[i].MemOp;
430 unsigned Flags = OpTbl0[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]431 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
432 RegOp, MemOp, TB_INDEX_0 | Flags);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]433 }
434
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]435 static const X86OpTblEntry OpTbl1[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]436 { X86::CMP16rr, X86::CMP16rm, 0 },
437 { X86::CMP32rr, X86::CMP32rm, 0 },
438 { X86::CMP64rr, X86::CMP64rm, 0 },
439 { X86::CMP8rr, X86::CMP8rm, 0 },
440 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
441 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
442 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
443 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
444 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
445 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
446 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
447 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
448 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
449 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]450 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
451 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
452 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
453 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
454 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
455 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
456 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
457 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]458 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
459 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]460 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
461 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]462 { X86::CVTDQ2PDrr, X86::CVTDQ2PDrm, TB_ALIGN_16 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]463 { X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]464 { X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]465 { X86::CVTPD2PSrr, X86::CVTPD2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]466 { X86::CVTPS2DQrr, X86::CVTPS2DQrm, TB_ALIGN_16 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]467 { X86::CVTPS2PDrr, X86::CVTPS2PDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]468 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
469 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
470 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
471 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
472 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
473 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
474 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
475 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]476 { X86::MOV16rr, X86::MOV16rm, 0 },
477 { X86::MOV32rr, X86::MOV32rm, 0 },
478 { X86::MOV64rr, X86::MOV64rm, 0 },
479 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
480 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
481 { X86::MOV8rr, X86::MOV8rm, 0 },
482 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
483 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]484 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
485 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
486 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
487 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]488 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
489 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
490 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
491 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
492 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
493 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
494 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
495 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
496 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
497 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]498 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
499 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
500 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
501 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
502 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
503 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]504 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
505 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
506 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]507 { X86::PCMPESTRIrr, X86::PCMPESTRIrm, TB_ALIGN_16 },
508 { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm, TB_ALIGN_16 },
509 { X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 },
510 { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm, TB_ALIGN_16 },
511 { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128, TB_ALIGN_16 },
512 { X86::PMOVSXBDrr, X86::PMOVSXBDrm, TB_ALIGN_16 },
513 { X86::PMOVSXBQrr, X86::PMOVSXBQrm, TB_ALIGN_16 },
514 { X86::PMOVSXBWrr, X86::PMOVSXBWrm, TB_ALIGN_16 },
515 { X86::PMOVSXDQrr, X86::PMOVSXDQrm, TB_ALIGN_16 },
516 { X86::PMOVSXWDrr, X86::PMOVSXWDrm, TB_ALIGN_16 },
517 { X86::PMOVSXWQrr, X86::PMOVSXWQrm, TB_ALIGN_16 },
518 { X86::PMOVZXBDrr, X86::PMOVZXBDrm, TB_ALIGN_16 },
519 { X86::PMOVZXBQrr, X86::PMOVZXBQrm, TB_ALIGN_16 },
520 { X86::PMOVZXBWrr, X86::PMOVZXBWrm, TB_ALIGN_16 },
521 { X86::PMOVZXDQrr, X86::PMOVZXDQrm, TB_ALIGN_16 },
522 { X86::PMOVZXWDrr, X86::PMOVZXWDrm, TB_ALIGN_16 },
523 { X86::PMOVZXWQrr, X86::PMOVZXWQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]524 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
525 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
526 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]527 { X86::PTESTrr, X86::PTESTrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]528 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
529 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]530 { X86::ROUNDPDr, X86::ROUNDPDm, TB_ALIGN_16 },
531 { X86::ROUNDPSr, X86::ROUNDPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]532 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
533 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 },
534 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
535 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
536 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]537 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]538 { X86::SQRTSDr, X86::SQRTSDm, 0 },
539 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
540 { X86::SQRTSSr, X86::SQRTSSm, 0 },
541 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
542 { X86::TEST16rr, X86::TEST16rm, 0 },
543 { X86::TEST32rr, X86::TEST32rm, 0 },
544 { X86::TEST64rr, X86::TEST64rm, 0 },
545 { X86::TEST8rr, X86::TEST8rm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]546 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]547 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
548 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame^]549
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]550 // AVX 128-bit versions of foldable instructions
551 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
552 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]553 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
554 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]555 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
556 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
Pete Cooper8bbce762012-06-14 22:12:58 +0000[diff] [blame]557 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]558 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
559 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
560 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
561 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
562 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
563 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
564 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
565 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
566 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]567 { X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]568 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]569 { X86::VCVTPD2DQrr, X86::VCVTPD2DQXrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]570 { X86::VCVTPD2PSrr, X86::VCVTPD2PSXrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]571 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]572 { X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]573 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
574 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]575 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
576 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
577 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
578 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
579 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
580 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
581 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
582 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]583 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, 0 },
584 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, 0 },
Craig Topperb2922162012-12-26 02:14:19 +0000[diff] [blame]585 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]586 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]587 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
588 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]589 { X86::VPABSBrr128, X86::VPABSBrm128, 0 },
590 { X86::VPABSDrr128, X86::VPABSDrm128, 0 },
591 { X86::VPABSWrr128, X86::VPABSWrm128, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]592 { X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 },
593 { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 },
594 { X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 },
595 { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 },
596 { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]597 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
598 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]599 { X86::VPMOVSXBDrr, X86::VPMOVSXBDrm, 0 },
600 { X86::VPMOVSXBQrr, X86::VPMOVSXBQrm, 0 },
601 { X86::VPMOVSXBWrr, X86::VPMOVSXBWrm, 0 },
602 { X86::VPMOVSXDQrr, X86::VPMOVSXDQrm, 0 },
603 { X86::VPMOVSXWDrr, X86::VPMOVSXWDrm, 0 },
604 { X86::VPMOVSXWQrr, X86::VPMOVSXWQrm, 0 },
605 { X86::VPMOVZXBDrr, X86::VPMOVZXBDrm, 0 },
606 { X86::VPMOVZXBQrr, X86::VPMOVZXBQrm, 0 },
607 { X86::VPMOVZXBWrr, X86::VPMOVZXBWrm, 0 },
608 { X86::VPMOVZXDQrr, X86::VPMOVZXDQrm, 0 },
609 { X86::VPMOVZXWDrr, X86::VPMOVZXWDrm, 0 },
610 { X86::VPMOVZXWQrr, X86::VPMOVZXWQrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]611 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
612 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
613 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]614 { X86::VPTESTrr, X86::VPTESTrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]615 { X86::VRCPPSr, X86::VRCPPSm, 0 },
616 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]617 { X86::VROUNDPDr, X86::VROUNDPDm, 0 },
618 { X86::VROUNDPSr, X86::VROUNDPSm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]619 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
620 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, 0 },
621 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]622 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]623 { X86::VTESTPDrr, X86::VTESTPDrm, 0 },
624 { X86::VTESTPSrr, X86::VTESTPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]625 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]626 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]627
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]628 // AVX 256-bit foldable instructions
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]629 { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]630 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]631 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]632 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]633 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]634 { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]635 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 },
636 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]637 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
638 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]639 { X86::VMOVDDUPYrr, X86::VMOVDDUPYrm, 0 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]640 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]641 { X86::VMOVSLDUPYrr, X86::VMOVSLDUPYrm, 0 },
642 { X86::VMOVSHDUPYrr, X86::VMOVSHDUPYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]643 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]644 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]645 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
646 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
Simon Pilgrima2618672015-02-07 21:44:06 +0000[diff] [blame]647 { X86::VPTESTYrr, X86::VPTESTYrm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]648 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
649 { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]650 { X86::VROUNDYPDr, X86::VROUNDYPDm, 0 },
651 { X86::VROUNDYPSr, X86::VROUNDYPSm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]652 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]653 { X86::VRSQRTPSYr_Int, X86::VRSQRTPSYm_Int, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]654 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
655 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]656 { X86::VTESTPDYrr, X86::VTESTPDYrm, 0 },
657 { X86::VTESTPSYrr, X86::VTESTPSYrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]658
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]659 // AVX2 foldable instructions
Simon Pilgrimd11b0132015-02-08 17:13:54 +0000[diff] [blame]660 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
661 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
662 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]663 { X86::VPABSBrr256, X86::VPABSBrm256, 0 },
664 { X86::VPABSDrr256, X86::VPABSDrm256, 0 },
665 { X86::VPABSWrr256, X86::VPABSWrm256, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame^]666 { X86::VPBROADCASTBrr, X86::VPBROADCASTBrm, 0 },
667 { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm, 0 },
668 { X86::VPBROADCASTDrr, X86::VPBROADCASTDrm, 0 },
669 { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm, 0 },
670 { X86::VPBROADCASTQrr, X86::VPBROADCASTQrm, 0 },
671 { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm, 0 },
672 { X86::VPBROADCASTWrr, X86::VPBROADCASTWrm, 0 },
673 { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm, 0 },
674 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
675 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
676 { X86::VPMOVSXBDYrr, X86::VPMOVSXBDYrm, 0 },
677 { X86::VPMOVSXBQYrr, X86::VPMOVSXBQYrm, 0 },
678 { X86::VPMOVSXBWYrr, X86::VPMOVSXBWYrm, 0 },
679 { X86::VPMOVSXDQYrr, X86::VPMOVSXDQYrm, 0 },
680 { X86::VPMOVSXWDYrr, X86::VPMOVSXWDYrm, 0 },
681 { X86::VPMOVSXWQYrr, X86::VPMOVSXWQYrm, 0 },
682 { X86::VPMOVZXBDYrr, X86::VPMOVZXBDYrm, 0 },
683 { X86::VPMOVZXBQYrr, X86::VPMOVZXBQYrm, 0 },
684 { X86::VPMOVZXBWYrr, X86::VPMOVZXBWYrm, 0 },
685 { X86::VPMOVZXDQYrr, X86::VPMOVZXDQYrm, 0 },
686 { X86::VPMOVZXWDYrr, X86::VPMOVZXWDYrm, 0 },
687 { X86::VPMOVZXWQYrr, X86::VPMOVZXWQYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]688 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
689 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
690 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]691
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]692 // XOP foldable instructions
693 { X86::VFRCZPDrr, X86::VFRCZPDrm, 0 },
694 { X86::VFRCZPDrrY, X86::VFRCZPDrmY, 0 },
695 { X86::VFRCZPSrr, X86::VFRCZPSrm, 0 },
696 { X86::VFRCZPSrrY, X86::VFRCZPSrmY, 0 },
697 { X86::VFRCZSDrr, X86::VFRCZSDrm, 0 },
698 { X86::VFRCZSSrr, X86::VFRCZSSrm, 0 },
699 { X86::VPHADDBDrr, X86::VPHADDBDrm, 0 },
700 { X86::VPHADDBQrr, X86::VPHADDBQrm, 0 },
701 { X86::VPHADDBWrr, X86::VPHADDBWrm, 0 },
702 { X86::VPHADDDQrr, X86::VPHADDDQrm, 0 },
703 { X86::VPHADDWDrr, X86::VPHADDWDrm, 0 },
704 { X86::VPHADDWQrr, X86::VPHADDWQrm, 0 },
705 { X86::VPHADDUBDrr, X86::VPHADDUBDrm, 0 },
706 { X86::VPHADDUBQrr, X86::VPHADDUBQrm, 0 },
707 { X86::VPHADDUBWrr, X86::VPHADDUBWrm, 0 },
708 { X86::VPHADDUDQrr, X86::VPHADDUDQrm, 0 },
709 { X86::VPHADDUWDrr, X86::VPHADDUWDrm, 0 },
710 { X86::VPHADDUWQrr, X86::VPHADDUWQrm, 0 },
711 { X86::VPHSUBBWrr, X86::VPHSUBBWrm, 0 },
712 { X86::VPHSUBDQrr, X86::VPHSUBDQrm, 0 },
713 { X86::VPHSUBWDrr, X86::VPHSUBWDrm, 0 },
714 { X86::VPROTBri, X86::VPROTBmi, 0 },
715 { X86::VPROTBrr, X86::VPROTBmr, 0 },
716 { X86::VPROTDri, X86::VPROTDmi, 0 },
717 { X86::VPROTDrr, X86::VPROTDmr, 0 },
718 { X86::VPROTQri, X86::VPROTQmi, 0 },
719 { X86::VPROTQrr, X86::VPROTQmr, 0 },
720 { X86::VPROTWri, X86::VPROTWmi, 0 },
721 { X86::VPROTWrr, X86::VPROTWmr, 0 },
722 { X86::VPSHABrr, X86::VPSHABmr, 0 },
723 { X86::VPSHADrr, X86::VPSHADmr, 0 },
724 { X86::VPSHAQrr, X86::VPSHAQmr, 0 },
725 { X86::VPSHAWrr, X86::VPSHAWmr, 0 },
726 { X86::VPSHLBrr, X86::VPSHLBmr, 0 },
727 { X86::VPSHLDrr, X86::VPSHLDmr, 0 },
728 { X86::VPSHLQrr, X86::VPSHLQmr, 0 },
729 { X86::VPSHLWrr, X86::VPSHLWmr, 0 },
730
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]731 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]732 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
733 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]734 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
735 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
736 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
737 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
738 { X86::BLCI32rr, X86::BLCI32rm, 0 },
739 { X86::BLCI64rr, X86::BLCI64rm, 0 },
740 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
741 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
742 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
743 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
744 { X86::BLCS32rr, X86::BLCS32rm, 0 },
745 { X86::BLCS64rr, X86::BLCS64rm, 0 },
746 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
747 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]748 { X86::BLSI32rr, X86::BLSI32rm, 0 },
749 { X86::BLSI64rr, X86::BLSI64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]750 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
751 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]752 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
753 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
754 { X86::BLSR32rr, X86::BLSR32rm, 0 },
755 { X86::BLSR64rr, X86::BLSR64rm, 0 },
756 { X86::BZHI32rr, X86::BZHI32rm, 0 },
757 { X86::BZHI64rr, X86::BZHI64rm, 0 },
758 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
759 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
760 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
761 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
762 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
763 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]764 { X86::RORX32ri, X86::RORX32mi, 0 },
765 { X86::RORX64ri, X86::RORX64mi, 0 },
Michael Liao2b425e12012-09-26 08:26:25 +0000[diff] [blame]766 { X86::SARX32rr, X86::SARX32rm, 0 },
767 { X86::SARX64rr, X86::SARX64rm, 0 },
768 { X86::SHRX32rr, X86::SHRX32rm, 0 },
769 { X86::SHRX64rr, X86::SHRX64rm, 0 },
770 { X86::SHLX32rr, X86::SHLX32rm, 0 },
771 { X86::SHLX64rr, X86::SHLX64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]772 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
773 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]774 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
775 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
776 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]777 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
778 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]779
780 // AVX-512 foldable instructions
781 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
782 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]783 { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 },
784 { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 },
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]785 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 },
786 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]787 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 },
788 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 },
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]789 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
790 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]791 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
792 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]793 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
794 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]795 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE },
796 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame^]797
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]798 // AVX-512 foldable instructions (256-bit versions)
799 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 },
800 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 },
801 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm, TB_ALIGN_32 },
802 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm, TB_ALIGN_32 },
803 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 },
804 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 },
805 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 },
806 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
807 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
808 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]809 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
810 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame^]811
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]812 // AVX-512 foldable instructions (256-bit versions)
813 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 },
814 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 },
815 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm, TB_ALIGN_16 },
816 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm, TB_ALIGN_16 },
817 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 },
818 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 },
819 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 },
820 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
821 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
822 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]823 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]824
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]825 // F16C foldable instructions
826 { X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, 0 },
827 { X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]828
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]829 // AES foldable instructions
830 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
831 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
832 { X86::VAESIMCrr, X86::VAESIMCrm, TB_ALIGN_16 },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]833 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, TB_ALIGN_16 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]834 };
835
836 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]837 unsigned RegOp = OpTbl1[i].RegOp;
838 unsigned MemOp = OpTbl1[i].MemOp;
839 unsigned Flags = OpTbl1[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]840 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
841 RegOp, MemOp,
842 // Index 1, folded load
843 Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]844 }
845
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]846 static const X86OpTblEntry OpTbl2[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]847 { X86::ADC32rr, X86::ADC32rm, 0 },
848 { X86::ADC64rr, X86::ADC64rm, 0 },
849 { X86::ADD16rr, X86::ADD16rm, 0 },
850 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
851 { X86::ADD32rr, X86::ADD32rm, 0 },
852 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
853 { X86::ADD64rr, X86::ADD64rm, 0 },
854 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
855 { X86::ADD8rr, X86::ADD8rm, 0 },
856 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
857 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
858 { X86::ADDSDrr, X86::ADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]859 { X86::ADDSDrr_Int, X86::ADDSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]860 { X86::ADDSSrr, X86::ADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]861 { X86::ADDSSrr_Int, X86::ADDSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]862 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
863 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
864 { X86::AND16rr, X86::AND16rm, 0 },
865 { X86::AND32rr, X86::AND32rm, 0 },
866 { X86::AND64rr, X86::AND64rm, 0 },
867 { X86::AND8rr, X86::AND8rm, 0 },
868 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
869 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
870 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
871 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]872 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
873 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
874 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
875 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]876 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
877 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
878 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
879 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
880 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
881 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
882 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
883 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
884 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
885 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
886 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
887 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
888 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
889 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
890 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
891 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
892 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
893 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
894 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
895 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
896 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
897 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
898 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
899 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
900 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
901 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
902 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
903 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
904 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
905 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
906 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
907 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
908 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
909 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
910 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
911 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
912 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
913 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
914 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
915 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
916 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
917 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
918 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
919 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
920 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
921 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
922 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
923 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
924 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
925 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
926 { X86::CMPSDrr, X86::CMPSDrm, 0 },
927 { X86::CMPSSrr, X86::CMPSSrm, 0 },
928 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
929 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
930 { X86::DIVSDrr, X86::DIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]931 { X86::DIVSDrr_Int, X86::DIVSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]932 { X86::DIVSSrr, X86::DIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]933 { X86::DIVSSrr_Int, X86::DIVSSrm_Int, 0 },
934 { X86::DPPDrri, X86::DPPDrmi, TB_ALIGN_16 },
935 { X86::DPPSrri, X86::DPPSrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]936 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 },
937 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 },
938 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 },
939 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 },
940 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 },
941 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 },
942 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 },
943 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 },
944 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
945 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
946 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
947 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
948 { X86::IMUL16rr, X86::IMUL16rm, 0 },
949 { X86::IMUL32rr, X86::IMUL32rm, 0 },
950 { X86::IMUL64rr, X86::IMUL64rm, 0 },
951 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
952 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
Manman Ren959acb12012-08-13 18:29:41 +0000[diff] [blame]953 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
954 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
955 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
956 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
957 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
958 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]959 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]960 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]961 { X86::MAXSDrr, X86::MAXSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]962 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]963 { X86::MAXSSrr, X86::MAXSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]964 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]965 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]966 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]967 { X86::MINSDrr, X86::MINSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]968 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]969 { X86::MINSSrr, X86::MINSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]970 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]971 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]972 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
973 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
974 { X86::MULSDrr, X86::MULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]975 { X86::MULSDrr_Int, X86::MULSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]976 { X86::MULSSrr, X86::MULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]977 { X86::MULSSrr_Int, X86::MULSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]978 { X86::OR16rr, X86::OR16rm, 0 },
979 { X86::OR32rr, X86::OR32rm, 0 },
980 { X86::OR64rr, X86::OR64rm, 0 },
981 { X86::OR8rr, X86::OR8rm, 0 },
982 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
983 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
984 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
985 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]986 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]987 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
988 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
989 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
990 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
991 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
992 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]993 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
994 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]995 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]996 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]997 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
998 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
999 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
1000 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1001 { X86::PBLENDVBrr0, X86::PBLENDVBrm0, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1002 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1003 { X86::PCLMULQDQrr, X86::PCLMULQDQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1004 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
1005 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1006 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1007 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
1008 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
1009 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1010 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1011 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1012 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
1013 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1014 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1015 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1016 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1017 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1018 { X86::PINSRBrr, X86::PINSRBrm, 0 },
1019 { X86::PINSRDrr, X86::PINSRDrm, 0 },
1020 { X86::PINSRQrr, X86::PINSRQrm, 0 },
1021 { X86::PINSRWrri, X86::PINSRWrmi, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1022 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1023 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
1024 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
1025 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
1026 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
1027 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
Benjamin Kramer4669d182012-12-21 14:04:55 +0000[diff] [blame]1028 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
1029 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
1030 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
1031 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
1032 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
1033 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
1034 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
1035 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1036 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1037 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1038 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
1039 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
1040 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
1041 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
1042 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
1043 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
1044 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]1045 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
1046 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 },
1047 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 },
1048 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1049 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
1050 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
1051 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
1052 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
1053 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
1054 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
1055 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
1056 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
1057 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
1058 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1059 { X86::PSUBQrr, X86::PSUBQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1060 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
1061 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1062 { X86::PSUBUSBrr, X86::PSUBUSBrm, TB_ALIGN_16 },
1063 { X86::PSUBUSWrr, X86::PSUBUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1064 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
1065 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
1066 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
1067 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
1068 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
1069 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
1070 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
1071 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
1072 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
1073 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
1074 { X86::SBB32rr, X86::SBB32rm, 0 },
1075 { X86::SBB64rr, X86::SBB64rm, 0 },
1076 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
1077 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
1078 { X86::SUB16rr, X86::SUB16rm, 0 },
1079 { X86::SUB32rr, X86::SUB32rm, 0 },
1080 { X86::SUB64rr, X86::SUB64rm, 0 },
1081 { X86::SUB8rr, X86::SUB8rm, 0 },
1082 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
1083 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
1084 { X86::SUBSDrr, X86::SUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1085 { X86::SUBSDrr_Int, X86::SUBSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1086 { X86::SUBSSrr, X86::SUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1087 { X86::SUBSSrr_Int, X86::SUBSSrm_Int, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1088 // FIXME: TEST*rr -> swapped operand of TEST*mr.
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1089 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
1090 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
1091 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
1092 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
1093 { X86::XOR16rr, X86::XOR16rm, 0 },
1094 { X86::XOR32rr, X86::XOR32rm, 0 },
1095 { X86::XOR64rr, X86::XOR64rm, 0 },
1096 { X86::XOR8rr, X86::XOR8rm, 0 },
1097 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1098 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1099
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1100 // AVX 128-bit versions of foldable instructions
1101 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
1102 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
1103 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
1104 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
1105 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
1106 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
1107 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
1108 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
1109 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
1110 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
Craig Toppercaef1c52012-12-26 00:35:47 +0000[diff] [blame]1111 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
1112 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1113 { X86::VRCPSSr, X86::VRCPSSm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1114 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
1115 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
1116 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1117 { X86::VADDPDrr, X86::VADDPDrm, 0 },
1118 { X86::VADDPSrr, X86::VADDPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1119 { X86::VADDSDrr, X86::VADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1120 { X86::VADDSDrr_Int, X86::VADDSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1121 { X86::VADDSSrr, X86::VADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1122 { X86::VADDSSrr_Int, X86::VADDSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1123 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
1124 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
1125 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
1126 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
1127 { X86::VANDPDrr, X86::VANDPDrm, 0 },
1128 { X86::VANDPSrr, X86::VANDPSrm, 0 },
1129 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
1130 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
1131 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
1132 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
1133 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
1134 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1135 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
1136 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1137 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
1138 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1139 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1140 { X86::VDIVSDrr_Int, X86::VDIVSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1141 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1142 { X86::VDIVSSrr_Int, X86::VDIVSSrm_Int, 0 },
1143 { X86::VDPPDrri, X86::VDPPDrmi, 0 },
1144 { X86::VDPPSrri, X86::VDPPSrmi, 0 },
Craig Topperf7e92f12015-02-10 05:10:50 +0000[diff] [blame]1145 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, 0 },
1146 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, 0 },
1147 { X86::VFsANDPDrr, X86::VFsANDPDrm, 0 },
1148 { X86::VFsANDPSrr, X86::VFsANDPSrm, 0 },
1149 { X86::VFsORPDrr, X86::VFsORPDrm, 0 },
1150 { X86::VFsORPSrr, X86::VFsORPSrm, 0 },
1151 { X86::VFsXORPDrr, X86::VFsXORPDrm, 0 },
1152 { X86::VFsXORPSrr, X86::VFsXORPSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1153 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
1154 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
1155 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
1156 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1157 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
1158 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1159 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1160 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1161 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1162 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1163 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1164 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1165 { X86::VMINPDrr, X86::VMINPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1166 { X86::VMINPSrr, X86::VMINPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1167 { X86::VMINSDrr, X86::VMINSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1168 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1169 { X86::VMINSSrr, X86::VMINSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1170 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1171 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
1172 { X86::VMULPDrr, X86::VMULPDrm, 0 },
1173 { X86::VMULPSrr, X86::VMULPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1174 { X86::VMULSDrr, X86::VMULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1175 { X86::VMULSDrr_Int, X86::VMULSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1176 { X86::VMULSSrr, X86::VMULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1177 { X86::VMULSSrr_Int, X86::VMULSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1178 { X86::VORPDrr, X86::VORPDrm, 0 },
1179 { X86::VORPSrr, X86::VORPSrm, 0 },
1180 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
1181 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
1182 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
1183 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
1184 { X86::VPADDBrr, X86::VPADDBrm, 0 },
1185 { X86::VPADDDrr, X86::VPADDDrm, 0 },
1186 { X86::VPADDQrr, X86::VPADDQrm, 0 },
1187 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
1188 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
1189 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
1190 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
1191 { X86::VPADDWrr, X86::VPADDWrm, 0 },
1192 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, 0 },
1193 { X86::VPANDNrr, X86::VPANDNrm, 0 },
1194 { X86::VPANDrr, X86::VPANDrm, 0 },
1195 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
1196 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1197 { X86::VPBLENDVBrr, X86::VPBLENDVBrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1198 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1199 { X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1200 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
1201 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
1202 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
1203 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
1204 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
1205 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
1206 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
1207 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
1208 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
1209 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
1210 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
1211 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
1212 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
1213 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
1214 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
1215 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1216 { X86::VPINSRBrr, X86::VPINSRBrm, 0 },
1217 { X86::VPINSRDrr, X86::VPINSRDrm, 0 },
1218 { X86::VPINSRQrr, X86::VPINSRQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1219 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
1220 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
1221 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
1222 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
1223 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
1224 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
1225 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
1226 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
1227 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
1228 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
1229 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
1230 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
1231 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
1232 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
1233 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
1234 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
1235 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
1236 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
1237 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
1238 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
1239 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
1240 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
1241 { X86::VPORrr, X86::VPORrm, 0 },
1242 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
1243 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
1244 { X86::VPSIGNBrr, X86::VPSIGNBrm, 0 },
1245 { X86::VPSIGNWrr, X86::VPSIGNWrm, 0 },
1246 { X86::VPSIGNDrr, X86::VPSIGNDrm, 0 },
1247 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
1248 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
1249 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
1250 { X86::VPSRADrr, X86::VPSRADrm, 0 },
1251 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
1252 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
1253 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
1254 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1255 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1256 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1257 { X86::VPSUBQrr, X86::VPSUBQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1258 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1259 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1260 { X86::VPSUBUSBrr, X86::VPSUBUSBrm, 0 },
1261 { X86::VPSUBUSWrr, X86::VPSUBUSWrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1262 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1263 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1264 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1265 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1266 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1267 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1268 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1269 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1270 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1271 { X86::VPXORrr, X86::VPXORrm, 0 },
1272 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1273 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1274 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1275 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1276 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1277 { X86::VSUBSDrr_Int, X86::VSUBSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1278 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1279 { X86::VSUBSSrr_Int, X86::VSUBSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1280 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1281 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1282 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1283 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1284 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1285 { X86::VXORPSrr, X86::VXORPSrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1286
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1287 // AVX 256-bit foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1288 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1289 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1290 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1291 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1292 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1293 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1294 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1295 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1296 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1297 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1298 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1299 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1300 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1301 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1302 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1303 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1304 { X86::VDPPSYrri, X86::VDPPSYrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1305 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1306 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1307 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1308 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1309 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1310 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1311 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1312 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1313 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1314 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1315 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1316 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1317 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1318 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1319 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1320 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1321 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1322 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1323 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1324 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1325 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1326 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1327 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1328 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1329 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1330 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1331
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1332 // AVX2 foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1333 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1334 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1335 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1336 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1337 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1338 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1339 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1340 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1341 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1342 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1343 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1344 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1345 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
1346 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, 0 },
1347 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1348 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1349 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1350 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1351 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1352 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame^]1353 { X86::VPBLENDVBYrr, X86::VPBLENDVBYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1354 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1355 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1356 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1357 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1358 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1359 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1360 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1361 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1362 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1363 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1364 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1365 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1366 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1367 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1368 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1369 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1370 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1371 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1372 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1373 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1374 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1375 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1376 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1377 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1378 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1379 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1380 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1381 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1382 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1383 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1384 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1385 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1386 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1387 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1388 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1389 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1390 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1391 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1392 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1393 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1394 { X86::VPORYrr, X86::VPORYrm, 0 },
1395 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1396 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
1397 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, 0 },
1398 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, 0 },
1399 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, 0 },
1400 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1401 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1402 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1403 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1404 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1405 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1406 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1407 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1408 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1409 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1410 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
1411 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1412 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1413 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1414 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1415 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1416 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1417 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1418 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1419 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame^]1420 { X86::VPSUBQYrr, X86::VPSUBQYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1421 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1422 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame^]1423 { X86::VPSUBUSBYrr, X86::VPSUBUSBYrm, 0 },
1424 { X86::VPSUBUSWYrr, X86::VPSUBUSWYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1425 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1426 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1427 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1428 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1429 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1430 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1431 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1432 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1433 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1434 { X86::VPXORYrr, X86::VPXORYrm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1435
1436 // FMA4 foldable patterns
Craig Topperf7e92f12015-02-10 05:10:50 +0000[diff] [blame]1437 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, 0 },
1438 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, 0 },
1439 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, 0 },
1440 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, 0 },
1441 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, 0 },
1442 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, 0 },
1443 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, 0 },
1444 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, 0 },
1445 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, 0 },
1446 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, 0 },
1447 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, 0 },
1448 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, 0 },
1449 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, 0 },
1450 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, 0 },
1451 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, 0 },
1452 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, 0 },
1453 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, 0 },
1454 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, 0 },
1455 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, 0 },
1456 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, 0 },
1457 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, 0 },
1458 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, 0 },
1459 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, 0 },
1460 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, 0 },
1461 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, 0 },
1462 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, 0 },
1463 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, 0 },
1464 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, 0 },
1465 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, 0 },
1466 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, 0 },
1467 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, 0 },
1468 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, 0 },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1469
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1470 // XOP foldable instructions
1471 { X86::VPCMOVrr, X86::VPCMOVmr, 0 },
1472 { X86::VPCMOVrrY, X86::VPCMOVmrY, 0 },
1473 { X86::VPCOMBri, X86::VPCOMBmi, 0 },
1474 { X86::VPCOMDri, X86::VPCOMDmi, 0 },
1475 { X86::VPCOMQri, X86::VPCOMQmi, 0 },
1476 { X86::VPCOMWri, X86::VPCOMWmi, 0 },
1477 { X86::VPCOMUBri, X86::VPCOMUBmi, 0 },
1478 { X86::VPCOMUDri, X86::VPCOMUDmi, 0 },
1479 { X86::VPCOMUQri, X86::VPCOMUQmi, 0 },
1480 { X86::VPCOMUWri, X86::VPCOMUWmi, 0 },
1481 { X86::VPERMIL2PDrr, X86::VPERMIL2PDmr, 0 },
1482 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDmrY, 0 },
1483 { X86::VPERMIL2PSrr, X86::VPERMIL2PSmr, 0 },
1484 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSmrY, 0 },
1485 { X86::VPMACSDDrr, X86::VPMACSDDrm, 0 },
1486 { X86::VPMACSDQHrr, X86::VPMACSDQHrm, 0 },
1487 { X86::VPMACSDQLrr, X86::VPMACSDQLrm, 0 },
1488 { X86::VPMACSSDDrr, X86::VPMACSSDDrm, 0 },
1489 { X86::VPMACSSDQHrr, X86::VPMACSSDQHrm, 0 },
1490 { X86::VPMACSSDQLrr, X86::VPMACSSDQLrm, 0 },
1491 { X86::VPMACSSWDrr, X86::VPMACSSWDrm, 0 },
1492 { X86::VPMACSSWWrr, X86::VPMACSSWWrm, 0 },
1493 { X86::VPMACSWDrr, X86::VPMACSWDrm, 0 },
1494 { X86::VPMACSWWrr, X86::VPMACSWWrm, 0 },
1495 { X86::VPMADCSSWDrr, X86::VPMADCSSWDrm, 0 },
1496 { X86::VPMADCSWDrr, X86::VPMADCSWDrm, 0 },
1497 { X86::VPPERMrr, X86::VPPERMmr, 0 },
1498 { X86::VPROTBrr, X86::VPROTBrm, 0 },
1499 { X86::VPROTDrr, X86::VPROTDrm, 0 },
1500 { X86::VPROTQrr, X86::VPROTQrm, 0 },
1501 { X86::VPROTWrr, X86::VPROTWrm, 0 },
1502 { X86::VPSHABrr, X86::VPSHABrm, 0 },
1503 { X86::VPSHADrr, X86::VPSHADrm, 0 },
1504 { X86::VPSHAQrr, X86::VPSHAQrm, 0 },
1505 { X86::VPSHAWrr, X86::VPSHAWrm, 0 },
1506 { X86::VPSHLBrr, X86::VPSHLBrm, 0 },
1507 { X86::VPSHLDrr, X86::VPSHLDrm, 0 },
1508 { X86::VPSHLQrr, X86::VPSHLQrm, 0 },
1509 { X86::VPSHLWrr, X86::VPSHLWrm, 0 },
1510
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1511 // BMI/BMI2 foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1512 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1513 { X86::ANDN64rr, X86::ANDN64rm, 0 },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1514 { X86::MULX32rr, X86::MULX32rm, 0 },
1515 { X86::MULX64rr, X86::MULX64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1516 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1517 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1518 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1519 { X86::PEXT64rr, X86::PEXT64rm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1520
1521 // AVX-512 foldable instructions
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1522 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1523 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
1524 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1525 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
1526 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1527 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
1528 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1529 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
1530 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1531 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1532 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1533 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1534 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1535 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1536 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1537 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1538 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1539 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1540 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1541 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1542 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1543 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1544 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1545 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1546 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1547 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1548 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1549 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1550 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1551 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1552 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1553 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1554 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1555 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
1556 { X86::VALIGNQrri, X86::VALIGNQrmi, 0 },
1557 { X86::VALIGNDrri, X86::VALIGNDrmi, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1558 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1559 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE },
1560 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE },
1561
1562 // AVX-512{F,VL} foldable instructions
1563 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE },
1564 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE },
1565 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1566
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1567 // AVX-512{F,VL} foldable instructions
1568 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 },
1569 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 },
1570 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 },
1571 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 },
1572
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1573 // AES foldable instructions
1574 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
1575 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
1576 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
1577 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
Craig Topperf7e92f12015-02-10 05:10:50 +0000[diff] [blame]1578 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, 0 },
1579 { X86::VAESDECrr, X86::VAESDECrm, 0 },
1580 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, 0 },
1581 { X86::VAESENCrr, X86::VAESENCrm, 0 },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1582
1583 // SHA foldable instructions
1584 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },
1585 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 },
1586 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 },
1587 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 },
1588 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 },
1589 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1590 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1591 };
1592
1593 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]1594 unsigned RegOp = OpTbl2[i].RegOp;
1595 unsigned MemOp = OpTbl2[i].MemOp;
1596 unsigned Flags = OpTbl2[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1597 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1598 RegOp, MemOp,
1599 // Index 2, folded load
1600 Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1601 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1602
1603 static const X86OpTblEntry OpTbl3[] = {
1604 // FMA foldable instructions
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1605 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, TB_ALIGN_NONE },
1606 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, TB_ALIGN_NONE },
1607 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, TB_ALIGN_NONE },
1608 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, TB_ALIGN_NONE },
1609 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, TB_ALIGN_NONE },
1610 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1611
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1612 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_NONE },
1613 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_NONE },
1614 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_NONE },
1615 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_NONE },
1616 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_NONE },
1617 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_NONE },
1618 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_NONE },
1619 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_NONE },
1620 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_NONE },
1621 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_NONE },
1622 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_NONE },
1623 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1624
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1625 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, TB_ALIGN_NONE },
1626 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, TB_ALIGN_NONE },
1627 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, TB_ALIGN_NONE },
1628 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, TB_ALIGN_NONE },
1629 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, TB_ALIGN_NONE },
1630 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1631
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1632 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_NONE },
1633 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_NONE },
1634 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_NONE },
1635 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_NONE },
1636 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_NONE },
1637 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_NONE },
1638 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_NONE },
1639 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_NONE },
1640 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_NONE },
1641 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_NONE },
1642 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_NONE },
1643 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1644
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1645 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, TB_ALIGN_NONE },
1646 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, TB_ALIGN_NONE },
1647 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, TB_ALIGN_NONE },
1648 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, TB_ALIGN_NONE },
1649 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, TB_ALIGN_NONE },
1650 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1651
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1652 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_NONE },
1653 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_NONE },
1654 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_NONE },
1655 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_NONE },
1656 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_NONE },
1657 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_NONE },
1658 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_NONE },
1659 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_NONE },
1660 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_NONE },
1661 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_NONE },
1662 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_NONE },
1663 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1664
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1665 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, TB_ALIGN_NONE },
1666 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, TB_ALIGN_NONE },
1667 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, TB_ALIGN_NONE },
1668 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, TB_ALIGN_NONE },
1669 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, TB_ALIGN_NONE },
1670 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, TB_ALIGN_NONE },
Craig Topper2e127b52012-06-01 05:48:39 +0000[diff] [blame]1671
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1672 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_NONE },
1673 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_NONE },
1674 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_NONE },
1675 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_NONE },
1676 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_NONE },
1677 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_NONE },
1678 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_NONE },
1679 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_NONE },
1680 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_NONE },
1681 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_NONE },
1682 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_NONE },
1683 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1684
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1685 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_NONE },
1686 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_NONE },
1687 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_NONE },
1688 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_NONE },
1689 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_NONE },
1690 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_NONE },
1691 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_NONE },
1692 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_NONE },
1693 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_NONE },
1694 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_NONE },
1695 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_NONE },
1696 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1697
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1698 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_NONE },
1699 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_NONE },
1700 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_NONE },
1701 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_NONE },
1702 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_NONE },
1703 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_NONE },
1704 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_NONE },
1705 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_NONE },
1706 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_NONE },
1707 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_NONE },
1708 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_NONE },
1709 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_NONE },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1710
1711 // FMA4 foldable patterns
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1712 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, 0 },
1713 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1714 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_16 },
1715 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_16 },
1716 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_32 },
1717 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1718 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, 0 },
1719 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1720 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_16 },
1721 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_16 },
1722 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_32 },
1723 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1724 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, 0 },
1725 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1726 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_16 },
1727 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_16 },
1728 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_32 },
1729 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1730 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, 0 },
1731 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1732 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_16 },
1733 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_16 },
1734 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_32 },
1735 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_32 },
1736 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_16 },
1737 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_16 },
1738 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_32 },
1739 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_32 },
1740 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_16 },
1741 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_16 },
1742 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_32 },
1743 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_32 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1744
1745 // XOP foldable instructions
1746 { X86::VPCMOVrr, X86::VPCMOVrm, 0 },
1747 { X86::VPCMOVrrY, X86::VPCMOVrmY, 0 },
1748 { X86::VPERMIL2PDrr, X86::VPERMIL2PDrm, 0 },
1749 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDrmY, 0 },
1750 { X86::VPERMIL2PSrr, X86::VPERMIL2PSrm, 0 },
1751 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSrmY, 0 },
1752 { X86::VPPERMrr, X86::VPPERMrm, 0 },
1753
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]1754 // AVX-512 VPERMI instructions with 3 source operands.
1755 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
1756 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
1757 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
1758 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1759 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
1760 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
1761 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1762 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 },
1763 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE },
1764 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE },
1765 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE },
1766 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1767 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE },
1768 // AVX-512 arithmetic instructions
1769 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 },
1770 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 },
1771 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 },
1772 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 },
1773 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 },
1774 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 },
1775 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 },
1776 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 },
1777 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 },
1778 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 },
1779 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 },
1780 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 },
1781 // AVX-512{F,VL} arithmetic instructions 256-bit
1782 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 },
1783 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 },
1784 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 },
1785 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 },
1786 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 },
1787 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 },
1788 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 },
1789 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 },
1790 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 },
1791 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 },
1792 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 },
1793 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 },
1794 // AVX-512{F,VL} arithmetic instructions 128-bit
1795 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 },
1796 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 },
1797 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 },
1798 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 },
1799 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 },
1800 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 },
1801 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 },
1802 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 },
1803 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 },
1804 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 },
1805 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 },
1806 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1807 };
1808
1809 for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1810 unsigned RegOp = OpTbl3[i].RegOp;
1811 unsigned MemOp = OpTbl3[i].MemOp;
1812 unsigned Flags = OpTbl3[i].Flags;
1813 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1814 RegOp, MemOp,
1815 // Index 3, folded load
1816 Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1817 }
1818
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1819 static const X86OpTblEntry OpTbl4[] = {
1820 // AVX-512 foldable instructions
1821 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 },
1822 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 },
1823 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 },
1824 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 },
1825 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 },
1826 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 },
1827 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 },
1828 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 },
1829 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 },
1830 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 },
1831 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 },
1832 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 },
1833 // AVX-512{F,VL} foldable instructions 256-bit
1834 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 },
1835 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 },
1836 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 },
1837 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 },
1838 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 },
1839 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 },
1840 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 },
1841 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 },
1842 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 },
1843 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 },
1844 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 },
1845 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 },
1846 // AVX-512{F,VL} foldable instructions 128-bit
1847 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 },
1848 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 },
1849 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 },
1850 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 },
1851 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 },
1852 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 },
1853 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 },
1854 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 },
1855 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 },
1856 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 },
1857 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 },
1858 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 }
1859 };
1860
1861 for (unsigned i = 0, e = array_lengthof(OpTbl4); i != e; ++i) {
1862 unsigned RegOp = OpTbl4[i].RegOp;
1863 unsigned MemOp = OpTbl4[i].MemOp;
1864 unsigned Flags = OpTbl4[i].Flags;
1865 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
1866 RegOp, MemOp,
1867 // Index 4, folded load
1868 Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
1869 }
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]1870}
1871
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1872void
1873X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1874 MemOp2RegOpTableType &M2RTable,
1875 unsigned RegOp, unsigned MemOp, unsigned Flags) {
1876 if ((Flags & TB_NO_FORWARD) == 0) {
1877 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1878 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1879 }
1880 if ((Flags & TB_NO_REVERSE) == 0) {
1881 assert(!M2RTable.count(MemOp) &&
1882 "Duplicated entries in unfolding maps?");
1883 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1884 }
1885}
1886
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1887bool
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]1888X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1889 unsigned &SrcReg, unsigned &DstReg,
1890 unsigned &SubIdx) const {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1891 switch (MI.getOpcode()) {
1892 default: break;
1893 case X86::MOVSX16rr8:
1894 case X86::MOVZX16rr8:
1895 case X86::MOVSX32rr8:
1896 case X86::MOVZX32rr8:
1897 case X86::MOVSX64rr8:
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]1898 if (!Subtarget.is64Bit())
Evan Chengceb5a4e2010-01-13 08:01:32 +0000[diff] [blame]1899 // It's not always legal to reference the low 8-bit of the larger
1900 // register in 32-bit mode.
1901 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1902 case X86::MOVSX32rr16:
1903 case X86::MOVZX32rr16:
1904 case X86::MOVSX64rr16:
Tim Northover04eb4232013-05-30 10:43:18 +0000[diff] [blame]1905 case X86::MOVSX64rr32: {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1906 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1907 // Be conservative.
1908 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1909 SrcReg = MI.getOperand(1).getReg();
1910 DstReg = MI.getOperand(0).getReg();
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1911 switch (MI.getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]1912 default: llvm_unreachable("Unreachable!");
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1913 case X86::MOVSX16rr8:
1914 case X86::MOVZX16rr8:
1915 case X86::MOVSX32rr8:
1916 case X86::MOVZX32rr8:
1917 case X86::MOVSX64rr8:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]1918 SubIdx = X86::sub_8bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1919 break;
1920 case X86::MOVSX32rr16:
1921 case X86::MOVZX32rr16:
1922 case X86::MOVSX64rr16:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]1923 SubIdx = X86::sub_16bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1924 break;
1925 case X86::MOVSX64rr32:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]1926 SubIdx = X86::sub_32bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1927 break;
1928 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]1929 return true;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1930 }
1931 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]1932 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1933}
1934
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]1935int X86InstrInfo::getSPAdjust(const MachineInstr *MI) const {
1936 const MachineFunction *MF = MI->getParent()->getParent();
1937 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
1938
1939 if (MI->getOpcode() == getCallFrameSetupOpcode() ||
1940 MI->getOpcode() == getCallFrameDestroyOpcode()) {
1941 unsigned StackAlign = TFI->getStackAlignment();
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1942 int SPAdj = (MI->getOperand(0).getImm() + StackAlign - 1) / StackAlign *
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]1943 StackAlign;
1944
1945 SPAdj -= MI->getOperand(1).getImm();
1946
1947 if (MI->getOpcode() == getCallFrameSetupOpcode())
1948 return SPAdj;
1949 else
1950 return -SPAdj;
1951 }
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1952
1953 // To know whether a call adjusts the stack, we need information
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]1954 // that is bound to the following ADJCALLSTACKUP pseudo.
1955 // Look for the next ADJCALLSTACKUP that follows the call.
1956 if (MI->isCall()) {
1957 const MachineBasicBlock* MBB = MI->getParent();
1958 auto I = ++MachineBasicBlock::const_iterator(MI);
1959 for (auto E = MBB->end(); I != E; ++I) {
1960 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
1961 I->isCall())
1962 break;
1963 }
1964
1965 // If we could not find a frame destroy opcode, then it has already
1966 // been simplified, so we don't care.
1967 if (I->getOpcode() != getCallFrameDestroyOpcode())
1968 return 0;
1969
1970 return -(I->getOperand(1).getImm());
1971 }
1972
1973 // Currently handle only PUSHes we can reasonably expect to see
1974 // in call sequences
1975 switch (MI->getOpcode()) {
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1976 default:
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]1977 return 0;
1978 case X86::PUSH32i8:
1979 case X86::PUSH32r:
1980 case X86::PUSH32rmm:
1981 case X86::PUSH32rmr:
1982 case X86::PUSHi32:
1983 return 4;
1984 }
1985}
1986
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]1987/// isFrameOperand - Return true and the FrameIndex if the specified
1988/// operand and follow operands form a reference to the stack frame.
1989bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1990 int &FrameIndex) const {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]1991 if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
1992 MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
1993 MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
1994 MI->getOperand(Op+X86::AddrDisp).isImm() &&
1995 MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
1996 MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
1997 MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
1998 FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]1999 return true;
2000 }
2001 return false;
2002}
2003
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2004static bool isFrameLoadOpcode(int Opcode) {
2005 switch (Opcode) {
David Blaikie46a9f012012-01-20 21:51:11 +0000[diff] [blame]2006 default:
2007 return false;
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2008 case X86::MOV8rm:
2009 case X86::MOV16rm:
2010 case X86::MOV32rm:
Evan Cheng11b0a5d2006-09-08 06:48:29 +0000[diff] [blame]2011 case X86::MOV64rm:
Dale Johannesen3d7008c2007-07-04 21:07:47 +0000[diff] [blame]2012 case X86::LD_Fp64m:
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2013 case X86::MOVSSrm:
2014 case X86::MOVSDrm:
Chris Lattnerbfc2c682006-04-18 16:44:51 +0000[diff] [blame]2015 case X86::MOVAPSrm:
2016 case X86::MOVAPDrm:
Dan Gohmanbdc0f8b2009-01-09 02:40:34 +0000[diff] [blame]2017 case X86::MOVDQArm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2018 case X86::VMOVSSrm:
2019 case X86::VMOVSDrm:
2020 case X86::VMOVAPSrm:
2021 case X86::VMOVAPDrm:
2022 case X86::VMOVDQArm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2023 case X86::VMOVUPSYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2024 case X86::VMOVAPSYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2025 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2026 case X86::VMOVAPDYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2027 case X86::VMOVDQUYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2028 case X86::VMOVDQAYrm:
Bill Wendlinge7b2a862007-04-03 06:00:37 +0000[diff] [blame]2029 case X86::MMX_MOVD64rm:
2030 case X86::MMX_MOVQ64rm:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2031 case X86::VMOVAPSZrm:
2032 case X86::VMOVUPSZrm:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2033 return true;
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2034 }
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2035}
2036
2037static bool isFrameStoreOpcode(int Opcode) {
2038 switch (Opcode) {
2039 default: break;
2040 case X86::MOV8mr:
2041 case X86::MOV16mr:
2042 case X86::MOV32mr:
2043 case X86::MOV64mr:
2044 case X86::ST_FpP64m:
2045 case X86::MOVSSmr:
2046 case X86::MOVSDmr:
2047 case X86::MOVAPSmr:
2048 case X86::MOVAPDmr:
2049 case X86::MOVDQAmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2050 case X86::VMOVSSmr:
2051 case X86::VMOVSDmr:
2052 case X86::VMOVAPSmr:
2053 case X86::VMOVAPDmr:
2054 case X86::VMOVDQAmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2055 case X86::VMOVUPSYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2056 case X86::VMOVAPSYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2057 case X86::VMOVUPDYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2058 case X86::VMOVAPDYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2059 case X86::VMOVDQUYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2060 case X86::VMOVDQAYmr:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2061 case X86::VMOVUPSZmr:
2062 case X86::VMOVAPSZmr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2063 case X86::MMX_MOVD64mr:
2064 case X86::MMX_MOVQ64mr:
2065 case X86::MMX_MOVNTQmr:
2066 return true;
2067 }
2068 return false;
2069}
2070
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2071unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2072 int &FrameIndex) const {
2073 if (isFrameLoadOpcode(MI->getOpcode()))
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]2074 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2075 return MI->getOperand(0).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2076 return 0;
2077}
2078
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2079unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2080 int &FrameIndex) const {
2081 if (isFrameLoadOpcode(MI->getOpcode())) {
2082 unsigned Reg;
2083 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2084 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2085 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2086 const MachineMemOperand *Dummy;
2087 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2088 }
2089 return 0;
2090}
2091
Dan Gohman0b273252008-11-18 19:49:32 +0000[diff] [blame]2092unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2093 int &FrameIndex) const {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2094 if (isFrameStoreOpcode(MI->getOpcode()))
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]2095 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
2096 isFrameOperand(MI, 0, FrameIndex))
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]2097 return MI->getOperand(X86::AddrNumOperands).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2098 return 0;
2099}
2100
2101unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
2102 int &FrameIndex) const {
2103 if (isFrameStoreOpcode(MI->getOpcode())) {
2104 unsigned Reg;
2105 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2106 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2107 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2108 const MachineMemOperand *Dummy;
2109 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2110 }
2111 return 0;
2112}
2113
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2114/// regIsPICBase - Return true if register is PIC base (i.e.g defined by
2115/// X86::MOVPC32r.
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2116static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
Jakob Stoklund Olesen3b9a4422012-08-08 00:40:47 +0000[diff] [blame]2117 // Don't waste compile time scanning use-def chains of physregs.
2118 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2119 return false;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2120 bool isPICBase = false;
Owen Anderson16c6bf42014-03-13 23:12:04 +0000[diff] [blame]2121 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2122 E = MRI.def_instr_end(); I != E; ++I) {
2123 MachineInstr *DefMI = &*I;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2124 if (DefMI->getOpcode() != X86::MOVPC32r)
2125 return false;
2126 assert(!isPICBase && "More than one PIC base?");
2127 isPICBase = true;
2128 }
2129 return isPICBase;
2130}
Evan Cheng1973a462008-03-31 07:54:19 +0000[diff] [blame]2131
Bill Wendling1e117682008-05-12 20:54:26 +0000[diff] [blame]2132bool
Dan Gohmane919de52009-10-10 00:34:18 +0000[diff] [blame]2133X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
2134 AliasAnalysis *AA) const {
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2135 switch (MI->getOpcode()) {
2136 default: break;
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2137 case X86::MOV8rm:
2138 case X86::MOV16rm:
2139 case X86::MOV32rm:
2140 case X86::MOV64rm:
2141 case X86::LD_Fp64m:
2142 case X86::MOVSSrm:
2143 case X86::MOVSDrm:
2144 case X86::MOVAPSrm:
2145 case X86::MOVUPSrm:
2146 case X86::MOVAPDrm:
2147 case X86::MOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2148 case X86::MOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2149 case X86::VMOVSSrm:
2150 case X86::VMOVSDrm:
2151 case X86::VMOVAPSrm:
2152 case X86::VMOVUPSrm:
2153 case X86::VMOVAPDrm:
2154 case X86::VMOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2155 case X86::VMOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2156 case X86::VMOVAPSYrm:
2157 case X86::VMOVUPSYrm:
2158 case X86::VMOVAPDYrm:
2159 case X86::VMOVDQAYrm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2160 case X86::VMOVDQUYrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2161 case X86::MMX_MOVD64rm:
2162 case X86::MMX_MOVQ64rm:
2163 case X86::FsVMOVAPSrm:
2164 case X86::FsVMOVAPDrm:
2165 case X86::FsMOVAPSrm:
2166 case X86::FsMOVAPDrm: {
2167 // Loads from constant pools are trivially rematerializable.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2168 if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
2169 MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2170 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2171 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2172 MI->isInvariantLoad(AA)) {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2173 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2174 if (BaseReg == 0 || BaseReg == X86::RIP)
2175 return true;
2176 // Allow re-materialization of PIC load.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2177 if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2178 return false;
2179 const MachineFunction &MF = *MI->getParent()->getParent();
2180 const MachineRegisterInfo &MRI = MF.getRegInfo();
2181 return regIsPICBase(BaseReg, MRI);
Evan Cheng94ba37f2008-02-22 09:25:47 +0000[diff] [blame]2182 }
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2183 return false;
2184 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2185
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2186 case X86::LEA32r:
2187 case X86::LEA64r: {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2188 if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2189 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2190 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2191 !MI->getOperand(1+X86::AddrDisp).isReg()) {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2192 // lea fi#, lea GV, etc. are all rematerializable.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2193 if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2194 return true;
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2195 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2196 if (BaseReg == 0)
2197 return true;
2198 // Allow re-materialization of lea PICBase + x.
2199 const MachineFunction &MF = *MI->getParent()->getParent();
2200 const MachineRegisterInfo &MRI = MF.getRegInfo();
2201 return regIsPICBase(BaseReg, MRI);
2202 }
2203 return false;
2204 }
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2205 }
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]2206
Dan Gohmane8c1e422007-06-26 00:48:07 +0000[diff] [blame]2207 // All other instructions marked M_REMATERIALIZABLE are always trivially
2208 // rematerializable.
2209 return true;
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2210}
2211
Alexey Volkov6226de62014-05-20 08:55:50 +0000[diff] [blame]2212bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2213 MachineBasicBlock::iterator I) const {
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2214 MachineBasicBlock::iterator E = MBB.end();
2215
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2216 // For compile time consideration, if we are not able to determine the
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2217 // safety after visiting 4 instructions in each direction, we will assume
2218 // it's not safe.
2219 MachineBasicBlock::iterator Iter = I;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2220 for (unsigned i = 0; Iter != E && i < 4; ++i) {
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2221 bool SeenDef = false;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2222 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2223 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2224 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2225 SeenDef = true;
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2226 if (!MO.isReg())
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2227 continue;
2228 if (MO.getReg() == X86::EFLAGS) {
2229 if (MO.isUse())
2230 return false;
2231 SeenDef = true;
2232 }
2233 }
2234
2235 if (SeenDef)
2236 // This instruction defines EFLAGS, no need to look any further.
2237 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2238 ++Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2239 // Skip over DBG_VALUE.
2240 while (Iter != E && Iter->isDebugValue())
2241 ++Iter;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2242 }
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2243
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2244 // It is safe to clobber EFLAGS at the end of a block of no successor has it
2245 // live in.
2246 if (Iter == E) {
2247 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
2248 SE = MBB.succ_end(); SI != SE; ++SI)
2249 if ((*SI)->isLiveIn(X86::EFLAGS))
2250 return false;
2251 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2252 }
2253
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2254 MachineBasicBlock::iterator B = MBB.begin();
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2255 Iter = I;
2256 for (unsigned i = 0; i < 4; ++i) {
2257 // If we make it to the beginning of the block, it's safe to clobber
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +0000[diff] [blame]2258 // EFLAGS iff EFLAGS is not live-in.
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2259 if (Iter == B)
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2260 return !MBB.isLiveIn(X86::EFLAGS);
2261
2262 --Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2263 // Skip over DBG_VALUE.
2264 while (Iter != B && Iter->isDebugValue())
2265 --Iter;
2266
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2267 bool SawKill = false;
2268 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2269 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2270 // A register mask may clobber EFLAGS, but we should still look for a
2271 // live EFLAGS def.
2272 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2273 SawKill = true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2274 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2275 if (MO.isDef()) return MO.isDead();
2276 if (MO.isKill()) SawKill = true;
2277 }
2278 }
2279
2280 if (SawKill)
2281 // This instruction kills EFLAGS and doesn't redefine it, so
2282 // there's no need to look further.
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2283 return true;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2284 }
2285
2286 // Conservative answer.
2287 return false;
2288}
2289
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2290void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2291 MachineBasicBlock::iterator I,
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]2292 unsigned DestReg, unsigned SubIdx,
Evan Cheng6ad7da92009-11-14 02:55:43 +0000[diff] [blame]2293 const MachineInstr *Orig,
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]2294 const TargetRegisterInfo &TRI) const {
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]2295 // MOV32r0 is implemented with a xor which clobbers condition code.
2296 // Re-materialize it as movri instructions to avoid side effects.
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]2297 unsigned Opc = Orig->getOpcode();
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]2298 if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
2299 DebugLoc DL = Orig->getDebugLoc();
2300 BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
2301 .addImm(0);
2302 } else {
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2303 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2304 MBB.insert(I, MI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2305 }
Evan Cheng147cb762008-04-16 23:44:44 +0000[diff] [blame]2306
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]2307 MachineInstr *NewMI = std::prev(I);
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]2308 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2309}
2310
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]2311/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
2312/// is not marked dead.
2313static bool hasLiveCondCodeDef(MachineInstr *MI) {
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]2314 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2315 MachineOperand &MO = MI->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2316 if (MO.isReg() && MO.isDef() &&
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]2317 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2318 return true;
2319 }
2320 }
2321 return false;
2322}
2323
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2324/// getTruncatedShiftCount - check whether the shift count for a machine operand
2325/// is non-zero.
2326inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
2327 unsigned ShiftAmtOperandIdx) {
2328 // The shift count is six bits with the REX.W prefix and five bits without.
2329 unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2330 unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
2331 return Imm & ShiftCountMask;
2332}
2333
2334/// isTruncatedShiftCountForLEA - check whether the given shift count is appropriate
2335/// can be represented by a LEA instruction.
2336inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2337 // Left shift instructions can be transformed into load-effective-address
2338 // instructions if we can encode them appropriately.
2339 // A LEA instruction utilizes a SIB byte to encode it's scale factor.
2340 // The SIB.scale field is two bits wide which means that we can encode any
2341 // shift amount less than 4.
2342 return ShAmt < 4 && ShAmt > 0;
2343}
2344
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2345bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
2346 unsigned Opc, bool AllowSP,
2347 unsigned &NewSrc, bool &isKill, bool &isUndef,
2348 MachineOperand &ImplicitOp) const {
2349 MachineFunction &MF = *MI->getParent()->getParent();
2350 const TargetRegisterClass *RC;
2351 if (AllowSP) {
2352 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2353 } else {
2354 RC = Opc != X86::LEA32r ?
2355 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2356 }
2357 unsigned SrcReg = Src.getReg();
2358
2359 // For both LEA64 and LEA32 the register already has essentially the right
2360 // type (32-bit or 64-bit) we may just need to forbid SP.
2361 if (Opc != X86::LEA64_32r) {
2362 NewSrc = SrcReg;
2363 isKill = Src.isKill();
2364 isUndef = Src.isUndef();
2365
2366 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2367 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2368 return false;
2369
2370 return true;
2371 }
2372
2373 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2374 // another we need to add 64-bit registers to the final MI.
2375 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2376 ImplicitOp = Src;
2377 ImplicitOp.setImplicit();
2378
2379 NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
2380 MachineBasicBlock::LivenessQueryResult LQR =
2381 MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2382
2383 switch (LQR) {
2384 case MachineBasicBlock::LQR_Unknown:
2385 // We can't give sane liveness flags to the instruction, abandon LEA
2386 // formation.
2387 return false;
2388 case MachineBasicBlock::LQR_Live:
2389 isKill = MI->killsRegister(SrcReg);
2390 isUndef = false;
2391 break;
2392 default:
2393 // The physreg itself is dead, so we have to use it as an <undef>.
2394 isKill = false;
2395 isUndef = true;
2396 break;
2397 }
2398 } else {
2399 // Virtual register of the wrong class, we have to create a temporary 64-bit
2400 // vreg to feed into the LEA.
2401 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2402 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
2403 get(TargetOpcode::COPY))
2404 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2405 .addOperand(Src);
2406
2407 // Which is obviously going to be dead after we're done with it.
2408 isKill = true;
2409 isUndef = false;
2410 }
2411
2412 // We've set all the parameters without issue.
2413 return true;
2414}
2415
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2416/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2417/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
2418/// to a 32-bit superregister and then truncating back down to a 16-bit
2419/// subregister.
2420MachineInstr *
2421X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2422 MachineFunction::iterator &MFI,
2423 MachineBasicBlock::iterator &MBBI,
2424 LiveVariables *LV) const {
2425 MachineInstr *MI = MBBI;
2426 unsigned Dest = MI->getOperand(0).getReg();
2427 unsigned Src = MI->getOperand(1).getReg();
2428 bool isDead = MI->getOperand(0).isDead();
2429 bool isKill = MI->getOperand(1).isKill();
2430
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2431 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2432 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2433 unsigned Opc, leaInReg;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2434 if (Subtarget.is64Bit()) {
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2435 Opc = X86::LEA64_32r;
2436 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2437 } else {
2438 Opc = X86::LEA32r;
2439 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2440 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2441
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2442 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2443 // well be shifting and then extracting the lower 16-bits.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2444 // This has the potential to cause partial register stall. e.g.
Evan Cheng3974c8d2009-12-12 18:55:26 +0000[diff] [blame]2445 // movw (%rbp,%rcx,2), %dx
2446 // leal -65(%rdx), %esi
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2447 // But testing has shown this *does* help performance in 64-bit mode (at
2448 // least on modern x86 machines).
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2449 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2450 MachineInstr *InsMI =
Jakob Stoklund Olesena1e883d2010-07-08 16:40:15 +0000[diff] [blame]2451 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2452 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2453 .addReg(Src, getKillRegState(isKill));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2454
2455 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2456 get(Opc), leaOutReg);
2457 switch (MIOpc) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2458 default: llvm_unreachable("Unreachable!");
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2459 case X86::SHL16ri: {
2460 unsigned ShAmt = MI->getOperand(2).getImm();
2461 MIB.addReg(0).addImm(1 << ShAmt)
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2462 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2463 break;
2464 }
2465 case X86::INC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2466 addRegOffset(MIB, leaInReg, true, 1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2467 break;
2468 case X86::DEC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2469 addRegOffset(MIB, leaInReg, true, -1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2470 break;
2471 case X86::ADD16ri:
2472 case X86::ADD16ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2473 case X86::ADD16ri_DB:
2474 case X86::ADD16ri8_DB:
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2475 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2476 break;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2477 case X86::ADD16rr:
2478 case X86::ADD16rr_DB: {
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2479 unsigned Src2 = MI->getOperand(2).getReg();
2480 bool isKill2 = MI->getOperand(2).isKill();
2481 unsigned leaInReg2 = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2482 MachineInstr *InsMI2 = nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2483 if (Src == Src2) {
2484 // ADD16rr %reg1028<kill>, %reg1028
2485 // just a single insert_subreg.
2486 addRegReg(MIB, leaInReg, true, leaInReg, false);
2487 } else {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2488 if (Subtarget.is64Bit())
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2489 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2490 else
2491 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2492 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2493 // well be shifting and then extracting the lower 16-bits.
Evan Cheng7fae11b2011-12-14 02:11:42 +0000[diff] [blame]2494 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2495 InsMI2 =
Evan Cheng7fae11b2011-12-14 02:11:42 +0000[diff] [blame]2496 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
Jakob Stoklund Olesena1e883d2010-07-08 16:40:15 +0000[diff] [blame]2497 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2498 .addReg(Src2, getKillRegState(isKill2));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2499 addRegReg(MIB, leaInReg, true, leaInReg2, true);
2500 }
2501 if (LV && isKill2 && InsMI2)
2502 LV->replaceKillInstruction(Src2, MI, InsMI2);
2503 break;
2504 }
2505 }
2506
2507 MachineInstr *NewMI = MIB;
2508 MachineInstr *ExtMI =
Jakob Stoklund Olesen00264622010-07-08 16:40:22 +0000[diff] [blame]2509 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2510 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
Jakob Stoklund Olesen00264622010-07-08 16:40:22 +0000[diff] [blame]2511 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2512
2513 if (LV) {
2514 // Update live variables
2515 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2516 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2517 if (isKill)
2518 LV->replaceKillInstruction(Src, MI, InsMI);
2519 if (isDead)
2520 LV->replaceKillInstruction(Dest, MI, ExtMI);
2521 }
2522
2523 return ExtMI;
2524}
2525
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2526/// convertToThreeAddress - This method must be implemented by targets that
2527/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
2528/// may be able to convert a two-address instruction into a true
2529/// three-address instruction on demand. This allows the X86 target (for
2530/// example) to convert ADD and SHL instructions into LEA instructions if they
2531/// would require register copies due to two-addressness.
2532///
2533/// This method returns a null pointer if the transformation cannot be
2534/// performed, otherwise it returns the new instruction.
2535///
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2536MachineInstr *
2537X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2538 MachineBasicBlock::iterator &MBBI,
Owen Anderson30cc0282008-07-02 23:41:07 +0000[diff] [blame]2539 LiveVariables *LV) const {
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2540 MachineInstr *MI = MBBI;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2541
2542 // The following opcodes also sets the condition code register(s). Only
2543 // convert them to equivalent lea if the condition code register def's
2544 // are dead!
2545 if (hasLiveCondCodeDef(MI))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2546 return nullptr;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2547
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2548 MachineFunction &MF = *MI->getParent()->getParent();
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2549 // All instructions input are two-addr instructions. Get the known operands.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2550 const MachineOperand &Dest = MI->getOperand(0);
2551 const MachineOperand &Src = MI->getOperand(1);
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2552
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2553 MachineInstr *NewMI = nullptr;
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2554 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2555 // we have better subtarget support, enable the 16-bit LEA generation here.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2556 // 16-bit LEA is also slow on Core2.
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2557 bool DisableLEA16 = true;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2558 bool is64Bit = Subtarget.is64Bit();
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2559
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2560 unsigned MIOpc = MI->getOpcode();
2561 switch (MIOpc) {
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2562 default: return nullptr;
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2563 case X86::SHL64ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2564 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2565 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2566 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2567
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2568 // LEA can't handle RSP.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2569 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2570 !MF.getRegInfo().constrainRegClass(Src.getReg(),
2571 &X86::GR64_NOSPRegClass))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2572 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2573
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]2574 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2575 .addOperand(Dest)
2576 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2577 break;
2578 }
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2579 case X86::SHL32ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2580 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2581 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2582 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2583
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2584 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2585
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2586 // LEA can't handle ESP.
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2587 bool isKill, isUndef;
2588 unsigned SrcReg;
2589 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2590 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2591 SrcReg, isKill, isUndef, ImplicitOp))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2592 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2593
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2594 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2595 .addOperand(Dest)
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2596 .addReg(0).addImm(1 << ShAmt)
2597 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2598 .addImm(0).addReg(0);
2599 if (ImplicitOp.getReg() != 0)
2600 MIB.addOperand(ImplicitOp);
2601 NewMI = MIB;
2602
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2603 break;
2604 }
2605 case X86::SHL16ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2606 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2607 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2608 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2609
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2610 if (DisableLEA16)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2611 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2612 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2613 .addOperand(Dest)
2614 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2615 break;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2616 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2617 case X86::INC64r:
2618 case X86::INC32r: {
2619 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2620 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2621 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2622 bool isKill, isUndef;
2623 unsigned SrcReg;
2624 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2625 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2626 SrcReg, isKill, isUndef, ImplicitOp))
2627 return nullptr;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2628
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2629 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2630 .addOperand(Dest)
2631 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2632 if (ImplicitOp.getReg() != 0)
2633 MIB.addOperand(ImplicitOp);
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2634
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2635 NewMI = addOffset(MIB, 1);
2636 break;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2637 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2638 case X86::INC16r:
2639 if (DisableLEA16)
2640 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2641 : nullptr;
2642 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2643 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2644 .addOperand(Dest).addOperand(Src), 1);
2645 break;
2646 case X86::DEC64r:
2647 case X86::DEC32r: {
2648 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2649 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2650 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2651
2652 bool isKill, isUndef;
2653 unsigned SrcReg;
2654 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2655 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2656 SrcReg, isKill, isUndef, ImplicitOp))
2657 return nullptr;
2658
2659 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2660 .addOperand(Dest)
2661 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2662 if (ImplicitOp.getReg() != 0)
2663 MIB.addOperand(ImplicitOp);
2664
2665 NewMI = addOffset(MIB, -1);
2666
2667 break;
2668 }
2669 case X86::DEC16r:
2670 if (DisableLEA16)
2671 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2672 : nullptr;
2673 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2674 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2675 .addOperand(Dest).addOperand(Src), -1);
2676 break;
2677 case X86::ADD64rr:
2678 case X86::ADD64rr_DB:
2679 case X86::ADD32rr:
2680 case X86::ADD32rr_DB: {
2681 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2682 unsigned Opc;
2683 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2684 Opc = X86::LEA64r;
2685 else
2686 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2687
2688 bool isKill, isUndef;
2689 unsigned SrcReg;
2690 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2691 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2692 SrcReg, isKill, isUndef, ImplicitOp))
2693 return nullptr;
2694
2695 const MachineOperand &Src2 = MI->getOperand(2);
2696 bool isKill2, isUndef2;
2697 unsigned SrcReg2;
2698 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2699 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2700 SrcReg2, isKill2, isUndef2, ImplicitOp2))
2701 return nullptr;
2702
2703 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2704 .addOperand(Dest);
2705 if (ImplicitOp.getReg() != 0)
2706 MIB.addOperand(ImplicitOp);
2707 if (ImplicitOp2.getReg() != 0)
2708 MIB.addOperand(ImplicitOp2);
2709
2710 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2711
2712 // Preserve undefness of the operands.
2713 NewMI->getOperand(1).setIsUndef(isUndef);
2714 NewMI->getOperand(3).setIsUndef(isUndef2);
2715
2716 if (LV && Src2.isKill())
2717 LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2718 break;
2719 }
2720 case X86::ADD16rr:
2721 case X86::ADD16rr_DB: {
2722 if (DisableLEA16)
2723 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2724 : nullptr;
2725 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2726 unsigned Src2 = MI->getOperand(2).getReg();
2727 bool isKill2 = MI->getOperand(2).isKill();
2728 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2729 .addOperand(Dest),
2730 Src.getReg(), Src.isKill(), Src2, isKill2);
2731
2732 // Preserve undefness of the operands.
2733 bool isUndef = MI->getOperand(1).isUndef();
2734 bool isUndef2 = MI->getOperand(2).isUndef();
2735 NewMI->getOperand(1).setIsUndef(isUndef);
2736 NewMI->getOperand(3).setIsUndef(isUndef2);
2737
2738 if (LV && isKill2)
2739 LV->replaceKillInstruction(Src2, MI, NewMI);
2740 break;
2741 }
2742 case X86::ADD64ri32:
2743 case X86::ADD64ri8:
2744 case X86::ADD64ri32_DB:
2745 case X86::ADD64ri8_DB:
2746 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2747 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2748 .addOperand(Dest).addOperand(Src),
2749 MI->getOperand(2).getImm());
2750 break;
2751 case X86::ADD32ri:
2752 case X86::ADD32ri8:
2753 case X86::ADD32ri_DB:
2754 case X86::ADD32ri8_DB: {
2755 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2756 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2757
2758 bool isKill, isUndef;
2759 unsigned SrcReg;
2760 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2761 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2762 SrcReg, isKill, isUndef, ImplicitOp))
2763 return nullptr;
2764
2765 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2766 .addOperand(Dest)
2767 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2768 if (ImplicitOp.getReg() != 0)
2769 MIB.addOperand(ImplicitOp);
2770
2771 NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2772 break;
2773 }
2774 case X86::ADD16ri:
2775 case X86::ADD16ri8:
2776 case X86::ADD16ri_DB:
2777 case X86::ADD16ri8_DB:
2778 if (DisableLEA16)
2779 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2780 : nullptr;
2781 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2782 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2783 .addOperand(Dest).addOperand(Src),
2784 MI->getOperand(2).getImm());
2785 break;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2786 }
2787
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2788 if (!NewMI) return nullptr;
Evan Cheng1bc1cae2008-02-07 08:29:53 +0000[diff] [blame]2789
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2790 if (LV) { // Update live variables
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2791 if (Src.isKill())
2792 LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2793 if (Dest.isDead())
2794 LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2795 }
2796
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2797 MFI->insert(MBBI, NewMI); // Insert the new inst
Evan Chengdc2c8742006-11-15 20:58:11 +0000[diff] [blame]2798 return NewMI;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2799}
2800
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2801/// commuteInstruction - We have a few instructions that must be hacked on to
2802/// commute them.
2803///
Evan Cheng03553bb2008-06-16 07:33:11 +0000[diff] [blame]2804MachineInstr *
2805X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2806 switch (MI->getOpcode()) {
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2807 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2808 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2809 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]2810 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2811 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2812 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2813 unsigned Opc;
2814 unsigned Size;
2815 switch (MI->getOpcode()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]2816 default: llvm_unreachable("Unreachable!");
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2817 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2818 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2819 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2820 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]2821 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2822 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2823 }
Chris Lattner5c463782007-12-30 20:49:49 +0000[diff] [blame]2824 unsigned Amt = MI->getOperand(3).getImm();
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2825 if (NewMI) {
2826 MachineFunction &MF = *MI->getParent()->getParent();
2827 MI = MF.CloneMachineInstr(MI);
2828 NewMI = false;
Evan Cheng244183e2008-02-13 02:46:49 +0000[diff] [blame]2829 }
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2830 MI->setDesc(get(Opc));
2831 MI->getOperand(3).setImm(Size-Amt);
Jakob Stoklund Olesen9de596e2012-11-28 02:35:17 +0000[diff] [blame]2832 return TargetInstrInfo::commuteInstruction(MI, NewMI);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2833 }
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]2834 case X86::BLENDPDrri:
2835 case X86::BLENDPSrri:
2836 case X86::PBLENDWrri:
2837 case X86::VBLENDPDrri:
2838 case X86::VBLENDPSrri:
2839 case X86::VBLENDPDYrri:
2840 case X86::VBLENDPSYrri:
2841 case X86::VPBLENDDrri:
2842 case X86::VPBLENDWrri:
2843 case X86::VPBLENDDYrri:
2844 case X86::VPBLENDWYrri:{
2845 unsigned Mask;
2846 switch (MI->getOpcode()) {
2847 default: llvm_unreachable("Unreachable!");
2848 case X86::BLENDPDrri: Mask = 0x03; break;
2849 case X86::BLENDPSrri: Mask = 0x0F; break;
2850 case X86::PBLENDWrri: Mask = 0xFF; break;
2851 case X86::VBLENDPDrri: Mask = 0x03; break;
2852 case X86::VBLENDPSrri: Mask = 0x0F; break;
2853 case X86::VBLENDPDYrri: Mask = 0x0F; break;
2854 case X86::VBLENDPSYrri: Mask = 0xFF; break;
2855 case X86::VPBLENDDrri: Mask = 0x0F; break;
2856 case X86::VPBLENDWrri: Mask = 0xFF; break;
2857 case X86::VPBLENDDYrri: Mask = 0xFF; break;
2858 case X86::VPBLENDWYrri: Mask = 0xFF; break;
2859 }
Andrea Di Biagio7ecd22c2014-11-06 14:36:45 +0000[diff] [blame]2860 // Only the least significant bits of Imm are used.
2861 unsigned Imm = MI->getOperand(3).getImm() & Mask;
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]2862 if (NewMI) {
2863 MachineFunction &MF = *MI->getParent()->getParent();
2864 MI = MF.CloneMachineInstr(MI);
2865 NewMI = false;
2866 }
2867 MI->getOperand(3).setImm(Mask ^ Imm);
2868 return TargetInstrInfo::commuteInstruction(MI, NewMI);
2869 }
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]2870 case X86::PCLMULQDQrr:
2871 case X86::VPCLMULQDQrr:{
2872 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
2873 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
2874 unsigned Imm = MI->getOperand(3).getImm();
2875 unsigned Src1Hi = Imm & 0x01;
2876 unsigned Src2Hi = Imm & 0x10;
2877 if (NewMI) {
2878 MachineFunction &MF = *MI->getParent()->getParent();
2879 MI = MF.CloneMachineInstr(MI);
2880 NewMI = false;
2881 }
2882 MI->getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
2883 return TargetInstrInfo::commuteInstruction(MI, NewMI);
2884 }
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]2885 case X86::CMPPDrri:
2886 case X86::CMPPSrri:
2887 case X86::VCMPPDrri:
2888 case X86::VCMPPSrri:
2889 case X86::VCMPPDYrri:
2890 case X86::VCMPPSYrri: {
2891 // Float comparison can be safely commuted for
2892 // Ordered/Unordered/Equal/NotEqual tests
2893 unsigned Imm = MI->getOperand(3).getImm() & 0x7;
2894 switch (Imm) {
2895 case 0x00: // EQUAL
2896 case 0x03: // UNORDERED
2897 case 0x04: // NOT EQUAL
2898 case 0x07: // ORDERED
2899 if (NewMI) {
2900 MachineFunction &MF = *MI->getParent()->getParent();
2901 MI = MF.CloneMachineInstr(MI);
2902 NewMI = false;
2903 }
2904 return TargetInstrInfo::commuteInstruction(MI, NewMI);
2905 default:
2906 return nullptr;
2907 }
2908 }
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]2909 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
2910 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2911 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
2912 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2913 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2914 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
2915 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
2916 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2917 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2918 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
2919 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
2920 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2921 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
2922 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2923 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
2924 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2925 unsigned Opc;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2926 switch (MI->getOpcode()) {
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]2927 default: llvm_unreachable("Unreachable!");
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2928 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
2929 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
2930 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
2931 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2932 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2933 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2934 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
2935 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
2936 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
2937 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2938 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2939 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
Chris Lattner1a1c6002010-10-05 23:00:14 +0000[diff] [blame]2940 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2941 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2942 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2943 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
2944 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
2945 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2946 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
2947 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
2948 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
2949 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2950 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2951 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2952 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2953 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2954 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2955 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
2956 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
2957 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
2958 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
2959 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]2960 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2961 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2962 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2963 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2964 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
2965 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]2966 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2967 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2968 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2969 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]2970 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
2971 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]2972 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]2973 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2974 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2975 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2976 }
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2977 if (NewMI) {
2978 MachineFunction &MF = *MI->getParent()->getParent();
2979 MI = MF.CloneMachineInstr(MI);
2980 NewMI = false;
2981 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]2982 MI->setDesc(get(Opc));
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]2983 // Fallthrough intended.
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2984 }
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2985 default:
Jakob Stoklund Olesen9de596e2012-11-28 02:35:17 +0000[diff] [blame]2986 return TargetInstrInfo::commuteInstruction(MI, NewMI);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2987 }
2988}
2989
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]2990bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
2991 unsigned &SrcOpIdx2) const {
2992 switch (MI->getOpcode()) {
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]2993 case X86::CMPPDrri:
2994 case X86::CMPPSrri:
2995 case X86::VCMPPDrri:
2996 case X86::VCMPPSrri:
2997 case X86::VCMPPDYrri:
2998 case X86::VCMPPSYrri: {
2999 // Float comparison can be safely commuted for
3000 // Ordered/Unordered/Equal/NotEqual tests
3001 unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3002 switch (Imm) {
3003 case 0x00: // EQUAL
3004 case 0x03: // UNORDERED
3005 case 0x04: // NOT EQUAL
3006 case 0x07: // ORDERED
3007 SrcOpIdx1 = 1;
3008 SrcOpIdx2 = 2;
3009 return true;
3010 }
3011 return false;
3012 }
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3013 case X86::VFMADDPDr231r:
3014 case X86::VFMADDPSr231r:
3015 case X86::VFMADDSDr231r:
3016 case X86::VFMADDSSr231r:
3017 case X86::VFMSUBPDr231r:
3018 case X86::VFMSUBPSr231r:
3019 case X86::VFMSUBSDr231r:
3020 case X86::VFMSUBSSr231r:
3021 case X86::VFNMADDPDr231r:
3022 case X86::VFNMADDPSr231r:
3023 case X86::VFNMADDSDr231r:
3024 case X86::VFNMADDSSr231r:
3025 case X86::VFNMSUBPDr231r:
3026 case X86::VFNMSUBPSr231r:
3027 case X86::VFNMSUBSDr231r:
3028 case X86::VFNMSUBSSr231r:
3029 case X86::VFMADDPDr231rY:
3030 case X86::VFMADDPSr231rY:
3031 case X86::VFMSUBPDr231rY:
3032 case X86::VFMSUBPSr231rY:
3033 case X86::VFNMADDPDr231rY:
3034 case X86::VFNMADDPSr231rY:
3035 case X86::VFNMSUBPDr231rY:
3036 case X86::VFNMSUBPSr231rY:
3037 SrcOpIdx1 = 2;
3038 SrcOpIdx2 = 3;
3039 return true;
3040 default:
3041 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3042 }
3043}
3044
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3045static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3046 switch (BrOpc) {
3047 default: return X86::COND_INVALID;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3048 case X86::JE_1: return X86::COND_E;
3049 case X86::JNE_1: return X86::COND_NE;
3050 case X86::JL_1: return X86::COND_L;
3051 case X86::JLE_1: return X86::COND_LE;
3052 case X86::JG_1: return X86::COND_G;
3053 case X86::JGE_1: return X86::COND_GE;
3054 case X86::JB_1: return X86::COND_B;
3055 case X86::JBE_1: return X86::COND_BE;
3056 case X86::JA_1: return X86::COND_A;
3057 case X86::JAE_1: return X86::COND_AE;
3058 case X86::JS_1: return X86::COND_S;
3059 case X86::JNS_1: return X86::COND_NS;
3060 case X86::JP_1: return X86::COND_P;
3061 case X86::JNP_1: return X86::COND_NP;
3062 case X86::JO_1: return X86::COND_O;
3063 case X86::JNO_1: return X86::COND_NO;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3064 }
3065}
3066
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3067/// getCondFromSETOpc - return condition code of a SET opcode.
3068static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3069 switch (Opc) {
3070 default: return X86::COND_INVALID;
3071 case X86::SETAr: case X86::SETAm: return X86::COND_A;
3072 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3073 case X86::SETBr: case X86::SETBm: return X86::COND_B;
3074 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3075 case X86::SETEr: case X86::SETEm: return X86::COND_E;
3076 case X86::SETGr: case X86::SETGm: return X86::COND_G;
3077 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3078 case X86::SETLr: case X86::SETLm: return X86::COND_L;
3079 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3080 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3081 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3082 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3083 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3084 case X86::SETOr: case X86::SETOm: return X86::COND_O;
3085 case X86::SETPr: case X86::SETPm: return X86::COND_P;
3086 case X86::SETSr: case X86::SETSm: return X86::COND_S;
3087 }
3088}
3089
3090/// getCondFromCmovOpc - return condition code of a CMov opcode.
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]3091X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3092 switch (Opc) {
3093 default: return X86::COND_INVALID;
3094 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
3095 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
3096 return X86::COND_A;
3097 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3098 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3099 return X86::COND_AE;
3100 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
3101 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
3102 return X86::COND_B;
3103 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3104 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3105 return X86::COND_BE;
3106 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
3107 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
3108 return X86::COND_E;
3109 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
3110 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
3111 return X86::COND_G;
3112 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3113 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3114 return X86::COND_GE;
3115 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
3116 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
3117 return X86::COND_L;
3118 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3119 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3120 return X86::COND_LE;
3121 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3122 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3123 return X86::COND_NE;
3124 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3125 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3126 return X86::COND_NO;
3127 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3128 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3129 return X86::COND_NP;
3130 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3131 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3132 return X86::COND_NS;
3133 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
3134 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
3135 return X86::COND_O;
3136 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
3137 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
3138 return X86::COND_P;
3139 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
3140 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
3141 return X86::COND_S;
3142 }
3143}
3144
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3145unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3146 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3147 default: llvm_unreachable("Illegal condition code!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3148 case X86::COND_E: return X86::JE_1;
3149 case X86::COND_NE: return X86::JNE_1;
3150 case X86::COND_L: return X86::JL_1;
3151 case X86::COND_LE: return X86::JLE_1;
3152 case X86::COND_G: return X86::JG_1;
3153 case X86::COND_GE: return X86::JGE_1;
3154 case X86::COND_B: return X86::JB_1;
3155 case X86::COND_BE: return X86::JBE_1;
3156 case X86::COND_A: return X86::JA_1;
3157 case X86::COND_AE: return X86::JAE_1;
3158 case X86::COND_S: return X86::JS_1;
3159 case X86::COND_NS: return X86::JNS_1;
3160 case X86::COND_P: return X86::JP_1;
3161 case X86::COND_NP: return X86::JNP_1;
3162 case X86::COND_O: return X86::JO_1;
3163 case X86::COND_NO: return X86::JNO_1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3164 }
3165}
3166
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3167/// GetOppositeBranchCondition - Return the inverse of the specified condition,
3168/// e.g. turning COND_E to COND_NE.
3169X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3170 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3171 default: llvm_unreachable("Illegal condition code!");
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3172 case X86::COND_E: return X86::COND_NE;
3173 case X86::COND_NE: return X86::COND_E;
3174 case X86::COND_L: return X86::COND_GE;
3175 case X86::COND_LE: return X86::COND_G;
3176 case X86::COND_G: return X86::COND_LE;
3177 case X86::COND_GE: return X86::COND_L;
3178 case X86::COND_B: return X86::COND_AE;
3179 case X86::COND_BE: return X86::COND_A;
3180 case X86::COND_A: return X86::COND_BE;
3181 case X86::COND_AE: return X86::COND_B;
3182 case X86::COND_S: return X86::COND_NS;
3183 case X86::COND_NS: return X86::COND_S;
3184 case X86::COND_P: return X86::COND_NP;
3185 case X86::COND_NP: return X86::COND_P;
3186 case X86::COND_O: return X86::COND_NO;
3187 case X86::COND_NO: return X86::COND_O;
3188 }
3189}
3190
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3191/// getSwappedCondition - assume the flags are set by MI(a,b), return
3192/// the condition code if we modify the instructions such that flags are
3193/// set by MI(b,a).
Benjamin Kramerabbfe692012-07-13 13:25:15 +0000[diff] [blame]3194static X86::CondCode getSwappedCondition(X86::CondCode CC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3195 switch (CC) {
3196 default: return X86::COND_INVALID;
3197 case X86::COND_E: return X86::COND_E;
3198 case X86::COND_NE: return X86::COND_NE;
3199 case X86::COND_L: return X86::COND_G;
3200 case X86::COND_LE: return X86::COND_GE;
3201 case X86::COND_G: return X86::COND_L;
3202 case X86::COND_GE: return X86::COND_LE;
3203 case X86::COND_B: return X86::COND_A;
3204 case X86::COND_BE: return X86::COND_AE;
3205 case X86::COND_A: return X86::COND_B;
3206 case X86::COND_AE: return X86::COND_BE;
3207 }
3208}
3209
3210/// getSETFromCond - Return a set opcode for the given condition and
3211/// whether it has memory operand.
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]3212unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]3213 static const uint16_t Opc[16][2] = {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3214 { X86::SETAr, X86::SETAm },
3215 { X86::SETAEr, X86::SETAEm },
3216 { X86::SETBr, X86::SETBm },
3217 { X86::SETBEr, X86::SETBEm },
3218 { X86::SETEr, X86::SETEm },
3219 { X86::SETGr, X86::SETGm },
3220 { X86::SETGEr, X86::SETGEm },
3221 { X86::SETLr, X86::SETLm },
3222 { X86::SETLEr, X86::SETLEm },
3223 { X86::SETNEr, X86::SETNEm },
3224 { X86::SETNOr, X86::SETNOm },
3225 { X86::SETNPr, X86::SETNPm },
3226 { X86::SETNSr, X86::SETNSm },
3227 { X86::SETOr, X86::SETOm },
3228 { X86::SETPr, X86::SETPm },
3229 { X86::SETSr, X86::SETSm }
3230 };
3231
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]3232 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3233 return Opc[CC][HasMemoryOperand ? 1 : 0];
3234}
3235
3236/// getCMovFromCond - Return a cmov opcode for the given condition,
3237/// register size in bytes, and operand type.
Juergen Ributzka6ef06f92014-06-23 21:55:36 +0000[diff] [blame]3238unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3239 bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]3240 static const uint16_t Opc[32][3] = {
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3241 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
3242 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3243 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
3244 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3245 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
3246 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
3247 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3248 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
3249 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3250 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3251 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3252 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3253 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3254 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
3255 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3256 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
3257 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
3258 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3259 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
3260 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3261 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
3262 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
3263 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
3264 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
3265 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
3266 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
3267 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
3268 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
3269 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
3270 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
3271 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
3272 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3273 };
3274
3275 assert(CC < 16 && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3276 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3277 switch(RegBytes) {
3278 default: llvm_unreachable("Illegal register size!");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3279 case 2: return Opc[Idx][0];
3280 case 4: return Opc[Idx][1];
3281 case 8: return Opc[Idx][2];
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3282 }
3283}
3284
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]3285bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3286 if (!MI->isTerminator()) return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3287
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3288 // Conditional branch is a special case.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3289 if (MI->isBranch() && !MI->isBarrier())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3290 return true;
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3291 if (!MI->isPredicable())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3292 return true;
3293 return !isPredicated(MI);
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]3294}
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3295
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3296bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3297 MachineBasicBlock *&TBB,
3298 MachineBasicBlock *&FBB,
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]3299 SmallVectorImpl<MachineOperand> &Cond,
3300 bool AllowModify) const {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3301 // Start from the bottom of the block and work up, examining the
3302 // terminator instructions.
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3303 MachineBasicBlock::iterator I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3304 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3305 while (I != MBB.begin()) {
3306 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]3307 if (I->isDebugValue())
3308 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3309
3310 // Working from the bottom, when we see a non-terminator instruction, we're
3311 // done.
Jakob Stoklund Olesenc30b4dd2010-07-16 17:41:44 +0000[diff] [blame]3312 if (!isUnpredicatedTerminator(I))
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3313 break;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3314
3315 // A terminator that isn't a branch can't easily be handled by this
3316 // analysis.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3317 if (!I->isBranch())
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3318 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3319
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3320 // Handle unconditional branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3321 if (I->getOpcode() == X86::JMP_1) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3322 UnCondBrIter = I;
3323
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]3324 if (!AllowModify) {
3325 TBB = I->getOperand(0).getMBB();
Evan Cheng2fa28112009-05-08 06:34:09 +0000[diff] [blame]3326 continue;
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]3327 }
3328
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3329 // If the block has any instructions after a JMP, delete them.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]3330 while (std::next(I) != MBB.end())
3331 std::next(I)->eraseFromParent();
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3332
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3333 Cond.clear();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3334 FBB = nullptr;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3335
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3336 // Delete the JMP if it's equivalent to a fall-through.
3337 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3338 TBB = nullptr;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3339 I->eraseFromParent();
3340 I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3341 UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3342 continue;
3343 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3344
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3345 // TBB is used to indicate the unconditional destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3346 TBB = I->getOperand(0).getMBB();
3347 continue;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3348 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3349
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3350 // Handle conditional branches.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3351 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3352 if (BranchCode == X86::COND_INVALID)
3353 return true; // Can't handle indirect branch.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3354
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3355 // Working from the bottom, handle the first conditional branch.
3356 if (Cond.empty()) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3357 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3358 if (AllowModify && UnCondBrIter != MBB.end() &&
3359 MBB.isLayoutSuccessor(TargetBB)) {
3360 // If we can modify the code and it ends in something like:
3361 //
3362 // jCC L1
3363 // jmp L2
3364 // L1:
3365 // ...
3366 // L2:
3367 //
3368 // Then we can change this to:
3369 //
3370 // jnCC L2
3371 // L1:
3372 // ...
3373 // L2:
3374 //
3375 // Which is a bit more efficient.
3376 // We conditionally jump to the fall-through block.
3377 BranchCode = GetOppositeBranchCondition(BranchCode);
3378 unsigned JNCC = GetCondBranchFromCond(BranchCode);
3379 MachineBasicBlock::iterator OldInst = I;
3380
3381 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
3382 .addMBB(UnCondBrIter->getOperand(0).getMBB());
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3383 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3384 .addMBB(TargetBB);
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3385
3386 OldInst->eraseFromParent();
3387 UnCondBrIter->eraseFromParent();
3388
3389 // Restart the analysis.
3390 UnCondBrIter = MBB.end();
3391 I = MBB.end();
3392 continue;
3393 }
3394
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3395 FBB = TBB;
3396 TBB = I->getOperand(0).getMBB();
3397 Cond.push_back(MachineOperand::CreateImm(BranchCode));
3398 continue;
3399 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3400
3401 // Handle subsequent conditional branches. Only handle the case where all
3402 // conditional branches branch to the same destination and their condition
3403 // opcodes fit one of the special multi-branch idioms.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3404 assert(Cond.size() == 1);
3405 assert(TBB);
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3406
3407 // Only handle the case where all conditional branches branch to the same
3408 // destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3409 if (TBB != I->getOperand(0).getMBB())
3410 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3411
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3412 // If the conditions are the same, we can leave them alone.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3413 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3414 if (OldBranchCode == BranchCode)
3415 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3416
3417 // If they differ, see if they fit one of the known patterns. Theoretically,
3418 // we could handle more patterns here, but we shouldn't expect to see them
3419 // if instruction selection has done a reasonable job.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3420 if ((OldBranchCode == X86::COND_NP &&
3421 BranchCode == X86::COND_E) ||
3422 (OldBranchCode == X86::COND_E &&
3423 BranchCode == X86::COND_NP))
3424 BranchCode = X86::COND_NP_OR_E;
3425 else if ((OldBranchCode == X86::COND_P &&
3426 BranchCode == X86::COND_NE) ||
3427 (OldBranchCode == X86::COND_NE &&
3428 BranchCode == X86::COND_P))
3429 BranchCode = X86::COND_NE_OR_P;
3430 else
3431 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3432
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3433 // Update the MachineOperand.
3434 Cond[0].setImm(BranchCode);
Chris Lattner74436002006-10-30 22:27:23 +0000[diff] [blame]3435 }
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3436
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3437 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3438}
3439
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]3440unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3441 MachineBasicBlock::iterator I = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3442 unsigned Count = 0;
3443
3444 while (I != MBB.begin()) {
3445 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]3446 if (I->isDebugValue())
3447 continue;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3448 if (I->getOpcode() != X86::JMP_1 &&
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3449 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3450 break;
3451 // Remove the branch.
3452 I->eraseFromParent();
3453 I = MBB.end();
3454 ++Count;
3455 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3456
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3457 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3458}
3459
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]3460unsigned
3461X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
3462 MachineBasicBlock *FBB,
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]3463 const SmallVectorImpl<MachineOperand> &Cond,
3464 DebugLoc DL) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3465 // Shouldn't be a fall through.
3466 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
Chris Lattner6fca75e2006-10-21 05:34:23 +0000[diff] [blame]3467 assert((Cond.size() == 1 || Cond.size() == 0) &&
3468 "X86 branch conditions have one component!");
3469
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3470 if (Cond.empty()) {
3471 // Unconditional branch?
3472 assert(!FBB && "Unconditional branch with multiple successors!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3473 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]3474 return 1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3475 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3476
3477 // Conditional branch.
3478 unsigned Count = 0;
3479 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3480 switch (CC) {
3481 case X86::COND_NP_OR_E:
3482 // Synthesize NP_OR_E with two branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3483 BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3484 ++Count;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3485 BuildMI(&MBB, DL, get(X86::JE_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3486 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3487 break;
3488 case X86::COND_NE_OR_P:
3489 // Synthesize NE_OR_P with two branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3490 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3491 ++Count;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3492 BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3493 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3494 break;
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3495 default: {
3496 unsigned Opc = GetCondBranchFromCond(CC);
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]3497 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3498 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3499 }
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3500 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3501 if (FBB) {
3502 // Two-way Conditional branch. Insert the second branch.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3503 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3504 ++Count;
3505 }
3506 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3507}
3508
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3509bool X86InstrInfo::
3510canInsertSelect(const MachineBasicBlock &MBB,
3511 const SmallVectorImpl<MachineOperand> &Cond,
3512 unsigned TrueReg, unsigned FalseReg,
3513 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
3514 // Not all subtargets have cmov instructions.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3515 if (!Subtarget.hasCMov())
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3516 return false;
3517 if (Cond.size() != 1)
3518 return false;
3519 // We cannot do the composite conditions, at least not in SSA form.
3520 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
3521 return false;
3522
3523 // Check register classes.
3524 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3525 const TargetRegisterClass *RC =
3526 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3527 if (!RC)
3528 return false;
3529
3530 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3531 if (X86::GR16RegClass.hasSubClassEq(RC) ||
3532 X86::GR32RegClass.hasSubClassEq(RC) ||
3533 X86::GR64RegClass.hasSubClassEq(RC)) {
3534 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3535 // Bridge. Probably Ivy Bridge as well.
3536 CondCycles = 2;
3537 TrueCycles = 2;
3538 FalseCycles = 2;
3539 return true;
3540 }
3541
3542 // Can't do vectors.
3543 return false;
3544}
3545
3546void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3547 MachineBasicBlock::iterator I, DebugLoc DL,
3548 unsigned DstReg,
3549 const SmallVectorImpl<MachineOperand> &Cond,
3550 unsigned TrueReg, unsigned FalseReg) const {
3551 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3552 assert(Cond.size() == 1 && "Invalid Cond array");
3553 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3554 MRI.getRegClass(DstReg)->getSize(),
3555 false/*HasMemoryOperand*/);
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3556 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
3557}
3558
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]3559/// isHReg - Test if the given register is a physical h register.
3560static bool isHReg(unsigned Reg) {
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]3561 return X86::GR8_ABCD_HRegClass.contains(Reg);
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]3562}
3563
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3564// Try and copy between VR128/VR64 and GR64 registers.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3565static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3566 const X86Subtarget &Subtarget) {
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3567
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3568 // SrcReg(VR128) -> DestReg(GR64)
3569 // SrcReg(VR64) -> DestReg(GR64)
3570 // SrcReg(GR64) -> DestReg(VR128)
3571 // SrcReg(GR64) -> DestReg(VR64)
3572
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3573 bool HasAVX = Subtarget.hasAVX();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3574 bool HasAVX512 = Subtarget.hasAVX512();
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3575 if (X86::GR64RegClass.contains(DestReg)) {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3576 if (X86::VR128XRegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3577 // Copy from a VR128 register to a GR64 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3578 return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
3579 X86::MOVPQIto64rr);
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3580 if (X86::VR64RegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3581 // Copy from a VR64 register to a GR64 register.
3582 return X86::MOVSDto64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3583 } else if (X86::GR64RegClass.contains(SrcReg)) {
3584 // Copy from a GR64 register to a VR128 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3585 if (X86::VR128XRegClass.contains(DestReg))
3586 return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
3587 X86::MOV64toPQIrr);
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3588 // Copy from a GR64 register to a VR64 register.
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3589 if (X86::VR64RegClass.contains(DestReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3590 return X86::MOV64toSDrr;
3591 }
3592
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]3593 // SrcReg(FR32) -> DestReg(GR32)
3594 // SrcReg(GR32) -> DestReg(FR32)
3595
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3596 if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3597 // Copy from a FR32 register to a GR32 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3598 return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]3599
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3600 if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3601 // Copy from a GR32 register to a FR32 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3602 return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3603 return 0;
3604}
3605
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3606inline static bool MaskRegClassContains(unsigned Reg) {
3607 return X86::VK8RegClass.contains(Reg) ||
3608 X86::VK16RegClass.contains(Reg) ||
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]3609 X86::VK32RegClass.contains(Reg) ||
3610 X86::VK64RegClass.contains(Reg) ||
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3611 X86::VK1RegClass.contains(Reg);
3612}
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3613static
3614unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
3615 if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
3616 X86::VR256XRegClass.contains(DestReg, SrcReg) ||
3617 X86::VR512RegClass.contains(DestReg, SrcReg)) {
3618 DestReg = get512BitSuperRegister(DestReg);
3619 SrcReg = get512BitSuperRegister(SrcReg);
3620 return X86::VMOVAPSZrr;
3621 }
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3622 if (MaskRegClassContains(DestReg) &&
3623 MaskRegClassContains(SrcReg))
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3624 return X86::KMOVWkk;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3625 if (MaskRegClassContains(DestReg) &&
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]3626 (X86::GR32RegClass.contains(SrcReg) ||
3627 X86::GR16RegClass.contains(SrcReg) ||
3628 X86::GR8RegClass.contains(SrcReg))) {
3629 SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
3630 return X86::KMOVWkr;
3631 }
3632 if ((X86::GR32RegClass.contains(DestReg) ||
3633 X86::GR16RegClass.contains(DestReg) ||
3634 X86::GR8RegClass.contains(DestReg)) &&
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3635 MaskRegClassContains(SrcReg)) {
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]3636 DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
3637 return X86::KMOVWrk;
3638 }
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3639 return 0;
3640}
3641
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3642void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3643 MachineBasicBlock::iterator MI, DebugLoc DL,
3644 unsigned DestReg, unsigned SrcReg,
3645 bool KillSrc) const {
3646 // First deal with the normal symmetric copies.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3647 bool HasAVX = Subtarget.hasAVX();
3648 bool HasAVX512 = Subtarget.hasAVX512();
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3649 unsigned Opc = 0;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3650 if (X86::GR64RegClass.contains(DestReg, SrcReg))
3651 Opc = X86::MOV64rr;
3652 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3653 Opc = X86::MOV32rr;
3654 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3655 Opc = X86::MOV16rr;
3656 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3657 // Copying to or from a physical H register on x86-64 requires a NOREX
3658 // move. Otherwise use a normal move.
3659 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3660 Subtarget.is64Bit()) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3661 Opc = X86::MOV8rr_NOREX;
Jakob Stoklund Olesen464fcc02011-10-07 20:15:54 +0000[diff] [blame]3662 // Both operands must be encodable without an REX prefix.
3663 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3664 "8-bit H register can not be copied outside GR8_NOREX");
3665 } else
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3666 Opc = X86::MOV8rr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3667 }
3668 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3669 Opc = X86::MMX_MOVQ64rr;
3670 else if (HasAVX512)
3671 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
3672 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3673 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]3674 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3675 Opc = X86::VMOVAPSYrr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3676 if (!Opc)
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3677 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3678
3679 if (Opc) {
3680 BuildMI(MBB, MI, DL, get(Opc), DestReg)
3681 .addReg(SrcReg, getKillRegState(KillSrc));
3682 return;
3683 }
3684
3685 // Moving EFLAGS to / from another register requires a push and a pop.
Nadav Rotemd5aae982012-12-21 23:48:49 +0000[diff] [blame]3686 // Notice that we have to adjust the stack if we don't want to clobber the
JF Bastienac8b66b2014-08-05 23:27:34 +0000[diff] [blame]3687 // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3688 if (SrcReg == X86::EFLAGS) {
3689 if (X86::GR64RegClass.contains(DestReg)) {
3690 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
3691 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
3692 return;
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3693 }
3694 if (X86::GR32RegClass.contains(DestReg)) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3695 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
3696 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
3697 return;
3698 }
3699 }
3700 if (DestReg == X86::EFLAGS) {
3701 if (X86::GR64RegClass.contains(SrcReg)) {
3702 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
3703 .addReg(SrcReg, getKillRegState(KillSrc));
3704 BuildMI(MBB, MI, DL, get(X86::POPF64));
3705 return;
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3706 }
3707 if (X86::GR32RegClass.contains(SrcReg)) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3708 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
3709 .addReg(SrcReg, getKillRegState(KillSrc));
3710 BuildMI(MBB, MI, DL, get(X86::POPF32));
3711 return;
3712 }
3713 }
3714
3715 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
3716 << " to " << RI.getName(DestReg) << '\n');
3717 llvm_unreachable("Cannot emit physreg copy instruction");
3718}
3719
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3720static unsigned getLoadStoreRegOpcode(unsigned Reg,
3721 const TargetRegisterClass *RC,
3722 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3723 const X86Subtarget &STI,
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3724 bool load) {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3725 if (STI.hasAVX512()) {
Andrew Trick8460a3b2013-10-14 22:18:56 +0000[diff] [blame]3726 if (X86::VK8RegClass.hasSubClassEq(RC) ||
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3727 X86::VK16RegClass.hasSubClassEq(RC))
3728 return load ? X86::KMOVWkm : X86::KMOVWmk;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]3729 if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3730 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]3731 if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3732 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]3733 if (X86::VR512RegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3734 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3735 }
3736
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3737 bool HasAVX = STI.hasAVX();
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3738 switch (RC->getSize()) {
Rafael Espindola6635f982010-07-12 03:43:04 +0000[diff] [blame]3739 default:
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3740 llvm_unreachable("Unknown spill size");
3741 case 1:
3742 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3743 if (STI.is64Bit())
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3744 // Copying to or from a physical H register on x86-64 requires a NOREX
3745 // move. Otherwise use a normal move.
3746 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3747 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3748 return load ? X86::MOV8rm : X86::MOV8mr;
3749 case 2:
3750 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3751 return load ? X86::MOV16rm : X86::MOV16mr;
3752 case 4:
3753 if (X86::GR32RegClass.hasSubClassEq(RC))
3754 return load ? X86::MOV32rm : X86::MOV32mr;
3755 if (X86::FR32RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3756 return load ?
3757 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3758 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3759 if (X86::RFP32RegClass.hasSubClassEq(RC))
3760 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3761 llvm_unreachable("Unknown 4-byte regclass");
3762 case 8:
3763 if (X86::GR64RegClass.hasSubClassEq(RC))
3764 return load ? X86::MOV64rm : X86::MOV64mr;
3765 if (X86::FR64RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3766 return load ?
3767 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3768 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3769 if (X86::VR64RegClass.hasSubClassEq(RC))
3770 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3771 if (X86::RFP64RegClass.hasSubClassEq(RC))
3772 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3773 llvm_unreachable("Unknown 8-byte regclass");
3774 case 10:
3775 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3776 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]3777 case 16: {
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3778 assert((X86::VR128RegClass.hasSubClassEq(RC) ||
3779 X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3780 // If stack is realigned we can use aligned stores.
3781 if (isStackAligned)
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]3782 return load ?
3783 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
3784 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3785 else
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]3786 return load ?
3787 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
3788 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
3789 }
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]3790 case 32:
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3791 assert((X86::VR256RegClass.hasSubClassEq(RC) ||
3792 X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]3793 // If stack is realigned we can use aligned stores.
3794 if (isStackAligned)
3795 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
3796 else
3797 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3798 case 64:
3799 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3800 if (isStackAligned)
3801 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3802 else
3803 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3804 }
3805}
3806
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]3807static unsigned getStoreRegOpcode(unsigned SrcReg,
3808 const TargetRegisterClass *RC,
3809 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3810 const X86Subtarget &STI) {
3811 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3812}
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3813
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3814
3815static unsigned getLoadRegOpcode(unsigned DestReg,
3816 const TargetRegisterClass *RC,
3817 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3818 const X86Subtarget &STI) {
3819 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3820}
3821
3822void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3823 MachineBasicBlock::iterator MI,
3824 unsigned SrcReg, bool isKill, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]3825 const TargetRegisterClass *RC,
3826 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]3827 const MachineFunction &MF = *MBB.getParent();
Jakob Stoklund Olesenc3c05ed2010-07-27 04:16:58 +0000[diff] [blame]3828 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
3829 "Stack slot too small for store");
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3830 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]3831 bool isAligned =
3832 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3833 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3834 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]3835 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]3836 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]3837 .addReg(SrcReg, getKillRegState(isKill));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3838}
3839
3840void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
3841 bool isKill,
3842 SmallVectorImpl<MachineOperand> &Addr,
3843 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3844 MachineInstr::mmo_iterator MMOBegin,
3845 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3846 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3847 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3848 bool isAligned = MMOBegin != MMOEnd &&
3849 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3850 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]3851 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]3852 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3853 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]3854 MIB.addOperand(Addr[i]);
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]3855 MIB.addReg(SrcReg, getKillRegState(isKill));
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3856 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3857 NewMIs.push_back(MIB);
3858}
3859
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3860
3861void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]3862 MachineBasicBlock::iterator MI,
3863 unsigned DestReg, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]3864 const TargetRegisterClass *RC,
3865 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]3866 const MachineFunction &MF = *MBB.getParent();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3867 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]3868 bool isAligned =
3869 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3870 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3871 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]3872 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]3873 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3874}
3875
3876void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3877 SmallVectorImpl<MachineOperand> &Addr,
3878 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3879 MachineInstr::mmo_iterator MMOBegin,
3880 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3881 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3882 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3883 bool isAligned = MMOBegin != MMOEnd &&
3884 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3885 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]3886 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]3887 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3888 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]3889 MIB.addOperand(Addr[i]);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3890 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3891 NewMIs.push_back(MIB);
3892}
3893
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3894bool X86InstrInfo::
3895analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
3896 int &CmpMask, int &CmpValue) const {
3897 switch (MI->getOpcode()) {
3898 default: break;
3899 case X86::CMP64ri32:
3900 case X86::CMP64ri8:
3901 case X86::CMP32ri:
3902 case X86::CMP32ri8:
3903 case X86::CMP16ri:
3904 case X86::CMP16ri8:
3905 case X86::CMP8ri:
3906 SrcReg = MI->getOperand(0).getReg();
3907 SrcReg2 = 0;
3908 CmpMask = ~0;
3909 CmpValue = MI->getOperand(1).getImm();
3910 return true;
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]3911 // A SUB can be used to perform comparison.
3912 case X86::SUB64rm:
3913 case X86::SUB32rm:
3914 case X86::SUB16rm:
3915 case X86::SUB8rm:
3916 SrcReg = MI->getOperand(1).getReg();
3917 SrcReg2 = 0;
3918 CmpMask = ~0;
3919 CmpValue = 0;
3920 return true;
3921 case X86::SUB64rr:
3922 case X86::SUB32rr:
3923 case X86::SUB16rr:
3924 case X86::SUB8rr:
3925 SrcReg = MI->getOperand(1).getReg();
3926 SrcReg2 = MI->getOperand(2).getReg();
3927 CmpMask = ~0;
3928 CmpValue = 0;
3929 return true;
3930 case X86::SUB64ri32:
3931 case X86::SUB64ri8:
3932 case X86::SUB32ri:
3933 case X86::SUB32ri8:
3934 case X86::SUB16ri:
3935 case X86::SUB16ri8:
3936 case X86::SUB8ri:
3937 SrcReg = MI->getOperand(1).getReg();
3938 SrcReg2 = 0;
3939 CmpMask = ~0;
3940 CmpValue = MI->getOperand(2).getImm();
3941 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3942 case X86::CMP64rr:
3943 case X86::CMP32rr:
3944 case X86::CMP16rr:
3945 case X86::CMP8rr:
3946 SrcReg = MI->getOperand(0).getReg();
3947 SrcReg2 = MI->getOperand(1).getReg();
3948 CmpMask = ~0;
3949 CmpValue = 0;
3950 return true;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3951 case X86::TEST8rr:
3952 case X86::TEST16rr:
3953 case X86::TEST32rr:
3954 case X86::TEST64rr:
3955 SrcReg = MI->getOperand(0).getReg();
3956 if (MI->getOperand(1).getReg() != SrcReg) return false;
3957 // Compare against zero.
3958 SrcReg2 = 0;
3959 CmpMask = ~0;
3960 CmpValue = 0;
3961 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3962 }
3963 return false;
3964}
3965
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3966/// isRedundantFlagInstr - check whether the first instruction, whose only
3967/// purpose is to update flags, can be made redundant.
3968/// CMPrr can be made redundant by SUBrr if the operands are the same.
3969/// This function can be extended later on.
3970/// SrcReg, SrcRegs: register operands for FlagI.
3971/// ImmValue: immediate for FlagI if it takes an immediate.
3972inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
3973 unsigned SrcReg2, int ImmValue,
3974 MachineInstr *OI) {
3975 if (((FlagI->getOpcode() == X86::CMP64rr &&
3976 OI->getOpcode() == X86::SUB64rr) ||
3977 (FlagI->getOpcode() == X86::CMP32rr &&
3978 OI->getOpcode() == X86::SUB32rr)||
3979 (FlagI->getOpcode() == X86::CMP16rr &&
3980 OI->getOpcode() == X86::SUB16rr)||
3981 (FlagI->getOpcode() == X86::CMP8rr &&
3982 OI->getOpcode() == X86::SUB8rr)) &&
3983 ((OI->getOperand(1).getReg() == SrcReg &&
3984 OI->getOperand(2).getReg() == SrcReg2) ||
3985 (OI->getOperand(1).getReg() == SrcReg2 &&
3986 OI->getOperand(2).getReg() == SrcReg)))
3987 return true;
3988
3989 if (((FlagI->getOpcode() == X86::CMP64ri32 &&
3990 OI->getOpcode() == X86::SUB64ri32) ||
3991 (FlagI->getOpcode() == X86::CMP64ri8 &&
3992 OI->getOpcode() == X86::SUB64ri8) ||
3993 (FlagI->getOpcode() == X86::CMP32ri &&
3994 OI->getOpcode() == X86::SUB32ri) ||
3995 (FlagI->getOpcode() == X86::CMP32ri8 &&
3996 OI->getOpcode() == X86::SUB32ri8) ||
3997 (FlagI->getOpcode() == X86::CMP16ri &&
3998 OI->getOpcode() == X86::SUB16ri) ||
3999 (FlagI->getOpcode() == X86::CMP16ri8 &&
4000 OI->getOpcode() == X86::SUB16ri8) ||
4001 (FlagI->getOpcode() == X86::CMP8ri &&
4002 OI->getOpcode() == X86::SUB8ri)) &&
4003 OI->getOperand(1).getReg() == SrcReg &&
4004 OI->getOperand(2).getImm() == ImmValue)
4005 return true;
4006 return false;
4007}
4008
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4009/// isDefConvertible - check whether the definition can be converted
4010/// to remove a comparison against zero.
4011inline static bool isDefConvertible(MachineInstr *MI) {
4012 switch (MI->getOpcode()) {
4013 default: return false;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]4014
4015 // The shift instructions only modify ZF if their shift count is non-zero.
4016 // N.B.: The processor truncates the shift count depending on the encoding.
4017 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
4018 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
4019 return getTruncatedShiftCount(MI, 2) != 0;
4020
4021 // Some left shift instructions can be turned into LEA instructions but only
4022 // if their flags aren't used. Avoid transforming such instructions.
4023 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
4024 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4025 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
4026 return ShAmt != 0;
4027 }
4028
4029 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
4030 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
4031 return getTruncatedShiftCount(MI, 3) != 0;
4032
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4033 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
4034 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
4035 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
4036 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
4037 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]4038 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4039 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4040 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
4041 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
4042 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
4043 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]4044 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4045 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
4046 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
4047 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
4048 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
4049 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
4050 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
4051 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
4052 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
4053 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
4054 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
4055 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
4056 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
4057 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
4058 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
4059 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]4060 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
4061 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
4062 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
4063 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
4064 case X86::ADC32ri: case X86::ADC32ri8:
4065 case X86::ADC32rr: case X86::ADC64ri32:
4066 case X86::ADC64ri8: case X86::ADC64rr:
4067 case X86::SBB32ri: case X86::SBB32ri8:
4068 case X86::SBB32rr: case X86::SBB64ri32:
4069 case X86::SBB64ri8: case X86::SBB64rr:
Craig Topperf3ff6ae2012-12-17 05:12:30 +0000[diff] [blame]4070 case X86::ANDN32rr: case X86::ANDN32rm:
4071 case X86::ANDN64rr: case X86::ANDN64rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]4072 case X86::BEXTR32rr: case X86::BEXTR64rr:
4073 case X86::BEXTR32rm: case X86::BEXTR64rm:
4074 case X86::BLSI32rr: case X86::BLSI32rm:
4075 case X86::BLSI64rr: case X86::BLSI64rm:
4076 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
4077 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
4078 case X86::BLSR32rr: case X86::BLSR32rm:
4079 case X86::BLSR64rr: case X86::BLSR64rm:
4080 case X86::BZHI32rr: case X86::BZHI32rm:
4081 case X86::BZHI64rr: case X86::BZHI64rm:
4082 case X86::LZCNT16rr: case X86::LZCNT16rm:
4083 case X86::LZCNT32rr: case X86::LZCNT32rm:
4084 case X86::LZCNT64rr: case X86::LZCNT64rm:
4085 case X86::POPCNT16rr:case X86::POPCNT16rm:
4086 case X86::POPCNT32rr:case X86::POPCNT32rm:
4087 case X86::POPCNT64rr:case X86::POPCNT64rm:
4088 case X86::TZCNT16rr: case X86::TZCNT16rm:
4089 case X86::TZCNT32rr: case X86::TZCNT32rm:
4090 case X86::TZCNT64rr: case X86::TZCNT64rm:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4091 return true;
4092 }
4093}
4094
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4095/// isUseDefConvertible - check whether the use can be converted
4096/// to remove a comparison against zero.
4097static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
4098 switch (MI->getOpcode()) {
4099 default: return X86::COND_INVALID;
4100 case X86::LZCNT16rr: case X86::LZCNT16rm:
4101 case X86::LZCNT32rr: case X86::LZCNT32rm:
4102 case X86::LZCNT64rr: case X86::LZCNT64rm:
4103 return X86::COND_B;
4104 case X86::POPCNT16rr:case X86::POPCNT16rm:
4105 case X86::POPCNT32rr:case X86::POPCNT32rm:
4106 case X86::POPCNT64rr:case X86::POPCNT64rm:
4107 return X86::COND_E;
4108 case X86::TZCNT16rr: case X86::TZCNT16rm:
4109 case X86::TZCNT32rr: case X86::TZCNT32rm:
4110 case X86::TZCNT64rr: case X86::TZCNT64rm:
4111 return X86::COND_B;
4112 }
4113}
4114
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4115/// optimizeCompareInstr - Check if there exists an earlier instruction that
4116/// operates on the same source operands and sets flags in the same way as
4117/// Compare; remove Compare if possible.
4118bool X86InstrInfo::
4119optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
4120 int CmpMask, int CmpValue,
4121 const MachineRegisterInfo *MRI) const {
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4122 // Check whether we can replace SUB with CMP.
4123 unsigned NewOpcode = 0;
4124 switch (CmpInstr->getOpcode()) {
4125 default: break;
4126 case X86::SUB64ri32:
4127 case X86::SUB64ri8:
4128 case X86::SUB32ri:
4129 case X86::SUB32ri8:
4130 case X86::SUB16ri:
4131 case X86::SUB16ri8:
4132 case X86::SUB8ri:
4133 case X86::SUB64rm:
4134 case X86::SUB32rm:
4135 case X86::SUB16rm:
4136 case X86::SUB8rm:
4137 case X86::SUB64rr:
4138 case X86::SUB32rr:
4139 case X86::SUB16rr:
4140 case X86::SUB8rr: {
4141 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
4142 return false;
4143 // There is no use of the destination register, we can replace SUB with CMP.
4144 switch (CmpInstr->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]4145 default: llvm_unreachable("Unreachable!");
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4146 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
4147 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
4148 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
4149 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
4150 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
4151 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
4152 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
4153 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
4154 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
4155 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
4156 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
4157 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
4158 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
4159 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
4160 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
4161 }
4162 CmpInstr->setDesc(get(NewOpcode));
4163 CmpInstr->RemoveOperand(0);
4164 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
4165 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4166 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4167 return false;
4168 }
4169 }
4170
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4171 // Get the unique definition of SrcReg.
4172 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
4173 if (!MI) return false;
4174
4175 // CmpInstr is the first instruction of the BB.
4176 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
4177
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4178 // If we are comparing against zero, check whether we can use MI to update
4179 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
4180 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4181 if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4182 return false;
4183
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4184 // If we have a use of the source register between the def and our compare
4185 // instruction we can eliminate the compare iff the use sets EFLAGS in the
4186 // right way.
4187 bool ShouldUpdateCC = false;
4188 X86::CondCode NewCC = X86::COND_INVALID;
4189 if (IsCmpZero && !isDefConvertible(MI)) {
4190 // Scan forward from the use until we hit the use we're looking for or the
4191 // compare instruction.
4192 for (MachineBasicBlock::iterator J = MI;; ++J) {
4193 // Do we have a convertible instruction?
4194 NewCC = isUseDefConvertible(J);
4195 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
4196 J->getOperand(1).getReg() == SrcReg) {
4197 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
4198 ShouldUpdateCC = true; // Update CC later on.
4199 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
4200 // with the new def.
4201 MI = Def = J;
4202 break;
4203 }
4204
4205 if (J == I)
4206 return false;
4207 }
4208 }
4209
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4210 // We are searching for an earlier instruction that can make CmpInstr
4211 // redundant and that instruction will be saved in Sub.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4212 MachineInstr *Sub = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4213 const TargetRegisterInfo *TRI = &getRegisterInfo();
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4214
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4215 // We iterate backward, starting from the instruction before CmpInstr and
4216 // stop when reaching the definition of a source register or done with the BB.
4217 // RI points to the instruction before CmpInstr.
4218 // If the definition is in this basic block, RE points to the definition;
4219 // otherwise, RE is the rend of the basic block.
4220 MachineBasicBlock::reverse_iterator
4221 RI = MachineBasicBlock::reverse_iterator(I),
4222 RE = CmpInstr->getParent() == MI->getParent() ?
4223 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
4224 CmpInstr->getParent()->rend();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4225 MachineInstr *Movr0Inst = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4226 for (; RI != RE; ++RI) {
4227 MachineInstr *Instr = &*RI;
4228 // Check whether CmpInstr can be made redundant by the current instruction.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4229 if (!IsCmpZero &&
4230 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4231 Sub = Instr;
4232 break;
4233 }
4234
4235 if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4236 Instr->readsRegister(X86::EFLAGS, TRI)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4237 // This instruction modifies or uses EFLAGS.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4238
4239 // MOV32r0 etc. are implemented with xor which clobbers condition code.
4240 // They are safe to move up, if the definition to EFLAGS is dead and
4241 // earlier instructions do not read or write EFLAGS.
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]4242 if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4243 Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
4244 Movr0Inst = Instr;
4245 continue;
4246 }
4247
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4248 // We can't remove CmpInstr.
4249 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4250 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4251 }
4252
4253 // Return false if no candidates exist.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4254 if (!IsCmpZero && !Sub)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4255 return false;
4256
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4257 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
4258 Sub->getOperand(2).getReg() == SrcReg);
4259
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4260 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4261 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
4262 // If we are done with the basic block, we need to check whether EFLAGS is
4263 // live-out.
4264 bool IsSafe = false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4265 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
4266 MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
4267 for (++I; I != E; ++I) {
4268 const MachineInstr &Instr = *I;
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]4269 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
4270 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
4271 // We should check the usage if this instruction uses and updates EFLAGS.
4272 if (!UseEFLAGS && ModifyEFLAGS) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4273 // It is safe to remove CmpInstr if EFLAGS is updated again.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4274 IsSafe = true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4275 break;
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4276 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]4277 if (!UseEFLAGS && !ModifyEFLAGS)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4278 continue;
4279
4280 // EFLAGS is used by this instruction.
Nick Lewycky0a9a8662014-06-04 07:45:54 +0000[diff] [blame]4281 X86::CondCode OldCC = X86::COND_INVALID;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4282 bool OpcIsSET = false;
4283 if (IsCmpZero || IsSwapped) {
4284 // We decode the condition code from opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4285 if (Instr.isBranch())
4286 OldCC = getCondFromBranchOpc(Instr.getOpcode());
4287 else {
4288 OldCC = getCondFromSETOpc(Instr.getOpcode());
4289 if (OldCC != X86::COND_INVALID)
4290 OpcIsSET = true;
4291 else
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]4292 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4293 }
4294 if (OldCC == X86::COND_INVALID) return false;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4295 }
4296 if (IsCmpZero) {
4297 switch (OldCC) {
4298 default: break;
4299 case X86::COND_A: case X86::COND_AE:
4300 case X86::COND_B: case X86::COND_BE:
4301 case X86::COND_G: case X86::COND_GE:
4302 case X86::COND_L: case X86::COND_LE:
4303 case X86::COND_O: case X86::COND_NO:
4304 // CF and OF are used, we can't perform this optimization.
4305 return false;
4306 }
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4307
4308 // If we're updating the condition code check if we have to reverse the
4309 // condition.
4310 if (ShouldUpdateCC)
4311 switch (OldCC) {
4312 default:
4313 return false;
4314 case X86::COND_E:
4315 break;
4316 case X86::COND_NE:
4317 NewCC = GetOppositeBranchCondition(NewCC);
4318 break;
4319 }
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4320 } else if (IsSwapped) {
4321 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4322 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4323 // We swap the condition code and synthesize the new opcode.
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4324 NewCC = getSwappedCondition(OldCC);
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4325 if (NewCC == X86::COND_INVALID) return false;
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4326 }
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4327
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4328 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4329 // Synthesize the new opcode.
4330 bool HasMemoryOperand = Instr.hasOneMemOperand();
4331 unsigned NewOpc;
4332 if (Instr.isBranch())
4333 NewOpc = GetCondBranchFromCond(NewCC);
4334 else if(OpcIsSET)
4335 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
4336 else {
4337 unsigned DstReg = Instr.getOperand(0).getReg();
4338 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
4339 HasMemoryOperand);
4340 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4341
4342 // Push the MachineInstr to OpsToUpdate.
4343 // If it is safe to remove CmpInstr, the condition code of these
4344 // instructions will be modified.
4345 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
4346 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]4347 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4348 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4349 IsSafe = true;
4350 break;
4351 }
4352 }
4353
4354 // If EFLAGS is not killed nor re-defined, we should check whether it is
4355 // live-out. If it is live-out, do not optimize.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4356 if ((IsCmpZero || IsSwapped) && !IsSafe) {
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4357 MachineBasicBlock *MBB = CmpInstr->getParent();
4358 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
4359 SE = MBB->succ_end(); SI != SE; ++SI)
4360 if ((*SI)->isLiveIn(X86::EFLAGS))
4361 return false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4362 }
4363
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4364 // The instruction to be updated is either Sub or MI.
4365 Sub = IsCmpZero ? MI : Sub;
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]4366 // Move Movr0Inst to the appropriate place before Sub.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4367 if (Movr0Inst) {
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]4368 // Look backwards until we find a def that doesn't use the current EFLAGS.
4369 Def = Sub;
4370 MachineBasicBlock::reverse_iterator
4371 InsertI = MachineBasicBlock::reverse_iterator(++Def),
4372 InsertE = Sub->getParent()->rend();
4373 for (; InsertI != InsertE; ++InsertI) {
4374 MachineInstr *Instr = &*InsertI;
4375 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4376 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
4377 Sub->getParent()->remove(Movr0Inst);
4378 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
4379 Movr0Inst);
4380 break;
4381 }
4382 }
4383 if (InsertI == InsertE)
4384 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4385 }
4386
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]4387 // Make sure Sub instruction defines EFLAGS and mark the def live.
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]4388 unsigned i = 0, e = Sub->getNumOperands();
4389 for (; i != e; ++i) {
4390 MachineOperand &MO = Sub->getOperand(i);
4391 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
4392 MO.setIsDead(false);
4393 break;
4394 }
4395 }
4396 assert(i != e && "Unable to locate a def EFLAGS operand");
4397
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4398 CmpInstr->eraseFromParent();
4399
4400 // Modify the condition code of instructions in OpsToUpdate.
4401 for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
4402 OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
4403 return true;
4404}
4405
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4406/// optimizeLoadInstr - Try to remove the load by folding it to a register
4407/// operand at the use. We fold the load instructions if load defines a virtual
4408/// register, the virtual register is used once in the same BB, and the
4409/// instructions in-between do not load or store, and have no side effects.
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4410MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI,
4411 const MachineRegisterInfo *MRI,
4412 unsigned &FoldAsLoadDefReg,
4413 MachineInstr *&DefMI) const {
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4414 if (FoldAsLoadDefReg == 0)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4415 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4416 // To be conservative, if there exists another load, clear the load candidate.
4417 if (MI->mayLoad()) {
4418 FoldAsLoadDefReg = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4419 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4420 }
4421
4422 // Check whether we can move DefMI here.
4423 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4424 assert(DefMI);
4425 bool SawStore = false;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4426 if (!DefMI->isSafeToMove(this, nullptr, SawStore))
4427 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4428
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4429 // Collect information about virtual register operands of MI.
4430 unsigned SrcOperandId = 0;
4431 bool FoundSrcOperand = false;
4432 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
4433 MachineOperand &MO = MI->getOperand(i);
4434 if (!MO.isReg())
4435 continue;
4436 unsigned Reg = MO.getReg();
4437 if (Reg != FoldAsLoadDefReg)
4438 continue;
4439 // Do not fold if we have a subreg use or a def or multiple uses.
4440 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4441 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4442
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4443 SrcOperandId = i;
4444 FoundSrcOperand = true;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4445 }
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4446 if (!FoundSrcOperand)
4447 return nullptr;
4448
4449 // Check whether we can fold the def into SrcOperandId.
4450 SmallVector<unsigned, 8> Ops;
4451 Ops.push_back(SrcOperandId);
4452 MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
4453 if (FoldMI) {
4454 FoldAsLoadDefReg = 0;
4455 return FoldMI;
4456 }
4457
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4458 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4459}
4460
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4461/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
4462/// instruction with two undef reads of the register being defined. This is
4463/// used for mapping:
4464/// %xmm4 = V_SET0
4465/// to:
4466/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
4467///
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4468static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4469 const MCInstrDesc &Desc) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4470 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4471 unsigned Reg = MIB->getOperand(0).getReg();
4472 MIB->setDesc(Desc);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4473
4474 // MachineInstr::addOperand() will insert explicit operands before any
4475 // implicit operands.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4476 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4477 // But we don't trust that.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4478 assert(MIB->getOperand(1).getReg() == Reg &&
4479 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4480 return true;
4481}
4482
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]4483// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4484// code sequence is needed for other targets.
4485static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4486 const TargetInstrInfo &TII) {
4487 MachineBasicBlock &MBB = *MIB->getParent();
4488 DebugLoc DL = MIB->getDebugLoc();
4489 unsigned Reg = MIB->getOperand(0).getReg();
4490 const GlobalValue *GV =
4491 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4492 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
4493 MachineMemOperand *MMO = MBB.getParent()->
4494 getMachineMemOperand(MachinePointerInfo::getGOT(), Flag, 8, 8);
Reid Klecknerda00cf52014-10-31 23:19:46 +0000[diff] [blame]4495 MachineBasicBlock::iterator I = MIB.getInstr();
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]4496
4497 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4498 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4499 .addMemOperand(MMO);
4500 MIB->setDebugLoc(DL);
4501 MIB->setDesc(TII.get(X86::MOV64rm));
4502 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4503}
4504
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4505bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4506 bool HasAVX = Subtarget.hasAVX();
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4507 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4508 switch (MI->getOpcode()) {
Craig Topper854f6442013-12-31 03:05:38 +0000[diff] [blame]4509 case X86::MOV32r0:
4510 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]4511 case X86::SETB_C8r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4512 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]4513 case X86::SETB_C16r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4514 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]4515 case X86::SETB_C32r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4516 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]4517 case X86::SETB_C64r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4518 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4519 case X86::V_SET0:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]4520 case X86::FsFLD0SS:
4521 case X86::FsFLD0SD:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4522 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]4523 case X86::AVX_SET0:
4524 assert(HasAVX && "AVX not supported");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4525 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]4526 case X86::AVX512_512_SET0:
4527 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]4528 case X86::V_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4529 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]4530 case X86::AVX2_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4531 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]4532 case X86::TEST8ri_NOREX:
4533 MI->setDesc(get(X86::TEST8ri));
4534 return true;
Michael Liao5bf95782014-12-04 05:20:33 +0000[diff] [blame]4535 case X86::KSET0B:
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]4536 case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
4537 case X86::KSET1B:
4538 case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]4539 case TargetOpcode::LOAD_STACK_GUARD:
4540 expandLoadStackGuard(MIB, *this);
4541 return true;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4542 }
4543 return false;
4544}
4545
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]4546static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]4547 const SmallVectorImpl<MachineOperand> &MOs,
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]4548 MachineInstr *MI,
4549 const TargetInstrInfo &TII) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4550 // Create the base instruction with the memory operand as the first part.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4551 // Omit the implicit operands, something BuildMI can't do.
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]4552 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4553 MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4554 MachineInstrBuilder MIB(MF, NewMI);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4555 unsigned NumAddrOps = MOs.size();
4556 for (unsigned i = 0; i != NumAddrOps; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4557 MIB.addOperand(MOs[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4558 if (NumAddrOps < 4) // FrameIndex only
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]4559 addOffset(MIB, 0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4560
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4561 // Loop over the rest of the ri operands, converting them over.
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]4562 unsigned NumOps = MI->getDesc().getNumOperands()-2;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4563 for (unsigned i = 0; i != NumOps; ++i) {
4564 MachineOperand &MO = MI->getOperand(i+2);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4565 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4566 }
4567 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
4568 MachineOperand &MO = MI->getOperand(i);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4569 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4570 }
4571 return MIB;
4572}
4573
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]4574static MachineInstr *FuseInst(MachineFunction &MF,
4575 unsigned Opcode, unsigned OpNo,
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]4576 const SmallVectorImpl<MachineOperand> &MOs,
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4577 MachineInstr *MI, const TargetInstrInfo &TII) {
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4578 // Omit the implicit operands, something BuildMI can't do.
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]4579 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4580 MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4581 MachineInstrBuilder MIB(MF, NewMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4582
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4583 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4584 MachineOperand &MO = MI->getOperand(i);
4585 if (i == OpNo) {
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]4586 assert(MO.isReg() && "Expected to fold into reg operand!");
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4587 unsigned NumAddrOps = MOs.size();
4588 for (unsigned i = 0; i != NumAddrOps; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4589 MIB.addOperand(MOs[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4590 if (NumAddrOps < 4) // FrameIndex only
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]4591 addOffset(MIB, 0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4592 } else {
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4593 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4594 }
4595 }
4596 return MIB;
4597}
4598
4599static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]4600 const SmallVectorImpl<MachineOperand> &MOs,
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4601 MachineInstr *MI) {
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]4602 MachineFunction &MF = *MI->getParent()->getParent();
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4603 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4604
4605 unsigned NumAddrOps = MOs.size();
4606 for (unsigned i = 0; i != NumAddrOps; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4607 MIB.addOperand(MOs[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4608 if (NumAddrOps < 4) // FrameIndex only
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]4609 addOffset(MIB, 0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4610 return MIB.addImm(0);
4611}
4612
4613MachineInstr*
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]4614X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4615 MachineInstr *MI, unsigned OpNum,
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]4616 const SmallVectorImpl<MachineOperand> &MOs,
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4617 unsigned Size, unsigned Align,
4618 bool AllowCommute) const {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4619 const DenseMap<unsigned,
4620 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4621 bool isCallRegIndirect = Subtarget.callRegIndirect();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4622 bool isTwoAddrFold = false;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]4623
Sanjay Patelfc54c612015-02-09 16:04:52 +0000[diff] [blame]4624 // For CPUs that favor the register form of a call,
4625 // do not fold loads into calls.
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]4626 if (isCallRegIndirect &&
Sanjay Patelfc54c612015-02-09 16:04:52 +0000[diff] [blame]4627 (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4628 return nullptr;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]4629
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]4630 unsigned NumOps = MI->getDesc().getNumOperands();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4631 bool isTwoAddr = NumOps > 1 &&
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4632 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4633
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]4634 // FIXME: AsmPrinter doesn't know how to handle
4635 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4636 if (MI->getOpcode() == X86::ADD32ri &&
4637 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4638 return nullptr;
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]4639
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4640 MachineInstr *NewMI = nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4641 // Folding a memory location into the two-address part of a two-address
4642 // instruction is different than folding it other places. It requires
4643 // replacing the *two* registers with the memory location.
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4644 if (isTwoAddr && NumOps >= 2 && OpNum < 2 &&
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]4645 MI->getOperand(0).isReg() &&
4646 MI->getOperand(1).isReg() &&
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4647 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4648 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4649 isTwoAddrFold = true;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4650 } else if (OpNum == 0) {
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]4651 if (MI->getOpcode() == X86::MOV32r0) {
4652 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
4653 if (NewMI)
4654 return NewMI;
Craig Topperf9115972012-08-23 04:57:36 +0000[diff] [blame]4655 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4656
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4657 OpcodeTablePtr = &RegOp2MemOpTable0;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4658 } else if (OpNum == 1) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4659 OpcodeTablePtr = &RegOp2MemOpTable1;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4660 } else if (OpNum == 2) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4661 OpcodeTablePtr = &RegOp2MemOpTable2;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4662 } else if (OpNum == 3) {
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]4663 OpcodeTablePtr = &RegOp2MemOpTable3;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4664 } else if (OpNum == 4) {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]4665 OpcodeTablePtr = &RegOp2MemOpTable4;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4666 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4667
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4668 // If table selected...
4669 if (OpcodeTablePtr) {
4670 // Find the Opcode to fuse
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]4671 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4672 OpcodeTablePtr->find(MI->getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4673 if (I != OpcodeTablePtr->end()) {
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4674 unsigned Opcode = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]4675 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]4676 if (Align < MinAlign)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4677 return nullptr;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4678 bool NarrowToMOV32rm = false;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4679 if (Size) {
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4680 unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4681 if (Size < RCSize) {
4682 // Check if it's safe to fold the load. If the size of the object is
4683 // narrower than the load width, then it's not.
4684 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4685 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4686 // If this is a 64-bit load, but the spill slot is 32, then we can do
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4687 // a 32-bit load which is implicitly zero-extended. This likely is
4688 // due to live interval analysis remat'ing a load from stack slot.
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4689 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4690 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4691 Opcode = X86::MOV32rm;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4692 NarrowToMOV32rm = true;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4693 }
4694 }
4695
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4696 if (isTwoAddrFold)
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4697 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4698 else
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4699 NewMI = FuseInst(MF, Opcode, OpNum, MOs, MI, *this);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4700
4701 if (NarrowToMOV32rm) {
4702 // If this is the special case where we use a MOV32rm to load a 32-bit
4703 // value and zero-extend the top bits. Change the destination register
4704 // to a 32-bit one.
4705 unsigned DstReg = NewMI->getOperand(0).getReg();
4706 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4707 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4708 else
Jakob Stoklund Olesen9340ea52010-05-24 14:48:17 +0000[diff] [blame]4709 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4710 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4711 return NewMI;
4712 }
4713 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4714
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4715 // If the instruction and target operand are commutable, commute the
4716 // instruction and try again.
4717 if (AllowCommute) {
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4718 unsigned OriginalOpIdx = OpNum, CommuteOpIdx1, CommuteOpIdx2;
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4719 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
4720 bool HasDef = MI->getDesc().getNumDefs();
4721 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
4722 unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg();
4723 unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg();
4724 bool Tied0 =
4725 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
4726 bool Tied1 =
4727 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
4728
4729 // If either of the commutable operands are tied to the destination
4730 // then we can not commute + fold.
4731 if ((HasDef && Reg0 == Reg1 && Tied0) ||
4732 (HasDef && Reg0 == Reg2 && Tied1))
4733 return nullptr;
4734
4735 if ((CommuteOpIdx1 == OriginalOpIdx) ||
4736 (CommuteOpIdx2 == OriginalOpIdx)) {
4737 MachineInstr *CommutedMI = commuteInstruction(MI, false);
4738 if (!CommutedMI) {
4739 // Unable to commute.
4740 return nullptr;
4741 }
4742 if (CommutedMI != MI) {
4743 // New instruction. We can't fold from this.
4744 CommutedMI->eraseFromParent();
4745 return nullptr;
4746 }
4747
4748 // Attempt to fold with the commuted version of the instruction.
4749 unsigned CommuteOp =
4750 (CommuteOpIdx1 == OriginalOpIdx ? CommuteOpIdx2 : CommuteOpIdx1);
4751 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOp, MOs, Size, Align,
4752 /*AllowCommute=*/false);
4753 if (NewMI)
4754 return NewMI;
4755
4756 // Folding failed again - undo the commute before returning.
4757 MachineInstr *UncommutedMI = commuteInstruction(MI, false);
4758 if (!UncommutedMI) {
4759 // Unable to commute.
4760 return nullptr;
4761 }
4762 if (UncommutedMI != MI) {
4763 // New instruction. It doesn't need to be kept.
4764 UncommutedMI->eraseFromParent();
4765 return nullptr;
4766 }
4767
4768 // Return here to prevent duplicate fuse failure report.
4769 return nullptr;
4770 }
4771 }
4772 }
4773
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4774 // No fusion
Jakob Stoklund Olesen51702ec2010-07-09 20:43:09 +0000[diff] [blame]4775 if (PrintFailedFusing && !MI->isCopy())
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4776 dbgs() << "We failed to fuse operand " << OpNum << " in " << *MI;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4777 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4778}
4779
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4780/// hasPartialRegUpdate - Return true for all instructions that only update
4781/// the first 32 or 64-bits of the destination register and leave the rest
4782/// unmodified. This can be used to avoid folding loads if the instructions
4783/// only update part of the destination register, and the non-updated part is
4784/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4785/// instructions breaks the partial register dependency and it can improve
4786/// performance. e.g.:
4787///
4788/// movss (%rdi), %xmm0
4789/// cvtss2sd %xmm0, %xmm0
4790///
4791/// Instead of
4792/// cvtss2sd (%rdi), %xmm0
4793///
Bruno Cardoso Lopes7b435682011-09-15 23:04:24 +0000[diff] [blame]4794/// FIXME: This should be turned into a TSFlags.
4795///
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4796static bool hasPartialRegUpdate(unsigned Opcode) {
4797 switch (Opcode) {
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4798 case X86::CVTSI2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4799 case X86::CVTSI2SSrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4800 case X86::CVTSI2SS64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4801 case X86::CVTSI2SS64rm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4802 case X86::CVTSI2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4803 case X86::CVTSI2SDrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4804 case X86::CVTSI2SD64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4805 case X86::CVTSI2SD64rm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4806 case X86::CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4807 case X86::CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4808 case X86::Int_CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4809 case X86::Int_CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4810 case X86::CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4811 case X86::CVTSS2SDrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4812 case X86::Int_CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4813 case X86::Int_CVTSS2SDrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4814 case X86::RCPSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4815 case X86::RCPSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4816 case X86::RCPSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4817 case X86::RCPSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4818 case X86::ROUNDSDr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4819 case X86::ROUNDSDm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]4820 case X86::ROUNDSDr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4821 case X86::ROUNDSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4822 case X86::ROUNDSSm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]4823 case X86::ROUNDSSr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4824 case X86::RSQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4825 case X86::RSQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4826 case X86::RSQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4827 case X86::RSQRTSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4828 case X86::SQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4829 case X86::SQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4830 case X86::SQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]4831 case X86::SQRTSSm_Int:
4832 case X86::SQRTSDr:
4833 case X86::SQRTSDm:
4834 case X86::SQRTSDr_Int:
4835 case X86::SQRTSDm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4836 return true;
4837 }
4838
4839 return false;
4840}
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4841
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4842/// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
4843/// instructions we would like before a partial register update.
4844unsigned X86InstrInfo::
4845getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
4846 const TargetRegisterInfo *TRI) const {
4847 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
4848 return 0;
4849
4850 // If MI is marked as reading Reg, the partial register update is wanted.
4851 const MachineOperand &MO = MI->getOperand(0);
4852 unsigned Reg = MO.getReg();
4853 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4854 if (MO.readsReg() || MI->readsVirtualRegister(Reg))
4855 return 0;
4856 } else {
4857 if (MI->readsRegister(Reg, TRI))
4858 return 0;
4859 }
4860
4861 // If any of the preceding 16 instructions are reading Reg, insert a
4862 // dependency breaking instruction. The magic number is based on a few
4863 // Nehalem experiments.
4864 return 16;
4865}
4866
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4867// Return true for any instruction the copies the high bits of the first source
4868// operand into the unused high bits of the destination operand.
4869static bool hasUndefRegUpdate(unsigned Opcode) {
4870 switch (Opcode) {
4871 case X86::VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4872 case X86::VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4873 case X86::Int_VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4874 case X86::Int_VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4875 case X86::VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4876 case X86::VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4877 case X86::Int_VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4878 case X86::Int_VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4879 case X86::VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4880 case X86::VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4881 case X86::Int_VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4882 case X86::Int_VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4883 case X86::VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4884 case X86::VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4885 case X86::Int_VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4886 case X86::Int_VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4887 case X86::VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4888 case X86::VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4889 case X86::Int_VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4890 case X86::Int_VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4891 case X86::VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4892 case X86::VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4893 case X86::Int_VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4894 case X86::Int_VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4895 case X86::VRCPSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4896 case X86::VRCPSSm:
4897 case X86::VRCPSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4898 case X86::VROUNDSDr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4899 case X86::VROUNDSDm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4900 case X86::VROUNDSDr_Int:
4901 case X86::VROUNDSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4902 case X86::VROUNDSSm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4903 case X86::VROUNDSSr_Int:
4904 case X86::VRSQRTSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4905 case X86::VRSQRTSSm:
4906 case X86::VRSQRTSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4907 case X86::VSQRTSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4908 case X86::VSQRTSSm:
4909 case X86::VSQRTSSm_Int:
4910 case X86::VSQRTSDr:
4911 case X86::VSQRTSDm:
4912 case X86::VSQRTSDm_Int:
4913 // AVX-512
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4914 case X86::VCVTSD2SSZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4915 case X86::VCVTSD2SSZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4916 case X86::VCVTSS2SDZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]4917 case X86::VCVTSS2SDZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4918 return true;
4919 }
4920
4921 return false;
4922}
4923
4924/// Inform the ExeDepsFix pass how many idle instructions we would like before
4925/// certain undef register reads.
4926///
4927/// This catches the VCVTSI2SD family of instructions:
4928///
4929/// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
4930///
4931/// We should to be careful *not* to catch VXOR idioms which are presumably
4932/// handled specially in the pipeline:
4933///
4934/// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
4935///
4936/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4937/// high bits that are passed-through are not live.
4938unsigned X86InstrInfo::
4939getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
4940 const TargetRegisterInfo *TRI) const {
4941 if (!hasUndefRegUpdate(MI->getOpcode()))
4942 return 0;
4943
4944 // Set the OpNum parameter to the first source operand.
4945 OpNum = 1;
4946
4947 const MachineOperand &MO = MI->getOperand(OpNum);
4948 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
4949 // Use the same magic number as getPartialRegUpdateClearance.
4950 return 16;
4951 }
4952 return 0;
4953}
4954
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4955void X86InstrInfo::
4956breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
4957 const TargetRegisterInfo *TRI) const {
4958 unsigned Reg = MI->getOperand(OpNum).getReg();
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]4959 // If MI kills this register, the false dependence is already broken.
4960 if (MI->killsRegister(Reg, TRI))
4961 return;
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4962 if (X86::VR128RegClass.contains(Reg)) {
4963 // These instructions are all floating point domain, so xorps is the best
4964 // choice.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4965 bool HasAVX = Subtarget.hasAVX();
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]4966 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
4967 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
4968 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4969 } else if (X86::VR256RegClass.contains(Reg)) {
4970 // Use vxorps to clear the full ymm register.
4971 // It wants to read and write the xmm sub-register.
4972 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4973 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
4974 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
4975 .addReg(Reg, RegState::ImplicitDefine);
4976 } else
4977 return;
4978 MI->addRegisterKilled(Reg, TRI, true);
4979}
4980
Andrew Trick153ebe62013-10-31 22:11:56 +0000[diff] [blame]4981MachineInstr*
4982X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
4983 const SmallVectorImpl<unsigned> &Ops,
4984 int FrameIndex) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4985 // Check switch flag
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4986 if (NoFusing) return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4987
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4988 // Unless optimizing for size, don't fold to avoid partial
4989 // register update stalls
Bill Wendling698e84f2012-12-30 10:32:01 +0000[diff] [blame]4990 if (!MF.getFunction()->getAttributes().
4991 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]4992 hasPartialRegUpdate(MI->getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4993 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]4994
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]4995 const MachineFrameInfo *MFI = MF.getFrameInfo();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4996 unsigned Size = MFI->getObjectSize(FrameIndex);
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]4997 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
Benjamin Kramer858a3882013-10-06 13:48:22 +0000[diff] [blame]4998 // If the function stack isn't realigned we don't want to fold instructions
4999 // that need increased alignment.
5000 if (!RI.needsStackRealignment(MF))
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]5001 Alignment =
5002 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5003 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5004 unsigned NewOpc = 0;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5005 unsigned RCSize = 0;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5006 switch (MI->getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5007 default: return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5008 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
Dan Gohman887dd1c2010-05-18 21:42:03 +0000[diff] [blame]5009 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5010 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5011 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5012 }
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5013 // Check if it's safe to fold the load. If the size of the object is
5014 // narrower than the load width, then it's not.
5015 if (Size < RCSize)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5016 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5017 // Change to CMPXXri r, 0 first.
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]5018 MI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5019 MI->getOperand(1).ChangeToImmediate(0);
5020 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5021 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5022
5023 SmallVector<MachineOperand,4> MOs;
5024 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5025 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs,
5026 Size, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5027}
5028
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]5029static bool isPartialRegisterLoad(const MachineInstr &LoadMI,
5030 const MachineFunction &MF) {
5031 unsigned Opc = LoadMI.getOpcode();
5032 unsigned RegSize =
5033 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
5034
5035 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4)
5036 // These instructions only load 32 bits, we can't fold them if the
5037 // destination register is wider than 32 bits (4 bytes).
5038 return true;
5039
5040 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8)
5041 // These instructions only load 64 bits, we can't fold them if the
5042 // destination register is wider than 64 bits (8 bytes).
5043 return true;
5044
5045 return false;
5046}
5047
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]5048MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
5049 MachineInstr *MI,
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]5050 const SmallVectorImpl<unsigned> &Ops,
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]5051 MachineInstr *LoadMI) const {
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]5052 // If loading from a FrameIndex, fold directly from the FrameIndex.
5053 unsigned NumOps = LoadMI->getDesc().getNumOperands();
5054 int FrameIndex;
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]5055 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
5056 if (isPartialRegisterLoad(*LoadMI, MF))
5057 return nullptr;
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]5058 return foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]5059 }
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]5060
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5061 // Check switch flag
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5062 if (NoFusing) return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5063
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5064 // Unless optimizing for size, don't fold to avoid partial
5065 // register update stalls
Bill Wendling698e84f2012-12-30 10:32:01 +0000[diff] [blame]5066 if (!MF.getFunction()->getAttributes().
5067 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5068 hasPartialRegUpdate(MI->getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5069 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]5070
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]5071 // Determine the alignment of the load.
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]5072 unsigned Alignment = 0;
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]5073 if (LoadMI->hasOneMemOperand())
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]5074 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5075 else
5076 switch (LoadMI->getOpcode()) {
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]5077 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]5078 case X86::AVX_SET0:
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]5079 Alignment = 32;
5080 break;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5081 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5082 case X86::V_SETALLONES:
5083 Alignment = 16;
5084 break;
5085 case X86::FsFLD0SD:
5086 Alignment = 8;
5087 break;
5088 case X86::FsFLD0SS:
5089 Alignment = 4;
5090 break;
5091 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5092 return nullptr;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5093 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5094 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5095 unsigned NewOpc = 0;
5096 switch (MI->getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5097 default: return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5098 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5099 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
5100 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
5101 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5102 }
5103 // Change to CMPXXri r, 0 first.
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]5104 MI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5105 MI->getOperand(1).ChangeToImmediate(0);
5106 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5107 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5108
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]5109 // Make sure the subregisters match.
5110 // Otherwise we risk changing the size of the load.
5111 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5112 return nullptr;
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]5113
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]5114 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5115 switch (LoadMI->getOpcode()) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5116 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5117 case X86::V_SETALLONES:
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]5118 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]5119 case X86::AVX_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5120 case X86::FsFLD0SD:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]5121 case X86::FsFLD0SS: {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5122 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5123 // Create a constant-pool entry and operands to load from it.
5124
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]5125 // Medium and large mode can't fold loads this way.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5126 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
5127 MF.getTarget().getCodeModel() != CodeModel::Kernel)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5128 return nullptr;
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]5129
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5130 // x86-32 PIC requires a PIC base register for constant pools.
5131 unsigned PICBase = 0;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5132 if (MF.getTarget().getRelocationModel() == Reloc::PIC_) {
5133 if (Subtarget.is64Bit())
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]5134 PICBase = X86::RIP;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]5135 else
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5136 // FIXME: PICBase = getGlobalBaseReg(&MF);
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]5137 // This doesn't work for several reasons.
5138 // 1. GlobalBaseReg may have been spilled.
5139 // 2. It may not be live at MI.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5140 return nullptr;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]5141 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5142
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5143 // Create a constant-pool entry.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5144 MachineConstantPool &MCP = *MF.getConstantPool();
Chris Lattner229907c2011-07-18 04:54:35 +0000[diff] [blame]5145 Type *Ty;
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]5146 unsigned Opc = LoadMI->getOpcode();
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]5147 if (Opc == X86::FsFLD0SS)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5148 Ty = Type::getFloatTy(MF.getFunction()->getContext());
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]5149 else if (Opc == X86::FsFLD0SD)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5150 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]5151 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
Craig Toppera4c5a472012-01-13 06:12:41 +0000[diff] [blame]5152 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5153 else
5154 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]5155
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]5156 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]5157 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
5158 Constant::getNullValue(Ty);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5159 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5160
5161 // Create operands to load from the constant pool entry.
5162 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
5163 MOs.push_back(MachineOperand::CreateImm(1));
5164 MOs.push_back(MachineOperand::CreateReg(0, false));
5165 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]5166 MOs.push_back(MachineOperand::CreateReg(0, false));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5167 break;
5168 }
5169 default: {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]5170 if (isPartialRegisterLoad(*LoadMI, MF))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5171 return nullptr;
Manman Ren5b462822012-11-27 18:09:26 +0000[diff] [blame]5172
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5173 // Folding a normal load. Just copy the load's address operands.
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]5174 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5175 MOs.push_back(LoadMI->getOperand(i));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5176 break;
5177 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5178 }
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5179 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs,
5180 /*Size=*/0, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5181}
5182
5183
Dan Gohman33332bc2008-10-16 01:49:15 +0000[diff] [blame]5184bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
5185 const SmallVectorImpl<unsigned> &Ops) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5186 // Check switch flag
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5187 if (NoFusing) return 0;
5188
5189 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5190 switch (MI->getOpcode()) {
5191 default: return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5192 case X86::TEST8rr:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5193 case X86::TEST16rr:
5194 case X86::TEST32rr:
5195 case X86::TEST64rr:
5196 return true;
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]5197 case X86::ADD32ri:
5198 // FIXME: AsmPrinter doesn't know how to handle
5199 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5200 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5201 return false;
5202 break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5203 }
5204 }
5205
5206 if (Ops.size() != 1)
5207 return false;
5208
5209 unsigned OpNum = Ops[0];
5210 unsigned Opc = MI->getOpcode();
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]5211 unsigned NumOps = MI->getDesc().getNumOperands();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5212 bool isTwoAddr = NumOps > 1 &&
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5213 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5214
5215 // Folding a memory location into the two-address part of a two-address
5216 // instruction is different than folding it other places. It requires
5217 // replacing the *two* registers with the memory location.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5218 const DenseMap<unsigned,
5219 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5220 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5221 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5222 } else if (OpNum == 0) {
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]5223 if (Opc == X86::MOV32r0)
5224 return true;
5225
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5226 OpcodeTablePtr = &RegOp2MemOpTable0;
5227 } else if (OpNum == 1) {
5228 OpcodeTablePtr = &RegOp2MemOpTable1;
5229 } else if (OpNum == 2) {
5230 OpcodeTablePtr = &RegOp2MemOpTable2;
Craig Topper7573c8f2012-08-31 22:12:16 +0000[diff] [blame]5231 } else if (OpNum == 3) {
5232 OpcodeTablePtr = &RegOp2MemOpTable3;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5233 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5234
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]5235 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
5236 return true;
Jakob Stoklund Olesen9de596e2012-11-28 02:35:17 +0000[diff] [blame]5237 return TargetInstrInfo::canFoldMemoryOperand(MI, Ops);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5238}
5239
5240bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
5241 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]5242 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]5243 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5244 MemOp2RegOpTable.find(MI->getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5245 if (I == MemOp2RegOpTable.end())
5246 return false;
5247 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5248 unsigned Index = I->second.second & TB_INDEX_MASK;
5249 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5250 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5251 if (UnfoldLoad && !FoldedLoad)
5252 return false;
5253 UnfoldLoad &= FoldedLoad;
5254 if (UnfoldStore && !FoldedStore)
5255 return false;
5256 UnfoldStore &= FoldedStore;
5257
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5258 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]5259 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5260 if (!MI->hasOneMemOperand() &&
5261 RC == &X86::VR128RegClass &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5262 !Subtarget.isUnalignedMemAccessFast())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5263 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
5264 // conservatively assume the address is unaligned. That's bad for
5265 // performance.
5266 return false;
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]5267 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5268 SmallVector<MachineOperand,2> BeforeOps;
5269 SmallVector<MachineOperand,2> AfterOps;
5270 SmallVector<MachineOperand,4> ImpOps;
5271 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
5272 MachineOperand &Op = MI->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]5273 if (i >= Index && i < Index + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5274 AddrOps.push_back(Op);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]5275 else if (Op.isReg() && Op.isImplicit())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5276 ImpOps.push_back(Op);
5277 else if (i < Index)
5278 BeforeOps.push_back(Op);
5279 else if (i > Index)
5280 AfterOps.push_back(Op);
5281 }
5282
5283 // Emit the load instruction.
5284 if (UnfoldLoad) {
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5285 std::pair<MachineInstr::mmo_iterator,
5286 MachineInstr::mmo_iterator> MMOs =
5287 MF.extractLoadMemRefs(MI->memoperands_begin(),
5288 MI->memoperands_end());
5289 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5290 if (UnfoldStore) {
5291 // Address operands cannot be marked isKill.
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]5292 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5293 MachineOperand &MO = NewMIs[0]->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]5294 if (MO.isReg())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5295 MO.setIsKill(false);
5296 }
5297 }
5298 }
5299
5300 // Emit the data processing instruction.
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5301 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5302 MachineInstrBuilder MIB(MF, DataMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5303
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5304 if (FoldedStore)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]5305 MIB.addReg(Reg, RegState::Define);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5306 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5307 MIB.addOperand(BeforeOps[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5308 if (FoldedLoad)
5309 MIB.addReg(Reg);
5310 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5311 MIB.addOperand(AfterOps[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5312 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
5313 MachineOperand &MO = ImpOps[i];
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]5314 MIB.addReg(MO.getReg(),
5315 getDefRegState(MO.isDef()) |
5316 RegState::Implicit |
5317 getKillRegState(MO.isKill()) |
Evan Cheng0dc101b2009-06-30 08:49:04 +0000[diff] [blame]5318 getDeadRegState(MO.isDead()) |
5319 getUndefRegState(MO.isUndef()));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5320 }
5321 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5322 switch (DataMI->getOpcode()) {
5323 default: break;
5324 case X86::CMP64ri32:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5325 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5326 case X86::CMP32ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5327 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5328 case X86::CMP16ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5329 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5330 case X86::CMP8ri: {
5331 MachineOperand &MO0 = DataMI->getOperand(0);
5332 MachineOperand &MO1 = DataMI->getOperand(1);
5333 if (MO1.getImm() == 0) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]5334 unsigned NewOpc;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5335 switch (DataMI->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]5336 default: llvm_unreachable("Unreachable!");
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5337 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5338 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5339 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5340 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5341 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5342 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
5343 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
5344 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]5345 DataMI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5346 MO1.ChangeToRegister(MO0.getReg(), false);
5347 }
5348 }
5349 }
5350 NewMIs.push_back(DataMI);
5351
5352 // Emit the store instruction.
5353 if (UnfoldStore) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]5354 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5355 std::pair<MachineInstr::mmo_iterator,
5356 MachineInstr::mmo_iterator> MMOs =
5357 MF.extractStoreMemRefs(MI->memoperands_begin(),
5358 MI->memoperands_end());
5359 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5360 }
5361
5362 return true;
5363}
5364
5365bool
5366X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]5367 SmallVectorImpl<SDNode*> &NewNodes) const {
Dan Gohman17059682008-07-17 19:10:17 +0000[diff] [blame]5368 if (!N->isMachineOpcode())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5369 return false;
5370
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]5371 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5372 MemOp2RegOpTable.find(N->getMachineOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5373 if (I == MemOp2RegOpTable.end())
5374 return false;
5375 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5376 unsigned Index = I->second.second & TB_INDEX_MASK;
5377 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5378 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5379 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]5380 MachineFunction &MF = DAG.getMachineFunction();
5381 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5382 unsigned NumDefs = MCID.NumDefs;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]5383 std::vector<SDValue> AddrOps;
5384 std::vector<SDValue> BeforeOps;
5385 std::vector<SDValue> AfterOps;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]5386 SDLoc dl(N);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5387 unsigned NumOps = N->getNumOperands();
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]5388 for (unsigned i = 0; i != NumOps-1; ++i) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]5389 SDValue Op = N->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]5390 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5391 AddrOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]5392 else if (i < Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5393 BeforeOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]5394 else if (i > Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5395 AfterOps.push_back(Op);
5396 }
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]5397 SDValue Chain = N->getOperand(NumOps-1);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5398 AddrOps.push_back(Chain);
5399
5400 // Emit the load instruction.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5401 SDNode *Load = nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5402 if (FoldedLoad) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]5403 EVT VT = *RC->vt_begin();
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]5404 std::pair<MachineInstr::mmo_iterator,
5405 MachineInstr::mmo_iterator> MMOs =
5406 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
5407 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5408 if (!(*MMOs.first) &&
5409 RC == &X86::VR128RegClass &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5410 !Subtarget.isUnalignedMemAccessFast())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5411 // Do not introduce a slow unaligned load.
5412 return false;
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]5413 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
5414 bool isAligned = (*MMOs.first) &&
5415 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5416 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]5417 VT, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5418 NewNodes.push_back(Load);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5419
5420 // Preserve memory reference information.
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5421 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5422 }
5423
5424 // Emit the data processing instruction.
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]5425 std::vector<EVT> VTs;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5426 const TargetRegisterClass *DstRC = nullptr;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5427 if (MCID.getNumDefs() > 0) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]5428 DstRC = getRegClass(MCID, 0, &RI, MF);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5429 VTs.push_back(*DstRC->vt_begin());
5430 }
5431 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]5432 EVT VT = N->getValueType(i);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5433 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5434 VTs.push_back(VT);
5435 }
5436 if (Load)
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]5437 BeforeOps.push_back(SDValue(Load, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5438 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]5439 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5440 NewNodes.push_back(NewNode);
5441
5442 // Emit the store instruction.
5443 if (FoldedStore) {
5444 AddrOps.pop_back();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]5445 AddrOps.push_back(SDValue(NewNode, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5446 AddrOps.push_back(Chain);
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]5447 std::pair<MachineInstr::mmo_iterator,
5448 MachineInstr::mmo_iterator> MMOs =
5449 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
5450 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5451 if (!(*MMOs.first) &&
5452 RC == &X86::VR128RegClass &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5453 !Subtarget.isUnalignedMemAccessFast())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5454 // Do not introduce a slow unaligned store.
5455 return false;
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]5456 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
5457 bool isAligned = (*MMOs.first) &&
5458 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5459 SDNode *Store =
5460 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
5461 dl, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5462 NewNodes.push_back(Store);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5463
5464 // Preserve memory reference information.
Craig Topper9e71b822015-02-10 06:29:28 +0000[diff] [blame]5465 cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5466 }
5467
5468 return true;
5469}
5470
5471unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]5472 bool UnfoldLoad, bool UnfoldStore,
5473 unsigned *LoadRegIndex) const {
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]5474 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5475 MemOp2RegOpTable.find(Opc);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5476 if (I == MemOp2RegOpTable.end())
5477 return 0;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5478 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5479 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5480 if (UnfoldLoad && !FoldedLoad)
5481 return 0;
5482 if (UnfoldStore && !FoldedStore)
5483 return 0;
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]5484 if (LoadRegIndex)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5485 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5486 return I->second.first;
5487}
5488
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5489bool
5490X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
5491 int64_t &Offset1, int64_t &Offset2) const {
5492 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
5493 return false;
5494 unsigned Opc1 = Load1->getMachineOpcode();
5495 unsigned Opc2 = Load2->getMachineOpcode();
5496 switch (Opc1) {
5497 default: return false;
5498 case X86::MOV8rm:
5499 case X86::MOV16rm:
5500 case X86::MOV32rm:
5501 case X86::MOV64rm:
5502 case X86::LD_Fp32m:
5503 case X86::LD_Fp64m:
5504 case X86::LD_Fp80m:
5505 case X86::MOVSSrm:
5506 case X86::MOVSDrm:
5507 case X86::MMX_MOVD64rm:
5508 case X86::MMX_MOVQ64rm:
5509 case X86::FsMOVAPSrm:
5510 case X86::FsMOVAPDrm:
5511 case X86::MOVAPSrm:
5512 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5513 case X86::MOVAPDrm:
5514 case X86::MOVDQArm:
5515 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5516 // AVX load instructions
5517 case X86::VMOVSSrm:
5518 case X86::VMOVSDrm:
5519 case X86::FsVMOVAPSrm:
5520 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]5521 case X86::VMOVAPSrm:
5522 case X86::VMOVUPSrm:
5523 case X86::VMOVAPDrm:
5524 case X86::VMOVDQArm:
5525 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]5526 case X86::VMOVAPSYrm:
5527 case X86::VMOVUPSYrm:
5528 case X86::VMOVAPDYrm:
5529 case X86::VMOVDQAYrm:
5530 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5531 break;
5532 }
5533 switch (Opc2) {
5534 default: return false;
5535 case X86::MOV8rm:
5536 case X86::MOV16rm:
5537 case X86::MOV32rm:
5538 case X86::MOV64rm:
5539 case X86::LD_Fp32m:
5540 case X86::LD_Fp64m:
5541 case X86::LD_Fp80m:
5542 case X86::MOVSSrm:
5543 case X86::MOVSDrm:
5544 case X86::MMX_MOVD64rm:
5545 case X86::MMX_MOVQ64rm:
5546 case X86::FsMOVAPSrm:
5547 case X86::FsMOVAPDrm:
5548 case X86::MOVAPSrm:
5549 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5550 case X86::MOVAPDrm:
5551 case X86::MOVDQArm:
5552 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5553 // AVX load instructions
5554 case X86::VMOVSSrm:
5555 case X86::VMOVSDrm:
5556 case X86::FsVMOVAPSrm:
5557 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]5558 case X86::VMOVAPSrm:
5559 case X86::VMOVUPSrm:
5560 case X86::VMOVAPDrm:
5561 case X86::VMOVDQArm:
5562 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]5563 case X86::VMOVAPSYrm:
5564 case X86::VMOVUPSYrm:
5565 case X86::VMOVAPDYrm:
5566 case X86::VMOVDQAYrm:
5567 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5568 break;
5569 }
5570
5571 // Check if chain operands and base addresses match.
5572 if (Load1->getOperand(0) != Load2->getOperand(0) ||
5573 Load1->getOperand(5) != Load2->getOperand(5))
5574 return false;
5575 // Segment operands should match as well.
5576 if (Load1->getOperand(4) != Load2->getOperand(4))
5577 return false;
5578 // Scale should be 1, Index should be Reg0.
5579 if (Load1->getOperand(1) == Load2->getOperand(1) &&
5580 Load1->getOperand(2) == Load2->getOperand(2)) {
5581 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
5582 return false;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5583
5584 // Now let's examine the displacements.
5585 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
5586 isa<ConstantSDNode>(Load2->getOperand(3))) {
5587 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
5588 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
5589 return true;
5590 }
5591 }
5592 return false;
5593}
5594
5595bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
5596 int64_t Offset1, int64_t Offset2,
5597 unsigned NumLoads) const {
5598 assert(Offset2 > Offset1);
5599 if ((Offset2 - Offset1) / 8 > 64)
5600 return false;
5601
5602 unsigned Opc1 = Load1->getMachineOpcode();
5603 unsigned Opc2 = Load2->getMachineOpcode();
5604 if (Opc1 != Opc2)
5605 return false; // FIXME: overly conservative?
5606
5607 switch (Opc1) {
5608 default: break;
5609 case X86::LD_Fp32m:
5610 case X86::LD_Fp64m:
5611 case X86::LD_Fp80m:
5612 case X86::MMX_MOVD64rm:
5613 case X86::MMX_MOVQ64rm:
5614 return false;
5615 }
5616
5617 EVT VT = Load1->getValueType(0);
5618 switch (VT.getSimpleVT().SimpleTy) {
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]5619 default:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5620 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
5621 // have 16 of them to play with.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5622 if (Subtarget.is64Bit()) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5623 if (NumLoads >= 3)
5624 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]5625 } else if (NumLoads) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5626 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]5627 }
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5628 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5629 case MVT::i8:
5630 case MVT::i16:
5631 case MVT::i32:
5632 case MVT::i64:
Evan Cheng16cf9342010-01-22 23:49:11 +0000[diff] [blame]5633 case MVT::f32:
5634 case MVT::f64:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5635 if (NumLoads)
5636 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]5637 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5638 }
5639
5640 return true;
5641}
5642
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5643bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
5644 MachineInstr *Second) const {
5645 // Check if this processor supports macro-fusion. Since this is a minor
5646 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
5647 // proxy for SandyBridge+.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5648 if (!Subtarget.hasAVX())
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5649 return false;
5650
5651 enum {
5652 FuseTest,
5653 FuseCmp,
5654 FuseInc
5655 } FuseKind;
5656
5657 switch(Second->getOpcode()) {
5658 default:
5659 return false;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]5660 case X86::JE_1:
5661 case X86::JNE_1:
5662 case X86::JL_1:
5663 case X86::JLE_1:
5664 case X86::JG_1:
5665 case X86::JGE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5666 FuseKind = FuseInc;
5667 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]5668 case X86::JB_1:
5669 case X86::JBE_1:
5670 case X86::JA_1:
5671 case X86::JAE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5672 FuseKind = FuseCmp;
5673 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]5674 case X86::JS_1:
5675 case X86::JNS_1:
5676 case X86::JP_1:
5677 case X86::JNP_1:
5678 case X86::JO_1:
5679 case X86::JNO_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5680 FuseKind = FuseTest;
5681 break;
5682 }
5683 switch (First->getOpcode()) {
5684 default:
5685 return false;
5686 case X86::TEST8rr:
5687 case X86::TEST16rr:
5688 case X86::TEST32rr:
5689 case X86::TEST64rr:
5690 case X86::TEST8ri:
5691 case X86::TEST16ri:
5692 case X86::TEST32ri:
5693 case X86::TEST32i32:
5694 case X86::TEST64i32:
5695 case X86::TEST64ri32:
5696 case X86::TEST8rm:
5697 case X86::TEST16rm:
5698 case X86::TEST32rm:
5699 case X86::TEST64rm:
Akira Hatanaka7cc27642014-07-10 18:00:53 +0000[diff] [blame]5700 case X86::TEST8ri_NOREX:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5701 case X86::AND16i16:
5702 case X86::AND16ri:
5703 case X86::AND16ri8:
5704 case X86::AND16rm:
5705 case X86::AND16rr:
5706 case X86::AND32i32:
5707 case X86::AND32ri:
5708 case X86::AND32ri8:
5709 case X86::AND32rm:
5710 case X86::AND32rr:
5711 case X86::AND64i32:
5712 case X86::AND64ri32:
5713 case X86::AND64ri8:
5714 case X86::AND64rm:
5715 case X86::AND64rr:
5716 case X86::AND8i8:
5717 case X86::AND8ri:
5718 case X86::AND8rm:
5719 case X86::AND8rr:
5720 return true;
5721 case X86::CMP16i16:
5722 case X86::CMP16ri:
5723 case X86::CMP16ri8:
5724 case X86::CMP16rm:
5725 case X86::CMP16rr:
5726 case X86::CMP32i32:
5727 case X86::CMP32ri:
5728 case X86::CMP32ri8:
5729 case X86::CMP32rm:
5730 case X86::CMP32rr:
5731 case X86::CMP64i32:
5732 case X86::CMP64ri32:
5733 case X86::CMP64ri8:
5734 case X86::CMP64rm:
5735 case X86::CMP64rr:
5736 case X86::CMP8i8:
5737 case X86::CMP8ri:
5738 case X86::CMP8rm:
5739 case X86::CMP8rr:
5740 case X86::ADD16i16:
5741 case X86::ADD16ri:
5742 case X86::ADD16ri8:
5743 case X86::ADD16ri8_DB:
5744 case X86::ADD16ri_DB:
5745 case X86::ADD16rm:
5746 case X86::ADD16rr:
5747 case X86::ADD16rr_DB:
5748 case X86::ADD32i32:
5749 case X86::ADD32ri:
5750 case X86::ADD32ri8:
5751 case X86::ADD32ri8_DB:
5752 case X86::ADD32ri_DB:
5753 case X86::ADD32rm:
5754 case X86::ADD32rr:
5755 case X86::ADD32rr_DB:
5756 case X86::ADD64i32:
5757 case X86::ADD64ri32:
5758 case X86::ADD64ri32_DB:
5759 case X86::ADD64ri8:
5760 case X86::ADD64ri8_DB:
5761 case X86::ADD64rm:
5762 case X86::ADD64rr:
5763 case X86::ADD64rr_DB:
5764 case X86::ADD8i8:
5765 case X86::ADD8mi:
5766 case X86::ADD8mr:
5767 case X86::ADD8ri:
5768 case X86::ADD8rm:
5769 case X86::ADD8rr:
5770 case X86::SUB16i16:
5771 case X86::SUB16ri:
5772 case X86::SUB16ri8:
5773 case X86::SUB16rm:
5774 case X86::SUB16rr:
5775 case X86::SUB32i32:
5776 case X86::SUB32ri:
5777 case X86::SUB32ri8:
5778 case X86::SUB32rm:
5779 case X86::SUB32rr:
5780 case X86::SUB64i32:
5781 case X86::SUB64ri32:
5782 case X86::SUB64ri8:
5783 case X86::SUB64rm:
5784 case X86::SUB64rr:
5785 case X86::SUB8i8:
5786 case X86::SUB8ri:
5787 case X86::SUB8rm:
5788 case X86::SUB8rr:
5789 return FuseKind == FuseCmp || FuseKind == FuseInc;
5790 case X86::INC16r:
5791 case X86::INC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5792 case X86::INC64r:
5793 case X86::INC8r:
5794 case X86::DEC16r:
5795 case X86::DEC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5796 case X86::DEC64r:
5797 case X86::DEC8r:
5798 return FuseKind == FuseInc;
5799 }
5800}
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5801
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]5802bool X86InstrInfo::
Owen Anderson4f6bf042008-08-14 22:49:33 +0000[diff] [blame]5803ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]5804 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]5805 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]5806 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
5807 return true;
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]5808 Cond[0].setImm(GetOppositeBranchCondition(CC));
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]5809 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]5810}
5811
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]5812bool X86InstrInfo::
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]5813isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5814 // FIXME: Return false for x87 stack register classes for now. We can't
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]5815 // allow any loads of these registers before FpGet_ST0_80.
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]5816 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
5817 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]5818}
5819
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]5820/// getGlobalBaseReg - Return a virtual register initialized with the
5821/// the global base register value. Output instructions required to
5822/// initialize the register in the function entry block, if necessary.
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]5823///
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5824/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
5825///
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]5826unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5827 assert(!Subtarget.is64Bit() &&
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]5828 "X86-64 PIC uses RIP relative addressing");
5829
5830 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5831 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5832 if (GlobalBaseReg != 0)
5833 return GlobalBaseReg;
5834
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5835 // Create the register. The code to initialize it is inserted
5836 // later, by the CGBR pass (below).
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]5837 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Jakob Stoklund Olesen38dcd592012-05-20 18:43:00 +0000[diff] [blame]5838 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]5839 X86FI->setGlobalBaseReg(GlobalBaseReg);
5840 return GlobalBaseReg;
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]5841}
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5842
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5843// These are the replaceable SSE instructions. Some of these have Int variants
5844// that we don't include here. We don't want to replace instructions selected
5845// by intrinsics.
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5846static const uint16_t ReplaceableInstrs[][3] = {
Bruno Cardoso Lopes1401e042010-08-12 02:08:52 +0000[diff] [blame]5847 //PackedSingle PackedDouble PackedInt
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]5848 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
5849 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
5850 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
5851 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
5852 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
5853 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
5854 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
5855 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
5856 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
5857 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
5858 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
5859 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
5860 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
5861 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]5862 // AVX 128-bit support
5863 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
5864 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
5865 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
5866 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
5867 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
5868 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5869 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
5870 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
5871 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
5872 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
5873 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
5874 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]5875 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
5876 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]5877 // AVX 256-bit support
5878 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
5879 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
5880 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
5881 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
5882 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]5883 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
5884};
5885
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5886static const uint16_t ReplaceableInstrsAVX2[][3] = {
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]5887 //PackedSingle PackedDouble PackedInt
Craig Topperf87a2be2011-11-09 09:37:21 +0000[diff] [blame]5888 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
5889 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
5890 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
5891 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
5892 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
5893 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
5894 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
Craig Topper12b72de2011-11-29 05:37:58 +0000[diff] [blame]5895 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
5896 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
5897 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
5898 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
5899 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
5900 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
Quentin Colombet6f12ae02014-03-26 00:10:22 +0000[diff] [blame]5901 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
5902 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
5903 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
5904 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
5905 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
5906 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
5907 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5908};
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5909
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5910// FIXME: Some shuffle and unpack instructions have equivalents in different
5911// domains, but they require a bit more work than just switching opcodes.
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5912
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5913static const uint16_t *lookup(unsigned opcode, unsigned domain) {
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5914 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5915 if (ReplaceableInstrs[i][domain-1] == opcode)
5916 return ReplaceableInstrs[i];
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5917 return nullptr;
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]5918}
5919
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5920static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]5921 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
5922 if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
5923 return ReplaceableInstrsAVX2[i];
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5924 return nullptr;
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5925}
5926
5927std::pair<uint16_t, uint16_t>
Jakob Stoklund Olesenb48c9942011-09-27 22:57:18 +0000[diff] [blame]5928X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5929 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5930 bool hasAVX2 = Subtarget.hasAVX2();
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]5931 uint16_t validDomains = 0;
5932 if (domain && lookup(MI->getOpcode(), domain))
5933 validDomains = 0xe;
5934 else if (domain && lookupAVX2(MI->getOpcode(), domain))
5935 validDomains = hasAVX2 ? 0xe : 0x6;
5936 return std::make_pair(domain, validDomains);
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5937}
5938
Jakob Stoklund Olesenb48c9942011-09-27 22:57:18 +0000[diff] [blame]5939void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5940 assert(Domain>0 && Domain<4 && "Invalid execution domain");
5941 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5942 assert(dom && "Not an SSE instruction");
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]5943 const uint16_t *table = lookup(MI->getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]5944 if (!table) { // try the other table
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5945 assert((Subtarget.hasAVX2() || Domain < 3) &&
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]5946 "256-bit vector operations only available in AVX2");
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]5947 table = lookupAVX2(MI->getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]5948 }
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]5949 assert(table && "Cannot change domain");
5950 MI->setDesc(get(table[Domain-1]));
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]5951}
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]5952
5953/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
5954void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
5955 NopInst.setOpcode(X86::NOOP);
5956}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5957
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]5958// This code must remain in sync with getJumpInstrTableEntryBound in this class!
5959// In particular, getJumpInstrTableEntryBound must always return an upper bound
5960// on the encoding lengths of the instructions generated by
5961// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]5962void X86InstrInfo::getUnconditionalBranch(
5963 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]5964 Branch.setOpcode(X86::JMP_1);
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]5965 Branch.addOperand(MCOperand::CreateExpr(BranchTarget));
5966}
5967
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]5968// This code must remain in sync with getJumpInstrTableEntryBound in this class!
5969// In particular, getJumpInstrTableEntryBound must always return an upper bound
5970// on the encoding lengths of the instructions generated by
5971// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]5972void X86InstrInfo::getTrap(MCInst &MI) const {
5973 MI.setOpcode(X86::TRAP);
5974}
5975
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]5976// See getTrap and getUnconditionalBranch for conditions on the value returned
5977// by this function.
5978unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
5979 // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
5980 // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
5981 return 5;
5982}
5983
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]5984bool X86InstrInfo::isHighLatencyDef(int opc) const {
5985 switch (opc) {
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5986 default: return false;
5987 case X86::DIVSDrm:
5988 case X86::DIVSDrm_Int:
5989 case X86::DIVSDrr:
5990 case X86::DIVSDrr_Int:
5991 case X86::DIVSSrm:
5992 case X86::DIVSSrm_Int:
5993 case X86::DIVSSrr:
5994 case X86::DIVSSrr_Int:
5995 case X86::SQRTPDm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5996 case X86::SQRTPDr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5997 case X86::SQRTPSm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5998 case X86::SQRTPSr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]5999 case X86::SQRTSDm:
6000 case X86::SQRTSDm_Int:
6001 case X86::SQRTSDr:
6002 case X86::SQRTSDr_Int:
6003 case X86::SQRTSSm:
6004 case X86::SQRTSSm_Int:
6005 case X86::SQRTSSr:
6006 case X86::SQRTSSr_Int:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6007 // AVX instructions with high latency
6008 case X86::VDIVSDrm:
6009 case X86::VDIVSDrm_Int:
6010 case X86::VDIVSDrr:
6011 case X86::VDIVSDrr_Int:
6012 case X86::VDIVSSrm:
6013 case X86::VDIVSSrm_Int:
6014 case X86::VDIVSSrr:
6015 case X86::VDIVSSrr_Int:
6016 case X86::VSQRTPDm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6017 case X86::VSQRTPDr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6018 case X86::VSQRTPSm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6019 case X86::VSQRTPSr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6020 case X86::VSQRTSDm:
6021 case X86::VSQRTSDm_Int:
6022 case X86::VSQRTSDr:
6023 case X86::VSQRTSSm:
6024 case X86::VSQRTSSm_Int:
6025 case X86::VSQRTSSr:
Robert Khasanov1cf354c2014-10-28 18:22:41 +0000[diff] [blame]6026 case X86::VSQRTPDZm:
6027 case X86::VSQRTPDZr:
6028 case X86::VSQRTPSZm:
6029 case X86::VSQRTPSZr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]6030 case X86::VSQRTSDZm:
6031 case X86::VSQRTSDZm_Int:
6032 case X86::VSQRTSDZr:
6033 case X86::VSQRTSSZm_Int:
6034 case X86::VSQRTSSZr:
6035 case X86::VSQRTSSZm:
6036 case X86::VDIVSDZrm:
6037 case X86::VDIVSDZrr:
6038 case X86::VDIVSSZrm:
6039 case X86::VDIVSSZrr:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]6040
6041 case X86::VGATHERQPSZrm:
6042 case X86::VGATHERQPDZrm:
6043 case X86::VGATHERDPDZrm:
6044 case X86::VGATHERDPSZrm:
6045 case X86::VPGATHERQDZrm:
6046 case X86::VPGATHERQQZrm:
6047 case X86::VPGATHERDDZrm:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]6048 case X86::VPGATHERDQZrm:
6049 case X86::VSCATTERQPDZmr:
6050 case X86::VSCATTERQPSZmr:
6051 case X86::VSCATTERDPDZmr:
6052 case X86::VSCATTERDPSZmr:
6053 case X86::VPSCATTERQDZmr:
6054 case X86::VPSCATTERQQZmr:
6055 case X86::VPSCATTERDDZmr:
6056 case X86::VPSCATTERDQZmr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]6057 return true;
6058 }
6059}
6060
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]6061bool X86InstrInfo::
6062hasHighOperandLatency(const InstrItineraryData *ItinData,
6063 const MachineRegisterInfo *MRI,
6064 const MachineInstr *DefMI, unsigned DefIdx,
6065 const MachineInstr *UseMI, unsigned UseIdx) const {
6066 return isHighLatencyDef(DefMI->getOpcode());
6067}
6068
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6069namespace {
6070 /// CGBR - Create Global Base Reg pass. This initializes the PIC
6071 /// global base register for x86-32.
6072 struct CGBR : public MachineFunctionPass {
6073 static char ID;
Owen Andersona7aed182010-08-06 18:33:48 +0000[diff] [blame]6074 CGBR() : MachineFunctionPass(ID) {}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6075
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]6076 bool runOnMachineFunction(MachineFunction &MF) override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6077 const X86TargetMachine *TM =
6078 static_cast<const X86TargetMachine *>(&MF.getTarget());
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6079 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6080
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]6081 // Don't do anything if this is 64-bit as 64-bit PIC
6082 // uses RIP relative addressing.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6083 if (STI.is64Bit())
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]6084 return false;
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6085
6086 // Only emit a global base reg in PIC mode.
6087 if (TM->getRelocationModel() != Reloc::PIC_)
6088 return false;
6089
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]6090 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
6091 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6092
6093 // If we didn't need a GlobalBaseReg, don't insert code.
6094 if (GlobalBaseReg == 0)
6095 return false;
6096
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6097 // Insert the set of GlobalBaseReg into the first MBB of the function
6098 MachineBasicBlock &FirstMBB = MF.front();
6099 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
6100 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
6101 MachineRegisterInfo &RegInfo = MF.getRegInfo();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6102 const X86InstrInfo *TII = STI.getInstrInfo();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6103
6104 unsigned PC;
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6105 if (STI.isPICStyleGOT())
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]6106 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6107 else
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]6108 PC = GlobalBaseReg;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6109
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6110 // Operand of MovePCtoStack is completely ignored by asm printer. It's
6111 // only used in JIT code emission as displacement to pc.
6112 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6113
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6114 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
6115 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6116 if (STI.isPICStyleGOT()) {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6117 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
6118 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
6119 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
6120 X86II::MO_GOT_ABSOLUTE_ADDRESS);
6121 }
6122
6123 return true;
6124 }
6125
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]6126 const char *getPassName() const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6127 return "X86 PIC Global Base Reg Initialization";
6128 }
6129
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]6130 void getAnalysisUsage(AnalysisUsage &AU) const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6131 AU.setPreservesCFG();
6132 MachineFunctionPass::getAnalysisUsage(AU);
6133 }
6134 };
6135}
6136
6137char CGBR::ID = 0;
6138FunctionPass*
Eric Christopher463b84b2014-05-22 01:45:57 +0000[diff] [blame]6139llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]6140
6141namespace {
6142 struct LDTLSCleanup : public MachineFunctionPass {
6143 static char ID;
6144 LDTLSCleanup() : MachineFunctionPass(ID) {}
6145
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]6146 bool runOnMachineFunction(MachineFunction &MF) override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]6147 X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
6148 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
6149 // No point folding accesses if there isn't at least two.
6150 return false;
6151 }
6152
6153 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
6154 return VisitNode(DT->getRootNode(), 0);
6155 }
6156
6157 // Visit the dominator subtree rooted at Node in pre-order.
6158 // If TLSBaseAddrReg is non-null, then use that to replace any
6159 // TLS_base_addr instructions. Otherwise, create the register
6160 // when the first such instruction is seen, and then use it
6161 // as we encounter more instructions.
6162 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
6163 MachineBasicBlock *BB = Node->getBlock();
6164 bool Changed = false;
6165
6166 // Traverse the current block.
6167 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
6168 ++I) {
6169 switch (I->getOpcode()) {
6170 case X86::TLS_base_addr32:
6171 case X86::TLS_base_addr64:
6172 if (TLSBaseAddrReg)
6173 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
6174 else
6175 I = SetRegister(I, &TLSBaseAddrReg);
6176 Changed = true;
6177 break;
6178 default:
6179 break;
6180 }
6181 }
6182
6183 // Visit the children of this block in the dominator tree.
6184 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
6185 I != E; ++I) {
6186 Changed |= VisitNode(*I, TLSBaseAddrReg);
6187 }
6188
6189 return Changed;
6190 }
6191
6192 // Replace the TLS_base_addr instruction I with a copy from
6193 // TLSBaseAddrReg, returning the new instruction.
6194 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
6195 unsigned TLSBaseAddrReg) {
6196 MachineFunction *MF = I->getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6197 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
6198 const bool is64Bit = STI.is64Bit();
6199 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]6200
6201 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
6202 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
6203 TII->get(TargetOpcode::COPY),
6204 is64Bit ? X86::RAX : X86::EAX)
6205 .addReg(TLSBaseAddrReg);
6206
6207 // Erase the TLS_base_addr instruction.
6208 I->eraseFromParent();
6209
6210 return Copy;
6211 }
6212
6213 // Create a virtal register in *TLSBaseAddrReg, and populate it by
6214 // inserting a copy instruction after I. Returns the new instruction.
6215 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
6216 MachineFunction *MF = I->getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6217 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
6218 const bool is64Bit = STI.is64Bit();
6219 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]6220
6221 // Create a virtual register for the TLS base address.
6222 MachineRegisterInfo &RegInfo = MF->getRegInfo();
6223 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
6224 ? &X86::GR64RegClass
6225 : &X86::GR32RegClass);
6226
6227 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
6228 MachineInstr *Next = I->getNextNode();
6229 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
6230 TII->get(TargetOpcode::COPY),
6231 *TLSBaseAddrReg)
6232 .addReg(is64Bit ? X86::RAX : X86::EAX);
6233
6234 return Copy;
6235 }
6236
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]6237 const char *getPassName() const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]6238 return "Local Dynamic TLS Access Clean-up";
6239 }
6240
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]6241 void getAnalysisUsage(AnalysisUsage &AU) const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]6242 AU.setPreservesCFG();
6243 AU.addRequired<MachineDominatorTree>();
6244 MachineFunctionPass::getAnalysisUsage(AU);
6245 }
6246 };
6247}
6248
6249char LDTLSCleanup::ID = 0;
6250FunctionPass*
6251llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }