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gerrit-public.fairphone.software / toolchain / llvm-project / f171cf23b8dee56cb8ac66c78d2f0e44d23442ce / . / llvm / lib / Target / R600 / AMDGPU.td
blob: 6a23d361eb85edd083cf98818959205e43121cea [file] [log] [blame]
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]1//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//==-----------------------------------------------------------------------===//
9
Tom Stellardbc5b5372014-06-13 16:38:59 +0000[diff] [blame]10include "llvm/Target/Target.td"
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]11
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]12//===----------------------------------------------------------------------===//
13// Subtarget Features
14//===----------------------------------------------------------------------===//
15
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]16// Debugging Features
17
18def FeatureDumpCode : SubtargetFeature <"DumpCode",
19 "DumpCode",
20 "true",
21 "Dump MachineInstrs in the CodeEmitter">;
22
Tom Stellard66df8a22013-11-18 19:43:44 +0000[diff] [blame]23def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
Tom Stellarded0ceec2013-10-10 17:11:12 +0000[diff] [blame]24 "EnableIRStructurizer",
Tom Stellard66df8a22013-11-18 19:43:44 +0000[diff] [blame]25 "false",
26 "Disable IR Structurizer">;
Tom Stellarded0ceec2013-10-10 17:11:12 +0000[diff] [blame]27
Matt Arsenaultd9a23ab2014-07-13 02:08:26 +0000[diff] [blame]28def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
29 "EnablePromoteAlloca",
30 "true",
31 "Enable promote alloca pass">;
32
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]33// Target features
34
Tom Stellard783893a2013-11-18 19:43:33 +0000[diff] [blame]35def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
36 "EnableIfCvt",
37 "false",
38 "Disable the if conversion pass">;
39
Matt Arsenaultf5e29972014-06-20 06:50:05 +0000[diff] [blame]40def FeatureFP64 : SubtargetFeature<"fp64",
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]41 "FP64",
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]42 "true",
Matt Arsenaultf5e29972014-06-20 06:50:05 +0000[diff] [blame]43 "Enable double precision operations">;
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]44
Matt Arsenaultf171cf22014-07-14 23:40:49 +0000[diff] [blame^]45def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
46 "FP64Denormals",
47 "true",
48 "Enable double precision denormal handling",
49 [FeatureFP64]>;
50
51// Some instructions do not support denormals despite this flag. Using
52// fp32 denormals also causes instructions to run at the double
53// precision rate for the device.
54def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
55 "FP32Denormals",
56 "true",
57 "Enable single precision denormal handling">;
58
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]59def Feature64BitPtr : SubtargetFeature<"64BitPtr",
60 "Is64bit",
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]61 "true",
Matt Arsenaultf5e29972014-06-20 06:50:05 +0000[diff] [blame]62 "Specify if 64-bit addressing should be used">;
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]63
64def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
65 "R600ALUInst",
66 "false",
Matt Arsenaultf5e29972014-06-20 06:50:05 +0000[diff] [blame]67 "Older version of ALU instructions encoding">;
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]68
69def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
70 "HasVertexCache",
71 "true",
Matt Arsenaultf5e29972014-06-20 06:50:05 +0000[diff] [blame]72 "Specify use of dedicated vertex cache">;
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]73
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]74def FeatureCaymanISA : SubtargetFeature<"caymanISA",
75 "CaymanISA",
76 "true",
77 "Use Cayman ISA">;
78
Tom Stellard348273d2014-01-23 16:18:02 +0000[diff] [blame]79def FeatureCFALUBug : SubtargetFeature<"cfalubug",
80 "CFALUBug",
81 "true",
82 "GPU has CF_ALU bug">;
83
Tom Stellard3498e4f2013-06-07 20:28:55 +0000[diff] [blame]84class SubtargetFeatureFetchLimit <string Value> :
85 SubtargetFeature <"fetch"#Value,
86 "TexVTXClauseSize",
87 Value,
88 "Limit the maximum number of fetches in a clause to "#Value>;
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]89
Tom Stellard3498e4f2013-06-07 20:28:55 +0000[diff] [blame]90def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
91def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
92
Tom Stellard8c347b02014-01-22 21:55:40 +0000[diff] [blame]93class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
94 "wavefrontsize"#Value,
95 "WavefrontSize",
96 !cast<string>(Value),
97 "The number of threads per wavefront">;
98
99def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
100def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
101def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
102
Tom Stellard880a80a2014-06-17 16:53:14 +0000[diff] [blame]103class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
104 "localmemorysize"#Value,
105 "LocalMemorySize",
106 !cast<string>(Value),
107 "The size of local memory in bytes">;
108
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]109class SubtargetFeatureGeneration <string Value,
110 list<SubtargetFeature> Implies> :
111 SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
112 Value#" GPU generation", Implies>;
113
Tom Stellard880a80a2014-06-17 16:53:14 +0000[diff] [blame]114def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
115def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
116def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
117
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]118def FeatureR600 : SubtargetFeatureGeneration<"R600",
Tom Stellard880a80a2014-06-17 16:53:14 +0000[diff] [blame]119 [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]120
121def FeatureR700 : SubtargetFeatureGeneration<"R700",
Tom Stellard880a80a2014-06-17 16:53:14 +0000[diff] [blame]122 [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]123
124def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
Tom Stellard880a80a2014-06-17 16:53:14 +0000[diff] [blame]125 [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]126
127def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
Tom Stellard880a80a2014-06-17 16:53:14 +0000[diff] [blame]128 [FeatureFetchLimit16, FeatureWavefrontSize64,
129 FeatureLocalMemorySize32768]
130>;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]131
132def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
Tom Stellard880a80a2014-06-17 16:53:14 +0000[diff] [blame]133 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768]>;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]134
Tom Stellard6e1ee472013-10-29 16:37:28 +0000[diff] [blame]135def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
Tom Stellard880a80a2014-06-17 16:53:14 +0000[diff] [blame]136 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536]>;
Tom Stellard3498e4f2013-06-07 20:28:55 +0000[diff] [blame]137//===----------------------------------------------------------------------===//
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]138
139def AMDGPUInstrInfo : InstrInfo {
140 let guessInstructionProperties = 1;
141}
142
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]143def AMDGPU : Target {
144 // Pull in Instruction Info:
145 let InstructionSet = AMDGPUInstrInfo;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]146}
147
Tom Stellardbc5b5372014-06-13 16:38:59 +0000[diff] [blame]148// Dummy Instruction itineraries for pseudo instructions
149def ALU_NULL : FuncUnit;
150def NullALU : InstrItinClass;
151
Tom Stellard0e70de52014-05-16 20:56:45 +0000[diff] [blame]152//===----------------------------------------------------------------------===//
153// Predicate helper class
154//===----------------------------------------------------------------------===//
155
156class PredicateControl {
157 Predicate SubtargetPredicate;
158 list<Predicate> OtherPredicates = [];
159 list<Predicate> Predicates = !listconcat([SubtargetPredicate],
160 OtherPredicates);
161}
162
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]163// Include AMDGPU TD files
164include "R600Schedule.td"
165include "SISchedule.td"
166include "Processors.td"
167include "AMDGPUInstrInfo.td"
168include "AMDGPUIntrinsics.td"
169include "AMDGPURegisterInfo.td"
170include "AMDGPUInstructions.td"
Christian Konig2c8f6d52013-03-07 09:03:52 +0000[diff] [blame]171include "AMDGPUCallingConv.td"