Jia Liu | b22310f | 2012-02-18 12:03:15 +0000 | [diff] [blame] | 1 | //===-- ARMInstrFormats.td - ARM Instruction Formats -------*- tablegen -*-===// |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 2 | // |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 7 | // |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
| 9 | |
| 10 | //===----------------------------------------------------------------------===// |
| 11 | // |
| 12 | // ARM Instruction Format Definitions. |
| 13 | // |
| 14 | |
| 15 | // Format specifies the encoding used by the instruction. This is part of the |
| 16 | // ad-hoc solution used to emit machine instruction encodings by our machine |
| 17 | // code emitter. |
Bob Wilson | 69ba1bc | 2010-03-17 21:13:43 +0000 | [diff] [blame] | 18 | class Format<bits<6> val> { |
| 19 | bits<6> Value = val; |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 20 | } |
| 21 | |
Evan Cheng | fabdcce | 2008-11-13 23:36:57 +0000 | [diff] [blame] | 22 | def Pseudo : Format<0>; |
| 23 | def MulFrm : Format<1>; |
| 24 | def BrFrm : Format<2>; |
| 25 | def BrMiscFrm : Format<3>; |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 26 | |
Evan Cheng | fabdcce | 2008-11-13 23:36:57 +0000 | [diff] [blame] | 27 | def DPFrm : Format<4>; |
Owen Anderson | 0491270 | 2011-07-21 23:38:37 +0000 | [diff] [blame] | 28 | def DPSoRegRegFrm : Format<5>; |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 29 | |
Evan Cheng | fabdcce | 2008-11-13 23:36:57 +0000 | [diff] [blame] | 30 | def LdFrm : Format<6>; |
| 31 | def StFrm : Format<7>; |
| 32 | def LdMiscFrm : Format<8>; |
| 33 | def StMiscFrm : Format<9>; |
| 34 | def LdStMulFrm : Format<10>; |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 35 | |
Johnny Chen | 0dab68f | 2010-03-19 17:39:00 +0000 | [diff] [blame] | 36 | def LdStExFrm : Format<11>; |
Jim Grosbach | 5c4e99f | 2009-12-11 01:42:04 +0000 | [diff] [blame] | 37 | |
Johnny Chen | 0dab68f | 2010-03-19 17:39:00 +0000 | [diff] [blame] | 38 | def ArithMiscFrm : Format<12>; |
Bob Wilson | 9664984 | 2010-08-11 00:01:18 +0000 | [diff] [blame] | 39 | def SatFrm : Format<13>; |
| 40 | def ExtFrm : Format<14>; |
Evan Cheng | 8cbbcb1 | 2008-11-11 21:48:44 +0000 | [diff] [blame] | 41 | |
Bob Wilson | 9664984 | 2010-08-11 00:01:18 +0000 | [diff] [blame] | 42 | def VFPUnaryFrm : Format<15>; |
| 43 | def VFPBinaryFrm : Format<16>; |
| 44 | def VFPConv1Frm : Format<17>; |
| 45 | def VFPConv2Frm : Format<18>; |
| 46 | def VFPConv3Frm : Format<19>; |
| 47 | def VFPConv4Frm : Format<20>; |
| 48 | def VFPConv5Frm : Format<21>; |
| 49 | def VFPLdStFrm : Format<22>; |
| 50 | def VFPLdStMulFrm : Format<23>; |
| 51 | def VFPMiscFrm : Format<24>; |
Evan Cheng | 8cbbcb1 | 2008-11-11 21:48:44 +0000 | [diff] [blame] | 52 | |
Bob Wilson | 9664984 | 2010-08-11 00:01:18 +0000 | [diff] [blame] | 53 | def ThumbFrm : Format<25>; |
| 54 | def MiscFrm : Format<26>; |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 55 | |
Bob Wilson | 9664984 | 2010-08-11 00:01:18 +0000 | [diff] [blame] | 56 | def NGetLnFrm : Format<27>; |
| 57 | def NSetLnFrm : Format<28>; |
| 58 | def NDupFrm : Format<29>; |
| 59 | def NLdStFrm : Format<30>; |
| 60 | def N1RegModImmFrm: Format<31>; |
| 61 | def N2RegFrm : Format<32>; |
| 62 | def NVCVTFrm : Format<33>; |
| 63 | def NVDupLnFrm : Format<34>; |
| 64 | def N2RegVShLFrm : Format<35>; |
| 65 | def N2RegVShRFrm : Format<36>; |
| 66 | def N3RegFrm : Format<37>; |
| 67 | def N3RegVShFrm : Format<38>; |
| 68 | def NVExtFrm : Format<39>; |
| 69 | def NVMulSLFrm : Format<40>; |
| 70 | def NVTBLFrm : Format<41>; |
Owen Anderson | 0491270 | 2011-07-21 23:38:37 +0000 | [diff] [blame] | 71 | def DPSoRegImmFrm : Format<42>; |
Sam Parker | 963da5b | 2017-09-29 13:11:33 +0000 | [diff] [blame] | 72 | def N3RegCplxFrm : Format<43>; |
Johnny Chen | f833fad | 2010-03-20 00:17:00 +0000 | [diff] [blame] | 73 | |
Evan Cheng | 1496576 | 2009-07-08 01:46:35 +0000 | [diff] [blame] | 74 | // Misc flags. |
| 75 | |
Bill Wendling | cbb08ca | 2010-12-01 02:42:55 +0000 | [diff] [blame] | 76 | // The instruction has an Rn register operand. |
Evan Cheng | 1496576 | 2009-07-08 01:46:35 +0000 | [diff] [blame] | 77 | // UnaryDP - Indicates this is a unary data processing instruction, i.e. |
| 78 | // it doesn't have a Rn operand. |
| 79 | class UnaryDP { bit isUnaryDataProc = 1; } |
| 80 | |
| 81 | // Xform16Bit - Indicates this Thumb2 instruction may be transformed into |
| 82 | // a 16-bit Thumb instruction if certain conditions are met. |
| 83 | class Xform16Bit { bit canXformTo16Bit = 1; } |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 84 | |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 85 | //===----------------------------------------------------------------------===// |
Bob Wilson | a4d86b6 | 2010-03-18 23:57:57 +0000 | [diff] [blame] | 86 | // ARM Instruction flags. These need to match ARMBaseInstrInfo.h. |
Evan Cheng | b23b50d | 2009-06-29 07:51:04 +0000 | [diff] [blame] | 87 | // |
| 88 | |
Jim Grosbach | ec86bac | 2011-01-18 19:59:19 +0000 | [diff] [blame] | 89 | // FIXME: Once the JIT is MC-ized, these can go away. |
Evan Cheng | b23b50d | 2009-06-29 07:51:04 +0000 | [diff] [blame] | 90 | // Addressing mode. |
Jim Grosbach | e929899 | 2010-10-05 18:14:55 +0000 | [diff] [blame] | 91 | class AddrMode<bits<5> val> { |
| 92 | bits<5> Value = val; |
Evan Cheng | b23b50d | 2009-06-29 07:51:04 +0000 | [diff] [blame] | 93 | } |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 94 | def AddrModeNone : AddrMode<0>; |
| 95 | def AddrMode1 : AddrMode<1>; |
| 96 | def AddrMode2 : AddrMode<2>; |
| 97 | def AddrMode3 : AddrMode<3>; |
| 98 | def AddrMode4 : AddrMode<4>; |
| 99 | def AddrMode5 : AddrMode<5>; |
| 100 | def AddrMode6 : AddrMode<6>; |
| 101 | def AddrModeT1_1 : AddrMode<7>; |
| 102 | def AddrModeT1_2 : AddrMode<8>; |
| 103 | def AddrModeT1_4 : AddrMode<9>; |
| 104 | def AddrModeT1_s : AddrMode<10>; |
| 105 | def AddrModeT2_i12 : AddrMode<11>; |
| 106 | def AddrModeT2_i8 : AddrMode<12>; |
| 107 | def AddrModeT2_so : AddrMode<13>; |
| 108 | def AddrModeT2_pc : AddrMode<14>; |
Bob Wilson | deb35af | 2009-07-01 23:16:05 +0000 | [diff] [blame] | 109 | def AddrModeT2_i8s4 : AddrMode<15>; |
Jim Grosbach | 1e4d9a1 | 2010-10-26 22:37:02 +0000 | [diff] [blame] | 110 | def AddrMode_i12 : AddrMode<16>; |
Sjoerd Meijer | 011de9c | 2018-01-26 09:26:40 +0000 | [diff] [blame] | 111 | def AddrMode5FP16 : AddrMode<17>; |
Evan Cheng | b23b50d | 2009-06-29 07:51:04 +0000 | [diff] [blame] | 112 | |
Evan Cheng | b23b50d | 2009-06-29 07:51:04 +0000 | [diff] [blame] | 113 | // Load / store index mode. |
| 114 | class IndexMode<bits<2> val> { |
| 115 | bits<2> Value = val; |
| 116 | } |
| 117 | def IndexModeNone : IndexMode<0>; |
| 118 | def IndexModePre : IndexMode<1>; |
| 119 | def IndexModePost : IndexMode<2>; |
Bob Wilson | f1e8f7f | 2010-03-13 07:34:35 +0000 | [diff] [blame] | 120 | def IndexModeUpd : IndexMode<3>; |
Evan Cheng | b23b50d | 2009-06-29 07:51:04 +0000 | [diff] [blame] | 121 | |
Anton Korobeynikov | 14635da | 2009-11-02 00:10:38 +0000 | [diff] [blame] | 122 | // Instruction execution domain. |
Evan Cheng | 04ad35b | 2011-02-22 19:53:14 +0000 | [diff] [blame] | 123 | class Domain<bits<3> val> { |
| 124 | bits<3> Value = val; |
Anton Korobeynikov | 14635da | 2009-11-02 00:10:38 +0000 | [diff] [blame] | 125 | } |
| 126 | def GenericDomain : Domain<0>; |
| 127 | def VFPDomain : Domain<1>; // Instructions in VFP domain only |
| 128 | def NeonDomain : Domain<2>; // Instructions in Neon domain only |
| 129 | def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains |
Evan Cheng | 97e6428 | 2011-02-23 02:35:33 +0000 | [diff] [blame] | 130 | def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8 |
Anton Korobeynikov | 14635da | 2009-11-02 00:10:38 +0000 | [diff] [blame] | 131 | |
Evan Cheng | b23b50d | 2009-06-29 07:51:04 +0000 | [diff] [blame] | 132 | //===----------------------------------------------------------------------===// |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 133 | // ARM special operands. |
| 134 | // |
| 135 | |
Bruno Cardoso Lopes | 90d1dfe | 2011-02-14 13:09:44 +0000 | [diff] [blame] | 136 | // ARM imod and iflag operands, used only by the CPS instruction. |
| 137 | def imod_op : Operand<i32> { |
| 138 | let PrintMethod = "printCPSIMod"; |
| 139 | } |
| 140 | |
Jim Grosbach | eeaab22 | 2011-07-25 20:38:18 +0000 | [diff] [blame] | 141 | def ProcIFlagsOperand : AsmOperandClass { |
| 142 | let Name = "ProcIFlags"; |
| 143 | let ParserMethod = "parseProcIFlagsOperand"; |
| 144 | } |
Bruno Cardoso Lopes | 90d1dfe | 2011-02-14 13:09:44 +0000 | [diff] [blame] | 145 | def iflags_op : Operand<i32> { |
| 146 | let PrintMethod = "printCPSIFlag"; |
| 147 | let ParserMatchClass = ProcIFlagsOperand; |
| 148 | } |
| 149 | |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 150 | // ARM Predicate operand. Default to 14 = always (AL). Second part is CC |
| 151 | // register whose default is 0 (no register). |
Jim Grosbach | eeaab22 | 2011-07-25 20:38:18 +0000 | [diff] [blame] | 152 | def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; } |
Jim Grosbach | f86cd37 | 2011-08-19 20:46:54 +0000 | [diff] [blame] | 153 | def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 154 | (ops (i32 14), (i32 zero_reg))> { |
| 155 | let PrintMethod = "printPredicateOperand"; |
Daniel Dunbar | d8042b7 | 2010-08-11 06:36:53 +0000 | [diff] [blame] | 156 | let ParserMatchClass = CondCodeOperand; |
Jim Grosbach | dbb60f9 | 2011-08-19 20:30:19 +0000 | [diff] [blame] | 157 | let DecoderMethod = "DecodePredicateOperand"; |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 158 | } |
| 159 | |
Tim Northover | 4218044 | 2013-08-22 09:57:11 +0000 | [diff] [blame] | 160 | // Selectable predicate operand for CMOV instructions. We can't use a normal |
| 161 | // predicate because the default values interfere with instruction selection. In |
| 162 | // all other respects it is identical though: pseudo-instruction expansion |
| 163 | // relies on the MachineOperands being compatible. |
| 164 | def cmovpred : Operand<i32>, PredicateOp, |
| 165 | ComplexPattern<i32, 2, "SelectCMOVPred"> { |
| 166 | let MIOperandInfo = (ops i32imm, i32imm); |
| 167 | let PrintMethod = "printPredicateOperand"; |
| 168 | } |
| 169 | |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 170 | // Conditional code result for instructions whose 's' bit is set, e.g. subs. |
Jim Grosbach | eeaab22 | 2011-07-25 20:38:18 +0000 | [diff] [blame] | 171 | def CCOutOperand : AsmOperandClass { let Name = "CCOut"; } |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 172 | def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { |
Chris Lattner | 63274cb | 2010-11-15 05:19:05 +0000 | [diff] [blame] | 173 | let EncoderMethod = "getCCOutOpValue"; |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 174 | let PrintMethod = "printSBitModifierOperand"; |
Jim Grosbach | 0bfb4d5 | 2010-12-06 18:21:12 +0000 | [diff] [blame] | 175 | let ParserMatchClass = CCOutOperand; |
Jim Grosbach | 9c92049 | 2011-08-19 19:41:46 +0000 | [diff] [blame] | 176 | let DecoderMethod = "DecodeCCOutOperand"; |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 177 | } |
| 178 | |
| 179 | // Same as cc_out except it defaults to setting CPSR. |
| 180 | def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { |
Chris Lattner | 63274cb | 2010-11-15 05:19:05 +0000 | [diff] [blame] | 181 | let EncoderMethod = "getCCOutOpValue"; |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 182 | let PrintMethod = "printSBitModifierOperand"; |
Jim Grosbach | 0bfb4d5 | 2010-12-06 18:21:12 +0000 | [diff] [blame] | 183 | let ParserMatchClass = CCOutOperand; |
Jim Grosbach | 9c92049 | 2011-08-19 19:41:46 +0000 | [diff] [blame] | 184 | let DecoderMethod = "DecodeCCOutOperand"; |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 185 | } |
| 186 | |
Johnny Chen | 9a3e239 | 2010-03-10 18:59:38 +0000 | [diff] [blame] | 187 | // ARM special operands for disassembly only. |
| 188 | // |
Sjoerd Meijer | 1179470 | 2017-04-03 14:50:04 +0000 | [diff] [blame] | 189 | def SetEndAsmOperand : ImmAsmOperand<0,1> { |
Jim Grosbach | 0a54770 | 2011-07-22 17:44:50 +0000 | [diff] [blame] | 190 | let Name = "SetEndImm"; |
| 191 | let ParserMethod = "parseSetEndImm"; |
| 192 | } |
Jim Grosbach | 7e72ec6 | 2010-10-13 21:00:04 +0000 | [diff] [blame] | 193 | def setend_op : Operand<i32> { |
| 194 | let PrintMethod = "printSetendOperand"; |
Jim Grosbach | 0a54770 | 2011-07-22 17:44:50 +0000 | [diff] [blame] | 195 | let ParserMatchClass = SetEndAsmOperand; |
Jim Grosbach | 7e72ec6 | 2010-10-13 21:00:04 +0000 | [diff] [blame] | 196 | } |
Johnny Chen | 9a3e239 | 2010-03-10 18:59:38 +0000 | [diff] [blame] | 197 | |
Jim Grosbach | eeaab22 | 2011-07-25 20:38:18 +0000 | [diff] [blame] | 198 | def MSRMaskOperand : AsmOperandClass { |
| 199 | let Name = "MSRMask"; |
| 200 | let ParserMethod = "parseMSRMaskOperand"; |
| 201 | } |
Johnny Chen | 9a3e239 | 2010-03-10 18:59:38 +0000 | [diff] [blame] | 202 | def msr_mask : Operand<i32> { |
| 203 | let PrintMethod = "printMSRMaskOperand"; |
Owen Anderson | 6066340 | 2011-08-11 20:21:46 +0000 | [diff] [blame] | 204 | let DecoderMethod = "DecodeMSRMask"; |
Bruno Cardoso Lopes | 9cd4397 | 2011-02-18 19:45:59 +0000 | [diff] [blame] | 205 | let ParserMatchClass = MSRMaskOperand; |
Johnny Chen | 9a3e239 | 2010-03-10 18:59:38 +0000 | [diff] [blame] | 206 | } |
| 207 | |
Tim Northover | ee843ef | 2014-08-15 10:47:12 +0000 | [diff] [blame] | 208 | def BankedRegOperand : AsmOperandClass { |
| 209 | let Name = "BankedReg"; |
| 210 | let ParserMethod = "parseBankedRegOperand"; |
| 211 | } |
| 212 | def banked_reg : Operand<i32> { |
| 213 | let PrintMethod = "printBankedRegOperand"; |
| 214 | let DecoderMethod = "DecodeBankedReg"; |
| 215 | let ParserMatchClass = BankedRegOperand; |
| 216 | } |
| 217 | |
Bill Wendling | 77ad1dc | 2011-03-07 23:38:41 +0000 | [diff] [blame] | 218 | // Shift Right Immediate - A shift right immediate is encoded differently from |
| 219 | // other shift immediates. The imm6 field is encoded like so: |
Bill Wendling | 3b1459b | 2011-03-01 01:00:59 +0000 | [diff] [blame] | 220 | // |
Bill Wendling | 77ad1dc | 2011-03-07 23:38:41 +0000 | [diff] [blame] | 221 | // Offset Encoding |
| 222 | // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0> |
| 223 | // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0> |
| 224 | // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0> |
| 225 | // 64 64 - <imm> is encoded in imm6<5:0> |
Sjoerd Meijer | 1179470 | 2017-04-03 14:50:04 +0000 | [diff] [blame] | 226 | def shr_imm8_asm_operand : ImmAsmOperand<1,8> { let Name = "ShrImm8"; } |
Tim Northover | 170daaf | 2014-02-10 14:04:07 +0000 | [diff] [blame] | 227 | def shr_imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 8; }]> { |
Bill Wendling | 77ad1dc | 2011-03-07 23:38:41 +0000 | [diff] [blame] | 228 | let EncoderMethod = "getShiftRight8Imm"; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 229 | let DecoderMethod = "DecodeShiftRight8Imm"; |
Jim Grosbach | ba7d6ed | 2011-12-08 22:06:06 +0000 | [diff] [blame] | 230 | let ParserMatchClass = shr_imm8_asm_operand; |
Bill Wendling | 3b1459b | 2011-03-01 01:00:59 +0000 | [diff] [blame] | 231 | } |
Sjoerd Meijer | 1179470 | 2017-04-03 14:50:04 +0000 | [diff] [blame] | 232 | def shr_imm16_asm_operand : ImmAsmOperand<1,16> { let Name = "ShrImm16"; } |
Tim Northover | 170daaf | 2014-02-10 14:04:07 +0000 | [diff] [blame] | 233 | def shr_imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 16; }]> { |
Bill Wendling | 77ad1dc | 2011-03-07 23:38:41 +0000 | [diff] [blame] | 234 | let EncoderMethod = "getShiftRight16Imm"; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 235 | let DecoderMethod = "DecodeShiftRight16Imm"; |
Jim Grosbach | ba7d6ed | 2011-12-08 22:06:06 +0000 | [diff] [blame] | 236 | let ParserMatchClass = shr_imm16_asm_operand; |
Bill Wendling | 3b1459b | 2011-03-01 01:00:59 +0000 | [diff] [blame] | 237 | } |
Sjoerd Meijer | 1179470 | 2017-04-03 14:50:04 +0000 | [diff] [blame] | 238 | def shr_imm32_asm_operand : ImmAsmOperand<1,32> { let Name = "ShrImm32"; } |
Tim Northover | 170daaf | 2014-02-10 14:04:07 +0000 | [diff] [blame] | 239 | def shr_imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]> { |
Bill Wendling | 77ad1dc | 2011-03-07 23:38:41 +0000 | [diff] [blame] | 240 | let EncoderMethod = "getShiftRight32Imm"; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 241 | let DecoderMethod = "DecodeShiftRight32Imm"; |
Jim Grosbach | ba7d6ed | 2011-12-08 22:06:06 +0000 | [diff] [blame] | 242 | let ParserMatchClass = shr_imm32_asm_operand; |
Bill Wendling | 77ad1dc | 2011-03-07 23:38:41 +0000 | [diff] [blame] | 243 | } |
Sjoerd Meijer | 1179470 | 2017-04-03 14:50:04 +0000 | [diff] [blame] | 244 | def shr_imm64_asm_operand : ImmAsmOperand<1,64> { let Name = "ShrImm64"; } |
Tim Northover | 170daaf | 2014-02-10 14:04:07 +0000 | [diff] [blame] | 245 | def shr_imm64 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 64; }]> { |
Bill Wendling | 77ad1dc | 2011-03-07 23:38:41 +0000 | [diff] [blame] | 246 | let EncoderMethod = "getShiftRight64Imm"; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 247 | let DecoderMethod = "DecodeShiftRight64Imm"; |
Jim Grosbach | ba7d6ed | 2011-12-08 22:06:06 +0000 | [diff] [blame] | 248 | let ParserMatchClass = shr_imm64_asm_operand; |
Bill Wendling | 3b1459b | 2011-03-01 01:00:59 +0000 | [diff] [blame] | 249 | } |
| 250 | |
Renato Golin | 3f12613 | 2016-05-12 21:22:31 +0000 | [diff] [blame] | 251 | |
| 252 | // ARM Assembler operand for ldr Rd, =expression which generates an offset |
| 253 | // to a constant pool entry or a MOV depending on the value of expression |
| 254 | def const_pool_asm_operand : AsmOperandClass { let Name = "ConstPoolAsmImm"; } |
| 255 | def const_pool_asm_imm : Operand<i32> { |
| 256 | let ParserMatchClass = const_pool_asm_operand; |
| 257 | } |
| 258 | |
| 259 | |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 260 | //===----------------------------------------------------------------------===// |
Jim Grosbach | 6caa557 | 2011-08-22 18:04:24 +0000 | [diff] [blame] | 261 | // ARM Assembler alias templates. |
| 262 | // |
Sjoerd Meijer | 9da258d | 2016-06-03 13:19:43 +0000 | [diff] [blame] | 263 | // Note: When EmitPriority == 1, the alias will be used for printing |
| 264 | class ARMInstAlias<string Asm, dag Result, bit EmitPriority = 0> |
| 265 | : InstAlias<Asm, Result, EmitPriority>, Requires<[IsARM]>; |
Sanne Wouda | 2409c64 | 2017-03-21 14:59:17 +0000 | [diff] [blame] | 266 | class ARMInstSubst<string Asm, dag Result, bit EmitPriority = 0> |
| 267 | : InstAlias<Asm, Result, EmitPriority>, |
| 268 | Requires<[IsARM,UseNegativeImmediates]>; |
Sjoerd Meijer | 9da258d | 2016-06-03 13:19:43 +0000 | [diff] [blame] | 269 | class tInstAlias<string Asm, dag Result, bit EmitPriority = 0> |
| 270 | : InstAlias<Asm, Result, EmitPriority>, Requires<[IsThumb]>; |
Sanne Wouda | 2409c64 | 2017-03-21 14:59:17 +0000 | [diff] [blame] | 271 | class tInstSubst<string Asm, dag Result, bit EmitPriority = 0> |
| 272 | : InstAlias<Asm, Result, EmitPriority>, |
| 273 | Requires<[IsThumb,UseNegativeImmediates]>; |
Sjoerd Meijer | 9da258d | 2016-06-03 13:19:43 +0000 | [diff] [blame] | 274 | class t2InstAlias<string Asm, dag Result, bit EmitPriority = 0> |
| 275 | : InstAlias<Asm, Result, EmitPriority>, Requires<[IsThumb2]>; |
Sanne Wouda | 2409c64 | 2017-03-21 14:59:17 +0000 | [diff] [blame] | 276 | class t2InstSubst<string Asm, dag Result, bit EmitPriority = 0> |
| 277 | : InstAlias<Asm, Result, EmitPriority>, |
| 278 | Requires<[IsThumb2,UseNegativeImmediates]>; |
Sjoerd Meijer | 9da258d | 2016-06-03 13:19:43 +0000 | [diff] [blame] | 279 | class VFP2InstAlias<string Asm, dag Result, bit EmitPriority = 0> |
| 280 | : InstAlias<Asm, Result, EmitPriority>, Requires<[HasVFP2]>; |
| 281 | class VFP2DPInstAlias<string Asm, dag Result, bit EmitPriority = 0> |
| 282 | : InstAlias<Asm, Result, EmitPriority>, Requires<[HasVFP2,HasDPVFP]>; |
| 283 | class VFP3InstAlias<string Asm, dag Result, bit EmitPriority = 0> |
| 284 | : InstAlias<Asm, Result, EmitPriority>, Requires<[HasVFP3]>; |
| 285 | class NEONInstAlias<string Asm, dag Result, bit EmitPriority = 0> |
| 286 | : InstAlias<Asm, Result, EmitPriority>, Requires<[HasNEON]>; |
Jim Grosbach | 6caa557 | 2011-08-22 18:04:24 +0000 | [diff] [blame] | 287 | |
Jim Grosbach | 9227f39 | 2011-12-13 20:08:32 +0000 | [diff] [blame] | 288 | |
| 289 | class VFP2MnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>, |
| 290 | Requires<[HasVFP2]>; |
| 291 | class NEONMnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>, |
| 292 | Requires<[HasNEON]>; |
| 293 | |
Jim Grosbach | 6caa557 | 2011-08-22 18:04:24 +0000 | [diff] [blame] | 294 | //===----------------------------------------------------------------------===// |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 295 | // ARM Instruction templates. |
| 296 | // |
| 297 | |
Jim Grosbach | 6caa557 | 2011-08-22 18:04:24 +0000 | [diff] [blame] | 298 | |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 299 | class InstTemplate<AddrMode am, int sz, IndexMode im, |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 300 | Format f, Domain d, string cstr, InstrItinClass itin> |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 301 | : Instruction { |
| 302 | let Namespace = "ARM"; |
| 303 | |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 304 | AddrMode AM = am; |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 305 | int Size = sz; |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 306 | IndexMode IM = im; |
| 307 | bits<2> IndexModeBits = IM.Value; |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 308 | Format F = f; |
Bob Wilson | 69ba1bc | 2010-03-17 21:13:43 +0000 | [diff] [blame] | 309 | bits<6> Form = F.Value; |
Anton Korobeynikov | 14635da | 2009-11-02 00:10:38 +0000 | [diff] [blame] | 310 | Domain D = d; |
Evan Cheng | 81889d01 | 2008-11-05 18:35:52 +0000 | [diff] [blame] | 311 | bit isUnaryDataProc = 0; |
Evan Cheng | 1496576 | 2009-07-08 01:46:35 +0000 | [diff] [blame] | 312 | bit canXformTo16Bit = 0; |
Jim Grosbach | 3e941ae | 2011-08-16 20:45:50 +0000 | [diff] [blame] | 313 | // The instruction is a 16-bit flag setting Thumb instruction. Used |
| 314 | // by the parser to determine whether to require the 'S' suffix on the |
| 315 | // mnemonic (when not in an IT block) or preclude it (when in an IT block). |
| 316 | bit thumbArithFlagSetting = 0; |
Jim Grosbach | 5876e41 | 2010-11-19 22:42:55 +0000 | [diff] [blame] | 317 | |
Chris Lattner | 7ff3346 | 2010-10-31 19:22:57 +0000 | [diff] [blame] | 318 | // If this is a pseudo instruction, mark it isCodeGenOnly. |
| 319 | let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo"); |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 320 | |
Jim Grosbach | 30694dc | 2011-08-15 16:52:24 +0000 | [diff] [blame] | 321 | // The layout of TSFlags should be kept in sync with ARMBaseInfo.h. |
Jim Grosbach | e929899 | 2010-10-05 18:14:55 +0000 | [diff] [blame] | 322 | let TSFlags{4-0} = AM.Value; |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 323 | let TSFlags{6-5} = IndexModeBits; |
| 324 | let TSFlags{12-7} = Form; |
| 325 | let TSFlags{13} = isUnaryDataProc; |
| 326 | let TSFlags{14} = canXformTo16Bit; |
| 327 | let TSFlags{17-15} = D.Value; |
Jim Grosbach | 3e941ae | 2011-08-16 20:45:50 +0000 | [diff] [blame] | 328 | let TSFlags{18} = thumbArithFlagSetting; |
Jakob Stoklund Olesen | b93331f | 2010-04-05 03:10:20 +0000 | [diff] [blame] | 329 | |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 330 | let Constraints = cstr; |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 331 | let Itinerary = itin; |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 332 | } |
| 333 | |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 334 | class Encoding { |
| 335 | field bits<32> Inst; |
James Molloy | d9ba4fd | 2012-02-09 10:56:31 +0000 | [diff] [blame] | 336 | // Mask of bits that cause an encoding to be UNPREDICTABLE. |
| 337 | // If a bit is set, then if the corresponding bit in the |
| 338 | // target encoding differs from its value in the "Inst" field, |
| 339 | // the instruction is UNPREDICTABLE (SoftFail in abstract parlance). |
| 340 | field bits<32> Unpredictable = 0; |
| 341 | // SoftFail is the generic name for this field, but we alias it so |
| 342 | // as to make it more obvious what it means in ARM-land. |
| 343 | field bits<32> SoftFail = Unpredictable; |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 344 | } |
| 345 | |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 346 | class InstARM<AddrMode am, int sz, IndexMode im, |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 347 | Format f, Domain d, string cstr, InstrItinClass itin> |
Owen Anderson | c78e03c | 2011-07-19 21:06:00 +0000 | [diff] [blame] | 348 | : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding { |
| 349 | let DecoderNamespace = "ARM"; |
| 350 | } |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 351 | |
| 352 | // This Encoding-less class is used by Thumb1 to specify the encoding bits later |
| 353 | // on by adding flavors to specific instructions. |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 354 | class InstThumb<AddrMode am, int sz, IndexMode im, |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 355 | Format f, Domain d, string cstr, InstrItinClass itin> |
Owen Anderson | c78e03c | 2011-07-19 21:06:00 +0000 | [diff] [blame] | 356 | : InstTemplate<am, sz, im, f, d, cstr, itin> { |
| 357 | let DecoderNamespace = "Thumb"; |
| 358 | } |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 359 | |
Jim Grosbach | fb2f1d6 | 2011-11-01 01:24:45 +0000 | [diff] [blame] | 360 | // Pseudo-instructions for alternate assembly syntax (never used by codegen). |
| 361 | // These are aliases that require C++ handling to convert to the target |
| 362 | // instruction, while InstAliases can be handled directly by tblgen. |
Saleem Abdulrasool | fb3950e | 2014-01-12 04:36:01 +0000 | [diff] [blame] | 363 | class AsmPseudoInst<string asm, dag iops, dag oops = (outs)> |
Jim Grosbach | fb2f1d6 | 2011-11-01 01:24:45 +0000 | [diff] [blame] | 364 | : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, |
| 365 | "", NoItinerary> { |
Saleem Abdulrasool | fb3950e | 2014-01-12 04:36:01 +0000 | [diff] [blame] | 366 | let OutOperandList = oops; |
Jim Grosbach | fb2f1d6 | 2011-11-01 01:24:45 +0000 | [diff] [blame] | 367 | let InOperandList = iops; |
| 368 | let Pattern = []; |
| 369 | let isCodeGenOnly = 0; // So we get asm matcher for it. |
Jim Grosbach | 61db5a5 | 2011-11-10 16:44:55 +0000 | [diff] [blame] | 370 | let AsmString = asm; |
Jim Grosbach | fb2f1d6 | 2011-11-01 01:24:45 +0000 | [diff] [blame] | 371 | let isPseudo = 1; |
| 372 | } |
| 373 | |
Saleem Abdulrasool | fb3950e | 2014-01-12 04:36:01 +0000 | [diff] [blame] | 374 | class ARMAsmPseudo<string asm, dag iops, dag oops = (outs)> |
| 375 | : AsmPseudoInst<asm, iops, oops>, Requires<[IsARM]>; |
| 376 | class tAsmPseudo<string asm, dag iops, dag oops = (outs)> |
| 377 | : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb]>; |
| 378 | class t2AsmPseudo<string asm, dag iops, dag oops = (outs)> |
| 379 | : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb2]>; |
| 380 | class VFP2AsmPseudo<string asm, dag iops, dag oops = (outs)> |
| 381 | : AsmPseudoInst<asm, iops, oops>, Requires<[HasVFP2]>; |
| 382 | class NEONAsmPseudo<string asm, dag iops, dag oops = (outs)> |
| 383 | : AsmPseudoInst<asm, iops, oops>, Requires<[HasNEON]>; |
Jim Grosbach | fb2f1d6 | 2011-11-01 01:24:45 +0000 | [diff] [blame] | 384 | |
| 385 | // Pseudo instructions for the code generator. |
Jim Grosbach | a74c7ccd | 2010-11-18 01:38:26 +0000 | [diff] [blame] | 386 | class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 387 | : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, |
Jim Grosbach | 7c301ea | 2011-07-06 21:35:46 +0000 | [diff] [blame] | 388 | GenericDomain, "", itin> { |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 389 | let OutOperandList = oops; |
| 390 | let InOperandList = iops; |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 391 | let Pattern = pattern; |
Jim Grosbach | e175682 | 2011-03-10 19:06:39 +0000 | [diff] [blame] | 392 | let isCodeGenOnly = 1; |
Jim Grosbach | 7c301ea | 2011-07-06 21:35:46 +0000 | [diff] [blame] | 393 | let isPseudo = 1; |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 394 | } |
| 395 | |
Jim Grosbach | cfb6620 | 2010-11-18 01:15:56 +0000 | [diff] [blame] | 396 | // PseudoInst that's ARM-mode only. |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 397 | class ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, |
Jim Grosbach | a74c7ccd | 2010-11-18 01:38:26 +0000 | [diff] [blame] | 398 | list<dag> pattern> |
| 399 | : PseudoInst<oops, iops, itin, pattern> { |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 400 | let Size = sz; |
Jim Grosbach | cfb6620 | 2010-11-18 01:15:56 +0000 | [diff] [blame] | 401 | list<Predicate> Predicates = [IsARM]; |
| 402 | } |
| 403 | |
Jim Grosbach | 58bc36a | 2010-11-29 19:32:47 +0000 | [diff] [blame] | 404 | // PseudoInst that's Thumb-mode only. |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 405 | class tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, |
Jim Grosbach | 58bc36a | 2010-11-29 19:32:47 +0000 | [diff] [blame] | 406 | list<dag> pattern> |
| 407 | : PseudoInst<oops, iops, itin, pattern> { |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 408 | let Size = sz; |
Jim Grosbach | 58bc36a | 2010-11-29 19:32:47 +0000 | [diff] [blame] | 409 | list<Predicate> Predicates = [IsThumb]; |
| 410 | } |
Jim Grosbach | cfb6620 | 2010-11-18 01:15:56 +0000 | [diff] [blame] | 411 | |
Prakhar Bahuguna | 52a7dd7 | 2016-12-15 07:59:08 +0000 | [diff] [blame] | 412 | // PseudoInst that's in ARMv8-M baseline (Somewhere between Thumb and Thumb2) |
| 413 | class t2basePseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, |
| 414 | list<dag> pattern> |
| 415 | : PseudoInst<oops, iops, itin, pattern> { |
| 416 | let Size = sz; |
| 417 | list<Predicate> Predicates = [IsThumb,HasV8MBaseline]; |
| 418 | } |
| 419 | |
Jim Grosbach | d42257c | 2010-12-15 18:48:45 +0000 | [diff] [blame] | 420 | // PseudoInst that's Thumb2-mode only. |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 421 | class t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, |
Jim Grosbach | d42257c | 2010-12-15 18:48:45 +0000 | [diff] [blame] | 422 | list<dag> pattern> |
| 423 | : PseudoInst<oops, iops, itin, pattern> { |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 424 | let Size = sz; |
Jim Grosbach | d42257c | 2010-12-15 18:48:45 +0000 | [diff] [blame] | 425 | list<Predicate> Predicates = [IsThumb2]; |
| 426 | } |
Jim Grosbach | 95dee40 | 2011-07-08 17:40:42 +0000 | [diff] [blame] | 427 | |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 428 | class ARMPseudoExpand<dag oops, dag iops, int sz, |
Jim Grosbach | 95dee40 | 2011-07-08 17:40:42 +0000 | [diff] [blame] | 429 | InstrItinClass itin, list<dag> pattern, |
| 430 | dag Result> |
| 431 | : ARMPseudoInst<oops, iops, sz, itin, pattern>, |
| 432 | PseudoInstExpansion<Result>; |
| 433 | |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 434 | class tPseudoExpand<dag oops, dag iops, int sz, |
Jim Grosbach | 95dee40 | 2011-07-08 17:40:42 +0000 | [diff] [blame] | 435 | InstrItinClass itin, list<dag> pattern, |
| 436 | dag Result> |
| 437 | : tPseudoInst<oops, iops, sz, itin, pattern>, |
| 438 | PseudoInstExpansion<Result>; |
| 439 | |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 440 | class t2PseudoExpand<dag oops, dag iops, int sz, |
Jim Grosbach | 95dee40 | 2011-07-08 17:40:42 +0000 | [diff] [blame] | 441 | InstrItinClass itin, list<dag> pattern, |
| 442 | dag Result> |
| 443 | : t2PseudoInst<oops, iops, sz, itin, pattern>, |
| 444 | PseudoInstExpansion<Result>; |
| 445 | |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 446 | // Almost all ARM instructions are predicable. |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 447 | class I<dag oops, dag iops, AddrMode am, int sz, |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 448 | IndexMode im, Format f, InstrItinClass itin, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 449 | string opc, string asm, string cstr, |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 450 | list<dag> pattern> |
Anton Korobeynikov | 14635da | 2009-11-02 00:10:38 +0000 | [diff] [blame] | 451 | : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { |
Jim Grosbach | 5476a27 | 2010-10-11 18:51:51 +0000 | [diff] [blame] | 452 | bits<4> p; |
| 453 | let Inst{31-28} = p; |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 454 | let OutOperandList = oops; |
Chris Lattner | fb2ceed | 2010-03-18 21:06:54 +0000 | [diff] [blame] | 455 | let InOperandList = !con(iops, (ins pred:$p)); |
Chris Lattner | 04c342e | 2010-10-06 00:05:18 +0000 | [diff] [blame] | 456 | let AsmString = !strconcat(opc, "${p}", asm); |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 457 | let Pattern = pattern; |
| 458 | list<Predicate> Predicates = [IsARM]; |
| 459 | } |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 460 | |
Jim Grosbach | 5e0d2a2 | 2009-12-14 18:31:20 +0000 | [diff] [blame] | 461 | // A few are not predicable |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 462 | class InoP<dag oops, dag iops, AddrMode am, int sz, |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 463 | IndexMode im, Format f, InstrItinClass itin, |
| 464 | string opc, string asm, string cstr, |
| 465 | list<dag> pattern> |
Jim Grosbach | 5e0d2a2 | 2009-12-14 18:31:20 +0000 | [diff] [blame] | 466 | : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { |
| 467 | let OutOperandList = oops; |
| 468 | let InOperandList = iops; |
Bob Wilson | 722bff2 | 2010-05-24 20:08:34 +0000 | [diff] [blame] | 469 | let AsmString = !strconcat(opc, asm); |
Jim Grosbach | 5e0d2a2 | 2009-12-14 18:31:20 +0000 | [diff] [blame] | 470 | let Pattern = pattern; |
| 471 | let isPredicable = 0; |
| 472 | list<Predicate> Predicates = [IsARM]; |
| 473 | } |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 474 | |
Bill Wendling | f8dfa46 | 2010-08-30 01:47:35 +0000 | [diff] [blame] | 475 | // Same as I except it can optionally modify CPSR. Note it's modeled as an input |
| 476 | // operand since by default it's a zero register. It will become an implicit def |
| 477 | // once it's "flipped". |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 478 | class sI<dag oops, dag iops, AddrMode am, int sz, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 479 | IndexMode im, Format f, InstrItinClass itin, |
| 480 | string opc, string asm, string cstr, |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 481 | list<dag> pattern> |
Anton Korobeynikov | 14635da | 2009-11-02 00:10:38 +0000 | [diff] [blame] | 482 | : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { |
Jim Grosbach | 5476a27 | 2010-10-11 18:51:51 +0000 | [diff] [blame] | 483 | bits<4> p; // Predicate operand |
Jim Grosbach | d9d31da | 2010-10-12 23:00:24 +0000 | [diff] [blame] | 484 | bits<1> s; // condition-code set flag ('1' if the insn should set the flags) |
Jim Grosbach | 5476a27 | 2010-10-11 18:51:51 +0000 | [diff] [blame] | 485 | let Inst{31-28} = p; |
Jim Grosbach | d9d31da | 2010-10-12 23:00:24 +0000 | [diff] [blame] | 486 | let Inst{20} = s; |
Jim Grosbach | 5476a27 | 2010-10-11 18:51:51 +0000 | [diff] [blame] | 487 | |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 488 | let OutOperandList = oops; |
Chris Lattner | fb2ceed | 2010-03-18 21:06:54 +0000 | [diff] [blame] | 489 | let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); |
Bob Wilson | 5935184 | 2010-10-15 03:23:44 +0000 | [diff] [blame] | 490 | let AsmString = !strconcat(opc, "${s}${p}", asm); |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 491 | let Pattern = pattern; |
| 492 | list<Predicate> Predicates = [IsARM]; |
| 493 | } |
| 494 | |
Evan Cheng | a282723 | 2008-09-01 07:19:00 +0000 | [diff] [blame] | 495 | // Special cases |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 496 | class XI<dag oops, dag iops, AddrMode am, int sz, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 497 | IndexMode im, Format f, InstrItinClass itin, |
| 498 | string asm, string cstr, list<dag> pattern> |
Anton Korobeynikov | 14635da | 2009-11-02 00:10:38 +0000 | [diff] [blame] | 499 | : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { |
Evan Cheng | a282723 | 2008-09-01 07:19:00 +0000 | [diff] [blame] | 500 | let OutOperandList = oops; |
| 501 | let InOperandList = iops; |
Bob Wilson | 722bff2 | 2010-05-24 20:08:34 +0000 | [diff] [blame] | 502 | let AsmString = asm; |
Evan Cheng | a282723 | 2008-09-01 07:19:00 +0000 | [diff] [blame] | 503 | let Pattern = pattern; |
| 504 | list<Predicate> Predicates = [IsARM]; |
| 505 | } |
| 506 | |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 507 | class AI<dag oops, dag iops, Format f, InstrItinClass itin, |
| 508 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 509 | : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 510 | opc, asm, "", pattern>; |
| 511 | class AsI<dag oops, dag iops, Format f, InstrItinClass itin, |
| 512 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 513 | : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 514 | opc, asm, "", pattern>; |
| 515 | class AXI<dag oops, dag iops, Format f, InstrItinClass itin, |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 516 | string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 517 | : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, |
Evan Cheng | 49d6652 | 2008-11-06 22:15:19 +0000 | [diff] [blame] | 518 | asm, "", pattern>; |
David Peixotto | b76f55f | 2014-01-27 21:39:04 +0000 | [diff] [blame] | 519 | class AXIM<dag oops, dag iops, AddrMode am, Format f, InstrItinClass itin, |
| 520 | string asm, list<dag> pattern> |
| 521 | : XI<oops, iops, am, 4, IndexModeNone, f, itin, |
| 522 | asm, "", pattern>; |
Jim Grosbach | 5e0d2a2 | 2009-12-14 18:31:20 +0000 | [diff] [blame] | 523 | class AInoP<dag oops, dag iops, Format f, InstrItinClass itin, |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 524 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 525 | : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 526 | opc, asm, "", pattern>; |
Evan Cheng | fa55878 | 2008-09-01 08:25:56 +0000 | [diff] [blame] | 527 | |
| 528 | // Ctrl flow instructions |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 529 | class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, |
| 530 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 531 | : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 532 | opc, asm, "", pattern> { |
Jim Grosbach | b7c01f5 | 2008-10-14 20:36:24 +0000 | [diff] [blame] | 533 | let Inst{27-24} = opcod; |
Evan Cheng | fa55878 | 2008-09-01 08:25:56 +0000 | [diff] [blame] | 534 | } |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 535 | class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, |
| 536 | string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 537 | : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 538 | asm, "", pattern> { |
Jim Grosbach | b7c01f5 | 2008-10-14 20:36:24 +0000 | [diff] [blame] | 539 | let Inst{27-24} = opcod; |
Evan Cheng | fa55878 | 2008-09-01 08:25:56 +0000 | [diff] [blame] | 540 | } |
Evan Cheng | fa55878 | 2008-09-01 08:25:56 +0000 | [diff] [blame] | 541 | |
| 542 | // BR_JT instructions |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 543 | class JTI<dag oops, dag iops, InstrItinClass itin, |
| 544 | string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 545 | : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin, |
Evan Cheng | 7095cd2 | 2008-11-07 09:06:08 +0000 | [diff] [blame] | 546 | asm, "", pattern>; |
Evan Cheng | 624844b | 2008-09-01 01:51:14 +0000 | [diff] [blame] | 547 | |
Joey Gouly | e6d165c | 2013-08-27 17:38:16 +0000 | [diff] [blame] | 548 | class AIldr_ex_or_acq<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin, |
Jim Grosbach | 5c4e99f | 2009-12-11 01:42:04 +0000 | [diff] [blame] | 549 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 550 | : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin, |
Jim Grosbach | 5c4e99f | 2009-12-11 01:42:04 +0000 | [diff] [blame] | 551 | opc, asm, "", pattern> { |
Jim Grosbach | 4e57b52 | 2010-10-29 19:58:57 +0000 | [diff] [blame] | 552 | bits<4> Rt; |
Jim Grosbach | cb31193 | 2011-07-26 17:44:46 +0000 | [diff] [blame] | 553 | bits<4> addr; |
Jim Grosbach | 5c4e99f | 2009-12-11 01:42:04 +0000 | [diff] [blame] | 554 | let Inst{27-23} = 0b00011; |
| 555 | let Inst{22-21} = opcod; |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 556 | let Inst{20} = 1; |
Jim Grosbach | cb31193 | 2011-07-26 17:44:46 +0000 | [diff] [blame] | 557 | let Inst{19-16} = addr; |
Jim Grosbach | 4e57b52 | 2010-10-29 19:58:57 +0000 | [diff] [blame] | 558 | let Inst{15-12} = Rt; |
Joey Gouly | e6d165c | 2013-08-27 17:38:16 +0000 | [diff] [blame] | 559 | let Inst{11-10} = 0b11; |
| 560 | let Inst{9-8} = opcod2; |
| 561 | let Inst{7-0} = 0b10011111; |
Jim Grosbach | 5c4e99f | 2009-12-11 01:42:04 +0000 | [diff] [blame] | 562 | } |
Joey Gouly | e6d165c | 2013-08-27 17:38:16 +0000 | [diff] [blame] | 563 | class AIstr_ex_or_rel<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin, |
Jim Grosbach | 5c4e99f | 2009-12-11 01:42:04 +0000 | [diff] [blame] | 564 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 565 | : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin, |
Jim Grosbach | 5c4e99f | 2009-12-11 01:42:04 +0000 | [diff] [blame] | 566 | opc, asm, "", pattern> { |
Jim Grosbach | 4e57b52 | 2010-10-29 19:58:57 +0000 | [diff] [blame] | 567 | bits<4> Rt; |
Bruno Cardoso Lopes | f170f8b | 2011-03-24 21:04:58 +0000 | [diff] [blame] | 568 | bits<4> addr; |
Jim Grosbach | 5c4e99f | 2009-12-11 01:42:04 +0000 | [diff] [blame] | 569 | let Inst{27-23} = 0b00011; |
| 570 | let Inst{22-21} = opcod; |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 571 | let Inst{20} = 0; |
Bruno Cardoso Lopes | f170f8b | 2011-03-24 21:04:58 +0000 | [diff] [blame] | 572 | let Inst{19-16} = addr; |
Joey Gouly | e6d165c | 2013-08-27 17:38:16 +0000 | [diff] [blame] | 573 | let Inst{11-10} = 0b11; |
| 574 | let Inst{9-8} = opcod2; |
| 575 | let Inst{7-4} = 0b1001; |
Jim Grosbach | 4e57b52 | 2010-10-29 19:58:57 +0000 | [diff] [blame] | 576 | let Inst{3-0} = Rt; |
Jim Grosbach | 5c4e99f | 2009-12-11 01:42:04 +0000 | [diff] [blame] | 577 | } |
Joey Gouly | e6d165c | 2013-08-27 17:38:16 +0000 | [diff] [blame] | 578 | // Atomic load/store instructions |
| 579 | class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, |
| 580 | string opc, string asm, list<dag> pattern> |
| 581 | : AIldr_ex_or_acq<opcod, 0b11, oops, iops, itin, opc, asm, pattern>; |
| 582 | |
| 583 | class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, |
| 584 | string opc, string asm, list<dag> pattern> |
| 585 | : AIstr_ex_or_rel<opcod, 0b11, oops, iops, itin, opc, asm, pattern> { |
| 586 | bits<4> Rd; |
| 587 | let Inst{15-12} = Rd; |
| 588 | } |
| 589 | |
| 590 | // Exclusive load/store instructions |
| 591 | |
| 592 | class AIldaex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, |
| 593 | string opc, string asm, list<dag> pattern> |
| 594 | : AIldr_ex_or_acq<opcod, 0b10, oops, iops, itin, opc, asm, pattern>, |
Bradley Smith | 4c21cba | 2016-01-15 10:23:46 +0000 | [diff] [blame] | 595 | Requires<[IsARM, HasAcquireRelease, HasV7Clrex]>; |
Joey Gouly | e6d165c | 2013-08-27 17:38:16 +0000 | [diff] [blame] | 596 | |
| 597 | class AIstlex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, |
| 598 | string opc, string asm, list<dag> pattern> |
| 599 | : AIstr_ex_or_rel<opcod, 0b10, oops, iops, itin, opc, asm, pattern>, |
Bradley Smith | 4c21cba | 2016-01-15 10:23:46 +0000 | [diff] [blame] | 600 | Requires<[IsARM, HasAcquireRelease, HasV7Clrex]> { |
Joey Gouly | e6d165c | 2013-08-27 17:38:16 +0000 | [diff] [blame] | 601 | bits<4> Rd; |
| 602 | let Inst{15-12} = Rd; |
| 603 | } |
| 604 | |
Jim Grosbach | 3b7e05b | 2010-10-29 20:21:36 +0000 | [diff] [blame] | 605 | class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern> |
Jim Grosbach | 15e8d74 | 2011-07-26 17:15:11 +0000 | [diff] [blame] | 606 | : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> { |
Jim Grosbach | 3b7e05b | 2010-10-29 20:21:36 +0000 | [diff] [blame] | 607 | bits<4> Rt; |
| 608 | bits<4> Rt2; |
Jim Grosbach | 15e8d74 | 2011-07-26 17:15:11 +0000 | [diff] [blame] | 609 | bits<4> addr; |
Jim Grosbach | 3b7e05b | 2010-10-29 20:21:36 +0000 | [diff] [blame] | 610 | let Inst{27-23} = 0b00010; |
| 611 | let Inst{22} = b; |
| 612 | let Inst{21-20} = 0b00; |
Jim Grosbach | 15e8d74 | 2011-07-26 17:15:11 +0000 | [diff] [blame] | 613 | let Inst{19-16} = addr; |
Jim Grosbach | 3b7e05b | 2010-10-29 20:21:36 +0000 | [diff] [blame] | 614 | let Inst{15-12} = Rt; |
| 615 | let Inst{11-4} = 0b00001001; |
| 616 | let Inst{3-0} = Rt2; |
Owen Anderson | dde461c | 2011-10-28 18:02:13 +0000 | [diff] [blame] | 617 | |
Silviu Baranga | ca45af9 | 2012-04-18 14:18:57 +0000 | [diff] [blame] | 618 | let Unpredictable{11-8} = 0b1111; |
Owen Anderson | dde461c | 2011-10-28 18:02:13 +0000 | [diff] [blame] | 619 | let DecoderMethod = "DecodeSwap"; |
Jim Grosbach | 3b7e05b | 2010-10-29 20:21:36 +0000 | [diff] [blame] | 620 | } |
Joey Gouly | e6d165c | 2013-08-27 17:38:16 +0000 | [diff] [blame] | 621 | // Acquire/Release load/store instructions |
| 622 | class AIldracq<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, |
| 623 | string opc, string asm, list<dag> pattern> |
| 624 | : AIldr_ex_or_acq<opcod, 0b00, oops, iops, itin, opc, asm, pattern>, |
Bradley Smith | 4c21cba | 2016-01-15 10:23:46 +0000 | [diff] [blame] | 625 | Requires<[IsARM, HasAcquireRelease]>; |
Joey Gouly | e6d165c | 2013-08-27 17:38:16 +0000 | [diff] [blame] | 626 | |
| 627 | class AIstrrel<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, |
| 628 | string opc, string asm, list<dag> pattern> |
| 629 | : AIstr_ex_or_rel<opcod, 0b00, oops, iops, itin, opc, asm, pattern>, |
Bradley Smith | 4c21cba | 2016-01-15 10:23:46 +0000 | [diff] [blame] | 630 | Requires<[IsARM, HasAcquireRelease]> { |
Joey Gouly | e6d165c | 2013-08-27 17:38:16 +0000 | [diff] [blame] | 631 | let Inst{15-12} = 0b1111; |
| 632 | } |
Jim Grosbach | 5c4e99f | 2009-12-11 01:42:04 +0000 | [diff] [blame] | 633 | |
Evan Cheng | 624844b | 2008-09-01 01:51:14 +0000 | [diff] [blame] | 634 | // addrmode1 instructions |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 635 | class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, |
| 636 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 637 | : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 638 | opc, asm, "", pattern> { |
Jim Grosbach | b7c01f5 | 2008-10-14 20:36:24 +0000 | [diff] [blame] | 639 | let Inst{24-21} = opcod; |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 640 | let Inst{27-26} = 0b00; |
Evan Cheng | c139c22 | 2008-08-29 07:40:52 +0000 | [diff] [blame] | 641 | } |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 642 | class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, |
| 643 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 644 | : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 645 | opc, asm, "", pattern> { |
| 646 | let Inst{24-21} = opcod; |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 647 | let Inst{27-26} = 0b00; |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 648 | } |
| 649 | class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 650 | string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 651 | : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, |
Evan Cheng | c139c22 | 2008-08-29 07:40:52 +0000 | [diff] [blame] | 652 | asm, "", pattern> { |
Jim Grosbach | b7c01f5 | 2008-10-14 20:36:24 +0000 | [diff] [blame] | 653 | let Inst{24-21} = opcod; |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 654 | let Inst{27-26} = 0b00; |
Evan Cheng | c139c22 | 2008-08-29 07:40:52 +0000 | [diff] [blame] | 655 | } |
Evan Cheng | 624844b | 2008-09-01 01:51:14 +0000 | [diff] [blame] | 656 | |
Evan Cheng | cccca87 | 2008-09-01 01:27:33 +0000 | [diff] [blame] | 657 | // loads |
Jim Grosbach | 1e4d9a1 | 2010-10-26 22:37:02 +0000 | [diff] [blame] | 658 | |
Jim Grosbach | 4a22eba | 2010-11-19 21:07:51 +0000 | [diff] [blame] | 659 | // LDR/LDRB/STR/STRB/... |
| 660 | class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am, |
Jim Grosbach | 338de3e | 2010-10-27 23:12:14 +0000 | [diff] [blame] | 661 | Format f, InstrItinClass itin, string opc, string asm, |
| 662 | list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 663 | : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm, |
Jim Grosbach | 1e4d9a1 | 2010-10-26 22:37:02 +0000 | [diff] [blame] | 664 | "", pattern> { |
| 665 | let Inst{27-25} = op; |
| 666 | let Inst{24} = 1; // 24 == P |
| 667 | // 23 == U |
Jim Grosbach | 2f79074 | 2010-11-13 00:35:48 +0000 | [diff] [blame] | 668 | let Inst{22} = isByte; |
Jim Grosbach | 1e4d9a1 | 2010-10-26 22:37:02 +0000 | [diff] [blame] | 669 | let Inst{21} = 0; // 21 == W |
Jim Grosbach | 338de3e | 2010-10-27 23:12:14 +0000 | [diff] [blame] | 670 | let Inst{20} = isLd; |
Jim Grosbach | 1e4d9a1 | 2010-10-26 22:37:02 +0000 | [diff] [blame] | 671 | } |
Jim Grosbach | 2f79074 | 2010-11-13 00:35:48 +0000 | [diff] [blame] | 672 | // Indexed load/stores |
| 673 | class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops, |
Jim Grosbach | 6e9aace | 2010-11-19 21:35:06 +0000 | [diff] [blame] | 674 | IndexMode im, Format f, InstrItinClass itin, string opc, |
Jim Grosbach | 2f79074 | 2010-11-13 00:35:48 +0000 | [diff] [blame] | 675 | string asm, string cstr, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 676 | : I<oops, iops, AddrMode2, 4, im, f, itin, |
Jim Grosbach | 2f79074 | 2010-11-13 00:35:48 +0000 | [diff] [blame] | 677 | opc, asm, cstr, pattern> { |
Jim Grosbach | 38b469e | 2010-11-15 20:47:07 +0000 | [diff] [blame] | 678 | bits<4> Rt; |
Jim Grosbach | 2f79074 | 2010-11-13 00:35:48 +0000 | [diff] [blame] | 679 | let Inst{27-26} = 0b01; |
| 680 | let Inst{24} = isPre; // P bit |
| 681 | let Inst{22} = isByte; // B bit |
| 682 | let Inst{21} = isPre; // W bit |
| 683 | let Inst{20} = isLd; // L bit |
Jim Grosbach | 38b469e | 2010-11-15 20:47:07 +0000 | [diff] [blame] | 684 | let Inst{15-12} = Rt; |
Jim Grosbach | 1e4d9a1 | 2010-10-26 22:37:02 +0000 | [diff] [blame] | 685 | } |
Owen Anderson | 2aedba6 | 2011-07-26 20:54:26 +0000 | [diff] [blame] | 686 | class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops, |
Jim Grosbach | 6e9aace | 2010-11-19 21:35:06 +0000 | [diff] [blame] | 687 | IndexMode im, Format f, InstrItinClass itin, string opc, |
| 688 | string asm, string cstr, list<dag> pattern> |
| 689 | : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, |
| 690 | pattern> { |
| 691 | // AM2 store w/ two operands: (GPR, am2offset) |
Jim Grosbach | 6e9aace | 2010-11-19 21:35:06 +0000 | [diff] [blame] | 692 | // {12} isAdd |
| 693 | // {11-0} imm12/Rm |
Bruno Cardoso Lopes | c2452a6 | 2011-03-31 15:54:36 +0000 | [diff] [blame] | 694 | bits<14> offset; |
| 695 | bits<4> Rn; |
Owen Anderson | 2aedba6 | 2011-07-26 20:54:26 +0000 | [diff] [blame] | 696 | let Inst{25} = 1; |
| 697 | let Inst{23} = offset{12}; |
| 698 | let Inst{19-16} = Rn; |
| 699 | let Inst{11-5} = offset{11-5}; |
| 700 | let Inst{4} = 0; |
| 701 | let Inst{3-0} = offset{3-0}; |
| 702 | } |
| 703 | |
| 704 | class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops, |
| 705 | IndexMode im, Format f, InstrItinClass itin, string opc, |
| 706 | string asm, string cstr, list<dag> pattern> |
| 707 | : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, |
| 708 | pattern> { |
| 709 | // AM2 store w/ two operands: (GPR, am2offset) |
| 710 | // {12} isAdd |
| 711 | // {11-0} imm12/Rm |
| 712 | bits<14> offset; |
| 713 | bits<4> Rn; |
| 714 | let Inst{25} = 0; |
Bruno Cardoso Lopes | c2452a6 | 2011-03-31 15:54:36 +0000 | [diff] [blame] | 715 | let Inst{23} = offset{12}; |
| 716 | let Inst{19-16} = Rn; |
| 717 | let Inst{11-0} = offset{11-0}; |
Jim Grosbach | 6e9aace | 2010-11-19 21:35:06 +0000 | [diff] [blame] | 718 | } |
Owen Anderson | 2aedba6 | 2011-07-26 20:54:26 +0000 | [diff] [blame] | 719 | |
| 720 | |
Bruno Cardoso Lopes | ab83050 | 2011-03-31 23:26:08 +0000 | [diff] [blame] | 721 | // FIXME: Merge with the above class when addrmode2 gets used for STR, STRB |
| 722 | // but for now use this class for STRT and STRBT. |
| 723 | class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops, |
| 724 | IndexMode im, Format f, InstrItinClass itin, string opc, |
| 725 | string asm, string cstr, list<dag> pattern> |
| 726 | : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, |
| 727 | pattern> { |
| 728 | // AM2 store w/ two operands: (GPR, am2offset) |
| 729 | // {17-14} Rn |
| 730 | // {13} 1 == Rm, 0 == imm12 |
| 731 | // {12} isAdd |
| 732 | // {11-0} imm12/Rm |
| 733 | bits<18> addr; |
| 734 | let Inst{25} = addr{13}; |
| 735 | let Inst{23} = addr{12}; |
| 736 | let Inst{19-16} = addr{17-14}; |
| 737 | let Inst{11-0} = addr{11-0}; |
| 738 | } |
Jim Grosbach | 1e4d9a1 | 2010-10-26 22:37:02 +0000 | [diff] [blame] | 739 | |
Evan Cheng | 624844b | 2008-09-01 01:51:14 +0000 | [diff] [blame] | 740 | // addrmode3 instructions |
Jim Grosbach | 76aed40 | 2010-11-19 18:16:46 +0000 | [diff] [blame] | 741 | class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f, |
| 742 | InstrItinClass itin, string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 743 | : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin, |
Jim Grosbach | 8e7f8df | 2010-11-18 00:46:58 +0000 | [diff] [blame] | 744 | opc, asm, "", pattern> { |
| 745 | bits<14> addr; |
| 746 | bits<4> Rt; |
| 747 | let Inst{27-25} = 0b000; |
| 748 | let Inst{24} = 1; // P bit |
| 749 | let Inst{23} = addr{8}; // U bit |
| 750 | let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm |
| 751 | let Inst{21} = 0; // W bit |
Jim Grosbach | 76aed40 | 2010-11-19 18:16:46 +0000 | [diff] [blame] | 752 | let Inst{20} = op20; // L bit |
Jim Grosbach | 8e7f8df | 2010-11-18 00:46:58 +0000 | [diff] [blame] | 753 | let Inst{19-16} = addr{12-9}; // Rn |
| 754 | let Inst{15-12} = Rt; // Rt |
| 755 | let Inst{11-8} = addr{7-4}; // imm7_4/zero |
| 756 | let Inst{7-4} = op; |
| 757 | let Inst{3-0} = addr{3-0}; // imm3_0/Rm |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 758 | |
| 759 | let DecoderMethod = "DecodeAddrMode3Instruction"; |
Jim Grosbach | 8e7f8df | 2010-11-18 00:46:58 +0000 | [diff] [blame] | 760 | } |
Evan Cheng | 169eccc | 2008-09-01 07:00:14 +0000 | [diff] [blame] | 761 | |
Jim Grosbach | 2ea19d1 | 2011-08-11 20:41:13 +0000 | [diff] [blame] | 762 | class AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops, |
Jim Grosbach | 003c6e7 | 2010-11-19 19:41:26 +0000 | [diff] [blame] | 763 | IndexMode im, Format f, InstrItinClass itin, string opc, |
| 764 | string asm, string cstr, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 765 | : I<oops, iops, AddrMode3, 4, im, f, itin, |
Jim Grosbach | 003c6e7 | 2010-11-19 19:41:26 +0000 | [diff] [blame] | 766 | opc, asm, cstr, pattern> { |
| 767 | bits<4> Rt; |
| 768 | let Inst{27-25} = 0b000; |
| 769 | let Inst{24} = isPre; // P bit |
| 770 | let Inst{21} = isPre; // W bit |
| 771 | let Inst{20} = op20; // L bit |
| 772 | let Inst{15-12} = Rt; // Rt |
| 773 | let Inst{7-4} = op; |
| 774 | } |
Bruno Cardoso Lopes | bda3632 | 2011-04-04 17:18:19 +0000 | [diff] [blame] | 775 | |
| 776 | // FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB |
| 777 | // but for now use this class for LDRSBT, LDRHT, LDSHT. |
Jim Grosbach | d359571 | 2011-08-03 23:50:40 +0000 | [diff] [blame] | 778 | class AI3ldstidxT<bits<4> op, bit isLoad, dag oops, dag iops, |
Bruno Cardoso Lopes | bda3632 | 2011-04-04 17:18:19 +0000 | [diff] [blame] | 779 | IndexMode im, Format f, InstrItinClass itin, string opc, |
| 780 | string asm, string cstr, list<dag> pattern> |
Jim Grosbach | d359571 | 2011-08-03 23:50:40 +0000 | [diff] [blame] | 781 | : I<oops, iops, AddrMode3, 4, im, f, itin, opc, asm, cstr, pattern> { |
Bruno Cardoso Lopes | bda3632 | 2011-04-04 17:18:19 +0000 | [diff] [blame] | 782 | // {13} 1 == imm8, 0 == Rm |
| 783 | // {12-9} Rn |
| 784 | // {8} isAdd |
| 785 | // {7-4} imm7_4/zero |
| 786 | // {3-0} imm3_0/Rm |
Jim Grosbach | d359571 | 2011-08-03 23:50:40 +0000 | [diff] [blame] | 787 | bits<4> addr; |
Bruno Cardoso Lopes | bda3632 | 2011-04-04 17:18:19 +0000 | [diff] [blame] | 788 | bits<4> Rt; |
| 789 | let Inst{27-25} = 0b000; |
Jim Grosbach | d359571 | 2011-08-03 23:50:40 +0000 | [diff] [blame] | 790 | let Inst{24} = 0; // P bit |
| 791 | let Inst{21} = 1; |
| 792 | let Inst{20} = isLoad; // L bit |
| 793 | let Inst{19-16} = addr; // Rn |
Bruno Cardoso Lopes | bda3632 | 2011-04-04 17:18:19 +0000 | [diff] [blame] | 794 | let Inst{15-12} = Rt; // Rt |
Bruno Cardoso Lopes | bda3632 | 2011-04-04 17:18:19 +0000 | [diff] [blame] | 795 | let Inst{7-4} = op; |
Bruno Cardoso Lopes | bda3632 | 2011-04-04 17:18:19 +0000 | [diff] [blame] | 796 | } |
| 797 | |
Evan Cheng | 169eccc | 2008-09-01 07:00:14 +0000 | [diff] [blame] | 798 | // stores |
Jim Grosbach | 09d7bfd | 2010-11-19 22:14:31 +0000 | [diff] [blame] | 799 | class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 800 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 801 | : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 802 | opc, asm, "", pattern> { |
Jim Grosbach | 607efcb | 2010-11-11 01:09:40 +0000 | [diff] [blame] | 803 | bits<14> addr; |
| 804 | bits<4> Rt; |
Evan Cheng | 5edd90c | 2009-07-08 22:51:32 +0000 | [diff] [blame] | 805 | let Inst{27-25} = 0b000; |
Jim Grosbach | 607efcb | 2010-11-11 01:09:40 +0000 | [diff] [blame] | 806 | let Inst{24} = 1; // P bit |
| 807 | let Inst{23} = addr{8}; // U bit |
| 808 | let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm |
| 809 | let Inst{21} = 0; // W bit |
| 810 | let Inst{20} = 0; // L bit |
| 811 | let Inst{19-16} = addr{12-9}; // Rn |
| 812 | let Inst{15-12} = Rt; // Rt |
| 813 | let Inst{11-8} = addr{7-4}; // imm7_4/zero |
Jim Grosbach | 09d7bfd | 2010-11-19 22:14:31 +0000 | [diff] [blame] | 814 | let Inst{7-4} = op; |
Jim Grosbach | 607efcb | 2010-11-11 01:09:40 +0000 | [diff] [blame] | 815 | let Inst{3-0} = addr{3-0}; // imm3_0/Rm |
Owen Anderson | 60138ea | 2011-08-12 20:02:50 +0000 | [diff] [blame] | 816 | let DecoderMethod = "DecodeAddrMode3Instruction"; |
Evan Cheng | 169eccc | 2008-09-01 07:00:14 +0000 | [diff] [blame] | 817 | } |
Evan Cheng | 169eccc | 2008-09-01 07:00:14 +0000 | [diff] [blame] | 818 | |
Evan Cheng | 624844b | 2008-09-01 01:51:14 +0000 | [diff] [blame] | 819 | // addrmode4 instructions |
Bill Wendling | e69afc6 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 820 | class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, |
| 821 | string asm, string cstr, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 822 | : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> { |
Bill Wendling | e69afc6 | 2010-11-13 09:09:38 +0000 | [diff] [blame] | 823 | bits<4> p; |
| 824 | bits<16> regs; |
| 825 | bits<4> Rn; |
| 826 | let Inst{31-28} = p; |
| 827 | let Inst{27-25} = 0b100; |
| 828 | let Inst{22} = 0; // S bit |
| 829 | let Inst{19-16} = Rn; |
| 830 | let Inst{15-0} = regs; |
| 831 | } |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 832 | |
Jim Grosbach | 4d0549e | 2008-11-03 18:38:31 +0000 | [diff] [blame] | 833 | // Unsigned multiply, multiply-accumulate instructions. |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 834 | class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, |
| 835 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 836 | : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 837 | opc, asm, "", pattern> { |
Jim Grosbach | 4d0549e | 2008-11-03 18:38:31 +0000 | [diff] [blame] | 838 | let Inst{7-4} = 0b1001; |
Evan Cheng | 2686c8f | 2008-11-06 01:21:28 +0000 | [diff] [blame] | 839 | let Inst{20} = 0; // S bit |
Evan Cheng | 47b546d | 2008-11-06 08:47:38 +0000 | [diff] [blame] | 840 | let Inst{27-21} = opcod; |
Jim Grosbach | 4d0549e | 2008-11-03 18:38:31 +0000 | [diff] [blame] | 841 | } |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 842 | class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, |
| 843 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 844 | : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 845 | opc, asm, "", pattern> { |
Jim Grosbach | 4d0549e | 2008-11-03 18:38:31 +0000 | [diff] [blame] | 846 | let Inst{7-4} = 0b1001; |
Evan Cheng | 47b546d | 2008-11-06 08:47:38 +0000 | [diff] [blame] | 847 | let Inst{27-21} = opcod; |
Evan Cheng | 2686c8f | 2008-11-06 01:21:28 +0000 | [diff] [blame] | 848 | } |
| 849 | |
| 850 | // Most significant word multiply |
Jim Grosbach | 2226160 | 2010-10-22 17:16:17 +0000 | [diff] [blame] | 851 | class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, |
| 852 | InstrItinClass itin, string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 853 | : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 854 | opc, asm, "", pattern> { |
Jim Grosbach | 2226160 | 2010-10-22 17:16:17 +0000 | [diff] [blame] | 855 | bits<4> Rd; |
| 856 | bits<4> Rn; |
| 857 | bits<4> Rm; |
| 858 | let Inst{7-4} = opc7_4; |
Evan Cheng | 2686c8f | 2008-11-06 01:21:28 +0000 | [diff] [blame] | 859 | let Inst{20} = 1; |
Evan Cheng | 47b546d | 2008-11-06 08:47:38 +0000 | [diff] [blame] | 860 | let Inst{27-21} = opcod; |
Jim Grosbach | 2226160 | 2010-10-22 17:16:17 +0000 | [diff] [blame] | 861 | let Inst{19-16} = Rd; |
| 862 | let Inst{11-8} = Rm; |
| 863 | let Inst{3-0} = Rn; |
| 864 | } |
| 865 | // MSW multiple w/ Ra operand |
| 866 | class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, |
| 867 | InstrItinClass itin, string opc, string asm, list<dag> pattern> |
| 868 | : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> { |
| 869 | bits<4> Ra; |
| 870 | let Inst{15-12} = Ra; |
Jim Grosbach | 4d0549e | 2008-11-03 18:38:31 +0000 | [diff] [blame] | 871 | } |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 872 | |
Evan Cheng | 36ae403 | 2008-11-06 03:35:07 +0000 | [diff] [blame] | 873 | // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> |
Jim Grosbach | 6956a60 | 2010-10-22 18:35:16 +0000 | [diff] [blame] | 874 | class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, |
Jim Grosbach | f98df08 | 2010-10-22 17:42:06 +0000 | [diff] [blame] | 875 | InstrItinClass itin, string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 876 | : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 877 | opc, asm, "", pattern> { |
Jim Grosbach | 6956a60 | 2010-10-22 18:35:16 +0000 | [diff] [blame] | 878 | bits<4> Rn; |
| 879 | bits<4> Rm; |
Evan Cheng | 36ae403 | 2008-11-06 03:35:07 +0000 | [diff] [blame] | 880 | let Inst{4} = 0; |
| 881 | let Inst{7} = 1; |
| 882 | let Inst{20} = 0; |
Evan Cheng | 47b546d | 2008-11-06 08:47:38 +0000 | [diff] [blame] | 883 | let Inst{27-21} = opcod; |
Jim Grosbach | f98df08 | 2010-10-22 17:42:06 +0000 | [diff] [blame] | 884 | let Inst{6-5} = bit6_5; |
Jim Grosbach | 6956a60 | 2010-10-22 18:35:16 +0000 | [diff] [blame] | 885 | let Inst{11-8} = Rm; |
| 886 | let Inst{3-0} = Rn; |
| 887 | } |
| 888 | class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, |
| 889 | InstrItinClass itin, string opc, string asm, list<dag> pattern> |
| 890 | : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { |
| 891 | bits<4> Rd; |
| 892 | let Inst{19-16} = Rd; |
| 893 | } |
| 894 | |
| 895 | // AMulxyI with Ra operand |
| 896 | class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, |
| 897 | InstrItinClass itin, string opc, string asm, list<dag> pattern> |
| 898 | : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { |
| 899 | bits<4> Ra; |
| 900 | let Inst{15-12} = Ra; |
| 901 | } |
| 902 | // SMLAL* |
| 903 | class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, |
| 904 | InstrItinClass itin, string opc, string asm, list<dag> pattern> |
| 905 | : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { |
| 906 | bits<4> RdLo; |
| 907 | bits<4> RdHi; |
| 908 | let Inst{19-16} = RdHi; |
| 909 | let Inst{15-12} = RdLo; |
Evan Cheng | 36ae403 | 2008-11-06 03:35:07 +0000 | [diff] [blame] | 910 | } |
| 911 | |
Evan Cheng | 49d6652 | 2008-11-06 22:15:19 +0000 | [diff] [blame] | 912 | // Extend instructions. |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 913 | class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, |
| 914 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 915 | : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 916 | opc, asm, "", pattern> { |
Jim Grosbach | 1e7db68 | 2010-10-13 19:56:10 +0000 | [diff] [blame] | 917 | // All AExtI instructions have Rd and Rm register operands. |
| 918 | bits<4> Rd; |
| 919 | bits<4> Rm; |
| 920 | let Inst{15-12} = Rd; |
| 921 | let Inst{3-0} = Rm; |
Evan Cheng | 49d6652 | 2008-11-06 22:15:19 +0000 | [diff] [blame] | 922 | let Inst{7-4} = 0b0111; |
Jim Grosbach | 1e7db68 | 2010-10-13 19:56:10 +0000 | [diff] [blame] | 923 | let Inst{9-8} = 0b00; |
Evan Cheng | 49d6652 | 2008-11-06 22:15:19 +0000 | [diff] [blame] | 924 | let Inst{27-20} = opcod; |
Silviu Baranga | ddc67a7 | 2012-05-11 09:28:27 +0000 | [diff] [blame] | 925 | |
| 926 | let Unpredictable{9-8} = 0b11; |
Evan Cheng | 49d6652 | 2008-11-06 22:15:19 +0000 | [diff] [blame] | 927 | } |
| 928 | |
Evan Cheng | 98dc53e | 2008-11-07 01:41:35 +0000 | [diff] [blame] | 929 | // Misc Arithmetic instructions. |
Jim Grosbach | 2c9ae05 | 2010-10-22 22:12:16 +0000 | [diff] [blame] | 930 | class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops, |
| 931 | InstrItinClass itin, string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 932 | : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 933 | opc, asm, "", pattern> { |
Jim Grosbach | 2c9ae05 | 2010-10-22 22:12:16 +0000 | [diff] [blame] | 934 | bits<4> Rd; |
| 935 | bits<4> Rm; |
Evan Cheng | 98dc53e | 2008-11-07 01:41:35 +0000 | [diff] [blame] | 936 | let Inst{27-20} = opcod; |
Jim Grosbach | 2c9ae05 | 2010-10-22 22:12:16 +0000 | [diff] [blame] | 937 | let Inst{19-16} = 0b1111; |
| 938 | let Inst{15-12} = Rd; |
| 939 | let Inst{11-8} = 0b1111; |
| 940 | let Inst{7-4} = opc7_4; |
| 941 | let Inst{3-0} = Rm; |
| 942 | } |
| 943 | |
Bob Wilson | e8a549c | 2012-09-29 21:43:49 +0000 | [diff] [blame] | 944 | // Division instructions. |
| 945 | class ADivA1I<bits<3> opcod, dag oops, dag iops, |
| 946 | InstrItinClass itin, string opc, string asm, list<dag> pattern> |
| 947 | : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, |
| 948 | opc, asm, "", pattern> { |
| 949 | bits<4> Rd; |
| 950 | bits<4> Rn; |
| 951 | bits<4> Rm; |
| 952 | let Inst{27-23} = 0b01110; |
| 953 | let Inst{22-20} = opcod; |
| 954 | let Inst{19-16} = Rd; |
| 955 | let Inst{15-12} = 0b1111; |
| 956 | let Inst{11-8} = Rm; |
| 957 | let Inst{7-4} = 0b0001; |
| 958 | let Inst{3-0} = Rn; |
| 959 | } |
| 960 | |
Jim Grosbach | 2c9ae05 | 2010-10-22 22:12:16 +0000 | [diff] [blame] | 961 | // PKH instructions |
Sjoerd Meijer | 1179470 | 2017-04-03 14:50:04 +0000 | [diff] [blame] | 962 | def PKHLSLAsmOperand : ImmAsmOperand<0,31> { |
Jim Grosbach | 27c1e25 | 2011-07-21 17:23:04 +0000 | [diff] [blame] | 963 | let Name = "PKHLSLImm"; |
| 964 | let ParserMethod = "parsePKHLSLImm"; |
| 965 | } |
Jim Grosbach | a288b1c | 2011-07-20 21:40:26 +0000 | [diff] [blame] | 966 | def pkh_lsl_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>{ |
| 967 | let PrintMethod = "printPKHLSLShiftImm"; |
Jim Grosbach | 27c1e25 | 2011-07-21 17:23:04 +0000 | [diff] [blame] | 968 | let ParserMatchClass = PKHLSLAsmOperand; |
| 969 | } |
| 970 | def PKHASRAsmOperand : AsmOperandClass { |
| 971 | let Name = "PKHASRImm"; |
| 972 | let ParserMethod = "parsePKHASRImm"; |
Jim Grosbach | a288b1c | 2011-07-20 21:40:26 +0000 | [diff] [blame] | 973 | } |
| 974 | def pkh_asr_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>{ |
| 975 | let PrintMethod = "printPKHASRShiftImm"; |
Jim Grosbach | 27c1e25 | 2011-07-21 17:23:04 +0000 | [diff] [blame] | 976 | let ParserMatchClass = PKHASRAsmOperand; |
Jim Grosbach | a288b1c | 2011-07-20 21:40:26 +0000 | [diff] [blame] | 977 | } |
Jim Grosbach | 94df3be | 2011-07-20 20:49:03 +0000 | [diff] [blame] | 978 | |
Jim Grosbach | 2c9ae05 | 2010-10-22 22:12:16 +0000 | [diff] [blame] | 979 | class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin, |
| 980 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 981 | : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, |
Jim Grosbach | 2c9ae05 | 2010-10-22 22:12:16 +0000 | [diff] [blame] | 982 | opc, asm, "", pattern> { |
| 983 | bits<4> Rd; |
| 984 | bits<4> Rn; |
| 985 | bits<4> Rm; |
Jim Grosbach | a98f800 | 2011-07-20 20:32:09 +0000 | [diff] [blame] | 986 | bits<5> sh; |
Jim Grosbach | 2c9ae05 | 2010-10-22 22:12:16 +0000 | [diff] [blame] | 987 | let Inst{27-20} = opcod; |
| 988 | let Inst{19-16} = Rn; |
| 989 | let Inst{15-12} = Rd; |
Jim Grosbach | a98f800 | 2011-07-20 20:32:09 +0000 | [diff] [blame] | 990 | let Inst{11-7} = sh; |
Jim Grosbach | 2c9ae05 | 2010-10-22 22:12:16 +0000 | [diff] [blame] | 991 | let Inst{6} = tb; |
| 992 | let Inst{5-4} = 0b01; |
| 993 | let Inst{3-0} = Rm; |
Evan Cheng | 98dc53e | 2008-11-07 01:41:35 +0000 | [diff] [blame] | 994 | } |
| 995 | |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 996 | //===----------------------------------------------------------------------===// |
| 997 | |
| 998 | // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. |
| 999 | class ARMPat<dag pattern, dag result> : Pat<pattern, result> { |
| 1000 | list<Predicate> Predicates = [IsARM]; |
| 1001 | } |
Bruno Cardoso Lopes | 168c900 | 2011-05-03 17:29:22 +0000 | [diff] [blame] | 1002 | class ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> { |
| 1003 | list<Predicate> Predicates = [IsARM, HasV5T]; |
| 1004 | } |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 1005 | class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { |
| 1006 | list<Predicate> Predicates = [IsARM, HasV5TE]; |
| 1007 | } |
Bob Wilson | e8a549c | 2012-09-29 21:43:49 +0000 | [diff] [blame] | 1008 | // ARMV5MOPat - Same as ARMV5TEPat with UseMulOps. |
| 1009 | class ARMV5MOPat<dag pattern, dag result> : Pat<pattern, result> { |
| 1010 | list<Predicate> Predicates = [IsARM, HasV5TE, UseMulOps]; |
| 1011 | } |
Evan Cheng | 2d37f19 | 2008-08-28 23:39:26 +0000 | [diff] [blame] | 1012 | class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { |
| 1013 | list<Predicate> Predicates = [IsARM, HasV6]; |
| 1014 | } |
James Molloy | fa04115 | 2015-03-23 16:15:16 +0000 | [diff] [blame] | 1015 | class VFPPat<dag pattern, dag result> : Pat<pattern, result> { |
| 1016 | list<Predicate> Predicates = [HasVFP2]; |
| 1017 | } |
| 1018 | class VFPNoNEONPat<dag pattern, dag result> : Pat<pattern, result> { |
| 1019 | list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP]; |
| 1020 | } |
Sam Parker | 18bc3a0 | 2016-08-02 12:44:27 +0000 | [diff] [blame] | 1021 | class Thumb2DSPPat<dag pattern, dag result> : Pat<pattern, result> { |
| 1022 | list<Predicate> Predicates = [IsThumb2, HasDSP]; |
| 1023 | } |
| 1024 | class Thumb2DSPMulPat<dag pattern, dag result> : Pat<pattern, result> { |
| 1025 | list<Predicate> Predicates = [IsThumb2, UseMulOps, HasDSP]; |
| 1026 | } |
Sjoerd Meijer | 3ddb7fb | 2018-01-29 11:28:06 +0000 | [diff] [blame] | 1027 | class FP16Pat<dag pattern, dag result> : Pat<pattern, result> { |
| 1028 | list<Predicate> Predicates = [HasFP16]; |
| 1029 | } |
| 1030 | class FullFP16Pat<dag pattern, dag result> : Pat<pattern, result> { |
| 1031 | list<Predicate> Predicates = [HasFullFP16]; |
| 1032 | } |
Evan Cheng | ee98fa9 | 2008-08-29 06:41:12 +0000 | [diff] [blame] | 1033 | //===----------------------------------------------------------------------===// |
Evan Cheng | ee98fa9 | 2008-08-29 06:41:12 +0000 | [diff] [blame] | 1034 | // Thumb Instruction Format Definitions. |
| 1035 | // |
| 1036 | |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1037 | class ThumbI<dag oops, dag iops, AddrMode am, int sz, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1038 | InstrItinClass itin, string asm, string cstr, list<dag> pattern> |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1039 | : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 1040 | let OutOperandList = oops; |
| 1041 | let InOperandList = iops; |
Bob Wilson | 722bff2 | 2010-05-24 20:08:34 +0000 | [diff] [blame] | 1042 | let AsmString = asm; |
Evan Cheng | ee98fa9 | 2008-08-29 06:41:12 +0000 | [diff] [blame] | 1043 | let Pattern = pattern; |
| 1044 | list<Predicate> Predicates = [IsThumb]; |
| 1045 | } |
| 1046 | |
Bill Wendling | cbb08ca | 2010-12-01 02:42:55 +0000 | [diff] [blame] | 1047 | // TI - Thumb instruction. |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1048 | class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1049 | : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>; |
Evan Cheng | ee98fa9 | 2008-08-29 06:41:12 +0000 | [diff] [blame] | 1050 | |
Evan Cheng | 7cc6aca | 2009-08-04 23:47:55 +0000 | [diff] [blame] | 1051 | // Two-address instructions |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 1052 | class TIt<dag oops, dag iops, InstrItinClass itin, string asm, |
| 1053 | list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1054 | : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst", |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 1055 | pattern>; |
Evan Cheng | 7cc6aca | 2009-08-04 23:47:55 +0000 | [diff] [blame] | 1056 | |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1057 | // tBL, tBX 32-bit instructions |
| 1058 | class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3, |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 1059 | dag oops, dag iops, InstrItinClass itin, string asm, |
| 1060 | list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1061 | : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>, |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 1062 | Encoding { |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1063 | let Inst{31-27} = opcod1; |
| 1064 | let Inst{15-14} = opcod2; |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 1065 | let Inst{12} = opcod3; |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1066 | } |
Evan Cheng | ee98fa9 | 2008-08-29 06:41:12 +0000 | [diff] [blame] | 1067 | |
| 1068 | // BR_JT instructions |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 1069 | class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, |
| 1070 | list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1071 | : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>; |
Evan Cheng | ee98fa9 | 2008-08-29 06:41:12 +0000 | [diff] [blame] | 1072 | |
Evan Cheng | bec1dba89 | 2009-06-23 19:38:13 +0000 | [diff] [blame] | 1073 | // Thumb1 only |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1074 | class Thumb1I<dag oops, dag iops, AddrMode am, int sz, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1075 | InstrItinClass itin, string asm, string cstr, list<dag> pattern> |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1076 | : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 1077 | let OutOperandList = oops; |
| 1078 | let InOperandList = iops; |
Bob Wilson | 722bff2 | 2010-05-24 20:08:34 +0000 | [diff] [blame] | 1079 | let AsmString = asm; |
Evan Cheng | bec1dba89 | 2009-06-23 19:38:13 +0000 | [diff] [blame] | 1080 | let Pattern = pattern; |
Jim Grosbach | fddf36d | 2010-11-01 17:08:58 +0000 | [diff] [blame] | 1081 | list<Predicate> Predicates = [IsThumb, IsThumb1Only]; |
Evan Cheng | bec1dba89 | 2009-06-23 19:38:13 +0000 | [diff] [blame] | 1082 | } |
| 1083 | |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1084 | class T1I<dag oops, dag iops, InstrItinClass itin, |
| 1085 | string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1086 | : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>; |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1087 | class T1Ix2<dag oops, dag iops, InstrItinClass itin, |
| 1088 | string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1089 | : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>; |
Evan Cheng | bec1dba89 | 2009-06-23 19:38:13 +0000 | [diff] [blame] | 1090 | |
| 1091 | // Two-address instructions |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1092 | class T1It<dag oops, dag iops, InstrItinClass itin, |
Bob Wilson | 947f04b | 2010-03-13 01:08:20 +0000 | [diff] [blame] | 1093 | string asm, string cstr, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1094 | : Thumb1I<oops, iops, AddrModeNone, 2, itin, |
Bob Wilson | 947f04b | 2010-03-13 01:08:20 +0000 | [diff] [blame] | 1095 | asm, cstr, pattern>; |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 1096 | |
| 1097 | // Thumb1 instruction that can either be predicated or set CPSR. |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1098 | class Thumb1sI<dag oops, dag iops, AddrMode am, int sz, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1099 | InstrItinClass itin, |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 1100 | string opc, string asm, string cstr, list<dag> pattern> |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1101 | : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { |
Chris Lattner | fb2ceed | 2010-03-18 21:06:54 +0000 | [diff] [blame] | 1102 | let OutOperandList = !con(oops, (outs s_cc_out:$s)); |
| 1103 | let InOperandList = !con(iops, (ins pred:$p)); |
Chris Lattner | 04c342e | 2010-10-06 00:05:18 +0000 | [diff] [blame] | 1104 | let AsmString = !strconcat(opc, "${s}${p}", asm); |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 1105 | let Pattern = pattern; |
Jim Grosbach | 3e941ae | 2011-08-16 20:45:50 +0000 | [diff] [blame] | 1106 | let thumbArithFlagSetting = 1; |
Jim Grosbach | fddf36d | 2010-11-01 17:08:58 +0000 | [diff] [blame] | 1107 | list<Predicate> Predicates = [IsThumb, IsThumb1Only]; |
Owen Anderson | 91a8f9b | 2011-08-16 23:45:44 +0000 | [diff] [blame] | 1108 | let DecoderNamespace = "ThumbSBit"; |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 1109 | } |
| 1110 | |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1111 | class T1sI<dag oops, dag iops, InstrItinClass itin, |
| 1112 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1113 | : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>; |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 1114 | |
| 1115 | // Two-address instructions |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1116 | class T1sIt<dag oops, dag iops, InstrItinClass itin, |
| 1117 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1118 | : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, |
Bill Wendling | 05632cb | 2010-11-30 23:54:45 +0000 | [diff] [blame] | 1119 | "$Rn = $Rdn", pattern>; |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 1120 | |
| 1121 | // Thumb1 instruction that can be predicated. |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1122 | class Thumb1pI<dag oops, dag iops, AddrMode am, int sz, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1123 | InstrItinClass itin, |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 1124 | string opc, string asm, string cstr, list<dag> pattern> |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1125 | : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 1126 | let OutOperandList = oops; |
Chris Lattner | fb2ceed | 2010-03-18 21:06:54 +0000 | [diff] [blame] | 1127 | let InOperandList = !con(iops, (ins pred:$p)); |
Chris Lattner | 04c342e | 2010-10-06 00:05:18 +0000 | [diff] [blame] | 1128 | let AsmString = !strconcat(opc, "${p}", asm); |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 1129 | let Pattern = pattern; |
Jim Grosbach | fddf36d | 2010-11-01 17:08:58 +0000 | [diff] [blame] | 1130 | list<Predicate> Predicates = [IsThumb, IsThumb1Only]; |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 1131 | } |
| 1132 | |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1133 | class T1pI<dag oops, dag iops, InstrItinClass itin, |
| 1134 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1135 | : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>; |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 1136 | |
| 1137 | // Two-address instructions |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1138 | class T1pIt<dag oops, dag iops, InstrItinClass itin, |
| 1139 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1140 | : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, |
Bill Wendling | 7c646b9 | 2010-12-01 01:32:02 +0000 | [diff] [blame] | 1141 | "$Rn = $Rdn", pattern>; |
Evan Cheng | cd4cdd1 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 1142 | |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 1143 | class T1pIs<dag oops, dag iops, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1144 | InstrItinClass itin, string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1145 | : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>; |
Evan Cheng | bec1dba89 | 2009-06-23 19:38:13 +0000 | [diff] [blame] | 1146 | |
Johnny Chen | 466231a | 2009-12-16 02:32:54 +0000 | [diff] [blame] | 1147 | class Encoding16 : Encoding { |
| 1148 | let Inst{31-16} = 0x0000; |
| 1149 | } |
| 1150 | |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1151 | // A6.2 16-bit Thumb instruction encoding |
Johnny Chen | 466231a | 2009-12-16 02:32:54 +0000 | [diff] [blame] | 1152 | class T1Encoding<bits<6> opcode> : Encoding16 { |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1153 | let Inst{15-10} = opcode; |
| 1154 | } |
| 1155 | |
| 1156 | // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. |
Johnny Chen | 466231a | 2009-12-16 02:32:54 +0000 | [diff] [blame] | 1157 | class T1General<bits<5> opcode> : Encoding16 { |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1158 | let Inst{15-14} = 0b00; |
| 1159 | let Inst{13-9} = opcode; |
| 1160 | } |
| 1161 | |
| 1162 | // A6.2.2 Data-processing encoding. |
Johnny Chen | 466231a | 2009-12-16 02:32:54 +0000 | [diff] [blame] | 1163 | class T1DataProcessing<bits<4> opcode> : Encoding16 { |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1164 | let Inst{15-10} = 0b010000; |
| 1165 | let Inst{9-6} = opcode; |
| 1166 | } |
| 1167 | |
| 1168 | // A6.2.3 Special data instructions and branch and exchange encoding. |
Johnny Chen | 466231a | 2009-12-16 02:32:54 +0000 | [diff] [blame] | 1169 | class T1Special<bits<4> opcode> : Encoding16 { |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1170 | let Inst{15-10} = 0b010001; |
Bill Wendling | 345b48f | 2010-11-17 00:45:23 +0000 | [diff] [blame] | 1171 | let Inst{9-6} = opcode; |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1172 | } |
| 1173 | |
| 1174 | // A6.2.4 Load/store single data item encoding. |
Johnny Chen | 466231a | 2009-12-16 02:32:54 +0000 | [diff] [blame] | 1175 | class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1176 | let Inst{15-12} = opA; |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 1177 | let Inst{11-9} = opB; |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1178 | } |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 1179 | class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1180 | |
Eric Christopher | 9b67db8 | 2011-05-27 03:50:53 +0000 | [diff] [blame] | 1181 | class T1BranchCond<bits<4> opcode> : Encoding16 { |
| 1182 | let Inst{15-12} = opcode; |
| 1183 | } |
| 1184 | |
Bill Wendling | a9e3df7 | 2010-11-30 22:57:21 +0000 | [diff] [blame] | 1185 | // Helper classes to encode Thumb1 loads and stores. For immediates, the |
Bill Wendling | 05632cb | 2010-11-30 23:54:45 +0000 | [diff] [blame] | 1186 | // following bits are used for "opA" (see A6.2.4): |
Jim Grosbach | c4669ed | 2010-12-10 20:47:29 +0000 | [diff] [blame] | 1187 | // |
Bill Wendling | a9e3df7 | 2010-11-30 22:57:21 +0000 | [diff] [blame] | 1188 | // 0b0110 => Immediate, 4 bytes |
| 1189 | // 0b1000 => Immediate, 2 bytes |
| 1190 | // 0b0111 => Immediate, 1 byte |
Bill Wendling | c25545a | 2010-12-01 01:38:08 +0000 | [diff] [blame] | 1191 | class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am, |
| 1192 | InstrItinClass itin, string opc, string asm, |
| 1193 | list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1194 | : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>, |
Bill Wendling | 5c51fcd | 2010-11-30 23:16:25 +0000 | [diff] [blame] | 1195 | T1LoadStore<0b0101, opcode> { |
Bill Wendling | a9e3df7 | 2010-11-30 22:57:21 +0000 | [diff] [blame] | 1196 | bits<3> Rt; |
| 1197 | bits<8> addr; |
| 1198 | let Inst{8-6} = addr{5-3}; // Rm |
| 1199 | let Inst{5-3} = addr{2-0}; // Rn |
| 1200 | let Inst{2-0} = Rt; |
| 1201 | } |
Bill Wendling | c25545a | 2010-12-01 01:38:08 +0000 | [diff] [blame] | 1202 | class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am, |
| 1203 | InstrItinClass itin, string opc, string asm, |
| 1204 | list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1205 | : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>, |
Bill Wendling | 5c51fcd | 2010-11-30 23:16:25 +0000 | [diff] [blame] | 1206 | T1LoadStore<opA, {opB,?,?}> { |
Bill Wendling | a9e3df7 | 2010-11-30 22:57:21 +0000 | [diff] [blame] | 1207 | bits<3> Rt; |
| 1208 | bits<8> addr; |
| 1209 | let Inst{10-6} = addr{7-3}; // imm5 |
| 1210 | let Inst{5-3} = addr{2-0}; // Rn |
| 1211 | let Inst{2-0} = Rt; |
| 1212 | } |
| 1213 | |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1214 | // A6.2.5 Miscellaneous 16-bit instructions encoding. |
Johnny Chen | 466231a | 2009-12-16 02:32:54 +0000 | [diff] [blame] | 1215 | class T1Misc<bits<7> opcode> : Encoding16 { |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1216 | let Inst{15-12} = 0b1011; |
| 1217 | let Inst{11-5} = opcode; |
| 1218 | } |
| 1219 | |
Evan Cheng | d76f0be | 2009-06-25 02:08:06 +0000 | [diff] [blame] | 1220 | // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1221 | class Thumb2I<dag oops, dag iops, AddrMode am, int sz, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1222 | InstrItinClass itin, |
Evan Cheng | d76f0be | 2009-06-25 02:08:06 +0000 | [diff] [blame] | 1223 | string opc, string asm, string cstr, list<dag> pattern> |
Anton Korobeynikov | 14635da | 2009-11-02 00:10:38 +0000 | [diff] [blame] | 1224 | : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { |
Evan Cheng | d76f0be | 2009-06-25 02:08:06 +0000 | [diff] [blame] | 1225 | let OutOperandList = oops; |
Chris Lattner | fb2ceed | 2010-03-18 21:06:54 +0000 | [diff] [blame] | 1226 | let InOperandList = !con(iops, (ins pred:$p)); |
Chris Lattner | 04c342e | 2010-10-06 00:05:18 +0000 | [diff] [blame] | 1227 | let AsmString = !strconcat(opc, "${p}", asm); |
Evan Cheng | d76f0be | 2009-06-25 02:08:06 +0000 | [diff] [blame] | 1228 | let Pattern = pattern; |
Evan Cheng | 2c450d3 | 2009-07-02 06:38:40 +0000 | [diff] [blame] | 1229 | list<Predicate> Predicates = [IsThumb2]; |
Owen Anderson | c78e03c | 2011-07-19 21:06:00 +0000 | [diff] [blame] | 1230 | let DecoderNamespace = "Thumb2"; |
Evan Cheng | d76f0be | 2009-06-25 02:08:06 +0000 | [diff] [blame] | 1231 | } |
| 1232 | |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 1233 | // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an |
| 1234 | // input operand since by default it's a zero register. It will become an |
| 1235 | // implicit def once it's "flipped". |
Jim Grosbach | b938655 | 2010-10-13 23:12:26 +0000 | [diff] [blame] | 1236 | // |
Evan Cheng | d76f0be | 2009-06-25 02:08:06 +0000 | [diff] [blame] | 1237 | // FIXME: This uses unified syntax so {s} comes before {p}. We should make it |
| 1238 | // more consistent. |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1239 | class Thumb2sI<dag oops, dag iops, AddrMode am, int sz, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1240 | InstrItinClass itin, |
Evan Cheng | d76f0be | 2009-06-25 02:08:06 +0000 | [diff] [blame] | 1241 | string opc, string asm, string cstr, list<dag> pattern> |
Anton Korobeynikov | 14635da | 2009-11-02 00:10:38 +0000 | [diff] [blame] | 1242 | : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { |
Owen Anderson | cf096a4 | 2010-12-07 20:50:15 +0000 | [diff] [blame] | 1243 | bits<1> s; // condition-code set flag ('1' if the insn should set the flags) |
| 1244 | let Inst{20} = s; |
| 1245 | |
Evan Cheng | d76f0be | 2009-06-25 02:08:06 +0000 | [diff] [blame] | 1246 | let OutOperandList = oops; |
Chris Lattner | fb2ceed | 2010-03-18 21:06:54 +0000 | [diff] [blame] | 1247 | let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); |
Chris Lattner | 04c342e | 2010-10-06 00:05:18 +0000 | [diff] [blame] | 1248 | let AsmString = !strconcat(opc, "${s}${p}", asm); |
Evan Cheng | d76f0be | 2009-06-25 02:08:06 +0000 | [diff] [blame] | 1249 | let Pattern = pattern; |
Evan Cheng | 2c450d3 | 2009-07-02 06:38:40 +0000 | [diff] [blame] | 1250 | list<Predicate> Predicates = [IsThumb2]; |
Owen Anderson | c78e03c | 2011-07-19 21:06:00 +0000 | [diff] [blame] | 1251 | let DecoderNamespace = "Thumb2"; |
Evan Cheng | d76f0be | 2009-06-25 02:08:06 +0000 | [diff] [blame] | 1252 | } |
| 1253 | |
| 1254 | // Special cases |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1255 | class Thumb2XI<dag oops, dag iops, AddrMode am, int sz, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1256 | InstrItinClass itin, |
Evan Cheng | d76f0be | 2009-06-25 02:08:06 +0000 | [diff] [blame] | 1257 | string asm, string cstr, list<dag> pattern> |
Anton Korobeynikov | 14635da | 2009-11-02 00:10:38 +0000 | [diff] [blame] | 1258 | : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { |
Evan Cheng | d76f0be | 2009-06-25 02:08:06 +0000 | [diff] [blame] | 1259 | let OutOperandList = oops; |
| 1260 | let InOperandList = iops; |
Bob Wilson | 722bff2 | 2010-05-24 20:08:34 +0000 | [diff] [blame] | 1261 | let AsmString = asm; |
Evan Cheng | 431cf56 | 2009-06-23 17:48:47 +0000 | [diff] [blame] | 1262 | let Pattern = pattern; |
Evan Cheng | 2c450d3 | 2009-07-02 06:38:40 +0000 | [diff] [blame] | 1263 | list<Predicate> Predicates = [IsThumb2]; |
Owen Anderson | c78e03c | 2011-07-19 21:06:00 +0000 | [diff] [blame] | 1264 | let DecoderNamespace = "Thumb2"; |
Evan Cheng | 431cf56 | 2009-06-23 17:48:47 +0000 | [diff] [blame] | 1265 | } |
| 1266 | |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1267 | class ThumbXI<dag oops, dag iops, AddrMode am, int sz, |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 1268 | InstrItinClass itin, |
| 1269 | string asm, string cstr, list<dag> pattern> |
Jim Grosbach | 36d4dec | 2009-12-01 18:10:36 +0000 | [diff] [blame] | 1270 | : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { |
| 1271 | let OutOperandList = oops; |
| 1272 | let InOperandList = iops; |
Bob Wilson | 722bff2 | 2010-05-24 20:08:34 +0000 | [diff] [blame] | 1273 | let AsmString = asm; |
Jim Grosbach | 36d4dec | 2009-12-01 18:10:36 +0000 | [diff] [blame] | 1274 | let Pattern = pattern; |
Jim Grosbach | fddf36d | 2010-11-01 17:08:58 +0000 | [diff] [blame] | 1275 | list<Predicate> Predicates = [IsThumb, IsThumb1Only]; |
Owen Anderson | c78e03c | 2011-07-19 21:06:00 +0000 | [diff] [blame] | 1276 | let DecoderNamespace = "Thumb"; |
Jim Grosbach | 36d4dec | 2009-12-01 18:10:36 +0000 | [diff] [blame] | 1277 | } |
| 1278 | |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1279 | class T2I<dag oops, dag iops, InstrItinClass itin, |
| 1280 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1281 | : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>; |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1282 | class T2Ii12<dag oops, dag iops, InstrItinClass itin, |
| 1283 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1284 | : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>; |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1285 | class T2Ii8<dag oops, dag iops, InstrItinClass itin, |
| 1286 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1287 | : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>; |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1288 | class T2Iso<dag oops, dag iops, InstrItinClass itin, |
| 1289 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1290 | : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>; |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1291 | class T2Ipc<dag oops, dag iops, InstrItinClass itin, |
| 1292 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1293 | : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>; |
Jim Grosbach | 95bd6b7 | 2010-12-10 20:51:35 +0000 | [diff] [blame] | 1294 | class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin, |
Jim Grosbach | 7db8d69 | 2011-09-08 22:07:06 +0000 | [diff] [blame] | 1295 | string opc, string asm, string cstr, list<dag> pattern> |
| 1296 | : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr, |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1297 | pattern> { |
Owen Anderson | 943fb60 | 2010-12-01 19:18:46 +0000 | [diff] [blame] | 1298 | bits<4> Rt; |
| 1299 | bits<4> Rt2; |
| 1300 | bits<13> addr; |
Jim Grosbach | 95bd6b7 | 2010-12-10 20:51:35 +0000 | [diff] [blame] | 1301 | let Inst{31-25} = 0b1110100; |
| 1302 | let Inst{24} = P; |
| 1303 | let Inst{23} = addr{8}; |
| 1304 | let Inst{22} = 1; |
| 1305 | let Inst{21} = W; |
| 1306 | let Inst{20} = isLoad; |
| 1307 | let Inst{19-16} = addr{12-9}; |
Owen Anderson | 943fb60 | 2010-12-01 19:18:46 +0000 | [diff] [blame] | 1308 | let Inst{15-12} = Rt{3-0}; |
| 1309 | let Inst{11-8} = Rt2{3-0}; |
Owen Anderson | 943fb60 | 2010-12-01 19:18:46 +0000 | [diff] [blame] | 1310 | let Inst{7-0} = addr{7-0}; |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1311 | } |
Jim Grosbach | 7db8d69 | 2011-09-08 22:07:06 +0000 | [diff] [blame] | 1312 | class T2Ii8s4post<bit P, bit W, bit isLoad, dag oops, dag iops, |
| 1313 | InstrItinClass itin, string opc, string asm, string cstr, |
| 1314 | list<dag> pattern> |
| 1315 | : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr, |
Owen Anderson | 08d4bb0 | 2011-08-04 23:18:05 +0000 | [diff] [blame] | 1316 | pattern> { |
| 1317 | bits<4> Rt; |
| 1318 | bits<4> Rt2; |
Jim Grosbach | 7db8d69 | 2011-09-08 22:07:06 +0000 | [diff] [blame] | 1319 | bits<4> addr; |
Owen Anderson | 08d4bb0 | 2011-08-04 23:18:05 +0000 | [diff] [blame] | 1320 | bits<9> imm; |
| 1321 | let Inst{31-25} = 0b1110100; |
| 1322 | let Inst{24} = P; |
| 1323 | let Inst{23} = imm{8}; |
| 1324 | let Inst{22} = 1; |
| 1325 | let Inst{21} = W; |
| 1326 | let Inst{20} = isLoad; |
Jim Grosbach | 7db8d69 | 2011-09-08 22:07:06 +0000 | [diff] [blame] | 1327 | let Inst{19-16} = addr; |
Owen Anderson | 08d4bb0 | 2011-08-04 23:18:05 +0000 | [diff] [blame] | 1328 | let Inst{15-12} = Rt{3-0}; |
| 1329 | let Inst{11-8} = Rt2{3-0}; |
| 1330 | let Inst{7-0} = imm{7-0}; |
| 1331 | } |
| 1332 | |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1333 | class T2sI<dag oops, dag iops, InstrItinClass itin, |
| 1334 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1335 | : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>; |
Evan Cheng | d76f0be | 2009-06-25 02:08:06 +0000 | [diff] [blame] | 1336 | |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1337 | class T2XI<dag oops, dag iops, InstrItinClass itin, |
| 1338 | string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1339 | : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>; |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1340 | class T2JTI<dag oops, dag iops, InstrItinClass itin, |
| 1341 | string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1342 | : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>; |
Evan Cheng | 431cf56 | 2009-06-23 17:48:47 +0000 | [diff] [blame] | 1343 | |
Bruno Cardoso Lopes | 4d4b490 | 2011-01-20 16:58:48 +0000 | [diff] [blame] | 1344 | // Move to/from coprocessor instructions |
Tim Northover | 2c45a38 | 2013-06-26 16:52:40 +0000 | [diff] [blame] | 1345 | class T2Cop<bits<4> opc, dag oops, dag iops, string opcstr, string asm, |
| 1346 | list<dag> pattern> |
| 1347 | : T2I <oops, iops, NoItinerary, opcstr, asm, pattern>, Requires<[IsThumb2]> { |
Jim Grosbach | cabb48d | 2011-07-13 21:17:59 +0000 | [diff] [blame] | 1348 | let Inst{31-28} = opc; |
Bruno Cardoso Lopes | 4d4b490 | 2011-01-20 16:58:48 +0000 | [diff] [blame] | 1349 | } |
| 1350 | |
Bob Wilson | 947f04b | 2010-03-13 01:08:20 +0000 | [diff] [blame] | 1351 | // Two-address instructions |
| 1352 | class T2XIt<dag oops, dag iops, InstrItinClass itin, |
| 1353 | string asm, string cstr, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1354 | : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>; |
Evan Cheng | 83e0d48 | 2009-09-28 09:14:39 +0000 | [diff] [blame] | 1355 | |
Jim Grosbach | c086f68 | 2011-09-08 00:39:19 +0000 | [diff] [blame] | 1356 | // T2Ipreldst - Thumb2 pre-indexed load / store instructions. |
| 1357 | class T2Ipreldst<bit signed, bits<2> opcod, bit load, bit pre, |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1358 | dag oops, dag iops, |
| 1359 | AddrMode am, IndexMode im, InstrItinClass itin, |
Evan Cheng | 84c6cda | 2009-07-02 07:28:31 +0000 | [diff] [blame] | 1360 | string opc, string asm, string cstr, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1361 | : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> { |
Evan Cheng | 84c6cda | 2009-07-02 07:28:31 +0000 | [diff] [blame] | 1362 | let OutOperandList = oops; |
Chris Lattner | fb2ceed | 2010-03-18 21:06:54 +0000 | [diff] [blame] | 1363 | let InOperandList = !con(iops, (ins pred:$p)); |
Chris Lattner | 04c342e | 2010-10-06 00:05:18 +0000 | [diff] [blame] | 1364 | let AsmString = !strconcat(opc, "${p}", asm); |
Evan Cheng | 84c6cda | 2009-07-02 07:28:31 +0000 | [diff] [blame] | 1365 | let Pattern = pattern; |
| 1366 | list<Predicate> Predicates = [IsThumb2]; |
Owen Anderson | c78e03c | 2011-07-19 21:06:00 +0000 | [diff] [blame] | 1367 | let DecoderNamespace = "Thumb2"; |
Jim Grosbach | c086f68 | 2011-09-08 00:39:19 +0000 | [diff] [blame] | 1368 | |
| 1369 | bits<4> Rt; |
| 1370 | bits<13> addr; |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1371 | let Inst{31-27} = 0b11111; |
| 1372 | let Inst{26-25} = 0b00; |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 1373 | let Inst{24} = signed; |
| 1374 | let Inst{23} = 0; |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1375 | let Inst{22-21} = opcod; |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 1376 | let Inst{20} = load; |
Jim Grosbach | c086f68 | 2011-09-08 00:39:19 +0000 | [diff] [blame] | 1377 | let Inst{19-16} = addr{12-9}; |
| 1378 | let Inst{15-12} = Rt{3-0}; |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 1379 | let Inst{11} = 1; |
Johnny Chen | c28e629 | 2009-12-15 17:24:14 +0000 | [diff] [blame] | 1380 | // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 1381 | let Inst{10} = pre; // The P bit. |
Jim Grosbach | c086f68 | 2011-09-08 00:39:19 +0000 | [diff] [blame] | 1382 | let Inst{9} = addr{8}; // Sign bit |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 1383 | let Inst{8} = 1; // The W bit. |
Jim Grosbach | c086f68 | 2011-09-08 00:39:19 +0000 | [diff] [blame] | 1384 | let Inst{7-0} = addr{7-0}; |
Owen Anderson | a9ebf6f | 2011-09-12 18:56:30 +0000 | [diff] [blame] | 1385 | |
| 1386 | let DecoderMethod = "DecodeT2LdStPre"; |
Jim Grosbach | c086f68 | 2011-09-08 00:39:19 +0000 | [diff] [blame] | 1387 | } |
Jim Grosbach | c4669ed | 2010-12-10 20:47:29 +0000 | [diff] [blame] | 1388 | |
Jim Grosbach | c086f68 | 2011-09-08 00:39:19 +0000 | [diff] [blame] | 1389 | // T2Ipostldst - Thumb2 post-indexed load / store instructions. |
| 1390 | class T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre, |
| 1391 | dag oops, dag iops, |
| 1392 | AddrMode am, IndexMode im, InstrItinClass itin, |
| 1393 | string opc, string asm, string cstr, list<dag> pattern> |
| 1394 | : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> { |
| 1395 | let OutOperandList = oops; |
| 1396 | let InOperandList = !con(iops, (ins pred:$p)); |
| 1397 | let AsmString = !strconcat(opc, "${p}", asm); |
| 1398 | let Pattern = pattern; |
| 1399 | list<Predicate> Predicates = [IsThumb2]; |
| 1400 | let DecoderNamespace = "Thumb2"; |
Jim Grosbach | c4669ed | 2010-12-10 20:47:29 +0000 | [diff] [blame] | 1401 | |
Owen Anderson | e22c732 | 2010-11-30 00:14:31 +0000 | [diff] [blame] | 1402 | bits<4> Rt; |
| 1403 | bits<4> Rn; |
Jim Grosbach | 3343da5 | 2011-09-08 01:01:32 +0000 | [diff] [blame] | 1404 | bits<9> offset; |
Jim Grosbach | c086f68 | 2011-09-08 00:39:19 +0000 | [diff] [blame] | 1405 | let Inst{31-27} = 0b11111; |
| 1406 | let Inst{26-25} = 0b00; |
| 1407 | let Inst{24} = signed; |
| 1408 | let Inst{23} = 0; |
| 1409 | let Inst{22-21} = opcod; |
| 1410 | let Inst{20} = load; |
| 1411 | let Inst{19-16} = Rn; |
Owen Anderson | e22c732 | 2010-11-30 00:14:31 +0000 | [diff] [blame] | 1412 | let Inst{15-12} = Rt{3-0}; |
Jim Grosbach | c086f68 | 2011-09-08 00:39:19 +0000 | [diff] [blame] | 1413 | let Inst{11} = 1; |
| 1414 | // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed |
| 1415 | let Inst{10} = pre; // The P bit. |
Jim Grosbach | 3343da5 | 2011-09-08 01:01:32 +0000 | [diff] [blame] | 1416 | let Inst{9} = offset{8}; // Sign bit |
Jim Grosbach | c086f68 | 2011-09-08 00:39:19 +0000 | [diff] [blame] | 1417 | let Inst{8} = 1; // The W bit. |
Jim Grosbach | 3343da5 | 2011-09-08 01:01:32 +0000 | [diff] [blame] | 1418 | let Inst{7-0} = offset{7-0}; |
Owen Anderson | a9ebf6f | 2011-09-12 18:56:30 +0000 | [diff] [blame] | 1419 | |
| 1420 | let DecoderMethod = "DecodeT2LdStPre"; |
Evan Cheng | 84c6cda | 2009-07-02 07:28:31 +0000 | [diff] [blame] | 1421 | } |
| 1422 | |
David Goodwin | e5b969f | 2009-07-27 19:59:26 +0000 | [diff] [blame] | 1423 | // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. |
| 1424 | class T1Pat<dag pattern, dag result> : Pat<pattern, result> { |
Jim Grosbach | fddf36d | 2010-11-01 17:08:58 +0000 | [diff] [blame] | 1425 | list<Predicate> Predicates = [IsThumb, IsThumb1Only]; |
David Goodwin | e5b969f | 2009-07-27 19:59:26 +0000 | [diff] [blame] | 1426 | } |
Evan Cheng | 84c6cda | 2009-07-02 07:28:31 +0000 | [diff] [blame] | 1427 | |
Bruno Cardoso Lopes | 168c900 | 2011-05-03 17:29:22 +0000 | [diff] [blame] | 1428 | // T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode. |
| 1429 | class T2v6Pat<dag pattern, dag result> : Pat<pattern, result> { |
| 1430 | list<Predicate> Predicates = [IsThumb2, HasV6T2]; |
| 1431 | } |
| 1432 | |
Evan Cheng | eab9ca7 | 2009-06-27 02:26:13 +0000 | [diff] [blame] | 1433 | // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. |
| 1434 | class T2Pat<dag pattern, dag result> : Pat<pattern, result> { |
Evan Cheng | 2c450d3 | 2009-07-02 06:38:40 +0000 | [diff] [blame] | 1435 | list<Predicate> Predicates = [IsThumb2]; |
Evan Cheng | 431cf56 | 2009-06-23 17:48:47 +0000 | [diff] [blame] | 1436 | } |
| 1437 | |
Evan Cheng | ee98fa9 | 2008-08-29 06:41:12 +0000 | [diff] [blame] | 1438 | //===----------------------------------------------------------------------===// |
| 1439 | |
Evan Cheng | ac2af2f | 2008-11-11 02:11:05 +0000 | [diff] [blame] | 1440 | //===----------------------------------------------------------------------===// |
| 1441 | // ARM VFP Instruction templates. |
| 1442 | // |
| 1443 | |
David Goodwin | 81cdd21 | 2009-07-10 17:03:29 +0000 | [diff] [blame] | 1444 | // Almost all VFP instructions are predicable. |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1445 | class VFPI<dag oops, dag iops, AddrMode am, int sz, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1446 | IndexMode im, Format f, InstrItinClass itin, |
| 1447 | string opc, string asm, string cstr, list<dag> pattern> |
Anton Korobeynikov | 14635da | 2009-11-02 00:10:38 +0000 | [diff] [blame] | 1448 | : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { |
Jim Grosbach | 576640f | 2010-10-12 21:22:40 +0000 | [diff] [blame] | 1449 | bits<4> p; |
| 1450 | let Inst{31-28} = p; |
David Goodwin | 81cdd21 | 2009-07-10 17:03:29 +0000 | [diff] [blame] | 1451 | let OutOperandList = oops; |
Chris Lattner | fb2ceed | 2010-03-18 21:06:54 +0000 | [diff] [blame] | 1452 | let InOperandList = !con(iops, (ins pred:$p)); |
Chris Lattner | 04c342e | 2010-10-06 00:05:18 +0000 | [diff] [blame] | 1453 | let AsmString = !strconcat(opc, "${p}", asm); |
David Goodwin | 81cdd21 | 2009-07-10 17:03:29 +0000 | [diff] [blame] | 1454 | let Pattern = pattern; |
Bill Wendling | 87240d4 | 2010-12-01 21:54:50 +0000 | [diff] [blame] | 1455 | let PostEncoderMethod = "VFPThumb2PostEncoder"; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1456 | let DecoderNamespace = "VFP"; |
David Goodwin | 81cdd21 | 2009-07-10 17:03:29 +0000 | [diff] [blame] | 1457 | list<Predicate> Predicates = [HasVFP2]; |
| 1458 | } |
| 1459 | |
| 1460 | // Special cases |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1461 | class VFPXI<dag oops, dag iops, AddrMode am, int sz, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1462 | IndexMode im, Format f, InstrItinClass itin, |
| 1463 | string asm, string cstr, list<dag> pattern> |
Anton Korobeynikov | 14635da | 2009-11-02 00:10:38 +0000 | [diff] [blame] | 1464 | : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { |
Bill Wendling | 345b48f | 2010-11-17 00:45:23 +0000 | [diff] [blame] | 1465 | bits<4> p; |
| 1466 | let Inst{31-28} = p; |
David Goodwin | 81cdd21 | 2009-07-10 17:03:29 +0000 | [diff] [blame] | 1467 | let OutOperandList = oops; |
| 1468 | let InOperandList = iops; |
Bob Wilson | 722bff2 | 2010-05-24 20:08:34 +0000 | [diff] [blame] | 1469 | let AsmString = asm; |
David Goodwin | 81cdd21 | 2009-07-10 17:03:29 +0000 | [diff] [blame] | 1470 | let Pattern = pattern; |
Bill Wendling | 87240d4 | 2010-12-01 21:54:50 +0000 | [diff] [blame] | 1471 | let PostEncoderMethod = "VFPThumb2PostEncoder"; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1472 | let DecoderNamespace = "VFP"; |
David Goodwin | 81cdd21 | 2009-07-10 17:03:29 +0000 | [diff] [blame] | 1473 | list<Predicate> Predicates = [HasVFP2]; |
| 1474 | } |
| 1475 | |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1476 | class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin, |
| 1477 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1478 | : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, |
Bill Wendling | 87240d4 | 2010-12-01 21:54:50 +0000 | [diff] [blame] | 1479 | opc, asm, "", pattern> { |
| 1480 | let PostEncoderMethod = "VFPThumb2PostEncoder"; |
| 1481 | } |
David Goodwin | 81cdd21 | 2009-07-10 17:03:29 +0000 | [diff] [blame] | 1482 | |
Evan Cheng | 8cbbcb1 | 2008-11-11 21:48:44 +0000 | [diff] [blame] | 1483 | // ARM VFP addrmode5 loads and stores |
| 1484 | class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1485 | InstrItinClass itin, |
Evan Cheng | 8cbbcb1 | 2008-11-11 21:48:44 +0000 | [diff] [blame] | 1486 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1487 | : VFPI<oops, iops, AddrMode5, 4, IndexModeNone, |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 1488 | VFPLdStFrm, itin, opc, asm, "", pattern> { |
Bill Wendling | c002463 | 2010-11-04 00:59:42 +0000 | [diff] [blame] | 1489 | // Instruction operands. |
| 1490 | bits<5> Dd; |
| 1491 | bits<13> addr; |
| 1492 | |
| 1493 | // Encode instruction operands. |
| 1494 | let Inst{23} = addr{8}; // U (add = (U == '1')) |
| 1495 | let Inst{22} = Dd{4}; |
| 1496 | let Inst{19-16} = addr{12-9}; // Rn |
| 1497 | let Inst{15-12} = Dd{3-0}; |
| 1498 | let Inst{7-0} = addr{7-0}; // imm8 |
| 1499 | |
Evan Cheng | 8cbbcb1 | 2008-11-11 21:48:44 +0000 | [diff] [blame] | 1500 | let Inst{27-24} = opcod1; |
| 1501 | let Inst{21-20} = opcod2; |
Bill Wendling | 98c29d7 | 2010-10-12 22:03:19 +0000 | [diff] [blame] | 1502 | let Inst{11-9} = 0b101; |
| 1503 | let Inst{8} = 1; // Double precision |
Anton Korobeynikov | 8cce1eb | 2009-11-02 00:11:06 +0000 | [diff] [blame] | 1504 | |
Evan Cheng | 4a8c43f | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 1505 | // Loads & stores operate on both NEON and VFP pipelines. |
Jakob Stoklund Olesen | b93331f | 2010-04-05 03:10:20 +0000 | [diff] [blame] | 1506 | let D = VFPNeonDomain; |
Evan Cheng | ac2af2f | 2008-11-11 02:11:05 +0000 | [diff] [blame] | 1507 | } |
| 1508 | |
Evan Cheng | 8cbbcb1 | 2008-11-11 21:48:44 +0000 | [diff] [blame] | 1509 | class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1510 | InstrItinClass itin, |
Evan Cheng | 8cbbcb1 | 2008-11-11 21:48:44 +0000 | [diff] [blame] | 1511 | string opc, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1512 | : VFPI<oops, iops, AddrMode5, 4, IndexModeNone, |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 1513 | VFPLdStFrm, itin, opc, asm, "", pattern> { |
Bill Wendling | c002463 | 2010-11-04 00:59:42 +0000 | [diff] [blame] | 1514 | // Instruction operands. |
| 1515 | bits<5> Sd; |
| 1516 | bits<13> addr; |
| 1517 | |
| 1518 | // Encode instruction operands. |
| 1519 | let Inst{23} = addr{8}; // U (add = (U == '1')) |
| 1520 | let Inst{22} = Sd{0}; |
| 1521 | let Inst{19-16} = addr{12-9}; // Rn |
| 1522 | let Inst{15-12} = Sd{4-1}; |
| 1523 | let Inst{7-0} = addr{7-0}; // imm8 |
| 1524 | |
Evan Cheng | 8cbbcb1 | 2008-11-11 21:48:44 +0000 | [diff] [blame] | 1525 | let Inst{27-24} = opcod1; |
| 1526 | let Inst{21-20} = opcod2; |
Bill Wendling | 98c29d7 | 2010-10-12 22:03:19 +0000 | [diff] [blame] | 1527 | let Inst{11-9} = 0b101; |
| 1528 | let Inst{8} = 0; // Single precision |
Evan Cheng | 4a8c43f | 2011-02-16 00:35:02 +0000 | [diff] [blame] | 1529 | |
| 1530 | // Loads & stores operate on both NEON and VFP pipelines. |
| 1531 | let D = VFPNeonDomain; |
Evan Cheng | ac2af2f | 2008-11-11 02:11:05 +0000 | [diff] [blame] | 1532 | } |
| 1533 | |
Oliver Stannard | 65b8538 | 2016-01-25 10:26:26 +0000 | [diff] [blame] | 1534 | class AHI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, |
| 1535 | InstrItinClass itin, |
| 1536 | string opc, string asm, list<dag> pattern> |
Sjoerd Meijer | 011de9c | 2018-01-26 09:26:40 +0000 | [diff] [blame] | 1537 | : VFPI<oops, iops, AddrMode5FP16, 4, IndexModeNone, |
Oliver Stannard | 65b8538 | 2016-01-25 10:26:26 +0000 | [diff] [blame] | 1538 | VFPLdStFrm, itin, opc, asm, "", pattern> { |
| 1539 | list<Predicate> Predicates = [HasFullFP16]; |
| 1540 | |
| 1541 | // Instruction operands. |
| 1542 | bits<5> Sd; |
| 1543 | bits<13> addr; |
| 1544 | |
| 1545 | // Encode instruction operands. |
| 1546 | let Inst{23} = addr{8}; // U (add = (U == '1')) |
| 1547 | let Inst{22} = Sd{0}; |
| 1548 | let Inst{19-16} = addr{12-9}; // Rn |
| 1549 | let Inst{15-12} = Sd{4-1}; |
| 1550 | let Inst{7-0} = addr{7-0}; // imm8 |
| 1551 | |
| 1552 | let Inst{27-24} = opcod1; |
| 1553 | let Inst{21-20} = opcod2; |
| 1554 | let Inst{11-8} = 0b1001; // Half precision |
| 1555 | |
| 1556 | // Loads & stores operate on both NEON and VFP pipelines. |
| 1557 | let D = VFPNeonDomain; |
| 1558 | } |
| 1559 | |
Bob Wilson | 6b853c3 | 2010-09-16 00:31:02 +0000 | [diff] [blame] | 1560 | // VFP Load / store multiple pseudo instructions. |
| 1561 | class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr, |
| 1562 | list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1563 | : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain, |
Bob Wilson | 6b853c3 | 2010-09-16 00:31:02 +0000 | [diff] [blame] | 1564 | cstr, itin> { |
| 1565 | let OutOperandList = oops; |
| 1566 | let InOperandList = !con(iops, (ins pred:$p)); |
| 1567 | let Pattern = pattern; |
| 1568 | list<Predicate> Predicates = [HasVFP2]; |
| 1569 | } |
| 1570 | |
Evan Cheng | 8cbbcb1 | 2008-11-11 21:48:44 +0000 | [diff] [blame] | 1571 | // Load / store multiple |
Tim Northover | 4173e29 | 2013-05-31 15:55:51 +0000 | [diff] [blame] | 1572 | |
| 1573 | // Unknown precision |
| 1574 | class AXXI4<dag oops, dag iops, IndexMode im, |
| 1575 | string asm, string cstr, list<dag> pattern> |
| 1576 | : VFPXI<oops, iops, AddrMode4, 4, im, |
| 1577 | VFPLdStFrm, NoItinerary, asm, cstr, pattern> { |
| 1578 | // Instruction operands. |
| 1579 | bits<4> Rn; |
| 1580 | bits<13> regs; |
| 1581 | |
| 1582 | // Encode instruction operands. |
| 1583 | let Inst{19-16} = Rn; |
| 1584 | let Inst{22} = 0; |
| 1585 | let Inst{15-12} = regs{11-8}; |
| 1586 | let Inst{7-1} = regs{7-1}; |
| 1587 | |
| 1588 | let Inst{27-25} = 0b110; |
| 1589 | let Inst{11-8} = 0b1011; |
| 1590 | let Inst{0} = 1; |
| 1591 | } |
| 1592 | |
| 1593 | // Double precision |
Jim Grosbach | abcbe24 | 2010-09-08 00:25:50 +0000 | [diff] [blame] | 1594 | class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, |
Bob Wilson | 947f04b | 2010-03-13 01:08:20 +0000 | [diff] [blame] | 1595 | string asm, string cstr, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1596 | : VFPXI<oops, iops, AddrMode4, 4, im, |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 1597 | VFPLdStMulFrm, itin, asm, cstr, pattern> { |
Bill Wendling | 345b48f | 2010-11-17 00:45:23 +0000 | [diff] [blame] | 1598 | // Instruction operands. |
| 1599 | bits<4> Rn; |
| 1600 | bits<13> regs; |
| 1601 | |
| 1602 | // Encode instruction operands. |
| 1603 | let Inst{19-16} = Rn; |
| 1604 | let Inst{22} = regs{12}; |
| 1605 | let Inst{15-12} = regs{11-8}; |
Tim Northover | 4173e29 | 2013-05-31 15:55:51 +0000 | [diff] [blame] | 1606 | let Inst{7-1} = regs{7-1}; |
Bill Wendling | 345b48f | 2010-11-17 00:45:23 +0000 | [diff] [blame] | 1607 | |
Evan Cheng | 8cbbcb1 | 2008-11-11 21:48:44 +0000 | [diff] [blame] | 1608 | let Inst{27-25} = 0b110; |
Bill Wendling | 98c29d7 | 2010-10-12 22:03:19 +0000 | [diff] [blame] | 1609 | let Inst{11-9} = 0b101; |
| 1610 | let Inst{8} = 1; // Double precision |
Tim Northover | 4173e29 | 2013-05-31 15:55:51 +0000 | [diff] [blame] | 1611 | let Inst{0} = 0; |
Evan Cheng | 8cbbcb1 | 2008-11-11 21:48:44 +0000 | [diff] [blame] | 1612 | } |
| 1613 | |
Tim Northover | 4173e29 | 2013-05-31 15:55:51 +0000 | [diff] [blame] | 1614 | // Single Precision |
Jim Grosbach | abcbe24 | 2010-09-08 00:25:50 +0000 | [diff] [blame] | 1615 | class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, |
Bob Wilson | 947f04b | 2010-03-13 01:08:20 +0000 | [diff] [blame] | 1616 | string asm, string cstr, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 1617 | : VFPXI<oops, iops, AddrMode4, 4, im, |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 1618 | VFPLdStMulFrm, itin, asm, cstr, pattern> { |
Bill Wendling | 345b48f | 2010-11-17 00:45:23 +0000 | [diff] [blame] | 1619 | // Instruction operands. |
| 1620 | bits<4> Rn; |
| 1621 | bits<13> regs; |
| 1622 | |
| 1623 | // Encode instruction operands. |
| 1624 | let Inst{19-16} = Rn; |
| 1625 | let Inst{22} = regs{8}; |
| 1626 | let Inst{15-12} = regs{12-9}; |
| 1627 | let Inst{7-0} = regs{7-0}; |
| 1628 | |
Evan Cheng | 8cbbcb1 | 2008-11-11 21:48:44 +0000 | [diff] [blame] | 1629 | let Inst{27-25} = 0b110; |
Bill Wendling | 98c29d7 | 2010-10-12 22:03:19 +0000 | [diff] [blame] | 1630 | let Inst{11-9} = 0b101; |
| 1631 | let Inst{8} = 0; // Single precision |
Evan Cheng | 8cbbcb1 | 2008-11-11 21:48:44 +0000 | [diff] [blame] | 1632 | } |
| 1633 | |
Evan Cheng | ac2af2f | 2008-11-11 02:11:05 +0000 | [diff] [blame] | 1634 | // Double precision, unary |
Johnny Chen | 34a6afc | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 1635 | class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, |
| 1636 | bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, |
| 1637 | string asm, list<dag> pattern> |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1638 | : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { |
Bill Wendling | 2623343 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 1639 | // Instruction operands. |
| 1640 | bits<5> Dd; |
| 1641 | bits<5> Dm; |
| 1642 | |
| 1643 | // Encode instruction operands. |
| 1644 | let Inst{3-0} = Dm{3-0}; |
| 1645 | let Inst{5} = Dm{4}; |
| 1646 | let Inst{15-12} = Dd{3-0}; |
| 1647 | let Inst{22} = Dd{4}; |
| 1648 | |
Johnny Chen | 34a6afc | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 1649 | let Inst{27-23} = opcod1; |
| 1650 | let Inst{21-20} = opcod2; |
| 1651 | let Inst{19-16} = opcod3; |
Bill Wendling | 98c29d7 | 2010-10-12 22:03:19 +0000 | [diff] [blame] | 1652 | let Inst{11-9} = 0b101; |
| 1653 | let Inst{8} = 1; // Double precision |
Johnny Chen | 34a6afc | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 1654 | let Inst{7-6} = opcod4; |
| 1655 | let Inst{4} = opcod5; |
Tim Northover | 5620faf | 2013-10-24 15:49:39 +0000 | [diff] [blame] | 1656 | |
| 1657 | let Predicates = [HasVFP2, HasDPVFP]; |
Evan Cheng | ac2af2f | 2008-11-11 02:11:05 +0000 | [diff] [blame] | 1658 | } |
| 1659 | |
Joey Gouly | 0f12aa2 | 2013-07-09 11:26:18 +0000 | [diff] [blame] | 1660 | // Double precision, unary, not-predicated |
| 1661 | class ADuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, |
| 1662 | bit opcod5, dag oops, dag iops, InstrItinClass itin, |
| 1663 | string asm, list<dag> pattern> |
| 1664 | : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, VFPUnaryFrm, itin, asm, "", pattern> { |
| 1665 | // Instruction operands. |
| 1666 | bits<5> Dd; |
| 1667 | bits<5> Dm; |
| 1668 | |
| 1669 | let Inst{31-28} = 0b1111; |
| 1670 | |
| 1671 | // Encode instruction operands. |
| 1672 | let Inst{3-0} = Dm{3-0}; |
| 1673 | let Inst{5} = Dm{4}; |
| 1674 | let Inst{15-12} = Dd{3-0}; |
| 1675 | let Inst{22} = Dd{4}; |
| 1676 | |
| 1677 | let Inst{27-23} = opcod1; |
| 1678 | let Inst{21-20} = opcod2; |
| 1679 | let Inst{19-16} = opcod3; |
| 1680 | let Inst{11-9} = 0b101; |
| 1681 | let Inst{8} = 1; // Double precision |
| 1682 | let Inst{7-6} = opcod4; |
| 1683 | let Inst{4} = opcod5; |
| 1684 | } |
| 1685 | |
Evan Cheng | ac2af2f | 2008-11-11 02:11:05 +0000 | [diff] [blame] | 1686 | // Double precision, binary |
Johnny Chen | 34a6afc | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 1687 | class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 1688 | dag iops, InstrItinClass itin, string opc, string asm, |
| 1689 | list<dag> pattern> |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1690 | : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { |
Bill Wendling | 2623343 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 1691 | // Instruction operands. |
| 1692 | bits<5> Dd; |
| 1693 | bits<5> Dn; |
| 1694 | bits<5> Dm; |
| 1695 | |
| 1696 | // Encode instruction operands. |
| 1697 | let Inst{3-0} = Dm{3-0}; |
| 1698 | let Inst{5} = Dm{4}; |
| 1699 | let Inst{19-16} = Dn{3-0}; |
| 1700 | let Inst{7} = Dn{4}; |
| 1701 | let Inst{15-12} = Dd{3-0}; |
| 1702 | let Inst{22} = Dd{4}; |
| 1703 | |
Johnny Chen | 34a6afc | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 1704 | let Inst{27-23} = opcod1; |
| 1705 | let Inst{21-20} = opcod2; |
Bill Wendling | 98c29d7 | 2010-10-12 22:03:19 +0000 | [diff] [blame] | 1706 | let Inst{11-9} = 0b101; |
| 1707 | let Inst{8} = 1; // Double precision |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 1708 | let Inst{6} = op6; |
| 1709 | let Inst{4} = op4; |
Tim Northover | 5620faf | 2013-10-24 15:49:39 +0000 | [diff] [blame] | 1710 | |
| 1711 | let Predicates = [HasVFP2, HasDPVFP]; |
Evan Cheng | ac2af2f | 2008-11-11 02:11:05 +0000 | [diff] [blame] | 1712 | } |
| 1713 | |
Joey Gouly | cc4ff9e | 2013-07-04 14:57:20 +0000 | [diff] [blame] | 1714 | // FP, binary, not predicated |
Joey Gouly | 2efaa73 | 2013-07-06 20:50:18 +0000 | [diff] [blame] | 1715 | class ADbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops, |
Joey Gouly | cc4ff9e | 2013-07-04 14:57:20 +0000 | [diff] [blame] | 1716 | InstrItinClass itin, string asm, list<dag> pattern> |
Joey Gouly | 2d0175e | 2013-07-09 09:59:04 +0000 | [diff] [blame] | 1717 | : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, VFPBinaryFrm, itin, |
| 1718 | asm, "", pattern> |
Joey Gouly | cc4ff9e | 2013-07-04 14:57:20 +0000 | [diff] [blame] | 1719 | { |
| 1720 | // Instruction operands. |
| 1721 | bits<5> Dd; |
| 1722 | bits<5> Dn; |
| 1723 | bits<5> Dm; |
| 1724 | |
| 1725 | let Inst{31-28} = 0b1111; |
| 1726 | |
| 1727 | // Encode instruction operands. |
| 1728 | let Inst{3-0} = Dm{3-0}; |
| 1729 | let Inst{5} = Dm{4}; |
| 1730 | let Inst{19-16} = Dn{3-0}; |
| 1731 | let Inst{7} = Dn{4}; |
| 1732 | let Inst{15-12} = Dd{3-0}; |
| 1733 | let Inst{22} = Dd{4}; |
| 1734 | |
| 1735 | let Inst{27-23} = opcod1; |
| 1736 | let Inst{21-20} = opcod2; |
| 1737 | let Inst{11-9} = 0b101; |
| 1738 | let Inst{8} = 1; // double precision |
Joey Gouly | 2efaa73 | 2013-07-06 20:50:18 +0000 | [diff] [blame] | 1739 | let Inst{6} = opcod3; |
Joey Gouly | cc4ff9e | 2013-07-04 14:57:20 +0000 | [diff] [blame] | 1740 | let Inst{4} = 0; |
Tim Northover | 5620faf | 2013-10-24 15:49:39 +0000 | [diff] [blame] | 1741 | |
| 1742 | let Predicates = [HasVFP2, HasDPVFP]; |
Joey Gouly | cc4ff9e | 2013-07-04 14:57:20 +0000 | [diff] [blame] | 1743 | } |
| 1744 | |
Joey Gouly | 2d0175e | 2013-07-09 09:59:04 +0000 | [diff] [blame] | 1745 | // Single precision, unary, predicated |
Johnny Chen | 34a6afc | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 1746 | class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, |
| 1747 | bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, |
| 1748 | string asm, list<dag> pattern> |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1749 | : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { |
Bill Wendling | 2623343 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 1750 | // Instruction operands. |
| 1751 | bits<5> Sd; |
| 1752 | bits<5> Sm; |
| 1753 | |
| 1754 | // Encode instruction operands. |
| 1755 | let Inst{3-0} = Sm{4-1}; |
| 1756 | let Inst{5} = Sm{0}; |
| 1757 | let Inst{15-12} = Sd{4-1}; |
| 1758 | let Inst{22} = Sd{0}; |
| 1759 | |
Johnny Chen | 34a6afc | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 1760 | let Inst{27-23} = opcod1; |
| 1761 | let Inst{21-20} = opcod2; |
| 1762 | let Inst{19-16} = opcod3; |
Bill Wendling | 98c29d7 | 2010-10-12 22:03:19 +0000 | [diff] [blame] | 1763 | let Inst{11-9} = 0b101; |
| 1764 | let Inst{8} = 0; // Single precision |
Johnny Chen | 34a6afc | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 1765 | let Inst{7-6} = opcod4; |
| 1766 | let Inst{4} = opcod5; |
Evan Cheng | ac2af2f | 2008-11-11 02:11:05 +0000 | [diff] [blame] | 1767 | } |
| 1768 | |
Joey Gouly | 2d0175e | 2013-07-09 09:59:04 +0000 | [diff] [blame] | 1769 | // Single precision, unary, non-predicated |
| 1770 | class ASuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, |
| 1771 | bit opcod5, dag oops, dag iops, InstrItinClass itin, |
| 1772 | string asm, list<dag> pattern> |
| 1773 | : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, |
| 1774 | VFPUnaryFrm, itin, asm, "", pattern> { |
| 1775 | // Instruction operands. |
| 1776 | bits<5> Sd; |
| 1777 | bits<5> Sm; |
| 1778 | |
| 1779 | let Inst{31-28} = 0b1111; |
| 1780 | |
| 1781 | // Encode instruction operands. |
| 1782 | let Inst{3-0} = Sm{4-1}; |
| 1783 | let Inst{5} = Sm{0}; |
| 1784 | let Inst{15-12} = Sd{4-1}; |
| 1785 | let Inst{22} = Sd{0}; |
| 1786 | |
| 1787 | let Inst{27-23} = opcod1; |
| 1788 | let Inst{21-20} = opcod2; |
| 1789 | let Inst{19-16} = opcod3; |
| 1790 | let Inst{11-9} = 0b101; |
| 1791 | let Inst{8} = 0; // Single precision |
| 1792 | let Inst{7-6} = opcod4; |
| 1793 | let Inst{4} = opcod5; |
| 1794 | } |
| 1795 | |
Bill Wendling | cbb08ca | 2010-12-01 02:42:55 +0000 | [diff] [blame] | 1796 | // Single precision unary, if no NEON. Same as ASuI except not available if |
| 1797 | // NEON is enabled. |
Johnny Chen | 34a6afc | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 1798 | class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, |
| 1799 | bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, |
| 1800 | string asm, list<dag> pattern> |
| 1801 | : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm, |
| 1802 | pattern> { |
David Goodwin | 30bf625 | 2009-08-04 20:39:05 +0000 | [diff] [blame] | 1803 | list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; |
| 1804 | } |
| 1805 | |
Evan Cheng | ac2af2f | 2008-11-11 02:11:05 +0000 | [diff] [blame] | 1806 | // Single precision, binary |
Johnny Chen | 34a6afc | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 1807 | class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, |
| 1808 | InstrItinClass itin, string opc, string asm, list<dag> pattern> |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1809 | : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { |
Bill Wendling | 2623343 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 1810 | // Instruction operands. |
| 1811 | bits<5> Sd; |
| 1812 | bits<5> Sn; |
| 1813 | bits<5> Sm; |
| 1814 | |
| 1815 | // Encode instruction operands. |
| 1816 | let Inst{3-0} = Sm{4-1}; |
| 1817 | let Inst{5} = Sm{0}; |
| 1818 | let Inst{19-16} = Sn{4-1}; |
| 1819 | let Inst{7} = Sn{0}; |
| 1820 | let Inst{15-12} = Sd{4-1}; |
| 1821 | let Inst{22} = Sd{0}; |
| 1822 | |
Johnny Chen | 34a6afc | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 1823 | let Inst{27-23} = opcod1; |
| 1824 | let Inst{21-20} = opcod2; |
Bill Wendling | 98c29d7 | 2010-10-12 22:03:19 +0000 | [diff] [blame] | 1825 | let Inst{11-9} = 0b101; |
| 1826 | let Inst{8} = 0; // Single precision |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 1827 | let Inst{6} = op6; |
| 1828 | let Inst{4} = op4; |
Evan Cheng | ac2af2f | 2008-11-11 02:11:05 +0000 | [diff] [blame] | 1829 | } |
| 1830 | |
Joey Gouly | cc4ff9e | 2013-07-04 14:57:20 +0000 | [diff] [blame] | 1831 | // Single precision, binary, not predicated |
Joey Gouly | 2efaa73 | 2013-07-06 20:50:18 +0000 | [diff] [blame] | 1832 | class ASbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops, |
Joey Gouly | cc4ff9e | 2013-07-04 14:57:20 +0000 | [diff] [blame] | 1833 | InstrItinClass itin, string asm, list<dag> pattern> |
| 1834 | : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, |
| 1835 | VFPBinaryFrm, itin, asm, "", pattern> |
| 1836 | { |
| 1837 | // Instruction operands. |
| 1838 | bits<5> Sd; |
| 1839 | bits<5> Sn; |
| 1840 | bits<5> Sm; |
| 1841 | |
| 1842 | let Inst{31-28} = 0b1111; |
| 1843 | |
| 1844 | // Encode instruction operands. |
| 1845 | let Inst{3-0} = Sm{4-1}; |
| 1846 | let Inst{5} = Sm{0}; |
| 1847 | let Inst{19-16} = Sn{4-1}; |
| 1848 | let Inst{7} = Sn{0}; |
| 1849 | let Inst{15-12} = Sd{4-1}; |
| 1850 | let Inst{22} = Sd{0}; |
| 1851 | |
| 1852 | let Inst{27-23} = opcod1; |
| 1853 | let Inst{21-20} = opcod2; |
| 1854 | let Inst{11-9} = 0b101; |
| 1855 | let Inst{8} = 0; // Single precision |
Joey Gouly | 2efaa73 | 2013-07-06 20:50:18 +0000 | [diff] [blame] | 1856 | let Inst{6} = opcod3; |
Joey Gouly | cc4ff9e | 2013-07-04 14:57:20 +0000 | [diff] [blame] | 1857 | let Inst{4} = 0; |
| 1858 | } |
| 1859 | |
Bill Wendling | cbb08ca | 2010-12-01 02:42:55 +0000 | [diff] [blame] | 1860 | // Single precision binary, if no NEON. Same as ASbI except not available if |
| 1861 | // NEON is enabled. |
Johnny Chen | 34a6afc | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 1862 | class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 1863 | dag iops, InstrItinClass itin, string opc, string asm, |
| 1864 | list<dag> pattern> |
Johnny Chen | 34a6afc | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 1865 | : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { |
David Goodwin | 3b9c52c | 2009-08-04 17:53:06 +0000 | [diff] [blame] | 1866 | list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; |
Bill Wendling | 2623343 | 2010-11-01 06:00:39 +0000 | [diff] [blame] | 1867 | |
| 1868 | // Instruction operands. |
| 1869 | bits<5> Sd; |
| 1870 | bits<5> Sn; |
| 1871 | bits<5> Sm; |
| 1872 | |
| 1873 | // Encode instruction operands. |
| 1874 | let Inst{3-0} = Sm{4-1}; |
| 1875 | let Inst{5} = Sm{0}; |
| 1876 | let Inst{19-16} = Sn{4-1}; |
| 1877 | let Inst{7} = Sn{0}; |
| 1878 | let Inst{15-12} = Sd{4-1}; |
| 1879 | let Inst{22} = Sd{0}; |
David Goodwin | 3b9c52c | 2009-08-04 17:53:06 +0000 | [diff] [blame] | 1880 | } |
| 1881 | |
Oliver Stannard | 65b8538 | 2016-01-25 10:26:26 +0000 | [diff] [blame] | 1882 | // Half precision, unary, predicated |
| 1883 | class AHuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, |
| 1884 | bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, |
| 1885 | string asm, list<dag> pattern> |
| 1886 | : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { |
| 1887 | list<Predicate> Predicates = [HasFullFP16]; |
| 1888 | |
| 1889 | // Instruction operands. |
| 1890 | bits<5> Sd; |
| 1891 | bits<5> Sm; |
| 1892 | |
| 1893 | // Encode instruction operands. |
| 1894 | let Inst{3-0} = Sm{4-1}; |
| 1895 | let Inst{5} = Sm{0}; |
| 1896 | let Inst{15-12} = Sd{4-1}; |
| 1897 | let Inst{22} = Sd{0}; |
| 1898 | |
| 1899 | let Inst{27-23} = opcod1; |
| 1900 | let Inst{21-20} = opcod2; |
| 1901 | let Inst{19-16} = opcod3; |
| 1902 | let Inst{11-8} = 0b1001; // Half precision |
| 1903 | let Inst{7-6} = opcod4; |
| 1904 | let Inst{4} = opcod5; |
| 1905 | } |
| 1906 | |
| 1907 | // Half precision, unary, non-predicated |
| 1908 | class AHuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, |
| 1909 | bit opcod5, dag oops, dag iops, InstrItinClass itin, |
| 1910 | string asm, list<dag> pattern> |
| 1911 | : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, |
| 1912 | VFPUnaryFrm, itin, asm, "", pattern> { |
| 1913 | list<Predicate> Predicates = [HasFullFP16]; |
| 1914 | |
| 1915 | // Instruction operands. |
| 1916 | bits<5> Sd; |
| 1917 | bits<5> Sm; |
| 1918 | |
| 1919 | let Inst{31-28} = 0b1111; |
| 1920 | |
| 1921 | // Encode instruction operands. |
| 1922 | let Inst{3-0} = Sm{4-1}; |
| 1923 | let Inst{5} = Sm{0}; |
| 1924 | let Inst{15-12} = Sd{4-1}; |
| 1925 | let Inst{22} = Sd{0}; |
| 1926 | |
| 1927 | let Inst{27-23} = opcod1; |
| 1928 | let Inst{21-20} = opcod2; |
| 1929 | let Inst{19-16} = opcod3; |
| 1930 | let Inst{11-8} = 0b1001; // Half precision |
| 1931 | let Inst{7-6} = opcod4; |
| 1932 | let Inst{4} = opcod5; |
| 1933 | } |
| 1934 | |
| 1935 | // Half precision, binary |
| 1936 | class AHbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, |
| 1937 | InstrItinClass itin, string opc, string asm, list<dag> pattern> |
| 1938 | : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { |
| 1939 | list<Predicate> Predicates = [HasFullFP16]; |
| 1940 | |
| 1941 | // Instruction operands. |
| 1942 | bits<5> Sd; |
| 1943 | bits<5> Sn; |
| 1944 | bits<5> Sm; |
| 1945 | |
| 1946 | // Encode instruction operands. |
| 1947 | let Inst{3-0} = Sm{4-1}; |
| 1948 | let Inst{5} = Sm{0}; |
| 1949 | let Inst{19-16} = Sn{4-1}; |
| 1950 | let Inst{7} = Sn{0}; |
| 1951 | let Inst{15-12} = Sd{4-1}; |
| 1952 | let Inst{22} = Sd{0}; |
| 1953 | |
| 1954 | let Inst{27-23} = opcod1; |
| 1955 | let Inst{21-20} = opcod2; |
| 1956 | let Inst{11-8} = 0b1001; // Half precision |
| 1957 | let Inst{6} = op6; |
| 1958 | let Inst{4} = op4; |
| 1959 | } |
| 1960 | |
| 1961 | // Half precision, binary, not predicated |
| 1962 | class AHbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops, |
| 1963 | InstrItinClass itin, string asm, list<dag> pattern> |
| 1964 | : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, |
| 1965 | VFPBinaryFrm, itin, asm, "", pattern> { |
| 1966 | list<Predicate> Predicates = [HasFullFP16]; |
| 1967 | |
| 1968 | // Instruction operands. |
| 1969 | bits<5> Sd; |
| 1970 | bits<5> Sn; |
| 1971 | bits<5> Sm; |
| 1972 | |
| 1973 | let Inst{31-28} = 0b1111; |
| 1974 | |
| 1975 | // Encode instruction operands. |
| 1976 | let Inst{3-0} = Sm{4-1}; |
| 1977 | let Inst{5} = Sm{0}; |
| 1978 | let Inst{19-16} = Sn{4-1}; |
| 1979 | let Inst{7} = Sn{0}; |
| 1980 | let Inst{15-12} = Sd{4-1}; |
| 1981 | let Inst{22} = Sd{0}; |
| 1982 | |
| 1983 | let Inst{27-23} = opcod1; |
| 1984 | let Inst{21-20} = opcod2; |
| 1985 | let Inst{11-8} = 0b1001; // Half precision |
| 1986 | let Inst{6} = opcod3; |
| 1987 | let Inst{4} = 0; |
| 1988 | } |
| 1989 | |
Evan Cheng | 4b6c7ef | 2008-11-12 06:41:41 +0000 | [diff] [blame] | 1990 | // VFP conversion instructions |
Johnny Chen | 34a6afc | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 1991 | class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, |
| 1992 | dag oops, dag iops, InstrItinClass itin, string opc, string asm, |
| 1993 | list<dag> pattern> |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 1994 | : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> { |
Johnny Chen | 34a6afc | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 1995 | let Inst{27-23} = opcod1; |
| 1996 | let Inst{21-20} = opcod2; |
| 1997 | let Inst{19-16} = opcod3; |
| 1998 | let Inst{11-8} = opcod4; |
Evan Cheng | 4b6c7ef | 2008-11-12 06:41:41 +0000 | [diff] [blame] | 1999 | let Inst{6} = 1; |
Johnny Chen | 34a6afc | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 2000 | let Inst{4} = 0; |
Evan Cheng | 4b6c7ef | 2008-11-12 06:41:41 +0000 | [diff] [blame] | 2001 | } |
| 2002 | |
Johnny Chen | 3964059 | 2010-02-11 18:47:03 +0000 | [diff] [blame] | 2003 | // VFP conversion between floating-point and fixed-point |
| 2004 | class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 2005 | dag oops, dag iops, InstrItinClass itin, string opc, string asm, |
| 2006 | list<dag> pattern> |
Johnny Chen | 3964059 | 2010-02-11 18:47:03 +0000 | [diff] [blame] | 2007 | : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { |
Jim Grosbach | f0d2511 | 2011-12-22 19:55:21 +0000 | [diff] [blame] | 2008 | bits<5> fbits; |
Johnny Chen | 3964059 | 2010-02-11 18:47:03 +0000 | [diff] [blame] | 2009 | // size (fixed-point number): sx == 0 ? 16 : 32 |
| 2010 | let Inst{7} = op5; // sx |
Jim Grosbach | f0d2511 | 2011-12-22 19:55:21 +0000 | [diff] [blame] | 2011 | let Inst{5} = fbits{0}; |
| 2012 | let Inst{3-0} = fbits{4-1}; |
Johnny Chen | 3964059 | 2010-02-11 18:47:03 +0000 | [diff] [blame] | 2013 | } |
| 2014 | |
David Goodwin | 85b5b02 | 2009-08-10 22:17:39 +0000 | [diff] [blame] | 2015 | // VFP conversion instructions, if no NEON |
Johnny Chen | 34a6afc | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 2016 | class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, |
David Goodwin | 85b5b02 | 2009-08-10 22:17:39 +0000 | [diff] [blame] | 2017 | dag oops, dag iops, InstrItinClass itin, |
| 2018 | string opc, string asm, list<dag> pattern> |
Johnny Chen | 34a6afc | 2010-01-29 23:21:10 +0000 | [diff] [blame] | 2019 | : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, |
| 2020 | pattern> { |
David Goodwin | 85b5b02 | 2009-08-10 22:17:39 +0000 | [diff] [blame] | 2021 | list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; |
| 2022 | } |
| 2023 | |
Evan Cheng | 4b6c7ef | 2008-11-12 06:41:41 +0000 | [diff] [blame] | 2024 | class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 2025 | InstrItinClass itin, |
| 2026 | string opc, string asm, list<dag> pattern> |
| 2027 | : VFPAI<oops, iops, f, itin, opc, asm, pattern> { |
Evan Cheng | 4b6c7ef | 2008-11-12 06:41:41 +0000 | [diff] [blame] | 2028 | let Inst{27-20} = opcod1; |
Evan Cheng | 38c9a14 | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 2029 | let Inst{11-8} = opcod2; |
| 2030 | let Inst{4} = 1; |
| 2031 | } |
| 2032 | |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 2033 | class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, |
| 2034 | InstrItinClass itin, string opc, string asm, list<dag> pattern> |
| 2035 | : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>; |
Evan Cheng | 97ccab8 | 2008-11-11 22:46:12 +0000 | [diff] [blame] | 2036 | |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 2037 | class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 2038 | InstrItinClass itin, string opc, string asm, list<dag> pattern> |
| 2039 | : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>; |
Evan Cheng | 4b6c7ef | 2008-11-12 06:41:41 +0000 | [diff] [blame] | 2040 | |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 2041 | class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, |
| 2042 | InstrItinClass itin, string opc, string asm, list<dag> pattern> |
| 2043 | : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>; |
Evan Cheng | 4b6c7ef | 2008-11-12 06:41:41 +0000 | [diff] [blame] | 2044 | |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 2045 | class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, |
| 2046 | InstrItinClass itin, string opc, string asm, list<dag> pattern> |
| 2047 | : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>; |
Evan Cheng | 38c9a14 | 2008-11-11 19:40:26 +0000 | [diff] [blame] | 2048 | |
Evan Cheng | ac2af2f | 2008-11-11 02:11:05 +0000 | [diff] [blame] | 2049 | //===----------------------------------------------------------------------===// |
| 2050 | |
Bob Wilson | 2e076c4 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2051 | //===----------------------------------------------------------------------===// |
| 2052 | // ARM NEON Instruction templates. |
| 2053 | // |
Evan Cheng | ee98fa9 | 2008-08-29 06:41:12 +0000 | [diff] [blame] | 2054 | |
Johnny Chen | f833fad | 2010-03-20 00:17:00 +0000 | [diff] [blame] | 2055 | class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, |
| 2056 | InstrItinClass itin, string opc, string dt, string asm, string cstr, |
| 2057 | list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 2058 | : InstARM<am, 4, im, f, NeonDomain, cstr, itin> { |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2059 | let OutOperandList = oops; |
Chris Lattner | fb2ceed | 2010-03-18 21:06:54 +0000 | [diff] [blame] | 2060 | let InOperandList = !con(iops, (ins pred:$p)); |
Chris Lattner | 04c342e | 2010-10-06 00:05:18 +0000 | [diff] [blame] | 2061 | let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2062 | let Pattern = pattern; |
| 2063 | list<Predicate> Predicates = [HasNEON]; |
Owen Anderson | a6201f0 | 2011-08-15 23:38:54 +0000 | [diff] [blame] | 2064 | let DecoderNamespace = "NEON"; |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2065 | } |
| 2066 | |
| 2067 | // Same as NeonI except it does not have a "data type" specifier. |
Johnny Chen | 020023a | 2010-03-23 20:40:44 +0000 | [diff] [blame] | 2068 | class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, |
| 2069 | InstrItinClass itin, string opc, string asm, string cstr, |
| 2070 | list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 2071 | : InstARM<am, 4, im, f, NeonDomain, cstr, itin> { |
Bob Wilson | 2e076c4 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2072 | let OutOperandList = oops; |
Chris Lattner | fb2ceed | 2010-03-18 21:06:54 +0000 | [diff] [blame] | 2073 | let InOperandList = !con(iops, (ins pred:$p)); |
Chris Lattner | 04c342e | 2010-10-06 00:05:18 +0000 | [diff] [blame] | 2074 | let AsmString = !strconcat(opc, "${p}", "\t", asm); |
Bob Wilson | 2e076c4 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2075 | let Pattern = pattern; |
| 2076 | list<Predicate> Predicates = [HasNEON]; |
Owen Anderson | a6201f0 | 2011-08-15 23:38:54 +0000 | [diff] [blame] | 2077 | let DecoderNamespace = "NEON"; |
Evan Cheng | ee98fa9 | 2008-08-29 06:41:12 +0000 | [diff] [blame] | 2078 | } |
| 2079 | |
Joey Gouly | df68600 | 2013-07-17 13:59:38 +0000 | [diff] [blame] | 2080 | // Same as NeonI except it is not predicated |
| 2081 | class NeonInp<dag oops, dag iops, AddrMode am, IndexMode im, Format f, |
| 2082 | InstrItinClass itin, string opc, string dt, string asm, string cstr, |
| 2083 | list<dag> pattern> |
| 2084 | : InstARM<am, 4, im, f, NeonDomain, cstr, itin> { |
| 2085 | let OutOperandList = oops; |
| 2086 | let InOperandList = iops; |
| 2087 | let AsmString = !strconcat(opc, ".", dt, "\t", asm); |
| 2088 | let Pattern = pattern; |
| 2089 | list<Predicate> Predicates = [HasNEON]; |
| 2090 | let DecoderNamespace = "NEON"; |
| 2091 | |
| 2092 | let Inst{31-28} = 0b1111; |
| 2093 | } |
| 2094 | |
Bob Wilson | 50820a2 | 2009-10-07 21:53:04 +0000 | [diff] [blame] | 2095 | class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, |
| 2096 | dag oops, dag iops, InstrItinClass itin, |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2097 | string opc, string dt, string asm, string cstr, list<dag> pattern> |
Johnny Chen | f833fad | 2010-03-20 00:17:00 +0000 | [diff] [blame] | 2098 | : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm, |
| 2099 | cstr, pattern> { |
Bob Wilson | f731a2d | 2009-07-08 18:11:30 +0000 | [diff] [blame] | 2100 | let Inst{31-24} = 0b11110100; |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 2101 | let Inst{23} = op23; |
Jim Grosbach | 68f495c | 2009-10-20 00:19:08 +0000 | [diff] [blame] | 2102 | let Inst{21-20} = op21_20; |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 2103 | let Inst{11-8} = op11_8; |
| 2104 | let Inst{7-4} = op7_4; |
Jim Grosbach | 5876e41 | 2010-11-19 22:42:55 +0000 | [diff] [blame] | 2105 | |
Chris Lattner | 63274cb | 2010-11-15 05:19:05 +0000 | [diff] [blame] | 2106 | let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder"; |
Owen Anderson | c86a5bd | 2011-08-10 19:01:10 +0000 | [diff] [blame] | 2107 | let DecoderNamespace = "NEONLoadStore"; |
Jim Grosbach | 5876e41 | 2010-11-19 22:42:55 +0000 | [diff] [blame] | 2108 | |
Owen Anderson | ad40234 | 2010-11-02 00:05:05 +0000 | [diff] [blame] | 2109 | bits<5> Vd; |
Owen Anderson | 0ebd1fd | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2110 | bits<6> Rn; |
| 2111 | bits<4> Rm; |
Jim Grosbach | 5876e41 | 2010-11-19 22:42:55 +0000 | [diff] [blame] | 2112 | |
Owen Anderson | ad40234 | 2010-11-02 00:05:05 +0000 | [diff] [blame] | 2113 | let Inst{22} = Vd{4}; |
| 2114 | let Inst{15-12} = Vd{3-0}; |
Owen Anderson | 0ebd1fd | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2115 | let Inst{19-16} = Rn{3-0}; |
| 2116 | let Inst{3-0} = Rm{3-0}; |
Bob Wilson | f731a2d | 2009-07-08 18:11:30 +0000 | [diff] [blame] | 2117 | } |
| 2118 | |
Owen Anderson | 9f20daf | 2010-11-02 20:47:39 +0000 | [diff] [blame] | 2119 | class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, |
| 2120 | dag oops, dag iops, InstrItinClass itin, |
| 2121 | string opc, string dt, string asm, string cstr, list<dag> pattern> |
| 2122 | : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc, |
| 2123 | dt, asm, cstr, pattern> { |
| 2124 | bits<3> lane; |
| 2125 | } |
| 2126 | |
Bob Wilson | 9392b0e | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 2127 | class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 2128 | : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr, |
Bob Wilson | 9392b0e | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 2129 | itin> { |
| 2130 | let OutOperandList = oops; |
| 2131 | let InOperandList = !con(iops, (ins pred:$p)); |
| 2132 | list<Predicate> Predicates = [HasNEON]; |
| 2133 | } |
| 2134 | |
Jim Grosbach | 233b3a2 | 2010-10-06 20:36:55 +0000 | [diff] [blame] | 2135 | class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr, |
| 2136 | list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 2137 | : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr, |
Bob Wilson | c597fd3b | 2010-09-13 23:55:10 +0000 | [diff] [blame] | 2138 | itin> { |
| 2139 | let OutOperandList = oops; |
| 2140 | let InOperandList = !con(iops, (ins pred:$p)); |
Jim Grosbach | 233b3a2 | 2010-10-06 20:36:55 +0000 | [diff] [blame] | 2141 | let Pattern = pattern; |
Bob Wilson | c597fd3b | 2010-09-13 23:55:10 +0000 | [diff] [blame] | 2142 | list<Predicate> Predicates = [HasNEON]; |
| 2143 | } |
| 2144 | |
Johnny Chen | ac5024b | 2010-03-23 16:43:47 +0000 | [diff] [blame] | 2145 | class NDataI<dag oops, dag iops, Format f, InstrItinClass itin, |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2146 | string opc, string dt, string asm, string cstr, list<dag> pattern> |
Johnny Chen | ac5024b | 2010-03-23 16:43:47 +0000 | [diff] [blame] | 2147 | : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr, |
| 2148 | pattern> { |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2149 | let Inst{31-25} = 0b1111001; |
Chris Lattner | 63274cb | 2010-11-15 05:19:05 +0000 | [diff] [blame] | 2150 | let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; |
Owen Anderson | a6201f0 | 2011-08-15 23:38:54 +0000 | [diff] [blame] | 2151 | let DecoderNamespace = "NEONData"; |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2152 | } |
| 2153 | |
Johnny Chen | 020023a | 2010-03-23 20:40:44 +0000 | [diff] [blame] | 2154 | class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin, |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 2155 | string opc, string asm, string cstr, list<dag> pattern> |
Johnny Chen | 020023a | 2010-03-23 20:40:44 +0000 | [diff] [blame] | 2156 | : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm, |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 2157 | cstr, pattern> { |
Bob Wilson | 2e076c4 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2158 | let Inst{31-25} = 0b1111001; |
Owen Anderson | b538a22 | 2010-12-10 22:32:08 +0000 | [diff] [blame] | 2159 | let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; |
Owen Anderson | a6201f0 | 2011-08-15 23:38:54 +0000 | [diff] [blame] | 2160 | let DecoderNamespace = "NEONData"; |
Bob Wilson | 2e076c4 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2161 | } |
| 2162 | |
| 2163 | // NEON "one register and a modified immediate" format. |
| 2164 | class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, |
| 2165 | bit op5, bit op4, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 2166 | dag oops, dag iops, InstrItinClass itin, |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 2167 | string opc, string dt, string asm, string cstr, |
| 2168 | list<dag> pattern> |
Johnny Chen | 6a64320 | 2010-03-23 23:09:14 +0000 | [diff] [blame] | 2169 | : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> { |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 2170 | let Inst{23} = op23; |
Bob Wilson | 2e076c4 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2171 | let Inst{21-19} = op21_19; |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 2172 | let Inst{11-8} = op11_8; |
| 2173 | let Inst{7} = op7; |
| 2174 | let Inst{6} = op6; |
| 2175 | let Inst{5} = op5; |
| 2176 | let Inst{4} = op4; |
Jim Grosbach | 5876e41 | 2010-11-19 22:42:55 +0000 | [diff] [blame] | 2177 | |
Owen Anderson | 284cb36 | 2010-10-26 17:40:54 +0000 | [diff] [blame] | 2178 | // Instruction operands. |
| 2179 | bits<5> Vd; |
| 2180 | bits<13> SIMM; |
Jim Grosbach | 5876e41 | 2010-11-19 22:42:55 +0000 | [diff] [blame] | 2181 | |
Owen Anderson | 284cb36 | 2010-10-26 17:40:54 +0000 | [diff] [blame] | 2182 | let Inst{15-12} = Vd{3-0}; |
| 2183 | let Inst{22} = Vd{4}; |
| 2184 | let Inst{24} = SIMM{7}; |
| 2185 | let Inst{18-16} = SIMM{6-4}; |
| 2186 | let Inst{3-0} = SIMM{3-0}; |
Owen Anderson | e0152a7 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 2187 | let DecoderMethod = "DecodeNEONModImmInstruction"; |
Bob Wilson | 2e076c4 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2188 | } |
| 2189 | |
| 2190 | // NEON 2 vector register format. |
| 2191 | class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, |
| 2192 | bits<5> op11_7, bit op6, bit op4, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 2193 | dag oops, dag iops, InstrItinClass itin, |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2194 | string opc, string dt, string asm, string cstr, list<dag> pattern> |
Johnny Chen | 9b1f60a | 2010-03-24 00:57:50 +0000 | [diff] [blame] | 2195 | : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> { |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2196 | let Inst{24-23} = op24_23; |
| 2197 | let Inst{21-20} = op21_20; |
| 2198 | let Inst{19-18} = op19_18; |
| 2199 | let Inst{17-16} = op17_16; |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 2200 | let Inst{11-7} = op11_7; |
| 2201 | let Inst{6} = op6; |
| 2202 | let Inst{4} = op4; |
Jim Grosbach | 5876e41 | 2010-11-19 22:42:55 +0000 | [diff] [blame] | 2203 | |
Owen Anderson | 2477446 | 2010-10-25 18:43:52 +0000 | [diff] [blame] | 2204 | // Instruction operands. |
| 2205 | bits<5> Vd; |
| 2206 | bits<5> Vm; |
| 2207 | |
| 2208 | let Inst{15-12} = Vd{3-0}; |
| 2209 | let Inst{22} = Vd{4}; |
| 2210 | let Inst{3-0} = Vm{3-0}; |
| 2211 | let Inst{5} = Vm{4}; |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2212 | } |
| 2213 | |
Joey Gouly | 943dd59 | 2013-07-18 11:53:22 +0000 | [diff] [blame] | 2214 | // Same as N2V but not predicated. |
Amara Emerson | 3308909 | 2013-09-19 11:59:01 +0000 | [diff] [blame] | 2215 | class N2Vnp<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6, |
Joey Gouly | 943dd59 | 2013-07-18 11:53:22 +0000 | [diff] [blame] | 2216 | dag oops, dag iops, InstrItinClass itin, string OpcodeStr, |
Tim Northover | 6ad1f5c | 2014-04-28 13:53:00 +0000 | [diff] [blame] | 2217 | string Dt, list<dag> pattern> |
Joey Gouly | 943dd59 | 2013-07-18 11:53:22 +0000 | [diff] [blame] | 2218 | : NeonInp<oops, iops, AddrModeNone, IndexModeNone, N2RegFrm, itin, |
| 2219 | OpcodeStr, Dt, "$Vd, $Vm", "", pattern> { |
| 2220 | bits<5> Vd; |
| 2221 | bits<5> Vm; |
| 2222 | |
| 2223 | // Encode instruction operands |
| 2224 | let Inst{22} = Vd{4}; |
| 2225 | let Inst{15-12} = Vd{3-0}; |
| 2226 | let Inst{5} = Vm{4}; |
| 2227 | let Inst{3-0} = Vm{3-0}; |
| 2228 | |
| 2229 | // Encode constant bits |
| 2230 | let Inst{27-23} = 0b00111; |
| 2231 | let Inst{21-20} = 0b11; |
Amara Emerson | 3308909 | 2013-09-19 11:59:01 +0000 | [diff] [blame] | 2232 | let Inst{19-18} = op19_18; |
Joey Gouly | 943dd59 | 2013-07-18 11:53:22 +0000 | [diff] [blame] | 2233 | let Inst{17-16} = op17_16; |
| 2234 | let Inst{11} = 0; |
| 2235 | let Inst{10-8} = op10_8; |
| 2236 | let Inst{7} = op7; |
| 2237 | let Inst{6} = op6; |
| 2238 | let Inst{4} = 0; |
| 2239 | |
| 2240 | let DecoderNamespace = "NEON"; |
| 2241 | } |
| 2242 | |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2243 | // Same as N2V except it doesn't have a datatype suffix. |
| 2244 | class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 2245 | bits<5> op11_7, bit op6, bit op4, |
| 2246 | dag oops, dag iops, InstrItinClass itin, |
| 2247 | string opc, string asm, string cstr, list<dag> pattern> |
Johnny Chen | 9b1f60a | 2010-03-24 00:57:50 +0000 | [diff] [blame] | 2248 | : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> { |
Bob Wilson | 2e076c4 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2249 | let Inst{24-23} = op24_23; |
| 2250 | let Inst{21-20} = op21_20; |
| 2251 | let Inst{19-18} = op19_18; |
| 2252 | let Inst{17-16} = op17_16; |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 2253 | let Inst{11-7} = op11_7; |
| 2254 | let Inst{6} = op6; |
| 2255 | let Inst{4} = op4; |
Jim Grosbach | 5876e41 | 2010-11-19 22:42:55 +0000 | [diff] [blame] | 2256 | |
Owen Anderson | 2477446 | 2010-10-25 18:43:52 +0000 | [diff] [blame] | 2257 | // Instruction operands. |
| 2258 | bits<5> Vd; |
| 2259 | bits<5> Vm; |
| 2260 | |
| 2261 | let Inst{15-12} = Vd{3-0}; |
| 2262 | let Inst{22} = Vd{4}; |
| 2263 | let Inst{3-0} = Vm{3-0}; |
| 2264 | let Inst{5} = Vm{4}; |
Bob Wilson | 2e076c4 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2265 | } |
| 2266 | |
| 2267 | // NEON 2 vector register with immediate. |
Bob Wilson | bd3650c | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 2268 | class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, |
Johnny Chen | d82f900 | 2010-03-25 20:39:04 +0000 | [diff] [blame] | 2269 | dag oops, dag iops, Format f, InstrItinClass itin, |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2270 | string opc, string dt, string asm, string cstr, list<dag> pattern> |
Johnny Chen | d82f900 | 2010-03-25 20:39:04 +0000 | [diff] [blame] | 2271 | : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 2272 | let Inst{24} = op24; |
| 2273 | let Inst{23} = op23; |
Bob Wilson | 2e076c4 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2274 | let Inst{11-8} = op11_8; |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 2275 | let Inst{7} = op7; |
| 2276 | let Inst{6} = op6; |
| 2277 | let Inst{4} = op4; |
Jim Grosbach | 5876e41 | 2010-11-19 22:42:55 +0000 | [diff] [blame] | 2278 | |
Owen Anderson | 3665fee | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 2279 | // Instruction operands. |
| 2280 | bits<5> Vd; |
| 2281 | bits<5> Vm; |
| 2282 | bits<6> SIMM; |
| 2283 | |
| 2284 | let Inst{15-12} = Vd{3-0}; |
| 2285 | let Inst{22} = Vd{4}; |
| 2286 | let Inst{3-0} = Vm{3-0}; |
| 2287 | let Inst{5} = Vm{4}; |
| 2288 | let Inst{21-16} = SIMM{5-0}; |
Bob Wilson | 2e076c4 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2289 | } |
| 2290 | |
Bob Wilson | cf603fb | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2291 | // NEON 3 vector register format. |
Owen Anderson | abda3ca | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2292 | |
Jim Grosbach | eca54e4 | 2011-05-19 17:34:53 +0000 | [diff] [blame] | 2293 | class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, |
| 2294 | bit op4, dag oops, dag iops, Format f, InstrItinClass itin, |
| 2295 | string opc, string dt, string asm, string cstr, |
| 2296 | list<dag> pattern> |
Johnny Chen | 2cf0495 | 2010-03-26 21:26:28 +0000 | [diff] [blame] | 2297 | : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 2298 | let Inst{24} = op24; |
| 2299 | let Inst{23} = op23; |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2300 | let Inst{21-20} = op21_20; |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 2301 | let Inst{11-8} = op11_8; |
| 2302 | let Inst{6} = op6; |
| 2303 | let Inst{4} = op4; |
Owen Anderson | abda3ca | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2304 | } |
| 2305 | |
| 2306 | class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, |
| 2307 | dag oops, dag iops, Format f, InstrItinClass itin, |
| 2308 | string opc, string dt, string asm, string cstr, list<dag> pattern> |
| 2309 | : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, |
| 2310 | oops, iops, f, itin, opc, dt, asm, cstr, pattern> { |
Owen Anderson | 9e44cf2 | 2010-10-21 20:21:49 +0000 | [diff] [blame] | 2311 | // Instruction operands. |
| 2312 | bits<5> Vd; |
| 2313 | bits<5> Vn; |
| 2314 | bits<5> Vm; |
| 2315 | |
| 2316 | let Inst{15-12} = Vd{3-0}; |
| 2317 | let Inst{22} = Vd{4}; |
| 2318 | let Inst{19-16} = Vn{3-0}; |
| 2319 | let Inst{7} = Vn{4}; |
| 2320 | let Inst{3-0} = Vm{3-0}; |
| 2321 | let Inst{5} = Vm{4}; |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2322 | } |
| 2323 | |
Joey Gouly | df68600 | 2013-07-17 13:59:38 +0000 | [diff] [blame] | 2324 | class N3Vnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6, |
| 2325 | bit op4, dag oops, dag iops,Format f, InstrItinClass itin, |
Tim Northover | 6ad1f5c | 2014-04-28 13:53:00 +0000 | [diff] [blame] | 2326 | string OpcodeStr, string Dt, list<dag> pattern> |
Joey Gouly | df68600 | 2013-07-17 13:59:38 +0000 | [diff] [blame] | 2327 | : NeonInp<oops, iops, AddrModeNone, IndexModeNone, f, itin, OpcodeStr, |
| 2328 | Dt, "$Vd, $Vn, $Vm", "", pattern> { |
| 2329 | bits<5> Vd; |
| 2330 | bits<5> Vn; |
| 2331 | bits<5> Vm; |
| 2332 | |
| 2333 | // Encode instruction operands |
| 2334 | let Inst{22} = Vd{4}; |
| 2335 | let Inst{15-12} = Vd{3-0}; |
| 2336 | let Inst{19-16} = Vn{3-0}; |
| 2337 | let Inst{7} = Vn{4}; |
| 2338 | let Inst{5} = Vm{4}; |
| 2339 | let Inst{3-0} = Vm{3-0}; |
| 2340 | |
| 2341 | // Encode constant bits |
| 2342 | let Inst{27-23} = op27_23; |
| 2343 | let Inst{21-20} = op21_20; |
| 2344 | let Inst{11-8} = op11_8; |
| 2345 | let Inst{6} = op6; |
| 2346 | let Inst{4} = op4; |
| 2347 | } |
| 2348 | |
Jim Grosbach | eca54e4 | 2011-05-19 17:34:53 +0000 | [diff] [blame] | 2349 | class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, |
| 2350 | bit op4, dag oops, dag iops, Format f, InstrItinClass itin, |
| 2351 | string opc, string dt, string asm, string cstr, |
| 2352 | list<dag> pattern> |
Owen Anderson | abda3ca | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2353 | : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, |
| 2354 | oops, iops, f, itin, opc, dt, asm, cstr, pattern> { |
| 2355 | |
| 2356 | // Instruction operands. |
| 2357 | bits<5> Vd; |
| 2358 | bits<5> Vn; |
| 2359 | bits<5> Vm; |
| 2360 | bit lane; |
| 2361 | |
| 2362 | let Inst{15-12} = Vd{3-0}; |
| 2363 | let Inst{22} = Vd{4}; |
| 2364 | let Inst{19-16} = Vn{3-0}; |
| 2365 | let Inst{7} = Vn{4}; |
| 2366 | let Inst{3-0} = Vm{3-0}; |
| 2367 | let Inst{5} = lane; |
| 2368 | } |
| 2369 | |
Jim Grosbach | eca54e4 | 2011-05-19 17:34:53 +0000 | [diff] [blame] | 2370 | class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, |
| 2371 | bit op4, dag oops, dag iops, Format f, InstrItinClass itin, |
| 2372 | string opc, string dt, string asm, string cstr, |
| 2373 | list<dag> pattern> |
Owen Anderson | abda3ca | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2374 | : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, |
| 2375 | oops, iops, f, itin, opc, dt, asm, cstr, pattern> { |
| 2376 | |
| 2377 | // Instruction operands. |
| 2378 | bits<5> Vd; |
| 2379 | bits<5> Vn; |
| 2380 | bits<5> Vm; |
| 2381 | bits<2> lane; |
| 2382 | |
| 2383 | let Inst{15-12} = Vd{3-0}; |
| 2384 | let Inst{22} = Vd{4}; |
| 2385 | let Inst{19-16} = Vn{3-0}; |
| 2386 | let Inst{7} = Vn{4}; |
| 2387 | let Inst{2-0} = Vm{2-0}; |
| 2388 | let Inst{5} = lane{1}; |
| 2389 | let Inst{3} = lane{0}; |
| 2390 | } |
| 2391 | |
Johnny Chen | 8a68723 | 2010-03-23 21:35:03 +0000 | [diff] [blame] | 2392 | // Same as N3V except it doesn't have a data type suffix. |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 2393 | class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, |
| 2394 | bit op4, |
Bob Wilson | cf603fb | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2395 | dag oops, dag iops, Format f, InstrItinClass itin, |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 2396 | string opc, string asm, string cstr, list<dag> pattern> |
Bob Wilson | cf603fb | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2397 | : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> { |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 2398 | let Inst{24} = op24; |
| 2399 | let Inst{23} = op23; |
Bob Wilson | 2e076c4 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2400 | let Inst{21-20} = op21_20; |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 2401 | let Inst{11-8} = op11_8; |
| 2402 | let Inst{6} = op6; |
| 2403 | let Inst{4} = op4; |
Jim Grosbach | 5876e41 | 2010-11-19 22:42:55 +0000 | [diff] [blame] | 2404 | |
Owen Anderson | dff239c | 2010-10-25 18:28:30 +0000 | [diff] [blame] | 2405 | // Instruction operands. |
| 2406 | bits<5> Vd; |
| 2407 | bits<5> Vn; |
| 2408 | bits<5> Vm; |
| 2409 | |
| 2410 | let Inst{15-12} = Vd{3-0}; |
| 2411 | let Inst{22} = Vd{4}; |
| 2412 | let Inst{19-16} = Vn{3-0}; |
| 2413 | let Inst{7} = Vn{4}; |
| 2414 | let Inst{3-0} = Vm{3-0}; |
| 2415 | let Inst{5} = Vm{4}; |
Bob Wilson | 2e076c4 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2416 | } |
| 2417 | |
| 2418 | // NEON VMOVs between scalar and core registers. |
| 2419 | class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 2420 | dag oops, dag iops, Format f, InstrItinClass itin, |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2421 | string opc, string dt, string asm, list<dag> pattern> |
Owen Anderson | 651b230 | 2011-07-13 23:22:26 +0000 | [diff] [blame] | 2422 | : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain, |
Bob Wilson | 3968c6a | 2010-03-23 17:23:59 +0000 | [diff] [blame] | 2423 | "", itin> { |
Bob Wilson | 2e076c4 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2424 | let Inst{27-20} = opcod1; |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 2425 | let Inst{11-8} = opcod2; |
| 2426 | let Inst{6-5} = opcod3; |
| 2427 | let Inst{4} = 1; |
Johnny Chen | 8bca174 | 2011-04-06 18:27:46 +0000 | [diff] [blame] | 2428 | // A8.6.303, A8.6.328, A8.6.329 |
| 2429 | let Inst{3-0} = 0b0000; |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2430 | |
| 2431 | let OutOperandList = oops; |
Chris Lattner | fb2ceed | 2010-03-18 21:06:54 +0000 | [diff] [blame] | 2432 | let InOperandList = !con(iops, (ins pred:$p)); |
Chris Lattner | 04c342e | 2010-10-06 00:05:18 +0000 | [diff] [blame] | 2433 | let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2434 | let Pattern = pattern; |
Bob Wilson | 2e076c4 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2435 | list<Predicate> Predicates = [HasNEON]; |
Jim Grosbach | 5876e41 | 2010-11-19 22:42:55 +0000 | [diff] [blame] | 2436 | |
Chris Lattner | 63274cb | 2010-11-15 05:19:05 +0000 | [diff] [blame] | 2437 | let PostEncoderMethod = "NEONThumb2DupPostEncoder"; |
Owen Anderson | c86a5bd | 2011-08-10 19:01:10 +0000 | [diff] [blame] | 2438 | let DecoderNamespace = "NEONDup"; |
Jim Grosbach | 5876e41 | 2010-11-19 22:42:55 +0000 | [diff] [blame] | 2439 | |
Owen Anderson | ed9652f | 2010-10-27 21:28:09 +0000 | [diff] [blame] | 2440 | bits<5> V; |
| 2441 | bits<4> R; |
Owen Anderson | 40d24a4 | 2010-10-27 19:25:54 +0000 | [diff] [blame] | 2442 | bits<4> p; |
Owen Anderson | ed9652f | 2010-10-27 21:28:09 +0000 | [diff] [blame] | 2443 | bits<4> lane; |
Jim Grosbach | 5876e41 | 2010-11-19 22:42:55 +0000 | [diff] [blame] | 2444 | |
Owen Anderson | 40d24a4 | 2010-10-27 19:25:54 +0000 | [diff] [blame] | 2445 | let Inst{31-28} = p{3-0}; |
Owen Anderson | ed9652f | 2010-10-27 21:28:09 +0000 | [diff] [blame] | 2446 | let Inst{7} = V{4}; |
| 2447 | let Inst{19-16} = V{3-0}; |
| 2448 | let Inst{15-12} = R{3-0}; |
Bob Wilson | 2e076c4 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2449 | } |
| 2450 | class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 2451 | dag oops, dag iops, InstrItinClass itin, |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2452 | string opc, string dt, string asm, list<dag> pattern> |
Bob Wilson | cc386fb | 2010-06-25 23:56:05 +0000 | [diff] [blame] | 2453 | : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin, |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2454 | opc, dt, asm, pattern>; |
Bob Wilson | 2e076c4 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2455 | class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 2456 | dag oops, dag iops, InstrItinClass itin, |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2457 | string opc, string dt, string asm, list<dag> pattern> |
Bob Wilson | cc386fb | 2010-06-25 23:56:05 +0000 | [diff] [blame] | 2458 | : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin, |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2459 | opc, dt, asm, pattern>; |
Bob Wilson | 2e076c4 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2460 | class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, |
David Goodwin | b062c23 | 2009-08-06 16:52:47 +0000 | [diff] [blame] | 2461 | dag oops, dag iops, InstrItinClass itin, |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2462 | string opc, string dt, string asm, list<dag> pattern> |
Bob Wilson | cc386fb | 2010-06-25 23:56:05 +0000 | [diff] [blame] | 2463 | : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin, |
Evan Cheng | 738a97a | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2464 | opc, dt, asm, pattern>; |
David Goodwin | 3b9c52c | 2009-08-04 17:53:06 +0000 | [diff] [blame] | 2465 | |
Johnny Chen | 45ab3f3 | 2010-03-25 17:01:27 +0000 | [diff] [blame] | 2466 | // Vector Duplicate Lane (from scalar to all elements) |
| 2467 | class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops, |
| 2468 | InstrItinClass itin, string opc, string dt, string asm, |
| 2469 | list<dag> pattern> |
Johnny Chen | 91d2774 | 2010-03-25 21:49:12 +0000 | [diff] [blame] | 2470 | : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> { |
Johnny Chen | 45ab3f3 | 2010-03-25 17:01:27 +0000 | [diff] [blame] | 2471 | let Inst{24-23} = 0b11; |
| 2472 | let Inst{21-20} = 0b11; |
| 2473 | let Inst{19-16} = op19_16; |
Bill Wendling | b70dc87 | 2010-08-31 07:50:46 +0000 | [diff] [blame] | 2474 | let Inst{11-7} = 0b11000; |
| 2475 | let Inst{6} = op6; |
| 2476 | let Inst{4} = 0; |
Jim Grosbach | 5876e41 | 2010-11-19 22:42:55 +0000 | [diff] [blame] | 2477 | |
Owen Anderson | 40d24a4 | 2010-10-27 19:25:54 +0000 | [diff] [blame] | 2478 | bits<5> Vd; |
| 2479 | bits<5> Vm; |
Jim Grosbach | 5876e41 | 2010-11-19 22:42:55 +0000 | [diff] [blame] | 2480 | |
Owen Anderson | 40d24a4 | 2010-10-27 19:25:54 +0000 | [diff] [blame] | 2481 | let Inst{22} = Vd{4}; |
| 2482 | let Inst{15-12} = Vd{3-0}; |
| 2483 | let Inst{5} = Vm{4}; |
| 2484 | let Inst{3-0} = Vm{3-0}; |
Johnny Chen | 45ab3f3 | 2010-03-25 17:01:27 +0000 | [diff] [blame] | 2485 | } |
| 2486 | |
David Goodwin | 3b9c52c | 2009-08-04 17:53:06 +0000 | [diff] [blame] | 2487 | // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON |
| 2488 | // for single-precision FP. |
| 2489 | class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { |
| 2490 | list<Predicate> Predicates = [HasNEON,UseNEONForFP]; |
| 2491 | } |
Jim Grosbach | 7996b15 | 2011-11-14 22:28:39 +0000 | [diff] [blame] | 2492 | |
| 2493 | // VFP/NEON Instruction aliases for type suffices. |
Sjoerd Meijer | 9da258d | 2016-06-03 13:19:43 +0000 | [diff] [blame] | 2494 | // Note: When EmitPriority == 1, the alias will be used for printing |
| 2495 | class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result, bit EmitPriority = 0> : |
| 2496 | InstAlias<!strconcat(opc, dt, "\t", asm), Result, EmitPriority>, Requires<[HasVFP2]>; |
Jim Grosbach | 2cf294a | 2011-12-07 01:50:36 +0000 | [diff] [blame] | 2497 | |
Sjoerd Meijer | 9da258d | 2016-06-03 13:19:43 +0000 | [diff] [blame] | 2498 | // Note: When EmitPriority == 1, the alias will be used for printing |
| 2499 | multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result, bit EmitPriority = 0> { |
| 2500 | def : VFPDataTypeInstAlias<opc, ".8", asm, Result, EmitPriority>; |
| 2501 | def : VFPDataTypeInstAlias<opc, ".16", asm, Result, EmitPriority>; |
| 2502 | def : VFPDataTypeInstAlias<opc, ".32", asm, Result, EmitPriority>; |
| 2503 | def : VFPDataTypeInstAlias<opc, ".64", asm, Result, EmitPriority>; |
Jim Grosbach | e7dcbc8 | 2011-12-02 18:52:30 +0000 | [diff] [blame] | 2504 | } |
| 2505 | |
Sjoerd Meijer | 9da258d | 2016-06-03 13:19:43 +0000 | [diff] [blame] | 2506 | // Note: When EmitPriority == 1, the alias will be used for printing |
| 2507 | multiclass NEONDTAnyInstAlias<string opc, string asm, dag Result, bit EmitPriority = 0> { |
Jim Grosbach | 681db34 | 2012-01-24 17:23:29 +0000 | [diff] [blame] | 2508 | let Predicates = [HasNEON] in { |
Sjoerd Meijer | 9da258d | 2016-06-03 13:19:43 +0000 | [diff] [blame] | 2509 | def : VFPDataTypeInstAlias<opc, ".8", asm, Result, EmitPriority>; |
| 2510 | def : VFPDataTypeInstAlias<opc, ".16", asm, Result, EmitPriority>; |
| 2511 | def : VFPDataTypeInstAlias<opc, ".32", asm, Result, EmitPriority>; |
| 2512 | def : VFPDataTypeInstAlias<opc, ".64", asm, Result, EmitPriority>; |
Jim Grosbach | 681db34 | 2012-01-24 17:23:29 +0000 | [diff] [blame] | 2513 | } |
| 2514 | } |
| 2515 | |
Jim Grosbach | e7dcbc8 | 2011-12-02 18:52:30 +0000 | [diff] [blame] | 2516 | // The same alias classes using AsmPseudo instead, for the more complex |
| 2517 | // stuff in NEON that InstAlias can't quite handle. |
| 2518 | // Note that we can't use anonymous defm references here like we can |
| 2519 | // above, as we care about the ultimate instruction enum names generated, unlike |
| 2520 | // for instalias defs. |
| 2521 | class NEONDataTypeAsmPseudoInst<string opc, string dt, string asm, dag iops> : |
Jim Grosbach | dda976b | 2011-12-02 22:01:52 +0000 | [diff] [blame] | 2522 | AsmPseudoInst<!strconcat(opc, dt, "\t", asm), iops>, Requires<[HasNEON]>; |
Jim Grosbach | 585ce30 | 2011-12-07 01:17:58 +0000 | [diff] [blame] | 2523 | |
Sam Parker | 963da5b | 2017-09-29 13:11:33 +0000 | [diff] [blame] | 2524 | // Extension of NEON 3-vector data processing instructions in coprocessor 8 |
| 2525 | // encoding space, introduced in ARMv8.3-A. |
| 2526 | class N3VCP8<bits<2> op24_23, bits<2> op21_20, bit op6, bit op4, |
| 2527 | dag oops, dag iops, InstrItinClass itin, |
| 2528 | string opc, string dt, string asm, string cstr, list<dag> pattern> |
| 2529 | : NeonInp<oops, iops, AddrModeNone, IndexModeNone, N3RegCplxFrm, itin, opc, |
| 2530 | dt, asm, cstr, pattern> { |
| 2531 | bits<5> Vd; |
| 2532 | bits<5> Vn; |
| 2533 | bits<5> Vm; |
| 2534 | |
| 2535 | let DecoderNamespace = "VFPV8"; |
| 2536 | // These have the same encodings in ARM and Thumb2 |
| 2537 | let PostEncoderMethod = ""; |
| 2538 | |
| 2539 | let Inst{31-25} = 0b1111110; |
| 2540 | let Inst{24-23} = op24_23; |
| 2541 | let Inst{22} = Vd{4}; |
| 2542 | let Inst{21-20} = op21_20; |
| 2543 | let Inst{19-16} = Vn{3-0}; |
| 2544 | let Inst{15-12} = Vd{3-0}; |
| 2545 | let Inst{11-8} = 0b1000; |
| 2546 | let Inst{7} = Vn{4}; |
| 2547 | let Inst{6} = op6; |
| 2548 | let Inst{5} = Vm{4}; |
| 2549 | let Inst{4} = op4; |
| 2550 | let Inst{3-0} = Vm{3-0}; |
| 2551 | } |
| 2552 | |
| 2553 | // Extension of NEON 2-vector-and-scalar data processing instructions in |
| 2554 | // coprocessor 8 encoding space, introduced in ARMv8.3-A. |
| 2555 | class N3VLaneCP8<bit op23, bits<2> op21_20, bit op6, bit op4, |
| 2556 | dag oops, dag iops, InstrItinClass itin, |
| 2557 | string opc, string dt, string asm, string cstr, list<dag> pattern> |
| 2558 | : NeonInp<oops, iops, AddrModeNone, IndexModeNone, N3RegCplxFrm, itin, opc, |
| 2559 | dt, asm, cstr, pattern> { |
| 2560 | bits<5> Vd; |
| 2561 | bits<5> Vn; |
| 2562 | bits<5> Vm; |
| 2563 | |
| 2564 | let DecoderNamespace = "VFPV8"; |
| 2565 | // These have the same encodings in ARM and Thumb2 |
| 2566 | let PostEncoderMethod = ""; |
| 2567 | |
| 2568 | let Inst{31-24} = 0b11111110; |
| 2569 | let Inst{23} = op23; |
| 2570 | let Inst{22} = Vd{4}; |
| 2571 | let Inst{21-20} = op21_20; |
| 2572 | let Inst{19-16} = Vn{3-0}; |
| 2573 | let Inst{15-12} = Vd{3-0}; |
| 2574 | let Inst{11-8} = 0b1000; |
| 2575 | let Inst{7} = Vn{4}; |
| 2576 | let Inst{6} = op6; |
| 2577 | // Bit 5 set by sub-classes |
| 2578 | let Inst{4} = op4; |
| 2579 | let Inst{3-0} = Vm{3-0}; |
| 2580 | } |
| 2581 | |
| 2582 | // Operand types for complex instructions |
Oliver Stannard | 0d5c792 | 2017-10-03 14:38:52 +0000 | [diff] [blame] | 2583 | class ComplexRotationOperand<int Angle, int Remainder, string Type, string Diag> |
Sam Parker | 963da5b | 2017-09-29 13:11:33 +0000 | [diff] [blame] | 2584 | : AsmOperandClass { |
| 2585 | let PredicateMethod = "isComplexRotation<" # Angle # ", " # Remainder # ">"; |
Oliver Stannard | 0d5c792 | 2017-10-03 14:38:52 +0000 | [diff] [blame] | 2586 | let DiagnosticString = "complex rotation must be " # Diag; |
Sam Parker | 963da5b | 2017-09-29 13:11:33 +0000 | [diff] [blame] | 2587 | let Name = "ComplexRotation" # Type; |
| 2588 | } |
| 2589 | def complexrotateop : Operand<i32> { |
Oliver Stannard | 0d5c792 | 2017-10-03 14:38:52 +0000 | [diff] [blame] | 2590 | let ParserMatchClass = ComplexRotationOperand<90, 0, "Even", "0, 90, 180 or 270">; |
Sam Parker | 963da5b | 2017-09-29 13:11:33 +0000 | [diff] [blame] | 2591 | let PrintMethod = "printComplexRotationOp<90, 0>"; |
| 2592 | } |
| 2593 | def complexrotateopodd : Operand<i32> { |
Oliver Stannard | 0d5c792 | 2017-10-03 14:38:52 +0000 | [diff] [blame] | 2594 | let ParserMatchClass = ComplexRotationOperand<180, 90, "Odd", "90 or 270">; |
Sam Parker | 963da5b | 2017-09-29 13:11:33 +0000 | [diff] [blame] | 2595 | let PrintMethod = "printComplexRotationOp<180, 90>"; |
| 2596 | } |
| 2597 | |
Jim Grosbach | 585ce30 | 2011-12-07 01:17:58 +0000 | [diff] [blame] | 2598 | // Data type suffix token aliases. Implements Table A7-3 in the ARM ARM. |
| 2599 | def : TokenAlias<".s8", ".i8">; |
| 2600 | def : TokenAlias<".u8", ".i8">; |
| 2601 | def : TokenAlias<".s16", ".i16">; |
| 2602 | def : TokenAlias<".u16", ".i16">; |
| 2603 | def : TokenAlias<".s32", ".i32">; |
| 2604 | def : TokenAlias<".u32", ".i32">; |
Jim Grosbach | 2cf294a | 2011-12-07 01:50:36 +0000 | [diff] [blame] | 2605 | def : TokenAlias<".s64", ".i64">; |
| 2606 | def : TokenAlias<".u64", ".i64">; |
Jim Grosbach | 585ce30 | 2011-12-07 01:17:58 +0000 | [diff] [blame] | 2607 | |
| 2608 | def : TokenAlias<".i8", ".8">; |
| 2609 | def : TokenAlias<".i16", ".16">; |
| 2610 | def : TokenAlias<".i32", ".32">; |
Jim Grosbach | 2cf294a | 2011-12-07 01:50:36 +0000 | [diff] [blame] | 2611 | def : TokenAlias<".i64", ".64">; |
Jim Grosbach | 585ce30 | 2011-12-07 01:17:58 +0000 | [diff] [blame] | 2612 | |
| 2613 | def : TokenAlias<".p8", ".8">; |
| 2614 | def : TokenAlias<".p16", ".16">; |
| 2615 | |
| 2616 | def : TokenAlias<".f32", ".32">; |
| 2617 | def : TokenAlias<".f64", ".64">; |
| 2618 | def : TokenAlias<".f", ".f32">; |
| 2619 | def : TokenAlias<".d", ".f64">; |