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Jia Liub22310f2012-02-18 12:03:15 +00001//===-- ARMInstrFormats.td - ARM Instruction Formats -------*- tablegen -*-===//
Bob Wilson3968c6a2010-03-23 17:23:59 +00002//
Evan Cheng2d37f192008-08-28 23:39:26 +00003// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Bob Wilson3968c6a2010-03-23 17:23:59 +00007//
Evan Cheng2d37f192008-08-28 23:39:26 +00008//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11//
12// ARM Instruction Format Definitions.
13//
14
15// Format specifies the encoding used by the instruction. This is part of the
16// ad-hoc solution used to emit machine instruction encodings by our machine
17// code emitter.
Bob Wilson69ba1bc2010-03-17 21:13:43 +000018class Format<bits<6> val> {
19 bits<6> Value = val;
Evan Cheng2d37f192008-08-28 23:39:26 +000020}
21
Evan Chengfabdcce2008-11-13 23:36:57 +000022def Pseudo : Format<0>;
23def MulFrm : Format<1>;
24def BrFrm : Format<2>;
25def BrMiscFrm : Format<3>;
Evan Cheng2d37f192008-08-28 23:39:26 +000026
Evan Chengfabdcce2008-11-13 23:36:57 +000027def DPFrm : Format<4>;
Owen Anderson04912702011-07-21 23:38:37 +000028def DPSoRegRegFrm : Format<5>;
Evan Cheng2d37f192008-08-28 23:39:26 +000029
Evan Chengfabdcce2008-11-13 23:36:57 +000030def LdFrm : Format<6>;
31def StFrm : Format<7>;
32def LdMiscFrm : Format<8>;
33def StMiscFrm : Format<9>;
34def LdStMulFrm : Format<10>;
Evan Cheng2d37f192008-08-28 23:39:26 +000035
Johnny Chen0dab68f2010-03-19 17:39:00 +000036def LdStExFrm : Format<11>;
Jim Grosbach5c4e99f2009-12-11 01:42:04 +000037
Johnny Chen0dab68f2010-03-19 17:39:00 +000038def ArithMiscFrm : Format<12>;
Bob Wilson96649842010-08-11 00:01:18 +000039def SatFrm : Format<13>;
40def ExtFrm : Format<14>;
Evan Cheng8cbbcb12008-11-11 21:48:44 +000041
Bob Wilson96649842010-08-11 00:01:18 +000042def VFPUnaryFrm : Format<15>;
43def VFPBinaryFrm : Format<16>;
44def VFPConv1Frm : Format<17>;
45def VFPConv2Frm : Format<18>;
46def VFPConv3Frm : Format<19>;
47def VFPConv4Frm : Format<20>;
48def VFPConv5Frm : Format<21>;
49def VFPLdStFrm : Format<22>;
50def VFPLdStMulFrm : Format<23>;
51def VFPMiscFrm : Format<24>;
Evan Cheng8cbbcb12008-11-11 21:48:44 +000052
Bob Wilson96649842010-08-11 00:01:18 +000053def ThumbFrm : Format<25>;
54def MiscFrm : Format<26>;
Evan Cheng2d37f192008-08-28 23:39:26 +000055
Bob Wilson96649842010-08-11 00:01:18 +000056def NGetLnFrm : Format<27>;
57def NSetLnFrm : Format<28>;
58def NDupFrm : Format<29>;
59def NLdStFrm : Format<30>;
60def N1RegModImmFrm: Format<31>;
61def N2RegFrm : Format<32>;
62def NVCVTFrm : Format<33>;
63def NVDupLnFrm : Format<34>;
64def N2RegVShLFrm : Format<35>;
65def N2RegVShRFrm : Format<36>;
66def N3RegFrm : Format<37>;
67def N3RegVShFrm : Format<38>;
68def NVExtFrm : Format<39>;
69def NVMulSLFrm : Format<40>;
70def NVTBLFrm : Format<41>;
Owen Anderson04912702011-07-21 23:38:37 +000071def DPSoRegImmFrm : Format<42>;
Sam Parker963da5b2017-09-29 13:11:33 +000072def N3RegCplxFrm : Format<43>;
Johnny Chenf833fad2010-03-20 00:17:00 +000073
Evan Cheng14965762009-07-08 01:46:35 +000074// Misc flags.
75
Bill Wendlingcbb08ca2010-12-01 02:42:55 +000076// The instruction has an Rn register operand.
Evan Cheng14965762009-07-08 01:46:35 +000077// UnaryDP - Indicates this is a unary data processing instruction, i.e.
78// it doesn't have a Rn operand.
79class UnaryDP { bit isUnaryDataProc = 1; }
80
81// Xform16Bit - Indicates this Thumb2 instruction may be transformed into
82// a 16-bit Thumb instruction if certain conditions are met.
83class Xform16Bit { bit canXformTo16Bit = 1; }
Evan Cheng2d37f192008-08-28 23:39:26 +000084
Evan Cheng2d37f192008-08-28 23:39:26 +000085//===----------------------------------------------------------------------===//
Bob Wilsona4d86b62010-03-18 23:57:57 +000086// ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
Evan Chengb23b50d2009-06-29 07:51:04 +000087//
88
Jim Grosbachec86bac2011-01-18 19:59:19 +000089// FIXME: Once the JIT is MC-ized, these can go away.
Evan Chengb23b50d2009-06-29 07:51:04 +000090// Addressing mode.
Jim Grosbache9298992010-10-05 18:14:55 +000091class AddrMode<bits<5> val> {
92 bits<5> Value = val;
Evan Chengb23b50d2009-06-29 07:51:04 +000093}
Bill Wendlingb70dc872010-08-31 07:50:46 +000094def AddrModeNone : AddrMode<0>;
95def AddrMode1 : AddrMode<1>;
96def AddrMode2 : AddrMode<2>;
97def AddrMode3 : AddrMode<3>;
98def AddrMode4 : AddrMode<4>;
99def AddrMode5 : AddrMode<5>;
100def AddrMode6 : AddrMode<6>;
101def AddrModeT1_1 : AddrMode<7>;
102def AddrModeT1_2 : AddrMode<8>;
103def AddrModeT1_4 : AddrMode<9>;
104def AddrModeT1_s : AddrMode<10>;
105def AddrModeT2_i12 : AddrMode<11>;
106def AddrModeT2_i8 : AddrMode<12>;
107def AddrModeT2_so : AddrMode<13>;
108def AddrModeT2_pc : AddrMode<14>;
Bob Wilsondeb35af2009-07-01 23:16:05 +0000109def AddrModeT2_i8s4 : AddrMode<15>;
Jim Grosbach1e4d9a12010-10-26 22:37:02 +0000110def AddrMode_i12 : AddrMode<16>;
Sjoerd Meijer011de9c2018-01-26 09:26:40 +0000111def AddrMode5FP16 : AddrMode<17>;
Evan Chengb23b50d2009-06-29 07:51:04 +0000112
Evan Chengb23b50d2009-06-29 07:51:04 +0000113// Load / store index mode.
114class IndexMode<bits<2> val> {
115 bits<2> Value = val;
116}
117def IndexModeNone : IndexMode<0>;
118def IndexModePre : IndexMode<1>;
119def IndexModePost : IndexMode<2>;
Bob Wilsonf1e8f7f2010-03-13 07:34:35 +0000120def IndexModeUpd : IndexMode<3>;
Evan Chengb23b50d2009-06-29 07:51:04 +0000121
Anton Korobeynikov14635da2009-11-02 00:10:38 +0000122// Instruction execution domain.
Evan Cheng04ad35b2011-02-22 19:53:14 +0000123class Domain<bits<3> val> {
124 bits<3> Value = val;
Anton Korobeynikov14635da2009-11-02 00:10:38 +0000125}
126def GenericDomain : Domain<0>;
127def VFPDomain : Domain<1>; // Instructions in VFP domain only
128def NeonDomain : Domain<2>; // Instructions in Neon domain only
129def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
Evan Cheng97e64282011-02-23 02:35:33 +0000130def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8
Anton Korobeynikov14635da2009-11-02 00:10:38 +0000131
Evan Chengb23b50d2009-06-29 07:51:04 +0000132//===----------------------------------------------------------------------===//
Evan Chengcd4cdd12009-07-11 06:43:01 +0000133// ARM special operands.
134//
135
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +0000136// ARM imod and iflag operands, used only by the CPS instruction.
137def imod_op : Operand<i32> {
138 let PrintMethod = "printCPSIMod";
139}
140
Jim Grosbacheeaab222011-07-25 20:38:18 +0000141def ProcIFlagsOperand : AsmOperandClass {
142 let Name = "ProcIFlags";
143 let ParserMethod = "parseProcIFlagsOperand";
144}
Bruno Cardoso Lopes90d1dfe2011-02-14 13:09:44 +0000145def iflags_op : Operand<i32> {
146 let PrintMethod = "printCPSIFlag";
147 let ParserMatchClass = ProcIFlagsOperand;
148}
149
Evan Chengcd4cdd12009-07-11 06:43:01 +0000150// ARM Predicate operand. Default to 14 = always (AL). Second part is CC
151// register whose default is 0 (no register).
Jim Grosbacheeaab222011-07-25 20:38:18 +0000152def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
Jim Grosbachf86cd372011-08-19 20:46:54 +0000153def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
Evan Chengcd4cdd12009-07-11 06:43:01 +0000154 (ops (i32 14), (i32 zero_reg))> {
155 let PrintMethod = "printPredicateOperand";
Daniel Dunbard8042b72010-08-11 06:36:53 +0000156 let ParserMatchClass = CondCodeOperand;
Jim Grosbachdbb60f92011-08-19 20:30:19 +0000157 let DecoderMethod = "DecodePredicateOperand";
Evan Chengcd4cdd12009-07-11 06:43:01 +0000158}
159
Tim Northover42180442013-08-22 09:57:11 +0000160// Selectable predicate operand for CMOV instructions. We can't use a normal
161// predicate because the default values interfere with instruction selection. In
162// all other respects it is identical though: pseudo-instruction expansion
163// relies on the MachineOperands being compatible.
164def cmovpred : Operand<i32>, PredicateOp,
165 ComplexPattern<i32, 2, "SelectCMOVPred"> {
166 let MIOperandInfo = (ops i32imm, i32imm);
167 let PrintMethod = "printPredicateOperand";
168}
169
Evan Chengcd4cdd12009-07-11 06:43:01 +0000170// Conditional code result for instructions whose 's' bit is set, e.g. subs.
Jim Grosbacheeaab222011-07-25 20:38:18 +0000171def CCOutOperand : AsmOperandClass { let Name = "CCOut"; }
Evan Chengcd4cdd12009-07-11 06:43:01 +0000172def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
Chris Lattner63274cb2010-11-15 05:19:05 +0000173 let EncoderMethod = "getCCOutOpValue";
Evan Chengcd4cdd12009-07-11 06:43:01 +0000174 let PrintMethod = "printSBitModifierOperand";
Jim Grosbach0bfb4d52010-12-06 18:21:12 +0000175 let ParserMatchClass = CCOutOperand;
Jim Grosbach9c920492011-08-19 19:41:46 +0000176 let DecoderMethod = "DecodeCCOutOperand";
Evan Chengcd4cdd12009-07-11 06:43:01 +0000177}
178
179// Same as cc_out except it defaults to setting CPSR.
180def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
Chris Lattner63274cb2010-11-15 05:19:05 +0000181 let EncoderMethod = "getCCOutOpValue";
Evan Chengcd4cdd12009-07-11 06:43:01 +0000182 let PrintMethod = "printSBitModifierOperand";
Jim Grosbach0bfb4d52010-12-06 18:21:12 +0000183 let ParserMatchClass = CCOutOperand;
Jim Grosbach9c920492011-08-19 19:41:46 +0000184 let DecoderMethod = "DecodeCCOutOperand";
Evan Chengcd4cdd12009-07-11 06:43:01 +0000185}
186
Johnny Chen9a3e2392010-03-10 18:59:38 +0000187// ARM special operands for disassembly only.
188//
Sjoerd Meijer11794702017-04-03 14:50:04 +0000189def SetEndAsmOperand : ImmAsmOperand<0,1> {
Jim Grosbach0a547702011-07-22 17:44:50 +0000190 let Name = "SetEndImm";
191 let ParserMethod = "parseSetEndImm";
192}
Jim Grosbach7e72ec62010-10-13 21:00:04 +0000193def setend_op : Operand<i32> {
194 let PrintMethod = "printSetendOperand";
Jim Grosbach0a547702011-07-22 17:44:50 +0000195 let ParserMatchClass = SetEndAsmOperand;
Jim Grosbach7e72ec62010-10-13 21:00:04 +0000196}
Johnny Chen9a3e2392010-03-10 18:59:38 +0000197
Jim Grosbacheeaab222011-07-25 20:38:18 +0000198def MSRMaskOperand : AsmOperandClass {
199 let Name = "MSRMask";
200 let ParserMethod = "parseMSRMaskOperand";
201}
Johnny Chen9a3e2392010-03-10 18:59:38 +0000202def msr_mask : Operand<i32> {
203 let PrintMethod = "printMSRMaskOperand";
Owen Anderson60663402011-08-11 20:21:46 +0000204 let DecoderMethod = "DecodeMSRMask";
Bruno Cardoso Lopes9cd43972011-02-18 19:45:59 +0000205 let ParserMatchClass = MSRMaskOperand;
Johnny Chen9a3e2392010-03-10 18:59:38 +0000206}
207
Tim Northoveree843ef2014-08-15 10:47:12 +0000208def BankedRegOperand : AsmOperandClass {
209 let Name = "BankedReg";
210 let ParserMethod = "parseBankedRegOperand";
211}
212def banked_reg : Operand<i32> {
213 let PrintMethod = "printBankedRegOperand";
214 let DecoderMethod = "DecodeBankedReg";
215 let ParserMatchClass = BankedRegOperand;
216}
217
Bill Wendling77ad1dc2011-03-07 23:38:41 +0000218// Shift Right Immediate - A shift right immediate is encoded differently from
219// other shift immediates. The imm6 field is encoded like so:
Bill Wendling3b1459b2011-03-01 01:00:59 +0000220//
Bill Wendling77ad1dc2011-03-07 23:38:41 +0000221// Offset Encoding
222// 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
223// 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
224// 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
225// 64 64 - <imm> is encoded in imm6<5:0>
Sjoerd Meijer11794702017-04-03 14:50:04 +0000226def shr_imm8_asm_operand : ImmAsmOperand<1,8> { let Name = "ShrImm8"; }
Tim Northover170daaf2014-02-10 14:04:07 +0000227def shr_imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 8; }]> {
Bill Wendling77ad1dc2011-03-07 23:38:41 +0000228 let EncoderMethod = "getShiftRight8Imm";
Owen Andersone0152a72011-08-09 20:55:18 +0000229 let DecoderMethod = "DecodeShiftRight8Imm";
Jim Grosbachba7d6ed2011-12-08 22:06:06 +0000230 let ParserMatchClass = shr_imm8_asm_operand;
Bill Wendling3b1459b2011-03-01 01:00:59 +0000231}
Sjoerd Meijer11794702017-04-03 14:50:04 +0000232def shr_imm16_asm_operand : ImmAsmOperand<1,16> { let Name = "ShrImm16"; }
Tim Northover170daaf2014-02-10 14:04:07 +0000233def shr_imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 16; }]> {
Bill Wendling77ad1dc2011-03-07 23:38:41 +0000234 let EncoderMethod = "getShiftRight16Imm";
Owen Andersone0152a72011-08-09 20:55:18 +0000235 let DecoderMethod = "DecodeShiftRight16Imm";
Jim Grosbachba7d6ed2011-12-08 22:06:06 +0000236 let ParserMatchClass = shr_imm16_asm_operand;
Bill Wendling3b1459b2011-03-01 01:00:59 +0000237}
Sjoerd Meijer11794702017-04-03 14:50:04 +0000238def shr_imm32_asm_operand : ImmAsmOperand<1,32> { let Name = "ShrImm32"; }
Tim Northover170daaf2014-02-10 14:04:07 +0000239def shr_imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]> {
Bill Wendling77ad1dc2011-03-07 23:38:41 +0000240 let EncoderMethod = "getShiftRight32Imm";
Owen Andersone0152a72011-08-09 20:55:18 +0000241 let DecoderMethod = "DecodeShiftRight32Imm";
Jim Grosbachba7d6ed2011-12-08 22:06:06 +0000242 let ParserMatchClass = shr_imm32_asm_operand;
Bill Wendling77ad1dc2011-03-07 23:38:41 +0000243}
Sjoerd Meijer11794702017-04-03 14:50:04 +0000244def shr_imm64_asm_operand : ImmAsmOperand<1,64> { let Name = "ShrImm64"; }
Tim Northover170daaf2014-02-10 14:04:07 +0000245def shr_imm64 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 64; }]> {
Bill Wendling77ad1dc2011-03-07 23:38:41 +0000246 let EncoderMethod = "getShiftRight64Imm";
Owen Andersone0152a72011-08-09 20:55:18 +0000247 let DecoderMethod = "DecodeShiftRight64Imm";
Jim Grosbachba7d6ed2011-12-08 22:06:06 +0000248 let ParserMatchClass = shr_imm64_asm_operand;
Bill Wendling3b1459b2011-03-01 01:00:59 +0000249}
250
Renato Golin3f126132016-05-12 21:22:31 +0000251
252// ARM Assembler operand for ldr Rd, =expression which generates an offset
253// to a constant pool entry or a MOV depending on the value of expression
254def const_pool_asm_operand : AsmOperandClass { let Name = "ConstPoolAsmImm"; }
255def const_pool_asm_imm : Operand<i32> {
256 let ParserMatchClass = const_pool_asm_operand;
257}
258
259
Evan Chengcd4cdd12009-07-11 06:43:01 +0000260//===----------------------------------------------------------------------===//
Jim Grosbach6caa5572011-08-22 18:04:24 +0000261// ARM Assembler alias templates.
262//
Sjoerd Meijer9da258d2016-06-03 13:19:43 +0000263// Note: When EmitPriority == 1, the alias will be used for printing
264class ARMInstAlias<string Asm, dag Result, bit EmitPriority = 0>
265 : InstAlias<Asm, Result, EmitPriority>, Requires<[IsARM]>;
Sanne Wouda2409c642017-03-21 14:59:17 +0000266class ARMInstSubst<string Asm, dag Result, bit EmitPriority = 0>
267 : InstAlias<Asm, Result, EmitPriority>,
268 Requires<[IsARM,UseNegativeImmediates]>;
Sjoerd Meijer9da258d2016-06-03 13:19:43 +0000269class tInstAlias<string Asm, dag Result, bit EmitPriority = 0>
270 : InstAlias<Asm, Result, EmitPriority>, Requires<[IsThumb]>;
Sanne Wouda2409c642017-03-21 14:59:17 +0000271class tInstSubst<string Asm, dag Result, bit EmitPriority = 0>
272 : InstAlias<Asm, Result, EmitPriority>,
273 Requires<[IsThumb,UseNegativeImmediates]>;
Sjoerd Meijer9da258d2016-06-03 13:19:43 +0000274class t2InstAlias<string Asm, dag Result, bit EmitPriority = 0>
275 : InstAlias<Asm, Result, EmitPriority>, Requires<[IsThumb2]>;
Sanne Wouda2409c642017-03-21 14:59:17 +0000276class t2InstSubst<string Asm, dag Result, bit EmitPriority = 0>
277 : InstAlias<Asm, Result, EmitPriority>,
278 Requires<[IsThumb2,UseNegativeImmediates]>;
Sjoerd Meijer9da258d2016-06-03 13:19:43 +0000279class VFP2InstAlias<string Asm, dag Result, bit EmitPriority = 0>
280 : InstAlias<Asm, Result, EmitPriority>, Requires<[HasVFP2]>;
281class VFP2DPInstAlias<string Asm, dag Result, bit EmitPriority = 0>
282 : InstAlias<Asm, Result, EmitPriority>, Requires<[HasVFP2,HasDPVFP]>;
283class VFP3InstAlias<string Asm, dag Result, bit EmitPriority = 0>
284 : InstAlias<Asm, Result, EmitPriority>, Requires<[HasVFP3]>;
285class NEONInstAlias<string Asm, dag Result, bit EmitPriority = 0>
286 : InstAlias<Asm, Result, EmitPriority>, Requires<[HasNEON]>;
Jim Grosbach6caa5572011-08-22 18:04:24 +0000287
Jim Grosbach9227f392011-12-13 20:08:32 +0000288
289class VFP2MnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,
290 Requires<[HasVFP2]>;
291class NEONMnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,
292 Requires<[HasNEON]>;
293
Jim Grosbach6caa5572011-08-22 18:04:24 +0000294//===----------------------------------------------------------------------===//
Evan Cheng2d37f192008-08-28 23:39:26 +0000295// ARM Instruction templates.
296//
297
Jim Grosbach6caa5572011-08-22 18:04:24 +0000298
Owen Anderson651b2302011-07-13 23:22:26 +0000299class InstTemplate<AddrMode am, int sz, IndexMode im,
Johnny Chenc28e6292009-12-15 17:24:14 +0000300 Format f, Domain d, string cstr, InstrItinClass itin>
Evan Cheng2d37f192008-08-28 23:39:26 +0000301 : Instruction {
302 let Namespace = "ARM";
303
Evan Cheng2d37f192008-08-28 23:39:26 +0000304 AddrMode AM = am;
Owen Anderson651b2302011-07-13 23:22:26 +0000305 int Size = sz;
Evan Cheng2d37f192008-08-28 23:39:26 +0000306 IndexMode IM = im;
307 bits<2> IndexModeBits = IM.Value;
Evan Cheng2d37f192008-08-28 23:39:26 +0000308 Format F = f;
Bob Wilson69ba1bc2010-03-17 21:13:43 +0000309 bits<6> Form = F.Value;
Anton Korobeynikov14635da2009-11-02 00:10:38 +0000310 Domain D = d;
Evan Cheng81889d012008-11-05 18:35:52 +0000311 bit isUnaryDataProc = 0;
Evan Cheng14965762009-07-08 01:46:35 +0000312 bit canXformTo16Bit = 0;
Jim Grosbach3e941ae2011-08-16 20:45:50 +0000313 // The instruction is a 16-bit flag setting Thumb instruction. Used
314 // by the parser to determine whether to require the 'S' suffix on the
315 // mnemonic (when not in an IT block) or preclude it (when in an IT block).
316 bit thumbArithFlagSetting = 0;
Jim Grosbach5876e412010-11-19 22:42:55 +0000317
Chris Lattner7ff33462010-10-31 19:22:57 +0000318 // If this is a pseudo instruction, mark it isCodeGenOnly.
319 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
Bob Wilson3968c6a2010-03-23 17:23:59 +0000320
Jim Grosbach30694dc2011-08-15 16:52:24 +0000321 // The layout of TSFlags should be kept in sync with ARMBaseInfo.h.
Jim Grosbache9298992010-10-05 18:14:55 +0000322 let TSFlags{4-0} = AM.Value;
Owen Anderson651b2302011-07-13 23:22:26 +0000323 let TSFlags{6-5} = IndexModeBits;
324 let TSFlags{12-7} = Form;
325 let TSFlags{13} = isUnaryDataProc;
326 let TSFlags{14} = canXformTo16Bit;
327 let TSFlags{17-15} = D.Value;
Jim Grosbach3e941ae2011-08-16 20:45:50 +0000328 let TSFlags{18} = thumbArithFlagSetting;
Jakob Stoklund Olesenb93331f2010-04-05 03:10:20 +0000329
Evan Cheng2d37f192008-08-28 23:39:26 +0000330 let Constraints = cstr;
David Goodwinb062c232009-08-06 16:52:47 +0000331 let Itinerary = itin;
Evan Cheng2d37f192008-08-28 23:39:26 +0000332}
333
Johnny Chenc28e6292009-12-15 17:24:14 +0000334class Encoding {
335 field bits<32> Inst;
James Molloyd9ba4fd2012-02-09 10:56:31 +0000336 // Mask of bits that cause an encoding to be UNPREDICTABLE.
337 // If a bit is set, then if the corresponding bit in the
338 // target encoding differs from its value in the "Inst" field,
339 // the instruction is UNPREDICTABLE (SoftFail in abstract parlance).
340 field bits<32> Unpredictable = 0;
341 // SoftFail is the generic name for this field, but we alias it so
342 // as to make it more obvious what it means in ARM-land.
343 field bits<32> SoftFail = Unpredictable;
Johnny Chenc28e6292009-12-15 17:24:14 +0000344}
345
Owen Anderson651b2302011-07-13 23:22:26 +0000346class InstARM<AddrMode am, int sz, IndexMode im,
Johnny Chenc28e6292009-12-15 17:24:14 +0000347 Format f, Domain d, string cstr, InstrItinClass itin>
Owen Andersonc78e03c2011-07-19 21:06:00 +0000348 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding {
349 let DecoderNamespace = "ARM";
350}
Johnny Chenc28e6292009-12-15 17:24:14 +0000351
352// This Encoding-less class is used by Thumb1 to specify the encoding bits later
353// on by adding flavors to specific instructions.
Owen Anderson651b2302011-07-13 23:22:26 +0000354class InstThumb<AddrMode am, int sz, IndexMode im,
Johnny Chenc28e6292009-12-15 17:24:14 +0000355 Format f, Domain d, string cstr, InstrItinClass itin>
Owen Andersonc78e03c2011-07-19 21:06:00 +0000356 : InstTemplate<am, sz, im, f, d, cstr, itin> {
357 let DecoderNamespace = "Thumb";
358}
Johnny Chenc28e6292009-12-15 17:24:14 +0000359
Jim Grosbachfb2f1d62011-11-01 01:24:45 +0000360// Pseudo-instructions for alternate assembly syntax (never used by codegen).
361// These are aliases that require C++ handling to convert to the target
362// instruction, while InstAliases can be handled directly by tblgen.
Saleem Abdulrasoolfb3950e2014-01-12 04:36:01 +0000363class AsmPseudoInst<string asm, dag iops, dag oops = (outs)>
Jim Grosbachfb2f1d62011-11-01 01:24:45 +0000364 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
365 "", NoItinerary> {
Saleem Abdulrasoolfb3950e2014-01-12 04:36:01 +0000366 let OutOperandList = oops;
Jim Grosbachfb2f1d62011-11-01 01:24:45 +0000367 let InOperandList = iops;
368 let Pattern = [];
369 let isCodeGenOnly = 0; // So we get asm matcher for it.
Jim Grosbach61db5a52011-11-10 16:44:55 +0000370 let AsmString = asm;
Jim Grosbachfb2f1d62011-11-01 01:24:45 +0000371 let isPseudo = 1;
372}
373
Saleem Abdulrasoolfb3950e2014-01-12 04:36:01 +0000374class ARMAsmPseudo<string asm, dag iops, dag oops = (outs)>
375 : AsmPseudoInst<asm, iops, oops>, Requires<[IsARM]>;
376class tAsmPseudo<string asm, dag iops, dag oops = (outs)>
377 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb]>;
378class t2AsmPseudo<string asm, dag iops, dag oops = (outs)>
379 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb2]>;
380class VFP2AsmPseudo<string asm, dag iops, dag oops = (outs)>
381 : AsmPseudoInst<asm, iops, oops>, Requires<[HasVFP2]>;
382class NEONAsmPseudo<string asm, dag iops, dag oops = (outs)>
383 : AsmPseudoInst<asm, iops, oops>, Requires<[HasNEON]>;
Jim Grosbachfb2f1d62011-11-01 01:24:45 +0000384
385// Pseudo instructions for the code generator.
Jim Grosbacha74c7ccd2010-11-18 01:38:26 +0000386class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000387 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo,
Jim Grosbach7c301ea2011-07-06 21:35:46 +0000388 GenericDomain, "", itin> {
Evan Cheng2d37f192008-08-28 23:39:26 +0000389 let OutOperandList = oops;
390 let InOperandList = iops;
Evan Cheng2d37f192008-08-28 23:39:26 +0000391 let Pattern = pattern;
Jim Grosbache1756822011-03-10 19:06:39 +0000392 let isCodeGenOnly = 1;
Jim Grosbach7c301ea2011-07-06 21:35:46 +0000393 let isPseudo = 1;
Evan Cheng2d37f192008-08-28 23:39:26 +0000394}
395
Jim Grosbachcfb66202010-11-18 01:15:56 +0000396// PseudoInst that's ARM-mode only.
Owen Anderson651b2302011-07-13 23:22:26 +0000397class ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
Jim Grosbacha74c7ccd2010-11-18 01:38:26 +0000398 list<dag> pattern>
399 : PseudoInst<oops, iops, itin, pattern> {
Owen Anderson651b2302011-07-13 23:22:26 +0000400 let Size = sz;
Jim Grosbachcfb66202010-11-18 01:15:56 +0000401 list<Predicate> Predicates = [IsARM];
402}
403
Jim Grosbach58bc36a2010-11-29 19:32:47 +0000404// PseudoInst that's Thumb-mode only.
Owen Anderson651b2302011-07-13 23:22:26 +0000405class tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
Jim Grosbach58bc36a2010-11-29 19:32:47 +0000406 list<dag> pattern>
407 : PseudoInst<oops, iops, itin, pattern> {
Owen Anderson651b2302011-07-13 23:22:26 +0000408 let Size = sz;
Jim Grosbach58bc36a2010-11-29 19:32:47 +0000409 list<Predicate> Predicates = [IsThumb];
410}
Jim Grosbachcfb66202010-11-18 01:15:56 +0000411
Prakhar Bahuguna52a7dd72016-12-15 07:59:08 +0000412// PseudoInst that's in ARMv8-M baseline (Somewhere between Thumb and Thumb2)
413class t2basePseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
414 list<dag> pattern>
415 : PseudoInst<oops, iops, itin, pattern> {
416 let Size = sz;
417 list<Predicate> Predicates = [IsThumb,HasV8MBaseline];
418}
419
Jim Grosbachd42257c2010-12-15 18:48:45 +0000420// PseudoInst that's Thumb2-mode only.
Owen Anderson651b2302011-07-13 23:22:26 +0000421class t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
Jim Grosbachd42257c2010-12-15 18:48:45 +0000422 list<dag> pattern>
423 : PseudoInst<oops, iops, itin, pattern> {
Owen Anderson651b2302011-07-13 23:22:26 +0000424 let Size = sz;
Jim Grosbachd42257c2010-12-15 18:48:45 +0000425 list<Predicate> Predicates = [IsThumb2];
426}
Jim Grosbach95dee402011-07-08 17:40:42 +0000427
Owen Anderson651b2302011-07-13 23:22:26 +0000428class ARMPseudoExpand<dag oops, dag iops, int sz,
Jim Grosbach95dee402011-07-08 17:40:42 +0000429 InstrItinClass itin, list<dag> pattern,
430 dag Result>
431 : ARMPseudoInst<oops, iops, sz, itin, pattern>,
432 PseudoInstExpansion<Result>;
433
Owen Anderson651b2302011-07-13 23:22:26 +0000434class tPseudoExpand<dag oops, dag iops, int sz,
Jim Grosbach95dee402011-07-08 17:40:42 +0000435 InstrItinClass itin, list<dag> pattern,
436 dag Result>
437 : tPseudoInst<oops, iops, sz, itin, pattern>,
438 PseudoInstExpansion<Result>;
439
Owen Anderson651b2302011-07-13 23:22:26 +0000440class t2PseudoExpand<dag oops, dag iops, int sz,
Jim Grosbach95dee402011-07-08 17:40:42 +0000441 InstrItinClass itin, list<dag> pattern,
442 dag Result>
443 : t2PseudoInst<oops, iops, sz, itin, pattern>,
444 PseudoInstExpansion<Result>;
445
Evan Cheng2d37f192008-08-28 23:39:26 +0000446// Almost all ARM instructions are predicable.
Owen Anderson651b2302011-07-13 23:22:26 +0000447class I<dag oops, dag iops, AddrMode am, int sz,
Bob Wilson3968c6a2010-03-23 17:23:59 +0000448 IndexMode im, Format f, InstrItinClass itin,
David Goodwinb062c232009-08-06 16:52:47 +0000449 string opc, string asm, string cstr,
Evan Cheng2d37f192008-08-28 23:39:26 +0000450 list<dag> pattern>
Anton Korobeynikov14635da2009-11-02 00:10:38 +0000451 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
Jim Grosbach5476a272010-10-11 18:51:51 +0000452 bits<4> p;
453 let Inst{31-28} = p;
Evan Cheng2d37f192008-08-28 23:39:26 +0000454 let OutOperandList = oops;
Chris Lattnerfb2ceed2010-03-18 21:06:54 +0000455 let InOperandList = !con(iops, (ins pred:$p));
Chris Lattner04c342e2010-10-06 00:05:18 +0000456 let AsmString = !strconcat(opc, "${p}", asm);
Evan Cheng2d37f192008-08-28 23:39:26 +0000457 let Pattern = pattern;
458 list<Predicate> Predicates = [IsARM];
459}
Bill Wendlingb70dc872010-08-31 07:50:46 +0000460
Jim Grosbach5e0d2a22009-12-14 18:31:20 +0000461// A few are not predicable
Owen Anderson651b2302011-07-13 23:22:26 +0000462class InoP<dag oops, dag iops, AddrMode am, int sz,
Bob Wilson3968c6a2010-03-23 17:23:59 +0000463 IndexMode im, Format f, InstrItinClass itin,
464 string opc, string asm, string cstr,
465 list<dag> pattern>
Jim Grosbach5e0d2a22009-12-14 18:31:20 +0000466 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
467 let OutOperandList = oops;
468 let InOperandList = iops;
Bob Wilson722bff22010-05-24 20:08:34 +0000469 let AsmString = !strconcat(opc, asm);
Jim Grosbach5e0d2a22009-12-14 18:31:20 +0000470 let Pattern = pattern;
471 let isPredicable = 0;
472 list<Predicate> Predicates = [IsARM];
473}
Evan Cheng2d37f192008-08-28 23:39:26 +0000474
Bill Wendlingf8dfa462010-08-30 01:47:35 +0000475// Same as I except it can optionally modify CPSR. Note it's modeled as an input
476// operand since by default it's a zero register. It will become an implicit def
477// once it's "flipped".
Owen Anderson651b2302011-07-13 23:22:26 +0000478class sI<dag oops, dag iops, AddrMode am, int sz,
David Goodwinb062c232009-08-06 16:52:47 +0000479 IndexMode im, Format f, InstrItinClass itin,
480 string opc, string asm, string cstr,
Evan Cheng2d37f192008-08-28 23:39:26 +0000481 list<dag> pattern>
Anton Korobeynikov14635da2009-11-02 00:10:38 +0000482 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
Jim Grosbach5476a272010-10-11 18:51:51 +0000483 bits<4> p; // Predicate operand
Jim Grosbachd9d31da2010-10-12 23:00:24 +0000484 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
Jim Grosbach5476a272010-10-11 18:51:51 +0000485 let Inst{31-28} = p;
Jim Grosbachd9d31da2010-10-12 23:00:24 +0000486 let Inst{20} = s;
Jim Grosbach5476a272010-10-11 18:51:51 +0000487
Evan Cheng2d37f192008-08-28 23:39:26 +0000488 let OutOperandList = oops;
Chris Lattnerfb2ceed2010-03-18 21:06:54 +0000489 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
Bob Wilson59351842010-10-15 03:23:44 +0000490 let AsmString = !strconcat(opc, "${s}${p}", asm);
Evan Cheng2d37f192008-08-28 23:39:26 +0000491 let Pattern = pattern;
492 list<Predicate> Predicates = [IsARM];
493}
494
Evan Chenga2827232008-09-01 07:19:00 +0000495// Special cases
Owen Anderson651b2302011-07-13 23:22:26 +0000496class XI<dag oops, dag iops, AddrMode am, int sz,
David Goodwinb062c232009-08-06 16:52:47 +0000497 IndexMode im, Format f, InstrItinClass itin,
498 string asm, string cstr, list<dag> pattern>
Anton Korobeynikov14635da2009-11-02 00:10:38 +0000499 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
Evan Chenga2827232008-09-01 07:19:00 +0000500 let OutOperandList = oops;
501 let InOperandList = iops;
Bob Wilson722bff22010-05-24 20:08:34 +0000502 let AsmString = asm;
Evan Chenga2827232008-09-01 07:19:00 +0000503 let Pattern = pattern;
504 list<Predicate> Predicates = [IsARM];
505}
506
David Goodwinb062c232009-08-06 16:52:47 +0000507class AI<dag oops, dag iops, Format f, InstrItinClass itin,
508 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000509 : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
David Goodwinb062c232009-08-06 16:52:47 +0000510 opc, asm, "", pattern>;
511class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
512 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000513 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
David Goodwinb062c232009-08-06 16:52:47 +0000514 opc, asm, "", pattern>;
515class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
Evan Cheng2d37f192008-08-28 23:39:26 +0000516 string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000517 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
Evan Cheng49d66522008-11-06 22:15:19 +0000518 asm, "", pattern>;
David Peixottob76f55f2014-01-27 21:39:04 +0000519class AXIM<dag oops, dag iops, AddrMode am, Format f, InstrItinClass itin,
520 string asm, list<dag> pattern>
521 : XI<oops, iops, am, 4, IndexModeNone, f, itin,
522 asm, "", pattern>;
Jim Grosbach5e0d2a22009-12-14 18:31:20 +0000523class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
Bob Wilson3968c6a2010-03-23 17:23:59 +0000524 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000525 : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
Bob Wilson3968c6a2010-03-23 17:23:59 +0000526 opc, asm, "", pattern>;
Evan Chengfa558782008-09-01 08:25:56 +0000527
528// Ctrl flow instructions
David Goodwinb062c232009-08-06 16:52:47 +0000529class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
530 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000531 : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
David Goodwinb062c232009-08-06 16:52:47 +0000532 opc, asm, "", pattern> {
Jim Grosbachb7c01f52008-10-14 20:36:24 +0000533 let Inst{27-24} = opcod;
Evan Chengfa558782008-09-01 08:25:56 +0000534}
David Goodwinb062c232009-08-06 16:52:47 +0000535class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
536 string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000537 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
David Goodwinb062c232009-08-06 16:52:47 +0000538 asm, "", pattern> {
Jim Grosbachb7c01f52008-10-14 20:36:24 +0000539 let Inst{27-24} = opcod;
Evan Chengfa558782008-09-01 08:25:56 +0000540}
Evan Chengfa558782008-09-01 08:25:56 +0000541
542// BR_JT instructions
David Goodwinb062c232009-08-06 16:52:47 +0000543class JTI<dag oops, dag iops, InstrItinClass itin,
544 string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000545 : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin,
Evan Cheng7095cd22008-11-07 09:06:08 +0000546 asm, "", pattern>;
Evan Cheng624844b2008-09-01 01:51:14 +0000547
Joey Goulye6d165c2013-08-27 17:38:16 +0000548class AIldr_ex_or_acq<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin,
Jim Grosbach5c4e99f2009-12-11 01:42:04 +0000549 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000550 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
Jim Grosbach5c4e99f2009-12-11 01:42:04 +0000551 opc, asm, "", pattern> {
Jim Grosbach4e57b522010-10-29 19:58:57 +0000552 bits<4> Rt;
Jim Grosbachcb311932011-07-26 17:44:46 +0000553 bits<4> addr;
Jim Grosbach5c4e99f2009-12-11 01:42:04 +0000554 let Inst{27-23} = 0b00011;
555 let Inst{22-21} = opcod;
Bill Wendlingb70dc872010-08-31 07:50:46 +0000556 let Inst{20} = 1;
Jim Grosbachcb311932011-07-26 17:44:46 +0000557 let Inst{19-16} = addr;
Jim Grosbach4e57b522010-10-29 19:58:57 +0000558 let Inst{15-12} = Rt;
Joey Goulye6d165c2013-08-27 17:38:16 +0000559 let Inst{11-10} = 0b11;
560 let Inst{9-8} = opcod2;
561 let Inst{7-0} = 0b10011111;
Jim Grosbach5c4e99f2009-12-11 01:42:04 +0000562}
Joey Goulye6d165c2013-08-27 17:38:16 +0000563class AIstr_ex_or_rel<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin,
Jim Grosbach5c4e99f2009-12-11 01:42:04 +0000564 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000565 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
Jim Grosbach5c4e99f2009-12-11 01:42:04 +0000566 opc, asm, "", pattern> {
Jim Grosbach4e57b522010-10-29 19:58:57 +0000567 bits<4> Rt;
Bruno Cardoso Lopesf170f8b2011-03-24 21:04:58 +0000568 bits<4> addr;
Jim Grosbach5c4e99f2009-12-11 01:42:04 +0000569 let Inst{27-23} = 0b00011;
570 let Inst{22-21} = opcod;
Bill Wendlingb70dc872010-08-31 07:50:46 +0000571 let Inst{20} = 0;
Bruno Cardoso Lopesf170f8b2011-03-24 21:04:58 +0000572 let Inst{19-16} = addr;
Joey Goulye6d165c2013-08-27 17:38:16 +0000573 let Inst{11-10} = 0b11;
574 let Inst{9-8} = opcod2;
575 let Inst{7-4} = 0b1001;
Jim Grosbach4e57b522010-10-29 19:58:57 +0000576 let Inst{3-0} = Rt;
Jim Grosbach5c4e99f2009-12-11 01:42:04 +0000577}
Joey Goulye6d165c2013-08-27 17:38:16 +0000578// Atomic load/store instructions
579class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
580 string opc, string asm, list<dag> pattern>
581 : AIldr_ex_or_acq<opcod, 0b11, oops, iops, itin, opc, asm, pattern>;
582
583class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
584 string opc, string asm, list<dag> pattern>
585 : AIstr_ex_or_rel<opcod, 0b11, oops, iops, itin, opc, asm, pattern> {
586 bits<4> Rd;
587 let Inst{15-12} = Rd;
588}
589
590// Exclusive load/store instructions
591
592class AIldaex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
593 string opc, string asm, list<dag> pattern>
594 : AIldr_ex_or_acq<opcod, 0b10, oops, iops, itin, opc, asm, pattern>,
Bradley Smith4c21cba2016-01-15 10:23:46 +0000595 Requires<[IsARM, HasAcquireRelease, HasV7Clrex]>;
Joey Goulye6d165c2013-08-27 17:38:16 +0000596
597class AIstlex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
598 string opc, string asm, list<dag> pattern>
599 : AIstr_ex_or_rel<opcod, 0b10, oops, iops, itin, opc, asm, pattern>,
Bradley Smith4c21cba2016-01-15 10:23:46 +0000600 Requires<[IsARM, HasAcquireRelease, HasV7Clrex]> {
Joey Goulye6d165c2013-08-27 17:38:16 +0000601 bits<4> Rd;
602 let Inst{15-12} = Rd;
603}
604
Jim Grosbach3b7e05b2010-10-29 20:21:36 +0000605class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
Jim Grosbach15e8d742011-07-26 17:15:11 +0000606 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
Jim Grosbach3b7e05b2010-10-29 20:21:36 +0000607 bits<4> Rt;
608 bits<4> Rt2;
Jim Grosbach15e8d742011-07-26 17:15:11 +0000609 bits<4> addr;
Jim Grosbach3b7e05b2010-10-29 20:21:36 +0000610 let Inst{27-23} = 0b00010;
611 let Inst{22} = b;
612 let Inst{21-20} = 0b00;
Jim Grosbach15e8d742011-07-26 17:15:11 +0000613 let Inst{19-16} = addr;
Jim Grosbach3b7e05b2010-10-29 20:21:36 +0000614 let Inst{15-12} = Rt;
615 let Inst{11-4} = 0b00001001;
616 let Inst{3-0} = Rt2;
Owen Andersondde461c2011-10-28 18:02:13 +0000617
Silviu Barangaca45af92012-04-18 14:18:57 +0000618 let Unpredictable{11-8} = 0b1111;
Owen Andersondde461c2011-10-28 18:02:13 +0000619 let DecoderMethod = "DecodeSwap";
Jim Grosbach3b7e05b2010-10-29 20:21:36 +0000620}
Joey Goulye6d165c2013-08-27 17:38:16 +0000621// Acquire/Release load/store instructions
622class AIldracq<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
623 string opc, string asm, list<dag> pattern>
624 : AIldr_ex_or_acq<opcod, 0b00, oops, iops, itin, opc, asm, pattern>,
Bradley Smith4c21cba2016-01-15 10:23:46 +0000625 Requires<[IsARM, HasAcquireRelease]>;
Joey Goulye6d165c2013-08-27 17:38:16 +0000626
627class AIstrrel<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
628 string opc, string asm, list<dag> pattern>
629 : AIstr_ex_or_rel<opcod, 0b00, oops, iops, itin, opc, asm, pattern>,
Bradley Smith4c21cba2016-01-15 10:23:46 +0000630 Requires<[IsARM, HasAcquireRelease]> {
Joey Goulye6d165c2013-08-27 17:38:16 +0000631 let Inst{15-12} = 0b1111;
632}
Jim Grosbach5c4e99f2009-12-11 01:42:04 +0000633
Evan Cheng624844b2008-09-01 01:51:14 +0000634// addrmode1 instructions
David Goodwinb062c232009-08-06 16:52:47 +0000635class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
636 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000637 : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
David Goodwinb062c232009-08-06 16:52:47 +0000638 opc, asm, "", pattern> {
Jim Grosbachb7c01f52008-10-14 20:36:24 +0000639 let Inst{24-21} = opcod;
Bill Wendlingb70dc872010-08-31 07:50:46 +0000640 let Inst{27-26} = 0b00;
Evan Chengc139c222008-08-29 07:40:52 +0000641}
David Goodwinb062c232009-08-06 16:52:47 +0000642class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
643 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000644 : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
David Goodwinb062c232009-08-06 16:52:47 +0000645 opc, asm, "", pattern> {
646 let Inst{24-21} = opcod;
Bill Wendlingb70dc872010-08-31 07:50:46 +0000647 let Inst{27-26} = 0b00;
David Goodwinb062c232009-08-06 16:52:47 +0000648}
649class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
Evan Cheng2d37f192008-08-28 23:39:26 +0000650 string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000651 : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
Evan Chengc139c222008-08-29 07:40:52 +0000652 asm, "", pattern> {
Jim Grosbachb7c01f52008-10-14 20:36:24 +0000653 let Inst{24-21} = opcod;
Bill Wendlingb70dc872010-08-31 07:50:46 +0000654 let Inst{27-26} = 0b00;
Evan Chengc139c222008-08-29 07:40:52 +0000655}
Evan Cheng624844b2008-09-01 01:51:14 +0000656
Evan Chengcccca872008-09-01 01:27:33 +0000657// loads
Jim Grosbach1e4d9a12010-10-26 22:37:02 +0000658
Jim Grosbach4a22eba2010-11-19 21:07:51 +0000659// LDR/LDRB/STR/STRB/...
660class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
Jim Grosbach338de3e2010-10-27 23:12:14 +0000661 Format f, InstrItinClass itin, string opc, string asm,
662 list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000663 : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm,
Jim Grosbach1e4d9a12010-10-26 22:37:02 +0000664 "", pattern> {
665 let Inst{27-25} = op;
666 let Inst{24} = 1; // 24 == P
667 // 23 == U
Jim Grosbach2f790742010-11-13 00:35:48 +0000668 let Inst{22} = isByte;
Jim Grosbach1e4d9a12010-10-26 22:37:02 +0000669 let Inst{21} = 0; // 21 == W
Jim Grosbach338de3e2010-10-27 23:12:14 +0000670 let Inst{20} = isLd;
Jim Grosbach1e4d9a12010-10-26 22:37:02 +0000671}
Jim Grosbach2f790742010-11-13 00:35:48 +0000672// Indexed load/stores
673class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
Jim Grosbach6e9aace2010-11-19 21:35:06 +0000674 IndexMode im, Format f, InstrItinClass itin, string opc,
Jim Grosbach2f790742010-11-13 00:35:48 +0000675 string asm, string cstr, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000676 : I<oops, iops, AddrMode2, 4, im, f, itin,
Jim Grosbach2f790742010-11-13 00:35:48 +0000677 opc, asm, cstr, pattern> {
Jim Grosbach38b469e2010-11-15 20:47:07 +0000678 bits<4> Rt;
Jim Grosbach2f790742010-11-13 00:35:48 +0000679 let Inst{27-26} = 0b01;
680 let Inst{24} = isPre; // P bit
681 let Inst{22} = isByte; // B bit
682 let Inst{21} = isPre; // W bit
683 let Inst{20} = isLd; // L bit
Jim Grosbach38b469e2010-11-15 20:47:07 +0000684 let Inst{15-12} = Rt;
Jim Grosbach1e4d9a12010-10-26 22:37:02 +0000685}
Owen Anderson2aedba62011-07-26 20:54:26 +0000686class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops,
Jim Grosbach6e9aace2010-11-19 21:35:06 +0000687 IndexMode im, Format f, InstrItinClass itin, string opc,
688 string asm, string cstr, list<dag> pattern>
689 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
690 pattern> {
691 // AM2 store w/ two operands: (GPR, am2offset)
Jim Grosbach6e9aace2010-11-19 21:35:06 +0000692 // {12} isAdd
693 // {11-0} imm12/Rm
Bruno Cardoso Lopesc2452a62011-03-31 15:54:36 +0000694 bits<14> offset;
695 bits<4> Rn;
Owen Anderson2aedba62011-07-26 20:54:26 +0000696 let Inst{25} = 1;
697 let Inst{23} = offset{12};
698 let Inst{19-16} = Rn;
699 let Inst{11-5} = offset{11-5};
700 let Inst{4} = 0;
701 let Inst{3-0} = offset{3-0};
702}
703
704class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops,
705 IndexMode im, Format f, InstrItinClass itin, string opc,
706 string asm, string cstr, list<dag> pattern>
707 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
708 pattern> {
709 // AM2 store w/ two operands: (GPR, am2offset)
710 // {12} isAdd
711 // {11-0} imm12/Rm
712 bits<14> offset;
713 bits<4> Rn;
714 let Inst{25} = 0;
Bruno Cardoso Lopesc2452a62011-03-31 15:54:36 +0000715 let Inst{23} = offset{12};
716 let Inst{19-16} = Rn;
717 let Inst{11-0} = offset{11-0};
Jim Grosbach6e9aace2010-11-19 21:35:06 +0000718}
Owen Anderson2aedba62011-07-26 20:54:26 +0000719
720
Bruno Cardoso Lopesab830502011-03-31 23:26:08 +0000721// FIXME: Merge with the above class when addrmode2 gets used for STR, STRB
722// but for now use this class for STRT and STRBT.
723class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
724 IndexMode im, Format f, InstrItinClass itin, string opc,
725 string asm, string cstr, list<dag> pattern>
726 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
727 pattern> {
728 // AM2 store w/ two operands: (GPR, am2offset)
729 // {17-14} Rn
730 // {13} 1 == Rm, 0 == imm12
731 // {12} isAdd
732 // {11-0} imm12/Rm
733 bits<18> addr;
734 let Inst{25} = addr{13};
735 let Inst{23} = addr{12};
736 let Inst{19-16} = addr{17-14};
737 let Inst{11-0} = addr{11-0};
738}
Jim Grosbach1e4d9a12010-10-26 22:37:02 +0000739
Evan Cheng624844b2008-09-01 01:51:14 +0000740// addrmode3 instructions
Jim Grosbach76aed402010-11-19 18:16:46 +0000741class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
742 InstrItinClass itin, string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000743 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
Jim Grosbach8e7f8df2010-11-18 00:46:58 +0000744 opc, asm, "", pattern> {
745 bits<14> addr;
746 bits<4> Rt;
747 let Inst{27-25} = 0b000;
748 let Inst{24} = 1; // P bit
749 let Inst{23} = addr{8}; // U bit
750 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
751 let Inst{21} = 0; // W bit
Jim Grosbach76aed402010-11-19 18:16:46 +0000752 let Inst{20} = op20; // L bit
Jim Grosbach8e7f8df2010-11-18 00:46:58 +0000753 let Inst{19-16} = addr{12-9}; // Rn
754 let Inst{15-12} = Rt; // Rt
755 let Inst{11-8} = addr{7-4}; // imm7_4/zero
756 let Inst{7-4} = op;
757 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
Owen Andersone0152a72011-08-09 20:55:18 +0000758
759 let DecoderMethod = "DecodeAddrMode3Instruction";
Jim Grosbach8e7f8df2010-11-18 00:46:58 +0000760}
Evan Cheng169eccc2008-09-01 07:00:14 +0000761
Jim Grosbach2ea19d12011-08-11 20:41:13 +0000762class AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops,
Jim Grosbach003c6e72010-11-19 19:41:26 +0000763 IndexMode im, Format f, InstrItinClass itin, string opc,
764 string asm, string cstr, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000765 : I<oops, iops, AddrMode3, 4, im, f, itin,
Jim Grosbach003c6e72010-11-19 19:41:26 +0000766 opc, asm, cstr, pattern> {
767 bits<4> Rt;
768 let Inst{27-25} = 0b000;
769 let Inst{24} = isPre; // P bit
770 let Inst{21} = isPre; // W bit
771 let Inst{20} = op20; // L bit
772 let Inst{15-12} = Rt; // Rt
773 let Inst{7-4} = op;
774}
Bruno Cardoso Lopesbda36322011-04-04 17:18:19 +0000775
776// FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB
777// but for now use this class for LDRSBT, LDRHT, LDSHT.
Jim Grosbachd3595712011-08-03 23:50:40 +0000778class AI3ldstidxT<bits<4> op, bit isLoad, dag oops, dag iops,
Bruno Cardoso Lopesbda36322011-04-04 17:18:19 +0000779 IndexMode im, Format f, InstrItinClass itin, string opc,
780 string asm, string cstr, list<dag> pattern>
Jim Grosbachd3595712011-08-03 23:50:40 +0000781 : I<oops, iops, AddrMode3, 4, im, f, itin, opc, asm, cstr, pattern> {
Bruno Cardoso Lopesbda36322011-04-04 17:18:19 +0000782 // {13} 1 == imm8, 0 == Rm
783 // {12-9} Rn
784 // {8} isAdd
785 // {7-4} imm7_4/zero
786 // {3-0} imm3_0/Rm
Jim Grosbachd3595712011-08-03 23:50:40 +0000787 bits<4> addr;
Bruno Cardoso Lopesbda36322011-04-04 17:18:19 +0000788 bits<4> Rt;
789 let Inst{27-25} = 0b000;
Jim Grosbachd3595712011-08-03 23:50:40 +0000790 let Inst{24} = 0; // P bit
791 let Inst{21} = 1;
792 let Inst{20} = isLoad; // L bit
793 let Inst{19-16} = addr; // Rn
Bruno Cardoso Lopesbda36322011-04-04 17:18:19 +0000794 let Inst{15-12} = Rt; // Rt
Bruno Cardoso Lopesbda36322011-04-04 17:18:19 +0000795 let Inst{7-4} = op;
Bruno Cardoso Lopesbda36322011-04-04 17:18:19 +0000796}
797
Evan Cheng169eccc2008-09-01 07:00:14 +0000798// stores
Jim Grosbach09d7bfd2010-11-19 22:14:31 +0000799class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
David Goodwinb062c232009-08-06 16:52:47 +0000800 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000801 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
David Goodwinb062c232009-08-06 16:52:47 +0000802 opc, asm, "", pattern> {
Jim Grosbach607efcb2010-11-11 01:09:40 +0000803 bits<14> addr;
804 bits<4> Rt;
Evan Cheng5edd90c2009-07-08 22:51:32 +0000805 let Inst{27-25} = 0b000;
Jim Grosbach607efcb2010-11-11 01:09:40 +0000806 let Inst{24} = 1; // P bit
807 let Inst{23} = addr{8}; // U bit
808 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
809 let Inst{21} = 0; // W bit
810 let Inst{20} = 0; // L bit
811 let Inst{19-16} = addr{12-9}; // Rn
812 let Inst{15-12} = Rt; // Rt
813 let Inst{11-8} = addr{7-4}; // imm7_4/zero
Jim Grosbach09d7bfd2010-11-19 22:14:31 +0000814 let Inst{7-4} = op;
Jim Grosbach607efcb2010-11-11 01:09:40 +0000815 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
Owen Anderson60138ea2011-08-12 20:02:50 +0000816 let DecoderMethod = "DecodeAddrMode3Instruction";
Evan Cheng169eccc2008-09-01 07:00:14 +0000817}
Evan Cheng169eccc2008-09-01 07:00:14 +0000818
Evan Cheng624844b2008-09-01 01:51:14 +0000819// addrmode4 instructions
Bill Wendlinge69afc62010-11-13 09:09:38 +0000820class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
821 string asm, string cstr, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000822 : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> {
Bill Wendlinge69afc62010-11-13 09:09:38 +0000823 bits<4> p;
824 bits<16> regs;
825 bits<4> Rn;
826 let Inst{31-28} = p;
827 let Inst{27-25} = 0b100;
828 let Inst{22} = 0; // S bit
829 let Inst{19-16} = Rn;
830 let Inst{15-0} = regs;
831}
Evan Cheng2d37f192008-08-28 23:39:26 +0000832
Jim Grosbach4d0549e2008-11-03 18:38:31 +0000833// Unsigned multiply, multiply-accumulate instructions.
David Goodwinb062c232009-08-06 16:52:47 +0000834class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
835 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000836 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
David Goodwinb062c232009-08-06 16:52:47 +0000837 opc, asm, "", pattern> {
Jim Grosbach4d0549e2008-11-03 18:38:31 +0000838 let Inst{7-4} = 0b1001;
Evan Cheng2686c8f2008-11-06 01:21:28 +0000839 let Inst{20} = 0; // S bit
Evan Cheng47b546d2008-11-06 08:47:38 +0000840 let Inst{27-21} = opcod;
Jim Grosbach4d0549e2008-11-03 18:38:31 +0000841}
David Goodwinb062c232009-08-06 16:52:47 +0000842class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
843 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000844 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
David Goodwinb062c232009-08-06 16:52:47 +0000845 opc, asm, "", pattern> {
Jim Grosbach4d0549e2008-11-03 18:38:31 +0000846 let Inst{7-4} = 0b1001;
Evan Cheng47b546d2008-11-06 08:47:38 +0000847 let Inst{27-21} = opcod;
Evan Cheng2686c8f2008-11-06 01:21:28 +0000848}
849
850// Most significant word multiply
Jim Grosbach22261602010-10-22 17:16:17 +0000851class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
852 InstrItinClass itin, string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000853 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
David Goodwinb062c232009-08-06 16:52:47 +0000854 opc, asm, "", pattern> {
Jim Grosbach22261602010-10-22 17:16:17 +0000855 bits<4> Rd;
856 bits<4> Rn;
857 bits<4> Rm;
858 let Inst{7-4} = opc7_4;
Evan Cheng2686c8f2008-11-06 01:21:28 +0000859 let Inst{20} = 1;
Evan Cheng47b546d2008-11-06 08:47:38 +0000860 let Inst{27-21} = opcod;
Jim Grosbach22261602010-10-22 17:16:17 +0000861 let Inst{19-16} = Rd;
862 let Inst{11-8} = Rm;
863 let Inst{3-0} = Rn;
864}
865// MSW multiple w/ Ra operand
866class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
867 InstrItinClass itin, string opc, string asm, list<dag> pattern>
868 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
869 bits<4> Ra;
870 let Inst{15-12} = Ra;
Jim Grosbach4d0549e2008-11-03 18:38:31 +0000871}
Evan Cheng2d37f192008-08-28 23:39:26 +0000872
Evan Cheng36ae4032008-11-06 03:35:07 +0000873// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
Jim Grosbach6956a602010-10-22 18:35:16 +0000874class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
Jim Grosbachf98df082010-10-22 17:42:06 +0000875 InstrItinClass itin, string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000876 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
David Goodwinb062c232009-08-06 16:52:47 +0000877 opc, asm, "", pattern> {
Jim Grosbach6956a602010-10-22 18:35:16 +0000878 bits<4> Rn;
879 bits<4> Rm;
Evan Cheng36ae4032008-11-06 03:35:07 +0000880 let Inst{4} = 0;
881 let Inst{7} = 1;
882 let Inst{20} = 0;
Evan Cheng47b546d2008-11-06 08:47:38 +0000883 let Inst{27-21} = opcod;
Jim Grosbachf98df082010-10-22 17:42:06 +0000884 let Inst{6-5} = bit6_5;
Jim Grosbach6956a602010-10-22 18:35:16 +0000885 let Inst{11-8} = Rm;
886 let Inst{3-0} = Rn;
887}
888class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
889 InstrItinClass itin, string opc, string asm, list<dag> pattern>
890 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
891 bits<4> Rd;
892 let Inst{19-16} = Rd;
893}
894
895// AMulxyI with Ra operand
896class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
897 InstrItinClass itin, string opc, string asm, list<dag> pattern>
898 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
899 bits<4> Ra;
900 let Inst{15-12} = Ra;
901}
902// SMLAL*
903class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
904 InstrItinClass itin, string opc, string asm, list<dag> pattern>
905 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
906 bits<4> RdLo;
907 bits<4> RdHi;
908 let Inst{19-16} = RdHi;
909 let Inst{15-12} = RdLo;
Evan Cheng36ae4032008-11-06 03:35:07 +0000910}
911
Evan Cheng49d66522008-11-06 22:15:19 +0000912// Extend instructions.
David Goodwinb062c232009-08-06 16:52:47 +0000913class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
914 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000915 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin,
David Goodwinb062c232009-08-06 16:52:47 +0000916 opc, asm, "", pattern> {
Jim Grosbach1e7db682010-10-13 19:56:10 +0000917 // All AExtI instructions have Rd and Rm register operands.
918 bits<4> Rd;
919 bits<4> Rm;
920 let Inst{15-12} = Rd;
921 let Inst{3-0} = Rm;
Evan Cheng49d66522008-11-06 22:15:19 +0000922 let Inst{7-4} = 0b0111;
Jim Grosbach1e7db682010-10-13 19:56:10 +0000923 let Inst{9-8} = 0b00;
Evan Cheng49d66522008-11-06 22:15:19 +0000924 let Inst{27-20} = opcod;
Silviu Barangaddc67a72012-05-11 09:28:27 +0000925
926 let Unpredictable{9-8} = 0b11;
Evan Cheng49d66522008-11-06 22:15:19 +0000927}
928
Evan Cheng98dc53e2008-11-07 01:41:35 +0000929// Misc Arithmetic instructions.
Jim Grosbach2c9ae052010-10-22 22:12:16 +0000930class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
931 InstrItinClass itin, string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000932 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
David Goodwinb062c232009-08-06 16:52:47 +0000933 opc, asm, "", pattern> {
Jim Grosbach2c9ae052010-10-22 22:12:16 +0000934 bits<4> Rd;
935 bits<4> Rm;
Evan Cheng98dc53e2008-11-07 01:41:35 +0000936 let Inst{27-20} = opcod;
Jim Grosbach2c9ae052010-10-22 22:12:16 +0000937 let Inst{19-16} = 0b1111;
938 let Inst{15-12} = Rd;
939 let Inst{11-8} = 0b1111;
940 let Inst{7-4} = opc7_4;
941 let Inst{3-0} = Rm;
942}
943
Bob Wilsone8a549c2012-09-29 21:43:49 +0000944// Division instructions.
945class ADivA1I<bits<3> opcod, dag oops, dag iops,
946 InstrItinClass itin, string opc, string asm, list<dag> pattern>
947 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
948 opc, asm, "", pattern> {
949 bits<4> Rd;
950 bits<4> Rn;
951 bits<4> Rm;
952 let Inst{27-23} = 0b01110;
953 let Inst{22-20} = opcod;
954 let Inst{19-16} = Rd;
955 let Inst{15-12} = 0b1111;
956 let Inst{11-8} = Rm;
957 let Inst{7-4} = 0b0001;
958 let Inst{3-0} = Rn;
959}
960
Jim Grosbach2c9ae052010-10-22 22:12:16 +0000961// PKH instructions
Sjoerd Meijer11794702017-04-03 14:50:04 +0000962def PKHLSLAsmOperand : ImmAsmOperand<0,31> {
Jim Grosbach27c1e252011-07-21 17:23:04 +0000963 let Name = "PKHLSLImm";
964 let ParserMethod = "parsePKHLSLImm";
965}
Jim Grosbacha288b1c2011-07-20 21:40:26 +0000966def pkh_lsl_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>{
967 let PrintMethod = "printPKHLSLShiftImm";
Jim Grosbach27c1e252011-07-21 17:23:04 +0000968 let ParserMatchClass = PKHLSLAsmOperand;
969}
970def PKHASRAsmOperand : AsmOperandClass {
971 let Name = "PKHASRImm";
972 let ParserMethod = "parsePKHASRImm";
Jim Grosbacha288b1c2011-07-20 21:40:26 +0000973}
974def pkh_asr_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>{
975 let PrintMethod = "printPKHASRShiftImm";
Jim Grosbach27c1e252011-07-21 17:23:04 +0000976 let ParserMatchClass = PKHASRAsmOperand;
Jim Grosbacha288b1c2011-07-20 21:40:26 +0000977}
Jim Grosbach94df3be2011-07-20 20:49:03 +0000978
Jim Grosbach2c9ae052010-10-22 22:12:16 +0000979class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
980 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +0000981 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
Jim Grosbach2c9ae052010-10-22 22:12:16 +0000982 opc, asm, "", pattern> {
983 bits<4> Rd;
984 bits<4> Rn;
985 bits<4> Rm;
Jim Grosbacha98f8002011-07-20 20:32:09 +0000986 bits<5> sh;
Jim Grosbach2c9ae052010-10-22 22:12:16 +0000987 let Inst{27-20} = opcod;
988 let Inst{19-16} = Rn;
989 let Inst{15-12} = Rd;
Jim Grosbacha98f8002011-07-20 20:32:09 +0000990 let Inst{11-7} = sh;
Jim Grosbach2c9ae052010-10-22 22:12:16 +0000991 let Inst{6} = tb;
992 let Inst{5-4} = 0b01;
993 let Inst{3-0} = Rm;
Evan Cheng98dc53e2008-11-07 01:41:35 +0000994}
995
Evan Cheng2d37f192008-08-28 23:39:26 +0000996//===----------------------------------------------------------------------===//
997
998// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
999class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
1000 list<Predicate> Predicates = [IsARM];
1001}
Bruno Cardoso Lopes168c9002011-05-03 17:29:22 +00001002class ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> {
1003 list<Predicate> Predicates = [IsARM, HasV5T];
1004}
Evan Cheng2d37f192008-08-28 23:39:26 +00001005class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
1006 list<Predicate> Predicates = [IsARM, HasV5TE];
1007}
Bob Wilsone8a549c2012-09-29 21:43:49 +00001008// ARMV5MOPat - Same as ARMV5TEPat with UseMulOps.
1009class ARMV5MOPat<dag pattern, dag result> : Pat<pattern, result> {
1010 list<Predicate> Predicates = [IsARM, HasV5TE, UseMulOps];
1011}
Evan Cheng2d37f192008-08-28 23:39:26 +00001012class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
1013 list<Predicate> Predicates = [IsARM, HasV6];
1014}
James Molloyfa041152015-03-23 16:15:16 +00001015class VFPPat<dag pattern, dag result> : Pat<pattern, result> {
1016 list<Predicate> Predicates = [HasVFP2];
1017}
1018class VFPNoNEONPat<dag pattern, dag result> : Pat<pattern, result> {
1019 list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
1020}
Sam Parker18bc3a02016-08-02 12:44:27 +00001021class Thumb2DSPPat<dag pattern, dag result> : Pat<pattern, result> {
1022 list<Predicate> Predicates = [IsThumb2, HasDSP];
1023}
1024class Thumb2DSPMulPat<dag pattern, dag result> : Pat<pattern, result> {
1025 list<Predicate> Predicates = [IsThumb2, UseMulOps, HasDSP];
1026}
Sjoerd Meijer3ddb7fb2018-01-29 11:28:06 +00001027class FP16Pat<dag pattern, dag result> : Pat<pattern, result> {
1028 list<Predicate> Predicates = [HasFP16];
1029}
1030class FullFP16Pat<dag pattern, dag result> : Pat<pattern, result> {
1031 list<Predicate> Predicates = [HasFullFP16];
1032}
Evan Chengee98fa92008-08-29 06:41:12 +00001033//===----------------------------------------------------------------------===//
Evan Chengee98fa92008-08-29 06:41:12 +00001034// Thumb Instruction Format Definitions.
1035//
1036
Owen Anderson651b2302011-07-13 23:22:26 +00001037class ThumbI<dag oops, dag iops, AddrMode am, int sz,
David Goodwinb062c232009-08-06 16:52:47 +00001038 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
Johnny Chenc28e6292009-12-15 17:24:14 +00001039 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
Evan Chengcd4cdd12009-07-11 06:43:01 +00001040 let OutOperandList = oops;
1041 let InOperandList = iops;
Bob Wilson722bff22010-05-24 20:08:34 +00001042 let AsmString = asm;
Evan Chengee98fa92008-08-29 06:41:12 +00001043 let Pattern = pattern;
1044 list<Predicate> Predicates = [IsThumb];
1045}
1046
Bill Wendlingcbb08ca2010-12-01 02:42:55 +00001047// TI - Thumb instruction.
David Goodwinb062c232009-08-06 16:52:47 +00001048class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001049 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
Evan Chengee98fa92008-08-29 06:41:12 +00001050
Evan Cheng7cc6aca2009-08-04 23:47:55 +00001051// Two-address instructions
Bob Wilson3968c6a2010-03-23 17:23:59 +00001052class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
1053 list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001054 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst",
Bob Wilson3968c6a2010-03-23 17:23:59 +00001055 pattern>;
Evan Cheng7cc6aca2009-08-04 23:47:55 +00001056
Johnny Chenc28e6292009-12-15 17:24:14 +00001057// tBL, tBX 32-bit instructions
1058class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
Bob Wilson3968c6a2010-03-23 17:23:59 +00001059 dag oops, dag iops, InstrItinClass itin, string asm,
1060 list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001061 : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>,
Bob Wilson3968c6a2010-03-23 17:23:59 +00001062 Encoding {
Johnny Chenc28e6292009-12-15 17:24:14 +00001063 let Inst{31-27} = opcod1;
1064 let Inst{15-14} = opcod2;
Bill Wendlingb70dc872010-08-31 07:50:46 +00001065 let Inst{12} = opcod3;
Johnny Chenc28e6292009-12-15 17:24:14 +00001066}
Evan Chengee98fa92008-08-29 06:41:12 +00001067
1068// BR_JT instructions
Bob Wilson3968c6a2010-03-23 17:23:59 +00001069class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
1070 list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001071 : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
Evan Chengee98fa92008-08-29 06:41:12 +00001072
Evan Chengbec1dba892009-06-23 19:38:13 +00001073// Thumb1 only
Owen Anderson651b2302011-07-13 23:22:26 +00001074class Thumb1I<dag oops, dag iops, AddrMode am, int sz,
David Goodwinb062c232009-08-06 16:52:47 +00001075 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
Johnny Chenc28e6292009-12-15 17:24:14 +00001076 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
Evan Chengcd4cdd12009-07-11 06:43:01 +00001077 let OutOperandList = oops;
1078 let InOperandList = iops;
Bob Wilson722bff22010-05-24 20:08:34 +00001079 let AsmString = asm;
Evan Chengbec1dba892009-06-23 19:38:13 +00001080 let Pattern = pattern;
Jim Grosbachfddf36d2010-11-01 17:08:58 +00001081 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
Evan Chengbec1dba892009-06-23 19:38:13 +00001082}
1083
David Goodwinb062c232009-08-06 16:52:47 +00001084class T1I<dag oops, dag iops, InstrItinClass itin,
1085 string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001086 : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
David Goodwinb062c232009-08-06 16:52:47 +00001087class T1Ix2<dag oops, dag iops, InstrItinClass itin,
1088 string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001089 : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
Evan Chengbec1dba892009-06-23 19:38:13 +00001090
1091// Two-address instructions
David Goodwinb062c232009-08-06 16:52:47 +00001092class T1It<dag oops, dag iops, InstrItinClass itin,
Bob Wilson947f04b2010-03-13 01:08:20 +00001093 string asm, string cstr, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001094 : Thumb1I<oops, iops, AddrModeNone, 2, itin,
Bob Wilson947f04b2010-03-13 01:08:20 +00001095 asm, cstr, pattern>;
Evan Chengcd4cdd12009-07-11 06:43:01 +00001096
1097// Thumb1 instruction that can either be predicated or set CPSR.
Owen Anderson651b2302011-07-13 23:22:26 +00001098class Thumb1sI<dag oops, dag iops, AddrMode am, int sz,
David Goodwinb062c232009-08-06 16:52:47 +00001099 InstrItinClass itin,
Evan Chengcd4cdd12009-07-11 06:43:01 +00001100 string opc, string asm, string cstr, list<dag> pattern>
Johnny Chenc28e6292009-12-15 17:24:14 +00001101 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
Chris Lattnerfb2ceed2010-03-18 21:06:54 +00001102 let OutOperandList = !con(oops, (outs s_cc_out:$s));
1103 let InOperandList = !con(iops, (ins pred:$p));
Chris Lattner04c342e2010-10-06 00:05:18 +00001104 let AsmString = !strconcat(opc, "${s}${p}", asm);
Evan Chengcd4cdd12009-07-11 06:43:01 +00001105 let Pattern = pattern;
Jim Grosbach3e941ae2011-08-16 20:45:50 +00001106 let thumbArithFlagSetting = 1;
Jim Grosbachfddf36d2010-11-01 17:08:58 +00001107 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
Owen Anderson91a8f9b2011-08-16 23:45:44 +00001108 let DecoderNamespace = "ThumbSBit";
Evan Chengcd4cdd12009-07-11 06:43:01 +00001109}
1110
David Goodwinb062c232009-08-06 16:52:47 +00001111class T1sI<dag oops, dag iops, InstrItinClass itin,
1112 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001113 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
Evan Chengcd4cdd12009-07-11 06:43:01 +00001114
1115// Two-address instructions
David Goodwinb062c232009-08-06 16:52:47 +00001116class T1sIt<dag oops, dag iops, InstrItinClass itin,
1117 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001118 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm,
Bill Wendling05632cb2010-11-30 23:54:45 +00001119 "$Rn = $Rdn", pattern>;
Evan Chengcd4cdd12009-07-11 06:43:01 +00001120
1121// Thumb1 instruction that can be predicated.
Owen Anderson651b2302011-07-13 23:22:26 +00001122class Thumb1pI<dag oops, dag iops, AddrMode am, int sz,
David Goodwinb062c232009-08-06 16:52:47 +00001123 InstrItinClass itin,
Evan Chengcd4cdd12009-07-11 06:43:01 +00001124 string opc, string asm, string cstr, list<dag> pattern>
Johnny Chenc28e6292009-12-15 17:24:14 +00001125 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
Evan Chengcd4cdd12009-07-11 06:43:01 +00001126 let OutOperandList = oops;
Chris Lattnerfb2ceed2010-03-18 21:06:54 +00001127 let InOperandList = !con(iops, (ins pred:$p));
Chris Lattner04c342e2010-10-06 00:05:18 +00001128 let AsmString = !strconcat(opc, "${p}", asm);
Evan Chengcd4cdd12009-07-11 06:43:01 +00001129 let Pattern = pattern;
Jim Grosbachfddf36d2010-11-01 17:08:58 +00001130 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
Evan Chengcd4cdd12009-07-11 06:43:01 +00001131}
1132
David Goodwinb062c232009-08-06 16:52:47 +00001133class T1pI<dag oops, dag iops, InstrItinClass itin,
1134 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001135 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
Evan Chengcd4cdd12009-07-11 06:43:01 +00001136
1137// Two-address instructions
David Goodwinb062c232009-08-06 16:52:47 +00001138class T1pIt<dag oops, dag iops, InstrItinClass itin,
1139 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001140 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm,
Bill Wendling7c646b92010-12-01 01:32:02 +00001141 "$Rn = $Rdn", pattern>;
Evan Chengcd4cdd12009-07-11 06:43:01 +00001142
Bob Wilson3968c6a2010-03-23 17:23:59 +00001143class T1pIs<dag oops, dag iops,
David Goodwinb062c232009-08-06 16:52:47 +00001144 InstrItinClass itin, string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001145 : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>;
Evan Chengbec1dba892009-06-23 19:38:13 +00001146
Johnny Chen466231a2009-12-16 02:32:54 +00001147class Encoding16 : Encoding {
1148 let Inst{31-16} = 0x0000;
1149}
1150
Johnny Chenc28e6292009-12-15 17:24:14 +00001151// A6.2 16-bit Thumb instruction encoding
Johnny Chen466231a2009-12-16 02:32:54 +00001152class T1Encoding<bits<6> opcode> : Encoding16 {
Johnny Chenc28e6292009-12-15 17:24:14 +00001153 let Inst{15-10} = opcode;
1154}
1155
1156// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
Johnny Chen466231a2009-12-16 02:32:54 +00001157class T1General<bits<5> opcode> : Encoding16 {
Johnny Chenc28e6292009-12-15 17:24:14 +00001158 let Inst{15-14} = 0b00;
1159 let Inst{13-9} = opcode;
1160}
1161
1162// A6.2.2 Data-processing encoding.
Johnny Chen466231a2009-12-16 02:32:54 +00001163class T1DataProcessing<bits<4> opcode> : Encoding16 {
Johnny Chenc28e6292009-12-15 17:24:14 +00001164 let Inst{15-10} = 0b010000;
1165 let Inst{9-6} = opcode;
1166}
1167
1168// A6.2.3 Special data instructions and branch and exchange encoding.
Johnny Chen466231a2009-12-16 02:32:54 +00001169class T1Special<bits<4> opcode> : Encoding16 {
Johnny Chenc28e6292009-12-15 17:24:14 +00001170 let Inst{15-10} = 0b010001;
Bill Wendling345b48f2010-11-17 00:45:23 +00001171 let Inst{9-6} = opcode;
Johnny Chenc28e6292009-12-15 17:24:14 +00001172}
1173
1174// A6.2.4 Load/store single data item encoding.
Johnny Chen466231a2009-12-16 02:32:54 +00001175class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
Johnny Chenc28e6292009-12-15 17:24:14 +00001176 let Inst{15-12} = opA;
Bill Wendlingb70dc872010-08-31 07:50:46 +00001177 let Inst{11-9} = opB;
Johnny Chenc28e6292009-12-15 17:24:14 +00001178}
Bill Wendlingb70dc872010-08-31 07:50:46 +00001179class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
Johnny Chenc28e6292009-12-15 17:24:14 +00001180
Eric Christopher9b67db82011-05-27 03:50:53 +00001181class T1BranchCond<bits<4> opcode> : Encoding16 {
1182 let Inst{15-12} = opcode;
1183}
1184
Bill Wendlinga9e3df72010-11-30 22:57:21 +00001185// Helper classes to encode Thumb1 loads and stores. For immediates, the
Bill Wendling05632cb2010-11-30 23:54:45 +00001186// following bits are used for "opA" (see A6.2.4):
Jim Grosbachc4669ed2010-12-10 20:47:29 +00001187//
Bill Wendlinga9e3df72010-11-30 22:57:21 +00001188// 0b0110 => Immediate, 4 bytes
1189// 0b1000 => Immediate, 2 bytes
1190// 0b0111 => Immediate, 1 byte
Bill Wendlingc25545a2010-12-01 01:38:08 +00001191class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
1192 InstrItinClass itin, string opc, string asm,
1193 list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001194 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
Bill Wendling5c51fcd2010-11-30 23:16:25 +00001195 T1LoadStore<0b0101, opcode> {
Bill Wendlinga9e3df72010-11-30 22:57:21 +00001196 bits<3> Rt;
1197 bits<8> addr;
1198 let Inst{8-6} = addr{5-3}; // Rm
1199 let Inst{5-3} = addr{2-0}; // Rn
1200 let Inst{2-0} = Rt;
1201}
Bill Wendlingc25545a2010-12-01 01:38:08 +00001202class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
1203 InstrItinClass itin, string opc, string asm,
1204 list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001205 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
Bill Wendling5c51fcd2010-11-30 23:16:25 +00001206 T1LoadStore<opA, {opB,?,?}> {
Bill Wendlinga9e3df72010-11-30 22:57:21 +00001207 bits<3> Rt;
1208 bits<8> addr;
1209 let Inst{10-6} = addr{7-3}; // imm5
1210 let Inst{5-3} = addr{2-0}; // Rn
1211 let Inst{2-0} = Rt;
1212}
1213
Johnny Chenc28e6292009-12-15 17:24:14 +00001214// A6.2.5 Miscellaneous 16-bit instructions encoding.
Johnny Chen466231a2009-12-16 02:32:54 +00001215class T1Misc<bits<7> opcode> : Encoding16 {
Johnny Chenc28e6292009-12-15 17:24:14 +00001216 let Inst{15-12} = 0b1011;
1217 let Inst{11-5} = opcode;
1218}
1219
Evan Chengd76f0be2009-06-25 02:08:06 +00001220// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
Owen Anderson651b2302011-07-13 23:22:26 +00001221class Thumb2I<dag oops, dag iops, AddrMode am, int sz,
David Goodwinb062c232009-08-06 16:52:47 +00001222 InstrItinClass itin,
Evan Chengd76f0be2009-06-25 02:08:06 +00001223 string opc, string asm, string cstr, list<dag> pattern>
Anton Korobeynikov14635da2009-11-02 00:10:38 +00001224 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
Evan Chengd76f0be2009-06-25 02:08:06 +00001225 let OutOperandList = oops;
Chris Lattnerfb2ceed2010-03-18 21:06:54 +00001226 let InOperandList = !con(iops, (ins pred:$p));
Chris Lattner04c342e2010-10-06 00:05:18 +00001227 let AsmString = !strconcat(opc, "${p}", asm);
Evan Chengd76f0be2009-06-25 02:08:06 +00001228 let Pattern = pattern;
Evan Cheng2c450d32009-07-02 06:38:40 +00001229 list<Predicate> Predicates = [IsThumb2];
Owen Andersonc78e03c2011-07-19 21:06:00 +00001230 let DecoderNamespace = "Thumb2";
Evan Chengd76f0be2009-06-25 02:08:06 +00001231}
1232
Bill Wendlingb70dc872010-08-31 07:50:46 +00001233// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1234// input operand since by default it's a zero register. It will become an
1235// implicit def once it's "flipped".
Jim Grosbachb9386552010-10-13 23:12:26 +00001236//
Evan Chengd76f0be2009-06-25 02:08:06 +00001237// FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1238// more consistent.
Owen Anderson651b2302011-07-13 23:22:26 +00001239class Thumb2sI<dag oops, dag iops, AddrMode am, int sz,
David Goodwinb062c232009-08-06 16:52:47 +00001240 InstrItinClass itin,
Evan Chengd76f0be2009-06-25 02:08:06 +00001241 string opc, string asm, string cstr, list<dag> pattern>
Anton Korobeynikov14635da2009-11-02 00:10:38 +00001242 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
Owen Andersoncf096a42010-12-07 20:50:15 +00001243 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
1244 let Inst{20} = s;
1245
Evan Chengd76f0be2009-06-25 02:08:06 +00001246 let OutOperandList = oops;
Chris Lattnerfb2ceed2010-03-18 21:06:54 +00001247 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
Chris Lattner04c342e2010-10-06 00:05:18 +00001248 let AsmString = !strconcat(opc, "${s}${p}", asm);
Evan Chengd76f0be2009-06-25 02:08:06 +00001249 let Pattern = pattern;
Evan Cheng2c450d32009-07-02 06:38:40 +00001250 list<Predicate> Predicates = [IsThumb2];
Owen Andersonc78e03c2011-07-19 21:06:00 +00001251 let DecoderNamespace = "Thumb2";
Evan Chengd76f0be2009-06-25 02:08:06 +00001252}
1253
1254// Special cases
Owen Anderson651b2302011-07-13 23:22:26 +00001255class Thumb2XI<dag oops, dag iops, AddrMode am, int sz,
David Goodwinb062c232009-08-06 16:52:47 +00001256 InstrItinClass itin,
Evan Chengd76f0be2009-06-25 02:08:06 +00001257 string asm, string cstr, list<dag> pattern>
Anton Korobeynikov14635da2009-11-02 00:10:38 +00001258 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
Evan Chengd76f0be2009-06-25 02:08:06 +00001259 let OutOperandList = oops;
1260 let InOperandList = iops;
Bob Wilson722bff22010-05-24 20:08:34 +00001261 let AsmString = asm;
Evan Cheng431cf562009-06-23 17:48:47 +00001262 let Pattern = pattern;
Evan Cheng2c450d32009-07-02 06:38:40 +00001263 list<Predicate> Predicates = [IsThumb2];
Owen Andersonc78e03c2011-07-19 21:06:00 +00001264 let DecoderNamespace = "Thumb2";
Evan Cheng431cf562009-06-23 17:48:47 +00001265}
1266
Owen Anderson651b2302011-07-13 23:22:26 +00001267class ThumbXI<dag oops, dag iops, AddrMode am, int sz,
Bob Wilson3968c6a2010-03-23 17:23:59 +00001268 InstrItinClass itin,
1269 string asm, string cstr, list<dag> pattern>
Jim Grosbach36d4dec2009-12-01 18:10:36 +00001270 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1271 let OutOperandList = oops;
1272 let InOperandList = iops;
Bob Wilson722bff22010-05-24 20:08:34 +00001273 let AsmString = asm;
Jim Grosbach36d4dec2009-12-01 18:10:36 +00001274 let Pattern = pattern;
Jim Grosbachfddf36d2010-11-01 17:08:58 +00001275 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
Owen Andersonc78e03c2011-07-19 21:06:00 +00001276 let DecoderNamespace = "Thumb";
Jim Grosbach36d4dec2009-12-01 18:10:36 +00001277}
1278
David Goodwinb062c232009-08-06 16:52:47 +00001279class T2I<dag oops, dag iops, InstrItinClass itin,
1280 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001281 : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
David Goodwinb062c232009-08-06 16:52:47 +00001282class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1283 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001284 : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>;
David Goodwinb062c232009-08-06 16:52:47 +00001285class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1286 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001287 : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>;
David Goodwinb062c232009-08-06 16:52:47 +00001288class T2Iso<dag oops, dag iops, InstrItinClass itin,
1289 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001290 : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>;
David Goodwinb062c232009-08-06 16:52:47 +00001291class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1292 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001293 : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>;
Jim Grosbach95bd6b72010-12-10 20:51:35 +00001294class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
Jim Grosbach7db8d692011-09-08 22:07:06 +00001295 string opc, string asm, string cstr, list<dag> pattern>
1296 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
Johnny Chenc28e6292009-12-15 17:24:14 +00001297 pattern> {
Owen Anderson943fb602010-12-01 19:18:46 +00001298 bits<4> Rt;
1299 bits<4> Rt2;
1300 bits<13> addr;
Jim Grosbach95bd6b72010-12-10 20:51:35 +00001301 let Inst{31-25} = 0b1110100;
1302 let Inst{24} = P;
1303 let Inst{23} = addr{8};
1304 let Inst{22} = 1;
1305 let Inst{21} = W;
1306 let Inst{20} = isLoad;
1307 let Inst{19-16} = addr{12-9};
Owen Anderson943fb602010-12-01 19:18:46 +00001308 let Inst{15-12} = Rt{3-0};
1309 let Inst{11-8} = Rt2{3-0};
Owen Anderson943fb602010-12-01 19:18:46 +00001310 let Inst{7-0} = addr{7-0};
Johnny Chenc28e6292009-12-15 17:24:14 +00001311}
Jim Grosbach7db8d692011-09-08 22:07:06 +00001312class T2Ii8s4post<bit P, bit W, bit isLoad, dag oops, dag iops,
1313 InstrItinClass itin, string opc, string asm, string cstr,
1314 list<dag> pattern>
1315 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
Owen Anderson08d4bb02011-08-04 23:18:05 +00001316 pattern> {
1317 bits<4> Rt;
1318 bits<4> Rt2;
Jim Grosbach7db8d692011-09-08 22:07:06 +00001319 bits<4> addr;
Owen Anderson08d4bb02011-08-04 23:18:05 +00001320 bits<9> imm;
1321 let Inst{31-25} = 0b1110100;
1322 let Inst{24} = P;
1323 let Inst{23} = imm{8};
1324 let Inst{22} = 1;
1325 let Inst{21} = W;
1326 let Inst{20} = isLoad;
Jim Grosbach7db8d692011-09-08 22:07:06 +00001327 let Inst{19-16} = addr;
Owen Anderson08d4bb02011-08-04 23:18:05 +00001328 let Inst{15-12} = Rt{3-0};
1329 let Inst{11-8} = Rt2{3-0};
1330 let Inst{7-0} = imm{7-0};
1331}
1332
David Goodwinb062c232009-08-06 16:52:47 +00001333class T2sI<dag oops, dag iops, InstrItinClass itin,
1334 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001335 : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
Evan Chengd76f0be2009-06-25 02:08:06 +00001336
David Goodwinb062c232009-08-06 16:52:47 +00001337class T2XI<dag oops, dag iops, InstrItinClass itin,
1338 string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001339 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
David Goodwinb062c232009-08-06 16:52:47 +00001340class T2JTI<dag oops, dag iops, InstrItinClass itin,
1341 string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001342 : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
Evan Cheng431cf562009-06-23 17:48:47 +00001343
Bruno Cardoso Lopes4d4b4902011-01-20 16:58:48 +00001344// Move to/from coprocessor instructions
Tim Northover2c45a382013-06-26 16:52:40 +00001345class T2Cop<bits<4> opc, dag oops, dag iops, string opcstr, string asm,
1346 list<dag> pattern>
1347 : T2I <oops, iops, NoItinerary, opcstr, asm, pattern>, Requires<[IsThumb2]> {
Jim Grosbachcabb48d2011-07-13 21:17:59 +00001348 let Inst{31-28} = opc;
Bruno Cardoso Lopes4d4b4902011-01-20 16:58:48 +00001349}
1350
Bob Wilson947f04b2010-03-13 01:08:20 +00001351// Two-address instructions
1352class T2XIt<dag oops, dag iops, InstrItinClass itin,
1353 string asm, string cstr, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001354 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>;
Evan Cheng83e0d482009-09-28 09:14:39 +00001355
Jim Grosbachc086f682011-09-08 00:39:19 +00001356// T2Ipreldst - Thumb2 pre-indexed load / store instructions.
1357class T2Ipreldst<bit signed, bits<2> opcod, bit load, bit pre,
Johnny Chenc28e6292009-12-15 17:24:14 +00001358 dag oops, dag iops,
1359 AddrMode am, IndexMode im, InstrItinClass itin,
Evan Cheng84c6cda2009-07-02 07:28:31 +00001360 string opc, string asm, string cstr, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001361 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
Evan Cheng84c6cda2009-07-02 07:28:31 +00001362 let OutOperandList = oops;
Chris Lattnerfb2ceed2010-03-18 21:06:54 +00001363 let InOperandList = !con(iops, (ins pred:$p));
Chris Lattner04c342e2010-10-06 00:05:18 +00001364 let AsmString = !strconcat(opc, "${p}", asm);
Evan Cheng84c6cda2009-07-02 07:28:31 +00001365 let Pattern = pattern;
1366 list<Predicate> Predicates = [IsThumb2];
Owen Andersonc78e03c2011-07-19 21:06:00 +00001367 let DecoderNamespace = "Thumb2";
Jim Grosbachc086f682011-09-08 00:39:19 +00001368
1369 bits<4> Rt;
1370 bits<13> addr;
Johnny Chenc28e6292009-12-15 17:24:14 +00001371 let Inst{31-27} = 0b11111;
1372 let Inst{26-25} = 0b00;
Bill Wendlingb70dc872010-08-31 07:50:46 +00001373 let Inst{24} = signed;
1374 let Inst{23} = 0;
Johnny Chenc28e6292009-12-15 17:24:14 +00001375 let Inst{22-21} = opcod;
Bill Wendlingb70dc872010-08-31 07:50:46 +00001376 let Inst{20} = load;
Jim Grosbachc086f682011-09-08 00:39:19 +00001377 let Inst{19-16} = addr{12-9};
1378 let Inst{15-12} = Rt{3-0};
Bill Wendlingb70dc872010-08-31 07:50:46 +00001379 let Inst{11} = 1;
Johnny Chenc28e6292009-12-15 17:24:14 +00001380 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
Bill Wendlingb70dc872010-08-31 07:50:46 +00001381 let Inst{10} = pre; // The P bit.
Jim Grosbachc086f682011-09-08 00:39:19 +00001382 let Inst{9} = addr{8}; // Sign bit
Bill Wendlingb70dc872010-08-31 07:50:46 +00001383 let Inst{8} = 1; // The W bit.
Jim Grosbachc086f682011-09-08 00:39:19 +00001384 let Inst{7-0} = addr{7-0};
Owen Andersona9ebf6f2011-09-12 18:56:30 +00001385
1386 let DecoderMethod = "DecodeT2LdStPre";
Jim Grosbachc086f682011-09-08 00:39:19 +00001387}
Jim Grosbachc4669ed2010-12-10 20:47:29 +00001388
Jim Grosbachc086f682011-09-08 00:39:19 +00001389// T2Ipostldst - Thumb2 post-indexed load / store instructions.
1390class T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre,
1391 dag oops, dag iops,
1392 AddrMode am, IndexMode im, InstrItinClass itin,
1393 string opc, string asm, string cstr, list<dag> pattern>
1394 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1395 let OutOperandList = oops;
1396 let InOperandList = !con(iops, (ins pred:$p));
1397 let AsmString = !strconcat(opc, "${p}", asm);
1398 let Pattern = pattern;
1399 list<Predicate> Predicates = [IsThumb2];
1400 let DecoderNamespace = "Thumb2";
Jim Grosbachc4669ed2010-12-10 20:47:29 +00001401
Owen Andersone22c7322010-11-30 00:14:31 +00001402 bits<4> Rt;
1403 bits<4> Rn;
Jim Grosbach3343da52011-09-08 01:01:32 +00001404 bits<9> offset;
Jim Grosbachc086f682011-09-08 00:39:19 +00001405 let Inst{31-27} = 0b11111;
1406 let Inst{26-25} = 0b00;
1407 let Inst{24} = signed;
1408 let Inst{23} = 0;
1409 let Inst{22-21} = opcod;
1410 let Inst{20} = load;
1411 let Inst{19-16} = Rn;
Owen Andersone22c7322010-11-30 00:14:31 +00001412 let Inst{15-12} = Rt{3-0};
Jim Grosbachc086f682011-09-08 00:39:19 +00001413 let Inst{11} = 1;
1414 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1415 let Inst{10} = pre; // The P bit.
Jim Grosbach3343da52011-09-08 01:01:32 +00001416 let Inst{9} = offset{8}; // Sign bit
Jim Grosbachc086f682011-09-08 00:39:19 +00001417 let Inst{8} = 1; // The W bit.
Jim Grosbach3343da52011-09-08 01:01:32 +00001418 let Inst{7-0} = offset{7-0};
Owen Andersona9ebf6f2011-09-12 18:56:30 +00001419
1420 let DecoderMethod = "DecodeT2LdStPre";
Evan Cheng84c6cda2009-07-02 07:28:31 +00001421}
1422
David Goodwine5b969f2009-07-27 19:59:26 +00001423// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1424class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
Jim Grosbachfddf36d2010-11-01 17:08:58 +00001425 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
David Goodwine5b969f2009-07-27 19:59:26 +00001426}
Evan Cheng84c6cda2009-07-02 07:28:31 +00001427
Bruno Cardoso Lopes168c9002011-05-03 17:29:22 +00001428// T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode.
1429class T2v6Pat<dag pattern, dag result> : Pat<pattern, result> {
1430 list<Predicate> Predicates = [IsThumb2, HasV6T2];
1431}
1432
Evan Chengeab9ca72009-06-27 02:26:13 +00001433// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1434class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
Evan Cheng2c450d32009-07-02 06:38:40 +00001435 list<Predicate> Predicates = [IsThumb2];
Evan Cheng431cf562009-06-23 17:48:47 +00001436}
1437
Evan Chengee98fa92008-08-29 06:41:12 +00001438//===----------------------------------------------------------------------===//
1439
Evan Chengac2af2f2008-11-11 02:11:05 +00001440//===----------------------------------------------------------------------===//
1441// ARM VFP Instruction templates.
1442//
1443
David Goodwin81cdd212009-07-10 17:03:29 +00001444// Almost all VFP instructions are predicable.
Owen Anderson651b2302011-07-13 23:22:26 +00001445class VFPI<dag oops, dag iops, AddrMode am, int sz,
David Goodwinb062c232009-08-06 16:52:47 +00001446 IndexMode im, Format f, InstrItinClass itin,
1447 string opc, string asm, string cstr, list<dag> pattern>
Anton Korobeynikov14635da2009-11-02 00:10:38 +00001448 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
Jim Grosbach576640f2010-10-12 21:22:40 +00001449 bits<4> p;
1450 let Inst{31-28} = p;
David Goodwin81cdd212009-07-10 17:03:29 +00001451 let OutOperandList = oops;
Chris Lattnerfb2ceed2010-03-18 21:06:54 +00001452 let InOperandList = !con(iops, (ins pred:$p));
Chris Lattner04c342e2010-10-06 00:05:18 +00001453 let AsmString = !strconcat(opc, "${p}", asm);
David Goodwin81cdd212009-07-10 17:03:29 +00001454 let Pattern = pattern;
Bill Wendling87240d42010-12-01 21:54:50 +00001455 let PostEncoderMethod = "VFPThumb2PostEncoder";
Owen Andersone0152a72011-08-09 20:55:18 +00001456 let DecoderNamespace = "VFP";
David Goodwin81cdd212009-07-10 17:03:29 +00001457 list<Predicate> Predicates = [HasVFP2];
1458}
1459
1460// Special cases
Owen Anderson651b2302011-07-13 23:22:26 +00001461class VFPXI<dag oops, dag iops, AddrMode am, int sz,
David Goodwinb062c232009-08-06 16:52:47 +00001462 IndexMode im, Format f, InstrItinClass itin,
1463 string asm, string cstr, list<dag> pattern>
Anton Korobeynikov14635da2009-11-02 00:10:38 +00001464 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
Bill Wendling345b48f2010-11-17 00:45:23 +00001465 bits<4> p;
1466 let Inst{31-28} = p;
David Goodwin81cdd212009-07-10 17:03:29 +00001467 let OutOperandList = oops;
1468 let InOperandList = iops;
Bob Wilson722bff22010-05-24 20:08:34 +00001469 let AsmString = asm;
David Goodwin81cdd212009-07-10 17:03:29 +00001470 let Pattern = pattern;
Bill Wendling87240d42010-12-01 21:54:50 +00001471 let PostEncoderMethod = "VFPThumb2PostEncoder";
Owen Andersone0152a72011-08-09 20:55:18 +00001472 let DecoderNamespace = "VFP";
David Goodwin81cdd212009-07-10 17:03:29 +00001473 list<Predicate> Predicates = [HasVFP2];
1474}
1475
David Goodwinb062c232009-08-06 16:52:47 +00001476class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1477 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001478 : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
Bill Wendling87240d42010-12-01 21:54:50 +00001479 opc, asm, "", pattern> {
1480 let PostEncoderMethod = "VFPThumb2PostEncoder";
1481}
David Goodwin81cdd212009-07-10 17:03:29 +00001482
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001483// ARM VFP addrmode5 loads and stores
1484class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
David Goodwinb062c232009-08-06 16:52:47 +00001485 InstrItinClass itin,
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001486 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001487 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
Bob Wilson3968c6a2010-03-23 17:23:59 +00001488 VFPLdStFrm, itin, opc, asm, "", pattern> {
Bill Wendlingc0024632010-11-04 00:59:42 +00001489 // Instruction operands.
1490 bits<5> Dd;
1491 bits<13> addr;
1492
1493 // Encode instruction operands.
1494 let Inst{23} = addr{8}; // U (add = (U == '1'))
1495 let Inst{22} = Dd{4};
1496 let Inst{19-16} = addr{12-9}; // Rn
1497 let Inst{15-12} = Dd{3-0};
1498 let Inst{7-0} = addr{7-0}; // imm8
1499
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001500 let Inst{27-24} = opcod1;
1501 let Inst{21-20} = opcod2;
Bill Wendling98c29d72010-10-12 22:03:19 +00001502 let Inst{11-9} = 0b101;
1503 let Inst{8} = 1; // Double precision
Anton Korobeynikov8cce1eb2009-11-02 00:11:06 +00001504
Evan Cheng4a8c43f2011-02-16 00:35:02 +00001505 // Loads & stores operate on both NEON and VFP pipelines.
Jakob Stoklund Olesenb93331f2010-04-05 03:10:20 +00001506 let D = VFPNeonDomain;
Evan Chengac2af2f2008-11-11 02:11:05 +00001507}
1508
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001509class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
David Goodwinb062c232009-08-06 16:52:47 +00001510 InstrItinClass itin,
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001511 string opc, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001512 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
Bob Wilson3968c6a2010-03-23 17:23:59 +00001513 VFPLdStFrm, itin, opc, asm, "", pattern> {
Bill Wendlingc0024632010-11-04 00:59:42 +00001514 // Instruction operands.
1515 bits<5> Sd;
1516 bits<13> addr;
1517
1518 // Encode instruction operands.
1519 let Inst{23} = addr{8}; // U (add = (U == '1'))
1520 let Inst{22} = Sd{0};
1521 let Inst{19-16} = addr{12-9}; // Rn
1522 let Inst{15-12} = Sd{4-1};
1523 let Inst{7-0} = addr{7-0}; // imm8
1524
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001525 let Inst{27-24} = opcod1;
1526 let Inst{21-20} = opcod2;
Bill Wendling98c29d72010-10-12 22:03:19 +00001527 let Inst{11-9} = 0b101;
1528 let Inst{8} = 0; // Single precision
Evan Cheng4a8c43f2011-02-16 00:35:02 +00001529
1530 // Loads & stores operate on both NEON and VFP pipelines.
1531 let D = VFPNeonDomain;
Evan Chengac2af2f2008-11-11 02:11:05 +00001532}
1533
Oliver Stannard65b85382016-01-25 10:26:26 +00001534class AHI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1535 InstrItinClass itin,
1536 string opc, string asm, list<dag> pattern>
Sjoerd Meijer011de9c2018-01-26 09:26:40 +00001537 : VFPI<oops, iops, AddrMode5FP16, 4, IndexModeNone,
Oliver Stannard65b85382016-01-25 10:26:26 +00001538 VFPLdStFrm, itin, opc, asm, "", pattern> {
1539 list<Predicate> Predicates = [HasFullFP16];
1540
1541 // Instruction operands.
1542 bits<5> Sd;
1543 bits<13> addr;
1544
1545 // Encode instruction operands.
1546 let Inst{23} = addr{8}; // U (add = (U == '1'))
1547 let Inst{22} = Sd{0};
1548 let Inst{19-16} = addr{12-9}; // Rn
1549 let Inst{15-12} = Sd{4-1};
1550 let Inst{7-0} = addr{7-0}; // imm8
1551
1552 let Inst{27-24} = opcod1;
1553 let Inst{21-20} = opcod2;
1554 let Inst{11-8} = 0b1001; // Half precision
1555
1556 // Loads & stores operate on both NEON and VFP pipelines.
1557 let D = VFPNeonDomain;
1558}
1559
Bob Wilson6b853c32010-09-16 00:31:02 +00001560// VFP Load / store multiple pseudo instructions.
1561class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1562 list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001563 : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain,
Bob Wilson6b853c32010-09-16 00:31:02 +00001564 cstr, itin> {
1565 let OutOperandList = oops;
1566 let InOperandList = !con(iops, (ins pred:$p));
1567 let Pattern = pattern;
1568 list<Predicate> Predicates = [HasVFP2];
1569}
1570
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001571// Load / store multiple
Tim Northover4173e292013-05-31 15:55:51 +00001572
1573// Unknown precision
1574class AXXI4<dag oops, dag iops, IndexMode im,
1575 string asm, string cstr, list<dag> pattern>
1576 : VFPXI<oops, iops, AddrMode4, 4, im,
1577 VFPLdStFrm, NoItinerary, asm, cstr, pattern> {
1578 // Instruction operands.
1579 bits<4> Rn;
1580 bits<13> regs;
1581
1582 // Encode instruction operands.
1583 let Inst{19-16} = Rn;
1584 let Inst{22} = 0;
1585 let Inst{15-12} = regs{11-8};
1586 let Inst{7-1} = regs{7-1};
1587
1588 let Inst{27-25} = 0b110;
1589 let Inst{11-8} = 0b1011;
1590 let Inst{0} = 1;
1591}
1592
1593// Double precision
Jim Grosbachabcbe242010-09-08 00:25:50 +00001594class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
Bob Wilson947f04b2010-03-13 01:08:20 +00001595 string asm, string cstr, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001596 : VFPXI<oops, iops, AddrMode4, 4, im,
Bob Wilson3968c6a2010-03-23 17:23:59 +00001597 VFPLdStMulFrm, itin, asm, cstr, pattern> {
Bill Wendling345b48f2010-11-17 00:45:23 +00001598 // Instruction operands.
1599 bits<4> Rn;
1600 bits<13> regs;
1601
1602 // Encode instruction operands.
1603 let Inst{19-16} = Rn;
1604 let Inst{22} = regs{12};
1605 let Inst{15-12} = regs{11-8};
Tim Northover4173e292013-05-31 15:55:51 +00001606 let Inst{7-1} = regs{7-1};
Bill Wendling345b48f2010-11-17 00:45:23 +00001607
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001608 let Inst{27-25} = 0b110;
Bill Wendling98c29d72010-10-12 22:03:19 +00001609 let Inst{11-9} = 0b101;
1610 let Inst{8} = 1; // Double precision
Tim Northover4173e292013-05-31 15:55:51 +00001611 let Inst{0} = 0;
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001612}
1613
Tim Northover4173e292013-05-31 15:55:51 +00001614// Single Precision
Jim Grosbachabcbe242010-09-08 00:25:50 +00001615class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
Bob Wilson947f04b2010-03-13 01:08:20 +00001616 string asm, string cstr, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00001617 : VFPXI<oops, iops, AddrMode4, 4, im,
Bob Wilson3968c6a2010-03-23 17:23:59 +00001618 VFPLdStMulFrm, itin, asm, cstr, pattern> {
Bill Wendling345b48f2010-11-17 00:45:23 +00001619 // Instruction operands.
1620 bits<4> Rn;
1621 bits<13> regs;
1622
1623 // Encode instruction operands.
1624 let Inst{19-16} = Rn;
1625 let Inst{22} = regs{8};
1626 let Inst{15-12} = regs{12-9};
1627 let Inst{7-0} = regs{7-0};
1628
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001629 let Inst{27-25} = 0b110;
Bill Wendling98c29d72010-10-12 22:03:19 +00001630 let Inst{11-9} = 0b101;
1631 let Inst{8} = 0; // Single precision
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001632}
1633
Evan Chengac2af2f2008-11-11 02:11:05 +00001634// Double precision, unary
Johnny Chen34a6afc2010-01-29 23:21:10 +00001635class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1636 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1637 string asm, list<dag> pattern>
David Goodwinb062c232009-08-06 16:52:47 +00001638 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
Bill Wendling26233432010-11-01 06:00:39 +00001639 // Instruction operands.
1640 bits<5> Dd;
1641 bits<5> Dm;
1642
1643 // Encode instruction operands.
1644 let Inst{3-0} = Dm{3-0};
1645 let Inst{5} = Dm{4};
1646 let Inst{15-12} = Dd{3-0};
1647 let Inst{22} = Dd{4};
1648
Johnny Chen34a6afc2010-01-29 23:21:10 +00001649 let Inst{27-23} = opcod1;
1650 let Inst{21-20} = opcod2;
1651 let Inst{19-16} = opcod3;
Bill Wendling98c29d72010-10-12 22:03:19 +00001652 let Inst{11-9} = 0b101;
1653 let Inst{8} = 1; // Double precision
Johnny Chen34a6afc2010-01-29 23:21:10 +00001654 let Inst{7-6} = opcod4;
1655 let Inst{4} = opcod5;
Tim Northover5620faf2013-10-24 15:49:39 +00001656
1657 let Predicates = [HasVFP2, HasDPVFP];
Evan Chengac2af2f2008-11-11 02:11:05 +00001658}
1659
Joey Gouly0f12aa22013-07-09 11:26:18 +00001660// Double precision, unary, not-predicated
1661class ADuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1662 bit opcod5, dag oops, dag iops, InstrItinClass itin,
1663 string asm, list<dag> pattern>
1664 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, VFPUnaryFrm, itin, asm, "", pattern> {
1665 // Instruction operands.
1666 bits<5> Dd;
1667 bits<5> Dm;
1668
1669 let Inst{31-28} = 0b1111;
1670
1671 // Encode instruction operands.
1672 let Inst{3-0} = Dm{3-0};
1673 let Inst{5} = Dm{4};
1674 let Inst{15-12} = Dd{3-0};
1675 let Inst{22} = Dd{4};
1676
1677 let Inst{27-23} = opcod1;
1678 let Inst{21-20} = opcod2;
1679 let Inst{19-16} = opcod3;
1680 let Inst{11-9} = 0b101;
1681 let Inst{8} = 1; // Double precision
1682 let Inst{7-6} = opcod4;
1683 let Inst{4} = opcod5;
1684}
1685
Evan Chengac2af2f2008-11-11 02:11:05 +00001686// Double precision, binary
Johnny Chen34a6afc2010-01-29 23:21:10 +00001687class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
Bob Wilson3968c6a2010-03-23 17:23:59 +00001688 dag iops, InstrItinClass itin, string opc, string asm,
1689 list<dag> pattern>
David Goodwinb062c232009-08-06 16:52:47 +00001690 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
Bill Wendling26233432010-11-01 06:00:39 +00001691 // Instruction operands.
1692 bits<5> Dd;
1693 bits<5> Dn;
1694 bits<5> Dm;
1695
1696 // Encode instruction operands.
1697 let Inst{3-0} = Dm{3-0};
1698 let Inst{5} = Dm{4};
1699 let Inst{19-16} = Dn{3-0};
1700 let Inst{7} = Dn{4};
1701 let Inst{15-12} = Dd{3-0};
1702 let Inst{22} = Dd{4};
1703
Johnny Chen34a6afc2010-01-29 23:21:10 +00001704 let Inst{27-23} = opcod1;
1705 let Inst{21-20} = opcod2;
Bill Wendling98c29d72010-10-12 22:03:19 +00001706 let Inst{11-9} = 0b101;
1707 let Inst{8} = 1; // Double precision
Bill Wendlingb70dc872010-08-31 07:50:46 +00001708 let Inst{6} = op6;
1709 let Inst{4} = op4;
Tim Northover5620faf2013-10-24 15:49:39 +00001710
1711 let Predicates = [HasVFP2, HasDPVFP];
Evan Chengac2af2f2008-11-11 02:11:05 +00001712}
1713
Joey Goulycc4ff9e2013-07-04 14:57:20 +00001714// FP, binary, not predicated
Joey Gouly2efaa732013-07-06 20:50:18 +00001715class ADbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops,
Joey Goulycc4ff9e2013-07-04 14:57:20 +00001716 InstrItinClass itin, string asm, list<dag> pattern>
Joey Gouly2d0175e2013-07-09 09:59:04 +00001717 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, VFPBinaryFrm, itin,
1718 asm, "", pattern>
Joey Goulycc4ff9e2013-07-04 14:57:20 +00001719{
1720 // Instruction operands.
1721 bits<5> Dd;
1722 bits<5> Dn;
1723 bits<5> Dm;
1724
1725 let Inst{31-28} = 0b1111;
1726
1727 // Encode instruction operands.
1728 let Inst{3-0} = Dm{3-0};
1729 let Inst{5} = Dm{4};
1730 let Inst{19-16} = Dn{3-0};
1731 let Inst{7} = Dn{4};
1732 let Inst{15-12} = Dd{3-0};
1733 let Inst{22} = Dd{4};
1734
1735 let Inst{27-23} = opcod1;
1736 let Inst{21-20} = opcod2;
1737 let Inst{11-9} = 0b101;
1738 let Inst{8} = 1; // double precision
Joey Gouly2efaa732013-07-06 20:50:18 +00001739 let Inst{6} = opcod3;
Joey Goulycc4ff9e2013-07-04 14:57:20 +00001740 let Inst{4} = 0;
Tim Northover5620faf2013-10-24 15:49:39 +00001741
1742 let Predicates = [HasVFP2, HasDPVFP];
Joey Goulycc4ff9e2013-07-04 14:57:20 +00001743}
1744
Joey Gouly2d0175e2013-07-09 09:59:04 +00001745// Single precision, unary, predicated
Johnny Chen34a6afc2010-01-29 23:21:10 +00001746class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1747 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1748 string asm, list<dag> pattern>
David Goodwinb062c232009-08-06 16:52:47 +00001749 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
Bill Wendling26233432010-11-01 06:00:39 +00001750 // Instruction operands.
1751 bits<5> Sd;
1752 bits<5> Sm;
1753
1754 // Encode instruction operands.
1755 let Inst{3-0} = Sm{4-1};
1756 let Inst{5} = Sm{0};
1757 let Inst{15-12} = Sd{4-1};
1758 let Inst{22} = Sd{0};
1759
Johnny Chen34a6afc2010-01-29 23:21:10 +00001760 let Inst{27-23} = opcod1;
1761 let Inst{21-20} = opcod2;
1762 let Inst{19-16} = opcod3;
Bill Wendling98c29d72010-10-12 22:03:19 +00001763 let Inst{11-9} = 0b101;
1764 let Inst{8} = 0; // Single precision
Johnny Chen34a6afc2010-01-29 23:21:10 +00001765 let Inst{7-6} = opcod4;
1766 let Inst{4} = opcod5;
Evan Chengac2af2f2008-11-11 02:11:05 +00001767}
1768
Joey Gouly2d0175e2013-07-09 09:59:04 +00001769// Single precision, unary, non-predicated
1770class ASuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1771 bit opcod5, dag oops, dag iops, InstrItinClass itin,
1772 string asm, list<dag> pattern>
1773 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone,
1774 VFPUnaryFrm, itin, asm, "", pattern> {
1775 // Instruction operands.
1776 bits<5> Sd;
1777 bits<5> Sm;
1778
1779 let Inst{31-28} = 0b1111;
1780
1781 // Encode instruction operands.
1782 let Inst{3-0} = Sm{4-1};
1783 let Inst{5} = Sm{0};
1784 let Inst{15-12} = Sd{4-1};
1785 let Inst{22} = Sd{0};
1786
1787 let Inst{27-23} = opcod1;
1788 let Inst{21-20} = opcod2;
1789 let Inst{19-16} = opcod3;
1790 let Inst{11-9} = 0b101;
1791 let Inst{8} = 0; // Single precision
1792 let Inst{7-6} = opcod4;
1793 let Inst{4} = opcod5;
1794}
1795
Bill Wendlingcbb08ca2010-12-01 02:42:55 +00001796// Single precision unary, if no NEON. Same as ASuI except not available if
1797// NEON is enabled.
Johnny Chen34a6afc2010-01-29 23:21:10 +00001798class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1799 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1800 string asm, list<dag> pattern>
1801 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1802 pattern> {
David Goodwin30bf6252009-08-04 20:39:05 +00001803 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1804}
1805
Evan Chengac2af2f2008-11-11 02:11:05 +00001806// Single precision, binary
Johnny Chen34a6afc2010-01-29 23:21:10 +00001807class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1808 InstrItinClass itin, string opc, string asm, list<dag> pattern>
David Goodwinb062c232009-08-06 16:52:47 +00001809 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
Bill Wendling26233432010-11-01 06:00:39 +00001810 // Instruction operands.
1811 bits<5> Sd;
1812 bits<5> Sn;
1813 bits<5> Sm;
1814
1815 // Encode instruction operands.
1816 let Inst{3-0} = Sm{4-1};
1817 let Inst{5} = Sm{0};
1818 let Inst{19-16} = Sn{4-1};
1819 let Inst{7} = Sn{0};
1820 let Inst{15-12} = Sd{4-1};
1821 let Inst{22} = Sd{0};
1822
Johnny Chen34a6afc2010-01-29 23:21:10 +00001823 let Inst{27-23} = opcod1;
1824 let Inst{21-20} = opcod2;
Bill Wendling98c29d72010-10-12 22:03:19 +00001825 let Inst{11-9} = 0b101;
1826 let Inst{8} = 0; // Single precision
Bill Wendlingb70dc872010-08-31 07:50:46 +00001827 let Inst{6} = op6;
1828 let Inst{4} = op4;
Evan Chengac2af2f2008-11-11 02:11:05 +00001829}
1830
Joey Goulycc4ff9e2013-07-04 14:57:20 +00001831// Single precision, binary, not predicated
Joey Gouly2efaa732013-07-06 20:50:18 +00001832class ASbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops,
Joey Goulycc4ff9e2013-07-04 14:57:20 +00001833 InstrItinClass itin, string asm, list<dag> pattern>
1834 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone,
1835 VFPBinaryFrm, itin, asm, "", pattern>
1836{
1837 // Instruction operands.
1838 bits<5> Sd;
1839 bits<5> Sn;
1840 bits<5> Sm;
1841
1842 let Inst{31-28} = 0b1111;
1843
1844 // Encode instruction operands.
1845 let Inst{3-0} = Sm{4-1};
1846 let Inst{5} = Sm{0};
1847 let Inst{19-16} = Sn{4-1};
1848 let Inst{7} = Sn{0};
1849 let Inst{15-12} = Sd{4-1};
1850 let Inst{22} = Sd{0};
1851
1852 let Inst{27-23} = opcod1;
1853 let Inst{21-20} = opcod2;
1854 let Inst{11-9} = 0b101;
1855 let Inst{8} = 0; // Single precision
Joey Gouly2efaa732013-07-06 20:50:18 +00001856 let Inst{6} = opcod3;
Joey Goulycc4ff9e2013-07-04 14:57:20 +00001857 let Inst{4} = 0;
1858}
1859
Bill Wendlingcbb08ca2010-12-01 02:42:55 +00001860// Single precision binary, if no NEON. Same as ASbI except not available if
1861// NEON is enabled.
Johnny Chen34a6afc2010-01-29 23:21:10 +00001862class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
Bob Wilson3968c6a2010-03-23 17:23:59 +00001863 dag iops, InstrItinClass itin, string opc, string asm,
1864 list<dag> pattern>
Johnny Chen34a6afc2010-01-29 23:21:10 +00001865 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
David Goodwin3b9c52c2009-08-04 17:53:06 +00001866 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
Bill Wendling26233432010-11-01 06:00:39 +00001867
1868 // Instruction operands.
1869 bits<5> Sd;
1870 bits<5> Sn;
1871 bits<5> Sm;
1872
1873 // Encode instruction operands.
1874 let Inst{3-0} = Sm{4-1};
1875 let Inst{5} = Sm{0};
1876 let Inst{19-16} = Sn{4-1};
1877 let Inst{7} = Sn{0};
1878 let Inst{15-12} = Sd{4-1};
1879 let Inst{22} = Sd{0};
David Goodwin3b9c52c2009-08-04 17:53:06 +00001880}
1881
Oliver Stannard65b85382016-01-25 10:26:26 +00001882// Half precision, unary, predicated
1883class AHuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1884 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1885 string asm, list<dag> pattern>
1886 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1887 list<Predicate> Predicates = [HasFullFP16];
1888
1889 // Instruction operands.
1890 bits<5> Sd;
1891 bits<5> Sm;
1892
1893 // Encode instruction operands.
1894 let Inst{3-0} = Sm{4-1};
1895 let Inst{5} = Sm{0};
1896 let Inst{15-12} = Sd{4-1};
1897 let Inst{22} = Sd{0};
1898
1899 let Inst{27-23} = opcod1;
1900 let Inst{21-20} = opcod2;
1901 let Inst{19-16} = opcod3;
1902 let Inst{11-8} = 0b1001; // Half precision
1903 let Inst{7-6} = opcod4;
1904 let Inst{4} = opcod5;
1905}
1906
1907// Half precision, unary, non-predicated
1908class AHuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1909 bit opcod5, dag oops, dag iops, InstrItinClass itin,
1910 string asm, list<dag> pattern>
1911 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone,
1912 VFPUnaryFrm, itin, asm, "", pattern> {
1913 list<Predicate> Predicates = [HasFullFP16];
1914
1915 // Instruction operands.
1916 bits<5> Sd;
1917 bits<5> Sm;
1918
1919 let Inst{31-28} = 0b1111;
1920
1921 // Encode instruction operands.
1922 let Inst{3-0} = Sm{4-1};
1923 let Inst{5} = Sm{0};
1924 let Inst{15-12} = Sd{4-1};
1925 let Inst{22} = Sd{0};
1926
1927 let Inst{27-23} = opcod1;
1928 let Inst{21-20} = opcod2;
1929 let Inst{19-16} = opcod3;
1930 let Inst{11-8} = 0b1001; // Half precision
1931 let Inst{7-6} = opcod4;
1932 let Inst{4} = opcod5;
1933}
1934
1935// Half precision, binary
1936class AHbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1937 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1938 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1939 list<Predicate> Predicates = [HasFullFP16];
1940
1941 // Instruction operands.
1942 bits<5> Sd;
1943 bits<5> Sn;
1944 bits<5> Sm;
1945
1946 // Encode instruction operands.
1947 let Inst{3-0} = Sm{4-1};
1948 let Inst{5} = Sm{0};
1949 let Inst{19-16} = Sn{4-1};
1950 let Inst{7} = Sn{0};
1951 let Inst{15-12} = Sd{4-1};
1952 let Inst{22} = Sd{0};
1953
1954 let Inst{27-23} = opcod1;
1955 let Inst{21-20} = opcod2;
1956 let Inst{11-8} = 0b1001; // Half precision
1957 let Inst{6} = op6;
1958 let Inst{4} = op4;
1959}
1960
1961// Half precision, binary, not predicated
1962class AHbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops,
1963 InstrItinClass itin, string asm, list<dag> pattern>
1964 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone,
1965 VFPBinaryFrm, itin, asm, "", pattern> {
1966 list<Predicate> Predicates = [HasFullFP16];
1967
1968 // Instruction operands.
1969 bits<5> Sd;
1970 bits<5> Sn;
1971 bits<5> Sm;
1972
1973 let Inst{31-28} = 0b1111;
1974
1975 // Encode instruction operands.
1976 let Inst{3-0} = Sm{4-1};
1977 let Inst{5} = Sm{0};
1978 let Inst{19-16} = Sn{4-1};
1979 let Inst{7} = Sn{0};
1980 let Inst{15-12} = Sd{4-1};
1981 let Inst{22} = Sd{0};
1982
1983 let Inst{27-23} = opcod1;
1984 let Inst{21-20} = opcod2;
1985 let Inst{11-8} = 0b1001; // Half precision
1986 let Inst{6} = opcod3;
1987 let Inst{4} = 0;
1988}
1989
Evan Cheng4b6c7ef2008-11-12 06:41:41 +00001990// VFP conversion instructions
Johnny Chen34a6afc2010-01-29 23:21:10 +00001991class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1992 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1993 list<dag> pattern>
David Goodwinb062c232009-08-06 16:52:47 +00001994 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
Johnny Chen34a6afc2010-01-29 23:21:10 +00001995 let Inst{27-23} = opcod1;
1996 let Inst{21-20} = opcod2;
1997 let Inst{19-16} = opcod3;
1998 let Inst{11-8} = opcod4;
Evan Cheng4b6c7ef2008-11-12 06:41:41 +00001999 let Inst{6} = 1;
Johnny Chen34a6afc2010-01-29 23:21:10 +00002000 let Inst{4} = 0;
Evan Cheng4b6c7ef2008-11-12 06:41:41 +00002001}
2002
Johnny Chen39640592010-02-11 18:47:03 +00002003// VFP conversion between floating-point and fixed-point
2004class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
Bob Wilson3968c6a2010-03-23 17:23:59 +00002005 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
2006 list<dag> pattern>
Johnny Chen39640592010-02-11 18:47:03 +00002007 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
Jim Grosbachf0d25112011-12-22 19:55:21 +00002008 bits<5> fbits;
Johnny Chen39640592010-02-11 18:47:03 +00002009 // size (fixed-point number): sx == 0 ? 16 : 32
2010 let Inst{7} = op5; // sx
Jim Grosbachf0d25112011-12-22 19:55:21 +00002011 let Inst{5} = fbits{0};
2012 let Inst{3-0} = fbits{4-1};
Johnny Chen39640592010-02-11 18:47:03 +00002013}
2014
David Goodwin85b5b022009-08-10 22:17:39 +00002015// VFP conversion instructions, if no NEON
Johnny Chen34a6afc2010-01-29 23:21:10 +00002016class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
David Goodwin85b5b022009-08-10 22:17:39 +00002017 dag oops, dag iops, InstrItinClass itin,
2018 string opc, string asm, list<dag> pattern>
Johnny Chen34a6afc2010-01-29 23:21:10 +00002019 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
2020 pattern> {
David Goodwin85b5b022009-08-10 22:17:39 +00002021 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
2022}
2023
Evan Cheng4b6c7ef2008-11-12 06:41:41 +00002024class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
David Goodwinb062c232009-08-06 16:52:47 +00002025 InstrItinClass itin,
2026 string opc, string asm, list<dag> pattern>
2027 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
Evan Cheng4b6c7ef2008-11-12 06:41:41 +00002028 let Inst{27-20} = opcod1;
Evan Cheng38c9a142008-11-11 19:40:26 +00002029 let Inst{11-8} = opcod2;
2030 let Inst{4} = 1;
2031}
2032
David Goodwinb062c232009-08-06 16:52:47 +00002033class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
2034 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2035 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
Evan Cheng97ccab82008-11-11 22:46:12 +00002036
Bob Wilson3968c6a2010-03-23 17:23:59 +00002037class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
David Goodwinb062c232009-08-06 16:52:47 +00002038 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2039 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
Evan Cheng4b6c7ef2008-11-12 06:41:41 +00002040
David Goodwinb062c232009-08-06 16:52:47 +00002041class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
2042 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2043 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
Evan Cheng4b6c7ef2008-11-12 06:41:41 +00002044
David Goodwinb062c232009-08-06 16:52:47 +00002045class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
2046 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2047 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
Evan Cheng38c9a142008-11-11 19:40:26 +00002048
Evan Chengac2af2f2008-11-11 02:11:05 +00002049//===----------------------------------------------------------------------===//
2050
Bob Wilson2e076c42009-06-22 23:27:02 +00002051//===----------------------------------------------------------------------===//
2052// ARM NEON Instruction templates.
2053//
Evan Chengee98fa92008-08-29 06:41:12 +00002054
Johnny Chenf833fad2010-03-20 00:17:00 +00002055class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
2056 InstrItinClass itin, string opc, string dt, string asm, string cstr,
2057 list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00002058 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
Evan Cheng738a97a2009-11-23 21:57:23 +00002059 let OutOperandList = oops;
Chris Lattnerfb2ceed2010-03-18 21:06:54 +00002060 let InOperandList = !con(iops, (ins pred:$p));
Chris Lattner04c342e2010-10-06 00:05:18 +00002061 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
Evan Cheng738a97a2009-11-23 21:57:23 +00002062 let Pattern = pattern;
2063 list<Predicate> Predicates = [HasNEON];
Owen Andersona6201f02011-08-15 23:38:54 +00002064 let DecoderNamespace = "NEON";
Evan Cheng738a97a2009-11-23 21:57:23 +00002065}
2066
2067// Same as NeonI except it does not have a "data type" specifier.
Johnny Chen020023a2010-03-23 20:40:44 +00002068class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
2069 InstrItinClass itin, string opc, string asm, string cstr,
2070 list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00002071 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
Bob Wilson2e076c42009-06-22 23:27:02 +00002072 let OutOperandList = oops;
Chris Lattnerfb2ceed2010-03-18 21:06:54 +00002073 let InOperandList = !con(iops, (ins pred:$p));
Chris Lattner04c342e2010-10-06 00:05:18 +00002074 let AsmString = !strconcat(opc, "${p}", "\t", asm);
Bob Wilson2e076c42009-06-22 23:27:02 +00002075 let Pattern = pattern;
2076 list<Predicate> Predicates = [HasNEON];
Owen Andersona6201f02011-08-15 23:38:54 +00002077 let DecoderNamespace = "NEON";
Evan Chengee98fa92008-08-29 06:41:12 +00002078}
2079
Joey Goulydf686002013-07-17 13:59:38 +00002080// Same as NeonI except it is not predicated
2081class NeonInp<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
2082 InstrItinClass itin, string opc, string dt, string asm, string cstr,
2083 list<dag> pattern>
2084 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
2085 let OutOperandList = oops;
2086 let InOperandList = iops;
2087 let AsmString = !strconcat(opc, ".", dt, "\t", asm);
2088 let Pattern = pattern;
2089 list<Predicate> Predicates = [HasNEON];
2090 let DecoderNamespace = "NEON";
2091
2092 let Inst{31-28} = 0b1111;
2093}
2094
Bob Wilson50820a22009-10-07 21:53:04 +00002095class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
2096 dag oops, dag iops, InstrItinClass itin,
Evan Cheng738a97a2009-11-23 21:57:23 +00002097 string opc, string dt, string asm, string cstr, list<dag> pattern>
Johnny Chenf833fad2010-03-20 00:17:00 +00002098 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
2099 cstr, pattern> {
Bob Wilsonf731a2d2009-07-08 18:11:30 +00002100 let Inst{31-24} = 0b11110100;
Bill Wendlingb70dc872010-08-31 07:50:46 +00002101 let Inst{23} = op23;
Jim Grosbach68f495c2009-10-20 00:19:08 +00002102 let Inst{21-20} = op21_20;
Bill Wendlingb70dc872010-08-31 07:50:46 +00002103 let Inst{11-8} = op11_8;
2104 let Inst{7-4} = op7_4;
Jim Grosbach5876e412010-11-19 22:42:55 +00002105
Chris Lattner63274cb2010-11-15 05:19:05 +00002106 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
Owen Andersonc86a5bd2011-08-10 19:01:10 +00002107 let DecoderNamespace = "NEONLoadStore";
Jim Grosbach5876e412010-11-19 22:42:55 +00002108
Owen Andersonad402342010-11-02 00:05:05 +00002109 bits<5> Vd;
Owen Anderson0ebd1fd2010-11-02 23:47:29 +00002110 bits<6> Rn;
2111 bits<4> Rm;
Jim Grosbach5876e412010-11-19 22:42:55 +00002112
Owen Andersonad402342010-11-02 00:05:05 +00002113 let Inst{22} = Vd{4};
2114 let Inst{15-12} = Vd{3-0};
Owen Anderson0ebd1fd2010-11-02 23:47:29 +00002115 let Inst{19-16} = Rn{3-0};
2116 let Inst{3-0} = Rm{3-0};
Bob Wilsonf731a2d2009-07-08 18:11:30 +00002117}
2118
Owen Anderson9f20daf2010-11-02 20:47:39 +00002119class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
2120 dag oops, dag iops, InstrItinClass itin,
2121 string opc, string dt, string asm, string cstr, list<dag> pattern>
2122 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
2123 dt, asm, cstr, pattern> {
2124 bits<3> lane;
2125}
2126
Bob Wilson9392b0e2010-08-25 23:27:42 +00002127class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
Owen Anderson651b2302011-07-13 23:22:26 +00002128 : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
Bob Wilson9392b0e2010-08-25 23:27:42 +00002129 itin> {
2130 let OutOperandList = oops;
2131 let InOperandList = !con(iops, (ins pred:$p));
2132 list<Predicate> Predicates = [HasNEON];
2133}
2134
Jim Grosbach233b3a22010-10-06 20:36:55 +00002135class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
2136 list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00002137 : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
Bob Wilsonc597fd3b2010-09-13 23:55:10 +00002138 itin> {
2139 let OutOperandList = oops;
2140 let InOperandList = !con(iops, (ins pred:$p));
Jim Grosbach233b3a22010-10-06 20:36:55 +00002141 let Pattern = pattern;
Bob Wilsonc597fd3b2010-09-13 23:55:10 +00002142 list<Predicate> Predicates = [HasNEON];
2143}
2144
Johnny Chenac5024b2010-03-23 16:43:47 +00002145class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
Evan Cheng738a97a2009-11-23 21:57:23 +00002146 string opc, string dt, string asm, string cstr, list<dag> pattern>
Johnny Chenac5024b2010-03-23 16:43:47 +00002147 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
2148 pattern> {
Evan Cheng738a97a2009-11-23 21:57:23 +00002149 let Inst{31-25} = 0b1111001;
Chris Lattner63274cb2010-11-15 05:19:05 +00002150 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
Owen Andersona6201f02011-08-15 23:38:54 +00002151 let DecoderNamespace = "NEONData";
Evan Cheng738a97a2009-11-23 21:57:23 +00002152}
2153
Johnny Chen020023a2010-03-23 20:40:44 +00002154class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
Bob Wilson3968c6a2010-03-23 17:23:59 +00002155 string opc, string asm, string cstr, list<dag> pattern>
Johnny Chen020023a2010-03-23 20:40:44 +00002156 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
Bob Wilson3968c6a2010-03-23 17:23:59 +00002157 cstr, pattern> {
Bob Wilson2e076c42009-06-22 23:27:02 +00002158 let Inst{31-25} = 0b1111001;
Owen Andersonb538a222010-12-10 22:32:08 +00002159 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
Owen Andersona6201f02011-08-15 23:38:54 +00002160 let DecoderNamespace = "NEONData";
Bob Wilson2e076c42009-06-22 23:27:02 +00002161}
2162
2163// NEON "one register and a modified immediate" format.
2164class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
2165 bit op5, bit op4,
David Goodwinb062c232009-08-06 16:52:47 +00002166 dag oops, dag iops, InstrItinClass itin,
Bob Wilson3968c6a2010-03-23 17:23:59 +00002167 string opc, string dt, string asm, string cstr,
2168 list<dag> pattern>
Johnny Chen6a643202010-03-23 23:09:14 +00002169 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
Bill Wendlingb70dc872010-08-31 07:50:46 +00002170 let Inst{23} = op23;
Bob Wilson2e076c42009-06-22 23:27:02 +00002171 let Inst{21-19} = op21_19;
Bill Wendlingb70dc872010-08-31 07:50:46 +00002172 let Inst{11-8} = op11_8;
2173 let Inst{7} = op7;
2174 let Inst{6} = op6;
2175 let Inst{5} = op5;
2176 let Inst{4} = op4;
Jim Grosbach5876e412010-11-19 22:42:55 +00002177
Owen Anderson284cb362010-10-26 17:40:54 +00002178 // Instruction operands.
2179 bits<5> Vd;
2180 bits<13> SIMM;
Jim Grosbach5876e412010-11-19 22:42:55 +00002181
Owen Anderson284cb362010-10-26 17:40:54 +00002182 let Inst{15-12} = Vd{3-0};
2183 let Inst{22} = Vd{4};
2184 let Inst{24} = SIMM{7};
2185 let Inst{18-16} = SIMM{6-4};
2186 let Inst{3-0} = SIMM{3-0};
Owen Andersone0152a72011-08-09 20:55:18 +00002187 let DecoderMethod = "DecodeNEONModImmInstruction";
Bob Wilson2e076c42009-06-22 23:27:02 +00002188}
2189
2190// NEON 2 vector register format.
2191class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
2192 bits<5> op11_7, bit op6, bit op4,
David Goodwinb062c232009-08-06 16:52:47 +00002193 dag oops, dag iops, InstrItinClass itin,
Evan Cheng738a97a2009-11-23 21:57:23 +00002194 string opc, string dt, string asm, string cstr, list<dag> pattern>
Johnny Chen9b1f60a2010-03-24 00:57:50 +00002195 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
Evan Cheng738a97a2009-11-23 21:57:23 +00002196 let Inst{24-23} = op24_23;
2197 let Inst{21-20} = op21_20;
2198 let Inst{19-18} = op19_18;
2199 let Inst{17-16} = op17_16;
Bill Wendlingb70dc872010-08-31 07:50:46 +00002200 let Inst{11-7} = op11_7;
2201 let Inst{6} = op6;
2202 let Inst{4} = op4;
Jim Grosbach5876e412010-11-19 22:42:55 +00002203
Owen Anderson24774462010-10-25 18:43:52 +00002204 // Instruction operands.
2205 bits<5> Vd;
2206 bits<5> Vm;
2207
2208 let Inst{15-12} = Vd{3-0};
2209 let Inst{22} = Vd{4};
2210 let Inst{3-0} = Vm{3-0};
2211 let Inst{5} = Vm{4};
Evan Cheng738a97a2009-11-23 21:57:23 +00002212}
2213
Joey Gouly943dd592013-07-18 11:53:22 +00002214// Same as N2V but not predicated.
Amara Emerson33089092013-09-19 11:59:01 +00002215class N2Vnp<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
Joey Gouly943dd592013-07-18 11:53:22 +00002216 dag oops, dag iops, InstrItinClass itin, string OpcodeStr,
Tim Northover6ad1f5c2014-04-28 13:53:00 +00002217 string Dt, list<dag> pattern>
Joey Gouly943dd592013-07-18 11:53:22 +00002218 : NeonInp<oops, iops, AddrModeNone, IndexModeNone, N2RegFrm, itin,
2219 OpcodeStr, Dt, "$Vd, $Vm", "", pattern> {
2220 bits<5> Vd;
2221 bits<5> Vm;
2222
2223 // Encode instruction operands
2224 let Inst{22} = Vd{4};
2225 let Inst{15-12} = Vd{3-0};
2226 let Inst{5} = Vm{4};
2227 let Inst{3-0} = Vm{3-0};
2228
2229 // Encode constant bits
2230 let Inst{27-23} = 0b00111;
2231 let Inst{21-20} = 0b11;
Amara Emerson33089092013-09-19 11:59:01 +00002232 let Inst{19-18} = op19_18;
Joey Gouly943dd592013-07-18 11:53:22 +00002233 let Inst{17-16} = op17_16;
2234 let Inst{11} = 0;
2235 let Inst{10-8} = op10_8;
2236 let Inst{7} = op7;
2237 let Inst{6} = op6;
2238 let Inst{4} = 0;
2239
2240 let DecoderNamespace = "NEON";
2241}
2242
Evan Cheng738a97a2009-11-23 21:57:23 +00002243// Same as N2V except it doesn't have a datatype suffix.
2244class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
Bob Wilson3968c6a2010-03-23 17:23:59 +00002245 bits<5> op11_7, bit op6, bit op4,
2246 dag oops, dag iops, InstrItinClass itin,
2247 string opc, string asm, string cstr, list<dag> pattern>
Johnny Chen9b1f60a2010-03-24 00:57:50 +00002248 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
Bob Wilson2e076c42009-06-22 23:27:02 +00002249 let Inst{24-23} = op24_23;
2250 let Inst{21-20} = op21_20;
2251 let Inst{19-18} = op19_18;
2252 let Inst{17-16} = op17_16;
Bill Wendlingb70dc872010-08-31 07:50:46 +00002253 let Inst{11-7} = op11_7;
2254 let Inst{6} = op6;
2255 let Inst{4} = op4;
Jim Grosbach5876e412010-11-19 22:42:55 +00002256
Owen Anderson24774462010-10-25 18:43:52 +00002257 // Instruction operands.
2258 bits<5> Vd;
2259 bits<5> Vm;
2260
2261 let Inst{15-12} = Vd{3-0};
2262 let Inst{22} = Vd{4};
2263 let Inst{3-0} = Vm{3-0};
2264 let Inst{5} = Vm{4};
Bob Wilson2e076c42009-06-22 23:27:02 +00002265}
2266
2267// NEON 2 vector register with immediate.
Bob Wilsonbd3650c2009-10-21 02:15:46 +00002268class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
Johnny Chend82f9002010-03-25 20:39:04 +00002269 dag oops, dag iops, Format f, InstrItinClass itin,
Evan Cheng738a97a2009-11-23 21:57:23 +00002270 string opc, string dt, string asm, string cstr, list<dag> pattern>
Johnny Chend82f9002010-03-25 20:39:04 +00002271 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
Bill Wendlingb70dc872010-08-31 07:50:46 +00002272 let Inst{24} = op24;
2273 let Inst{23} = op23;
Bob Wilson2e076c42009-06-22 23:27:02 +00002274 let Inst{11-8} = op11_8;
Bill Wendlingb70dc872010-08-31 07:50:46 +00002275 let Inst{7} = op7;
2276 let Inst{6} = op6;
2277 let Inst{4} = op4;
Jim Grosbach5876e412010-11-19 22:42:55 +00002278
Owen Anderson3665fee2010-10-26 20:56:57 +00002279 // Instruction operands.
2280 bits<5> Vd;
2281 bits<5> Vm;
2282 bits<6> SIMM;
2283
2284 let Inst{15-12} = Vd{3-0};
2285 let Inst{22} = Vd{4};
2286 let Inst{3-0} = Vm{3-0};
2287 let Inst{5} = Vm{4};
2288 let Inst{21-16} = SIMM{5-0};
Bob Wilson2e076c42009-06-22 23:27:02 +00002289}
2290
Bob Wilsoncf603fb2010-03-27 03:56:52 +00002291// NEON 3 vector register format.
Owen Andersonabda3ca2011-03-30 23:45:29 +00002292
Jim Grosbacheca54e42011-05-19 17:34:53 +00002293class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2294 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
2295 string opc, string dt, string asm, string cstr,
2296 list<dag> pattern>
Johnny Chen2cf04952010-03-26 21:26:28 +00002297 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
Bill Wendlingb70dc872010-08-31 07:50:46 +00002298 let Inst{24} = op24;
2299 let Inst{23} = op23;
Evan Cheng738a97a2009-11-23 21:57:23 +00002300 let Inst{21-20} = op21_20;
Bill Wendlingb70dc872010-08-31 07:50:46 +00002301 let Inst{11-8} = op11_8;
2302 let Inst{6} = op6;
2303 let Inst{4} = op4;
Owen Andersonabda3ca2011-03-30 23:45:29 +00002304}
2305
2306class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
2307 dag oops, dag iops, Format f, InstrItinClass itin,
2308 string opc, string dt, string asm, string cstr, list<dag> pattern>
2309 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
2310 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
Owen Anderson9e44cf22010-10-21 20:21:49 +00002311 // Instruction operands.
2312 bits<5> Vd;
2313 bits<5> Vn;
2314 bits<5> Vm;
2315
2316 let Inst{15-12} = Vd{3-0};
2317 let Inst{22} = Vd{4};
2318 let Inst{19-16} = Vn{3-0};
2319 let Inst{7} = Vn{4};
2320 let Inst{3-0} = Vm{3-0};
2321 let Inst{5} = Vm{4};
Evan Cheng738a97a2009-11-23 21:57:23 +00002322}
2323
Joey Goulydf686002013-07-17 13:59:38 +00002324class N3Vnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2325 bit op4, dag oops, dag iops,Format f, InstrItinClass itin,
Tim Northover6ad1f5c2014-04-28 13:53:00 +00002326 string OpcodeStr, string Dt, list<dag> pattern>
Joey Goulydf686002013-07-17 13:59:38 +00002327 : NeonInp<oops, iops, AddrModeNone, IndexModeNone, f, itin, OpcodeStr,
2328 Dt, "$Vd, $Vn, $Vm", "", pattern> {
2329 bits<5> Vd;
2330 bits<5> Vn;
2331 bits<5> Vm;
2332
2333 // Encode instruction operands
2334 let Inst{22} = Vd{4};
2335 let Inst{15-12} = Vd{3-0};
2336 let Inst{19-16} = Vn{3-0};
2337 let Inst{7} = Vn{4};
2338 let Inst{5} = Vm{4};
2339 let Inst{3-0} = Vm{3-0};
2340
2341 // Encode constant bits
2342 let Inst{27-23} = op27_23;
2343 let Inst{21-20} = op21_20;
2344 let Inst{11-8} = op11_8;
2345 let Inst{6} = op6;
2346 let Inst{4} = op4;
2347}
2348
Jim Grosbacheca54e42011-05-19 17:34:53 +00002349class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2350 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
2351 string opc, string dt, string asm, string cstr,
2352 list<dag> pattern>
Owen Andersonabda3ca2011-03-30 23:45:29 +00002353 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
2354 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
2355
2356 // Instruction operands.
2357 bits<5> Vd;
2358 bits<5> Vn;
2359 bits<5> Vm;
2360 bit lane;
2361
2362 let Inst{15-12} = Vd{3-0};
2363 let Inst{22} = Vd{4};
2364 let Inst{19-16} = Vn{3-0};
2365 let Inst{7} = Vn{4};
2366 let Inst{3-0} = Vm{3-0};
2367 let Inst{5} = lane;
2368}
2369
Jim Grosbacheca54e42011-05-19 17:34:53 +00002370class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2371 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
2372 string opc, string dt, string asm, string cstr,
2373 list<dag> pattern>
Owen Andersonabda3ca2011-03-30 23:45:29 +00002374 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
2375 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
2376
2377 // Instruction operands.
2378 bits<5> Vd;
2379 bits<5> Vn;
2380 bits<5> Vm;
2381 bits<2> lane;
2382
2383 let Inst{15-12} = Vd{3-0};
2384 let Inst{22} = Vd{4};
2385 let Inst{19-16} = Vn{3-0};
2386 let Inst{7} = Vn{4};
2387 let Inst{2-0} = Vm{2-0};
2388 let Inst{5} = lane{1};
2389 let Inst{3} = lane{0};
2390}
2391
Johnny Chen8a687232010-03-23 21:35:03 +00002392// Same as N3V except it doesn't have a data type suffix.
Bob Wilson3968c6a2010-03-23 17:23:59 +00002393class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2394 bit op4,
Bob Wilsoncf603fb2010-03-27 03:56:52 +00002395 dag oops, dag iops, Format f, InstrItinClass itin,
Bob Wilson3968c6a2010-03-23 17:23:59 +00002396 string opc, string asm, string cstr, list<dag> pattern>
Bob Wilsoncf603fb2010-03-27 03:56:52 +00002397 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
Bill Wendlingb70dc872010-08-31 07:50:46 +00002398 let Inst{24} = op24;
2399 let Inst{23} = op23;
Bob Wilson2e076c42009-06-22 23:27:02 +00002400 let Inst{21-20} = op21_20;
Bill Wendlingb70dc872010-08-31 07:50:46 +00002401 let Inst{11-8} = op11_8;
2402 let Inst{6} = op6;
2403 let Inst{4} = op4;
Jim Grosbach5876e412010-11-19 22:42:55 +00002404
Owen Andersondff239c2010-10-25 18:28:30 +00002405 // Instruction operands.
2406 bits<5> Vd;
2407 bits<5> Vn;
2408 bits<5> Vm;
2409
2410 let Inst{15-12} = Vd{3-0};
2411 let Inst{22} = Vd{4};
2412 let Inst{19-16} = Vn{3-0};
2413 let Inst{7} = Vn{4};
2414 let Inst{3-0} = Vm{3-0};
2415 let Inst{5} = Vm{4};
Bob Wilson2e076c42009-06-22 23:27:02 +00002416}
2417
2418// NEON VMOVs between scalar and core registers.
2419class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
David Goodwinb062c232009-08-06 16:52:47 +00002420 dag oops, dag iops, Format f, InstrItinClass itin,
Evan Cheng738a97a2009-11-23 21:57:23 +00002421 string opc, string dt, string asm, list<dag> pattern>
Owen Anderson651b2302011-07-13 23:22:26 +00002422 : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain,
Bob Wilson3968c6a2010-03-23 17:23:59 +00002423 "", itin> {
Bob Wilson2e076c42009-06-22 23:27:02 +00002424 let Inst{27-20} = opcod1;
Bill Wendlingb70dc872010-08-31 07:50:46 +00002425 let Inst{11-8} = opcod2;
2426 let Inst{6-5} = opcod3;
2427 let Inst{4} = 1;
Johnny Chen8bca1742011-04-06 18:27:46 +00002428 // A8.6.303, A8.6.328, A8.6.329
2429 let Inst{3-0} = 0b0000;
Evan Cheng738a97a2009-11-23 21:57:23 +00002430
2431 let OutOperandList = oops;
Chris Lattnerfb2ceed2010-03-18 21:06:54 +00002432 let InOperandList = !con(iops, (ins pred:$p));
Chris Lattner04c342e2010-10-06 00:05:18 +00002433 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
Evan Cheng738a97a2009-11-23 21:57:23 +00002434 let Pattern = pattern;
Bob Wilson2e076c42009-06-22 23:27:02 +00002435 list<Predicate> Predicates = [HasNEON];
Jim Grosbach5876e412010-11-19 22:42:55 +00002436
Chris Lattner63274cb2010-11-15 05:19:05 +00002437 let PostEncoderMethod = "NEONThumb2DupPostEncoder";
Owen Andersonc86a5bd2011-08-10 19:01:10 +00002438 let DecoderNamespace = "NEONDup";
Jim Grosbach5876e412010-11-19 22:42:55 +00002439
Owen Andersoned9652f2010-10-27 21:28:09 +00002440 bits<5> V;
2441 bits<4> R;
Owen Anderson40d24a42010-10-27 19:25:54 +00002442 bits<4> p;
Owen Andersoned9652f2010-10-27 21:28:09 +00002443 bits<4> lane;
Jim Grosbach5876e412010-11-19 22:42:55 +00002444
Owen Anderson40d24a42010-10-27 19:25:54 +00002445 let Inst{31-28} = p{3-0};
Owen Andersoned9652f2010-10-27 21:28:09 +00002446 let Inst{7} = V{4};
2447 let Inst{19-16} = V{3-0};
2448 let Inst{15-12} = R{3-0};
Bob Wilson2e076c42009-06-22 23:27:02 +00002449}
2450class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
David Goodwinb062c232009-08-06 16:52:47 +00002451 dag oops, dag iops, InstrItinClass itin,
Evan Cheng738a97a2009-11-23 21:57:23 +00002452 string opc, string dt, string asm, list<dag> pattern>
Bob Wilsoncc386fb2010-06-25 23:56:05 +00002453 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
Evan Cheng738a97a2009-11-23 21:57:23 +00002454 opc, dt, asm, pattern>;
Bob Wilson2e076c42009-06-22 23:27:02 +00002455class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
David Goodwinb062c232009-08-06 16:52:47 +00002456 dag oops, dag iops, InstrItinClass itin,
Evan Cheng738a97a2009-11-23 21:57:23 +00002457 string opc, string dt, string asm, list<dag> pattern>
Bob Wilsoncc386fb2010-06-25 23:56:05 +00002458 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
Evan Cheng738a97a2009-11-23 21:57:23 +00002459 opc, dt, asm, pattern>;
Bob Wilson2e076c42009-06-22 23:27:02 +00002460class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
David Goodwinb062c232009-08-06 16:52:47 +00002461 dag oops, dag iops, InstrItinClass itin,
Evan Cheng738a97a2009-11-23 21:57:23 +00002462 string opc, string dt, string asm, list<dag> pattern>
Bob Wilsoncc386fb2010-06-25 23:56:05 +00002463 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
Evan Cheng738a97a2009-11-23 21:57:23 +00002464 opc, dt, asm, pattern>;
David Goodwin3b9c52c2009-08-04 17:53:06 +00002465
Johnny Chen45ab3f32010-03-25 17:01:27 +00002466// Vector Duplicate Lane (from scalar to all elements)
2467class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
2468 InstrItinClass itin, string opc, string dt, string asm,
2469 list<dag> pattern>
Johnny Chen91d27742010-03-25 21:49:12 +00002470 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
Johnny Chen45ab3f32010-03-25 17:01:27 +00002471 let Inst{24-23} = 0b11;
2472 let Inst{21-20} = 0b11;
2473 let Inst{19-16} = op19_16;
Bill Wendlingb70dc872010-08-31 07:50:46 +00002474 let Inst{11-7} = 0b11000;
2475 let Inst{6} = op6;
2476 let Inst{4} = 0;
Jim Grosbach5876e412010-11-19 22:42:55 +00002477
Owen Anderson40d24a42010-10-27 19:25:54 +00002478 bits<5> Vd;
2479 bits<5> Vm;
Jim Grosbach5876e412010-11-19 22:42:55 +00002480
Owen Anderson40d24a42010-10-27 19:25:54 +00002481 let Inst{22} = Vd{4};
2482 let Inst{15-12} = Vd{3-0};
2483 let Inst{5} = Vm{4};
2484 let Inst{3-0} = Vm{3-0};
Johnny Chen45ab3f32010-03-25 17:01:27 +00002485}
2486
David Goodwin3b9c52c2009-08-04 17:53:06 +00002487// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
2488// for single-precision FP.
2489class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
2490 list<Predicate> Predicates = [HasNEON,UseNEONForFP];
2491}
Jim Grosbach7996b152011-11-14 22:28:39 +00002492
2493// VFP/NEON Instruction aliases for type suffices.
Sjoerd Meijer9da258d2016-06-03 13:19:43 +00002494// Note: When EmitPriority == 1, the alias will be used for printing
2495class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result, bit EmitPriority = 0> :
2496 InstAlias<!strconcat(opc, dt, "\t", asm), Result, EmitPriority>, Requires<[HasVFP2]>;
Jim Grosbach2cf294a2011-12-07 01:50:36 +00002497
Sjoerd Meijer9da258d2016-06-03 13:19:43 +00002498// Note: When EmitPriority == 1, the alias will be used for printing
2499multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result, bit EmitPriority = 0> {
2500 def : VFPDataTypeInstAlias<opc, ".8", asm, Result, EmitPriority>;
2501 def : VFPDataTypeInstAlias<opc, ".16", asm, Result, EmitPriority>;
2502 def : VFPDataTypeInstAlias<opc, ".32", asm, Result, EmitPriority>;
2503 def : VFPDataTypeInstAlias<opc, ".64", asm, Result, EmitPriority>;
Jim Grosbache7dcbc82011-12-02 18:52:30 +00002504}
2505
Sjoerd Meijer9da258d2016-06-03 13:19:43 +00002506// Note: When EmitPriority == 1, the alias will be used for printing
2507multiclass NEONDTAnyInstAlias<string opc, string asm, dag Result, bit EmitPriority = 0> {
Jim Grosbach681db342012-01-24 17:23:29 +00002508 let Predicates = [HasNEON] in {
Sjoerd Meijer9da258d2016-06-03 13:19:43 +00002509 def : VFPDataTypeInstAlias<opc, ".8", asm, Result, EmitPriority>;
2510 def : VFPDataTypeInstAlias<opc, ".16", asm, Result, EmitPriority>;
2511 def : VFPDataTypeInstAlias<opc, ".32", asm, Result, EmitPriority>;
2512 def : VFPDataTypeInstAlias<opc, ".64", asm, Result, EmitPriority>;
Jim Grosbach681db342012-01-24 17:23:29 +00002513}
2514}
2515
Jim Grosbache7dcbc82011-12-02 18:52:30 +00002516// The same alias classes using AsmPseudo instead, for the more complex
2517// stuff in NEON that InstAlias can't quite handle.
2518// Note that we can't use anonymous defm references here like we can
2519// above, as we care about the ultimate instruction enum names generated, unlike
2520// for instalias defs.
2521class NEONDataTypeAsmPseudoInst<string opc, string dt, string asm, dag iops> :
Jim Grosbachdda976b2011-12-02 22:01:52 +00002522 AsmPseudoInst<!strconcat(opc, dt, "\t", asm), iops>, Requires<[HasNEON]>;
Jim Grosbach585ce302011-12-07 01:17:58 +00002523
Sam Parker963da5b2017-09-29 13:11:33 +00002524// Extension of NEON 3-vector data processing instructions in coprocessor 8
2525// encoding space, introduced in ARMv8.3-A.
2526class N3VCP8<bits<2> op24_23, bits<2> op21_20, bit op6, bit op4,
2527 dag oops, dag iops, InstrItinClass itin,
2528 string opc, string dt, string asm, string cstr, list<dag> pattern>
2529 : NeonInp<oops, iops, AddrModeNone, IndexModeNone, N3RegCplxFrm, itin, opc,
2530 dt, asm, cstr, pattern> {
2531 bits<5> Vd;
2532 bits<5> Vn;
2533 bits<5> Vm;
2534
2535 let DecoderNamespace = "VFPV8";
2536 // These have the same encodings in ARM and Thumb2
2537 let PostEncoderMethod = "";
2538
2539 let Inst{31-25} = 0b1111110;
2540 let Inst{24-23} = op24_23;
2541 let Inst{22} = Vd{4};
2542 let Inst{21-20} = op21_20;
2543 let Inst{19-16} = Vn{3-0};
2544 let Inst{15-12} = Vd{3-0};
2545 let Inst{11-8} = 0b1000;
2546 let Inst{7} = Vn{4};
2547 let Inst{6} = op6;
2548 let Inst{5} = Vm{4};
2549 let Inst{4} = op4;
2550 let Inst{3-0} = Vm{3-0};
2551}
2552
2553// Extension of NEON 2-vector-and-scalar data processing instructions in
2554// coprocessor 8 encoding space, introduced in ARMv8.3-A.
2555class N3VLaneCP8<bit op23, bits<2> op21_20, bit op6, bit op4,
2556 dag oops, dag iops, InstrItinClass itin,
2557 string opc, string dt, string asm, string cstr, list<dag> pattern>
2558 : NeonInp<oops, iops, AddrModeNone, IndexModeNone, N3RegCplxFrm, itin, opc,
2559 dt, asm, cstr, pattern> {
2560 bits<5> Vd;
2561 bits<5> Vn;
2562 bits<5> Vm;
2563
2564 let DecoderNamespace = "VFPV8";
2565 // These have the same encodings in ARM and Thumb2
2566 let PostEncoderMethod = "";
2567
2568 let Inst{31-24} = 0b11111110;
2569 let Inst{23} = op23;
2570 let Inst{22} = Vd{4};
2571 let Inst{21-20} = op21_20;
2572 let Inst{19-16} = Vn{3-0};
2573 let Inst{15-12} = Vd{3-0};
2574 let Inst{11-8} = 0b1000;
2575 let Inst{7} = Vn{4};
2576 let Inst{6} = op6;
2577 // Bit 5 set by sub-classes
2578 let Inst{4} = op4;
2579 let Inst{3-0} = Vm{3-0};
2580}
2581
2582// Operand types for complex instructions
Oliver Stannard0d5c7922017-10-03 14:38:52 +00002583class ComplexRotationOperand<int Angle, int Remainder, string Type, string Diag>
Sam Parker963da5b2017-09-29 13:11:33 +00002584 : AsmOperandClass {
2585 let PredicateMethod = "isComplexRotation<" # Angle # ", " # Remainder # ">";
Oliver Stannard0d5c7922017-10-03 14:38:52 +00002586 let DiagnosticString = "complex rotation must be " # Diag;
Sam Parker963da5b2017-09-29 13:11:33 +00002587 let Name = "ComplexRotation" # Type;
2588}
2589def complexrotateop : Operand<i32> {
Oliver Stannard0d5c7922017-10-03 14:38:52 +00002590 let ParserMatchClass = ComplexRotationOperand<90, 0, "Even", "0, 90, 180 or 270">;
Sam Parker963da5b2017-09-29 13:11:33 +00002591 let PrintMethod = "printComplexRotationOp<90, 0>";
2592}
2593def complexrotateopodd : Operand<i32> {
Oliver Stannard0d5c7922017-10-03 14:38:52 +00002594 let ParserMatchClass = ComplexRotationOperand<180, 90, "Odd", "90 or 270">;
Sam Parker963da5b2017-09-29 13:11:33 +00002595 let PrintMethod = "printComplexRotationOp<180, 90>";
2596}
2597
Jim Grosbach585ce302011-12-07 01:17:58 +00002598// Data type suffix token aliases. Implements Table A7-3 in the ARM ARM.
2599def : TokenAlias<".s8", ".i8">;
2600def : TokenAlias<".u8", ".i8">;
2601def : TokenAlias<".s16", ".i16">;
2602def : TokenAlias<".u16", ".i16">;
2603def : TokenAlias<".s32", ".i32">;
2604def : TokenAlias<".u32", ".i32">;
Jim Grosbach2cf294a2011-12-07 01:50:36 +00002605def : TokenAlias<".s64", ".i64">;
2606def : TokenAlias<".u64", ".i64">;
Jim Grosbach585ce302011-12-07 01:17:58 +00002607
2608def : TokenAlias<".i8", ".8">;
2609def : TokenAlias<".i16", ".16">;
2610def : TokenAlias<".i32", ".32">;
Jim Grosbach2cf294a2011-12-07 01:50:36 +00002611def : TokenAlias<".i64", ".64">;
Jim Grosbach585ce302011-12-07 01:17:58 +00002612
2613def : TokenAlias<".p8", ".8">;
2614def : TokenAlias<".p16", ".16">;
2615
2616def : TokenAlias<".f32", ".32">;
2617def : TokenAlias<".f64", ".64">;
2618def : TokenAlias<".f", ".f32">;
2619def : TokenAlias<".d", ".f64">;