blob: a2cc721a2bf5bcaaf7d9aa2b47f2bfb5bc585b28 [file] [log] [blame]
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
Stephen Hemminger798b6b12006-10-22 20:16:57 -070013 * the Free Software Foundation; either version 2 of the License.
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070014 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Stephen Hemminger793b8832005-09-14 16:06:14 -070017 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070018 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
Stephen Hemminger793b8832005-09-14 16:06:14 -070025#include <linux/crc32.h>
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070026#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
Andrew Mortond0bbccf2005-11-10 15:29:27 -080030#include <linux/dma-mapping.h>
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070031#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
Stephen Hemminger91c86df2005-12-09 11:34:57 -080038#include <linux/workqueue.h>
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -070039#include <linux/if_vlan.h>
Stephen Hemmingerd70cd512005-12-09 11:35:09 -080040#include <linux/prefetch.h>
shemminger@osdl.orgef743d32005-11-30 11:45:12 -080041#include <linux/mii.h>
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070042
43#include <asm/irq.h>
44
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -070045#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
46#define SKY2_VLAN_TAG_USED 1
47#endif
48
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070049#include "sky2.h"
50
51#define DRV_NAME "sky2"
Stephen Hemminger62ba7e62007-02-15 16:40:35 -080052#define DRV_VERSION "1.13"
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070053#define PFX DRV_NAME " "
54
55/*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
Stephen Hemminger14d02632006-09-26 11:57:43 -070058 * similar to Tigon3.
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070059 */
60
Stephen Hemminger14d02632006-09-26 11:57:43 -070061#define RX_LE_SIZE 1024
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070062#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
Stephen Hemminger14d02632006-09-26 11:57:43 -070063#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
shemminger@osdl.org13210ce2005-11-30 11:45:14 -080064#define RX_DEF_PENDING RX_MAX_PENDING
Stephen Hemminger82788c72006-01-17 13:43:10 -080065#define RX_SKB_ALIGN 8
Stephen Hemminger22e11702006-07-12 15:23:48 -070066#define RX_BUF_WRITE 16
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070067
Stephen Hemminger793b8832005-09-14 16:06:14 -070068#define TX_RING_SIZE 512
69#define TX_DEF_PENDING (TX_RING_SIZE - 1)
70#define TX_MIN_PENDING 64
Stephen Hemmingerb19666d2006-03-07 11:06:36 -080071#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
Stephen Hemminger793b8832005-09-14 16:06:14 -070072
73#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070074#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070075#define TX_WATCHDOG (5 * HZ)
76#define NAPI_WEIGHT 64
77#define PHY_RETRIES 1000
78
Stephen Hemmingercb5d9542006-05-08 15:11:29 -070079#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
80
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070081static const u32 default_msg =
Stephen Hemminger793b8832005-09-14 16:06:14 -070082 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
Stephen Hemminger3be92a72006-01-17 13:43:17 -080084 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070085
Stephen Hemminger793b8832005-09-14 16:06:14 -070086static int debug = -1; /* defaults above */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070087module_param(debug, int, 0);
88MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
Stephen Hemminger14d02632006-09-26 11:57:43 -070090static int copybreak __read_mostly = 128;
Stephen Hemmingerbdb5c582005-12-09 11:34:55 -080091module_param(copybreak, int, 0);
92MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -080094static int disable_msi = 0;
95module_param(disable_msi, int, 0);
96MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
Stephen Hemmingere561a832006-10-17 10:20:51 -070098static int idle_timeout = 0;
Stephen Hemminger01bd7562006-05-08 15:11:30 -070099module_param(idle_timeout, int, 0);
Stephen Hemmingere561a832006-10-17 10:20:51 -0700100MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
Stephen Hemminger01bd7562006-05-08 15:11:30 -0700101
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700102static const struct pci_device_id sky2_id_table[] = {
Stephen Hemmingere5b74c72006-12-04 15:53:36 -0800103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
Stephen Hemminger2d2a3872006-05-17 14:37:04 -0700105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
Stephen Hemminger2f4a66a2006-09-01 14:52:04 -0700106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
Stephen Hemminger508f89e2006-12-01 14:29:34 -0800107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
Stephen Hemmingerf1a0b6f2007-02-06 10:45:44 -0800108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
Stephen Hemmingere5b74c72006-12-04 15:53:36 -0800109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
Stephen Hemminger0a17e4c2007-04-11 14:47:58 -0700126#ifdef broken
127 /* This device causes data corruption problems that are not resolved */
Stephen Hemmingere5b74c72006-12-04 15:53:36 -0800128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
Stephen Hemminger0a17e4c2007-04-11 14:47:58 -0700129#endif
Stephen Hemmingere5b74c72006-12-04 15:53:36 -0800130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
Stephen Hemmingerf1a0b6f2007-02-06 10:45:44 -0800133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700136 { 0 }
137};
Stephen Hemminger793b8832005-09-14 16:06:14 -0700138
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700139MODULE_DEVICE_TABLE(pci, sky2_id_table);
140
141/* Avoid conditionals by using array */
142static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
143static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
Stephen Hemmingerf4ea4312006-05-09 14:46:54 -0700144static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700145
Stephen Hemminger92f965e2005-12-09 11:34:53 -0800146/* This driver supports yukon2 chipset only */
147static const char *yukon2_name[] = {
148 "XL", /* 0xb3 */
149 "EC Ultra", /* 0xb4 */
Stephen Hemminger93745492007-02-06 10:45:43 -0800150 "Extreme", /* 0xb5 */
Stephen Hemminger92f965e2005-12-09 11:34:53 -0800151 "EC", /* 0xb6 */
152 "FE", /* 0xb7 */
Stephen Hemminger793b8832005-09-14 16:06:14 -0700153};
154
Stephen Hemminger793b8832005-09-14 16:06:14 -0700155/* Access to external PHY */
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800156static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700157{
158 int i;
159
160 gma_write16(hw, port, GM_SMI_DATA, val);
161 gma_write16(hw, port, GM_SMI_CTRL,
162 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
163
164 for (i = 0; i < PHY_RETRIES; i++) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700165 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800166 return 0;
Stephen Hemminger793b8832005-09-14 16:06:14 -0700167 udelay(1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700168 }
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800169
Stephen Hemminger793b8832005-09-14 16:06:14 -0700170 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800171 return -ETIMEDOUT;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700172}
173
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800174static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700175{
176 int i;
177
Stephen Hemminger793b8832005-09-14 16:06:14 -0700178 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700179 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
180
181 for (i = 0; i < PHY_RETRIES; i++) {
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800182 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
183 *val = gma_read16(hw, port, GM_SMI_DATA);
184 return 0;
185 }
186
Stephen Hemminger793b8832005-09-14 16:06:14 -0700187 udelay(1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700188 }
189
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800190 return -ETIMEDOUT;
191}
192
193static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
194{
195 u16 v;
196
197 if (__gm_phy_read(hw, port, reg, &v) != 0)
198 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
199 return v;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700200}
201
Stephen Hemmingerae306cc2006-12-20 13:06:36 -0800202
203static void sky2_power_on(struct sky2_hw *hw)
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700204{
Stephen Hemmingerae306cc2006-12-20 13:06:36 -0800205 /* switch power to VCC (WA for VAUX problem) */
206 sky2_write8(hw, B0_POWER_CTRL,
207 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700208
Stephen Hemmingerae306cc2006-12-20 13:06:36 -0800209 /* disable Core Clock Division, */
210 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700211
Stephen Hemmingerae306cc2006-12-20 13:06:36 -0800212 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
213 /* enable bits are inverted */
214 sky2_write8(hw, B2_Y2_CLK_GATE,
215 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
216 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
217 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
218 else
219 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700220
Stephen Hemminger93745492007-02-06 10:45:43 -0800221 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
Stephen Hemmingerae306cc2006-12-20 13:06:36 -0800222 u32 reg1;
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700223
Stephen Hemmingerae306cc2006-12-20 13:06:36 -0800224 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
225 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
226 reg1 &= P_ASPM_CONTROL_MSK;
227 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
228 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700229 }
Stephen Hemmingerae306cc2006-12-20 13:06:36 -0800230}
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700231
Stephen Hemmingerae306cc2006-12-20 13:06:36 -0800232static void sky2_power_aux(struct sky2_hw *hw)
233{
234 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
235 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
236 else
237 /* enable bits are inverted */
238 sky2_write8(hw, B2_Y2_CLK_GATE,
239 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
240 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
241 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
242
243 /* switch power to VAUX */
244 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
245 sky2_write8(hw, B0_POWER_CTRL,
246 (PC_VAUX_ENA | PC_VCC_ENA |
247 PC_VAUX_ON | PC_VCC_OFF));
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700248}
249
shemminger@osdl.orgd3bcfbe2006-08-28 10:00:51 -0700250static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700251{
252 u16 reg;
253
254 /* disable all GMAC IRQ's */
255 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
256 /* disable PHY IRQs */
257 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700258
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700259 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
260 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
261 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
262 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
263
264 reg = gma_read16(hw, port, GM_RX_CTRL);
265 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
266 gma_write16(hw, port, GM_RX_CTRL, reg);
267}
268
Stephen Hemminger16ad91e2006-10-17 10:24:13 -0700269/* flow control to advertise bits */
270static const u16 copper_fc_adv[] = {
271 [FC_NONE] = 0,
272 [FC_TX] = PHY_M_AN_ASP,
273 [FC_RX] = PHY_M_AN_PC,
274 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
275};
276
277/* flow control to advertise bits when using 1000BaseX */
278static const u16 fiber_fc_adv[] = {
279 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
280 [FC_TX] = PHY_M_P_ASYM_MD_X,
281 [FC_RX] = PHY_M_P_SYM_MD_X,
282 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
283};
284
285/* flow control to GMA disable bits */
286static const u16 gm_fc_disable[] = {
287 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
288 [FC_TX] = GM_GPCR_FC_RX_DIS,
289 [FC_RX] = GM_GPCR_FC_TX_DIS,
290 [FC_BOTH] = 0,
291};
292
293
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700294static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
295{
296 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700297 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700298
Stephen Hemminger93745492007-02-06 10:45:43 -0800299 if (sky2->autoneg == AUTONEG_ENABLE
300 && !(hw->chip_id == CHIP_ID_YUKON_XL
301 || hw->chip_id == CHIP_ID_YUKON_EC_U
302 || hw->chip_id == CHIP_ID_YUKON_EX)) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700303 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
304
305 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
Stephen Hemminger793b8832005-09-14 16:06:14 -0700306 PHY_M_EC_MAC_S_MSK);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700307 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
308
309 if (hw->chip_id == CHIP_ID_YUKON_EC)
310 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
311 else
312 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
313
314 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
315 }
316
317 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
Stephen Hemmingerb89165f2006-09-06 12:44:53 -0700318 if (sky2_is_copper(hw)) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700319 if (hw->chip_id == CHIP_ID_YUKON_FE) {
320 /* enable automatic crossover */
321 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
322 } else {
323 /* disable energy detect */
324 ctrl &= ~PHY_M_PC_EN_DET_MSK;
325
326 /* enable automatic crossover */
327 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
328
Stephen Hemminger93745492007-02-06 10:45:43 -0800329 if (sky2->autoneg == AUTONEG_ENABLE
330 && (hw->chip_id == CHIP_ID_YUKON_XL
331 || hw->chip_id == CHIP_ID_YUKON_EC_U
332 || hw->chip_id == CHIP_ID_YUKON_EX)) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700333 ctrl &= ~PHY_M_PC_DSC_MSK;
334 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
335 }
336 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700337 } else {
338 /* workaround for deviation #4.88 (CRC errors) */
339 /* disable Automatic Crossover */
340
341 ctrl &= ~PHY_M_PC_MDIX_MSK;
Stephen Hemmingerb89165f2006-09-06 12:44:53 -0700342 }
343
344 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
345
346 /* special setup for PHY 88E1112 Fiber */
347 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
348 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
349
350 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
351 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
352 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
353 ctrl &= ~PHY_M_MAC_MD_MSK;
354 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700355 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
356
Stephen Hemmingerb89165f2006-09-06 12:44:53 -0700357 if (hw->pmd_type == 'P') {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700358 /* select page 1 to access Fiber registers */
359 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
Stephen Hemmingerb89165f2006-09-06 12:44:53 -0700360
361 /* for SFP-module set SIGDET polarity to low */
362 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
363 ctrl |= PHY_M_FIB_SIGD_POL;
364 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700365 }
Stephen Hemmingerb89165f2006-09-06 12:44:53 -0700366
367 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700368 }
369
Stephen Hemminger7800fdd2006-10-17 10:24:10 -0700370 ctrl = PHY_CT_RESET;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700371 ct1000 = 0;
372 adv = PHY_AN_CSMA;
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700373 reg = 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700374
375 if (sky2->autoneg == AUTONEG_ENABLE) {
Stephen Hemmingerb89165f2006-09-06 12:44:53 -0700376 if (sky2_is_copper(hw)) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700377 if (sky2->advertising & ADVERTISED_1000baseT_Full)
378 ct1000 |= PHY_M_1000C_AFD;
379 if (sky2->advertising & ADVERTISED_1000baseT_Half)
380 ct1000 |= PHY_M_1000C_AHD;
381 if (sky2->advertising & ADVERTISED_100baseT_Full)
382 adv |= PHY_M_AN_100_FD;
383 if (sky2->advertising & ADVERTISED_100baseT_Half)
384 adv |= PHY_M_AN_100_HD;
385 if (sky2->advertising & ADVERTISED_10baseT_Full)
386 adv |= PHY_M_AN_10_FD;
387 if (sky2->advertising & ADVERTISED_10baseT_Half)
388 adv |= PHY_M_AN_10_HD;
Stephen Hemminger709c6e72006-10-17 10:24:04 -0700389
Stephen Hemminger16ad91e2006-10-17 10:24:13 -0700390 adv |= copper_fc_adv[sky2->flow_mode];
Stephen Hemmingerb89165f2006-09-06 12:44:53 -0700391 } else { /* special defines for FIBER (88E1040S only) */
392 if (sky2->advertising & ADVERTISED_1000baseT_Full)
393 adv |= PHY_M_AN_1000X_AFD;
394 if (sky2->advertising & ADVERTISED_1000baseT_Half)
395 adv |= PHY_M_AN_1000X_AHD;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700396
Stephen Hemminger16ad91e2006-10-17 10:24:13 -0700397 adv |= fiber_fc_adv[sky2->flow_mode];
Stephen Hemminger709c6e72006-10-17 10:24:04 -0700398 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700399
400 /* Restart Auto-negotiation */
401 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
402 } else {
403 /* forced speed/duplex settings */
404 ct1000 = PHY_M_1000C_MSE;
405
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700406 /* Disable auto update for duplex flow control and speed */
407 reg |= GM_GPCR_AU_ALL_DIS;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700408
409 switch (sky2->speed) {
410 case SPEED_1000:
411 ctrl |= PHY_CT_SP1000;
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700412 reg |= GM_GPCR_SPEED_1000;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700413 break;
414 case SPEED_100:
415 ctrl |= PHY_CT_SP100;
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700416 reg |= GM_GPCR_SPEED_100;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700417 break;
418 }
419
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700420 if (sky2->duplex == DUPLEX_FULL) {
421 reg |= GM_GPCR_DUP_FULL;
422 ctrl |= PHY_CT_DUP_MD;
Stephen Hemminger16ad91e2006-10-17 10:24:13 -0700423 } else if (sky2->speed < SPEED_1000)
424 sky2->flow_mode = FC_NONE;
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700425
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700426
Stephen Hemminger16ad91e2006-10-17 10:24:13 -0700427 reg |= gm_fc_disable[sky2->flow_mode];
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700428
429 /* Forward pause packets to GMAC? */
Stephen Hemminger16ad91e2006-10-17 10:24:13 -0700430 if (sky2->flow_mode & FC_RX)
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700431 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
432 else
433 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700434 }
435
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700436 gma_write16(hw, port, GM_GP_CTRL, reg);
437
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700438 if (hw->chip_id != CHIP_ID_YUKON_FE)
439 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
440
441 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
442 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
443
444 /* Setup Phy LED's */
445 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
446 ledover = 0;
447
448 switch (hw->chip_id) {
449 case CHIP_ID_YUKON_FE:
450 /* on 88E3082 these bits are at 11..9 (shifted left) */
451 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
452
453 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
454
455 /* delete ACT LED control bits */
456 ctrl &= ~PHY_M_FELP_LED1_MSK;
457 /* change ACT LED control to blink mode */
458 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
459 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
460 break;
461
462 case CHIP_ID_YUKON_XL:
Stephen Hemminger793b8832005-09-14 16:06:14 -0700463 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700464
465 /* select page 3 to access LED control register */
466 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
467
468 /* set LED Function Control register */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700469 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
470 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
471 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
472 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
473 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700474
475 /* set Polarity Control register */
476 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
Stephen Hemminger793b8832005-09-14 16:06:14 -0700477 (PHY_M_POLC_LS1_P_MIX(4) |
478 PHY_M_POLC_IS0_P_MIX(4) |
479 PHY_M_POLC_LOS_CTRL(2) |
480 PHY_M_POLC_INIT_CTRL(2) |
481 PHY_M_POLC_STA1_CTRL(2) |
482 PHY_M_POLC_STA0_CTRL(2)));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700483
484 /* restore page register */
Stephen Hemminger793b8832005-09-14 16:06:14 -0700485 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700486 break;
Stephen Hemminger93745492007-02-06 10:45:43 -0800487
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700488 case CHIP_ID_YUKON_EC_U:
Stephen Hemminger93745492007-02-06 10:45:43 -0800489 case CHIP_ID_YUKON_EX:
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700490 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
491
492 /* select page 3 to access LED control register */
493 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
494
495 /* set LED Function Control register */
496 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
497 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
498 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
499 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
500 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
501
502 /* set Blink Rate in LED Timer Control Register */
503 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
504 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
505 /* restore page register */
506 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
507 break;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700508
509 default:
510 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
511 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
512 /* turn off the Rx LED (LED_RX) */
Stephen Hemminger0efdf262006-12-05 12:03:41 -0800513 ledover &= ~PHY_M_LED_MO_RX;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700514 }
515
Stephen Hemminger9467a8f2007-04-07 16:02:28 -0700516 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
517 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800518 /* apply fixes in PHY AFE */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
520
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800521 /* increase differential signal amplitude in 10BASE-T */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700522 gm_phy_write(hw, port, 0x18, 0xaa99);
523 gm_phy_write(hw, port, 0x17, 0x2011);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700524
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800525 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700526 gm_phy_write(hw, port, 0x18, 0xa204);
527 gm_phy_write(hw, port, 0x17, 0x2002);
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800528
529 /* set page register to 0 */
Stephen Hemminger9467a8f2007-04-07 16:02:28 -0700530 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
Stephen Hemminger93745492007-02-06 10:45:43 -0800531 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800532 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
533
534 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
535 /* turn on 100 Mbps LED (LED_LINK100) */
Stephen Hemminger0efdf262006-12-05 12:03:41 -0800536 ledover |= PHY_M_LED_MO_100;
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800537 }
538
539 if (ledover)
540 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
541
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700542 }
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700543
shemminger@osdl.orgd571b692005-10-26 12:16:09 -0700544 /* Enable phy interrupt on auto-negotiation complete (or link up) */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700545 if (sky2->autoneg == AUTONEG_ENABLE)
546 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
547 else
548 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
549}
550
shemminger@osdl.orgd3bcfbe2006-08-28 10:00:51 -0700551static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
552{
553 u32 reg1;
554 static const u32 phy_power[]
555 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
556
557 /* looks like this XL is back asswards .. */
558 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
559 onoff = !onoff;
560
Stephen Hemmingeraed2cec2006-12-20 13:06:35 -0800561 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
shemminger@osdl.orgd3bcfbe2006-08-28 10:00:51 -0700562 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
shemminger@osdl.orgd3bcfbe2006-08-28 10:00:51 -0700563 if (onoff)
564 /* Turn off phy power saving */
565 reg1 &= ~phy_power[port];
566 else
567 reg1 |= phy_power[port];
568
569 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
shemminger@osdl.org98232f82006-08-28 10:00:52 -0700570 sky2_pci_read32(hw, PCI_DEV_REG1);
Stephen Hemmingeraed2cec2006-12-20 13:06:35 -0800571 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
shemminger@osdl.orgd3bcfbe2006-08-28 10:00:51 -0700572 udelay(100);
573}
574
Stephen Hemminger1b537562005-12-20 15:08:07 -0800575/* Force a renegotiation */
576static void sky2_phy_reinit(struct sky2_port *sky2)
577{
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800578 spin_lock_bh(&sky2->phy_lock);
Stephen Hemminger1b537562005-12-20 15:08:07 -0800579 sky2_phy_init(sky2->hw, sky2->port);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800580 spin_unlock_bh(&sky2->phy_lock);
Stephen Hemminger1b537562005-12-20 15:08:07 -0800581}
582
Stephen Hemmingere3173832007-02-06 10:45:39 -0800583/* Put device in state to listen for Wake On Lan */
584static void sky2_wol_init(struct sky2_port *sky2)
585{
586 struct sky2_hw *hw = sky2->hw;
587 unsigned port = sky2->port;
588 enum flow_control save_mode;
589 u16 ctrl;
590 u32 reg1;
591
592 /* Bring hardware out of reset */
593 sky2_write16(hw, B0_CTST, CS_RST_CLR);
594 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
595
596 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
597 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
598
599 /* Force to 10/100
600 * sky2_reset will re-enable on resume
601 */
602 save_mode = sky2->flow_mode;
603 ctrl = sky2->advertising;
604
605 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
606 sky2->flow_mode = FC_NONE;
607 sky2_phy_power(hw, port, 1);
608 sky2_phy_reinit(sky2);
609
610 sky2->flow_mode = save_mode;
611 sky2->advertising = ctrl;
612
613 /* Set GMAC to no flow control and auto update for speed/duplex */
614 gma_write16(hw, port, GM_GP_CTRL,
615 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
616 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
617
618 /* Set WOL address */
619 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
620 sky2->netdev->dev_addr, ETH_ALEN);
621
622 /* Turn on appropriate WOL control bits */
623 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
624 ctrl = 0;
625 if (sky2->wol & WAKE_PHY)
626 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
627 else
628 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
629
630 if (sky2->wol & WAKE_MAGIC)
631 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
632 else
633 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
634
635 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
636 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
637
638 /* Turn on legacy PCI-Express PME mode */
639 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
640 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
641 reg1 |= PCI_Y2_PME_LEGACY;
642 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
643 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
644
645 /* block receiver */
646 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
647
648}
649
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700650static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
651{
652 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
653 u16 reg;
654 int i;
655 const u8 *addr = hw->dev[port]->dev_addr;
656
shemminger@osdl.org42eeea02005-11-30 11:45:13 -0800657 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
658 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700659
660 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
661
Stephen Hemminger793b8832005-09-14 16:06:14 -0700662 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700663 /* WA DEV_472 -- looks like crossed wires on port 2 */
664 /* clear GMAC 1 Control reset */
665 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
666 do {
667 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
668 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
669 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
670 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
671 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
672 }
673
Stephen Hemminger793b8832005-09-14 16:06:14 -0700674 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700675
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -0700676 /* Enable Transmit FIFO Underrun */
677 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
678
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800679 spin_lock_bh(&sky2->phy_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700680 sky2_phy_init(hw, port);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800681 spin_unlock_bh(&sky2->phy_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700682
683 /* MIB clear */
684 reg = gma_read16(hw, port, GM_PHY_ADDR);
685 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
686
Stephen Hemminger43f2f102006-04-05 17:47:15 -0700687 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
688 gma_read16(hw, port, i);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700689 gma_write16(hw, port, GM_PHY_ADDR, reg);
690
691 /* transmit control */
692 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
693
694 /* receive control reg: unicast + multicast + no FCS */
695 gma_write16(hw, port, GM_RX_CTRL,
Stephen Hemminger793b8832005-09-14 16:06:14 -0700696 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700697
698 /* transmit flow control */
699 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
700
701 /* transmit parameter */
702 gma_write16(hw, port, GM_TX_PARAM,
703 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
704 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
705 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
706 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
707
708 /* serial mode register */
709 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700710 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700711
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700712 if (hw->dev[port]->mtu > ETH_DATA_LEN)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700713 reg |= GM_SMOD_JUMBO_ENA;
714
715 gma_write16(hw, port, GM_SERIAL_MODE, reg);
716
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700717 /* virtual address for data */
718 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
719
Stephen Hemminger793b8832005-09-14 16:06:14 -0700720 /* physical address: used for pause frames */
721 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
722
723 /* ignore counter overflows */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700724 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
725 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
726 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
727
728 /* Configure Rx MAC FIFO */
729 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
Stephen Hemminger70f1be42006-03-07 11:06:37 -0800730 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
731 GMF_OPER_ON | GMF_RX_F_FL_ON);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700732
shemminger@osdl.orgd571b692005-10-26 12:16:09 -0700733 /* Flush Rx MAC FIFO on any flow control or error */
shemminger@osdl.org42eeea02005-11-30 11:45:13 -0800734 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700735
Stephen Hemminger8df9a872006-12-01 14:29:35 -0800736 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
737 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700738
739 /* Configure Tx MAC FIFO */
740 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
741 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -0800742
Stephen Hemminger93745492007-02-06 10:45:43 -0800743 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
Stephen Hemminger8df9a872006-12-01 14:29:35 -0800744 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -0800745 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
746 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
747 /* set Tx GMAC FIFO Almost Empty Threshold */
748 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
749 /* Disable Store & Forward mode for TX */
750 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
751 }
752 }
753
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700754}
755
Stephen Hemminger67712902006-12-04 15:53:45 -0800756/* Assign Ram Buffer allocation to queue */
757static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700758{
Stephen Hemminger67712902006-12-04 15:53:45 -0800759 u32 end;
760
761 /* convert from K bytes to qwords used for hw register */
762 start *= 1024/8;
763 space *= 1024/8;
764 end = start + space - 1;
Stephen Hemminger793b8832005-09-14 16:06:14 -0700765
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700766 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
767 sky2_write32(hw, RB_ADDR(q, RB_START), start);
768 sky2_write32(hw, RB_ADDR(q, RB_END), end);
769 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
770 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
771
772 if (q == Q_R1 || q == Q_R2) {
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -0800773 u32 tp = space - space/4;
Stephen Hemminger793b8832005-09-14 16:06:14 -0700774
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -0800775 /* On receive queue's set the thresholds
776 * give receiver priority when > 3/4 full
777 * send pause when down to 2K
778 */
779 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
780 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700781
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -0800782 tp = space - 2048/8;
783 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
784 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700785 } else {
786 /* Enable store & forward on Tx queue's because
787 * Tx FIFO is only 1K on Yukon
788 */
789 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
790 }
791
792 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700793 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700794}
795
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700796/* Setup Bus Memory Interface */
shemminger@osdl.orgaf4ed7e2005-11-30 11:45:21 -0800797static void sky2_qset(struct sky2_hw *hw, u16 q)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700798{
799 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
800 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
801 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
shemminger@osdl.orgaf4ed7e2005-11-30 11:45:21 -0800802 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700803}
804
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700805/* Setup prefetch unit registers. This is the interface between
806 * hardware and driver list elements
807 */
Stephen Hemminger8cc048e2005-12-09 11:35:07 -0800808static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700809 u64 addr, u32 last)
810{
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700811 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
812 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
813 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
814 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
815 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
816 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700817
818 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700819}
820
Stephen Hemminger793b8832005-09-14 16:06:14 -0700821static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
822{
823 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
824
Stephen Hemmingercb5d9542006-05-08 15:11:29 -0700825 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
Stephen Hemminger291ea612006-09-26 11:57:41 -0700826 le->ctrl = 0;
Stephen Hemminger793b8832005-09-14 16:06:14 -0700827 return le;
828}
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700829
Stephen Hemminger291ea612006-09-26 11:57:41 -0700830static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
831 struct sky2_tx_le *le)
832{
833 return sky2->tx_ring + (le - sky2->tx_le);
834}
835
Stephen Hemminger290d4de2006-03-20 15:48:15 -0800836/* Update chip's next pointer */
837static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700838{
shemminger@osdl.org98232f82006-08-28 10:00:52 -0700839 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
Stephen Hemminger762c2de2006-01-17 13:43:14 -0800840 wmb();
shemminger@osdl.org98232f82006-08-28 10:00:52 -0700841 sky2_write16(hw, q, idx);
842 sky2_read16(hw, q);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700843}
844
Stephen Hemminger793b8832005-09-14 16:06:14 -0700845
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700846static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
847{
848 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
Stephen Hemmingercb5d9542006-05-08 15:11:29 -0700849 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
Stephen Hemminger291ea612006-09-26 11:57:41 -0700850 le->ctrl = 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700851 return le;
852}
853
shemminger@osdl.orga018e332005-11-30 11:45:16 -0800854/* Return high part of DMA address (could be 32 or 64 bit) */
855static inline u32 high32(dma_addr_t a)
856{
Stephen Hemmingera0361192006-01-17 13:43:16 -0800857 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
shemminger@osdl.orga018e332005-11-30 11:45:16 -0800858}
859
Stephen Hemminger14d02632006-09-26 11:57:43 -0700860/* Build description to hardware for one receive segment */
861static void sky2_rx_add(struct sky2_port *sky2, u8 op,
862 dma_addr_t map, unsigned len)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700863{
864 struct sky2_rx_le *le;
Stephen Hemminger734d1862005-12-09 11:35:00 -0800865 u32 hi = high32(map);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700866
Stephen Hemminger793b8832005-09-14 16:06:14 -0700867 if (sky2->rx_addr64 != hi) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700868 le = sky2_next_rx(sky2);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700869 le->addr = cpu_to_le32(hi);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700870 le->opcode = OP_ADDR64 | HW_OWNER;
Stephen Hemminger734d1862005-12-09 11:35:00 -0800871 sky2->rx_addr64 = high32(map + len);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700872 }
Stephen Hemminger793b8832005-09-14 16:06:14 -0700873
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700874 le = sky2_next_rx(sky2);
Stephen Hemminger734d1862005-12-09 11:35:00 -0800875 le->addr = cpu_to_le32((u32) map);
876 le->length = cpu_to_le16(len);
Stephen Hemminger14d02632006-09-26 11:57:43 -0700877 le->opcode = op | HW_OWNER;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700878}
879
Stephen Hemminger14d02632006-09-26 11:57:43 -0700880/* Build description to hardware for one possibly fragmented skb */
881static void sky2_rx_submit(struct sky2_port *sky2,
882 const struct rx_ring_info *re)
883{
884 int i;
885
886 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
887
888 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
889 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
890}
891
892
893static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
894 unsigned size)
895{
896 struct sk_buff *skb = re->skb;
897 int i;
898
899 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
900 pci_unmap_len_set(re, data_size, size);
901
902 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
903 re->frag_addr[i] = pci_map_page(pdev,
904 skb_shinfo(skb)->frags[i].page,
905 skb_shinfo(skb)->frags[i].page_offset,
906 skb_shinfo(skb)->frags[i].size,
907 PCI_DMA_FROMDEVICE);
908}
909
910static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
911{
912 struct sk_buff *skb = re->skb;
913 int i;
914
915 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
916 PCI_DMA_FROMDEVICE);
917
918 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
919 pci_unmap_page(pdev, re->frag_addr[i],
920 skb_shinfo(skb)->frags[i].size,
921 PCI_DMA_FROMDEVICE);
922}
Stephen Hemminger793b8832005-09-14 16:06:14 -0700923
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700924/* Tell chip where to start receive checksum.
925 * Actually has two checksums, but set both same to avoid possible byte
926 * order problems.
927 */
Stephen Hemminger793b8832005-09-14 16:06:14 -0700928static void rx_set_checksum(struct sky2_port *sky2)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700929{
930 struct sky2_rx_le *le;
931
Stephen Hemminger793b8832005-09-14 16:06:14 -0700932 le = sky2_next_rx(sky2);
Stephen Hemmingerf65b1382006-09-06 12:45:02 -0700933 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700934 le->ctrl = 0;
935 le->opcode = OP_TCPSTART | HW_OWNER;
936
Stephen Hemminger793b8832005-09-14 16:06:14 -0700937 sky2_write32(sky2->hw,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700938 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
939 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
940
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700941}
942
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700943/*
944 * The RX Stop command will not work for Yukon-2 if the BMU does not
945 * reach the end of packet and since we can't make sure that we have
946 * incoming data, we must reset the BMU while it is not doing a DMA
947 * transfer. Since it is possible that the RX path is still active,
948 * the RX RAM buffer will be stopped first, so any possible incoming
949 * data will not trigger a DMA. After the RAM buffer is stopped, the
950 * BMU is polled until any DMA in progress is ended and only then it
951 * will be reset.
952 */
953static void sky2_rx_stop(struct sky2_port *sky2)
954{
955 struct sky2_hw *hw = sky2->hw;
956 unsigned rxq = rxqaddr[sky2->port];
957 int i;
958
959 /* disable the RAM Buffer receive queue */
960 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
961
962 for (i = 0; i < 0xffff; i++)
963 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
964 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
965 goto stopped;
966
967 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
968 sky2->netdev->name);
969stopped:
970 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
971
972 /* reset the Rx prefetch unit */
973 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
974}
Stephen Hemminger793b8832005-09-14 16:06:14 -0700975
shemminger@osdl.orgd571b692005-10-26 12:16:09 -0700976/* Clean out receive buffer area, assumes receiver hardware stopped */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700977static void sky2_rx_clean(struct sky2_port *sky2)
978{
979 unsigned i;
980
981 memset(sky2->rx_le, 0, RX_LE_BYTES);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700982 for (i = 0; i < sky2->rx_pending; i++) {
Stephen Hemminger291ea612006-09-26 11:57:41 -0700983 struct rx_ring_info *re = sky2->rx_ring + i;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700984
985 if (re->skb) {
Stephen Hemminger14d02632006-09-26 11:57:43 -0700986 sky2_rx_unmap_skb(sky2->hw->pdev, re);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700987 kfree_skb(re->skb);
988 re->skb = NULL;
989 }
990 }
991}
992
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800993/* Basic MII support */
994static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
995{
996 struct mii_ioctl_data *data = if_mii(ifr);
997 struct sky2_port *sky2 = netdev_priv(dev);
998 struct sky2_hw *hw = sky2->hw;
999 int err = -EOPNOTSUPP;
1000
1001 if (!netif_running(dev))
1002 return -ENODEV; /* Phy still in reset */
1003
Stephen Hemmingerd89e1342006-03-20 15:48:20 -08001004 switch (cmd) {
shemminger@osdl.orgef743d32005-11-30 11:45:12 -08001005 case SIOCGMIIPHY:
1006 data->phy_id = PHY_ADDR_MARV;
1007
1008 /* fallthru */
1009 case SIOCGMIIREG: {
1010 u16 val = 0;
Stephen Hemminger91c86df2005-12-09 11:34:57 -08001011
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001012 spin_lock_bh(&sky2->phy_lock);
shemminger@osdl.orgef743d32005-11-30 11:45:12 -08001013 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001014 spin_unlock_bh(&sky2->phy_lock);
Stephen Hemminger91c86df2005-12-09 11:34:57 -08001015
shemminger@osdl.orgef743d32005-11-30 11:45:12 -08001016 data->val_out = val;
1017 break;
1018 }
1019
1020 case SIOCSMIIREG:
1021 if (!capable(CAP_NET_ADMIN))
1022 return -EPERM;
1023
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001024 spin_lock_bh(&sky2->phy_lock);
shemminger@osdl.orgef743d32005-11-30 11:45:12 -08001025 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1026 data->val_in);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001027 spin_unlock_bh(&sky2->phy_lock);
shemminger@osdl.orgef743d32005-11-30 11:45:12 -08001028 break;
1029 }
1030 return err;
1031}
1032
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001033#ifdef SKY2_VLAN_TAG_USED
1034static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1035{
1036 struct sky2_port *sky2 = netdev_priv(dev);
1037 struct sky2_hw *hw = sky2->hw;
1038 u16 port = sky2->port;
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001039
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07001040 netif_tx_lock_bh(dev);
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001041
1042 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
1043 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
1044 sky2->vlgrp = grp;
1045
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07001046 netif_tx_unlock_bh(dev);
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001047}
1048
1049static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1050{
1051 struct sky2_port *sky2 = netdev_priv(dev);
1052 struct sky2_hw *hw = sky2->hw;
1053 u16 port = sky2->port;
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001054
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07001055 netif_tx_lock_bh(dev);
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001056
1057 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1058 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
Dan Aloni5c15bde2007-03-02 20:44:51 -08001059 vlan_group_set_device(sky2->vlgrp, vid, NULL);
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001060
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07001061 netif_tx_unlock_bh(dev);
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001062}
1063#endif
1064
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001065/*
Stephen Hemminger14d02632006-09-26 11:57:43 -07001066 * Allocate an skb for receiving. If the MTU is large enough
1067 * make the skb non-linear with a fragment list of pages.
1068 *
Stephen Hemminger82788c72006-01-17 13:43:10 -08001069 * It appears the hardware has a bug in the FIFO logic that
1070 * cause it to hang if the FIFO gets overrun and the receive buffer
shemminger@osdl.org497d7c82006-08-28 10:00:46 -07001071 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1072 * aligned except if slab debugging is enabled.
Stephen Hemminger82788c72006-01-17 13:43:10 -08001073 */
Stephen Hemminger14d02632006-09-26 11:57:43 -07001074static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
Stephen Hemminger82788c72006-01-17 13:43:10 -08001075{
1076 struct sk_buff *skb;
Stephen Hemminger14d02632006-09-26 11:57:43 -07001077 unsigned long p;
1078 int i;
Stephen Hemminger82788c72006-01-17 13:43:10 -08001079
Stephen Hemminger14d02632006-09-26 11:57:43 -07001080 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1081 if (!skb)
1082 goto nomem;
1083
1084 p = (unsigned long) skb->data;
1085 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1086
1087 for (i = 0; i < sky2->rx_nfrags; i++) {
1088 struct page *page = alloc_page(GFP_ATOMIC);
1089
1090 if (!page)
1091 goto free_partial;
1092 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
Stephen Hemminger82788c72006-01-17 13:43:10 -08001093 }
1094
1095 return skb;
Stephen Hemminger14d02632006-09-26 11:57:43 -07001096free_partial:
1097 kfree_skb(skb);
1098nomem:
1099 return NULL;
Stephen Hemminger82788c72006-01-17 13:43:10 -08001100}
1101
1102/*
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001103 * Allocate and setup receiver buffer pool.
Stephen Hemminger14d02632006-09-26 11:57:43 -07001104 * Normal case this ends up creating one list element for skb
1105 * in the receive ring. Worst case if using large MTU and each
1106 * allocation falls on a different 64 bit region, that results
1107 * in 6 list elements per ring entry.
1108 * One element is used for checksum enable/disable, and one
1109 * extra to avoid wrap.
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001110 */
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001111static int sky2_rx_start(struct sky2_port *sky2)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001112{
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001113 struct sky2_hw *hw = sky2->hw;
Stephen Hemminger14d02632006-09-26 11:57:43 -07001114 struct rx_ring_info *re;
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001115 unsigned rxq = rxqaddr[sky2->port];
Stephen Hemminger14d02632006-09-26 11:57:43 -07001116 unsigned i, size, space, thresh;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001117
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001118 sky2->rx_put = sky2->rx_next = 0;
shemminger@osdl.orgaf4ed7e2005-11-30 11:45:21 -08001119 sky2_qset(hw, rxq);
Stephen Hemminger977bdf02006-02-22 11:44:58 -08001120
Stephen Hemmingerc3905bc2006-12-04 17:08:19 -08001121 /* On PCI express lowering the watermark gives better performance */
1122 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1123 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1124
1125 /* These chips have no ram buffer?
1126 * MAC Rx RAM Read is controlled by hardware */
Stephen Hemminger8df9a872006-12-01 14:29:35 -08001127 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
Stephen Hemmingerc3905bc2006-12-04 17:08:19 -08001128 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1129 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
Stephen Hemminger977bdf02006-02-22 11:44:58 -08001130 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
Stephen Hemminger977bdf02006-02-22 11:44:58 -08001131
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001132 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1133
1134 rx_set_checksum(sky2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001135
Stephen Hemminger14d02632006-09-26 11:57:43 -07001136 /* Space needed for frame data + headers rounded up */
1137 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1138 + 8;
1139
1140 /* Stopping point for hardware truncation */
1141 thresh = (size - 8) / sizeof(u32);
1142
1143 /* Account for overhead of skb - to avoid order > 0 allocation */
1144 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1145 + sizeof(struct skb_shared_info);
1146
1147 sky2->rx_nfrags = space >> PAGE_SHIFT;
1148 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1149
1150 if (sky2->rx_nfrags != 0) {
1151 /* Compute residue after pages */
1152 space = sky2->rx_nfrags << PAGE_SHIFT;
1153
1154 if (space < size)
1155 size -= space;
1156 else
1157 size = 0;
1158
1159 /* Optimize to handle small packets and headers */
1160 if (size < copybreak)
1161 size = copybreak;
1162 if (size < ETH_HLEN)
1163 size = ETH_HLEN;
1164 }
1165 sky2->rx_data_size = size;
1166
1167 /* Fill Rx ring */
1168 for (i = 0; i < sky2->rx_pending; i++) {
1169 re = sky2->rx_ring + i;
1170
1171 re->skb = sky2_rx_alloc(sky2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001172 if (!re->skb)
1173 goto nomem;
1174
Stephen Hemminger14d02632006-09-26 11:57:43 -07001175 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1176 sky2_rx_submit(sky2, re);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001177 }
1178
Stephen Hemmingera1433ac2006-05-22 12:03:42 -07001179 /*
1180 * The receiver hangs if it receives frames larger than the
1181 * packet buffer. As a workaround, truncate oversize frames, but
1182 * the register is limited to 9 bits, so if you do frames > 2052
1183 * you better get the MTU right!
1184 */
Stephen Hemmingera1433ac2006-05-22 12:03:42 -07001185 if (thresh > 0x1ff)
1186 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1187 else {
1188 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1189 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1190 }
1191
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001192 /* Tell chip about available buffers */
1193 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001194 return 0;
1195nomem:
1196 sky2_rx_clean(sky2);
1197 return -ENOMEM;
1198}
1199
1200/* Bring up network interface. */
1201static int sky2_up(struct net_device *dev)
1202{
1203 struct sky2_port *sky2 = netdev_priv(dev);
1204 struct sky2_hw *hw = sky2->hw;
1205 unsigned port = sky2->port;
Stephen Hemminger67712902006-12-04 15:53:45 -08001206 u32 ramsize, imask;
Stephen Hemmingeree7abb02006-05-18 11:16:21 -07001207 int cap, err = -ENOMEM;
Stephen Hemminger843a46f2006-05-11 15:07:28 -07001208 struct net_device *otherdev = hw->dev[sky2->port^1];
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001209
Stephen Hemmingeree7abb02006-05-18 11:16:21 -07001210 /*
1211 * On dual port PCI-X card, there is an problem where status
1212 * can be received out of order due to split transactions
Stephen Hemminger843a46f2006-05-11 15:07:28 -07001213 */
Stephen Hemmingeree7abb02006-05-18 11:16:21 -07001214 if (otherdev && netif_running(otherdev) &&
1215 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1216 struct sky2_port *osky2 = netdev_priv(otherdev);
1217 u16 cmd;
Stephen Hemminger843a46f2006-05-11 15:07:28 -07001218
Stephen Hemmingeree7abb02006-05-18 11:16:21 -07001219 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1220 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1221 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1222
1223 sky2->rx_csum = 0;
1224 osky2->rx_csum = 0;
1225 }
1226
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001227 if (netif_msg_ifup(sky2))
1228 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1229
1230 /* must be power of 2 */
1231 sky2->tx_le = pci_alloc_consistent(hw->pdev,
Stephen Hemminger793b8832005-09-14 16:06:14 -07001232 TX_RING_SIZE *
1233 sizeof(struct sky2_tx_le),
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001234 &sky2->tx_le_map);
1235 if (!sky2->tx_le)
1236 goto err_out;
1237
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001238 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001239 GFP_KERNEL);
1240 if (!sky2->tx_ring)
1241 goto err_out;
1242 sky2->tx_prod = sky2->tx_cons = 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001243
1244 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1245 &sky2->rx_le_map);
1246 if (!sky2->rx_le)
1247 goto err_out;
1248 memset(sky2->rx_le, 0, RX_LE_BYTES);
1249
Stephen Hemminger291ea612006-09-26 11:57:41 -07001250 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001251 GFP_KERNEL);
1252 if (!sky2->rx_ring)
1253 goto err_out;
1254
shemminger@osdl.orgd3bcfbe2006-08-28 10:00:51 -07001255 sky2_phy_power(hw, port, 1);
1256
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001257 sky2_mac_init(hw, port);
1258
Stephen Hemminger67712902006-12-04 15:53:45 -08001259 /* Register is number of 4K blocks on internal RAM buffer. */
1260 ramsize = sky2_read8(hw, B2_E_0) * 4;
1261 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
Stephen Hemminger470ea7e2006-10-20 17:06:11 -07001262
Stephen Hemminger67712902006-12-04 15:53:45 -08001263 if (ramsize > 0) {
1264 u32 rxspace;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001265
Stephen Hemminger67712902006-12-04 15:53:45 -08001266 if (ramsize < 16)
1267 rxspace = ramsize / 2;
1268 else
1269 rxspace = 8 + (2*(ramsize - 16))/3;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001270
Stephen Hemminger67712902006-12-04 15:53:45 -08001271 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1272 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1273
1274 /* Make sure SyncQ is disabled */
1275 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1276 RB_RST_SET);
1277 }
Stephen Hemminger793b8832005-09-14 16:06:14 -07001278
shemminger@osdl.orgaf4ed7e2005-11-30 11:45:21 -08001279 sky2_qset(hw, txqaddr[port]);
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -08001280
Stephen Hemminger977bdf02006-02-22 11:44:58 -08001281 /* Set almost empty threshold */
Stephen Hemmingerc2716fb2006-09-26 11:57:39 -07001282 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1283 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
Stephen Hemminger977bdf02006-02-22 11:44:58 -08001284 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -08001285
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001286 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1287 TX_RING_SIZE - 1);
1288
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001289 err = sky2_rx_start(sky2);
1290 if (err)
1291 goto err_out;
1292
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001293 /* Enable interrupts from phy/mac for port */
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001294 imask = sky2_read32(hw, B0_IMSK);
Stephen Hemmingerf4ea4312006-05-09 14:46:54 -07001295 imask |= portirq_msk[port];
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001296 sky2_write32(hw, B0_IMSK, imask);
1297
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001298 return 0;
1299
1300err_out:
Stephen Hemminger1b537562005-12-20 15:08:07 -08001301 if (sky2->rx_le) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001302 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1303 sky2->rx_le, sky2->rx_le_map);
Stephen Hemminger1b537562005-12-20 15:08:07 -08001304 sky2->rx_le = NULL;
1305 }
1306 if (sky2->tx_le) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001307 pci_free_consistent(hw->pdev,
1308 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1309 sky2->tx_le, sky2->tx_le_map);
Stephen Hemminger1b537562005-12-20 15:08:07 -08001310 sky2->tx_le = NULL;
1311 }
1312 kfree(sky2->tx_ring);
1313 kfree(sky2->rx_ring);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001314
Stephen Hemminger1b537562005-12-20 15:08:07 -08001315 sky2->tx_ring = NULL;
1316 sky2->rx_ring = NULL;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001317 return err;
1318}
1319
Stephen Hemminger793b8832005-09-14 16:06:14 -07001320/* Modular subtraction in ring */
1321static inline int tx_dist(unsigned tail, unsigned head)
1322{
Stephen Hemmingercb5d9542006-05-08 15:11:29 -07001323 return (head - tail) & (TX_RING_SIZE - 1);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001324}
1325
1326/* Number of list elements available for next tx */
1327static inline int tx_avail(const struct sky2_port *sky2)
1328{
1329 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1330}
1331
1332/* Estimate of number of transmit list elements required */
Stephen Hemminger28bd1812006-01-17 13:43:19 -08001333static unsigned tx_le_req(const struct sk_buff *skb)
Stephen Hemminger793b8832005-09-14 16:06:14 -07001334{
1335 unsigned count;
1336
1337 count = sizeof(dma_addr_t) / sizeof(u32);
1338 count += skb_shinfo(skb)->nr_frags * count;
1339
Herbert Xu89114af2006-07-08 13:34:32 -07001340 if (skb_is_gso(skb))
Stephen Hemminger793b8832005-09-14 16:06:14 -07001341 ++count;
1342
Patrick McHardy84fa7932006-08-29 16:44:56 -07001343 if (skb->ip_summed == CHECKSUM_PARTIAL)
Stephen Hemminger793b8832005-09-14 16:06:14 -07001344 ++count;
1345
1346 return count;
1347}
1348
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001349/*
Stephen Hemminger793b8832005-09-14 16:06:14 -07001350 * Put one packet in ring for transmit.
1351 * A single packet can generate multiple list elements, and
1352 * the number of ring elements will probably be less than the number
1353 * of list elements used.
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001354 */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001355static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1356{
1357 struct sky2_port *sky2 = netdev_priv(dev);
1358 struct sky2_hw *hw = sky2->hw;
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001359 struct sky2_tx_le *le = NULL;
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001360 struct tx_ring_info *re;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001361 unsigned i, len;
1362 dma_addr_t mapping;
1363 u32 addr64;
1364 u16 mss;
1365 u8 ctrl;
1366
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07001367 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1368 return NETDEV_TX_BUSY;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001369
Stephen Hemminger793b8832005-09-14 16:06:14 -07001370 if (unlikely(netif_msg_tx_queued(sky2)))
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001371 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1372 dev->name, sky2->tx_prod, skb->len);
1373
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001374 len = skb_headlen(skb);
1375 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
shemminger@osdl.orga018e332005-11-30 11:45:16 -08001376 addr64 = high32(mapping);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001377
shemminger@osdl.orga018e332005-11-30 11:45:16 -08001378 /* Send high bits if changed or crosses boundary */
1379 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07001380 le = get_tx_le(sky2);
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07001381 le->addr = cpu_to_le32(addr64);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001382 le->opcode = OP_ADDR64 | HW_OWNER;
shemminger@osdl.orga018e332005-11-30 11:45:16 -08001383 sky2->tx_addr64 = high32(mapping + len);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001384 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001385
1386 /* Check for TCP Segmentation Offload */
Herbert Xu79671682006-06-22 02:40:14 -07001387 mss = skb_shinfo(skb)->gso_size;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001388 if (mss != 0) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001389 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1390 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1391 mss += ETH_HLEN;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001392
shemminger@osdl.orge07560c2006-08-28 10:00:49 -07001393 if (mss != sky2->tx_last_mss) {
1394 le = get_tx_le(sky2);
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07001395 le->addr = cpu_to_le32(mss);
shemminger@osdl.orge07560c2006-08-28 10:00:49 -07001396 le->opcode = OP_LRGLEN | HW_OWNER;
shemminger@osdl.orge07560c2006-08-28 10:00:49 -07001397 sky2->tx_last_mss = mss;
1398 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001399 }
1400
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001401 ctrl = 0;
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001402#ifdef SKY2_VLAN_TAG_USED
1403 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1404 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1405 if (!le) {
1406 le = get_tx_le(sky2);
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07001407 le->addr = 0;
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001408 le->opcode = OP_VLAN|HW_OWNER;
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001409 } else
1410 le->opcode |= OP_VLAN;
1411 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1412 ctrl |= INS_VLAN;
1413 }
1414#endif
1415
1416 /* Handle TCP checksum offload */
Patrick McHardy84fa7932006-08-29 16:44:56 -07001417 if (skb->ip_summed == CHECKSUM_PARTIAL) {
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07001418 unsigned offset = skb->h.raw - skb->data;
1419 u32 tcpsum;
1420
1421 tcpsum = offset << 16; /* sum start */
Al Viroff1dcad2006-11-20 18:07:29 -08001422 tcpsum |= offset + skb->csum_offset; /* sum write */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001423
1424 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1425 if (skb->nh.iph->protocol == IPPROTO_UDP)
1426 ctrl |= UDPTCP;
1427
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07001428 if (tcpsum != sky2->tx_tcpsum) {
1429 sky2->tx_tcpsum = tcpsum;
shemminger@osdl.org1d179332006-08-28 10:00:50 -07001430
1431 le = get_tx_le(sky2);
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07001432 le->addr = cpu_to_le32(tcpsum);
shemminger@osdl.org1d179332006-08-28 10:00:50 -07001433 le->length = 0; /* initial checksum value */
1434 le->ctrl = 1; /* one packet */
1435 le->opcode = OP_TCPLISW | HW_OWNER;
1436 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001437 }
1438
1439 le = get_tx_le(sky2);
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07001440 le->addr = cpu_to_le32((u32) mapping);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001441 le->length = cpu_to_le16(len);
1442 le->ctrl = ctrl;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001443 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001444
Stephen Hemminger291ea612006-09-26 11:57:41 -07001445 re = tx_le_re(sky2, le);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001446 re->skb = skb;
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001447 pci_unmap_addr_set(re, mapaddr, mapping);
Stephen Hemminger291ea612006-09-26 11:57:41 -07001448 pci_unmap_len_set(re, maplen, len);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001449
1450 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
Stephen Hemminger291ea612006-09-26 11:57:41 -07001451 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001452
1453 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1454 frag->size, PCI_DMA_TODEVICE);
Stephen Hemmingera0361192006-01-17 13:43:16 -08001455 addr64 = high32(mapping);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001456 if (addr64 != sky2->tx_addr64) {
1457 le = get_tx_le(sky2);
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07001458 le->addr = cpu_to_le32(addr64);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001459 le->ctrl = 0;
1460 le->opcode = OP_ADDR64 | HW_OWNER;
1461 sky2->tx_addr64 = addr64;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001462 }
1463
1464 le = get_tx_le(sky2);
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07001465 le->addr = cpu_to_le32((u32) mapping);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001466 le->length = cpu_to_le16(frag->size);
1467 le->ctrl = ctrl;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001468 le->opcode = OP_BUFFER | HW_OWNER;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001469
Stephen Hemminger291ea612006-09-26 11:57:41 -07001470 re = tx_le_re(sky2, le);
1471 re->skb = skb;
1472 pci_unmap_addr_set(re, mapaddr, mapping);
1473 pci_unmap_len_set(re, maplen, frag->size);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001474 }
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001475
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001476 le->ctrl |= EOP;
1477
shemminger@osdl.org97bda702006-08-28 10:00:47 -07001478 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1479 netif_stop_queue(dev);
Stephen Hemmingerb19666d2006-03-07 11:06:36 -08001480
Stephen Hemminger290d4de2006-03-20 15:48:15 -08001481 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001482
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001483 dev->trans_start = jiffies;
1484 return NETDEV_TX_OK;
1485}
1486
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001487/*
Stephen Hemminger793b8832005-09-14 16:06:14 -07001488 * Free ring elements from starting at tx_cons until "done"
1489 *
1490 * NB: the hardware will tell us about partial completion of multi-part
Stephen Hemminger291ea612006-09-26 11:57:41 -07001491 * buffers so make sure not to free skb to early.
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001492 */
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001493static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001494{
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001495 struct net_device *dev = sky2->netdev;
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08001496 struct pci_dev *pdev = sky2->hw->pdev;
Stephen Hemminger291ea612006-09-26 11:57:41 -07001497 unsigned idx;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001498
Stephen Hemminger0e3ff6a2005-12-09 11:35:02 -08001499 BUG_ON(done >= TX_RING_SIZE);
shemminger@osdl.org22247952005-11-30 11:45:19 -08001500
Stephen Hemminger291ea612006-09-26 11:57:41 -07001501 for (idx = sky2->tx_cons; idx != done;
1502 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1503 struct sky2_tx_le *le = sky2->tx_le + idx;
1504 struct tx_ring_info *re = sky2->tx_ring + idx;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001505
Stephen Hemminger291ea612006-09-26 11:57:41 -07001506 switch(le->opcode & ~HW_OWNER) {
1507 case OP_LARGESEND:
1508 case OP_PACKET:
1509 pci_unmap_single(pdev,
1510 pci_unmap_addr(re, mapaddr),
1511 pci_unmap_len(re, maplen),
1512 PCI_DMA_TODEVICE);
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08001513 break;
Stephen Hemminger291ea612006-09-26 11:57:41 -07001514 case OP_BUFFER:
1515 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1516 pci_unmap_len(re, maplen),
Stephen Hemminger734d1862005-12-09 11:35:00 -08001517 PCI_DMA_TODEVICE);
Stephen Hemminger291ea612006-09-26 11:57:41 -07001518 break;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001519 }
1520
Stephen Hemminger291ea612006-09-26 11:57:41 -07001521 if (le->ctrl & EOP) {
1522 if (unlikely(netif_msg_tx_done(sky2)))
1523 printk(KERN_DEBUG "%s: tx done %u\n",
1524 dev->name, idx);
shemminger@linux-foundation.org2bf56fe2007-01-26 11:38:39 -08001525 sky2->net_stats.tx_packets++;
1526 sky2->net_stats.tx_bytes += re->skb->len;
1527
Stephen Hemminger794b2bd2006-12-01 14:29:36 -08001528 dev_kfree_skb_any(re->skb);
Stephen Hemminger291ea612006-09-26 11:57:41 -07001529 }
1530
1531 le->opcode = 0; /* paranoia */
Stephen Hemminger793b8832005-09-14 16:06:14 -07001532 }
Stephen Hemminger793b8832005-09-14 16:06:14 -07001533
Stephen Hemminger291ea612006-09-26 11:57:41 -07001534 sky2->tx_cons = idx;
Stephen Hemminger22e11702006-07-12 15:23:48 -07001535 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001536 netif_wake_queue(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001537}
1538
1539/* Cleanup all untransmitted buffers, assume transmitter not running */
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07001540static void sky2_tx_clean(struct net_device *dev)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001541{
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07001542 struct sky2_port *sky2 = netdev_priv(dev);
1543
1544 netif_tx_lock_bh(dev);
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001545 sky2_tx_complete(sky2, sky2->tx_prod);
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07001546 netif_tx_unlock_bh(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001547}
1548
1549/* Network shutdown */
1550static int sky2_down(struct net_device *dev)
1551{
1552 struct sky2_port *sky2 = netdev_priv(dev);
1553 struct sky2_hw *hw = sky2->hw;
1554 unsigned port = sky2->port;
1555 u16 ctrl;
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001556 u32 imask;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001557
Stephen Hemminger1b537562005-12-20 15:08:07 -08001558 /* Never really got started! */
1559 if (!sky2->tx_le)
1560 return 0;
1561
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001562 if (netif_msg_ifdown(sky2))
1563 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1564
shemminger@osdl.org018d1c62005-11-30 11:45:18 -08001565 /* Stop more packets from being queued */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001566 netif_stop_queue(dev);
Stephen Hemminger9a872402007-04-07 16:02:26 -07001567 netif_carrier_off(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001568
Stephen Hemmingerebc646f2006-10-17 10:23:56 -07001569 /* Disable port IRQ */
1570 imask = sky2_read32(hw, B0_IMSK);
1571 imask &= ~portirq_msk[port];
1572 sky2_write32(hw, B0_IMSK, imask);
1573
Stephen Hemminger25d82d72006-12-20 13:06:33 -08001574 /*
1575 * Both ports share the NAPI poll on port 0, so if necessary undo the
1576 * the disable that is done in dev_close.
1577 */
1578 if (sky2->port == 0 && hw->ports > 1)
1579 netif_poll_enable(dev);
1580
shemminger@osdl.orgd3bcfbe2006-08-28 10:00:51 -07001581 sky2_gmac_reset(hw, port);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001582
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001583 /* Stop transmitter */
1584 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1585 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1586
1587 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
Stephen Hemminger793b8832005-09-14 16:06:14 -07001588 RB_RST_SET | RB_DIS_OP_MD);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001589
Stephen Hemmingerc2716fb2006-09-26 11:57:39 -07001590 /* WA for dev. #4.209 */
1591 if (hw->chip_id == CHIP_ID_YUKON_EC_U
Stephen Hemminger8df9a872006-12-01 14:29:35 -08001592 && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
Stephen Hemmingerc2716fb2006-09-26 11:57:39 -07001593 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1594 sky2->speed != SPEED_1000 ?
1595 TX_STFW_ENA : TX_STFW_DIS);
1596
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001597 ctrl = gma_read16(hw, port, GM_GP_CTRL);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001598 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001599 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1600
1601 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1602
1603 /* Workaround shared GMAC reset */
Stephen Hemminger793b8832005-09-14 16:06:14 -07001604 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1605 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001606 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1607
1608 /* Disable Force Sync bit and Enable Alloc bit */
1609 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1610 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1611
1612 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1613 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1614 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1615
1616 /* Reset the PCI FIFO of the async Tx queue */
Stephen Hemminger793b8832005-09-14 16:06:14 -07001617 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1618 BMU_RST_SET | BMU_FIFO_RST);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001619
1620 /* Reset the Tx prefetch units */
1621 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1622 PREF_UNIT_RST_SET);
1623
1624 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1625
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001626 sky2_rx_stop(sky2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001627
1628 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1629 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1630
shemminger@osdl.orgd3bcfbe2006-08-28 10:00:51 -07001631 sky2_phy_power(hw, port, 0);
1632
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07001633 /* turn off LED's */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001634 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1635
shemminger@osdl.org018d1c62005-11-30 11:45:18 -08001636 synchronize_irq(hw->pdev->irq);
1637
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07001638 sky2_tx_clean(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001639 sky2_rx_clean(sky2);
1640
1641 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1642 sky2->rx_le, sky2->rx_le_map);
1643 kfree(sky2->rx_ring);
1644
1645 pci_free_consistent(hw->pdev,
1646 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1647 sky2->tx_le, sky2->tx_le_map);
1648 kfree(sky2->tx_ring);
1649
Stephen Hemminger1b537562005-12-20 15:08:07 -08001650 sky2->tx_le = NULL;
1651 sky2->rx_le = NULL;
1652
1653 sky2->rx_ring = NULL;
1654 sky2->tx_ring = NULL;
1655
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001656 return 0;
1657}
1658
1659static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1660{
Stephen Hemmingerb89165f2006-09-06 12:44:53 -07001661 if (!sky2_is_copper(hw))
Stephen Hemminger793b8832005-09-14 16:06:14 -07001662 return SPEED_1000;
1663
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001664 if (hw->chip_id == CHIP_ID_YUKON_FE)
1665 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1666
1667 switch (aux & PHY_M_PS_SPEED_MSK) {
1668 case PHY_M_PS_SPEED_1000:
1669 return SPEED_1000;
1670 case PHY_M_PS_SPEED_100:
1671 return SPEED_100;
1672 default:
1673 return SPEED_10;
1674 }
1675}
1676
1677static void sky2_link_up(struct sky2_port *sky2)
1678{
1679 struct sky2_hw *hw = sky2->hw;
1680 unsigned port = sky2->port;
1681 u16 reg;
Stephen Hemminger16ad91e2006-10-17 10:24:13 -07001682 static const char *fc_name[] = {
1683 [FC_NONE] = "none",
1684 [FC_TX] = "tx",
1685 [FC_RX] = "rx",
1686 [FC_BOTH] = "both",
1687 };
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001688
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001689 /* enable Rx/Tx */
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -07001690 reg = gma_read16(hw, port, GM_GP_CTRL);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001691 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1692 gma_write16(hw, port, GM_GP_CTRL, reg);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001693
1694 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1695
1696 netif_carrier_on(sky2->netdev);
1697 netif_wake_queue(sky2->netdev);
1698
1699 /* Turn on link LED */
Stephen Hemminger793b8832005-09-14 16:06:14 -07001700 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001701 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1702
Stephen Hemminger93745492007-02-06 10:45:43 -08001703 if (hw->chip_id == CHIP_ID_YUKON_XL
1704 || hw->chip_id == CHIP_ID_YUKON_EC_U
1705 || hw->chip_id == CHIP_ID_YUKON_EX) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07001706 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
Stephen Hemmingered6d32c2006-05-08 15:11:33 -07001707 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1708
1709 switch(sky2->speed) {
1710 case SPEED_10:
1711 led |= PHY_M_LEDC_INIT_CTRL(7);
1712 break;
1713
1714 case SPEED_100:
1715 led |= PHY_M_LEDC_STA1_CTRL(7);
1716 break;
1717
1718 case SPEED_1000:
1719 led |= PHY_M_LEDC_STA0_CTRL(7);
1720 break;
1721 }
Stephen Hemminger793b8832005-09-14 16:06:14 -07001722
1723 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
Stephen Hemmingered6d32c2006-05-08 15:11:33 -07001724 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001725 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1726 }
1727
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001728 if (netif_msg_link(sky2))
1729 printk(KERN_INFO PFX
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07001730 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001731 sky2->netdev->name, sky2->speed,
1732 sky2->duplex == DUPLEX_FULL ? "full" : "half",
Stephen Hemminger16ad91e2006-10-17 10:24:13 -07001733 fc_name[sky2->flow_status]);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001734}
1735
1736static void sky2_link_down(struct sky2_port *sky2)
1737{
1738 struct sky2_hw *hw = sky2->hw;
1739 unsigned port = sky2->port;
1740 u16 reg;
1741
1742 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1743
1744 reg = gma_read16(hw, port, GM_GP_CTRL);
1745 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1746 gma_write16(hw, port, GM_GP_CTRL, reg);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001747
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001748 netif_carrier_off(sky2->netdev);
1749 netif_stop_queue(sky2->netdev);
1750
1751 /* Turn on link LED */
1752 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1753
1754 if (netif_msg_link(sky2))
1755 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -07001756
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001757 sky2_phy_init(hw, port);
1758}
1759
Stephen Hemminger16ad91e2006-10-17 10:24:13 -07001760static enum flow_control sky2_flow(int rx, int tx)
1761{
1762 if (rx)
1763 return tx ? FC_BOTH : FC_RX;
1764 else
1765 return tx ? FC_TX : FC_NONE;
1766}
1767
Stephen Hemminger793b8832005-09-14 16:06:14 -07001768static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1769{
1770 struct sky2_hw *hw = sky2->hw;
1771 unsigned port = sky2->port;
Stephen Hemmingerda4c1ff2007-02-15 16:40:32 -08001772 u16 advert, lpa;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001773
Stephen Hemmingerda4c1ff2007-02-15 16:40:32 -08001774 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001775 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001776 if (lpa & PHY_M_AN_RF) {
1777 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1778 return -1;
1779 }
1780
Stephen Hemminger793b8832005-09-14 16:06:14 -07001781 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1782 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1783 sky2->netdev->name);
1784 return -1;
1785 }
1786
Stephen Hemminger793b8832005-09-14 16:06:14 -07001787 sky2->speed = sky2_phy_speed(hw, aux);
Stephen Hemminger7c74ac12006-10-17 10:24:08 -07001788 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001789
Stephen Hemmingerda4c1ff2007-02-15 16:40:32 -08001790 /* Since the pause result bits seem to in different positions on
1791 * different chips. look at registers.
1792 */
1793 if (!sky2_is_copper(hw)) {
1794 /* Shift for bits in fiber PHY */
1795 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1796 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001797
Stephen Hemmingerda4c1ff2007-02-15 16:40:32 -08001798 if (advert & ADVERTISE_1000XPAUSE)
1799 advert |= ADVERTISE_PAUSE_CAP;
1800 if (advert & ADVERTISE_1000XPSE_ASYM)
1801 advert |= ADVERTISE_PAUSE_ASYM;
1802 if (lpa & LPA_1000XPAUSE)
1803 lpa |= LPA_PAUSE_CAP;
1804 if (lpa & LPA_1000XPAUSE_ASYM)
1805 lpa |= LPA_PAUSE_ASYM;
1806 }
1807
1808 sky2->flow_status = FC_NONE;
1809 if (advert & ADVERTISE_PAUSE_CAP) {
1810 if (lpa & LPA_PAUSE_CAP)
1811 sky2->flow_status = FC_BOTH;
1812 else if (advert & ADVERTISE_PAUSE_ASYM)
1813 sky2->flow_status = FC_RX;
1814 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1815 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1816 sky2->flow_status = FC_TX;
1817 }
Stephen Hemminger793b8832005-09-14 16:06:14 -07001818
Stephen Hemminger16ad91e2006-10-17 10:24:13 -07001819 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
Stephen Hemminger93745492007-02-06 10:45:43 -08001820 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
Stephen Hemminger16ad91e2006-10-17 10:24:13 -07001821 sky2->flow_status = FC_NONE;
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -07001822
Stephen Hemmingerda4c1ff2007-02-15 16:40:32 -08001823 if (sky2->flow_status & FC_TX)
Stephen Hemminger793b8832005-09-14 16:06:14 -07001824 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1825 else
1826 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1827
1828 return 0;
1829}
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001830
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001831/* Interrupt from PHY */
1832static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001833{
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001834 struct net_device *dev = hw->dev[port];
1835 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001836 u16 istatus, phystat;
1837
Stephen Hemmingerebc646f2006-10-17 10:23:56 -07001838 if (!netif_running(dev))
1839 return;
1840
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001841 spin_lock(&sky2->phy_lock);
1842 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1843 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1844
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001845 if (netif_msg_intr(sky2))
1846 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1847 sky2->netdev->name, istatus, phystat);
1848
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -07001849 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07001850 if (sky2_autoneg_done(sky2, phystat) == 0)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001851 sky2_link_up(sky2);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001852 goto out;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001853 }
1854
Stephen Hemminger793b8832005-09-14 16:06:14 -07001855 if (istatus & PHY_M_IS_LSP_CHANGE)
1856 sky2->speed = sky2_phy_speed(hw, phystat);
1857
1858 if (istatus & PHY_M_IS_DUP_CHANGE)
1859 sky2->duplex =
1860 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1861
1862 if (istatus & PHY_M_IS_LST_CHANGE) {
1863 if (phystat & PHY_M_PS_LINK_UP)
1864 sky2_link_up(sky2);
1865 else
1866 sky2_link_down(sky2);
1867 }
1868out:
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001869 spin_unlock(&sky2->phy_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001870}
1871
Stephen Hemminger62335ab2007-02-06 10:45:42 -08001872/* Transmit timeout is only called if we are running, carrier is up
Stephen Hemminger302d1252006-01-17 13:43:20 -08001873 * and tx queue is full (stopped).
1874 */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001875static void sky2_tx_timeout(struct net_device *dev)
1876{
1877 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger8cc048e2005-12-09 11:35:07 -08001878 struct sky2_hw *hw = sky2->hw;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001879
1880 if (netif_msg_timer(sky2))
1881 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1882
Stephen Hemminger8f246642006-03-20 15:48:21 -08001883 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
Stephen Hemminger62335ab2007-02-06 10:45:42 -08001884 dev->name, sky2->tx_cons, sky2->tx_prod,
1885 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1886 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
Stephen Hemminger8cc048e2005-12-09 11:35:07 -08001887
Stephen Hemminger81906792007-02-15 16:40:33 -08001888 /* can't restart safely under softirq */
1889 schedule_work(&hw->restart_work);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001890}
1891
1892static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1893{
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001894 struct sky2_port *sky2 = netdev_priv(dev);
1895 struct sky2_hw *hw = sky2->hw;
1896 int err;
1897 u16 ctl, mode;
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001898 u32 imask;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001899
1900 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1901 return -EINVAL;
1902
Stephen Hemminger4a50a872007-02-06 10:45:41 -08001903 /* TSO on Yukon Ultra and MTU > 1500 not supported */
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -08001904 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
Stephen Hemminger4a50a872007-02-06 10:45:41 -08001905 dev->features &= ~NETIF_F_TSO;
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -08001906
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001907 if (!netif_running(dev)) {
1908 dev->mtu = new_mtu;
1909 return 0;
1910 }
1911
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001912 imask = sky2_read32(hw, B0_IMSK);
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001913 sky2_write32(hw, B0_IMSK, 0);
1914
shemminger@osdl.org018d1c62005-11-30 11:45:18 -08001915 dev->trans_start = jiffies; /* prevent tx timeout */
1916 netif_stop_queue(dev);
1917 netif_poll_disable(hw->dev[0]);
1918
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001919 synchronize_irq(hw->pdev->irq);
1920
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001921 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1922 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1923 sky2_rx_stop(sky2);
1924 sky2_rx_clean(sky2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001925
1926 dev->mtu = new_mtu;
Stephen Hemminger14d02632006-09-26 11:57:43 -07001927
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001928 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1929 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001930
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001931 if (dev->mtu > ETH_DATA_LEN)
1932 mode |= GM_SMOD_JUMBO_ENA;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001933
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001934 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1935
1936 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1937
1938 err = sky2_rx_start(sky2);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001939 sky2_write32(hw, B0_IMSK, imask);
shemminger@osdl.org018d1c62005-11-30 11:45:18 -08001940
Stephen Hemminger1b537562005-12-20 15:08:07 -08001941 if (err)
1942 dev_close(dev);
1943 else {
1944 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1945
1946 netif_poll_enable(hw->dev[0]);
1947 netif_wake_queue(dev);
1948 }
1949
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001950 return err;
1951}
1952
Stephen Hemminger14d02632006-09-26 11:57:43 -07001953/* For small just reuse existing skb for next receive */
1954static struct sk_buff *receive_copy(struct sky2_port *sky2,
1955 const struct rx_ring_info *re,
1956 unsigned length)
1957{
1958 struct sk_buff *skb;
1959
1960 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1961 if (likely(skb)) {
1962 skb_reserve(skb, 2);
1963 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1964 length, PCI_DMA_FROMDEVICE);
1965 memcpy(skb->data, re->skb->data, length);
1966 skb->ip_summed = re->skb->ip_summed;
1967 skb->csum = re->skb->csum;
1968 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1969 length, PCI_DMA_FROMDEVICE);
1970 re->skb->ip_summed = CHECKSUM_NONE;
Stephen Hemminger489b10c2006-10-03 16:39:12 -07001971 skb_put(skb, length);
Stephen Hemminger14d02632006-09-26 11:57:43 -07001972 }
1973 return skb;
1974}
1975
1976/* Adjust length of skb with fragments to match received data */
1977static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1978 unsigned int length)
1979{
1980 int i, num_frags;
1981 unsigned int size;
1982
1983 /* put header into skb */
1984 size = min(length, hdr_space);
1985 skb->tail += size;
1986 skb->len += size;
1987 length -= size;
1988
1989 num_frags = skb_shinfo(skb)->nr_frags;
1990 for (i = 0; i < num_frags; i++) {
1991 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1992
1993 if (length == 0) {
1994 /* don't need this page */
1995 __free_page(frag->page);
1996 --skb_shinfo(skb)->nr_frags;
1997 } else {
1998 size = min(length, (unsigned) PAGE_SIZE);
1999
2000 frag->size = size;
2001 skb->data_len += size;
2002 skb->truesize += size;
2003 skb->len += size;
2004 length -= size;
2005 }
2006 }
2007}
2008
2009/* Normal packet - take skb from ring element and put in a new one */
2010static struct sk_buff *receive_new(struct sky2_port *sky2,
2011 struct rx_ring_info *re,
2012 unsigned int length)
2013{
2014 struct sk_buff *skb, *nskb;
2015 unsigned hdr_space = sky2->rx_data_size;
2016
2017 pr_debug(PFX "receive new length=%d\n", length);
2018
2019 /* Don't be tricky about reusing pages (yet) */
2020 nskb = sky2_rx_alloc(sky2);
2021 if (unlikely(!nskb))
2022 return NULL;
2023
2024 skb = re->skb;
2025 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2026
2027 prefetch(skb->data);
2028 re->skb = nskb;
2029 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2030
2031 if (skb_shinfo(skb)->nr_frags)
2032 skb_put_frags(skb, hdr_space, length);
2033 else
Stephen Hemminger489b10c2006-10-03 16:39:12 -07002034 skb_put(skb, length);
Stephen Hemminger14d02632006-09-26 11:57:43 -07002035 return skb;
2036}
2037
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002038/*
2039 * Receive one packet.
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07002040 * For larger packets, get new buffer.
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002041 */
shemminger@osdl.org497d7c82006-08-28 10:00:46 -07002042static struct sk_buff *sky2_receive(struct net_device *dev,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002043 u16 length, u32 status)
2044{
shemminger@osdl.org497d7c82006-08-28 10:00:46 -07002045 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger291ea612006-09-26 11:57:41 -07002046 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
Stephen Hemminger79e57d32005-09-19 15:42:33 -07002047 struct sk_buff *skb = NULL;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002048
2049 if (unlikely(netif_msg_rx_status(sky2)))
2050 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
shemminger@osdl.org497d7c82006-08-28 10:00:46 -07002051 dev->name, sky2->rx_next, status, length);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002052
Stephen Hemminger793b8832005-09-14 16:06:14 -07002053 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
Stephen Hemmingerd70cd512005-12-09 11:35:09 -08002054 prefetch(sky2->rx_ring + sky2->rx_next);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002055
shemminger@osdl.org42eeea02005-11-30 11:45:13 -08002056 if (status & GMR_FS_ANY_ERR)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002057 goto error;
2058
shemminger@osdl.org42eeea02005-11-30 11:45:13 -08002059 if (!(status & GMR_FS_RX_OK))
2060 goto resubmit;
2061
Stephen Hemminger14d02632006-09-26 11:57:43 -07002062 if (length < copybreak)
2063 skb = receive_copy(sky2, re, length);
2064 else
2065 skb = receive_new(sky2, re, length);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002066resubmit:
Stephen Hemminger14d02632006-09-26 11:57:43 -07002067 sky2_rx_submit(sky2, re);
Stephen Hemminger79e57d32005-09-19 15:42:33 -07002068
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002069 return skb;
2070
2071error:
Stephen Hemminger6e15b712005-12-20 15:08:09 -08002072 ++sky2->net_stats.rx_errors;
Stephen Hemmingerb6d77732006-10-17 10:24:16 -07002073 if (status & GMR_FS_RX_FF_OV) {
Stephen Hemmingera79abdc2007-02-15 16:40:34 -08002074 sky2->net_stats.rx_over_errors++;
Stephen Hemmingerb6d77732006-10-17 10:24:16 -07002075 goto resubmit;
2076 }
Stephen Hemminger6e15b712005-12-20 15:08:09 -08002077
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002078 if (netif_msg_rx_err(sky2) && net_ratelimit())
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002079 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
shemminger@osdl.org497d7c82006-08-28 10:00:46 -07002080 dev->name, status, length);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002081
2082 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002083 sky2->net_stats.rx_length_errors++;
2084 if (status & GMR_FS_FRAGMENT)
2085 sky2->net_stats.rx_frame_errors++;
2086 if (status & GMR_FS_CRC_ERR)
2087 sky2->net_stats.rx_crc_errors++;
Stephen Hemminger79e57d32005-09-19 15:42:33 -07002088
Stephen Hemminger793b8832005-09-14 16:06:14 -07002089 goto resubmit;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002090}
2091
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002092/* Transmit complete */
2093static inline void sky2_tx_done(struct net_device *dev, u16 last)
Stephen Hemminger13b97b72005-12-09 11:35:03 -08002094{
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002095 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger302d1252006-01-17 13:43:20 -08002096
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002097 if (netif_running(dev)) {
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07002098 netif_tx_lock(dev);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002099 sky2_tx_complete(sky2, last);
Stephen Hemminger2bb8c262006-09-26 11:57:42 -07002100 netif_tx_unlock(dev);
shemminger@osdl.org22247952005-11-30 11:45:19 -08002101 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002102}
2103
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002104/* Process status response ring */
2105static int sky2_status_intr(struct sky2_hw *hw, int to_do)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002106{
Stephen Hemminger22e11702006-07-12 15:23:48 -07002107 struct sky2_port *sky2;
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002108 int work_done = 0;
Stephen Hemminger22e11702006-07-12 15:23:48 -07002109 unsigned buf_write[2] = { 0, 0 };
Stephen Hemmingere71ebd72006-05-08 15:11:31 -07002110 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002111
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08002112 rmb();
shemminger@osdl.orgbea86102005-10-26 12:16:10 -07002113
Stephen Hemmingere71ebd72006-05-08 15:11:31 -07002114 while (hw->st_idx != hwidx) {
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08002115 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2116 struct net_device *dev;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002117 struct sk_buff *skb;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002118 u32 status;
2119 u16 length;
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002120
Stephen Hemmingercb5d9542006-05-08 15:11:29 -07002121 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
shemminger@osdl.orgbea86102005-10-26 12:16:10 -07002122
Stephen Hemmingere71ebd72006-05-08 15:11:31 -07002123 BUG_ON(le->link >= 2);
2124 dev = hw->dev[le->link];
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08002125
2126 sky2 = netdev_priv(dev);
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07002127 length = le16_to_cpu(le->length);
2128 status = le32_to_cpu(le->status);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002129
Stephen Hemmingere71ebd72006-05-08 15:11:31 -07002130 switch (le->opcode & ~HW_OWNER) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002131 case OP_RXSTAT:
shemminger@osdl.org497d7c82006-08-28 10:00:46 -07002132 skb = sky2_receive(dev, length, status);
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07002133 if (!skb)
Stephen Hemminger5df79112006-12-01 14:29:33 -08002134 goto force_update;
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08002135
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08002136 skb->protocol = eth_type_trans(skb, dev);
shemminger@linux-foundation.org2bf56fe2007-01-26 11:38:39 -08002137 sky2->net_stats.rx_packets++;
2138 sky2->net_stats.rx_bytes += skb->len;
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08002139 dev->last_rx = jiffies;
2140
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07002141#ifdef SKY2_VLAN_TAG_USED
2142 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2143 vlan_hwaccel_receive_skb(skb,
2144 sky2->vlgrp,
2145 be16_to_cpu(sky2->rx_tag));
2146 } else
2147#endif
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002148 netif_receive_skb(skb);
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08002149
Stephen Hemminger22e11702006-07-12 15:23:48 -07002150 /* Update receiver after 16 frames */
2151 if (++buf_write[le->link] == RX_BUF_WRITE) {
Stephen Hemminger5df79112006-12-01 14:29:33 -08002152force_update:
2153 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
Stephen Hemminger22e11702006-07-12 15:23:48 -07002154 buf_write[le->link] = 0;
2155 }
2156
2157 /* Stop after net poll weight */
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08002158 if (++work_done >= to_do)
2159 goto exit_loop;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002160 break;
2161
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07002162#ifdef SKY2_VLAN_TAG_USED
2163 case OP_RXVLAN:
2164 sky2->rx_tag = length;
2165 break;
2166
2167 case OP_RXCHKSVLAN:
2168 sky2->rx_tag = length;
2169 /* fall through */
2170#endif
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002171 case OP_RXCHKS:
Stephen Hemminger87418302007-03-08 12:42:30 -08002172 if (!sky2->rx_csum)
2173 break;
2174
2175 /* Both checksum counters are programmed to start at
2176 * the same offset, so unless there is a problem they
2177 * should match. This failure is an early indication that
2178 * hardware receive checksumming won't work.
2179 */
2180 if (likely(status >> 16 == (status & 0xffff))) {
2181 skb = sky2->rx_ring[sky2->rx_next].skb;
2182 skb->ip_summed = CHECKSUM_COMPLETE;
2183 skb->csum = status & 0xffff;
2184 } else {
2185 printk(KERN_NOTICE PFX "%s: hardware receive "
2186 "checksum problem (status = %#x)\n",
2187 dev->name, status);
2188 sky2->rx_csum = 0;
2189 sky2_write32(sky2->hw,
2190 Q_ADDR(rxqaddr[le->link], Q_CSR),
2191 BMU_DIS_RX_CHKSUM);
2192 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002193 break;
2194
2195 case OP_TXINDEXLE:
Stephen Hemminger13b97b72005-12-09 11:35:03 -08002196 /* TX index reports status for both ports */
Stephen Hemmingerf55925d2006-05-08 15:11:28 -07002197 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2198 sky2_tx_done(hw->dev[0], status & 0xfff);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002199 if (hw->dev[1])
2200 sky2_tx_done(hw->dev[1],
2201 ((status >> 24) & 0xff)
2202 | (u16)(length & 0xf) << 8);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002203 break;
2204
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002205 default:
2206 if (net_ratelimit())
Stephen Hemminger793b8832005-09-14 16:06:14 -07002207 printk(KERN_WARNING PFX
Stephen Hemmingere71ebd72006-05-08 15:11:31 -07002208 "unknown status opcode 0x%x\n", le->opcode);
2209 goto exit_loop;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002210 }
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08002211 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002212
Stephen Hemmingerfe2a24d2006-08-01 11:55:23 -07002213 /* Fully processed status ring so clear irq */
2214 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2215
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08002216exit_loop:
Stephen Hemminger22e11702006-07-12 15:23:48 -07002217 if (buf_write[0]) {
2218 sky2 = netdev_priv(hw->dev[0]);
2219 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2220 }
2221
2222 if (buf_write[1]) {
2223 sky2 = netdev_priv(hw->dev[1]);
2224 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2225 }
2226
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002227 return work_done;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002228}
2229
2230static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2231{
2232 struct net_device *dev = hw->dev[port];
2233
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002234 if (net_ratelimit())
2235 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2236 dev->name, status);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002237
2238 if (status & Y2_IS_PAR_RD1) {
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002239 if (net_ratelimit())
2240 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2241 dev->name);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002242 /* Clear IRQ */
2243 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2244 }
2245
2246 if (status & Y2_IS_PAR_WR1) {
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002247 if (net_ratelimit())
2248 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2249 dev->name);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002250
2251 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2252 }
2253
2254 if (status & Y2_IS_PAR_MAC1) {
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002255 if (net_ratelimit())
2256 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002257 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2258 }
2259
2260 if (status & Y2_IS_PAR_RX1) {
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002261 if (net_ratelimit())
2262 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002263 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2264 }
2265
2266 if (status & Y2_IS_TCP_TXA1) {
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002267 if (net_ratelimit())
2268 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2269 dev->name);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002270 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2271 }
2272}
2273
2274static void sky2_hw_intr(struct sky2_hw *hw)
2275{
2276 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2277
Stephen Hemminger793b8832005-09-14 16:06:14 -07002278 if (status & Y2_IS_TIST_OV)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002279 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002280
2281 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07002282 u16 pci_err;
2283
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002284 pci_err = sky2_pci_read16(hw, PCI_STATUS);
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002285 if (net_ratelimit())
Stephen Hemmingerb02a9252007-02-06 10:45:40 -08002286 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2287 pci_err);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002288
2289 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002290 sky2_pci_write16(hw, PCI_STATUS,
Stephen Hemminger91aeb3e2006-09-26 11:57:38 -07002291 pci_err | PCI_STATUS_ERROR_BITS);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002292 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2293 }
2294
2295 if (status & Y2_IS_PCI_EXP) {
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07002296 /* PCI-Express uncorrectable Error occurred */
Stephen Hemminger793b8832005-09-14 16:06:14 -07002297 u32 pex_err;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002298
Stephen Hemminger7bd656d2006-10-09 14:40:38 -07002299 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002300
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002301 if (net_ratelimit())
Stephen Hemmingerb02a9252007-02-06 10:45:40 -08002302 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2303 pex_err);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002304
2305 /* clear the interrupt */
2306 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
Stephen Hemminger7bd656d2006-10-09 14:40:38 -07002307 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2308 0xffffffffUL);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002309 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2310
Stephen Hemminger7bd656d2006-10-09 14:40:38 -07002311 if (pex_err & PEX_FATAL_ERRORS) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002312 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2313 hwmsk &= ~Y2_IS_PCI_EXP;
2314 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2315 }
2316 }
2317
2318 if (status & Y2_HWE_L1_MASK)
2319 sky2_hw_error(hw, 0, status);
2320 status >>= 8;
2321 if (status & Y2_HWE_L1_MASK)
2322 sky2_hw_error(hw, 1, status);
2323}
2324
2325static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2326{
2327 struct net_device *dev = hw->dev[port];
2328 struct sky2_port *sky2 = netdev_priv(dev);
2329 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2330
2331 if (netif_msg_intr(sky2))
2332 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2333 dev->name, status);
2334
2335 if (status & GM_IS_RX_FF_OR) {
2336 ++sky2->net_stats.rx_fifo_errors;
2337 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2338 }
2339
2340 if (status & GM_IS_TX_FF_UR) {
2341 ++sky2->net_stats.tx_fifo_errors;
2342 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2343 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002344}
2345
Stephen Hemminger40b01722007-04-11 14:47:59 -07002346/* This should never happen it is a bug. */
2347static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2348 u16 q, unsigned ring_size)
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002349{
2350 struct net_device *dev = hw->dev[port];
2351 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger40b01722007-04-11 14:47:59 -07002352 unsigned idx;
2353 const u64 *le = (q == Q_R1 || q == Q_R2)
2354 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002355
Stephen Hemminger40b01722007-04-11 14:47:59 -07002356 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2357 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2358 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2359 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002360
Stephen Hemminger40b01722007-04-11 14:47:59 -07002361 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002362}
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002363
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07002364/* If idle then force a fake soft NAPI poll once a second
2365 * to work around cases where sharing an edge triggered interrupt.
2366 */
Stephen Hemmingereb35cf62006-06-13 17:17:31 +09002367static inline void sky2_idle_start(struct sky2_hw *hw)
2368{
2369 if (idle_timeout > 0)
2370 mod_timer(&hw->idle_timer,
2371 jiffies + msecs_to_jiffies(idle_timeout));
2372}
2373
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07002374static void sky2_idle(unsigned long arg)
2375{
Stephen Hemminger01bd7562006-05-08 15:11:30 -07002376 struct sky2_hw *hw = (struct sky2_hw *) arg;
2377 struct net_device *dev = hw->dev[0];
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07002378
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07002379 if (__netif_rx_schedule_prep(dev))
2380 __netif_rx_schedule(dev);
Stephen Hemminger01bd7562006-05-08 15:11:30 -07002381
2382 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07002383}
2384
Stephen Hemminger40b01722007-04-11 14:47:59 -07002385/* Hardware/software error handling */
2386static void sky2_err_intr(struct sky2_hw *hw, u32 status)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002387{
Stephen Hemminger40b01722007-04-11 14:47:59 -07002388 if (net_ratelimit())
2389 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002390
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002391 if (status & Y2_IS_HW_ERR)
2392 sky2_hw_intr(hw);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002393
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002394 if (status & Y2_IS_IRQ_MAC1)
2395 sky2_mac_intr(hw, 0);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002396
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002397 if (status & Y2_IS_IRQ_MAC2)
2398 sky2_mac_intr(hw, 1);
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002399
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002400 if (status & Y2_IS_CHK_RX1)
Stephen Hemminger40b01722007-04-11 14:47:59 -07002401 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002402
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002403 if (status & Y2_IS_CHK_RX2)
Stephen Hemminger40b01722007-04-11 14:47:59 -07002404 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002405
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002406 if (status & Y2_IS_CHK_TXA1)
Stephen Hemminger40b01722007-04-11 14:47:59 -07002407 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002408
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002409 if (status & Y2_IS_CHK_TXA2)
Stephen Hemminger40b01722007-04-11 14:47:59 -07002410 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2411}
2412
2413static int sky2_poll(struct net_device *dev0, int *budget)
2414{
2415 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2416 int work_limit = min(dev0->quota, *budget);
2417 int work_done = 0;
2418 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2419
2420 if (unlikely(status & Y2_IS_ERROR))
2421 sky2_err_intr(hw, status);
2422
2423 if (status & Y2_IS_IRQ_PHY1)
2424 sky2_phy_intr(hw, 0);
2425
2426 if (status & Y2_IS_IRQ_PHY2)
2427 sky2_phy_intr(hw, 1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002428
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002429 work_done = sky2_status_intr(hw, work_limit);
Stephen Hemmingerfe2a24d2006-08-01 11:55:23 -07002430 if (work_done < work_limit) {
2431 netif_rx_complete(dev0);
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002432
Stephen Hemmingerfe2a24d2006-08-01 11:55:23 -07002433 sky2_read32(hw, B0_Y2_SP_LISR);
2434 return 0;
2435 } else {
2436 *budget -= work_done;
2437 dev0->quota -= work_done;
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002438 return 1;
Stephen Hemmingerfe2a24d2006-08-01 11:55:23 -07002439 }
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002440}
2441
David Howells7d12e782006-10-05 14:55:46 +01002442static irqreturn_t sky2_intr(int irq, void *dev_id)
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002443{
2444 struct sky2_hw *hw = dev_id;
2445 struct net_device *dev0 = hw->dev[0];
2446 u32 status;
2447
2448 /* Reading this mask interrupts as side effect */
2449 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2450 if (status == 0 || status == ~0)
2451 return IRQ_NONE;
2452
2453 prefetch(&hw->st_le[hw->st_idx]);
2454 if (likely(__netif_rx_schedule_prep(dev0)))
2455 __netif_rx_schedule(dev0);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002456
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002457 return IRQ_HANDLED;
2458}
2459
2460#ifdef CONFIG_NET_POLL_CONTROLLER
2461static void sky2_netpoll(struct net_device *dev)
2462{
2463 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger88d11362006-06-16 12:10:46 -07002464 struct net_device *dev0 = sky2->hw->dev[0];
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002465
Stephen Hemminger88d11362006-06-16 12:10:46 -07002466 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2467 __netif_rx_schedule(dev0);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002468}
2469#endif
2470
2471/* Chip internal frequency for clock calculations */
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002472static inline u32 sky2_mhz(const struct sky2_hw *hw)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002473{
Stephen Hemminger793b8832005-09-14 16:06:14 -07002474 switch (hw->chip_id) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002475 case CHIP_ID_YUKON_EC:
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -08002476 case CHIP_ID_YUKON_EC_U:
Stephen Hemminger93745492007-02-06 10:45:43 -08002477 case CHIP_ID_YUKON_EX:
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002478 return 125; /* 125 Mhz */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002479 case CHIP_ID_YUKON_FE:
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002480 return 100; /* 100 Mhz */
Stephen Hemminger793b8832005-09-14 16:06:14 -07002481 default: /* YUKON_XL */
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002482 return 156; /* 156 Mhz */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002483 }
2484}
2485
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002486static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2487{
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002488 return sky2_mhz(hw) * us;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002489}
2490
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002491static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2492{
2493 return clk / sky2_mhz(hw);
2494}
2495
2496
Stephen Hemmingere3173832007-02-06 10:45:39 -08002497static int __devinit sky2_init(struct sky2_hw *hw)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002498{
Stephen Hemmingerb89165f2006-09-06 12:44:53 -07002499 u8 t8;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002500
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002501 sky2_write8(hw, B0_CTST, CS_RST_CLR);
Stephen Hemminger08c06d82006-01-30 11:37:54 -08002502
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002503 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2504 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
Stephen Hemmingerb02a9252007-02-06 10:45:40 -08002505 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2506 hw->chip_id);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002507 return -EOPNOTSUPP;
2508 }
2509
Stephen Hemminger93745492007-02-06 10:45:43 -08002510 if (hw->chip_id == CHIP_ID_YUKON_EX)
2511 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
2512 "Please report success or failure to <netdev@vger.kernel.org>\n");
2513
2514 /* Make sure and enable all clocks */
2515 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
2516 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2517
Stephen Hemminger290d4de2006-03-20 15:48:15 -08002518 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2519
2520 /* This rev is really old, and requires untested workarounds */
2521 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
Stephen Hemmingerb02a9252007-02-06 10:45:40 -08002522 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2523 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2524 hw->chip_id, hw->chip_rev);
Stephen Hemminger290d4de2006-03-20 15:48:15 -08002525 return -EOPNOTSUPP;
2526 }
2527
Stephen Hemmingere3173832007-02-06 10:45:39 -08002528 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2529 hw->ports = 1;
2530 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2531 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2532 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2533 ++hw->ports;
2534 }
2535
2536 return 0;
2537}
2538
2539static void sky2_reset(struct sky2_hw *hw)
2540{
2541 u16 status;
2542 int i;
2543
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002544 /* disable ASF */
2545 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
Stephen Hemminger93745492007-02-06 10:45:43 -08002546 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2547 status = sky2_read16(hw, HCU_CCSR);
2548 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2549 HCU_CCSR_UC_STATE_MSK);
2550 sky2_write16(hw, HCU_CCSR, status);
2551 } else
2552 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002553 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2554 }
2555
2556 /* do a SW reset */
2557 sky2_write8(hw, B0_CTST, CS_RST_SET);
2558 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2559
2560 /* clear PCI errors, if any */
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002561 status = sky2_pci_read16(hw, PCI_STATUS);
Stephen Hemminger2d42d212006-01-30 11:37:55 -08002562
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002563 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002564 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2565
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002566
2567 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2568
2569 /* clear any PEX errors */
Stephen Hemminger7bd656d2006-10-09 14:40:38 -07002570 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2571 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2572
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002573
Stephen Hemmingerae306cc2006-12-20 13:06:36 -08002574 sky2_power_on(hw);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002575
2576 for (i = 0; i < hw->ports; i++) {
2577 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2578 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2579 }
2580
2581 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2582
Stephen Hemminger793b8832005-09-14 16:06:14 -07002583 /* Clear I2C IRQ noise */
2584 sky2_write32(hw, B2_I2C_IRQ, 1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002585
2586 /* turn off hardware timer (unused) */
2587 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2588 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002589
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002590 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2591
Stephen Hemminger69634ee2005-12-09 11:35:06 -08002592 /* Turn off descriptor polling */
2593 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002594
2595 /* Turn off receive timestamp */
2596 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002597 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002598
2599 /* enable the Tx Arbiters */
2600 for (i = 0; i < hw->ports; i++)
2601 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2602
2603 /* Initialize ram interface */
2604 for (i = 0; i < hw->ports; i++) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07002605 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002606
2607 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2608 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2609 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2610 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2611 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2612 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2613 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2614 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2615 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2616 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2617 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2618 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2619 }
2620
Stephen Hemminger7bd656d2006-10-09 14:40:38 -07002621 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002622
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002623 for (i = 0; i < hw->ports; i++)
shemminger@osdl.orgd3bcfbe2006-08-28 10:00:51 -07002624 sky2_gmac_reset(hw, i);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002625
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002626 memset(hw->st_le, 0, STATUS_LE_BYTES);
2627 hw->st_idx = 0;
2628
2629 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2630 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2631
2632 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002633 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002634
2635 /* Set the list last index */
Stephen Hemminger793b8832005-09-14 16:06:14 -07002636 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002637
Stephen Hemminger290d4de2006-03-20 15:48:15 -08002638 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2639 sky2_write8(hw, STAT_FIFO_WM, 16);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002640
Stephen Hemminger290d4de2006-03-20 15:48:15 -08002641 /* set Status-FIFO ISR watermark */
2642 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2643 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2644 else
2645 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002646
Stephen Hemminger290d4de2006-03-20 15:48:15 -08002647 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
Stephen Hemminger77b3d6a2006-03-20 15:48:18 -08002648 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2649 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002650
Stephen Hemminger793b8832005-09-14 16:06:14 -07002651 /* enable status unit */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002652 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2653
2654 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2655 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2656 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
Stephen Hemmingere3173832007-02-06 10:45:39 -08002657}
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002658
Stephen Hemminger81906792007-02-15 16:40:33 -08002659static void sky2_restart(struct work_struct *work)
2660{
2661 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2662 struct net_device *dev;
2663 int i, err;
2664
2665 dev_dbg(&hw->pdev->dev, "restarting\n");
2666
2667 del_timer_sync(&hw->idle_timer);
2668
2669 rtnl_lock();
2670 sky2_write32(hw, B0_IMSK, 0);
2671 sky2_read32(hw, B0_IMSK);
2672
2673 netif_poll_disable(hw->dev[0]);
2674
2675 for (i = 0; i < hw->ports; i++) {
2676 dev = hw->dev[i];
2677 if (netif_running(dev))
2678 sky2_down(dev);
2679 }
2680
2681 sky2_reset(hw);
2682 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2683 netif_poll_enable(hw->dev[0]);
2684
2685 for (i = 0; i < hw->ports; i++) {
2686 dev = hw->dev[i];
2687 if (netif_running(dev)) {
2688 err = sky2_up(dev);
2689 if (err) {
2690 printk(KERN_INFO PFX "%s: could not restart %d\n",
2691 dev->name, err);
2692 dev_close(dev);
2693 }
2694 }
2695 }
2696
2697 sky2_idle_start(hw);
2698
2699 rtnl_unlock();
2700}
2701
Stephen Hemmingere3173832007-02-06 10:45:39 -08002702static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2703{
2704 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2705}
2706
2707static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2708{
2709 const struct sky2_port *sky2 = netdev_priv(dev);
2710
2711 wol->supported = sky2_wol_supported(sky2->hw);
2712 wol->wolopts = sky2->wol;
2713}
2714
2715static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2716{
2717 struct sky2_port *sky2 = netdev_priv(dev);
2718 struct sky2_hw *hw = sky2->hw;
2719
2720 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2721 return -EOPNOTSUPP;
2722
2723 sky2->wol = wol->wolopts;
2724
2725 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2726 sky2_write32(hw, B0_CTST, sky2->wol
2727 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2728
2729 if (!netif_running(dev))
2730 sky2_wol_init(sky2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002731 return 0;
2732}
2733
Stephen Hemminger28bd1812006-01-17 13:43:19 -08002734static u32 sky2_supported_modes(const struct sky2_hw *hw)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002735{
Stephen Hemmingerb89165f2006-09-06 12:44:53 -07002736 if (sky2_is_copper(hw)) {
2737 u32 modes = SUPPORTED_10baseT_Half
2738 | SUPPORTED_10baseT_Full
2739 | SUPPORTED_100baseT_Half
2740 | SUPPORTED_100baseT_Full
2741 | SUPPORTED_Autoneg | SUPPORTED_TP;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002742
2743 if (hw->chip_id != CHIP_ID_YUKON_FE)
2744 modes |= SUPPORTED_1000baseT_Half
Stephen Hemmingerb89165f2006-09-06 12:44:53 -07002745 | SUPPORTED_1000baseT_Full;
2746 return modes;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002747 } else
Stephen Hemmingerb89165f2006-09-06 12:44:53 -07002748 return SUPPORTED_1000baseT_Half
2749 | SUPPORTED_1000baseT_Full
2750 | SUPPORTED_Autoneg
2751 | SUPPORTED_FIBRE;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002752}
2753
Stephen Hemminger793b8832005-09-14 16:06:14 -07002754static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002755{
2756 struct sky2_port *sky2 = netdev_priv(dev);
2757 struct sky2_hw *hw = sky2->hw;
2758
2759 ecmd->transceiver = XCVR_INTERNAL;
2760 ecmd->supported = sky2_supported_modes(hw);
2761 ecmd->phy_address = PHY_ADDR_MARV;
Stephen Hemmingerb89165f2006-09-06 12:44:53 -07002762 if (sky2_is_copper(hw)) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002763 ecmd->supported = SUPPORTED_10baseT_Half
Stephen Hemminger793b8832005-09-14 16:06:14 -07002764 | SUPPORTED_10baseT_Full
2765 | SUPPORTED_100baseT_Half
2766 | SUPPORTED_100baseT_Full
2767 | SUPPORTED_1000baseT_Half
2768 | SUPPORTED_1000baseT_Full
2769 | SUPPORTED_Autoneg | SUPPORTED_TP;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002770 ecmd->port = PORT_TP;
Stephen Hemmingerb89165f2006-09-06 12:44:53 -07002771 ecmd->speed = sky2->speed;
2772 } else {
2773 ecmd->speed = SPEED_1000;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002774 ecmd->port = PORT_FIBRE;
Stephen Hemmingerb89165f2006-09-06 12:44:53 -07002775 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002776
2777 ecmd->advertising = sky2->advertising;
2778 ecmd->autoneg = sky2->autoneg;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002779 ecmd->duplex = sky2->duplex;
2780 return 0;
2781}
2782
2783static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2784{
2785 struct sky2_port *sky2 = netdev_priv(dev);
2786 const struct sky2_hw *hw = sky2->hw;
2787 u32 supported = sky2_supported_modes(hw);
2788
2789 if (ecmd->autoneg == AUTONEG_ENABLE) {
2790 ecmd->advertising = supported;
2791 sky2->duplex = -1;
2792 sky2->speed = -1;
2793 } else {
2794 u32 setting;
2795
Stephen Hemminger793b8832005-09-14 16:06:14 -07002796 switch (ecmd->speed) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002797 case SPEED_1000:
2798 if (ecmd->duplex == DUPLEX_FULL)
2799 setting = SUPPORTED_1000baseT_Full;
2800 else if (ecmd->duplex == DUPLEX_HALF)
2801 setting = SUPPORTED_1000baseT_Half;
2802 else
2803 return -EINVAL;
2804 break;
2805 case SPEED_100:
2806 if (ecmd->duplex == DUPLEX_FULL)
2807 setting = SUPPORTED_100baseT_Full;
2808 else if (ecmd->duplex == DUPLEX_HALF)
2809 setting = SUPPORTED_100baseT_Half;
2810 else
2811 return -EINVAL;
2812 break;
2813
2814 case SPEED_10:
2815 if (ecmd->duplex == DUPLEX_FULL)
2816 setting = SUPPORTED_10baseT_Full;
2817 else if (ecmd->duplex == DUPLEX_HALF)
2818 setting = SUPPORTED_10baseT_Half;
2819 else
2820 return -EINVAL;
2821 break;
2822 default:
2823 return -EINVAL;
2824 }
2825
2826 if ((setting & supported) == 0)
2827 return -EINVAL;
2828
2829 sky2->speed = ecmd->speed;
2830 sky2->duplex = ecmd->duplex;
2831 }
2832
2833 sky2->autoneg = ecmd->autoneg;
2834 sky2->advertising = ecmd->advertising;
2835
Stephen Hemminger1b537562005-12-20 15:08:07 -08002836 if (netif_running(dev))
2837 sky2_phy_reinit(sky2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002838
2839 return 0;
2840}
2841
2842static void sky2_get_drvinfo(struct net_device *dev,
2843 struct ethtool_drvinfo *info)
2844{
2845 struct sky2_port *sky2 = netdev_priv(dev);
2846
2847 strcpy(info->driver, DRV_NAME);
2848 strcpy(info->version, DRV_VERSION);
2849 strcpy(info->fw_version, "N/A");
2850 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2851}
2852
2853static const struct sky2_stat {
Stephen Hemminger793b8832005-09-14 16:06:14 -07002854 char name[ETH_GSTRING_LEN];
2855 u16 offset;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002856} sky2_stats[] = {
2857 { "tx_bytes", GM_TXO_OK_HI },
2858 { "rx_bytes", GM_RXO_OK_HI },
2859 { "tx_broadcast", GM_TXF_BC_OK },
2860 { "rx_broadcast", GM_RXF_BC_OK },
2861 { "tx_multicast", GM_TXF_MC_OK },
2862 { "rx_multicast", GM_RXF_MC_OK },
2863 { "tx_unicast", GM_TXF_UC_OK },
2864 { "rx_unicast", GM_RXF_UC_OK },
2865 { "tx_mac_pause", GM_TXF_MPAUSE },
2866 { "rx_mac_pause", GM_RXF_MPAUSE },
Stephen Hemmingereadfa7dd2006-03-22 10:38:45 -08002867 { "collisions", GM_TXF_COL },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002868 { "late_collision",GM_TXF_LAT_COL },
2869 { "aborted", GM_TXF_ABO_COL },
Stephen Hemmingereadfa7dd2006-03-22 10:38:45 -08002870 { "single_collisions", GM_TXF_SNG_COL },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002871 { "multi_collisions", GM_TXF_MUL_COL },
Stephen Hemmingereadfa7dd2006-03-22 10:38:45 -08002872
Stephen Hemmingerd2604542006-03-23 08:51:36 -08002873 { "rx_short", GM_RXF_SHT },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002874 { "rx_runt", GM_RXE_FRAG },
Stephen Hemmingereadfa7dd2006-03-22 10:38:45 -08002875 { "rx_64_byte_packets", GM_RXF_64B },
2876 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2877 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2878 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2879 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2880 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2881 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002882 { "rx_too_long", GM_RXF_LNG_ERR },
Stephen Hemmingereadfa7dd2006-03-22 10:38:45 -08002883 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2884 { "rx_jabber", GM_RXF_JAB_PKT },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002885 { "rx_fcs_error", GM_RXF_FCS_ERR },
Stephen Hemmingereadfa7dd2006-03-22 10:38:45 -08002886
2887 { "tx_64_byte_packets", GM_TXF_64B },
2888 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2889 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2890 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2891 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2892 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2893 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2894 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002895};
2896
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002897static u32 sky2_get_rx_csum(struct net_device *dev)
2898{
2899 struct sky2_port *sky2 = netdev_priv(dev);
2900
2901 return sky2->rx_csum;
2902}
2903
2904static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2905{
2906 struct sky2_port *sky2 = netdev_priv(dev);
2907
2908 sky2->rx_csum = data;
Stephen Hemminger793b8832005-09-14 16:06:14 -07002909
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002910 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2911 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2912
2913 return 0;
2914}
2915
2916static u32 sky2_get_msglevel(struct net_device *netdev)
2917{
2918 struct sky2_port *sky2 = netdev_priv(netdev);
2919 return sky2->msg_enable;
2920}
2921
Stephen Hemminger9a7ae0a2005-09-27 15:28:42 -07002922static int sky2_nway_reset(struct net_device *dev)
2923{
2924 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger9a7ae0a2005-09-27 15:28:42 -07002925
Stephen Hemminger16ad91e2006-10-17 10:24:13 -07002926 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
Stephen Hemminger9a7ae0a2005-09-27 15:28:42 -07002927 return -EINVAL;
2928
Stephen Hemminger1b537562005-12-20 15:08:07 -08002929 sky2_phy_reinit(sky2);
Stephen Hemminger9a7ae0a2005-09-27 15:28:42 -07002930
2931 return 0;
2932}
2933
Stephen Hemminger793b8832005-09-14 16:06:14 -07002934static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002935{
2936 struct sky2_hw *hw = sky2->hw;
2937 unsigned port = sky2->port;
2938 int i;
2939
2940 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
Stephen Hemminger793b8832005-09-14 16:06:14 -07002941 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002942 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
Stephen Hemminger793b8832005-09-14 16:06:14 -07002943 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002944
Stephen Hemminger793b8832005-09-14 16:06:14 -07002945 for (i = 2; i < count; i++)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002946 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2947}
2948
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002949static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2950{
2951 struct sky2_port *sky2 = netdev_priv(netdev);
2952 sky2->msg_enable = value;
2953}
2954
2955static int sky2_get_stats_count(struct net_device *dev)
2956{
2957 return ARRAY_SIZE(sky2_stats);
2958}
2959
2960static void sky2_get_ethtool_stats(struct net_device *dev,
Stephen Hemminger793b8832005-09-14 16:06:14 -07002961 struct ethtool_stats *stats, u64 * data)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002962{
2963 struct sky2_port *sky2 = netdev_priv(dev);
2964
Stephen Hemminger793b8832005-09-14 16:06:14 -07002965 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002966}
2967
Stephen Hemminger793b8832005-09-14 16:06:14 -07002968static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002969{
2970 int i;
2971
2972 switch (stringset) {
2973 case ETH_SS_STATS:
2974 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2975 memcpy(data + i * ETH_GSTRING_LEN,
2976 sky2_stats[i].name, ETH_GSTRING_LEN);
2977 break;
2978 }
2979}
2980
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002981static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2982{
2983 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002984 return &sky2->net_stats;
2985}
2986
2987static int sky2_set_mac_address(struct net_device *dev, void *p)
2988{
2989 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemmingera8ab1ec2006-01-30 11:37:57 -08002990 struct sky2_hw *hw = sky2->hw;
2991 unsigned port = sky2->port;
2992 const struct sockaddr *addr = p;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002993
2994 if (!is_valid_ether_addr(addr->sa_data))
2995 return -EADDRNOTAVAIL;
2996
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002997 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
Stephen Hemmingera8ab1ec2006-01-30 11:37:57 -08002998 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002999 dev->dev_addr, ETH_ALEN);
Stephen Hemmingera8ab1ec2006-01-30 11:37:57 -08003000 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003001 dev->dev_addr, ETH_ALEN);
Stephen Hemminger1b537562005-12-20 15:08:07 -08003002
Stephen Hemmingera8ab1ec2006-01-30 11:37:57 -08003003 /* virtual address for data */
3004 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3005
3006 /* physical address: used for pause frames */
3007 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
Stephen Hemminger1b537562005-12-20 15:08:07 -08003008
3009 return 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003010}
3011
Stephen Hemmingera052b522006-10-17 10:24:23 -07003012static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3013{
3014 u32 bit;
3015
3016 bit = ether_crc(ETH_ALEN, addr) & 63;
3017 filter[bit >> 3] |= 1 << (bit & 7);
3018}
3019
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003020static void sky2_set_multicast(struct net_device *dev)
3021{
3022 struct sky2_port *sky2 = netdev_priv(dev);
3023 struct sky2_hw *hw = sky2->hw;
3024 unsigned port = sky2->port;
3025 struct dev_mc_list *list = dev->mc_list;
3026 u16 reg;
3027 u8 filter[8];
Stephen Hemmingera052b522006-10-17 10:24:23 -07003028 int rx_pause;
3029 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003030
Stephen Hemmingera052b522006-10-17 10:24:23 -07003031 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003032 memset(filter, 0, sizeof(filter));
3033
3034 reg = gma_read16(hw, port, GM_RX_CTRL);
3035 reg |= GM_RXCR_UCF_ENA;
3036
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07003037 if (dev->flags & IFF_PROMISC) /* promiscuous */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003038 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
Stephen Hemmingera052b522006-10-17 10:24:23 -07003039 else if (dev->flags & IFF_ALLMULTI)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003040 memset(filter, 0xff, sizeof(filter));
Stephen Hemmingera052b522006-10-17 10:24:23 -07003041 else if (dev->mc_count == 0 && !rx_pause)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003042 reg &= ~GM_RXCR_MCF_ENA;
3043 else {
3044 int i;
3045 reg |= GM_RXCR_MCF_ENA;
3046
Stephen Hemmingera052b522006-10-17 10:24:23 -07003047 if (rx_pause)
3048 sky2_add_filter(filter, pause_mc_addr);
3049
3050 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3051 sky2_add_filter(filter, list->dmi_addr);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003052 }
3053
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003054 gma_write16(hw, port, GM_MC_ADDR_H1,
Stephen Hemminger793b8832005-09-14 16:06:14 -07003055 (u16) filter[0] | ((u16) filter[1] << 8));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003056 gma_write16(hw, port, GM_MC_ADDR_H2,
Stephen Hemminger793b8832005-09-14 16:06:14 -07003057 (u16) filter[2] | ((u16) filter[3] << 8));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003058 gma_write16(hw, port, GM_MC_ADDR_H3,
Stephen Hemminger793b8832005-09-14 16:06:14 -07003059 (u16) filter[4] | ((u16) filter[5] << 8));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003060 gma_write16(hw, port, GM_MC_ADDR_H4,
Stephen Hemminger793b8832005-09-14 16:06:14 -07003061 (u16) filter[6] | ((u16) filter[7] << 8));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003062
3063 gma_write16(hw, port, GM_RX_CTRL, reg);
3064}
3065
3066/* Can have one global because blinking is controlled by
3067 * ethtool and that is always under RTNL mutex
3068 */
Stephen Hemminger91c86df2005-12-09 11:34:57 -08003069static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003070{
Stephen Hemminger793b8832005-09-14 16:06:14 -07003071 u16 pg;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003072
Stephen Hemminger793b8832005-09-14 16:06:14 -07003073 switch (hw->chip_id) {
3074 case CHIP_ID_YUKON_XL:
3075 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3076 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3077 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3078 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3079 PHY_M_LEDC_INIT_CTRL(7) |
3080 PHY_M_LEDC_STA1_CTRL(7) |
3081 PHY_M_LEDC_STA0_CTRL(7))
3082 : 0);
3083
3084 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3085 break;
3086
3087 default:
3088 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
Stephen Hemminger0efdf262006-12-05 12:03:41 -08003089 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3090 on ? PHY_M_LED_ALL : 0);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003091 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003092}
3093
3094/* blink LED's for finding board */
3095static int sky2_phys_id(struct net_device *dev, u32 data)
3096{
3097 struct sky2_port *sky2 = netdev_priv(dev);
3098 struct sky2_hw *hw = sky2->hw;
3099 unsigned port = sky2->port;
Stephen Hemminger793b8832005-09-14 16:06:14 -07003100 u16 ledctrl, ledover = 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003101 long ms;
Stephen Hemminger91c86df2005-12-09 11:34:57 -08003102 int interrupted;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003103 int onoff = 1;
3104
Stephen Hemminger793b8832005-09-14 16:06:14 -07003105 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003106 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3107 else
3108 ms = data * 1000;
3109
3110 /* save initial values */
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08003111 spin_lock_bh(&sky2->phy_lock);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003112 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3113 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3114 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3115 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3116 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3117 } else {
3118 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3119 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3120 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003121
Stephen Hemminger91c86df2005-12-09 11:34:57 -08003122 interrupted = 0;
3123 while (!interrupted && ms > 0) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003124 sky2_led(hw, port, onoff);
3125 onoff = !onoff;
3126
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08003127 spin_unlock_bh(&sky2->phy_lock);
Stephen Hemminger91c86df2005-12-09 11:34:57 -08003128 interrupted = msleep_interruptible(250);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08003129 spin_lock_bh(&sky2->phy_lock);
Stephen Hemminger91c86df2005-12-09 11:34:57 -08003130
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003131 ms -= 250;
3132 }
3133
3134 /* resume regularly scheduled programming */
Stephen Hemminger793b8832005-09-14 16:06:14 -07003135 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3136 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3137 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3138 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3139 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3140 } else {
3141 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3142 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3143 }
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08003144 spin_unlock_bh(&sky2->phy_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003145
3146 return 0;
3147}
3148
3149static void sky2_get_pauseparam(struct net_device *dev,
3150 struct ethtool_pauseparam *ecmd)
3151{
3152 struct sky2_port *sky2 = netdev_priv(dev);
3153
Stephen Hemminger16ad91e2006-10-17 10:24:13 -07003154 switch (sky2->flow_mode) {
3155 case FC_NONE:
3156 ecmd->tx_pause = ecmd->rx_pause = 0;
3157 break;
3158 case FC_TX:
3159 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3160 break;
3161 case FC_RX:
3162 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3163 break;
3164 case FC_BOTH:
3165 ecmd->tx_pause = ecmd->rx_pause = 1;
3166 }
3167
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003168 ecmd->autoneg = sky2->autoneg;
3169}
3170
3171static int sky2_set_pauseparam(struct net_device *dev,
3172 struct ethtool_pauseparam *ecmd)
3173{
3174 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003175
3176 sky2->autoneg = ecmd->autoneg;
Stephen Hemminger16ad91e2006-10-17 10:24:13 -07003177 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003178
Stephen Hemminger16ad91e2006-10-17 10:24:13 -07003179 if (netif_running(dev))
3180 sky2_phy_reinit(sky2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003181
Stephen Hemminger2eaba1a2006-09-06 12:44:47 -07003182 return 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003183}
3184
Stephen Hemmingerfb173582005-12-09 11:34:56 -08003185static int sky2_get_coalesce(struct net_device *dev,
3186 struct ethtool_coalesce *ecmd)
3187{
3188 struct sky2_port *sky2 = netdev_priv(dev);
3189 struct sky2_hw *hw = sky2->hw;
3190
3191 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3192 ecmd->tx_coalesce_usecs = 0;
3193 else {
3194 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3195 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3196 }
3197 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3198
3199 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3200 ecmd->rx_coalesce_usecs = 0;
3201 else {
3202 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3203 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3204 }
3205 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3206
3207 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3208 ecmd->rx_coalesce_usecs_irq = 0;
3209 else {
3210 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3211 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3212 }
3213
3214 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3215
3216 return 0;
3217}
3218
3219/* Note: this affect both ports */
3220static int sky2_set_coalesce(struct net_device *dev,
3221 struct ethtool_coalesce *ecmd)
3222{
3223 struct sky2_port *sky2 = netdev_priv(dev);
3224 struct sky2_hw *hw = sky2->hw;
Stephen Hemminger77b3d6a2006-03-20 15:48:18 -08003225 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
Stephen Hemmingerfb173582005-12-09 11:34:56 -08003226
Stephen Hemminger77b3d6a2006-03-20 15:48:18 -08003227 if (ecmd->tx_coalesce_usecs > tmax ||
3228 ecmd->rx_coalesce_usecs > tmax ||
3229 ecmd->rx_coalesce_usecs_irq > tmax)
Stephen Hemmingerfb173582005-12-09 11:34:56 -08003230 return -EINVAL;
3231
Stephen Hemmingerff81fbb2006-02-22 11:44:59 -08003232 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
Stephen Hemmingerfb173582005-12-09 11:34:56 -08003233 return -EINVAL;
Stephen Hemmingerff81fbb2006-02-22 11:44:59 -08003234 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
Stephen Hemmingerfb173582005-12-09 11:34:56 -08003235 return -EINVAL;
Stephen Hemmingerff81fbb2006-02-22 11:44:59 -08003236 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
Stephen Hemmingerfb173582005-12-09 11:34:56 -08003237 return -EINVAL;
3238
3239 if (ecmd->tx_coalesce_usecs == 0)
3240 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3241 else {
3242 sky2_write32(hw, STAT_TX_TIMER_INI,
3243 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3244 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3245 }
3246 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3247
3248 if (ecmd->rx_coalesce_usecs == 0)
3249 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3250 else {
3251 sky2_write32(hw, STAT_LEV_TIMER_INI,
3252 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3253 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3254 }
3255 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3256
3257 if (ecmd->rx_coalesce_usecs_irq == 0)
3258 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3259 else {
Stephen Hemmingerd28d4872006-01-30 11:37:56 -08003260 sky2_write32(hw, STAT_ISR_TIMER_INI,
Stephen Hemmingerfb173582005-12-09 11:34:56 -08003261 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3262 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3263 }
3264 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3265 return 0;
3266}
3267
Stephen Hemminger793b8832005-09-14 16:06:14 -07003268static void sky2_get_ringparam(struct net_device *dev,
3269 struct ethtool_ringparam *ering)
3270{
3271 struct sky2_port *sky2 = netdev_priv(dev);
3272
3273 ering->rx_max_pending = RX_MAX_PENDING;
3274 ering->rx_mini_max_pending = 0;
3275 ering->rx_jumbo_max_pending = 0;
3276 ering->tx_max_pending = TX_RING_SIZE - 1;
3277
3278 ering->rx_pending = sky2->rx_pending;
3279 ering->rx_mini_pending = 0;
3280 ering->rx_jumbo_pending = 0;
3281 ering->tx_pending = sky2->tx_pending;
3282}
3283
3284static int sky2_set_ringparam(struct net_device *dev,
3285 struct ethtool_ringparam *ering)
3286{
3287 struct sky2_port *sky2 = netdev_priv(dev);
3288 int err = 0;
3289
3290 if (ering->rx_pending > RX_MAX_PENDING ||
3291 ering->rx_pending < 8 ||
3292 ering->tx_pending < MAX_SKB_TX_LE ||
3293 ering->tx_pending > TX_RING_SIZE - 1)
3294 return -EINVAL;
3295
3296 if (netif_running(dev))
3297 sky2_down(dev);
3298
3299 sky2->rx_pending = ering->rx_pending;
3300 sky2->tx_pending = ering->tx_pending;
3301
Stephen Hemminger1b537562005-12-20 15:08:07 -08003302 if (netif_running(dev)) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07003303 err = sky2_up(dev);
Stephen Hemminger1b537562005-12-20 15:08:07 -08003304 if (err)
3305 dev_close(dev);
Stephen Hemminger6ed995b2005-12-20 15:08:08 -08003306 else
3307 sky2_set_multicast(dev);
Stephen Hemminger1b537562005-12-20 15:08:07 -08003308 }
Stephen Hemminger793b8832005-09-14 16:06:14 -07003309
3310 return err;
3311}
3312
Stephen Hemminger793b8832005-09-14 16:06:14 -07003313static int sky2_get_regs_len(struct net_device *dev)
3314{
Stephen Hemminger6e4cbb32005-09-19 15:47:57 -07003315 return 0x4000;
Stephen Hemminger793b8832005-09-14 16:06:14 -07003316}
3317
3318/*
3319 * Returns copy of control register region
Stephen Hemminger6e4cbb32005-09-19 15:47:57 -07003320 * Note: access to the RAM address register set will cause timeouts.
Stephen Hemminger793b8832005-09-14 16:06:14 -07003321 */
3322static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3323 void *p)
3324{
3325 const struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003326 const void __iomem *io = sky2->hw->regs;
Stephen Hemminger793b8832005-09-14 16:06:14 -07003327
Stephen Hemminger6e4cbb32005-09-19 15:47:57 -07003328 BUG_ON(regs->len < B3_RI_WTO_R1);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003329 regs->version = 1;
Stephen Hemminger6e4cbb32005-09-19 15:47:57 -07003330 memset(p, 0, regs->len);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003331
Stephen Hemminger6e4cbb32005-09-19 15:47:57 -07003332 memcpy_fromio(p, io, B3_RAM_ADDR);
3333
3334 memcpy_fromio(p + B3_RI_WTO_R1,
3335 io + B3_RI_WTO_R1,
3336 regs->len - B3_RI_WTO_R1);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003337}
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003338
Jeff Garzik7282d492006-09-13 14:30:00 -04003339static const struct ethtool_ops sky2_ethtool_ops = {
Stephen Hemminger793b8832005-09-14 16:06:14 -07003340 .get_settings = sky2_get_settings,
3341 .set_settings = sky2_set_settings,
Stephen Hemmingere3173832007-02-06 10:45:39 -08003342 .get_drvinfo = sky2_get_drvinfo,
3343 .get_wol = sky2_get_wol,
3344 .set_wol = sky2_set_wol,
Stephen Hemminger793b8832005-09-14 16:06:14 -07003345 .get_msglevel = sky2_get_msglevel,
3346 .set_msglevel = sky2_set_msglevel,
Stephen Hemminger9a7ae0a2005-09-27 15:28:42 -07003347 .nway_reset = sky2_nway_reset,
Stephen Hemminger793b8832005-09-14 16:06:14 -07003348 .get_regs_len = sky2_get_regs_len,
3349 .get_regs = sky2_get_regs,
3350 .get_link = ethtool_op_get_link,
3351 .get_sg = ethtool_op_get_sg,
3352 .set_sg = ethtool_op_set_sg,
3353 .get_tx_csum = ethtool_op_get_tx_csum,
3354 .set_tx_csum = ethtool_op_set_tx_csum,
3355 .get_tso = ethtool_op_get_tso,
3356 .set_tso = ethtool_op_set_tso,
3357 .get_rx_csum = sky2_get_rx_csum,
3358 .set_rx_csum = sky2_set_rx_csum,
3359 .get_strings = sky2_get_strings,
Stephen Hemmingerfb173582005-12-09 11:34:56 -08003360 .get_coalesce = sky2_get_coalesce,
3361 .set_coalesce = sky2_set_coalesce,
Stephen Hemminger793b8832005-09-14 16:06:14 -07003362 .get_ringparam = sky2_get_ringparam,
3363 .set_ringparam = sky2_set_ringparam,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003364 .get_pauseparam = sky2_get_pauseparam,
3365 .set_pauseparam = sky2_set_pauseparam,
Stephen Hemminger793b8832005-09-14 16:06:14 -07003366 .phys_id = sky2_phys_id,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003367 .get_stats_count = sky2_get_stats_count,
3368 .get_ethtool_stats = sky2_get_ethtool_stats,
Stephen Hemminger2995bfb2005-09-28 10:01:03 -07003369 .get_perm_addr = ethtool_op_get_perm_addr,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003370};
3371
3372/* Initialize network device */
3373static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
Stephen Hemmingere3173832007-02-06 10:45:39 -08003374 unsigned port,
3375 int highmem, int wol)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003376{
3377 struct sky2_port *sky2;
3378 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3379
3380 if (!dev) {
Stephen Hemmingerb02a9252007-02-06 10:45:40 -08003381 dev_err(&hw->pdev->dev, "etherdev alloc failed");
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003382 return NULL;
3383 }
3384
3385 SET_MODULE_OWNER(dev);
3386 SET_NETDEV_DEV(dev, &hw->pdev->dev);
shemminger@osdl.orgef743d32005-11-30 11:45:12 -08003387 dev->irq = hw->pdev->irq;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003388 dev->open = sky2_up;
3389 dev->stop = sky2_down;
shemminger@osdl.orgef743d32005-11-30 11:45:12 -08003390 dev->do_ioctl = sky2_ioctl;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003391 dev->hard_start_xmit = sky2_xmit_frame;
3392 dev->get_stats = sky2_get_stats;
3393 dev->set_multicast_list = sky2_set_multicast;
3394 dev->set_mac_address = sky2_set_mac_address;
3395 dev->change_mtu = sky2_change_mtu;
3396 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3397 dev->tx_timeout = sky2_tx_timeout;
3398 dev->watchdog_timeo = TX_WATCHDOG;
3399 if (port == 0)
3400 dev->poll = sky2_poll;
3401 dev->weight = NAPI_WEIGHT;
3402#ifdef CONFIG_NET_POLL_CONTROLLER
Stephen Hemminger0ca43232006-10-18 13:39:28 -07003403 /* Network console (only works on port 0)
3404 * because netpoll makes assumptions about NAPI
3405 */
3406 if (port == 0)
3407 dev->poll_controller = sky2_netpoll;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003408#endif
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003409
3410 sky2 = netdev_priv(dev);
3411 sky2->netdev = dev;
3412 sky2->hw = hw;
3413 sky2->msg_enable = netif_msg_init(debug, default_msg);
3414
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003415 /* Auto speed and flow control */
3416 sky2->autoneg = AUTONEG_ENABLE;
Stephen Hemminger16ad91e2006-10-17 10:24:13 -07003417 sky2->flow_mode = FC_BOTH;
3418
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003419 sky2->duplex = -1;
3420 sky2->speed = -1;
3421 sky2->advertising = sky2_supported_modes(hw);
Stephen Hemmingeree7abb02006-05-18 11:16:21 -07003422 sky2->rx_csum = 1;
Stephen Hemmingere3173832007-02-06 10:45:39 -08003423 sky2->wol = wol;
Stephen Hemminger75d070c2005-12-09 11:35:11 -08003424
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08003425 spin_lock_init(&sky2->phy_lock);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003426 sky2->tx_pending = TX_DEF_PENDING;
Stephen Hemminger290d4de2006-03-20 15:48:15 -08003427 sky2->rx_pending = RX_DEF_PENDING;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003428
3429 hw->dev[port] = dev;
3430
3431 sky2->port = port;
3432
Stephen Hemminger4a50a872007-02-06 10:45:41 -08003433 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003434 if (highmem)
3435 dev->features |= NETIF_F_HIGHDMA;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003436
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07003437#ifdef SKY2_VLAN_TAG_USED
3438 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3439 dev->vlan_rx_register = sky2_vlan_rx_register;
3440 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3441#endif
3442
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003443 /* read the mac address */
Stephen Hemminger793b8832005-09-14 16:06:14 -07003444 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
Stephen Hemminger2995bfb2005-09-28 10:01:03 -07003445 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003446
3447 /* device is off until link detection */
3448 netif_carrier_off(dev);
3449 netif_stop_queue(dev);
3450
3451 return dev;
3452}
3453
Stephen Hemminger28bd1812006-01-17 13:43:19 -08003454static void __devinit sky2_show_addr(struct net_device *dev)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003455{
3456 const struct sky2_port *sky2 = netdev_priv(dev);
3457
3458 if (netif_msg_probe(sky2))
3459 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3460 dev->name,
3461 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3462 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3463}
3464
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003465/* Handle software interrupt used during MSI test */
David Howells7d12e782006-10-05 14:55:46 +01003466static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003467{
3468 struct sky2_hw *hw = dev_id;
3469 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3470
3471 if (status == 0)
3472 return IRQ_NONE;
3473
3474 if (status & Y2_IS_IRQ_SW) {
Stephen Hemmingerb0a20de2006-12-01 14:29:37 -08003475 hw->msi = 1;
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003476 wake_up(&hw->msi_wait);
3477 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3478 }
3479 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3480
3481 return IRQ_HANDLED;
3482}
3483
3484/* Test interrupt path by forcing a a software IRQ */
3485static int __devinit sky2_test_msi(struct sky2_hw *hw)
3486{
3487 struct pci_dev *pdev = hw->pdev;
3488 int err;
3489
shemminger@osdl.orgbb507fe2006-08-28 10:00:48 -07003490 init_waitqueue_head (&hw->msi_wait);
3491
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003492 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3493
Stephen Hemmingerb0a20de2006-12-01 14:29:37 -08003494 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003495 if (err) {
Stephen Hemmingerb02a9252007-02-06 10:45:40 -08003496 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003497 return err;
3498 }
3499
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003500 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
shemminger@osdl.orgbb507fe2006-08-28 10:00:48 -07003501 sky2_read8(hw, B0_CTST);
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003502
Stephen Hemmingerb0a20de2006-12-01 14:29:37 -08003503 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003504
Stephen Hemmingerb0a20de2006-12-01 14:29:37 -08003505 if (!hw->msi) {
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003506 /* MSI test failed, go back to INTx mode */
Stephen Hemmingerb02a9252007-02-06 10:45:40 -08003507 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3508 "switching to INTx mode.\n");
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003509
3510 err = -EOPNOTSUPP;
3511 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3512 }
3513
3514 sky2_write32(hw, B0_IMSK, 0);
Stephen Hemminger2bffc232006-10-17 10:17:18 -07003515 sky2_read32(hw, B0_IMSK);
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003516
3517 free_irq(pdev->irq, hw);
3518
3519 return err;
3520}
3521
Stephen Hemmingere3173832007-02-06 10:45:39 -08003522static int __devinit pci_wake_enabled(struct pci_dev *dev)
3523{
3524 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3525 u16 value;
3526
3527 if (!pm)
3528 return 0;
3529 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3530 return 0;
3531 return value & PCI_PM_CTRL_PME_ENABLE;
3532}
3533
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003534static int __devinit sky2_probe(struct pci_dev *pdev,
3535 const struct pci_device_id *ent)
3536{
shemminger@linux-foundation.org7f60c642007-01-26 11:38:36 -08003537 struct net_device *dev;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003538 struct sky2_hw *hw;
Stephen Hemmingere3173832007-02-06 10:45:39 -08003539 int err, using_dac = 0, wol_default;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003540
Stephen Hemminger793b8832005-09-14 16:06:14 -07003541 err = pci_enable_device(pdev);
3542 if (err) {
Stephen Hemmingerb02a9252007-02-06 10:45:40 -08003543 dev_err(&pdev->dev, "cannot enable PCI device\n");
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003544 goto err_out;
3545 }
3546
Stephen Hemminger793b8832005-09-14 16:06:14 -07003547 err = pci_request_regions(pdev, DRV_NAME);
3548 if (err) {
Stephen Hemmingerb02a9252007-02-06 10:45:40 -08003549 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
Stephen Hemminger793b8832005-09-14 16:06:14 -07003550 goto err_out;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003551 }
3552
3553 pci_set_master(pdev);
3554
Stephen Hemmingerd1f3d4d2006-01-17 13:43:11 -08003555 if (sizeof(dma_addr_t) > sizeof(u32) &&
3556 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3557 using_dac = 1;
3558 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3559 if (err < 0) {
Stephen Hemmingerb02a9252007-02-06 10:45:40 -08003560 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3561 "for consistent allocations\n");
Stephen Hemmingerd1f3d4d2006-01-17 13:43:11 -08003562 goto err_out_free_regions;
3563 }
Stephen Hemmingerd1f3d4d2006-01-17 13:43:11 -08003564 } else {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003565 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3566 if (err) {
Stephen Hemmingerb02a9252007-02-06 10:45:40 -08003567 dev_err(&pdev->dev, "no usable DMA configuration\n");
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003568 goto err_out_free_regions;
3569 }
3570 }
Stephen Hemmingerd1f3d4d2006-01-17 13:43:11 -08003571
Stephen Hemmingere3173832007-02-06 10:45:39 -08003572 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3573
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003574 err = -ENOMEM;
Stephen Hemminger6aad85d2006-01-17 13:43:18 -08003575 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003576 if (!hw) {
Stephen Hemmingerb02a9252007-02-06 10:45:40 -08003577 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003578 goto err_out_free_regions;
3579 }
3580
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003581 hw->pdev = pdev;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003582
3583 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3584 if (!hw->regs) {
Stephen Hemmingerb02a9252007-02-06 10:45:40 -08003585 dev_err(&pdev->dev, "cannot map device registers\n");
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003586 goto err_out_free_hw;
3587 }
3588
Stephen Hemminger56a645c2006-02-22 11:45:02 -08003589#ifdef __BIG_ENDIAN
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07003590 /* The sk98lin vendor driver uses hardware byte swapping but
3591 * this driver uses software swapping.
3592 */
Stephen Hemminger56a645c2006-02-22 11:45:02 -08003593 {
3594 u32 reg;
Stephen Hemminger56a645c2006-02-22 11:45:02 -08003595 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
Stephen Hemmingerf65b1382006-09-06 12:45:02 -07003596 reg &= ~PCI_REV_DESC;
Stephen Hemminger56a645c2006-02-22 11:45:02 -08003597 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3598 }
3599#endif
3600
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003601 /* ring for status responses */
3602 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3603 &hw->st_dma);
3604 if (!hw->st_le)
3605 goto err_out_iounmap;
3606
Stephen Hemmingere3173832007-02-06 10:45:39 -08003607 err = sky2_init(hw);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003608 if (err)
Stephen Hemminger793b8832005-09-14 16:06:14 -07003609 goto err_out_iounmap;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003610
Stephen Hemmingerb02a9252007-02-06 10:45:40 -08003611 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
Greg Kroah-Hartman7c7459d2006-06-12 15:13:08 -07003612 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3613 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
Stephen Hemminger793b8832005-09-14 16:06:14 -07003614 hw->chip_id, hw->chip_rev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003615
Stephen Hemmingere3173832007-02-06 10:45:39 -08003616 sky2_reset(hw);
3617
3618 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
shemminger@linux-foundation.org7f60c642007-01-26 11:38:36 -08003619 if (!dev) {
3620 err = -ENOMEM;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003621 goto err_out_free_pci;
shemminger@linux-foundation.org7f60c642007-01-26 11:38:36 -08003622 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003623
Stephen Hemminger9fa1b1f2006-09-26 11:57:40 -07003624 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3625 err = sky2_test_msi(hw);
3626 if (err == -EOPNOTSUPP)
3627 pci_disable_msi(pdev);
3628 else if (err)
3629 goto err_out_free_netdev;
3630 }
3631
Stephen Hemminger793b8832005-09-14 16:06:14 -07003632 err = register_netdev(dev);
3633 if (err) {
Stephen Hemmingerb02a9252007-02-06 10:45:40 -08003634 dev_err(&pdev->dev, "cannot register net device\n");
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003635 goto err_out_free_netdev;
3636 }
3637
Stephen Hemmingerb0a20de2006-12-01 14:29:37 -08003638 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3639 dev->name, hw);
Stephen Hemminger9fa1b1f2006-09-26 11:57:40 -07003640 if (err) {
Stephen Hemmingerb02a9252007-02-06 10:45:40 -08003641 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
Stephen Hemminger9fa1b1f2006-09-26 11:57:40 -07003642 goto err_out_unregister;
3643 }
3644 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3645
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003646 sky2_show_addr(dev);
3647
shemminger@linux-foundation.org7f60c642007-01-26 11:38:36 -08003648 if (hw->ports > 1) {
3649 struct net_device *dev1;
3650
Stephen Hemmingere3173832007-02-06 10:45:39 -08003651 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
Stephen Hemmingerb02a9252007-02-06 10:45:40 -08003652 if (!dev1)
3653 dev_warn(&pdev->dev, "allocation for second device failed\n");
3654 else if ((err = register_netdev(dev1))) {
3655 dev_warn(&pdev->dev,
3656 "register of second port failed (%d)\n", err);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003657 hw->dev[1] = NULL;
3658 free_netdev(dev1);
Stephen Hemmingerb02a9252007-02-06 10:45:40 -08003659 } else
3660 sky2_show_addr(dev1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003661 }
3662
Stephen Hemminger01bd7562006-05-08 15:11:30 -07003663 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
Stephen Hemminger81906792007-02-15 16:40:33 -08003664 INIT_WORK(&hw->restart_work, sky2_restart);
3665
Stephen Hemmingereb35cf62006-06-13 17:17:31 +09003666 sky2_idle_start(hw);
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07003667
Stephen Hemminger793b8832005-09-14 16:06:14 -07003668 pci_set_drvdata(pdev, hw);
3669
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003670 return 0;
3671
Stephen Hemminger793b8832005-09-14 16:06:14 -07003672err_out_unregister:
Stephen Hemmingerb0a20de2006-12-01 14:29:37 -08003673 if (hw->msi)
3674 pci_disable_msi(pdev);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003675 unregister_netdev(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003676err_out_free_netdev:
3677 free_netdev(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003678err_out_free_pci:
Stephen Hemminger793b8832005-09-14 16:06:14 -07003679 sky2_write8(hw, B0_CTST, CS_RST_SET);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003680 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3681err_out_iounmap:
3682 iounmap(hw->regs);
3683err_out_free_hw:
3684 kfree(hw);
3685err_out_free_regions:
3686 pci_release_regions(pdev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003687 pci_disable_device(pdev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003688err_out:
3689 return err;
3690}
3691
3692static void __devexit sky2_remove(struct pci_dev *pdev)
3693{
Stephen Hemminger793b8832005-09-14 16:06:14 -07003694 struct sky2_hw *hw = pci_get_drvdata(pdev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003695 struct net_device *dev0, *dev1;
3696
Stephen Hemminger793b8832005-09-14 16:06:14 -07003697 if (!hw)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003698 return;
3699
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07003700 del_timer_sync(&hw->idle_timer);
3701
Stephen Hemminger81906792007-02-15 16:40:33 -08003702 flush_scheduled_work();
3703
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07003704 sky2_write32(hw, B0_IMSK, 0);
Stephen Hemminger72cb8522006-05-08 15:11:32 -07003705 synchronize_irq(hw->pdev->irq);
3706
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003707 dev0 = hw->dev[0];
Stephen Hemminger793b8832005-09-14 16:06:14 -07003708 dev1 = hw->dev[1];
3709 if (dev1)
3710 unregister_netdev(dev1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003711 unregister_netdev(dev0);
3712
Stephen Hemmingerae306cc2006-12-20 13:06:36 -08003713 sky2_power_aux(hw);
3714
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003715 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003716 sky2_write8(hw, B0_CTST, CS_RST_SET);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003717 sky2_read8(hw, B0_CTST);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003718
3719 free_irq(pdev->irq, hw);
Stephen Hemmingerb0a20de2006-12-01 14:29:37 -08003720 if (hw->msi)
3721 pci_disable_msi(pdev);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003722 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003723 pci_release_regions(pdev);
3724 pci_disable_device(pdev);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003725
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003726 if (dev1)
3727 free_netdev(dev1);
3728 free_netdev(dev0);
3729 iounmap(hw->regs);
3730 kfree(hw);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003731
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003732 pci_set_drvdata(pdev, NULL);
3733}
3734
3735#ifdef CONFIG_PM
3736static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3737{
Stephen Hemminger793b8832005-09-14 16:06:14 -07003738 struct sky2_hw *hw = pci_get_drvdata(pdev);
Stephen Hemmingere3173832007-02-06 10:45:39 -08003739 int i, wol = 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003740
Stephen Hemmingereb35cf62006-06-13 17:17:31 +09003741 del_timer_sync(&hw->idle_timer);
Stephen Hemminger6a5706b2006-07-12 15:23:46 -07003742 netif_poll_disable(hw->dev[0]);
Stephen Hemmingereb35cf62006-06-13 17:17:31 +09003743
Stephen Hemmingerf05267e2006-06-13 17:17:28 +09003744 for (i = 0; i < hw->ports; i++) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003745 struct net_device *dev = hw->dev[i];
Stephen Hemmingere3173832007-02-06 10:45:39 -08003746 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003747
Stephen Hemmingere3173832007-02-06 10:45:39 -08003748 if (netif_running(dev))
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003749 sky2_down(dev);
Stephen Hemmingere3173832007-02-06 10:45:39 -08003750
3751 if (sky2->wol)
3752 sky2_wol_init(sky2);
3753
3754 wol |= sky2->wol;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003755 }
3756
Stephen Hemminger8ab8fca2006-06-13 17:17:30 +09003757 sky2_write32(hw, B0_IMSK, 0);
Stephen Hemmingerae306cc2006-12-20 13:06:36 -08003758 sky2_power_aux(hw);
Stephen Hemmingere3173832007-02-06 10:45:39 -08003759
Linus Torvaldsd374c1c2006-06-12 12:53:27 -07003760 pci_save_state(pdev);
Stephen Hemmingere3173832007-02-06 10:45:39 -08003761 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
Stephen Hemmingerae306cc2006-12-20 13:06:36 -08003762 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3763
Stephen Hemminger2ccc99b2006-06-13 17:17:27 +09003764 return 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003765}
3766
3767static int sky2_resume(struct pci_dev *pdev)
3768{
Stephen Hemminger793b8832005-09-14 16:06:14 -07003769 struct sky2_hw *hw = pci_get_drvdata(pdev);
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003770 int i, err;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003771
Stephen Hemmingerae306cc2006-12-20 13:06:36 -08003772 err = pci_set_power_state(pdev, PCI_D0);
3773 if (err)
3774 goto out;
3775
3776 err = pci_restore_state(pdev);
3777 if (err)
3778 goto out;
3779
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003780 pci_enable_wake(pdev, PCI_D0, 0);
Stephen Hemminger1ad5b4a2007-04-07 16:02:27 -07003781
3782 /* Re-enable all clocks */
3783 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
3784 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3785
Stephen Hemmingere3173832007-02-06 10:45:39 -08003786 sky2_reset(hw);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003787
Stephen Hemminger8ab8fca2006-06-13 17:17:30 +09003788 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3789
Stephen Hemmingerf05267e2006-06-13 17:17:28 +09003790 for (i = 0; i < hw->ports; i++) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003791 struct net_device *dev = hw->dev[i];
Stephen Hemminger6a5706b2006-07-12 15:23:46 -07003792 if (netif_running(dev)) {
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003793 err = sky2_up(dev);
3794 if (err) {
3795 printk(KERN_ERR PFX "%s: could not up: %d\n",
3796 dev->name, err);
3797 dev_close(dev);
Stephen Hemmingereb35cf62006-06-13 17:17:31 +09003798 goto out;
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003799 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003800 }
3801 }
Stephen Hemmingereb35cf62006-06-13 17:17:31 +09003802
Stephen Hemminger6a5706b2006-07-12 15:23:46 -07003803 netif_poll_enable(hw->dev[0]);
Stephen Hemmingereb35cf62006-06-13 17:17:31 +09003804 sky2_idle_start(hw);
Stephen Hemmingerae306cc2006-12-20 13:06:36 -08003805 return 0;
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003806out:
Stephen Hemmingerb02a9252007-02-06 10:45:40 -08003807 dev_err(&pdev->dev, "resume failed (%d)\n", err);
Stephen Hemmingerae306cc2006-12-20 13:06:36 -08003808 pci_disable_device(pdev);
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003809 return err;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003810}
3811#endif
3812
Stephen Hemmingere3173832007-02-06 10:45:39 -08003813static void sky2_shutdown(struct pci_dev *pdev)
3814{
3815 struct sky2_hw *hw = pci_get_drvdata(pdev);
3816 int i, wol = 0;
3817
3818 del_timer_sync(&hw->idle_timer);
3819 netif_poll_disable(hw->dev[0]);
3820
3821 for (i = 0; i < hw->ports; i++) {
3822 struct net_device *dev = hw->dev[i];
3823 struct sky2_port *sky2 = netdev_priv(dev);
3824
3825 if (sky2->wol) {
3826 wol = 1;
3827 sky2_wol_init(sky2);
3828 }
3829 }
3830
3831 if (wol)
3832 sky2_power_aux(hw);
3833
3834 pci_enable_wake(pdev, PCI_D3hot, wol);
3835 pci_enable_wake(pdev, PCI_D3cold, wol);
3836
3837 pci_disable_device(pdev);
3838 pci_set_power_state(pdev, PCI_D3hot);
3839
3840}
3841
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003842static struct pci_driver sky2_driver = {
Stephen Hemminger793b8832005-09-14 16:06:14 -07003843 .name = DRV_NAME,
3844 .id_table = sky2_id_table,
3845 .probe = sky2_probe,
3846 .remove = __devexit_p(sky2_remove),
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003847#ifdef CONFIG_PM
Stephen Hemminger793b8832005-09-14 16:06:14 -07003848 .suspend = sky2_suspend,
3849 .resume = sky2_resume,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003850#endif
Stephen Hemmingere3173832007-02-06 10:45:39 -08003851 .shutdown = sky2_shutdown,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003852};
3853
3854static int __init sky2_init_module(void)
3855{
shemminger@osdl.org50241c42005-11-30 11:45:22 -08003856 return pci_register_driver(&sky2_driver);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003857}
3858
3859static void __exit sky2_cleanup_module(void)
3860{
3861 pci_unregister_driver(&sky2_driver);
3862}
3863
3864module_init(sky2_init_module);
3865module_exit(sky2_cleanup_module);
3866
3867MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
Stephen Hemminger65ebe632007-01-23 11:38:57 -08003868MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003869MODULE_LICENSE("GPL");
shemminger@osdl.org5f4f9dc2005-11-30 11:45:23 -08003870MODULE_VERSION(DRV_VERSION);