blob: 7b33b4d5ebff3b6ba2521413196f4763e957e09f [file] [log] [blame]
Eric Anholt673a3942008-07-30 12:06:12 -07001/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
Chris Wilson1c5d22f2009-08-25 11:15:50 +010032#include "i915_trace.h"
Jesse Barnes652c3932009-08-17 13:31:43 -070033#include "intel_drv.h"
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090034#include <linux/slab.h>
Eric Anholt673a3942008-07-30 12:06:12 -070035#include <linux/swap.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include <linux/pci.h>
Zhenyu Wangf8f235e2010-08-27 11:08:57 +080037#include <linux/intel-gtt.h>
Eric Anholt673a3942008-07-30 12:06:12 -070038
Daniel Vetter0108a3e2010-08-07 11:01:21 +010039static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
Daniel Vetterba3d8d72010-02-11 22:37:04 +010040
41static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
42 bool pipelined);
Eric Anholte47c68e2008-11-14 13:35:19 -080043static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
44static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
Eric Anholte47c68e2008-11-14 13:35:19 -080045static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
46 int write);
47static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
48 uint64_t offset,
49 uint64_t size);
50static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
Chris Wilson2cf34d72010-09-14 13:03:28 +010051static int i915_gem_object_wait_rendering(struct drm_gem_object *obj,
52 bool interruptible);
Jesse Barnesde151cf2008-11-12 10:03:55 -080053static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
54 unsigned alignment);
Jesse Barnesde151cf2008-11-12 10:03:55 -080055static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +100056static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
57 struct drm_i915_gem_pwrite *args,
58 struct drm_file *file_priv);
Chris Wilsonbe726152010-07-23 23:18:50 +010059static void i915_gem_free_object_tail(struct drm_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -070060
Chris Wilson31169712009-09-14 16:50:28 +010061static LIST_HEAD(shrink_list);
62static DEFINE_SPINLOCK(shrink_list_lock);
63
Chris Wilson7d1c4802010-08-07 21:45:03 +010064static inline bool
65i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
66{
67 return obj_priv->gtt_space &&
68 !obj_priv->active &&
69 obj_priv->pin_count == 0;
70}
71
Jesse Barnes79e53942008-11-07 14:24:08 -080072int i915_gem_do_init(struct drm_device *dev, unsigned long start,
73 unsigned long end)
74{
75 drm_i915_private_t *dev_priv = dev->dev_private;
76
77 if (start >= end ||
78 (start & (PAGE_SIZE - 1)) != 0 ||
79 (end & (PAGE_SIZE - 1)) != 0) {
80 return -EINVAL;
81 }
82
83 drm_mm_init(&dev_priv->mm.gtt_space, start,
84 end - start);
85
86 dev->gtt_total = (uint32_t) (end - start);
87
88 return 0;
89}
Keith Packard6dbe2772008-10-14 21:41:13 -070090
Eric Anholt673a3942008-07-30 12:06:12 -070091int
92i915_gem_init_ioctl(struct drm_device *dev, void *data,
93 struct drm_file *file_priv)
94{
Eric Anholt673a3942008-07-30 12:06:12 -070095 struct drm_i915_gem_init *args = data;
Jesse Barnes79e53942008-11-07 14:24:08 -080096 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -070097
98 mutex_lock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080099 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
Eric Anholt673a3942008-07-30 12:06:12 -0700100 mutex_unlock(&dev->struct_mutex);
101
Jesse Barnes79e53942008-11-07 14:24:08 -0800102 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700103}
104
Eric Anholt5a125c32008-10-22 21:40:13 -0700105int
106i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
107 struct drm_file *file_priv)
108{
Eric Anholt5a125c32008-10-22 21:40:13 -0700109 struct drm_i915_gem_get_aperture *args = data;
Eric Anholt5a125c32008-10-22 21:40:13 -0700110
111 if (!(dev->driver->driver_features & DRIVER_GEM))
112 return -ENODEV;
113
114 args->aper_size = dev->gtt_total;
Keith Packard2678d9d2008-11-20 22:54:54 -0800115 args->aper_available_size = (args->aper_size -
116 atomic_read(&dev->pin_memory));
Eric Anholt5a125c32008-10-22 21:40:13 -0700117
118 return 0;
119}
120
Eric Anholt673a3942008-07-30 12:06:12 -0700121
122/**
123 * Creates a new mm object and returns a handle to it.
124 */
125int
126i915_gem_create_ioctl(struct drm_device *dev, void *data,
127 struct drm_file *file_priv)
128{
129 struct drm_i915_gem_create *args = data;
130 struct drm_gem_object *obj;
Pekka Paalanena1a2d1d2009-08-23 12:40:55 +0300131 int ret;
132 u32 handle;
Eric Anholt673a3942008-07-30 12:06:12 -0700133
134 args->size = roundup(args->size, PAGE_SIZE);
135
136 /* Allocate the new object */
Daniel Vetterac52bc52010-04-09 19:05:06 +0000137 obj = i915_gem_alloc_object(dev, args->size);
Eric Anholt673a3942008-07-30 12:06:12 -0700138 if (obj == NULL)
139 return -ENOMEM;
140
141 ret = drm_gem_handle_create(file_priv, obj, &handle);
Chris Wilson1dfd9752010-09-06 14:44:14 +0100142 if (ret) {
143 drm_gem_object_unreference_unlocked(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700144 return ret;
Chris Wilson1dfd9752010-09-06 14:44:14 +0100145 }
146
147 /* Sink the floating reference from kref_init(handlecount) */
148 drm_gem_object_handle_unreference_unlocked(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700149
150 args->handle = handle;
Eric Anholt673a3942008-07-30 12:06:12 -0700151 return 0;
152}
153
Eric Anholt40123c12009-03-09 13:42:30 -0700154static inline int
Eric Anholteb014592009-03-10 11:44:52 -0700155fast_shmem_read(struct page **pages,
156 loff_t page_base, int page_offset,
157 char __user *data,
158 int length)
159{
160 char __iomem *vaddr;
Florian Mickler2bc43b52009-04-06 22:55:41 +0200161 int unwritten;
Eric Anholteb014592009-03-10 11:44:52 -0700162
163 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
164 if (vaddr == NULL)
165 return -ENOMEM;
Florian Mickler2bc43b52009-04-06 22:55:41 +0200166 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
Eric Anholteb014592009-03-10 11:44:52 -0700167 kunmap_atomic(vaddr, KM_USER0);
168
Florian Mickler2bc43b52009-04-06 22:55:41 +0200169 if (unwritten)
170 return -EFAULT;
171
172 return 0;
Eric Anholteb014592009-03-10 11:44:52 -0700173}
174
Eric Anholt280b7132009-03-12 16:56:27 -0700175static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
176{
177 drm_i915_private_t *dev_priv = obj->dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +0100178 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt280b7132009-03-12 16:56:27 -0700179
180 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
181 obj_priv->tiling_mode != I915_TILING_NONE;
182}
183
Chris Wilson99a03df2010-05-27 14:15:34 +0100184static inline void
Eric Anholt40123c12009-03-09 13:42:30 -0700185slow_shmem_copy(struct page *dst_page,
186 int dst_offset,
187 struct page *src_page,
188 int src_offset,
189 int length)
190{
191 char *dst_vaddr, *src_vaddr;
192
Chris Wilson99a03df2010-05-27 14:15:34 +0100193 dst_vaddr = kmap(dst_page);
194 src_vaddr = kmap(src_page);
Eric Anholt40123c12009-03-09 13:42:30 -0700195
196 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
197
Chris Wilson99a03df2010-05-27 14:15:34 +0100198 kunmap(src_page);
199 kunmap(dst_page);
Eric Anholt40123c12009-03-09 13:42:30 -0700200}
201
Chris Wilson99a03df2010-05-27 14:15:34 +0100202static inline void
Eric Anholt280b7132009-03-12 16:56:27 -0700203slow_shmem_bit17_copy(struct page *gpu_page,
204 int gpu_offset,
205 struct page *cpu_page,
206 int cpu_offset,
207 int length,
208 int is_read)
209{
210 char *gpu_vaddr, *cpu_vaddr;
211
212 /* Use the unswizzled path if this page isn't affected. */
213 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
214 if (is_read)
215 return slow_shmem_copy(cpu_page, cpu_offset,
216 gpu_page, gpu_offset, length);
217 else
218 return slow_shmem_copy(gpu_page, gpu_offset,
219 cpu_page, cpu_offset, length);
220 }
221
Chris Wilson99a03df2010-05-27 14:15:34 +0100222 gpu_vaddr = kmap(gpu_page);
223 cpu_vaddr = kmap(cpu_page);
Eric Anholt280b7132009-03-12 16:56:27 -0700224
225 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
226 * XORing with the other bits (A9 for Y, A9 and A10 for X)
227 */
228 while (length > 0) {
229 int cacheline_end = ALIGN(gpu_offset + 1, 64);
230 int this_length = min(cacheline_end - gpu_offset, length);
231 int swizzled_gpu_offset = gpu_offset ^ 64;
232
233 if (is_read) {
234 memcpy(cpu_vaddr + cpu_offset,
235 gpu_vaddr + swizzled_gpu_offset,
236 this_length);
237 } else {
238 memcpy(gpu_vaddr + swizzled_gpu_offset,
239 cpu_vaddr + cpu_offset,
240 this_length);
241 }
242 cpu_offset += this_length;
243 gpu_offset += this_length;
244 length -= this_length;
245 }
246
Chris Wilson99a03df2010-05-27 14:15:34 +0100247 kunmap(cpu_page);
248 kunmap(gpu_page);
Eric Anholt280b7132009-03-12 16:56:27 -0700249}
250
Eric Anholt673a3942008-07-30 12:06:12 -0700251/**
Eric Anholteb014592009-03-10 11:44:52 -0700252 * This is the fast shmem pread path, which attempts to copy_from_user directly
253 * from the backing pages of the object to the user's address space. On a
254 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
255 */
256static int
257i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
258 struct drm_i915_gem_pread *args,
259 struct drm_file *file_priv)
260{
Daniel Vetter23010e42010-03-08 13:35:02 +0100261 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholteb014592009-03-10 11:44:52 -0700262 ssize_t remain;
263 loff_t offset, page_base;
264 char __user *user_data;
265 int page_offset, page_length;
266 int ret;
267
268 user_data = (char __user *) (uintptr_t) args->data_ptr;
269 remain = args->size;
270
271 mutex_lock(&dev->struct_mutex);
272
Chris Wilson4bdadb92010-01-27 13:36:32 +0000273 ret = i915_gem_object_get_pages(obj, 0);
Eric Anholteb014592009-03-10 11:44:52 -0700274 if (ret != 0)
275 goto fail_unlock;
276
277 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
278 args->size);
279 if (ret != 0)
280 goto fail_put_pages;
281
Daniel Vetter23010e42010-03-08 13:35:02 +0100282 obj_priv = to_intel_bo(obj);
Eric Anholteb014592009-03-10 11:44:52 -0700283 offset = args->offset;
284
285 while (remain > 0) {
286 /* Operation in this page
287 *
288 * page_base = page offset within aperture
289 * page_offset = offset within page
290 * page_length = bytes to copy for this page
291 */
292 page_base = (offset & ~(PAGE_SIZE-1));
293 page_offset = offset & (PAGE_SIZE-1);
294 page_length = remain;
295 if ((page_offset + remain) > PAGE_SIZE)
296 page_length = PAGE_SIZE - page_offset;
297
298 ret = fast_shmem_read(obj_priv->pages,
299 page_base, page_offset,
300 user_data, page_length);
301 if (ret)
302 goto fail_put_pages;
303
304 remain -= page_length;
305 user_data += page_length;
306 offset += page_length;
307 }
308
309fail_put_pages:
310 i915_gem_object_put_pages(obj);
311fail_unlock:
312 mutex_unlock(&dev->struct_mutex);
313
314 return ret;
315}
316
Chris Wilson07f73f62009-09-14 16:50:30 +0100317static int
318i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
319{
320 int ret;
321
Chris Wilson4bdadb92010-01-27 13:36:32 +0000322 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
Chris Wilson07f73f62009-09-14 16:50:30 +0100323
324 /* If we've insufficient memory to map in the pages, attempt
325 * to make some space by throwing out some old buffers.
326 */
327 if (ret == -ENOMEM) {
328 struct drm_device *dev = obj->dev;
Chris Wilson07f73f62009-09-14 16:50:30 +0100329
Daniel Vetter0108a3e2010-08-07 11:01:21 +0100330 ret = i915_gem_evict_something(dev, obj->size,
331 i915_gem_get_gtt_alignment(obj));
Chris Wilson07f73f62009-09-14 16:50:30 +0100332 if (ret)
333 return ret;
334
Chris Wilson4bdadb92010-01-27 13:36:32 +0000335 ret = i915_gem_object_get_pages(obj, 0);
Chris Wilson07f73f62009-09-14 16:50:30 +0100336 }
337
338 return ret;
339}
340
Eric Anholteb014592009-03-10 11:44:52 -0700341/**
342 * This is the fallback shmem pread path, which allocates temporary storage
343 * in kernel space to copy_to_user into outside of the struct_mutex, so we
344 * can copy out of the object's backing pages while holding the struct mutex
345 * and not take page faults.
346 */
347static int
348i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
349 struct drm_i915_gem_pread *args,
350 struct drm_file *file_priv)
351{
Daniel Vetter23010e42010-03-08 13:35:02 +0100352 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholteb014592009-03-10 11:44:52 -0700353 struct mm_struct *mm = current->mm;
354 struct page **user_pages;
355 ssize_t remain;
356 loff_t offset, pinned_pages, i;
357 loff_t first_data_page, last_data_page, num_pages;
358 int shmem_page_index, shmem_page_offset;
359 int data_page_index, data_page_offset;
360 int page_length;
361 int ret;
362 uint64_t data_ptr = args->data_ptr;
Eric Anholt280b7132009-03-12 16:56:27 -0700363 int do_bit17_swizzling;
Eric Anholteb014592009-03-10 11:44:52 -0700364
365 remain = args->size;
366
367 /* Pin the user pages containing the data. We can't fault while
368 * holding the struct mutex, yet we want to hold it while
369 * dereferencing the user data.
370 */
371 first_data_page = data_ptr / PAGE_SIZE;
372 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
373 num_pages = last_data_page - first_data_page + 1;
374
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700375 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
Eric Anholteb014592009-03-10 11:44:52 -0700376 if (user_pages == NULL)
377 return -ENOMEM;
378
379 down_read(&mm->mmap_sem);
380 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
Eric Anholte5e9ecd2009-04-07 16:01:22 -0700381 num_pages, 1, 0, user_pages, NULL);
Eric Anholteb014592009-03-10 11:44:52 -0700382 up_read(&mm->mmap_sem);
383 if (pinned_pages < num_pages) {
384 ret = -EFAULT;
385 goto fail_put_user_pages;
386 }
387
Eric Anholt280b7132009-03-12 16:56:27 -0700388 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
389
Eric Anholteb014592009-03-10 11:44:52 -0700390 mutex_lock(&dev->struct_mutex);
391
Chris Wilson07f73f62009-09-14 16:50:30 +0100392 ret = i915_gem_object_get_pages_or_evict(obj);
393 if (ret)
Eric Anholteb014592009-03-10 11:44:52 -0700394 goto fail_unlock;
395
396 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
397 args->size);
398 if (ret != 0)
399 goto fail_put_pages;
400
Daniel Vetter23010e42010-03-08 13:35:02 +0100401 obj_priv = to_intel_bo(obj);
Eric Anholteb014592009-03-10 11:44:52 -0700402 offset = args->offset;
403
404 while (remain > 0) {
405 /* Operation in this page
406 *
407 * shmem_page_index = page number within shmem file
408 * shmem_page_offset = offset within page in shmem file
409 * data_page_index = page number in get_user_pages return
410 * data_page_offset = offset with data_page_index page.
411 * page_length = bytes to copy for this page
412 */
413 shmem_page_index = offset / PAGE_SIZE;
414 shmem_page_offset = offset & ~PAGE_MASK;
415 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
416 data_page_offset = data_ptr & ~PAGE_MASK;
417
418 page_length = remain;
419 if ((shmem_page_offset + page_length) > PAGE_SIZE)
420 page_length = PAGE_SIZE - shmem_page_offset;
421 if ((data_page_offset + page_length) > PAGE_SIZE)
422 page_length = PAGE_SIZE - data_page_offset;
423
Eric Anholt280b7132009-03-12 16:56:27 -0700424 if (do_bit17_swizzling) {
Chris Wilson99a03df2010-05-27 14:15:34 +0100425 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
Eric Anholt280b7132009-03-12 16:56:27 -0700426 shmem_page_offset,
Chris Wilson99a03df2010-05-27 14:15:34 +0100427 user_pages[data_page_index],
428 data_page_offset,
429 page_length,
430 1);
431 } else {
432 slow_shmem_copy(user_pages[data_page_index],
433 data_page_offset,
434 obj_priv->pages[shmem_page_index],
435 shmem_page_offset,
436 page_length);
Eric Anholt280b7132009-03-12 16:56:27 -0700437 }
Eric Anholteb014592009-03-10 11:44:52 -0700438
439 remain -= page_length;
440 data_ptr += page_length;
441 offset += page_length;
442 }
443
444fail_put_pages:
445 i915_gem_object_put_pages(obj);
446fail_unlock:
447 mutex_unlock(&dev->struct_mutex);
448fail_put_user_pages:
449 for (i = 0; i < pinned_pages; i++) {
450 SetPageDirty(user_pages[i]);
451 page_cache_release(user_pages[i]);
452 }
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700453 drm_free_large(user_pages);
Eric Anholteb014592009-03-10 11:44:52 -0700454
455 return ret;
456}
457
Eric Anholt673a3942008-07-30 12:06:12 -0700458/**
459 * Reads data from the object referenced by handle.
460 *
461 * On error, the contents of *data are undefined.
462 */
463int
464i915_gem_pread_ioctl(struct drm_device *dev, void *data,
465 struct drm_file *file_priv)
466{
467 struct drm_i915_gem_pread *args = data;
468 struct drm_gem_object *obj;
469 struct drm_i915_gem_object *obj_priv;
Eric Anholt673a3942008-07-30 12:06:12 -0700470 int ret;
471
472 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
473 if (obj == NULL)
Chris Wilsonbf79cb92010-08-04 14:19:46 +0100474 return -ENOENT;
Daniel Vetter23010e42010-03-08 13:35:02 +0100475 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700476
477 /* Bounds check source.
478 *
479 * XXX: This could use review for overflow issues...
480 */
481 if (args->offset > obj->size || args->size > obj->size ||
482 args->offset + args->size > obj->size) {
Luca Barbieribc9025b2010-02-09 05:49:12 +0000483 drm_gem_object_unreference_unlocked(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700484 return -EINVAL;
485 }
486
Eric Anholt280b7132009-03-12 16:56:27 -0700487 if (i915_gem_object_needs_bit17_swizzle(obj)) {
Eric Anholteb014592009-03-10 11:44:52 -0700488 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
Eric Anholt280b7132009-03-12 16:56:27 -0700489 } else {
490 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
491 if (ret != 0)
492 ret = i915_gem_shmem_pread_slow(dev, obj, args,
493 file_priv);
494 }
Eric Anholt673a3942008-07-30 12:06:12 -0700495
Luca Barbieribc9025b2010-02-09 05:49:12 +0000496 drm_gem_object_unreference_unlocked(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700497
Eric Anholteb014592009-03-10 11:44:52 -0700498 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700499}
500
Keith Packard0839ccb2008-10-30 19:38:48 -0700501/* This is the fast write path which cannot handle
502 * page faults in the source data
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700503 */
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700504
Keith Packard0839ccb2008-10-30 19:38:48 -0700505static inline int
506fast_user_write(struct io_mapping *mapping,
507 loff_t page_base, int page_offset,
508 char __user *user_data,
509 int length)
510{
511 char *vaddr_atomic;
512 unsigned long unwritten;
513
Chris Wilsonfca3ec02010-08-04 14:34:24 +0100514 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0);
Keith Packard0839ccb2008-10-30 19:38:48 -0700515 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
516 user_data, length);
Chris Wilsonfca3ec02010-08-04 14:34:24 +0100517 io_mapping_unmap_atomic(vaddr_atomic, KM_USER0);
Keith Packard0839ccb2008-10-30 19:38:48 -0700518 if (unwritten)
519 return -EFAULT;
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700520 return 0;
Keith Packard0839ccb2008-10-30 19:38:48 -0700521}
522
523/* Here's the write path which can sleep for
524 * page faults
525 */
526
Chris Wilsonab34c222010-05-27 14:15:35 +0100527static inline void
Eric Anholt3de09aa2009-03-09 09:42:23 -0700528slow_kernel_write(struct io_mapping *mapping,
529 loff_t gtt_base, int gtt_offset,
530 struct page *user_page, int user_offset,
531 int length)
Keith Packard0839ccb2008-10-30 19:38:48 -0700532{
Chris Wilsonab34c222010-05-27 14:15:35 +0100533 char __iomem *dst_vaddr;
534 char *src_vaddr;
Keith Packard0839ccb2008-10-30 19:38:48 -0700535
Chris Wilsonab34c222010-05-27 14:15:35 +0100536 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
537 src_vaddr = kmap(user_page);
538
539 memcpy_toio(dst_vaddr + gtt_offset,
540 src_vaddr + user_offset,
541 length);
542
543 kunmap(user_page);
544 io_mapping_unmap(dst_vaddr);
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700545}
546
Eric Anholt40123c12009-03-09 13:42:30 -0700547static inline int
548fast_shmem_write(struct page **pages,
549 loff_t page_base, int page_offset,
550 char __user *data,
551 int length)
552{
553 char __iomem *vaddr;
Dave Airlied0088772009-03-28 20:29:48 -0400554 unsigned long unwritten;
Eric Anholt40123c12009-03-09 13:42:30 -0700555
556 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
557 if (vaddr == NULL)
558 return -ENOMEM;
Dave Airlied0088772009-03-28 20:29:48 -0400559 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
Eric Anholt40123c12009-03-09 13:42:30 -0700560 kunmap_atomic(vaddr, KM_USER0);
561
Dave Airlied0088772009-03-28 20:29:48 -0400562 if (unwritten)
563 return -EFAULT;
Eric Anholt40123c12009-03-09 13:42:30 -0700564 return 0;
565}
566
Eric Anholt3de09aa2009-03-09 09:42:23 -0700567/**
568 * This is the fast pwrite path, where we copy the data directly from the
569 * user into the GTT, uncached.
570 */
Eric Anholt673a3942008-07-30 12:06:12 -0700571static int
Eric Anholt3de09aa2009-03-09 09:42:23 -0700572i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
573 struct drm_i915_gem_pwrite *args,
574 struct drm_file *file_priv)
Eric Anholt673a3942008-07-30 12:06:12 -0700575{
Daniel Vetter23010e42010-03-08 13:35:02 +0100576 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Keith Packard0839ccb2008-10-30 19:38:48 -0700577 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -0700578 ssize_t remain;
Keith Packard0839ccb2008-10-30 19:38:48 -0700579 loff_t offset, page_base;
Eric Anholt673a3942008-07-30 12:06:12 -0700580 char __user *user_data;
Keith Packard0839ccb2008-10-30 19:38:48 -0700581 int page_offset, page_length;
582 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700583
584 user_data = (char __user *) (uintptr_t) args->data_ptr;
585 remain = args->size;
586 if (!access_ok(VERIFY_READ, user_data, remain))
587 return -EFAULT;
588
589
590 mutex_lock(&dev->struct_mutex);
591 ret = i915_gem_object_pin(obj, 0);
592 if (ret) {
593 mutex_unlock(&dev->struct_mutex);
594 return ret;
595 }
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800596 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
Eric Anholt673a3942008-07-30 12:06:12 -0700597 if (ret)
598 goto fail;
599
Daniel Vetter23010e42010-03-08 13:35:02 +0100600 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700601 offset = obj_priv->gtt_offset + args->offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700602
603 while (remain > 0) {
604 /* Operation in this page
605 *
Keith Packard0839ccb2008-10-30 19:38:48 -0700606 * page_base = page offset within aperture
607 * page_offset = offset within page
608 * page_length = bytes to copy for this page
Eric Anholt673a3942008-07-30 12:06:12 -0700609 */
Keith Packard0839ccb2008-10-30 19:38:48 -0700610 page_base = (offset & ~(PAGE_SIZE-1));
611 page_offset = offset & (PAGE_SIZE-1);
612 page_length = remain;
613 if ((page_offset + remain) > PAGE_SIZE)
614 page_length = PAGE_SIZE - page_offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700615
Keith Packard0839ccb2008-10-30 19:38:48 -0700616 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
617 page_offset, user_data, page_length);
Eric Anholt673a3942008-07-30 12:06:12 -0700618
Keith Packard0839ccb2008-10-30 19:38:48 -0700619 /* If we get a fault while copying data, then (presumably) our
Eric Anholt3de09aa2009-03-09 09:42:23 -0700620 * source page isn't available. Return the error and we'll
621 * retry in the slow path.
Keith Packard0839ccb2008-10-30 19:38:48 -0700622 */
Eric Anholt3de09aa2009-03-09 09:42:23 -0700623 if (ret)
624 goto fail;
Eric Anholt673a3942008-07-30 12:06:12 -0700625
Keith Packard0839ccb2008-10-30 19:38:48 -0700626 remain -= page_length;
627 user_data += page_length;
628 offset += page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700629 }
Eric Anholt673a3942008-07-30 12:06:12 -0700630
631fail:
632 i915_gem_object_unpin(obj);
633 mutex_unlock(&dev->struct_mutex);
634
635 return ret;
636}
637
Eric Anholt3de09aa2009-03-09 09:42:23 -0700638/**
639 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
640 * the memory and maps it using kmap_atomic for copying.
641 *
642 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
643 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
644 */
Eric Anholt3043c602008-10-02 12:24:47 -0700645static int
Eric Anholt3de09aa2009-03-09 09:42:23 -0700646i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
647 struct drm_i915_gem_pwrite *args,
648 struct drm_file *file_priv)
Eric Anholt673a3942008-07-30 12:06:12 -0700649{
Daniel Vetter23010e42010-03-08 13:35:02 +0100650 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt3de09aa2009-03-09 09:42:23 -0700651 drm_i915_private_t *dev_priv = dev->dev_private;
652 ssize_t remain;
653 loff_t gtt_page_base, offset;
654 loff_t first_data_page, last_data_page, num_pages;
655 loff_t pinned_pages, i;
656 struct page **user_pages;
657 struct mm_struct *mm = current->mm;
658 int gtt_page_offset, data_page_offset, data_page_index, page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700659 int ret;
Eric Anholt3de09aa2009-03-09 09:42:23 -0700660 uint64_t data_ptr = args->data_ptr;
661
662 remain = args->size;
663
664 /* Pin the user pages containing the data. We can't fault while
665 * holding the struct mutex, and all of the pwrite implementations
666 * want to hold it while dereferencing the user data.
667 */
668 first_data_page = data_ptr / PAGE_SIZE;
669 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
670 num_pages = last_data_page - first_data_page + 1;
671
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700672 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
Eric Anholt3de09aa2009-03-09 09:42:23 -0700673 if (user_pages == NULL)
674 return -ENOMEM;
675
676 down_read(&mm->mmap_sem);
677 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
678 num_pages, 0, 0, user_pages, NULL);
679 up_read(&mm->mmap_sem);
680 if (pinned_pages < num_pages) {
681 ret = -EFAULT;
682 goto out_unpin_pages;
683 }
684
685 mutex_lock(&dev->struct_mutex);
686 ret = i915_gem_object_pin(obj, 0);
687 if (ret)
688 goto out_unlock;
689
690 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
691 if (ret)
692 goto out_unpin_object;
693
Daniel Vetter23010e42010-03-08 13:35:02 +0100694 obj_priv = to_intel_bo(obj);
Eric Anholt3de09aa2009-03-09 09:42:23 -0700695 offset = obj_priv->gtt_offset + args->offset;
696
697 while (remain > 0) {
698 /* Operation in this page
699 *
700 * gtt_page_base = page offset within aperture
701 * gtt_page_offset = offset within page in aperture
702 * data_page_index = page number in get_user_pages return
703 * data_page_offset = offset with data_page_index page.
704 * page_length = bytes to copy for this page
705 */
706 gtt_page_base = offset & PAGE_MASK;
707 gtt_page_offset = offset & ~PAGE_MASK;
708 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
709 data_page_offset = data_ptr & ~PAGE_MASK;
710
711 page_length = remain;
712 if ((gtt_page_offset + page_length) > PAGE_SIZE)
713 page_length = PAGE_SIZE - gtt_page_offset;
714 if ((data_page_offset + page_length) > PAGE_SIZE)
715 page_length = PAGE_SIZE - data_page_offset;
716
Chris Wilsonab34c222010-05-27 14:15:35 +0100717 slow_kernel_write(dev_priv->mm.gtt_mapping,
718 gtt_page_base, gtt_page_offset,
719 user_pages[data_page_index],
720 data_page_offset,
721 page_length);
Eric Anholt3de09aa2009-03-09 09:42:23 -0700722
723 remain -= page_length;
724 offset += page_length;
725 data_ptr += page_length;
726 }
727
728out_unpin_object:
729 i915_gem_object_unpin(obj);
730out_unlock:
731 mutex_unlock(&dev->struct_mutex);
732out_unpin_pages:
733 for (i = 0; i < pinned_pages; i++)
734 page_cache_release(user_pages[i]);
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700735 drm_free_large(user_pages);
Eric Anholt3de09aa2009-03-09 09:42:23 -0700736
737 return ret;
738}
739
Eric Anholt40123c12009-03-09 13:42:30 -0700740/**
741 * This is the fast shmem pwrite path, which attempts to directly
742 * copy_from_user into the kmapped pages backing the object.
743 */
Eric Anholt673a3942008-07-30 12:06:12 -0700744static int
Eric Anholt40123c12009-03-09 13:42:30 -0700745i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
746 struct drm_i915_gem_pwrite *args,
747 struct drm_file *file_priv)
Eric Anholt673a3942008-07-30 12:06:12 -0700748{
Daniel Vetter23010e42010-03-08 13:35:02 +0100749 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt40123c12009-03-09 13:42:30 -0700750 ssize_t remain;
751 loff_t offset, page_base;
752 char __user *user_data;
753 int page_offset, page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700754 int ret;
Eric Anholt40123c12009-03-09 13:42:30 -0700755
756 user_data = (char __user *) (uintptr_t) args->data_ptr;
757 remain = args->size;
Eric Anholt673a3942008-07-30 12:06:12 -0700758
759 mutex_lock(&dev->struct_mutex);
760
Chris Wilson4bdadb92010-01-27 13:36:32 +0000761 ret = i915_gem_object_get_pages(obj, 0);
Eric Anholt40123c12009-03-09 13:42:30 -0700762 if (ret != 0)
763 goto fail_unlock;
764
Eric Anholte47c68e2008-11-14 13:35:19 -0800765 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
Eric Anholt40123c12009-03-09 13:42:30 -0700766 if (ret != 0)
767 goto fail_put_pages;
Eric Anholt673a3942008-07-30 12:06:12 -0700768
Daniel Vetter23010e42010-03-08 13:35:02 +0100769 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700770 offset = args->offset;
Eric Anholt40123c12009-03-09 13:42:30 -0700771 obj_priv->dirty = 1;
Eric Anholt673a3942008-07-30 12:06:12 -0700772
Eric Anholt40123c12009-03-09 13:42:30 -0700773 while (remain > 0) {
774 /* Operation in this page
775 *
776 * page_base = page offset within aperture
777 * page_offset = offset within page
778 * page_length = bytes to copy for this page
779 */
780 page_base = (offset & ~(PAGE_SIZE-1));
781 page_offset = offset & (PAGE_SIZE-1);
782 page_length = remain;
783 if ((page_offset + remain) > PAGE_SIZE)
784 page_length = PAGE_SIZE - page_offset;
785
786 ret = fast_shmem_write(obj_priv->pages,
787 page_base, page_offset,
788 user_data, page_length);
789 if (ret)
790 goto fail_put_pages;
791
792 remain -= page_length;
793 user_data += page_length;
794 offset += page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700795 }
796
Eric Anholt40123c12009-03-09 13:42:30 -0700797fail_put_pages:
798 i915_gem_object_put_pages(obj);
799fail_unlock:
Eric Anholt673a3942008-07-30 12:06:12 -0700800 mutex_unlock(&dev->struct_mutex);
801
Eric Anholt40123c12009-03-09 13:42:30 -0700802 return ret;
803}
804
805/**
806 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
807 * the memory and maps it using kmap_atomic for copying.
808 *
809 * This avoids taking mmap_sem for faulting on the user's address while the
810 * struct_mutex is held.
811 */
812static int
813i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
814 struct drm_i915_gem_pwrite *args,
815 struct drm_file *file_priv)
816{
Daniel Vetter23010e42010-03-08 13:35:02 +0100817 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt40123c12009-03-09 13:42:30 -0700818 struct mm_struct *mm = current->mm;
819 struct page **user_pages;
820 ssize_t remain;
821 loff_t offset, pinned_pages, i;
822 loff_t first_data_page, last_data_page, num_pages;
823 int shmem_page_index, shmem_page_offset;
824 int data_page_index, data_page_offset;
825 int page_length;
826 int ret;
827 uint64_t data_ptr = args->data_ptr;
Eric Anholt280b7132009-03-12 16:56:27 -0700828 int do_bit17_swizzling;
Eric Anholt40123c12009-03-09 13:42:30 -0700829
830 remain = args->size;
831
832 /* Pin the user pages containing the data. We can't fault while
833 * holding the struct mutex, and all of the pwrite implementations
834 * want to hold it while dereferencing the user data.
835 */
836 first_data_page = data_ptr / PAGE_SIZE;
837 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
838 num_pages = last_data_page - first_data_page + 1;
839
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700840 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
Eric Anholt40123c12009-03-09 13:42:30 -0700841 if (user_pages == NULL)
842 return -ENOMEM;
843
844 down_read(&mm->mmap_sem);
845 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
846 num_pages, 0, 0, user_pages, NULL);
847 up_read(&mm->mmap_sem);
848 if (pinned_pages < num_pages) {
849 ret = -EFAULT;
850 goto fail_put_user_pages;
851 }
852
Eric Anholt280b7132009-03-12 16:56:27 -0700853 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
854
Eric Anholt40123c12009-03-09 13:42:30 -0700855 mutex_lock(&dev->struct_mutex);
856
Chris Wilson07f73f62009-09-14 16:50:30 +0100857 ret = i915_gem_object_get_pages_or_evict(obj);
858 if (ret)
Eric Anholt40123c12009-03-09 13:42:30 -0700859 goto fail_unlock;
860
861 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
862 if (ret != 0)
863 goto fail_put_pages;
864
Daniel Vetter23010e42010-03-08 13:35:02 +0100865 obj_priv = to_intel_bo(obj);
Eric Anholt40123c12009-03-09 13:42:30 -0700866 offset = args->offset;
867 obj_priv->dirty = 1;
868
869 while (remain > 0) {
870 /* Operation in this page
871 *
872 * shmem_page_index = page number within shmem file
873 * shmem_page_offset = offset within page in shmem file
874 * data_page_index = page number in get_user_pages return
875 * data_page_offset = offset with data_page_index page.
876 * page_length = bytes to copy for this page
877 */
878 shmem_page_index = offset / PAGE_SIZE;
879 shmem_page_offset = offset & ~PAGE_MASK;
880 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
881 data_page_offset = data_ptr & ~PAGE_MASK;
882
883 page_length = remain;
884 if ((shmem_page_offset + page_length) > PAGE_SIZE)
885 page_length = PAGE_SIZE - shmem_page_offset;
886 if ((data_page_offset + page_length) > PAGE_SIZE)
887 page_length = PAGE_SIZE - data_page_offset;
888
Eric Anholt280b7132009-03-12 16:56:27 -0700889 if (do_bit17_swizzling) {
Chris Wilson99a03df2010-05-27 14:15:34 +0100890 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
Eric Anholt280b7132009-03-12 16:56:27 -0700891 shmem_page_offset,
892 user_pages[data_page_index],
893 data_page_offset,
Chris Wilson99a03df2010-05-27 14:15:34 +0100894 page_length,
895 0);
896 } else {
897 slow_shmem_copy(obj_priv->pages[shmem_page_index],
898 shmem_page_offset,
899 user_pages[data_page_index],
900 data_page_offset,
901 page_length);
Eric Anholt280b7132009-03-12 16:56:27 -0700902 }
Eric Anholt40123c12009-03-09 13:42:30 -0700903
904 remain -= page_length;
905 data_ptr += page_length;
906 offset += page_length;
907 }
908
909fail_put_pages:
910 i915_gem_object_put_pages(obj);
911fail_unlock:
912 mutex_unlock(&dev->struct_mutex);
913fail_put_user_pages:
914 for (i = 0; i < pinned_pages; i++)
915 page_cache_release(user_pages[i]);
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700916 drm_free_large(user_pages);
Eric Anholt40123c12009-03-09 13:42:30 -0700917
918 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700919}
920
921/**
922 * Writes data to the object referenced by handle.
923 *
924 * On error, the contents of the buffer that were to be modified are undefined.
925 */
926int
927i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
928 struct drm_file *file_priv)
929{
930 struct drm_i915_gem_pwrite *args = data;
931 struct drm_gem_object *obj;
932 struct drm_i915_gem_object *obj_priv;
933 int ret = 0;
934
935 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
936 if (obj == NULL)
Chris Wilsonbf79cb92010-08-04 14:19:46 +0100937 return -ENOENT;
Daniel Vetter23010e42010-03-08 13:35:02 +0100938 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700939
940 /* Bounds check destination.
941 *
942 * XXX: This could use review for overflow issues...
943 */
944 if (args->offset > obj->size || args->size > obj->size ||
945 args->offset + args->size > obj->size) {
Luca Barbieribc9025b2010-02-09 05:49:12 +0000946 drm_gem_object_unreference_unlocked(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700947 return -EINVAL;
948 }
949
950 /* We can only do the GTT pwrite on untiled buffers, as otherwise
951 * it would end up going through the fenced access, and we'll get
952 * different detiling behavior between reading and writing.
953 * pread/pwrite currently are reading and writing from the CPU
954 * perspective, requiring manual detiling by the client.
955 */
Dave Airlie71acb5e2008-12-30 20:31:46 +1000956 if (obj_priv->phys_obj)
957 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
958 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
Chris Wilson9b8c4a02010-05-27 14:21:01 +0100959 dev->gtt_total != 0 &&
960 obj->write_domain != I915_GEM_DOMAIN_CPU) {
Eric Anholt3de09aa2009-03-09 09:42:23 -0700961 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
962 if (ret == -EFAULT) {
963 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
964 file_priv);
965 }
Eric Anholt280b7132009-03-12 16:56:27 -0700966 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
967 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
Eric Anholt40123c12009-03-09 13:42:30 -0700968 } else {
969 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
970 if (ret == -EFAULT) {
971 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
972 file_priv);
973 }
974 }
Eric Anholt673a3942008-07-30 12:06:12 -0700975
976#if WATCH_PWRITE
977 if (ret)
978 DRM_INFO("pwrite failed %d\n", ret);
979#endif
980
Luca Barbieribc9025b2010-02-09 05:49:12 +0000981 drm_gem_object_unreference_unlocked(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700982
983 return ret;
984}
985
986/**
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800987 * Called when user space prepares to use an object with the CPU, either
988 * through the mmap ioctl's mapping or a GTT mapping.
Eric Anholt673a3942008-07-30 12:06:12 -0700989 */
990int
991i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
992 struct drm_file *file_priv)
993{
Eric Anholta09ba7f2009-08-29 12:49:51 -0700994 struct drm_i915_private *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -0700995 struct drm_i915_gem_set_domain *args = data;
996 struct drm_gem_object *obj;
Jesse Barnes652c3932009-08-17 13:31:43 -0700997 struct drm_i915_gem_object *obj_priv;
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800998 uint32_t read_domains = args->read_domains;
999 uint32_t write_domain = args->write_domain;
Eric Anholt673a3942008-07-30 12:06:12 -07001000 int ret;
1001
1002 if (!(dev->driver->driver_features & DRIVER_GEM))
1003 return -ENODEV;
1004
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001005 /* Only handle setting domains to types used by the CPU. */
Chris Wilson21d509e2009-06-06 09:46:02 +01001006 if (write_domain & I915_GEM_GPU_DOMAINS)
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001007 return -EINVAL;
1008
Chris Wilson21d509e2009-06-06 09:46:02 +01001009 if (read_domains & I915_GEM_GPU_DOMAINS)
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001010 return -EINVAL;
1011
1012 /* Having something in the write domain implies it's in the read
1013 * domain, and only that read domain. Enforce that in the request.
1014 */
1015 if (write_domain != 0 && read_domains != write_domain)
1016 return -EINVAL;
1017
Eric Anholt673a3942008-07-30 12:06:12 -07001018 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1019 if (obj == NULL)
Chris Wilsonbf79cb92010-08-04 14:19:46 +01001020 return -ENOENT;
Daniel Vetter23010e42010-03-08 13:35:02 +01001021 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001022
1023 mutex_lock(&dev->struct_mutex);
Jesse Barnes652c3932009-08-17 13:31:43 -07001024
1025 intel_mark_busy(dev, obj);
1026
Eric Anholt673a3942008-07-30 12:06:12 -07001027#if WATCH_BUF
Krzysztof Halasacfd43c02009-06-20 00:31:28 +02001028 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001029 obj, obj->size, read_domains, write_domain);
Eric Anholt673a3942008-07-30 12:06:12 -07001030#endif
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001031 if (read_domains & I915_GEM_DOMAIN_GTT) {
1032 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
Eric Anholt02354392008-11-26 13:58:13 -08001033
Eric Anholta09ba7f2009-08-29 12:49:51 -07001034 /* Update the LRU on the fence for the CPU access that's
1035 * about to occur.
1036 */
1037 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
Daniel Vetter007cc8a2010-04-28 11:02:31 +02001038 struct drm_i915_fence_reg *reg =
1039 &dev_priv->fence_regs[obj_priv->fence_reg];
1040 list_move_tail(&reg->lru_list,
Eric Anholta09ba7f2009-08-29 12:49:51 -07001041 &dev_priv->mm.fence_list);
1042 }
1043
Eric Anholt02354392008-11-26 13:58:13 -08001044 /* Silently promote "you're not bound, there was nothing to do"
1045 * to success, since the client was just asking us to
1046 * make sure everything was done.
1047 */
1048 if (ret == -EINVAL)
1049 ret = 0;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001050 } else {
Eric Anholte47c68e2008-11-14 13:35:19 -08001051 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001052 }
1053
Chris Wilson7d1c4802010-08-07 21:45:03 +01001054
1055 /* Maintain LRU order of "inactive" objects */
1056 if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
1057 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1058
Eric Anholt673a3942008-07-30 12:06:12 -07001059 drm_gem_object_unreference(obj);
1060 mutex_unlock(&dev->struct_mutex);
1061 return ret;
1062}
1063
1064/**
1065 * Called when user space has done writes to this buffer
1066 */
1067int
1068i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1069 struct drm_file *file_priv)
1070{
1071 struct drm_i915_gem_sw_finish *args = data;
1072 struct drm_gem_object *obj;
1073 struct drm_i915_gem_object *obj_priv;
1074 int ret = 0;
1075
1076 if (!(dev->driver->driver_features & DRIVER_GEM))
1077 return -ENODEV;
1078
1079 mutex_lock(&dev->struct_mutex);
1080 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1081 if (obj == NULL) {
1082 mutex_unlock(&dev->struct_mutex);
Chris Wilsonbf79cb92010-08-04 14:19:46 +01001083 return -ENOENT;
Eric Anholt673a3942008-07-30 12:06:12 -07001084 }
1085
1086#if WATCH_BUF
Krzysztof Halasacfd43c02009-06-20 00:31:28 +02001087 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
Eric Anholt673a3942008-07-30 12:06:12 -07001088 __func__, args->handle, obj, obj->size);
1089#endif
Daniel Vetter23010e42010-03-08 13:35:02 +01001090 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001091
1092 /* Pinned buffers may be scanout, so flush the cache */
Eric Anholte47c68e2008-11-14 13:35:19 -08001093 if (obj_priv->pin_count)
1094 i915_gem_object_flush_cpu_write_domain(obj);
1095
Eric Anholt673a3942008-07-30 12:06:12 -07001096 drm_gem_object_unreference(obj);
1097 mutex_unlock(&dev->struct_mutex);
1098 return ret;
1099}
1100
1101/**
1102 * Maps the contents of an object, returning the address it is mapped
1103 * into.
1104 *
1105 * While the mapping holds a reference on the contents of the object, it doesn't
1106 * imply a ref on the object itself.
1107 */
1108int
1109i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1110 struct drm_file *file_priv)
1111{
1112 struct drm_i915_gem_mmap *args = data;
1113 struct drm_gem_object *obj;
1114 loff_t offset;
1115 unsigned long addr;
1116
1117 if (!(dev->driver->driver_features & DRIVER_GEM))
1118 return -ENODEV;
1119
1120 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1121 if (obj == NULL)
Chris Wilsonbf79cb92010-08-04 14:19:46 +01001122 return -ENOENT;
Eric Anholt673a3942008-07-30 12:06:12 -07001123
1124 offset = args->offset;
1125
1126 down_write(&current->mm->mmap_sem);
1127 addr = do_mmap(obj->filp, 0, args->size,
1128 PROT_READ | PROT_WRITE, MAP_SHARED,
1129 args->offset);
1130 up_write(&current->mm->mmap_sem);
Luca Barbieribc9025b2010-02-09 05:49:12 +00001131 drm_gem_object_unreference_unlocked(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001132 if (IS_ERR((void *)addr))
1133 return addr;
1134
1135 args->addr_ptr = (uint64_t) addr;
1136
1137 return 0;
1138}
1139
Jesse Barnesde151cf2008-11-12 10:03:55 -08001140/**
1141 * i915_gem_fault - fault a page into the GTT
1142 * vma: VMA in question
1143 * vmf: fault info
1144 *
1145 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1146 * from userspace. The fault handler takes care of binding the object to
1147 * the GTT (if needed), allocating and programming a fence register (again,
1148 * only if needed based on whether the old reg is still valid or the object
1149 * is tiled) and inserting a new PTE into the faulting process.
1150 *
1151 * Note that the faulting process may involve evicting existing objects
1152 * from the GTT and/or fence registers to make room. So performance may
1153 * suffer if the GTT working set is large or there are few fence registers
1154 * left.
1155 */
1156int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1157{
1158 struct drm_gem_object *obj = vma->vm_private_data;
1159 struct drm_device *dev = obj->dev;
Chris Wilson7d1c4802010-08-07 21:45:03 +01001160 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01001161 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001162 pgoff_t page_offset;
1163 unsigned long pfn;
1164 int ret = 0;
Jesse Barnes0f973f22009-01-26 17:10:45 -08001165 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001166
1167 /* We don't use vmf->pgoff since that has the fake offset */
1168 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1169 PAGE_SHIFT;
1170
1171 /* Now bind it into the GTT if needed */
1172 mutex_lock(&dev->struct_mutex);
1173 if (!obj_priv->gtt_space) {
Chris Wilsone67b8ce2009-09-14 16:50:26 +01001174 ret = i915_gem_object_bind_to_gtt(obj, 0);
Chris Wilsonc7150892009-09-23 00:43:56 +01001175 if (ret)
1176 goto unlock;
Kristian Høgsberg07f4f3e2009-05-27 14:37:28 -04001177
Jesse Barnesde151cf2008-11-12 10:03:55 -08001178 ret = i915_gem_object_set_to_gtt_domain(obj, write);
Chris Wilsonc7150892009-09-23 00:43:56 +01001179 if (ret)
1180 goto unlock;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001181 }
1182
1183 /* Need a new fence register? */
Eric Anholta09ba7f2009-08-29 12:49:51 -07001184 if (obj_priv->tiling_mode != I915_TILING_NONE) {
Chris Wilson2cf34d72010-09-14 13:03:28 +01001185 ret = i915_gem_object_get_fence_reg(obj, true);
Chris Wilsonc7150892009-09-23 00:43:56 +01001186 if (ret)
1187 goto unlock;
Eric Anholtd9ddcb92009-01-27 10:33:49 -08001188 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08001189
Chris Wilson7d1c4802010-08-07 21:45:03 +01001190 if (i915_gem_object_is_inactive(obj_priv))
1191 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1192
Jesse Barnesde151cf2008-11-12 10:03:55 -08001193 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1194 page_offset;
1195
1196 /* Finally, remap it using the new GTT offset */
1197 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
Chris Wilsonc7150892009-09-23 00:43:56 +01001198unlock:
Jesse Barnesde151cf2008-11-12 10:03:55 -08001199 mutex_unlock(&dev->struct_mutex);
1200
1201 switch (ret) {
Chris Wilsonc7150892009-09-23 00:43:56 +01001202 case 0:
1203 case -ERESTARTSYS:
1204 return VM_FAULT_NOPAGE;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001205 case -ENOMEM:
1206 case -EAGAIN:
1207 return VM_FAULT_OOM;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001208 default:
Chris Wilsonc7150892009-09-23 00:43:56 +01001209 return VM_FAULT_SIGBUS;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001210 }
1211}
1212
1213/**
1214 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1215 * @obj: obj in question
1216 *
1217 * GEM memory mapping works by handing back to userspace a fake mmap offset
1218 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1219 * up the object based on the offset and sets up the various memory mapping
1220 * structures.
1221 *
1222 * This routine allocates and attaches a fake offset for @obj.
1223 */
1224static int
1225i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1226{
1227 struct drm_device *dev = obj->dev;
1228 struct drm_gem_mm *mm = dev->mm_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01001229 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001230 struct drm_map_list *list;
Benjamin Herrenschmidtf77d3902009-02-02 16:55:46 +11001231 struct drm_local_map *map;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001232 int ret = 0;
1233
1234 /* Set the object up for mmap'ing */
1235 list = &obj->map_list;
Eric Anholt9a298b22009-03-24 12:23:04 -07001236 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001237 if (!list->map)
1238 return -ENOMEM;
1239
1240 map = list->map;
1241 map->type = _DRM_GEM;
1242 map->size = obj->size;
1243 map->handle = obj;
1244
1245 /* Get a DRM GEM mmap offset allocated... */
1246 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1247 obj->size / PAGE_SIZE, 0, 0);
1248 if (!list->file_offset_node) {
1249 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1250 ret = -ENOMEM;
1251 goto out_free_list;
1252 }
1253
1254 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1255 obj->size / PAGE_SIZE, 0);
1256 if (!list->file_offset_node) {
1257 ret = -ENOMEM;
1258 goto out_free_list;
1259 }
1260
1261 list->hash.key = list->file_offset_node->start;
1262 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1263 DRM_ERROR("failed to add to map hash\n");
Chris Wilson5618ca62009-12-02 15:15:30 +00001264 ret = -ENOMEM;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001265 goto out_free_mm;
1266 }
1267
1268 /* By now we should be all set, any drm_mmap request on the offset
1269 * below will get to our mmap & fault handler */
1270 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1271
1272 return 0;
1273
1274out_free_mm:
1275 drm_mm_put_block(list->file_offset_node);
1276out_free_list:
Eric Anholt9a298b22009-03-24 12:23:04 -07001277 kfree(list->map);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001278
1279 return ret;
1280}
1281
Chris Wilson901782b2009-07-10 08:18:50 +01001282/**
1283 * i915_gem_release_mmap - remove physical page mappings
1284 * @obj: obj in question
1285 *
André Goddard Rosaaf901ca2009-11-14 13:09:05 -02001286 * Preserve the reservation of the mmapping with the DRM core code, but
Chris Wilson901782b2009-07-10 08:18:50 +01001287 * relinquish ownership of the pages back to the system.
1288 *
1289 * It is vital that we remove the page mapping if we have mapped a tiled
1290 * object through the GTT and then lose the fence register due to
1291 * resource pressure. Similarly if the object has been moved out of the
1292 * aperture, than pages mapped into userspace must be revoked. Removing the
1293 * mapping will then trigger a page fault on the next user access, allowing
1294 * fixup by i915_gem_fault().
1295 */
Eric Anholtd05ca302009-07-10 13:02:26 -07001296void
Chris Wilson901782b2009-07-10 08:18:50 +01001297i915_gem_release_mmap(struct drm_gem_object *obj)
1298{
1299 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01001300 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Chris Wilson901782b2009-07-10 08:18:50 +01001301
1302 if (dev->dev_mapping)
1303 unmap_mapping_range(dev->dev_mapping,
1304 obj_priv->mmap_offset, obj->size, 1);
1305}
1306
Jesse Barnesab00b3e2009-02-11 14:01:46 -08001307static void
1308i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1309{
1310 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01001311 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesab00b3e2009-02-11 14:01:46 -08001312 struct drm_gem_mm *mm = dev->mm_private;
1313 struct drm_map_list *list;
1314
1315 list = &obj->map_list;
1316 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1317
1318 if (list->file_offset_node) {
1319 drm_mm_put_block(list->file_offset_node);
1320 list->file_offset_node = NULL;
1321 }
1322
1323 if (list->map) {
Eric Anholt9a298b22009-03-24 12:23:04 -07001324 kfree(list->map);
Jesse Barnesab00b3e2009-02-11 14:01:46 -08001325 list->map = NULL;
1326 }
1327
1328 obj_priv->mmap_offset = 0;
1329}
1330
Jesse Barnesde151cf2008-11-12 10:03:55 -08001331/**
1332 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1333 * @obj: object to check
1334 *
1335 * Return the required GTT alignment for an object, taking into account
1336 * potential fence register mapping if needed.
1337 */
1338static uint32_t
1339i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1340{
1341 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01001342 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001343 int start, i;
1344
1345 /*
1346 * Minimum alignment is 4k (GTT page size), but might be greater
1347 * if a fence register is needed for the object.
1348 */
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001349 if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001350 return 4096;
1351
1352 /*
1353 * Previous chips need to be aligned to the size of the smallest
1354 * fence register that can contain the object.
1355 */
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001356 if (INTEL_INFO(dev)->gen == 3)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001357 start = 1024*1024;
1358 else
1359 start = 512*1024;
1360
1361 for (i = start; i < obj->size; i <<= 1)
1362 ;
1363
1364 return i;
1365}
1366
1367/**
1368 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1369 * @dev: DRM device
1370 * @data: GTT mapping ioctl data
1371 * @file_priv: GEM object info
1372 *
1373 * Simply returns the fake offset to userspace so it can mmap it.
1374 * The mmap call will end up in drm_gem_mmap(), which will set things
1375 * up so we can get faults in the handler above.
1376 *
1377 * The fault handler will take care of binding the object into the GTT
1378 * (since it may have been evicted to make room for something), allocating
1379 * a fence register, and mapping the appropriate aperture address into
1380 * userspace.
1381 */
1382int
1383i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1384 struct drm_file *file_priv)
1385{
1386 struct drm_i915_gem_mmap_gtt *args = data;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001387 struct drm_gem_object *obj;
1388 struct drm_i915_gem_object *obj_priv;
1389 int ret;
1390
1391 if (!(dev->driver->driver_features & DRIVER_GEM))
1392 return -ENODEV;
1393
1394 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1395 if (obj == NULL)
Chris Wilsonbf79cb92010-08-04 14:19:46 +01001396 return -ENOENT;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001397
1398 mutex_lock(&dev->struct_mutex);
1399
Daniel Vetter23010e42010-03-08 13:35:02 +01001400 obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001401
Chris Wilsonab182822009-09-22 18:46:17 +01001402 if (obj_priv->madv != I915_MADV_WILLNEED) {
1403 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1404 drm_gem_object_unreference(obj);
1405 mutex_unlock(&dev->struct_mutex);
1406 return -EINVAL;
1407 }
1408
1409
Jesse Barnesde151cf2008-11-12 10:03:55 -08001410 if (!obj_priv->mmap_offset) {
1411 ret = i915_gem_create_mmap_offset(obj);
Chris Wilson13af1062009-02-11 14:26:31 +00001412 if (ret) {
1413 drm_gem_object_unreference(obj);
1414 mutex_unlock(&dev->struct_mutex);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001415 return ret;
Chris Wilson13af1062009-02-11 14:26:31 +00001416 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08001417 }
1418
1419 args->offset = obj_priv->mmap_offset;
1420
Jesse Barnesde151cf2008-11-12 10:03:55 -08001421 /*
1422 * Pull it into the GTT so that we have a page list (makes the
1423 * initial fault faster and any subsequent flushing possible).
1424 */
1425 if (!obj_priv->agp_mem) {
Chris Wilsone67b8ce2009-09-14 16:50:26 +01001426 ret = i915_gem_object_bind_to_gtt(obj, 0);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001427 if (ret) {
1428 drm_gem_object_unreference(obj);
1429 mutex_unlock(&dev->struct_mutex);
1430 return ret;
1431 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08001432 }
1433
1434 drm_gem_object_unreference(obj);
1435 mutex_unlock(&dev->struct_mutex);
1436
1437 return 0;
1438}
1439
Ben Gamari6911a9b2009-04-02 11:24:54 -07001440void
Eric Anholt856fa192009-03-19 14:10:50 -07001441i915_gem_object_put_pages(struct drm_gem_object *obj)
Eric Anholt673a3942008-07-30 12:06:12 -07001442{
Daniel Vetter23010e42010-03-08 13:35:02 +01001443 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001444 int page_count = obj->size / PAGE_SIZE;
1445 int i;
1446
Eric Anholt856fa192009-03-19 14:10:50 -07001447 BUG_ON(obj_priv->pages_refcount == 0);
Chris Wilsonbb6baf72009-09-22 14:24:13 +01001448 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
Eric Anholt856fa192009-03-19 14:10:50 -07001449
1450 if (--obj_priv->pages_refcount != 0)
Eric Anholt673a3942008-07-30 12:06:12 -07001451 return;
1452
Eric Anholt280b7132009-03-12 16:56:27 -07001453 if (obj_priv->tiling_mode != I915_TILING_NONE)
1454 i915_gem_object_save_bit_17_swizzle(obj);
1455
Chris Wilson3ef94da2009-09-14 16:50:29 +01001456 if (obj_priv->madv == I915_MADV_DONTNEED)
Chris Wilson13a05fd2009-09-20 23:03:19 +01001457 obj_priv->dirty = 0;
Chris Wilson3ef94da2009-09-14 16:50:29 +01001458
1459 for (i = 0; i < page_count; i++) {
Chris Wilson3ef94da2009-09-14 16:50:29 +01001460 if (obj_priv->dirty)
1461 set_page_dirty(obj_priv->pages[i]);
1462
1463 if (obj_priv->madv == I915_MADV_WILLNEED)
Eric Anholt856fa192009-03-19 14:10:50 -07001464 mark_page_accessed(obj_priv->pages[i]);
Chris Wilson3ef94da2009-09-14 16:50:29 +01001465
1466 page_cache_release(obj_priv->pages[i]);
1467 }
Eric Anholt673a3942008-07-30 12:06:12 -07001468 obj_priv->dirty = 0;
1469
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07001470 drm_free_large(obj_priv->pages);
Eric Anholt856fa192009-03-19 14:10:50 -07001471 obj_priv->pages = NULL;
Eric Anholt673a3942008-07-30 12:06:12 -07001472}
1473
Daniel Vettere35a41d2010-02-11 22:13:59 +01001474static uint32_t
Daniel Vettera6910432010-02-02 17:08:37 +01001475i915_gem_next_request_seqno(struct drm_device *dev,
1476 struct intel_ring_buffer *ring)
Daniel Vettere35a41d2010-02-11 22:13:59 +01001477{
1478 drm_i915_private_t *dev_priv = dev->dev_private;
1479
Daniel Vettera6910432010-02-02 17:08:37 +01001480 ring->outstanding_lazy_request = true;
1481
Daniel Vettere35a41d2010-02-11 22:13:59 +01001482 return dev_priv->next_seqno;
1483}
1484
Eric Anholt673a3942008-07-30 12:06:12 -07001485static void
Daniel Vetter617dbe22010-02-11 22:16:02 +01001486i915_gem_object_move_to_active(struct drm_gem_object *obj,
Zou Nan hai852835f2010-05-21 09:08:56 +08001487 struct intel_ring_buffer *ring)
Eric Anholt673a3942008-07-30 12:06:12 -07001488{
1489 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01001490 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Daniel Vetter617dbe22010-02-11 22:16:02 +01001491 uint32_t seqno = i915_gem_next_request_seqno(dev, ring);
1492
Zou Nan hai852835f2010-05-21 09:08:56 +08001493 BUG_ON(ring == NULL);
1494 obj_priv->ring = ring;
Eric Anholt673a3942008-07-30 12:06:12 -07001495
1496 /* Add a reference if we're newly entering the active list. */
1497 if (!obj_priv->active) {
1498 drm_gem_object_reference(obj);
1499 obj_priv->active = 1;
1500 }
Daniel Vettere35a41d2010-02-11 22:13:59 +01001501
Eric Anholt673a3942008-07-30 12:06:12 -07001502 /* Move from whatever list we were on to the tail of execution. */
Zou Nan hai852835f2010-05-21 09:08:56 +08001503 list_move_tail(&obj_priv->list, &ring->active_list);
Eric Anholtce44b0e2008-11-06 16:00:31 -08001504 obj_priv->last_rendering_seqno = seqno;
Eric Anholt673a3942008-07-30 12:06:12 -07001505}
1506
Eric Anholtce44b0e2008-11-06 16:00:31 -08001507static void
1508i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1509{
1510 struct drm_device *dev = obj->dev;
1511 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01001512 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholtce44b0e2008-11-06 16:00:31 -08001513
1514 BUG_ON(!obj_priv->active);
1515 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1516 obj_priv->last_rendering_seqno = 0;
1517}
Eric Anholt673a3942008-07-30 12:06:12 -07001518
Chris Wilson963b4832009-09-20 23:03:54 +01001519/* Immediately discard the backing storage */
1520static void
1521i915_gem_object_truncate(struct drm_gem_object *obj)
1522{
Daniel Vetter23010e42010-03-08 13:35:02 +01001523 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Chris Wilsonbb6baf72009-09-22 14:24:13 +01001524 struct inode *inode;
Chris Wilson963b4832009-09-20 23:03:54 +01001525
Chris Wilsonae9fed62010-08-07 11:01:30 +01001526 /* Our goal here is to return as much of the memory as
1527 * is possible back to the system as we are called from OOM.
1528 * To do this we must instruct the shmfs to drop all of its
1529 * backing pages, *now*. Here we mirror the actions taken
1530 * when by shmem_delete_inode() to release the backing store.
1531 */
Chris Wilsonbb6baf72009-09-22 14:24:13 +01001532 inode = obj->filp->f_path.dentry->d_inode;
Chris Wilsonae9fed62010-08-07 11:01:30 +01001533 truncate_inode_pages(inode->i_mapping, 0);
1534 if (inode->i_op->truncate_range)
1535 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
Chris Wilsonbb6baf72009-09-22 14:24:13 +01001536
1537 obj_priv->madv = __I915_MADV_PURGED;
Chris Wilson963b4832009-09-20 23:03:54 +01001538}
1539
1540static inline int
1541i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1542{
1543 return obj_priv->madv == I915_MADV_DONTNEED;
1544}
1545
Eric Anholt673a3942008-07-30 12:06:12 -07001546static void
1547i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1548{
1549 struct drm_device *dev = obj->dev;
1550 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01001551 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001552
1553 i915_verify_inactive(dev, __FILE__, __LINE__);
1554 if (obj_priv->pin_count != 0)
1555 list_del_init(&obj_priv->list);
1556 else
1557 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1558
Daniel Vetter99fcb762010-02-07 16:20:18 +01001559 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1560
Eric Anholtce44b0e2008-11-06 16:00:31 -08001561 obj_priv->last_rendering_seqno = 0;
Zou Nan hai852835f2010-05-21 09:08:56 +08001562 obj_priv->ring = NULL;
Eric Anholt673a3942008-07-30 12:06:12 -07001563 if (obj_priv->active) {
1564 obj_priv->active = 0;
1565 drm_gem_object_unreference(obj);
1566 }
1567 i915_verify_inactive(dev, __FILE__, __LINE__);
1568}
1569
Chris Wilson92204342010-09-18 11:02:01 +01001570static void
Daniel Vetter63560392010-02-19 11:51:59 +01001571i915_gem_process_flushing_list(struct drm_device *dev,
Daniel Vetter8a1a49f2010-02-11 22:29:04 +01001572 uint32_t flush_domains,
Zou Nan hai852835f2010-05-21 09:08:56 +08001573 struct intel_ring_buffer *ring)
Daniel Vetter63560392010-02-19 11:51:59 +01001574{
1575 drm_i915_private_t *dev_priv = dev->dev_private;
1576 struct drm_i915_gem_object *obj_priv, *next;
1577
1578 list_for_each_entry_safe(obj_priv, next,
1579 &dev_priv->mm.gpu_write_list,
1580 gpu_write_list) {
Daniel Vettera8089e82010-04-09 19:05:09 +00001581 struct drm_gem_object *obj = &obj_priv->base;
Daniel Vetter63560392010-02-19 11:51:59 +01001582
Chris Wilson2b6efaa2010-09-14 17:04:02 +01001583 if (obj->write_domain & flush_domains &&
1584 obj_priv->ring == ring) {
Daniel Vetter63560392010-02-19 11:51:59 +01001585 uint32_t old_write_domain = obj->write_domain;
1586
1587 obj->write_domain = 0;
1588 list_del_init(&obj_priv->gpu_write_list);
Daniel Vetter617dbe22010-02-11 22:16:02 +01001589 i915_gem_object_move_to_active(obj, ring);
Daniel Vetter63560392010-02-19 11:51:59 +01001590
1591 /* update the fence lru list */
Daniel Vetter007cc8a2010-04-28 11:02:31 +02001592 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1593 struct drm_i915_fence_reg *reg =
1594 &dev_priv->fence_regs[obj_priv->fence_reg];
1595 list_move_tail(&reg->lru_list,
Daniel Vetter63560392010-02-19 11:51:59 +01001596 &dev_priv->mm.fence_list);
Daniel Vetter007cc8a2010-04-28 11:02:31 +02001597 }
Daniel Vetter63560392010-02-19 11:51:59 +01001598
1599 trace_i915_gem_object_change_domain(obj,
1600 obj->read_domains,
1601 old_write_domain);
1602 }
1603 }
1604}
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001605
Daniel Vetter5a5a0c62009-09-15 22:57:36 +02001606uint32_t
Daniel Vetter8a1a49f2010-02-11 22:29:04 +01001607i915_add_request(struct drm_device *dev,
1608 struct drm_file *file_priv,
Chris Wilson8dc5d142010-08-12 12:36:12 +01001609 struct drm_i915_gem_request *request,
Daniel Vetter8a1a49f2010-02-11 22:29:04 +01001610 struct intel_ring_buffer *ring)
Eric Anholt673a3942008-07-30 12:06:12 -07001611{
1612 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholtb9624422009-06-03 07:27:35 +00001613 struct drm_i915_file_private *i915_file_priv = NULL;
Eric Anholt673a3942008-07-30 12:06:12 -07001614 uint32_t seqno;
1615 int was_empty;
Eric Anholt673a3942008-07-30 12:06:12 -07001616
Eric Anholtb9624422009-06-03 07:27:35 +00001617 if (file_priv != NULL)
1618 i915_file_priv = file_priv->driver_priv;
1619
Chris Wilson8dc5d142010-08-12 12:36:12 +01001620 if (request == NULL) {
1621 request = kzalloc(sizeof(*request), GFP_KERNEL);
1622 if (request == NULL)
1623 return 0;
1624 }
Eric Anholt673a3942008-07-30 12:06:12 -07001625
Daniel Vetter8a1a49f2010-02-11 22:29:04 +01001626 seqno = ring->add_request(dev, ring, file_priv, 0);
Eric Anholt673a3942008-07-30 12:06:12 -07001627
1628 request->seqno = seqno;
Zou Nan hai852835f2010-05-21 09:08:56 +08001629 request->ring = ring;
Eric Anholt673a3942008-07-30 12:06:12 -07001630 request->emitted_jiffies = jiffies;
Zou Nan hai852835f2010-05-21 09:08:56 +08001631 was_empty = list_empty(&ring->request_list);
1632 list_add_tail(&request->list, &ring->request_list);
1633
Eric Anholtb9624422009-06-03 07:27:35 +00001634 if (i915_file_priv) {
1635 list_add_tail(&request->client_list,
1636 &i915_file_priv->mm.request_list);
1637 } else {
1638 INIT_LIST_HEAD(&request->client_list);
1639 }
Eric Anholt673a3942008-07-30 12:06:12 -07001640
Ben Gamarif65d9422009-09-14 17:48:44 -04001641 if (!dev_priv->mm.suspended) {
Chris Wilsonb3b079d2010-09-13 23:44:34 +01001642 mod_timer(&dev_priv->hangcheck_timer,
1643 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
Ben Gamarif65d9422009-09-14 17:48:44 -04001644 if (was_empty)
Chris Wilsonb3b079d2010-09-13 23:44:34 +01001645 queue_delayed_work(dev_priv->wq,
1646 &dev_priv->mm.retire_work, HZ);
Ben Gamarif65d9422009-09-14 17:48:44 -04001647 }
Eric Anholt673a3942008-07-30 12:06:12 -07001648 return seqno;
1649}
1650
1651/**
1652 * Command execution barrier
1653 *
1654 * Ensures that all commands in the ring are finished
1655 * before signalling the CPU
1656 */
Daniel Vetter8a1a49f2010-02-11 22:29:04 +01001657static void
Zou Nan hai852835f2010-05-21 09:08:56 +08001658i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
Eric Anholt673a3942008-07-30 12:06:12 -07001659{
Eric Anholt673a3942008-07-30 12:06:12 -07001660 uint32_t flush_domains = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07001661
1662 /* The sampler always gets flushed on i965 (sigh) */
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001663 if (INTEL_INFO(dev)->gen >= 4)
Eric Anholt673a3942008-07-30 12:06:12 -07001664 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
Zou Nan hai852835f2010-05-21 09:08:56 +08001665
1666 ring->flush(dev, ring,
1667 I915_GEM_DOMAIN_COMMAND, flush_domains);
Eric Anholt673a3942008-07-30 12:06:12 -07001668}
1669
1670/**
Eric Anholt673a3942008-07-30 12:06:12 -07001671 * Returns true if seq1 is later than seq2.
1672 */
Ben Gamari22be1722009-09-14 17:48:43 -04001673bool
Eric Anholt673a3942008-07-30 12:06:12 -07001674i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1675{
1676 return (int32_t)(seq1 - seq2) >= 0;
1677}
1678
1679uint32_t
Zou Nan hai852835f2010-05-21 09:08:56 +08001680i915_get_gem_seqno(struct drm_device *dev,
Zou Nan haid1b851f2010-05-21 09:08:57 +08001681 struct intel_ring_buffer *ring)
Eric Anholt673a3942008-07-30 12:06:12 -07001682{
Zou Nan hai852835f2010-05-21 09:08:56 +08001683 return ring->get_gem_seqno(dev, ring);
Eric Anholt673a3942008-07-30 12:06:12 -07001684}
1685
Chris Wilson9375e442010-09-19 12:21:28 +01001686void i915_gem_reset_flushing_list(struct drm_device *dev)
1687{
1688 struct drm_i915_private *dev_priv = dev->dev_private;
1689
1690 while (!list_empty(&dev_priv->mm.flushing_list)) {
1691 struct drm_i915_gem_object *obj_priv;
1692
1693 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1694 struct drm_i915_gem_object,
1695 list);
1696
1697 obj_priv->base.write_domain = 0;
1698 i915_gem_object_move_to_inactive(&obj_priv->base);
1699 }
1700}
1701
Chris Wilson77f01232010-09-19 12:31:36 +01001702void i915_gem_reset_inactive_gpu_domains(struct drm_device *dev)
1703{
1704 struct drm_i915_private *dev_priv = dev->dev_private;
1705 struct drm_i915_gem_object *obj_priv;
1706
1707 list_for_each_entry(obj_priv,
1708 &dev_priv->mm.inactive_list,
1709 list)
1710 {
1711 obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1712 }
1713}
1714
Eric Anholt673a3942008-07-30 12:06:12 -07001715/**
1716 * This function clears the request list as sequence numbers are passed.
1717 */
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01001718static void
1719i915_gem_retire_requests_ring(struct drm_device *dev,
1720 struct intel_ring_buffer *ring)
Eric Anholt673a3942008-07-30 12:06:12 -07001721{
1722 drm_i915_private_t *dev_priv = dev->dev_private;
1723 uint32_t seqno;
Chris Wilsonb84d5f02010-09-18 01:38:04 +01001724 bool wedged;
Eric Anholt673a3942008-07-30 12:06:12 -07001725
Chris Wilsonb84d5f02010-09-18 01:38:04 +01001726 if (!ring->status_page.page_addr ||
1727 list_empty(&ring->request_list))
Karsten Wiese6c0594a2009-02-23 15:07:57 +01001728 return;
1729
Zou Nan hai852835f2010-05-21 09:08:56 +08001730 seqno = i915_get_gem_seqno(dev, ring);
Chris Wilsonb84d5f02010-09-18 01:38:04 +01001731 wedged = atomic_read(&dev_priv->mm.wedged);
Eric Anholt673a3942008-07-30 12:06:12 -07001732
Zou Nan hai852835f2010-05-21 09:08:56 +08001733 while (!list_empty(&ring->request_list)) {
Eric Anholt673a3942008-07-30 12:06:12 -07001734 struct drm_i915_gem_request *request;
Eric Anholt673a3942008-07-30 12:06:12 -07001735
Zou Nan hai852835f2010-05-21 09:08:56 +08001736 request = list_first_entry(&ring->request_list,
Eric Anholt673a3942008-07-30 12:06:12 -07001737 struct drm_i915_gem_request,
1738 list);
Eric Anholt673a3942008-07-30 12:06:12 -07001739
Chris Wilsonb84d5f02010-09-18 01:38:04 +01001740 if (!wedged && !i915_seqno_passed(seqno, request->seqno))
Eric Anholt673a3942008-07-30 12:06:12 -07001741 break;
Chris Wilsonb84d5f02010-09-18 01:38:04 +01001742
1743 trace_i915_gem_request_retire(dev, request->seqno);
1744
1745 list_del(&request->list);
1746 list_del(&request->client_list);
1747 kfree(request);
1748 }
1749
1750 /* Move any buffers on the active list that are no longer referenced
1751 * by the ringbuffer to the flushing/inactive lists as appropriate.
1752 */
1753 while (!list_empty(&ring->active_list)) {
1754 struct drm_gem_object *obj;
1755 struct drm_i915_gem_object *obj_priv;
1756
1757 obj_priv = list_first_entry(&ring->active_list,
1758 struct drm_i915_gem_object,
1759 list);
1760
1761 if (!wedged &&
1762 !i915_seqno_passed(seqno, obj_priv->last_rendering_seqno))
1763 break;
1764
1765 obj = &obj_priv->base;
1766
1767#if WATCH_LRU
1768 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1769 __func__, request->seqno, obj);
1770#endif
1771
1772 if (obj->write_domain != 0)
1773 i915_gem_object_move_to_flushing(obj);
1774 else
1775 i915_gem_object_move_to_inactive(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001776 }
Chris Wilson9d34e5d2009-09-24 05:26:06 +01001777
1778 if (unlikely (dev_priv->trace_irq_seqno &&
1779 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001780 ring->user_irq_put(dev, ring);
Chris Wilson9d34e5d2009-09-24 05:26:06 +01001781 dev_priv->trace_irq_seqno = 0;
1782 }
Eric Anholt673a3942008-07-30 12:06:12 -07001783}
1784
1785void
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01001786i915_gem_retire_requests(struct drm_device *dev)
1787{
1788 drm_i915_private_t *dev_priv = dev->dev_private;
1789
Chris Wilsonbe726152010-07-23 23:18:50 +01001790 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1791 struct drm_i915_gem_object *obj_priv, *tmp;
1792
1793 /* We must be careful that during unbind() we do not
1794 * accidentally infinitely recurse into retire requests.
1795 * Currently:
1796 * retire -> free -> unbind -> wait -> retire_ring
1797 */
1798 list_for_each_entry_safe(obj_priv, tmp,
1799 &dev_priv->mm.deferred_free_list,
1800 list)
1801 i915_gem_free_object_tail(&obj_priv->base);
1802 }
1803
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01001804 i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1805 if (HAS_BSD(dev))
1806 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1807}
1808
Daniel Vetter75ef9da2010-08-21 00:25:16 +02001809static void
Eric Anholt673a3942008-07-30 12:06:12 -07001810i915_gem_retire_work_handler(struct work_struct *work)
1811{
1812 drm_i915_private_t *dev_priv;
1813 struct drm_device *dev;
1814
1815 dev_priv = container_of(work, drm_i915_private_t,
1816 mm.retire_work.work);
1817 dev = dev_priv->dev;
1818
1819 mutex_lock(&dev->struct_mutex);
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01001820 i915_gem_retire_requests(dev);
Zou Nan haid1b851f2010-05-21 09:08:57 +08001821
Keith Packard6dbe2772008-10-14 21:41:13 -07001822 if (!dev_priv->mm.suspended &&
Zou Nan haid1b851f2010-05-21 09:08:57 +08001823 (!list_empty(&dev_priv->render_ring.request_list) ||
1824 (HAS_BSD(dev) &&
1825 !list_empty(&dev_priv->bsd_ring.request_list))))
Eric Anholt9c9fe1f2009-08-03 16:09:16 -07001826 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
Eric Anholt673a3942008-07-30 12:06:12 -07001827 mutex_unlock(&dev->struct_mutex);
1828}
1829
Daniel Vetter5a5a0c62009-09-15 22:57:36 +02001830int
Zou Nan hai852835f2010-05-21 09:08:56 +08001831i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
Daniel Vetter8a1a49f2010-02-11 22:29:04 +01001832 bool interruptible, struct intel_ring_buffer *ring)
Eric Anholt673a3942008-07-30 12:06:12 -07001833{
1834 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes802c7eb2009-05-05 16:03:48 -07001835 u32 ier;
Eric Anholt673a3942008-07-30 12:06:12 -07001836 int ret = 0;
1837
1838 BUG_ON(seqno == 0);
1839
Daniel Vettere35a41d2010-02-11 22:13:59 +01001840 if (seqno == dev_priv->next_seqno) {
Chris Wilson8dc5d142010-08-12 12:36:12 +01001841 seqno = i915_add_request(dev, NULL, NULL, ring);
Daniel Vettere35a41d2010-02-11 22:13:59 +01001842 if (seqno == 0)
1843 return -ENOMEM;
1844 }
1845
Ben Gamariba1234d2009-09-14 17:48:47 -04001846 if (atomic_read(&dev_priv->mm.wedged))
Ben Gamariffed1d02009-09-14 17:48:41 -04001847 return -EIO;
1848
Zou Nan hai852835f2010-05-21 09:08:56 +08001849 if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
Eric Anholtbad720f2009-10-22 16:11:14 -07001850 if (HAS_PCH_SPLIT(dev))
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001851 ier = I915_READ(DEIER) | I915_READ(GTIER);
1852 else
1853 ier = I915_READ(IER);
Jesse Barnes802c7eb2009-05-05 16:03:48 -07001854 if (!ier) {
1855 DRM_ERROR("something (likely vbetool) disabled "
1856 "interrupts, re-enabling\n");
1857 i915_driver_irq_preinstall(dev);
1858 i915_driver_irq_postinstall(dev);
1859 }
1860
Chris Wilson1c5d22f2009-08-25 11:15:50 +01001861 trace_i915_gem_request_wait_begin(dev, seqno);
1862
Zou Nan hai852835f2010-05-21 09:08:56 +08001863 ring->waiting_gem_seqno = seqno;
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001864 ring->user_irq_get(dev, ring);
Daniel Vetter48764bf2009-09-15 22:57:32 +02001865 if (interruptible)
Zou Nan hai852835f2010-05-21 09:08:56 +08001866 ret = wait_event_interruptible(ring->irq_queue,
1867 i915_seqno_passed(
1868 ring->get_gem_seqno(dev, ring), seqno)
1869 || atomic_read(&dev_priv->mm.wedged));
Daniel Vetter48764bf2009-09-15 22:57:32 +02001870 else
Zou Nan hai852835f2010-05-21 09:08:56 +08001871 wait_event(ring->irq_queue,
1872 i915_seqno_passed(
1873 ring->get_gem_seqno(dev, ring), seqno)
1874 || atomic_read(&dev_priv->mm.wedged));
Daniel Vetter48764bf2009-09-15 22:57:32 +02001875
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001876 ring->user_irq_put(dev, ring);
Zou Nan hai852835f2010-05-21 09:08:56 +08001877 ring->waiting_gem_seqno = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01001878
1879 trace_i915_gem_request_wait_end(dev, seqno);
Eric Anholt673a3942008-07-30 12:06:12 -07001880 }
Ben Gamariba1234d2009-09-14 17:48:47 -04001881 if (atomic_read(&dev_priv->mm.wedged))
Eric Anholt673a3942008-07-30 12:06:12 -07001882 ret = -EIO;
1883
1884 if (ret && ret != -ERESTARTSYS)
Daniel Vetter8bff9172010-02-11 22:19:40 +01001885 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
1886 __func__, ret, seqno, ring->get_gem_seqno(dev, ring),
1887 dev_priv->next_seqno);
Eric Anholt673a3942008-07-30 12:06:12 -07001888
1889 /* Directly dispatch request retiring. While we have the work queue
1890 * to handle this, the waiter on a request often wants an associated
1891 * buffer to have made it to the inactive list, and we would need
1892 * a separate wait queue to handle that.
1893 */
1894 if (ret == 0)
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01001895 i915_gem_retire_requests_ring(dev, ring);
Eric Anholt673a3942008-07-30 12:06:12 -07001896
1897 return ret;
1898}
1899
Daniel Vetter48764bf2009-09-15 22:57:32 +02001900/**
1901 * Waits for a sequence number to be signaled, and cleans up the
1902 * request and object lists appropriately for that event.
1903 */
1904static int
Zou Nan hai852835f2010-05-21 09:08:56 +08001905i915_wait_request(struct drm_device *dev, uint32_t seqno,
1906 struct intel_ring_buffer *ring)
Daniel Vetter48764bf2009-09-15 22:57:32 +02001907{
Zou Nan hai852835f2010-05-21 09:08:56 +08001908 return i915_do_wait_request(dev, seqno, 1, ring);
Daniel Vetter48764bf2009-09-15 22:57:32 +02001909}
1910
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001911static void
Chris Wilson92204342010-09-18 11:02:01 +01001912i915_gem_flush_ring(struct drm_device *dev,
1913 struct intel_ring_buffer *ring,
1914 uint32_t invalidate_domains,
1915 uint32_t flush_domains)
1916{
1917 ring->flush(dev, ring, invalidate_domains, flush_domains);
1918 i915_gem_process_flushing_list(dev, flush_domains, ring);
1919}
1920
1921static void
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001922i915_gem_flush(struct drm_device *dev,
1923 uint32_t invalidate_domains,
Chris Wilson92204342010-09-18 11:02:01 +01001924 uint32_t flush_domains,
1925 uint32_t flush_rings)
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001926{
1927 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter8bff9172010-02-11 22:19:40 +01001928
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001929 if (flush_domains & I915_GEM_DOMAIN_CPU)
1930 drm_agp_chipset_flush(dev);
Daniel Vetter8bff9172010-02-11 22:19:40 +01001931
Chris Wilson92204342010-09-18 11:02:01 +01001932 if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
1933 if (flush_rings & RING_RENDER)
1934 i915_gem_flush_ring(dev,
1935 &dev_priv->render_ring,
1936 invalidate_domains, flush_domains);
1937 if (flush_rings & RING_BSD)
1938 i915_gem_flush_ring(dev,
1939 &dev_priv->bsd_ring,
1940 invalidate_domains, flush_domains);
1941 }
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001942}
1943
Eric Anholt673a3942008-07-30 12:06:12 -07001944/**
1945 * Ensures that all rendering to the object has completed and the object is
1946 * safe to unbind from the GTT or access from the CPU.
1947 */
1948static int
Chris Wilson2cf34d72010-09-14 13:03:28 +01001949i915_gem_object_wait_rendering(struct drm_gem_object *obj,
1950 bool interruptible)
Eric Anholt673a3942008-07-30 12:06:12 -07001951{
1952 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01001953 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001954 int ret;
1955
Eric Anholte47c68e2008-11-14 13:35:19 -08001956 /* This function only exists to support waiting for existing rendering,
1957 * not for emitting required flushes.
Eric Anholt673a3942008-07-30 12:06:12 -07001958 */
Eric Anholte47c68e2008-11-14 13:35:19 -08001959 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
Eric Anholt673a3942008-07-30 12:06:12 -07001960
1961 /* If there is rendering queued on the buffer being evicted, wait for
1962 * it.
1963 */
1964 if (obj_priv->active) {
1965#if WATCH_BUF
1966 DRM_INFO("%s: object %p wait for seqno %08x\n",
1967 __func__, obj, obj_priv->last_rendering_seqno);
1968#endif
Chris Wilson2cf34d72010-09-14 13:03:28 +01001969 ret = i915_do_wait_request(dev,
1970 obj_priv->last_rendering_seqno,
1971 interruptible,
1972 obj_priv->ring);
1973 if (ret)
Eric Anholt673a3942008-07-30 12:06:12 -07001974 return ret;
1975 }
1976
1977 return 0;
1978}
1979
1980/**
1981 * Unbinds an object from the GTT aperture.
1982 */
Jesse Barnes0f973f22009-01-26 17:10:45 -08001983int
Eric Anholt673a3942008-07-30 12:06:12 -07001984i915_gem_object_unbind(struct drm_gem_object *obj)
1985{
1986 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01001987 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001988 int ret = 0;
1989
1990#if WATCH_BUF
1991 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1992 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1993#endif
1994 if (obj_priv->gtt_space == NULL)
1995 return 0;
1996
1997 if (obj_priv->pin_count != 0) {
1998 DRM_ERROR("Attempting to unbind pinned buffer\n");
1999 return -EINVAL;
2000 }
2001
Eric Anholt5323fd02009-09-09 11:50:45 -07002002 /* blow away mappings if mapped through GTT */
2003 i915_gem_release_mmap(obj);
2004
Eric Anholt673a3942008-07-30 12:06:12 -07002005 /* Move the object to the CPU domain to ensure that
2006 * any possible CPU writes while it's not in the GTT
2007 * are flushed when we go to remap it. This will
2008 * also ensure that all pending GPU writes are finished
2009 * before we unbind.
2010 */
Eric Anholte47c68e2008-11-14 13:35:19 -08002011 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
Chris Wilson8dc17752010-07-23 23:18:51 +01002012 if (ret == -ERESTARTSYS)
Eric Anholt673a3942008-07-30 12:06:12 -07002013 return ret;
Chris Wilson8dc17752010-07-23 23:18:51 +01002014 /* Continue on if we fail due to EIO, the GPU is hung so we
2015 * should be safe and we need to cleanup or else we might
2016 * cause memory corruption through use-after-free.
2017 */
Eric Anholt673a3942008-07-30 12:06:12 -07002018
Daniel Vetter96b47b62009-12-15 17:50:00 +01002019 /* release the fence reg _after_ flushing */
2020 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2021 i915_gem_clear_fence_reg(obj);
2022
Eric Anholt673a3942008-07-30 12:06:12 -07002023 if (obj_priv->agp_mem != NULL) {
2024 drm_unbind_agp(obj_priv->agp_mem);
2025 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2026 obj_priv->agp_mem = NULL;
2027 }
2028
Eric Anholt856fa192009-03-19 14:10:50 -07002029 i915_gem_object_put_pages(obj);
Chris Wilsona32808c2009-09-20 21:29:47 +01002030 BUG_ON(obj_priv->pages_refcount);
Eric Anholt673a3942008-07-30 12:06:12 -07002031
2032 if (obj_priv->gtt_space) {
2033 atomic_dec(&dev->gtt_count);
2034 atomic_sub(obj->size, &dev->gtt_memory);
2035
2036 drm_mm_put_block(obj_priv->gtt_space);
2037 obj_priv->gtt_space = NULL;
2038 }
2039
2040 /* Remove ourselves from the LRU list if present. */
2041 if (!list_empty(&obj_priv->list))
2042 list_del_init(&obj_priv->list);
2043
Chris Wilson963b4832009-09-20 23:03:54 +01002044 if (i915_gem_object_is_purgeable(obj_priv))
2045 i915_gem_object_truncate(obj);
2046
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002047 trace_i915_gem_object_unbind(obj);
2048
Chris Wilson8dc17752010-07-23 23:18:51 +01002049 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -07002050}
2051
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01002052int
Daniel Vetter4df2faf2010-02-19 11:52:00 +01002053i915_gpu_idle(struct drm_device *dev)
2054{
2055 drm_i915_private_t *dev_priv = dev->dev_private;
2056 bool lists_empty;
Zou Nan hai852835f2010-05-21 09:08:56 +08002057 int ret;
Daniel Vetter4df2faf2010-02-19 11:52:00 +01002058
Zou Nan haid1b851f2010-05-21 09:08:57 +08002059 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2060 list_empty(&dev_priv->render_ring.active_list) &&
2061 (!HAS_BSD(dev) ||
2062 list_empty(&dev_priv->bsd_ring.active_list)));
Daniel Vetter4df2faf2010-02-19 11:52:00 +01002063 if (lists_empty)
2064 return 0;
2065
2066 /* Flush everything onto the inactive list. */
Chris Wilson92204342010-09-18 11:02:01 +01002067 i915_gem_flush_ring(dev,
2068 &dev_priv->render_ring,
2069 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
Daniel Vetter4fc6ee72010-02-11 22:53:20 +01002070
2071 ret = i915_wait_request(dev,
2072 i915_gem_next_request_seqno(dev, &dev_priv->render_ring),
2073 &dev_priv->render_ring);
Daniel Vetter8a1a49f2010-02-11 22:29:04 +01002074 if (ret)
2075 return ret;
Zou Nan haid1b851f2010-05-21 09:08:57 +08002076
2077 if (HAS_BSD(dev)) {
Chris Wilson92204342010-09-18 11:02:01 +01002078 i915_gem_flush_ring(dev,
2079 &dev_priv->bsd_ring,
2080 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2081
Daniel Vetter4fc6ee72010-02-11 22:53:20 +01002082 ret = i915_wait_request(dev,
2083 i915_gem_next_request_seqno(dev, &dev_priv->bsd_ring),
2084 &dev_priv->bsd_ring);
Zou Nan haid1b851f2010-05-21 09:08:57 +08002085 if (ret)
2086 return ret;
2087 }
2088
Daniel Vetter8a1a49f2010-02-11 22:29:04 +01002089 return 0;
Daniel Vetter4df2faf2010-02-19 11:52:00 +01002090}
2091
Ben Gamari6911a9b2009-04-02 11:24:54 -07002092int
Chris Wilson4bdadb92010-01-27 13:36:32 +00002093i915_gem_object_get_pages(struct drm_gem_object *obj,
2094 gfp_t gfpmask)
Eric Anholt673a3942008-07-30 12:06:12 -07002095{
Daniel Vetter23010e42010-03-08 13:35:02 +01002096 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002097 int page_count, i;
2098 struct address_space *mapping;
2099 struct inode *inode;
2100 struct page *page;
Eric Anholt673a3942008-07-30 12:06:12 -07002101
Daniel Vetter778c3542010-05-13 11:49:44 +02002102 BUG_ON(obj_priv->pages_refcount
2103 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2104
Eric Anholt856fa192009-03-19 14:10:50 -07002105 if (obj_priv->pages_refcount++ != 0)
Eric Anholt673a3942008-07-30 12:06:12 -07002106 return 0;
2107
2108 /* Get the list of pages out of our struct file. They'll be pinned
2109 * at this point until we release them.
2110 */
2111 page_count = obj->size / PAGE_SIZE;
Eric Anholt856fa192009-03-19 14:10:50 -07002112 BUG_ON(obj_priv->pages != NULL);
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07002113 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
Eric Anholt856fa192009-03-19 14:10:50 -07002114 if (obj_priv->pages == NULL) {
Eric Anholt856fa192009-03-19 14:10:50 -07002115 obj_priv->pages_refcount--;
Eric Anholt673a3942008-07-30 12:06:12 -07002116 return -ENOMEM;
2117 }
2118
2119 inode = obj->filp->f_path.dentry->d_inode;
2120 mapping = inode->i_mapping;
2121 for (i = 0; i < page_count; i++) {
Chris Wilson4bdadb92010-01-27 13:36:32 +00002122 page = read_cache_page_gfp(mapping, i,
Linus Torvalds985b8232010-07-02 10:04:42 +10002123 GFP_HIGHUSER |
Chris Wilson4bdadb92010-01-27 13:36:32 +00002124 __GFP_COLD |
Linus Torvaldscd9f0402010-07-18 09:44:37 -07002125 __GFP_RECLAIMABLE |
Chris Wilson4bdadb92010-01-27 13:36:32 +00002126 gfpmask);
Chris Wilson1f2b1012010-03-12 19:52:55 +00002127 if (IS_ERR(page))
2128 goto err_pages;
2129
Eric Anholt856fa192009-03-19 14:10:50 -07002130 obj_priv->pages[i] = page;
Eric Anholt673a3942008-07-30 12:06:12 -07002131 }
Eric Anholt280b7132009-03-12 16:56:27 -07002132
2133 if (obj_priv->tiling_mode != I915_TILING_NONE)
2134 i915_gem_object_do_bit_17_swizzle(obj);
2135
Eric Anholt673a3942008-07-30 12:06:12 -07002136 return 0;
Chris Wilson1f2b1012010-03-12 19:52:55 +00002137
2138err_pages:
2139 while (i--)
2140 page_cache_release(obj_priv->pages[i]);
2141
2142 drm_free_large(obj_priv->pages);
2143 obj_priv->pages = NULL;
2144 obj_priv->pages_refcount--;
2145 return PTR_ERR(page);
Eric Anholt673a3942008-07-30 12:06:12 -07002146}
2147
Eric Anholt4e901fd2009-10-26 16:44:17 -07002148static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2149{
2150 struct drm_gem_object *obj = reg->obj;
2151 struct drm_device *dev = obj->dev;
2152 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002153 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt4e901fd2009-10-26 16:44:17 -07002154 int regnum = obj_priv->fence_reg;
2155 uint64_t val;
2156
2157 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2158 0xfffff000) << 32;
2159 val |= obj_priv->gtt_offset & 0xfffff000;
2160 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2161 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2162
2163 if (obj_priv->tiling_mode == I915_TILING_Y)
2164 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2165 val |= I965_FENCE_REG_VALID;
2166
2167 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2168}
2169
Jesse Barnesde151cf2008-11-12 10:03:55 -08002170static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2171{
2172 struct drm_gem_object *obj = reg->obj;
2173 struct drm_device *dev = obj->dev;
2174 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002175 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002176 int regnum = obj_priv->fence_reg;
2177 uint64_t val;
2178
2179 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2180 0xfffff000) << 32;
2181 val |= obj_priv->gtt_offset & 0xfffff000;
2182 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2183 if (obj_priv->tiling_mode == I915_TILING_Y)
2184 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2185 val |= I965_FENCE_REG_VALID;
2186
2187 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2188}
2189
2190static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2191{
2192 struct drm_gem_object *obj = reg->obj;
2193 struct drm_device *dev = obj->dev;
2194 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002195 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002196 int regnum = obj_priv->fence_reg;
Jesse Barnes0f973f22009-01-26 17:10:45 -08002197 int tile_width;
Eric Anholtdc529a42009-03-10 22:34:49 -07002198 uint32_t fence_reg, val;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002199 uint32_t pitch_val;
2200
2201 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2202 (obj_priv->gtt_offset & (obj->size - 1))) {
Linus Torvaldsf06da262009-02-09 08:57:29 -08002203 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
Jesse Barnes0f973f22009-01-26 17:10:45 -08002204 __func__, obj_priv->gtt_offset, obj->size);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002205 return;
2206 }
2207
Jesse Barnes0f973f22009-01-26 17:10:45 -08002208 if (obj_priv->tiling_mode == I915_TILING_Y &&
2209 HAS_128_BYTE_Y_TILING(dev))
2210 tile_width = 128;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002211 else
Jesse Barnes0f973f22009-01-26 17:10:45 -08002212 tile_width = 512;
2213
2214 /* Note: pitch better be a power of two tile widths */
2215 pitch_val = obj_priv->stride / tile_width;
2216 pitch_val = ffs(pitch_val) - 1;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002217
Daniel Vetterc36a2a62010-04-17 15:12:03 +02002218 if (obj_priv->tiling_mode == I915_TILING_Y &&
2219 HAS_128_BYTE_Y_TILING(dev))
2220 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2221 else
2222 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2223
Jesse Barnesde151cf2008-11-12 10:03:55 -08002224 val = obj_priv->gtt_offset;
2225 if (obj_priv->tiling_mode == I915_TILING_Y)
2226 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2227 val |= I915_FENCE_SIZE_BITS(obj->size);
2228 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2229 val |= I830_FENCE_REG_VALID;
2230
Eric Anholtdc529a42009-03-10 22:34:49 -07002231 if (regnum < 8)
2232 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2233 else
2234 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2235 I915_WRITE(fence_reg, val);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002236}
2237
2238static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2239{
2240 struct drm_gem_object *obj = reg->obj;
2241 struct drm_device *dev = obj->dev;
2242 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002243 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002244 int regnum = obj_priv->fence_reg;
2245 uint32_t val;
2246 uint32_t pitch_val;
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002247 uint32_t fence_size_bits;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002248
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002249 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
Jesse Barnesde151cf2008-11-12 10:03:55 -08002250 (obj_priv->gtt_offset & (obj->size - 1))) {
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002251 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
Jesse Barnes0f973f22009-01-26 17:10:45 -08002252 __func__, obj_priv->gtt_offset);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002253 return;
2254 }
2255
Eric Anholte76a16d2009-05-26 17:44:56 -07002256 pitch_val = obj_priv->stride / 128;
2257 pitch_val = ffs(pitch_val) - 1;
2258 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2259
Jesse Barnesde151cf2008-11-12 10:03:55 -08002260 val = obj_priv->gtt_offset;
2261 if (obj_priv->tiling_mode == I915_TILING_Y)
2262 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002263 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2264 WARN_ON(fence_size_bits & ~0x00000f00);
2265 val |= fence_size_bits;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002266 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2267 val |= I830_FENCE_REG_VALID;
2268
2269 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002270}
2271
Chris Wilson2cf34d72010-09-14 13:03:28 +01002272static int i915_find_fence_reg(struct drm_device *dev,
2273 bool interruptible)
Daniel Vetterae3db242010-02-19 11:51:58 +01002274{
2275 struct drm_i915_fence_reg *reg = NULL;
2276 struct drm_i915_gem_object *obj_priv = NULL;
2277 struct drm_i915_private *dev_priv = dev->dev_private;
2278 struct drm_gem_object *obj = NULL;
2279 int i, avail, ret;
2280
2281 /* First try to find a free reg */
2282 avail = 0;
2283 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2284 reg = &dev_priv->fence_regs[i];
2285 if (!reg->obj)
2286 return i;
2287
Daniel Vetter23010e42010-03-08 13:35:02 +01002288 obj_priv = to_intel_bo(reg->obj);
Daniel Vetterae3db242010-02-19 11:51:58 +01002289 if (!obj_priv->pin_count)
2290 avail++;
2291 }
2292
2293 if (avail == 0)
2294 return -ENOSPC;
2295
2296 /* None available, try to steal one or wait for a user to finish */
2297 i = I915_FENCE_REG_NONE;
Daniel Vetter007cc8a2010-04-28 11:02:31 +02002298 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2299 lru_list) {
2300 obj = reg->obj;
2301 obj_priv = to_intel_bo(obj);
Daniel Vetterae3db242010-02-19 11:51:58 +01002302
2303 if (obj_priv->pin_count)
2304 continue;
2305
2306 /* found one! */
2307 i = obj_priv->fence_reg;
2308 break;
2309 }
2310
2311 BUG_ON(i == I915_FENCE_REG_NONE);
2312
2313 /* We only have a reference on obj from the active list. put_fence_reg
2314 * might drop that one, causing a use-after-free in it. So hold a
2315 * private reference to obj like the other callers of put_fence_reg
2316 * (set_tiling ioctl) do. */
2317 drm_gem_object_reference(obj);
Chris Wilson2cf34d72010-09-14 13:03:28 +01002318 ret = i915_gem_object_put_fence_reg(obj, interruptible);
Daniel Vetterae3db242010-02-19 11:51:58 +01002319 drm_gem_object_unreference(obj);
2320 if (ret != 0)
2321 return ret;
2322
2323 return i;
2324}
2325
Jesse Barnesde151cf2008-11-12 10:03:55 -08002326/**
2327 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2328 * @obj: object to map through a fence reg
2329 *
2330 * When mapping objects through the GTT, userspace wants to be able to write
2331 * to them without having to worry about swizzling if the object is tiled.
2332 *
2333 * This function walks the fence regs looking for a free one for @obj,
2334 * stealing one if it can't find any.
2335 *
2336 * It then sets up the reg based on the object's properties: address, pitch
2337 * and tiling format.
2338 */
Chris Wilson8c4b8c32009-06-17 22:08:52 +01002339int
Chris Wilson2cf34d72010-09-14 13:03:28 +01002340i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
2341 bool interruptible)
Jesse Barnesde151cf2008-11-12 10:03:55 -08002342{
2343 struct drm_device *dev = obj->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08002344 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002345 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002346 struct drm_i915_fence_reg *reg = NULL;
Daniel Vetterae3db242010-02-19 11:51:58 +01002347 int ret;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002348
Eric Anholta09ba7f2009-08-29 12:49:51 -07002349 /* Just update our place in the LRU if our fence is getting used. */
2350 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
Daniel Vetter007cc8a2010-04-28 11:02:31 +02002351 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2352 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
Eric Anholta09ba7f2009-08-29 12:49:51 -07002353 return 0;
2354 }
2355
Jesse Barnesde151cf2008-11-12 10:03:55 -08002356 switch (obj_priv->tiling_mode) {
2357 case I915_TILING_NONE:
2358 WARN(1, "allocating a fence for non-tiled object?\n");
2359 break;
2360 case I915_TILING_X:
Jesse Barnes0f973f22009-01-26 17:10:45 -08002361 if (!obj_priv->stride)
2362 return -EINVAL;
2363 WARN((obj_priv->stride & (512 - 1)),
2364 "object 0x%08x is X tiled but has non-512B pitch\n",
2365 obj_priv->gtt_offset);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002366 break;
2367 case I915_TILING_Y:
Jesse Barnes0f973f22009-01-26 17:10:45 -08002368 if (!obj_priv->stride)
2369 return -EINVAL;
2370 WARN((obj_priv->stride & (128 - 1)),
2371 "object 0x%08x is Y tiled but has non-128B pitch\n",
2372 obj_priv->gtt_offset);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002373 break;
2374 }
2375
Chris Wilson2cf34d72010-09-14 13:03:28 +01002376 ret = i915_find_fence_reg(dev, interruptible);
Daniel Vetterae3db242010-02-19 11:51:58 +01002377 if (ret < 0)
2378 return ret;
Chris Wilsonfc7170b2009-02-11 14:26:46 +00002379
Daniel Vetterae3db242010-02-19 11:51:58 +01002380 obj_priv->fence_reg = ret;
2381 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
Daniel Vetter007cc8a2010-04-28 11:02:31 +02002382 list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
Eric Anholta09ba7f2009-08-29 12:49:51 -07002383
Jesse Barnesde151cf2008-11-12 10:03:55 -08002384 reg->obj = obj;
2385
Chris Wilsone259bef2010-09-17 00:32:02 +01002386 switch (INTEL_INFO(dev)->gen) {
2387 case 6:
Eric Anholt4e901fd2009-10-26 16:44:17 -07002388 sandybridge_write_fence_reg(reg);
Chris Wilsone259bef2010-09-17 00:32:02 +01002389 break;
2390 case 5:
2391 case 4:
Jesse Barnesde151cf2008-11-12 10:03:55 -08002392 i965_write_fence_reg(reg);
Chris Wilsone259bef2010-09-17 00:32:02 +01002393 break;
2394 case 3:
Jesse Barnesde151cf2008-11-12 10:03:55 -08002395 i915_write_fence_reg(reg);
Chris Wilsone259bef2010-09-17 00:32:02 +01002396 break;
2397 case 2:
Jesse Barnesde151cf2008-11-12 10:03:55 -08002398 i830_write_fence_reg(reg);
Chris Wilsone259bef2010-09-17 00:32:02 +01002399 break;
2400 }
Eric Anholtd9ddcb92009-01-27 10:33:49 -08002401
Daniel Vetterae3db242010-02-19 11:51:58 +01002402 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2403 obj_priv->tiling_mode);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002404
Eric Anholtd9ddcb92009-01-27 10:33:49 -08002405 return 0;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002406}
2407
2408/**
2409 * i915_gem_clear_fence_reg - clear out fence register info
2410 * @obj: object to clear
2411 *
2412 * Zeroes out the fence register itself and clears out the associated
2413 * data structures in dev_priv and obj_priv.
2414 */
2415static void
2416i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2417{
2418 struct drm_device *dev = obj->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08002419 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002420 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Daniel Vetter007cc8a2010-04-28 11:02:31 +02002421 struct drm_i915_fence_reg *reg =
2422 &dev_priv->fence_regs[obj_priv->fence_reg];
Chris Wilsone259bef2010-09-17 00:32:02 +01002423 uint32_t fence_reg;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002424
Chris Wilsone259bef2010-09-17 00:32:02 +01002425 switch (INTEL_INFO(dev)->gen) {
2426 case 6:
Eric Anholt4e901fd2009-10-26 16:44:17 -07002427 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2428 (obj_priv->fence_reg * 8), 0);
Chris Wilsone259bef2010-09-17 00:32:02 +01002429 break;
2430 case 5:
2431 case 4:
Jesse Barnesde151cf2008-11-12 10:03:55 -08002432 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
Chris Wilsone259bef2010-09-17 00:32:02 +01002433 break;
2434 case 3:
2435 if (obj_priv->fence_reg > 8)
2436 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
Eric Anholtdc529a42009-03-10 22:34:49 -07002437 else
Chris Wilsone259bef2010-09-17 00:32:02 +01002438 case 2:
2439 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
Eric Anholtdc529a42009-03-10 22:34:49 -07002440
2441 I915_WRITE(fence_reg, 0);
Chris Wilsone259bef2010-09-17 00:32:02 +01002442 break;
Eric Anholtdc529a42009-03-10 22:34:49 -07002443 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08002444
Daniel Vetter007cc8a2010-04-28 11:02:31 +02002445 reg->obj = NULL;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002446 obj_priv->fence_reg = I915_FENCE_REG_NONE;
Daniel Vetter007cc8a2010-04-28 11:02:31 +02002447 list_del_init(&reg->lru_list);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002448}
2449
Eric Anholt673a3942008-07-30 12:06:12 -07002450/**
Chris Wilson52dc7d32009-06-06 09:46:01 +01002451 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2452 * to the buffer to finish, and then resets the fence register.
2453 * @obj: tiled object holding a fence register.
Chris Wilson2cf34d72010-09-14 13:03:28 +01002454 * @bool: whether the wait upon the fence is interruptible
Chris Wilson52dc7d32009-06-06 09:46:01 +01002455 *
2456 * Zeroes out the fence register itself and clears out the associated
2457 * data structures in dev_priv and obj_priv.
2458 */
2459int
Chris Wilson2cf34d72010-09-14 13:03:28 +01002460i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
2461 bool interruptible)
Chris Wilson52dc7d32009-06-06 09:46:01 +01002462{
2463 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01002464 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Chris Wilson52dc7d32009-06-06 09:46:01 +01002465
2466 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2467 return 0;
2468
Daniel Vetter10ae9bd2010-02-01 13:59:17 +01002469 /* If we've changed tiling, GTT-mappings of the object
2470 * need to re-fault to ensure that the correct fence register
2471 * setup is in place.
2472 */
2473 i915_gem_release_mmap(obj);
2474
Chris Wilson52dc7d32009-06-06 09:46:01 +01002475 /* On the i915, GPU access to tiled buffers is via a fence,
2476 * therefore we must wait for any outstanding access to complete
2477 * before clearing the fence.
2478 */
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002479 if (INTEL_INFO(dev)->gen < 4) {
Chris Wilson52dc7d32009-06-06 09:46:01 +01002480 int ret;
2481
Chris Wilson2cf34d72010-09-14 13:03:28 +01002482 ret = i915_gem_object_flush_gpu_write_domain(obj, true);
Chris Wilson0bc23aa2010-09-14 10:22:23 +01002483 if (ret)
2484 return ret;
2485
Chris Wilson2cf34d72010-09-14 13:03:28 +01002486 ret = i915_gem_object_wait_rendering(obj, interruptible);
Chris Wilson0bc23aa2010-09-14 10:22:23 +01002487 if (ret)
Chris Wilson52dc7d32009-06-06 09:46:01 +01002488 return ret;
2489 }
2490
Daniel Vetter4a726612010-02-01 13:59:16 +01002491 i915_gem_object_flush_gtt_write_domain(obj);
Chris Wilson0bc23aa2010-09-14 10:22:23 +01002492 i915_gem_clear_fence_reg(obj);
Chris Wilson52dc7d32009-06-06 09:46:01 +01002493
2494 return 0;
2495}
2496
2497/**
Eric Anholt673a3942008-07-30 12:06:12 -07002498 * Finds free space in the GTT aperture and binds the object there.
2499 */
2500static int
2501i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2502{
2503 struct drm_device *dev = obj->dev;
2504 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002505 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002506 struct drm_mm_node *free_space;
Chris Wilson4bdadb92010-01-27 13:36:32 +00002507 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
Chris Wilson07f73f62009-09-14 16:50:30 +01002508 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07002509
Chris Wilsonbb6baf72009-09-22 14:24:13 +01002510 if (obj_priv->madv != I915_MADV_WILLNEED) {
Chris Wilson3ef94da2009-09-14 16:50:29 +01002511 DRM_ERROR("Attempting to bind a purgeable object\n");
2512 return -EINVAL;
2513 }
2514
Eric Anholt673a3942008-07-30 12:06:12 -07002515 if (alignment == 0)
Jesse Barnes0f973f22009-01-26 17:10:45 -08002516 alignment = i915_gem_get_gtt_alignment(obj);
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002517 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
Eric Anholt673a3942008-07-30 12:06:12 -07002518 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2519 return -EINVAL;
2520 }
2521
Chris Wilson654fc602010-05-27 13:18:21 +01002522 /* If the object is bigger than the entire aperture, reject it early
2523 * before evicting everything in a vain attempt to find space.
2524 */
2525 if (obj->size > dev->gtt_total) {
2526 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2527 return -E2BIG;
2528 }
2529
Eric Anholt673a3942008-07-30 12:06:12 -07002530 search_free:
2531 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2532 obj->size, alignment, 0);
2533 if (free_space != NULL) {
2534 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2535 alignment);
Daniel Vetterdb3307a2010-07-02 15:02:12 +01002536 if (obj_priv->gtt_space != NULL)
Eric Anholt673a3942008-07-30 12:06:12 -07002537 obj_priv->gtt_offset = obj_priv->gtt_space->start;
Eric Anholt673a3942008-07-30 12:06:12 -07002538 }
2539 if (obj_priv->gtt_space == NULL) {
2540 /* If the gtt is empty and we're still having trouble
2541 * fitting our object in, we're out of memory.
2542 */
2543#if WATCH_LRU
2544 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2545#endif
Daniel Vetter0108a3e2010-08-07 11:01:21 +01002546 ret = i915_gem_evict_something(dev, obj->size, alignment);
Chris Wilson97311292009-09-21 00:22:34 +01002547 if (ret)
Eric Anholt673a3942008-07-30 12:06:12 -07002548 return ret;
Chris Wilson97311292009-09-21 00:22:34 +01002549
Eric Anholt673a3942008-07-30 12:06:12 -07002550 goto search_free;
2551 }
2552
2553#if WATCH_BUF
Krzysztof Halasacfd43c02009-06-20 00:31:28 +02002554 DRM_INFO("Binding object of size %zd at 0x%08x\n",
Eric Anholt673a3942008-07-30 12:06:12 -07002555 obj->size, obj_priv->gtt_offset);
2556#endif
Chris Wilson4bdadb92010-01-27 13:36:32 +00002557 ret = i915_gem_object_get_pages(obj, gfpmask);
Eric Anholt673a3942008-07-30 12:06:12 -07002558 if (ret) {
2559 drm_mm_put_block(obj_priv->gtt_space);
2560 obj_priv->gtt_space = NULL;
Chris Wilson07f73f62009-09-14 16:50:30 +01002561
2562 if (ret == -ENOMEM) {
2563 /* first try to clear up some space from the GTT */
Daniel Vetter0108a3e2010-08-07 11:01:21 +01002564 ret = i915_gem_evict_something(dev, obj->size,
2565 alignment);
Chris Wilson07f73f62009-09-14 16:50:30 +01002566 if (ret) {
Chris Wilson07f73f62009-09-14 16:50:30 +01002567 /* now try to shrink everyone else */
Chris Wilson4bdadb92010-01-27 13:36:32 +00002568 if (gfpmask) {
2569 gfpmask = 0;
2570 goto search_free;
Chris Wilson07f73f62009-09-14 16:50:30 +01002571 }
2572
2573 return ret;
2574 }
2575
2576 goto search_free;
2577 }
2578
Eric Anholt673a3942008-07-30 12:06:12 -07002579 return ret;
2580 }
2581
Eric Anholt673a3942008-07-30 12:06:12 -07002582 /* Create an AGP memory structure pointing at our pages, and bind it
2583 * into the GTT.
2584 */
2585 obj_priv->agp_mem = drm_agp_bind_pages(dev,
Eric Anholt856fa192009-03-19 14:10:50 -07002586 obj_priv->pages,
Chris Wilson07f73f62009-09-14 16:50:30 +01002587 obj->size >> PAGE_SHIFT,
Keith Packardba1eb1d2008-10-14 19:55:10 -07002588 obj_priv->gtt_offset,
2589 obj_priv->agp_type);
Eric Anholt673a3942008-07-30 12:06:12 -07002590 if (obj_priv->agp_mem == NULL) {
Eric Anholt856fa192009-03-19 14:10:50 -07002591 i915_gem_object_put_pages(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002592 drm_mm_put_block(obj_priv->gtt_space);
2593 obj_priv->gtt_space = NULL;
Chris Wilson07f73f62009-09-14 16:50:30 +01002594
Daniel Vetter0108a3e2010-08-07 11:01:21 +01002595 ret = i915_gem_evict_something(dev, obj->size, alignment);
Chris Wilson97311292009-09-21 00:22:34 +01002596 if (ret)
Chris Wilson07f73f62009-09-14 16:50:30 +01002597 return ret;
Chris Wilson07f73f62009-09-14 16:50:30 +01002598
2599 goto search_free;
Eric Anholt673a3942008-07-30 12:06:12 -07002600 }
2601 atomic_inc(&dev->gtt_count);
2602 atomic_add(obj->size, &dev->gtt_memory);
2603
Chris Wilsonbf1a1092010-08-07 11:01:20 +01002604 /* keep track of bounds object by adding it to the inactive list */
2605 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
2606
Eric Anholt673a3942008-07-30 12:06:12 -07002607 /* Assert that the object is not currently in any GPU domain. As it
2608 * wasn't in the GTT, there shouldn't be any way it could have been in
2609 * a GPU cache
2610 */
Chris Wilson21d509e2009-06-06 09:46:02 +01002611 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2612 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
Eric Anholt673a3942008-07-30 12:06:12 -07002613
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002614 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2615
Eric Anholt673a3942008-07-30 12:06:12 -07002616 return 0;
2617}
2618
2619void
2620i915_gem_clflush_object(struct drm_gem_object *obj)
2621{
Daniel Vetter23010e42010-03-08 13:35:02 +01002622 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002623
2624 /* If we don't have a page list set up, then we're not pinned
2625 * to GPU, and we can ignore the cache flush because it'll happen
2626 * again at bind time.
2627 */
Eric Anholt856fa192009-03-19 14:10:50 -07002628 if (obj_priv->pages == NULL)
Eric Anholt673a3942008-07-30 12:06:12 -07002629 return;
2630
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002631 trace_i915_gem_object_clflush(obj);
Eric Anholtcfa16a02009-05-26 18:46:16 -07002632
Eric Anholt856fa192009-03-19 14:10:50 -07002633 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
Eric Anholt673a3942008-07-30 12:06:12 -07002634}
2635
Eric Anholte47c68e2008-11-14 13:35:19 -08002636/** Flushes any GPU write domain for the object if it's dirty. */
Chris Wilson2dafb1e2010-06-07 14:03:05 +01002637static int
Daniel Vetterba3d8d72010-02-11 22:37:04 +01002638i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
2639 bool pipelined)
Eric Anholte47c68e2008-11-14 13:35:19 -08002640{
2641 struct drm_device *dev = obj->dev;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002642 uint32_t old_write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002643
2644 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
Chris Wilson2dafb1e2010-06-07 14:03:05 +01002645 return 0;
Eric Anholte47c68e2008-11-14 13:35:19 -08002646
2647 /* Queue the GPU write cache flushing we need. */
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002648 old_write_domain = obj->write_domain;
Chris Wilson92204342010-09-18 11:02:01 +01002649 i915_gem_flush_ring(dev,
2650 to_intel_bo(obj)->ring,
2651 0, obj->write_domain);
Chris Wilson48b956c2010-09-14 12:50:34 +01002652 BUG_ON(obj->write_domain);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002653
2654 trace_i915_gem_object_change_domain(obj,
2655 obj->read_domains,
2656 old_write_domain);
Daniel Vetterba3d8d72010-02-11 22:37:04 +01002657
2658 if (pipelined)
2659 return 0;
2660
Chris Wilson2cf34d72010-09-14 13:03:28 +01002661 return i915_gem_object_wait_rendering(obj, true);
Eric Anholte47c68e2008-11-14 13:35:19 -08002662}
2663
2664/** Flushes the GTT write domain for the object if it's dirty. */
2665static void
2666i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2667{
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002668 uint32_t old_write_domain;
2669
Eric Anholte47c68e2008-11-14 13:35:19 -08002670 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2671 return;
2672
2673 /* No actual flushing is required for the GTT write domain. Writes
2674 * to it immediately go to main memory as far as we know, so there's
2675 * no chipset flush. It also doesn't land in render cache.
2676 */
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002677 old_write_domain = obj->write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002678 obj->write_domain = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002679
2680 trace_i915_gem_object_change_domain(obj,
2681 obj->read_domains,
2682 old_write_domain);
Eric Anholte47c68e2008-11-14 13:35:19 -08002683}
2684
2685/** Flushes the CPU write domain for the object if it's dirty. */
2686static void
2687i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2688{
2689 struct drm_device *dev = obj->dev;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002690 uint32_t old_write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002691
2692 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2693 return;
2694
2695 i915_gem_clflush_object(obj);
2696 drm_agp_chipset_flush(dev);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002697 old_write_domain = obj->write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002698 obj->write_domain = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002699
2700 trace_i915_gem_object_change_domain(obj,
2701 obj->read_domains,
2702 old_write_domain);
Eric Anholte47c68e2008-11-14 13:35:19 -08002703}
2704
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002705/**
2706 * Moves a single object to the GTT read, and possibly write domain.
2707 *
2708 * This function returns when the move is complete, including waiting on
2709 * flushes to occur.
2710 */
Jesse Barnes79e53942008-11-07 14:24:08 -08002711int
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002712i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2713{
Daniel Vetter23010e42010-03-08 13:35:02 +01002714 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002715 uint32_t old_write_domain, old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08002716 int ret;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002717
Eric Anholt02354392008-11-26 13:58:13 -08002718 /* Not valid to be called on unbound objects. */
2719 if (obj_priv->gtt_space == NULL)
2720 return -EINVAL;
2721
Daniel Vetterba3d8d72010-02-11 22:37:04 +01002722 ret = i915_gem_object_flush_gpu_write_domain(obj, false);
Eric Anholte47c68e2008-11-14 13:35:19 -08002723 if (ret != 0)
2724 return ret;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002725
Chris Wilson72133422010-09-13 23:56:38 +01002726 i915_gem_object_flush_cpu_write_domain(obj);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002727
Daniel Vetterba3d8d72010-02-11 22:37:04 +01002728 if (write) {
Chris Wilson2cf34d72010-09-14 13:03:28 +01002729 ret = i915_gem_object_wait_rendering(obj, true);
Daniel Vetterba3d8d72010-02-11 22:37:04 +01002730 if (ret)
2731 return ret;
Daniel Vetterba3d8d72010-02-11 22:37:04 +01002732 }
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002733
Chris Wilson72133422010-09-13 23:56:38 +01002734 old_write_domain = obj->write_domain;
2735 old_read_domains = obj->read_domains;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002736
2737 /* It should now be out of any other write domains, and we can update
2738 * the domain values for our changes.
2739 */
2740 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2741 obj->read_domains |= I915_GEM_DOMAIN_GTT;
Eric Anholte47c68e2008-11-14 13:35:19 -08002742 if (write) {
Chris Wilson72133422010-09-13 23:56:38 +01002743 obj->read_domains = I915_GEM_DOMAIN_GTT;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002744 obj->write_domain = I915_GEM_DOMAIN_GTT;
Eric Anholte47c68e2008-11-14 13:35:19 -08002745 obj_priv->dirty = 1;
2746 }
2747
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002748 trace_i915_gem_object_change_domain(obj,
2749 old_read_domains,
2750 old_write_domain);
2751
Eric Anholte47c68e2008-11-14 13:35:19 -08002752 return 0;
2753}
2754
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002755/*
2756 * Prepare buffer for display plane. Use uninterruptible for possible flush
2757 * wait, as in modesetting process we're not supposed to be interrupted.
2758 */
2759int
Chris Wilson48b956c2010-09-14 12:50:34 +01002760i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
2761 bool pipelined)
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002762{
Daniel Vetter23010e42010-03-08 13:35:02 +01002763 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Daniel Vetterba3d8d72010-02-11 22:37:04 +01002764 uint32_t old_read_domains;
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002765 int ret;
2766
2767 /* Not valid to be called on unbound objects. */
2768 if (obj_priv->gtt_space == NULL)
2769 return -EINVAL;
2770
Chris Wilson48b956c2010-09-14 12:50:34 +01002771 ret = i915_gem_object_flush_gpu_write_domain(obj, pipelined);
2772 if (ret)
Daniel Vettere35a41d2010-02-11 22:13:59 +01002773 return ret;
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002774
Chris Wilsonb118c1e2010-05-27 13:18:14 +01002775 i915_gem_object_flush_cpu_write_domain(obj);
2776
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002777 old_read_domains = obj->read_domains;
Chris Wilsonb118c1e2010-05-27 13:18:14 +01002778 obj->read_domains = I915_GEM_DOMAIN_GTT;
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002779
2780 trace_i915_gem_object_change_domain(obj,
2781 old_read_domains,
Daniel Vetterba3d8d72010-02-11 22:37:04 +01002782 obj->write_domain);
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002783
2784 return 0;
2785}
2786
Eric Anholte47c68e2008-11-14 13:35:19 -08002787/**
2788 * Moves a single object to the CPU read, and possibly write domain.
2789 *
2790 * This function returns when the move is complete, including waiting on
2791 * flushes to occur.
2792 */
2793static int
2794i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2795{
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002796 uint32_t old_write_domain, old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08002797 int ret;
2798
Daniel Vetterba3d8d72010-02-11 22:37:04 +01002799 ret = i915_gem_object_flush_gpu_write_domain(obj, false);
Eric Anholte47c68e2008-11-14 13:35:19 -08002800 if (ret != 0)
2801 return ret;
2802
2803 i915_gem_object_flush_gtt_write_domain(obj);
2804
2805 /* If we have a partially-valid cache of the object in the CPU,
2806 * finish invalidating it and free the per-page flags.
2807 */
2808 i915_gem_object_set_to_full_cpu_read_domain(obj);
2809
Chris Wilson72133422010-09-13 23:56:38 +01002810 if (write) {
Chris Wilson2cf34d72010-09-14 13:03:28 +01002811 ret = i915_gem_object_wait_rendering(obj, true);
Chris Wilson72133422010-09-13 23:56:38 +01002812 if (ret)
2813 return ret;
2814 }
2815
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002816 old_write_domain = obj->write_domain;
2817 old_read_domains = obj->read_domains;
2818
Eric Anholte47c68e2008-11-14 13:35:19 -08002819 /* Flush the CPU cache if it's still invalid. */
2820 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2821 i915_gem_clflush_object(obj);
Eric Anholte47c68e2008-11-14 13:35:19 -08002822
2823 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2824 }
2825
2826 /* It should now be out of any other write domains, and we can update
2827 * the domain values for our changes.
2828 */
2829 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2830
2831 /* If we're writing through the CPU, then the GPU read domains will
2832 * need to be invalidated at next use.
2833 */
2834 if (write) {
2835 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2836 obj->write_domain = I915_GEM_DOMAIN_CPU;
2837 }
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002838
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002839 trace_i915_gem_object_change_domain(obj,
2840 old_read_domains,
2841 old_write_domain);
2842
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002843 return 0;
2844}
2845
Eric Anholt673a3942008-07-30 12:06:12 -07002846/*
2847 * Set the next domain for the specified object. This
2848 * may not actually perform the necessary flushing/invaliding though,
2849 * as that may want to be batched with other set_domain operations
2850 *
2851 * This is (we hope) the only really tricky part of gem. The goal
2852 * is fairly simple -- track which caches hold bits of the object
2853 * and make sure they remain coherent. A few concrete examples may
2854 * help to explain how it works. For shorthand, we use the notation
2855 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2856 * a pair of read and write domain masks.
2857 *
2858 * Case 1: the batch buffer
2859 *
2860 * 1. Allocated
2861 * 2. Written by CPU
2862 * 3. Mapped to GTT
2863 * 4. Read by GPU
2864 * 5. Unmapped from GTT
2865 * 6. Freed
2866 *
2867 * Let's take these a step at a time
2868 *
2869 * 1. Allocated
2870 * Pages allocated from the kernel may still have
2871 * cache contents, so we set them to (CPU, CPU) always.
2872 * 2. Written by CPU (using pwrite)
2873 * The pwrite function calls set_domain (CPU, CPU) and
2874 * this function does nothing (as nothing changes)
2875 * 3. Mapped by GTT
2876 * This function asserts that the object is not
2877 * currently in any GPU-based read or write domains
2878 * 4. Read by GPU
2879 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2880 * As write_domain is zero, this function adds in the
2881 * current read domains (CPU+COMMAND, 0).
2882 * flush_domains is set to CPU.
2883 * invalidate_domains is set to COMMAND
2884 * clflush is run to get data out of the CPU caches
2885 * then i915_dev_set_domain calls i915_gem_flush to
2886 * emit an MI_FLUSH and drm_agp_chipset_flush
2887 * 5. Unmapped from GTT
2888 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2889 * flush_domains and invalidate_domains end up both zero
2890 * so no flushing/invalidating happens
2891 * 6. Freed
2892 * yay, done
2893 *
2894 * Case 2: The shared render buffer
2895 *
2896 * 1. Allocated
2897 * 2. Mapped to GTT
2898 * 3. Read/written by GPU
2899 * 4. set_domain to (CPU,CPU)
2900 * 5. Read/written by CPU
2901 * 6. Read/written by GPU
2902 *
2903 * 1. Allocated
2904 * Same as last example, (CPU, CPU)
2905 * 2. Mapped to GTT
2906 * Nothing changes (assertions find that it is not in the GPU)
2907 * 3. Read/written by GPU
2908 * execbuffer calls set_domain (RENDER, RENDER)
2909 * flush_domains gets CPU
2910 * invalidate_domains gets GPU
2911 * clflush (obj)
2912 * MI_FLUSH and drm_agp_chipset_flush
2913 * 4. set_domain (CPU, CPU)
2914 * flush_domains gets GPU
2915 * invalidate_domains gets CPU
2916 * wait_rendering (obj) to make sure all drawing is complete.
2917 * This will include an MI_FLUSH to get the data from GPU
2918 * to memory
2919 * clflush (obj) to invalidate the CPU cache
2920 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2921 * 5. Read/written by CPU
2922 * cache lines are loaded and dirtied
2923 * 6. Read written by GPU
2924 * Same as last GPU access
2925 *
2926 * Case 3: The constant buffer
2927 *
2928 * 1. Allocated
2929 * 2. Written by CPU
2930 * 3. Read by GPU
2931 * 4. Updated (written) by CPU again
2932 * 5. Read by GPU
2933 *
2934 * 1. Allocated
2935 * (CPU, CPU)
2936 * 2. Written by CPU
2937 * (CPU, CPU)
2938 * 3. Read by GPU
2939 * (CPU+RENDER, 0)
2940 * flush_domains = CPU
2941 * invalidate_domains = RENDER
2942 * clflush (obj)
2943 * MI_FLUSH
2944 * drm_agp_chipset_flush
2945 * 4. Updated (written) by CPU again
2946 * (CPU, CPU)
2947 * flush_domains = 0 (no previous write domain)
2948 * invalidate_domains = 0 (no new read domains)
2949 * 5. Read by GPU
2950 * (CPU+RENDER, 0)
2951 * flush_domains = CPU
2952 * invalidate_domains = RENDER
2953 * clflush (obj)
2954 * MI_FLUSH
2955 * drm_agp_chipset_flush
2956 */
Keith Packardc0d90822008-11-20 23:11:08 -08002957static void
Eric Anholt8b0e3782009-02-19 14:40:50 -08002958i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
Eric Anholt673a3942008-07-30 12:06:12 -07002959{
2960 struct drm_device *dev = obj->dev;
Chris Wilson92204342010-09-18 11:02:01 +01002961 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002962 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002963 uint32_t invalidate_domains = 0;
2964 uint32_t flush_domains = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002965 uint32_t old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08002966
Eric Anholt8b0e3782009-02-19 14:40:50 -08002967 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2968 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
Eric Anholt673a3942008-07-30 12:06:12 -07002969
Jesse Barnes652c3932009-08-17 13:31:43 -07002970 intel_mark_busy(dev, obj);
2971
Eric Anholt673a3942008-07-30 12:06:12 -07002972#if WATCH_BUF
2973 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2974 __func__, obj,
Eric Anholt8b0e3782009-02-19 14:40:50 -08002975 obj->read_domains, obj->pending_read_domains,
2976 obj->write_domain, obj->pending_write_domain);
Eric Anholt673a3942008-07-30 12:06:12 -07002977#endif
2978 /*
2979 * If the object isn't moving to a new write domain,
2980 * let the object stay in multiple read domains
2981 */
Eric Anholt8b0e3782009-02-19 14:40:50 -08002982 if (obj->pending_write_domain == 0)
2983 obj->pending_read_domains |= obj->read_domains;
Eric Anholt673a3942008-07-30 12:06:12 -07002984 else
2985 obj_priv->dirty = 1;
2986
2987 /*
2988 * Flush the current write domain if
2989 * the new read domains don't match. Invalidate
2990 * any read domains which differ from the old
2991 * write domain
2992 */
Eric Anholt8b0e3782009-02-19 14:40:50 -08002993 if (obj->write_domain &&
2994 obj->write_domain != obj->pending_read_domains) {
Eric Anholt673a3942008-07-30 12:06:12 -07002995 flush_domains |= obj->write_domain;
Eric Anholt8b0e3782009-02-19 14:40:50 -08002996 invalidate_domains |=
2997 obj->pending_read_domains & ~obj->write_domain;
Eric Anholt673a3942008-07-30 12:06:12 -07002998 }
2999 /*
3000 * Invalidate any read caches which may have
3001 * stale data. That is, any new read domains.
3002 */
Eric Anholt8b0e3782009-02-19 14:40:50 -08003003 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
Eric Anholt673a3942008-07-30 12:06:12 -07003004 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3005#if WATCH_BUF
3006 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3007 __func__, flush_domains, invalidate_domains);
3008#endif
Eric Anholt673a3942008-07-30 12:06:12 -07003009 i915_gem_clflush_object(obj);
3010 }
3011
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003012 old_read_domains = obj->read_domains;
3013
Eric Anholtefbeed92009-02-19 14:54:51 -08003014 /* The actual obj->write_domain will be updated with
3015 * pending_write_domain after we emit the accumulated flush for all
3016 * of our domain changes in execbuffers (which clears objects'
3017 * write_domains). So if we have a current write domain that we
3018 * aren't changing, set pending_write_domain to that.
3019 */
3020 if (flush_domains == 0 && obj->pending_write_domain == 0)
3021 obj->pending_write_domain = obj->write_domain;
Eric Anholt8b0e3782009-02-19 14:40:50 -08003022 obj->read_domains = obj->pending_read_domains;
Eric Anholt673a3942008-07-30 12:06:12 -07003023
3024 dev->invalidate_domains |= invalidate_domains;
3025 dev->flush_domains |= flush_domains;
Chris Wilson92204342010-09-18 11:02:01 +01003026 if (obj_priv->ring)
3027 dev_priv->mm.flush_rings |= obj_priv->ring->id;
Eric Anholt673a3942008-07-30 12:06:12 -07003028#if WATCH_BUF
3029 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3030 __func__,
3031 obj->read_domains, obj->write_domain,
3032 dev->invalidate_domains, dev->flush_domains);
3033#endif
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003034
3035 trace_i915_gem_object_change_domain(obj,
3036 old_read_domains,
3037 obj->write_domain);
Eric Anholt673a3942008-07-30 12:06:12 -07003038}
3039
3040/**
Eric Anholte47c68e2008-11-14 13:35:19 -08003041 * Moves the object from a partially CPU read to a full one.
Eric Anholt673a3942008-07-30 12:06:12 -07003042 *
Eric Anholte47c68e2008-11-14 13:35:19 -08003043 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3044 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3045 */
3046static void
3047i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3048{
Daniel Vetter23010e42010-03-08 13:35:02 +01003049 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholte47c68e2008-11-14 13:35:19 -08003050
3051 if (!obj_priv->page_cpu_valid)
3052 return;
3053
3054 /* If we're partially in the CPU read domain, finish moving it in.
3055 */
3056 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3057 int i;
3058
3059 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3060 if (obj_priv->page_cpu_valid[i])
3061 continue;
Eric Anholt856fa192009-03-19 14:10:50 -07003062 drm_clflush_pages(obj_priv->pages + i, 1);
Eric Anholte47c68e2008-11-14 13:35:19 -08003063 }
Eric Anholte47c68e2008-11-14 13:35:19 -08003064 }
3065
3066 /* Free the page_cpu_valid mappings which are now stale, whether
3067 * or not we've got I915_GEM_DOMAIN_CPU.
3068 */
Eric Anholt9a298b22009-03-24 12:23:04 -07003069 kfree(obj_priv->page_cpu_valid);
Eric Anholte47c68e2008-11-14 13:35:19 -08003070 obj_priv->page_cpu_valid = NULL;
3071}
3072
3073/**
3074 * Set the CPU read domain on a range of the object.
3075 *
3076 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3077 * not entirely valid. The page_cpu_valid member of the object flags which
3078 * pages have been flushed, and will be respected by
3079 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3080 * of the whole object.
3081 *
3082 * This function returns when the move is complete, including waiting on
3083 * flushes to occur.
Eric Anholt673a3942008-07-30 12:06:12 -07003084 */
3085static int
Eric Anholte47c68e2008-11-14 13:35:19 -08003086i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3087 uint64_t offset, uint64_t size)
Eric Anholt673a3942008-07-30 12:06:12 -07003088{
Daniel Vetter23010e42010-03-08 13:35:02 +01003089 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003090 uint32_t old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08003091 int i, ret;
Eric Anholt673a3942008-07-30 12:06:12 -07003092
Eric Anholte47c68e2008-11-14 13:35:19 -08003093 if (offset == 0 && size == obj->size)
3094 return i915_gem_object_set_to_cpu_domain(obj, 0);
3095
Daniel Vetterba3d8d72010-02-11 22:37:04 +01003096 ret = i915_gem_object_flush_gpu_write_domain(obj, false);
Eric Anholte47c68e2008-11-14 13:35:19 -08003097 if (ret != 0)
3098 return ret;
3099 i915_gem_object_flush_gtt_write_domain(obj);
3100
3101 /* If we're already fully in the CPU read domain, we're done. */
3102 if (obj_priv->page_cpu_valid == NULL &&
3103 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
Eric Anholt673a3942008-07-30 12:06:12 -07003104 return 0;
3105
Eric Anholte47c68e2008-11-14 13:35:19 -08003106 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3107 * newly adding I915_GEM_DOMAIN_CPU
3108 */
Eric Anholt673a3942008-07-30 12:06:12 -07003109 if (obj_priv->page_cpu_valid == NULL) {
Eric Anholt9a298b22009-03-24 12:23:04 -07003110 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3111 GFP_KERNEL);
Eric Anholte47c68e2008-11-14 13:35:19 -08003112 if (obj_priv->page_cpu_valid == NULL)
3113 return -ENOMEM;
3114 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3115 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
Eric Anholt673a3942008-07-30 12:06:12 -07003116
3117 /* Flush the cache on any pages that are still invalid from the CPU's
3118 * perspective.
3119 */
Eric Anholte47c68e2008-11-14 13:35:19 -08003120 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3121 i++) {
Eric Anholt673a3942008-07-30 12:06:12 -07003122 if (obj_priv->page_cpu_valid[i])
3123 continue;
3124
Eric Anholt856fa192009-03-19 14:10:50 -07003125 drm_clflush_pages(obj_priv->pages + i, 1);
Eric Anholt673a3942008-07-30 12:06:12 -07003126
3127 obj_priv->page_cpu_valid[i] = 1;
3128 }
3129
Eric Anholte47c68e2008-11-14 13:35:19 -08003130 /* It should now be out of any other write domains, and we can update
3131 * the domain values for our changes.
3132 */
3133 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3134
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003135 old_read_domains = obj->read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08003136 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3137
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003138 trace_i915_gem_object_change_domain(obj,
3139 old_read_domains,
3140 obj->write_domain);
3141
Eric Anholt673a3942008-07-30 12:06:12 -07003142 return 0;
3143}
3144
3145/**
Eric Anholt673a3942008-07-30 12:06:12 -07003146 * Pin an object to the GTT and evaluate the relocations landing in it.
3147 */
3148static int
3149i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3150 struct drm_file *file_priv,
Jesse Barnes76446ca2009-12-17 22:05:42 -05003151 struct drm_i915_gem_exec_object2 *entry,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003152 struct drm_i915_gem_relocation_entry *relocs)
Eric Anholt673a3942008-07-30 12:06:12 -07003153{
3154 struct drm_device *dev = obj->dev;
Keith Packard0839ccb2008-10-30 19:38:48 -07003155 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01003156 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003157 int i, ret;
Keith Packard0839ccb2008-10-30 19:38:48 -07003158 void __iomem *reloc_page;
Jesse Barnes76446ca2009-12-17 22:05:42 -05003159 bool need_fence;
3160
3161 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3162 obj_priv->tiling_mode != I915_TILING_NONE;
3163
3164 /* Check fence reg constraints and rebind if necessary */
Chris Wilson808b24d2010-05-27 13:18:15 +01003165 if (need_fence &&
3166 !i915_gem_object_fence_offset_ok(obj,
3167 obj_priv->tiling_mode)) {
3168 ret = i915_gem_object_unbind(obj);
3169 if (ret)
3170 return ret;
3171 }
Eric Anholt673a3942008-07-30 12:06:12 -07003172
3173 /* Choose the GTT offset for our buffer and put it there. */
3174 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3175 if (ret)
3176 return ret;
3177
Jesse Barnes76446ca2009-12-17 22:05:42 -05003178 /*
3179 * Pre-965 chips need a fence register set up in order to
3180 * properly handle blits to/from tiled surfaces.
3181 */
3182 if (need_fence) {
Chris Wilson2cf34d72010-09-14 13:03:28 +01003183 ret = i915_gem_object_get_fence_reg(obj, false);
Jesse Barnes76446ca2009-12-17 22:05:42 -05003184 if (ret != 0) {
Jesse Barnes76446ca2009-12-17 22:05:42 -05003185 i915_gem_object_unpin(obj);
3186 return ret;
3187 }
3188 }
3189
Eric Anholt673a3942008-07-30 12:06:12 -07003190 entry->offset = obj_priv->gtt_offset;
3191
Eric Anholt673a3942008-07-30 12:06:12 -07003192 /* Apply the relocations, using the GTT aperture to avoid cache
3193 * flushing requirements.
3194 */
3195 for (i = 0; i < entry->relocation_count; i++) {
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003196 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
Eric Anholt673a3942008-07-30 12:06:12 -07003197 struct drm_gem_object *target_obj;
3198 struct drm_i915_gem_object *target_obj_priv;
Eric Anholt3043c602008-10-02 12:24:47 -07003199 uint32_t reloc_val, reloc_offset;
3200 uint32_t __iomem *reloc_entry;
Eric Anholt673a3942008-07-30 12:06:12 -07003201
Eric Anholt673a3942008-07-30 12:06:12 -07003202 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003203 reloc->target_handle);
Eric Anholt673a3942008-07-30 12:06:12 -07003204 if (target_obj == NULL) {
3205 i915_gem_object_unpin(obj);
Chris Wilsonbf79cb92010-08-04 14:19:46 +01003206 return -ENOENT;
Eric Anholt673a3942008-07-30 12:06:12 -07003207 }
Daniel Vetter23010e42010-03-08 13:35:02 +01003208 target_obj_priv = to_intel_bo(target_obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003209
Chris Wilson8542a0b2009-09-09 21:15:15 +01003210#if WATCH_RELOC
3211 DRM_INFO("%s: obj %p offset %08x target %d "
3212 "read %08x write %08x gtt %08x "
3213 "presumed %08x delta %08x\n",
3214 __func__,
3215 obj,
3216 (int) reloc->offset,
3217 (int) reloc->target_handle,
3218 (int) reloc->read_domains,
3219 (int) reloc->write_domain,
3220 (int) target_obj_priv->gtt_offset,
3221 (int) reloc->presumed_offset,
3222 reloc->delta);
3223#endif
3224
Eric Anholt673a3942008-07-30 12:06:12 -07003225 /* The target buffer should have appeared before us in the
3226 * exec_object list, so it should have a GTT space bound by now.
3227 */
3228 if (target_obj_priv->gtt_space == NULL) {
3229 DRM_ERROR("No GTT space found for object %d\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003230 reloc->target_handle);
Eric Anholt673a3942008-07-30 12:06:12 -07003231 drm_gem_object_unreference(target_obj);
3232 i915_gem_object_unpin(obj);
3233 return -EINVAL;
3234 }
3235
Chris Wilson8542a0b2009-09-09 21:15:15 +01003236 /* Validate that the target is in a valid r/w GPU domain */
Daniel Vetter16edd552010-02-19 11:52:02 +01003237 if (reloc->write_domain & (reloc->write_domain - 1)) {
3238 DRM_ERROR("reloc with multiple write domains: "
3239 "obj %p target %d offset %d "
3240 "read %08x write %08x",
3241 obj, reloc->target_handle,
3242 (int) reloc->offset,
3243 reloc->read_domains,
3244 reloc->write_domain);
3245 return -EINVAL;
3246 }
Chris Wilson8542a0b2009-09-09 21:15:15 +01003247 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3248 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3249 DRM_ERROR("reloc with read/write CPU domains: "
3250 "obj %p target %d offset %d "
3251 "read %08x write %08x",
3252 obj, reloc->target_handle,
3253 (int) reloc->offset,
3254 reloc->read_domains,
3255 reloc->write_domain);
3256 drm_gem_object_unreference(target_obj);
3257 i915_gem_object_unpin(obj);
3258 return -EINVAL;
3259 }
3260 if (reloc->write_domain && target_obj->pending_write_domain &&
3261 reloc->write_domain != target_obj->pending_write_domain) {
3262 DRM_ERROR("Write domain conflict: "
3263 "obj %p target %d offset %d "
3264 "new %08x old %08x\n",
3265 obj, reloc->target_handle,
3266 (int) reloc->offset,
3267 reloc->write_domain,
3268 target_obj->pending_write_domain);
3269 drm_gem_object_unreference(target_obj);
3270 i915_gem_object_unpin(obj);
3271 return -EINVAL;
3272 }
3273
3274 target_obj->pending_read_domains |= reloc->read_domains;
3275 target_obj->pending_write_domain |= reloc->write_domain;
3276
3277 /* If the relocation already has the right value in it, no
3278 * more work needs to be done.
3279 */
3280 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3281 drm_gem_object_unreference(target_obj);
3282 continue;
3283 }
3284
3285 /* Check that the relocation address is valid... */
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003286 if (reloc->offset > obj->size - 4) {
Eric Anholt673a3942008-07-30 12:06:12 -07003287 DRM_ERROR("Relocation beyond object bounds: "
3288 "obj %p target %d offset %d size %d.\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003289 obj, reloc->target_handle,
3290 (int) reloc->offset, (int) obj->size);
Eric Anholt673a3942008-07-30 12:06:12 -07003291 drm_gem_object_unreference(target_obj);
3292 i915_gem_object_unpin(obj);
3293 return -EINVAL;
3294 }
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003295 if (reloc->offset & 3) {
Eric Anholt673a3942008-07-30 12:06:12 -07003296 DRM_ERROR("Relocation not 4-byte aligned: "
3297 "obj %p target %d offset %d.\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003298 obj, reloc->target_handle,
3299 (int) reloc->offset);
Eric Anholt673a3942008-07-30 12:06:12 -07003300 drm_gem_object_unreference(target_obj);
3301 i915_gem_object_unpin(obj);
3302 return -EINVAL;
3303 }
3304
Chris Wilson8542a0b2009-09-09 21:15:15 +01003305 /* and points to somewhere within the target object. */
Chris Wilsoncd0b9fb2009-09-15 23:23:18 +01003306 if (reloc->delta >= target_obj->size) {
3307 DRM_ERROR("Relocation beyond target object bounds: "
3308 "obj %p target %d delta %d size %d.\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003309 obj, reloc->target_handle,
Chris Wilsoncd0b9fb2009-09-15 23:23:18 +01003310 (int) reloc->delta, (int) target_obj->size);
Chris Wilson491152b2009-02-11 14:26:32 +00003311 drm_gem_object_unreference(target_obj);
3312 i915_gem_object_unpin(obj);
Eric Anholte47c68e2008-11-14 13:35:19 -08003313 return -EINVAL;
3314 }
3315
Eric Anholt2ef7eea2008-11-10 10:53:25 -08003316 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3317 if (ret != 0) {
3318 drm_gem_object_unreference(target_obj);
3319 i915_gem_object_unpin(obj);
3320 return -EINVAL;
Eric Anholt673a3942008-07-30 12:06:12 -07003321 }
3322
3323 /* Map the page containing the relocation we're going to
3324 * perform.
3325 */
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003326 reloc_offset = obj_priv->gtt_offset + reloc->offset;
Keith Packard0839ccb2008-10-30 19:38:48 -07003327 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3328 (reloc_offset &
Chris Wilsonfca3ec02010-08-04 14:34:24 +01003329 ~(PAGE_SIZE - 1)),
3330 KM_USER0);
Eric Anholt3043c602008-10-02 12:24:47 -07003331 reloc_entry = (uint32_t __iomem *)(reloc_page +
Keith Packard0839ccb2008-10-30 19:38:48 -07003332 (reloc_offset & (PAGE_SIZE - 1)));
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003333 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
Eric Anholt673a3942008-07-30 12:06:12 -07003334
3335#if WATCH_BUF
3336 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003337 obj, (unsigned int) reloc->offset,
Eric Anholt673a3942008-07-30 12:06:12 -07003338 readl(reloc_entry), reloc_val);
3339#endif
3340 writel(reloc_val, reloc_entry);
Chris Wilsonfca3ec02010-08-04 14:34:24 +01003341 io_mapping_unmap_atomic(reloc_page, KM_USER0);
Eric Anholt673a3942008-07-30 12:06:12 -07003342
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003343 /* The updated presumed offset for this entry will be
3344 * copied back out to the user.
Eric Anholt673a3942008-07-30 12:06:12 -07003345 */
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003346 reloc->presumed_offset = target_obj_priv->gtt_offset;
Eric Anholt673a3942008-07-30 12:06:12 -07003347
3348 drm_gem_object_unreference(target_obj);
3349 }
3350
Eric Anholt673a3942008-07-30 12:06:12 -07003351#if WATCH_BUF
3352 if (0)
3353 i915_gem_dump_object(obj, 128, __func__, ~0);
3354#endif
3355 return 0;
3356}
3357
Eric Anholt673a3942008-07-30 12:06:12 -07003358/* Throttle our rendering by waiting until the ring has completed our requests
3359 * emitted over 20 msec ago.
3360 *
Eric Anholtb9624422009-06-03 07:27:35 +00003361 * Note that if we were to use the current jiffies each time around the loop,
3362 * we wouldn't escape the function with any frames outstanding if the time to
3363 * render a frame was over 20ms.
3364 *
Eric Anholt673a3942008-07-30 12:06:12 -07003365 * This should get us reasonable parallelism between CPU and GPU but also
3366 * relatively low latency when blocking on a particular request to finish.
3367 */
3368static int
3369i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3370{
3371 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3372 int ret = 0;
Eric Anholtb9624422009-06-03 07:27:35 +00003373 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
Eric Anholt673a3942008-07-30 12:06:12 -07003374
3375 mutex_lock(&dev->struct_mutex);
Eric Anholtb9624422009-06-03 07:27:35 +00003376 while (!list_empty(&i915_file_priv->mm.request_list)) {
3377 struct drm_i915_gem_request *request;
3378
3379 request = list_first_entry(&i915_file_priv->mm.request_list,
3380 struct drm_i915_gem_request,
3381 client_list);
3382
3383 if (time_after_eq(request->emitted_jiffies, recent_enough))
3384 break;
3385
Zou Nan hai852835f2010-05-21 09:08:56 +08003386 ret = i915_wait_request(dev, request->seqno, request->ring);
Eric Anholtb9624422009-06-03 07:27:35 +00003387 if (ret != 0)
3388 break;
3389 }
Eric Anholt673a3942008-07-30 12:06:12 -07003390 mutex_unlock(&dev->struct_mutex);
Eric Anholtb9624422009-06-03 07:27:35 +00003391
Eric Anholt673a3942008-07-30 12:06:12 -07003392 return ret;
3393}
3394
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003395static int
Jesse Barnes76446ca2009-12-17 22:05:42 -05003396i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003397 uint32_t buffer_count,
3398 struct drm_i915_gem_relocation_entry **relocs)
3399{
3400 uint32_t reloc_count = 0, reloc_index = 0, i;
3401 int ret;
3402
3403 *relocs = NULL;
3404 for (i = 0; i < buffer_count; i++) {
3405 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3406 return -EINVAL;
3407 reloc_count += exec_list[i].relocation_count;
3408 }
3409
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07003410 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
Jesse Barnes76446ca2009-12-17 22:05:42 -05003411 if (*relocs == NULL) {
3412 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003413 return -ENOMEM;
Jesse Barnes76446ca2009-12-17 22:05:42 -05003414 }
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003415
3416 for (i = 0; i < buffer_count; i++) {
3417 struct drm_i915_gem_relocation_entry __user *user_relocs;
3418
3419 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3420
3421 ret = copy_from_user(&(*relocs)[reloc_index],
3422 user_relocs,
3423 exec_list[i].relocation_count *
3424 sizeof(**relocs));
3425 if (ret != 0) {
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07003426 drm_free_large(*relocs);
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003427 *relocs = NULL;
Florian Mickler2bc43b52009-04-06 22:55:41 +02003428 return -EFAULT;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003429 }
3430
3431 reloc_index += exec_list[i].relocation_count;
3432 }
3433
Florian Mickler2bc43b52009-04-06 22:55:41 +02003434 return 0;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003435}
3436
3437static int
Jesse Barnes76446ca2009-12-17 22:05:42 -05003438i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003439 uint32_t buffer_count,
3440 struct drm_i915_gem_relocation_entry *relocs)
3441{
3442 uint32_t reloc_count = 0, i;
Florian Mickler2bc43b52009-04-06 22:55:41 +02003443 int ret = 0;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003444
Chris Wilson93533c22010-01-31 10:40:48 +00003445 if (relocs == NULL)
3446 return 0;
3447
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003448 for (i = 0; i < buffer_count; i++) {
3449 struct drm_i915_gem_relocation_entry __user *user_relocs;
Florian Mickler2bc43b52009-04-06 22:55:41 +02003450 int unwritten;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003451
3452 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3453
Florian Mickler2bc43b52009-04-06 22:55:41 +02003454 unwritten = copy_to_user(user_relocs,
3455 &relocs[reloc_count],
3456 exec_list[i].relocation_count *
3457 sizeof(*relocs));
3458
3459 if (unwritten) {
3460 ret = -EFAULT;
3461 goto err;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003462 }
3463
3464 reloc_count += exec_list[i].relocation_count;
3465 }
3466
Florian Mickler2bc43b52009-04-06 22:55:41 +02003467err:
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07003468 drm_free_large(relocs);
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003469
3470 return ret;
3471}
3472
Chris Wilson83d60792009-06-06 09:45:57 +01003473static int
Jesse Barnes76446ca2009-12-17 22:05:42 -05003474i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
Chris Wilson83d60792009-06-06 09:45:57 +01003475 uint64_t exec_offset)
3476{
3477 uint32_t exec_start, exec_len;
3478
3479 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3480 exec_len = (uint32_t) exec->batch_len;
3481
3482 if ((exec_start | exec_len) & 0x7)
3483 return -EINVAL;
3484
3485 if (!exec_start)
3486 return -EINVAL;
3487
3488 return 0;
3489}
3490
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05003491static int
3492i915_gem_wait_for_pending_flip(struct drm_device *dev,
3493 struct drm_gem_object **object_list,
3494 int count)
3495{
3496 drm_i915_private_t *dev_priv = dev->dev_private;
3497 struct drm_i915_gem_object *obj_priv;
3498 DEFINE_WAIT(wait);
3499 int i, ret = 0;
3500
3501 for (;;) {
3502 prepare_to_wait(&dev_priv->pending_flip_queue,
3503 &wait, TASK_INTERRUPTIBLE);
3504 for (i = 0; i < count; i++) {
Daniel Vetter23010e42010-03-08 13:35:02 +01003505 obj_priv = to_intel_bo(object_list[i]);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05003506 if (atomic_read(&obj_priv->pending_flip) > 0)
3507 break;
3508 }
3509 if (i == count)
3510 break;
3511
3512 if (!signal_pending(current)) {
3513 mutex_unlock(&dev->struct_mutex);
3514 schedule();
3515 mutex_lock(&dev->struct_mutex);
3516 continue;
3517 }
3518 ret = -ERESTARTSYS;
3519 break;
3520 }
3521 finish_wait(&dev_priv->pending_flip_queue, &wait);
3522
3523 return ret;
3524}
3525
Chris Wilson8dc5d142010-08-12 12:36:12 +01003526static int
Jesse Barnes76446ca2009-12-17 22:05:42 -05003527i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3528 struct drm_file *file_priv,
3529 struct drm_i915_gem_execbuffer2 *args,
3530 struct drm_i915_gem_exec_object2 *exec_list)
Eric Anholt673a3942008-07-30 12:06:12 -07003531{
3532 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -07003533 struct drm_gem_object **object_list = NULL;
3534 struct drm_gem_object *batch_obj;
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003535 struct drm_i915_gem_object *obj_priv;
Eric Anholt201361a2009-03-11 12:30:04 -07003536 struct drm_clip_rect *cliprects = NULL;
Chris Wilson93533c22010-01-31 10:40:48 +00003537 struct drm_i915_gem_relocation_entry *relocs = NULL;
Chris Wilson8dc5d142010-08-12 12:36:12 +01003538 struct drm_i915_gem_request *request = NULL;
Jesse Barnes76446ca2009-12-17 22:05:42 -05003539 int ret = 0, ret2, i, pinned = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07003540 uint64_t exec_offset;
Daniel Vetter8a1a49f2010-02-11 22:29:04 +01003541 uint32_t seqno, reloc_index;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05003542 int pin_tries, flips;
Eric Anholt673a3942008-07-30 12:06:12 -07003543
Zou Nan hai852835f2010-05-21 09:08:56 +08003544 struct intel_ring_buffer *ring = NULL;
3545
Eric Anholt673a3942008-07-30 12:06:12 -07003546#if WATCH_EXEC
3547 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3548 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3549#endif
Zou Nan haid1b851f2010-05-21 09:08:57 +08003550 if (args->flags & I915_EXEC_BSD) {
3551 if (!HAS_BSD(dev)) {
3552 DRM_ERROR("execbuf with wrong flag\n");
3553 return -EINVAL;
3554 }
3555 ring = &dev_priv->bsd_ring;
3556 } else {
3557 ring = &dev_priv->render_ring;
3558 }
3559
Eric Anholt4f481ed2008-09-10 14:22:49 -07003560 if (args->buffer_count < 1) {
3561 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3562 return -EINVAL;
3563 }
Eric Anholtc8e0f932009-11-22 03:49:37 +01003564 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
Jesse Barnes76446ca2009-12-17 22:05:42 -05003565 if (object_list == NULL) {
3566 DRM_ERROR("Failed to allocate object list for %d buffers\n",
Eric Anholt673a3942008-07-30 12:06:12 -07003567 args->buffer_count);
3568 ret = -ENOMEM;
3569 goto pre_mutex_err;
3570 }
Eric Anholt673a3942008-07-30 12:06:12 -07003571
Eric Anholt201361a2009-03-11 12:30:04 -07003572 if (args->num_cliprects != 0) {
Eric Anholt9a298b22009-03-24 12:23:04 -07003573 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3574 GFP_KERNEL);
Owain Ainswortha40e8d32010-02-09 14:25:55 +00003575 if (cliprects == NULL) {
3576 ret = -ENOMEM;
Eric Anholt201361a2009-03-11 12:30:04 -07003577 goto pre_mutex_err;
Owain Ainswortha40e8d32010-02-09 14:25:55 +00003578 }
Eric Anholt201361a2009-03-11 12:30:04 -07003579
3580 ret = copy_from_user(cliprects,
3581 (struct drm_clip_rect __user *)
3582 (uintptr_t) args->cliprects_ptr,
3583 sizeof(*cliprects) * args->num_cliprects);
3584 if (ret != 0) {
3585 DRM_ERROR("copy %d cliprects failed: %d\n",
3586 args->num_cliprects, ret);
Dan Carpenterc877cdc2010-06-23 19:03:01 +02003587 ret = -EFAULT;
Eric Anholt201361a2009-03-11 12:30:04 -07003588 goto pre_mutex_err;
3589 }
3590 }
3591
Chris Wilson8dc5d142010-08-12 12:36:12 +01003592 request = kzalloc(sizeof(*request), GFP_KERNEL);
3593 if (request == NULL) {
3594 ret = -ENOMEM;
3595 goto pre_mutex_err;
3596 }
3597
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003598 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3599 &relocs);
3600 if (ret != 0)
3601 goto pre_mutex_err;
3602
Eric Anholt673a3942008-07-30 12:06:12 -07003603 mutex_lock(&dev->struct_mutex);
3604
3605 i915_verify_inactive(dev, __FILE__, __LINE__);
3606
Ben Gamariba1234d2009-09-14 17:48:47 -04003607 if (atomic_read(&dev_priv->mm.wedged)) {
Eric Anholt673a3942008-07-30 12:06:12 -07003608 mutex_unlock(&dev->struct_mutex);
Chris Wilsona198bc82009-02-06 16:55:20 +00003609 ret = -EIO;
3610 goto pre_mutex_err;
Eric Anholt673a3942008-07-30 12:06:12 -07003611 }
3612
3613 if (dev_priv->mm.suspended) {
Eric Anholt673a3942008-07-30 12:06:12 -07003614 mutex_unlock(&dev->struct_mutex);
Chris Wilsona198bc82009-02-06 16:55:20 +00003615 ret = -EBUSY;
3616 goto pre_mutex_err;
Eric Anholt673a3942008-07-30 12:06:12 -07003617 }
3618
Keith Packardac94a962008-11-20 23:30:27 -08003619 /* Look up object handles */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05003620 flips = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07003621 for (i = 0; i < args->buffer_count; i++) {
3622 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3623 exec_list[i].handle);
3624 if (object_list[i] == NULL) {
3625 DRM_ERROR("Invalid object handle %d at index %d\n",
3626 exec_list[i].handle, i);
Chris Wilson0ce907f2010-01-23 20:26:35 +00003627 /* prevent error path from reading uninitialized data */
3628 args->buffer_count = i + 1;
Chris Wilsonbf79cb92010-08-04 14:19:46 +01003629 ret = -ENOENT;
Eric Anholt673a3942008-07-30 12:06:12 -07003630 goto err;
3631 }
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003632
Daniel Vetter23010e42010-03-08 13:35:02 +01003633 obj_priv = to_intel_bo(object_list[i]);
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003634 if (obj_priv->in_execbuffer) {
3635 DRM_ERROR("Object %p appears more than once in object list\n",
3636 object_list[i]);
Chris Wilson0ce907f2010-01-23 20:26:35 +00003637 /* prevent error path from reading uninitialized data */
3638 args->buffer_count = i + 1;
Chris Wilsonbf79cb92010-08-04 14:19:46 +01003639 ret = -EINVAL;
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003640 goto err;
3641 }
3642 obj_priv->in_execbuffer = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05003643 flips += atomic_read(&obj_priv->pending_flip);
3644 }
3645
3646 if (flips > 0) {
3647 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3648 args->buffer_count);
3649 if (ret)
3650 goto err;
Keith Packardac94a962008-11-20 23:30:27 -08003651 }
Eric Anholt673a3942008-07-30 12:06:12 -07003652
Keith Packardac94a962008-11-20 23:30:27 -08003653 /* Pin and relocate */
3654 for (pin_tries = 0; ; pin_tries++) {
3655 ret = 0;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003656 reloc_index = 0;
3657
Keith Packardac94a962008-11-20 23:30:27 -08003658 for (i = 0; i < args->buffer_count; i++) {
3659 object_list[i]->pending_read_domains = 0;
3660 object_list[i]->pending_write_domain = 0;
3661 ret = i915_gem_object_pin_and_relocate(object_list[i],
3662 file_priv,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003663 &exec_list[i],
3664 &relocs[reloc_index]);
Keith Packardac94a962008-11-20 23:30:27 -08003665 if (ret)
3666 break;
3667 pinned = i + 1;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003668 reloc_index += exec_list[i].relocation_count;
Keith Packardac94a962008-11-20 23:30:27 -08003669 }
3670 /* success */
3671 if (ret == 0)
3672 break;
3673
3674 /* error other than GTT full, or we've already tried again */
Chris Wilson2939e1f2009-06-06 09:46:03 +01003675 if (ret != -ENOSPC || pin_tries >= 1) {
Chris Wilson07f73f62009-09-14 16:50:30 +01003676 if (ret != -ERESTARTSYS) {
3677 unsigned long long total_size = 0;
Chris Wilson3d1cc472010-05-27 13:18:19 +01003678 int num_fences = 0;
3679 for (i = 0; i < args->buffer_count; i++) {
Chris Wilson43b27f42010-07-02 08:57:15 +01003680 obj_priv = to_intel_bo(object_list[i]);
Chris Wilson3d1cc472010-05-27 13:18:19 +01003681
Chris Wilson07f73f62009-09-14 16:50:30 +01003682 total_size += object_list[i]->size;
Chris Wilson3d1cc472010-05-27 13:18:19 +01003683 num_fences +=
3684 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3685 obj_priv->tiling_mode != I915_TILING_NONE;
3686 }
3687 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
Chris Wilson07f73f62009-09-14 16:50:30 +01003688 pinned+1, args->buffer_count,
Chris Wilson3d1cc472010-05-27 13:18:19 +01003689 total_size, num_fences,
3690 ret);
Chris Wilson07f73f62009-09-14 16:50:30 +01003691 DRM_ERROR("%d objects [%d pinned], "
3692 "%d object bytes [%d pinned], "
3693 "%d/%d gtt bytes\n",
3694 atomic_read(&dev->object_count),
3695 atomic_read(&dev->pin_count),
3696 atomic_read(&dev->object_memory),
3697 atomic_read(&dev->pin_memory),
3698 atomic_read(&dev->gtt_memory),
3699 dev->gtt_total);
3700 }
Eric Anholt673a3942008-07-30 12:06:12 -07003701 goto err;
3702 }
Keith Packardac94a962008-11-20 23:30:27 -08003703
3704 /* unpin all of our buffers */
3705 for (i = 0; i < pinned; i++)
3706 i915_gem_object_unpin(object_list[i]);
Eric Anholtb1177632008-12-10 10:09:41 -08003707 pinned = 0;
Keith Packardac94a962008-11-20 23:30:27 -08003708
3709 /* evict everyone we can from the aperture */
3710 ret = i915_gem_evict_everything(dev);
Chris Wilson07f73f62009-09-14 16:50:30 +01003711 if (ret && ret != -ENOSPC)
Keith Packardac94a962008-11-20 23:30:27 -08003712 goto err;
Eric Anholt673a3942008-07-30 12:06:12 -07003713 }
3714
3715 /* Set the pending read domains for the batch buffer to COMMAND */
3716 batch_obj = object_list[args->buffer_count-1];
Chris Wilson5f26a2c2009-06-06 09:45:58 +01003717 if (batch_obj->pending_write_domain) {
3718 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3719 ret = -EINVAL;
3720 goto err;
3721 }
3722 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
Eric Anholt673a3942008-07-30 12:06:12 -07003723
Chris Wilson83d60792009-06-06 09:45:57 +01003724 /* Sanity check the batch buffer, prior to moving objects */
3725 exec_offset = exec_list[args->buffer_count - 1].offset;
3726 ret = i915_gem_check_execbuffer (args, exec_offset);
3727 if (ret != 0) {
3728 DRM_ERROR("execbuf with invalid offset/length\n");
3729 goto err;
3730 }
3731
Eric Anholt673a3942008-07-30 12:06:12 -07003732 i915_verify_inactive(dev, __FILE__, __LINE__);
3733
Keith Packard646f0f62008-11-20 23:23:03 -08003734 /* Zero the global flush/invalidate flags. These
3735 * will be modified as new domains are computed
3736 * for each object
3737 */
3738 dev->invalidate_domains = 0;
3739 dev->flush_domains = 0;
Chris Wilson92204342010-09-18 11:02:01 +01003740 dev_priv->mm.flush_rings = 0;
Keith Packard646f0f62008-11-20 23:23:03 -08003741
Eric Anholt673a3942008-07-30 12:06:12 -07003742 for (i = 0; i < args->buffer_count; i++) {
3743 struct drm_gem_object *obj = object_list[i];
Eric Anholt673a3942008-07-30 12:06:12 -07003744
Keith Packard646f0f62008-11-20 23:23:03 -08003745 /* Compute new gpu domains and update invalidate/flush */
Eric Anholt8b0e3782009-02-19 14:40:50 -08003746 i915_gem_object_set_to_gpu_domain(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003747 }
3748
3749 i915_verify_inactive(dev, __FILE__, __LINE__);
3750
Keith Packard646f0f62008-11-20 23:23:03 -08003751 if (dev->invalidate_domains | dev->flush_domains) {
3752#if WATCH_EXEC
3753 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3754 __func__,
3755 dev->invalidate_domains,
3756 dev->flush_domains);
3757#endif
3758 i915_gem_flush(dev,
3759 dev->invalidate_domains,
Chris Wilson92204342010-09-18 11:02:01 +01003760 dev->flush_domains,
3761 dev_priv->mm.flush_rings);
Daniel Vettera6910432010-02-02 17:08:37 +01003762 }
3763
3764 if (dev_priv->render_ring.outstanding_lazy_request) {
Chris Wilson8dc5d142010-08-12 12:36:12 +01003765 (void)i915_add_request(dev, file_priv, NULL, &dev_priv->render_ring);
Daniel Vettera6910432010-02-02 17:08:37 +01003766 dev_priv->render_ring.outstanding_lazy_request = false;
3767 }
3768 if (dev_priv->bsd_ring.outstanding_lazy_request) {
Chris Wilson8dc5d142010-08-12 12:36:12 +01003769 (void)i915_add_request(dev, file_priv, NULL, &dev_priv->bsd_ring);
Daniel Vettera6910432010-02-02 17:08:37 +01003770 dev_priv->bsd_ring.outstanding_lazy_request = false;
Keith Packard646f0f62008-11-20 23:23:03 -08003771 }
Eric Anholt673a3942008-07-30 12:06:12 -07003772
Eric Anholtefbeed92009-02-19 14:54:51 -08003773 for (i = 0; i < args->buffer_count; i++) {
3774 struct drm_gem_object *obj = object_list[i];
Daniel Vetter23010e42010-03-08 13:35:02 +01003775 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003776 uint32_t old_write_domain = obj->write_domain;
Eric Anholtefbeed92009-02-19 14:54:51 -08003777
3778 obj->write_domain = obj->pending_write_domain;
Daniel Vetter99fcb762010-02-07 16:20:18 +01003779 if (obj->write_domain)
3780 list_move_tail(&obj_priv->gpu_write_list,
3781 &dev_priv->mm.gpu_write_list);
3782 else
3783 list_del_init(&obj_priv->gpu_write_list);
3784
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003785 trace_i915_gem_object_change_domain(obj,
3786 obj->read_domains,
3787 old_write_domain);
Eric Anholtefbeed92009-02-19 14:54:51 -08003788 }
3789
Eric Anholt673a3942008-07-30 12:06:12 -07003790 i915_verify_inactive(dev, __FILE__, __LINE__);
3791
3792#if WATCH_COHERENCY
3793 for (i = 0; i < args->buffer_count; i++) {
3794 i915_gem_object_check_coherency(object_list[i],
3795 exec_list[i].handle);
3796 }
3797#endif
3798
Eric Anholt673a3942008-07-30 12:06:12 -07003799#if WATCH_EXEC
Ben Gamari6911a9b2009-04-02 11:24:54 -07003800 i915_gem_dump_object(batch_obj,
Eric Anholt673a3942008-07-30 12:06:12 -07003801 args->batch_len,
3802 __func__,
3803 ~0);
3804#endif
3805
Eric Anholt673a3942008-07-30 12:06:12 -07003806 /* Exec the batchbuffer */
Zou Nan hai852835f2010-05-21 09:08:56 +08003807 ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3808 cliprects, exec_offset);
Eric Anholt673a3942008-07-30 12:06:12 -07003809 if (ret) {
3810 DRM_ERROR("dispatch failed %d\n", ret);
3811 goto err;
3812 }
3813
3814 /*
3815 * Ensure that the commands in the batch buffer are
3816 * finished before the interrupt fires
3817 */
Daniel Vetter8a1a49f2010-02-11 22:29:04 +01003818 i915_retire_commands(dev, ring);
Eric Anholt673a3942008-07-30 12:06:12 -07003819
3820 i915_verify_inactive(dev, __FILE__, __LINE__);
3821
Daniel Vetter617dbe22010-02-11 22:16:02 +01003822 for (i = 0; i < args->buffer_count; i++) {
3823 struct drm_gem_object *obj = object_list[i];
3824 obj_priv = to_intel_bo(obj);
3825
3826 i915_gem_object_move_to_active(obj, ring);
3827#if WATCH_LRU
3828 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3829#endif
3830 }
3831
Eric Anholt673a3942008-07-30 12:06:12 -07003832 /*
3833 * Get a seqno representing the execution of the current buffer,
3834 * which we can wait on. We would like to mitigate these interrupts,
3835 * likely by only creating seqnos occasionally (so that we have
3836 * *some* interrupts representing completion of buffers that we can
3837 * wait on when trying to clear up gtt space).
3838 */
Chris Wilson8dc5d142010-08-12 12:36:12 +01003839 seqno = i915_add_request(dev, file_priv, request, ring);
3840 request = NULL;
Eric Anholt673a3942008-07-30 12:06:12 -07003841
Eric Anholt673a3942008-07-30 12:06:12 -07003842#if WATCH_LRU
3843 i915_dump_lru(dev, __func__);
3844#endif
3845
3846 i915_verify_inactive(dev, __FILE__, __LINE__);
3847
Eric Anholt673a3942008-07-30 12:06:12 -07003848err:
Julia Lawallaad87df2008-12-21 16:28:47 +01003849 for (i = 0; i < pinned; i++)
3850 i915_gem_object_unpin(object_list[i]);
Eric Anholt673a3942008-07-30 12:06:12 -07003851
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003852 for (i = 0; i < args->buffer_count; i++) {
3853 if (object_list[i]) {
Daniel Vetter23010e42010-03-08 13:35:02 +01003854 obj_priv = to_intel_bo(object_list[i]);
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003855 obj_priv->in_execbuffer = false;
3856 }
Julia Lawallaad87df2008-12-21 16:28:47 +01003857 drm_gem_object_unreference(object_list[i]);
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003858 }
Julia Lawallaad87df2008-12-21 16:28:47 +01003859
Eric Anholt673a3942008-07-30 12:06:12 -07003860 mutex_unlock(&dev->struct_mutex);
3861
Chris Wilson93533c22010-01-31 10:40:48 +00003862pre_mutex_err:
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003863 /* Copy the updated relocations out regardless of current error
3864 * state. Failure to update the relocs would mean that the next
3865 * time userland calls execbuf, it would do so with presumed offset
3866 * state that didn't match the actual object state.
3867 */
3868 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3869 relocs);
3870 if (ret2 != 0) {
3871 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3872
3873 if (ret == 0)
3874 ret = ret2;
3875 }
3876
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07003877 drm_free_large(object_list);
Eric Anholt9a298b22009-03-24 12:23:04 -07003878 kfree(cliprects);
Chris Wilson8dc5d142010-08-12 12:36:12 +01003879 kfree(request);
Eric Anholt673a3942008-07-30 12:06:12 -07003880
3881 return ret;
3882}
3883
Jesse Barnes76446ca2009-12-17 22:05:42 -05003884/*
3885 * Legacy execbuffer just creates an exec2 list from the original exec object
3886 * list array and passes it to the real function.
3887 */
3888int
3889i915_gem_execbuffer(struct drm_device *dev, void *data,
3890 struct drm_file *file_priv)
3891{
3892 struct drm_i915_gem_execbuffer *args = data;
3893 struct drm_i915_gem_execbuffer2 exec2;
3894 struct drm_i915_gem_exec_object *exec_list = NULL;
3895 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3896 int ret, i;
3897
3898#if WATCH_EXEC
3899 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3900 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3901#endif
3902
3903 if (args->buffer_count < 1) {
3904 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3905 return -EINVAL;
3906 }
3907
3908 /* Copy in the exec list from userland */
3909 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3910 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3911 if (exec_list == NULL || exec2_list == NULL) {
3912 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3913 args->buffer_count);
3914 drm_free_large(exec_list);
3915 drm_free_large(exec2_list);
3916 return -ENOMEM;
3917 }
3918 ret = copy_from_user(exec_list,
3919 (struct drm_i915_relocation_entry __user *)
3920 (uintptr_t) args->buffers_ptr,
3921 sizeof(*exec_list) * args->buffer_count);
3922 if (ret != 0) {
3923 DRM_ERROR("copy %d exec entries failed %d\n",
3924 args->buffer_count, ret);
3925 drm_free_large(exec_list);
3926 drm_free_large(exec2_list);
3927 return -EFAULT;
3928 }
3929
3930 for (i = 0; i < args->buffer_count; i++) {
3931 exec2_list[i].handle = exec_list[i].handle;
3932 exec2_list[i].relocation_count = exec_list[i].relocation_count;
3933 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
3934 exec2_list[i].alignment = exec_list[i].alignment;
3935 exec2_list[i].offset = exec_list[i].offset;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01003936 if (INTEL_INFO(dev)->gen < 4)
Jesse Barnes76446ca2009-12-17 22:05:42 -05003937 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
3938 else
3939 exec2_list[i].flags = 0;
3940 }
3941
3942 exec2.buffers_ptr = args->buffers_ptr;
3943 exec2.buffer_count = args->buffer_count;
3944 exec2.batch_start_offset = args->batch_start_offset;
3945 exec2.batch_len = args->batch_len;
3946 exec2.DR1 = args->DR1;
3947 exec2.DR4 = args->DR4;
3948 exec2.num_cliprects = args->num_cliprects;
3949 exec2.cliprects_ptr = args->cliprects_ptr;
Zou Nan hai852835f2010-05-21 09:08:56 +08003950 exec2.flags = I915_EXEC_RENDER;
Jesse Barnes76446ca2009-12-17 22:05:42 -05003951
3952 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
3953 if (!ret) {
3954 /* Copy the new buffer offsets back to the user's exec list. */
3955 for (i = 0; i < args->buffer_count; i++)
3956 exec_list[i].offset = exec2_list[i].offset;
3957 /* ... and back out to userspace */
3958 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3959 (uintptr_t) args->buffers_ptr,
3960 exec_list,
3961 sizeof(*exec_list) * args->buffer_count);
3962 if (ret) {
3963 ret = -EFAULT;
3964 DRM_ERROR("failed to copy %d exec entries "
3965 "back to user (%d)\n",
3966 args->buffer_count, ret);
3967 }
Jesse Barnes76446ca2009-12-17 22:05:42 -05003968 }
3969
3970 drm_free_large(exec_list);
3971 drm_free_large(exec2_list);
3972 return ret;
3973}
3974
3975int
3976i915_gem_execbuffer2(struct drm_device *dev, void *data,
3977 struct drm_file *file_priv)
3978{
3979 struct drm_i915_gem_execbuffer2 *args = data;
3980 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3981 int ret;
3982
3983#if WATCH_EXEC
3984 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3985 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3986#endif
3987
3988 if (args->buffer_count < 1) {
3989 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
3990 return -EINVAL;
3991 }
3992
3993 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3994 if (exec2_list == NULL) {
3995 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3996 args->buffer_count);
3997 return -ENOMEM;
3998 }
3999 ret = copy_from_user(exec2_list,
4000 (struct drm_i915_relocation_entry __user *)
4001 (uintptr_t) args->buffers_ptr,
4002 sizeof(*exec2_list) * args->buffer_count);
4003 if (ret != 0) {
4004 DRM_ERROR("copy %d exec entries failed %d\n",
4005 args->buffer_count, ret);
4006 drm_free_large(exec2_list);
4007 return -EFAULT;
4008 }
4009
4010 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4011 if (!ret) {
4012 /* Copy the new buffer offsets back to the user's exec list. */
4013 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4014 (uintptr_t) args->buffers_ptr,
4015 exec2_list,
4016 sizeof(*exec2_list) * args->buffer_count);
4017 if (ret) {
4018 ret = -EFAULT;
4019 DRM_ERROR("failed to copy %d exec entries "
4020 "back to user (%d)\n",
4021 args->buffer_count, ret);
4022 }
4023 }
4024
4025 drm_free_large(exec2_list);
4026 return ret;
4027}
4028
Eric Anholt673a3942008-07-30 12:06:12 -07004029int
4030i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4031{
4032 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01004033 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004034 int ret;
4035
Daniel Vetter778c3542010-05-13 11:49:44 +02004036 BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4037
Eric Anholt673a3942008-07-30 12:06:12 -07004038 i915_verify_inactive(dev, __FILE__, __LINE__);
Chris Wilsonac0c6b52010-05-27 13:18:18 +01004039
4040 if (obj_priv->gtt_space != NULL) {
4041 if (alignment == 0)
4042 alignment = i915_gem_get_gtt_alignment(obj);
4043 if (obj_priv->gtt_offset & (alignment - 1)) {
Chris Wilsonae7d49d2010-08-04 12:37:41 +01004044 WARN(obj_priv->pin_count,
4045 "bo is already pinned with incorrect alignment:"
4046 " offset=%x, req.alignment=%x\n",
4047 obj_priv->gtt_offset, alignment);
Chris Wilsonac0c6b52010-05-27 13:18:18 +01004048 ret = i915_gem_object_unbind(obj);
4049 if (ret)
4050 return ret;
4051 }
4052 }
4053
Eric Anholt673a3942008-07-30 12:06:12 -07004054 if (obj_priv->gtt_space == NULL) {
4055 ret = i915_gem_object_bind_to_gtt(obj, alignment);
Chris Wilson97311292009-09-21 00:22:34 +01004056 if (ret)
Eric Anholt673a3942008-07-30 12:06:12 -07004057 return ret;
Chris Wilson22c344e2009-02-11 14:26:45 +00004058 }
Jesse Barnes76446ca2009-12-17 22:05:42 -05004059
Eric Anholt673a3942008-07-30 12:06:12 -07004060 obj_priv->pin_count++;
4061
4062 /* If the object is not active and not pending a flush,
4063 * remove it from the inactive list
4064 */
4065 if (obj_priv->pin_count == 1) {
4066 atomic_inc(&dev->pin_count);
4067 atomic_add(obj->size, &dev->pin_memory);
4068 if (!obj_priv->active &&
Chris Wilsonbf1a1092010-08-07 11:01:20 +01004069 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
Eric Anholt673a3942008-07-30 12:06:12 -07004070 list_del_init(&obj_priv->list);
4071 }
4072 i915_verify_inactive(dev, __FILE__, __LINE__);
4073
4074 return 0;
4075}
4076
4077void
4078i915_gem_object_unpin(struct drm_gem_object *obj)
4079{
4080 struct drm_device *dev = obj->dev;
4081 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01004082 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004083
4084 i915_verify_inactive(dev, __FILE__, __LINE__);
4085 obj_priv->pin_count--;
4086 BUG_ON(obj_priv->pin_count < 0);
4087 BUG_ON(obj_priv->gtt_space == NULL);
4088
4089 /* If the object is no longer pinned, and is
4090 * neither active nor being flushed, then stick it on
4091 * the inactive list
4092 */
4093 if (obj_priv->pin_count == 0) {
4094 if (!obj_priv->active &&
Chris Wilson21d509e2009-06-06 09:46:02 +01004095 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
Eric Anholt673a3942008-07-30 12:06:12 -07004096 list_move_tail(&obj_priv->list,
4097 &dev_priv->mm.inactive_list);
4098 atomic_dec(&dev->pin_count);
4099 atomic_sub(obj->size, &dev->pin_memory);
4100 }
4101 i915_verify_inactive(dev, __FILE__, __LINE__);
4102}
4103
4104int
4105i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4106 struct drm_file *file_priv)
4107{
4108 struct drm_i915_gem_pin *args = data;
4109 struct drm_gem_object *obj;
4110 struct drm_i915_gem_object *obj_priv;
4111 int ret;
4112
4113 mutex_lock(&dev->struct_mutex);
4114
4115 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4116 if (obj == NULL) {
4117 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4118 args->handle);
4119 mutex_unlock(&dev->struct_mutex);
Chris Wilsonbf79cb92010-08-04 14:19:46 +01004120 return -ENOENT;
Eric Anholt673a3942008-07-30 12:06:12 -07004121 }
Daniel Vetter23010e42010-03-08 13:35:02 +01004122 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004123
Chris Wilsonbb6baf72009-09-22 14:24:13 +01004124 if (obj_priv->madv != I915_MADV_WILLNEED) {
4125 DRM_ERROR("Attempting to pin a purgeable buffer\n");
Chris Wilson3ef94da2009-09-14 16:50:29 +01004126 drm_gem_object_unreference(obj);
4127 mutex_unlock(&dev->struct_mutex);
4128 return -EINVAL;
4129 }
4130
Jesse Barnes79e53942008-11-07 14:24:08 -08004131 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4132 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4133 args->handle);
Chris Wilson96dec612009-02-08 19:08:04 +00004134 drm_gem_object_unreference(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004135 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08004136 return -EINVAL;
4137 }
4138
4139 obj_priv->user_pin_count++;
4140 obj_priv->pin_filp = file_priv;
4141 if (obj_priv->user_pin_count == 1) {
4142 ret = i915_gem_object_pin(obj, args->alignment);
4143 if (ret != 0) {
4144 drm_gem_object_unreference(obj);
4145 mutex_unlock(&dev->struct_mutex);
4146 return ret;
4147 }
Eric Anholt673a3942008-07-30 12:06:12 -07004148 }
4149
4150 /* XXX - flush the CPU caches for pinned objects
4151 * as the X server doesn't manage domains yet
4152 */
Eric Anholte47c68e2008-11-14 13:35:19 -08004153 i915_gem_object_flush_cpu_write_domain(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004154 args->offset = obj_priv->gtt_offset;
4155 drm_gem_object_unreference(obj);
4156 mutex_unlock(&dev->struct_mutex);
4157
4158 return 0;
4159}
4160
4161int
4162i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4163 struct drm_file *file_priv)
4164{
4165 struct drm_i915_gem_pin *args = data;
4166 struct drm_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08004167 struct drm_i915_gem_object *obj_priv;
Eric Anholt673a3942008-07-30 12:06:12 -07004168
4169 mutex_lock(&dev->struct_mutex);
4170
4171 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4172 if (obj == NULL) {
4173 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4174 args->handle);
4175 mutex_unlock(&dev->struct_mutex);
Chris Wilsonbf79cb92010-08-04 14:19:46 +01004176 return -ENOENT;
Eric Anholt673a3942008-07-30 12:06:12 -07004177 }
4178
Daniel Vetter23010e42010-03-08 13:35:02 +01004179 obj_priv = to_intel_bo(obj);
Jesse Barnes79e53942008-11-07 14:24:08 -08004180 if (obj_priv->pin_filp != file_priv) {
4181 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4182 args->handle);
4183 drm_gem_object_unreference(obj);
4184 mutex_unlock(&dev->struct_mutex);
4185 return -EINVAL;
4186 }
4187 obj_priv->user_pin_count--;
4188 if (obj_priv->user_pin_count == 0) {
4189 obj_priv->pin_filp = NULL;
4190 i915_gem_object_unpin(obj);
4191 }
Eric Anholt673a3942008-07-30 12:06:12 -07004192
4193 drm_gem_object_unreference(obj);
4194 mutex_unlock(&dev->struct_mutex);
4195 return 0;
4196}
4197
4198int
4199i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4200 struct drm_file *file_priv)
4201{
4202 struct drm_i915_gem_busy *args = data;
4203 struct drm_gem_object *obj;
4204 struct drm_i915_gem_object *obj_priv;
4205
Eric Anholt673a3942008-07-30 12:06:12 -07004206 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4207 if (obj == NULL) {
4208 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4209 args->handle);
Chris Wilsonbf79cb92010-08-04 14:19:46 +01004210 return -ENOENT;
Eric Anholt673a3942008-07-30 12:06:12 -07004211 }
4212
Chris Wilsonb1ce7862009-06-06 09:46:00 +01004213 mutex_lock(&dev->struct_mutex);
Zou Nan haid1b851f2010-05-21 09:08:57 +08004214
Chris Wilson0be555b2010-08-04 15:36:30 +01004215 /* Count all active objects as busy, even if they are currently not used
4216 * by the gpu. Users of this interface expect objects to eventually
4217 * become non-busy without any further actions, therefore emit any
4218 * necessary flushes here.
Eric Anholtc4de0a52008-12-14 19:05:04 -08004219 */
Chris Wilson0be555b2010-08-04 15:36:30 +01004220 obj_priv = to_intel_bo(obj);
4221 args->busy = obj_priv->active;
4222 if (args->busy) {
4223 /* Unconditionally flush objects, even when the gpu still uses this
4224 * object. Userspace calling this function indicates that it wants to
4225 * use this buffer rather sooner than later, so issuing the required
4226 * flush earlier is beneficial.
4227 */
Chris Wilson92204342010-09-18 11:02:01 +01004228 if (obj->write_domain & I915_GEM_GPU_DOMAINS) {
4229 i915_gem_flush_ring(dev,
4230 obj_priv->ring,
4231 0, obj->write_domain);
Chris Wilson8dc5d142010-08-12 12:36:12 +01004232 (void)i915_add_request(dev, file_priv, NULL, obj_priv->ring);
Chris Wilson0be555b2010-08-04 15:36:30 +01004233 }
4234
4235 /* Update the active list for the hardware's current position.
4236 * Otherwise this only updates on a delayed timer or when irqs
4237 * are actually unmasked, and our working set ends up being
4238 * larger than required.
4239 */
4240 i915_gem_retire_requests_ring(dev, obj_priv->ring);
4241
4242 args->busy = obj_priv->active;
4243 }
Eric Anholt673a3942008-07-30 12:06:12 -07004244
4245 drm_gem_object_unreference(obj);
4246 mutex_unlock(&dev->struct_mutex);
4247 return 0;
4248}
4249
4250int
4251i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4252 struct drm_file *file_priv)
4253{
4254 return i915_gem_ring_throttle(dev, file_priv);
4255}
4256
Chris Wilson3ef94da2009-09-14 16:50:29 +01004257int
4258i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4259 struct drm_file *file_priv)
4260{
4261 struct drm_i915_gem_madvise *args = data;
4262 struct drm_gem_object *obj;
4263 struct drm_i915_gem_object *obj_priv;
4264
4265 switch (args->madv) {
4266 case I915_MADV_DONTNEED:
4267 case I915_MADV_WILLNEED:
4268 break;
4269 default:
4270 return -EINVAL;
4271 }
4272
4273 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4274 if (obj == NULL) {
4275 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4276 args->handle);
Chris Wilsonbf79cb92010-08-04 14:19:46 +01004277 return -ENOENT;
Chris Wilson3ef94da2009-09-14 16:50:29 +01004278 }
4279
4280 mutex_lock(&dev->struct_mutex);
Daniel Vetter23010e42010-03-08 13:35:02 +01004281 obj_priv = to_intel_bo(obj);
Chris Wilson3ef94da2009-09-14 16:50:29 +01004282
4283 if (obj_priv->pin_count) {
4284 drm_gem_object_unreference(obj);
4285 mutex_unlock(&dev->struct_mutex);
4286
4287 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4288 return -EINVAL;
4289 }
4290
Chris Wilsonbb6baf72009-09-22 14:24:13 +01004291 if (obj_priv->madv != __I915_MADV_PURGED)
4292 obj_priv->madv = args->madv;
Chris Wilson3ef94da2009-09-14 16:50:29 +01004293
Chris Wilson2d7ef392009-09-20 23:13:10 +01004294 /* if the object is no longer bound, discard its backing storage */
4295 if (i915_gem_object_is_purgeable(obj_priv) &&
4296 obj_priv->gtt_space == NULL)
4297 i915_gem_object_truncate(obj);
4298
Chris Wilsonbb6baf72009-09-22 14:24:13 +01004299 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4300
Chris Wilson3ef94da2009-09-14 16:50:29 +01004301 drm_gem_object_unreference(obj);
4302 mutex_unlock(&dev->struct_mutex);
4303
4304 return 0;
4305}
4306
Daniel Vetterac52bc52010-04-09 19:05:06 +00004307struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4308 size_t size)
4309{
Daniel Vetterc397b902010-04-09 19:05:07 +00004310 struct drm_i915_gem_object *obj;
4311
4312 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4313 if (obj == NULL)
4314 return NULL;
4315
4316 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4317 kfree(obj);
4318 return NULL;
4319 }
4320
4321 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4322 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4323
4324 obj->agp_type = AGP_USER_MEMORY;
Daniel Vetter62b8b212010-04-09 19:05:08 +00004325 obj->base.driver_private = NULL;
Daniel Vetterc397b902010-04-09 19:05:07 +00004326 obj->fence_reg = I915_FENCE_REG_NONE;
4327 INIT_LIST_HEAD(&obj->list);
4328 INIT_LIST_HEAD(&obj->gpu_write_list);
Daniel Vetterc397b902010-04-09 19:05:07 +00004329 obj->madv = I915_MADV_WILLNEED;
4330
4331 trace_i915_gem_object_create(&obj->base);
4332
4333 return &obj->base;
Daniel Vetterac52bc52010-04-09 19:05:06 +00004334}
4335
Eric Anholt673a3942008-07-30 12:06:12 -07004336int i915_gem_init_object(struct drm_gem_object *obj)
4337{
Daniel Vetterc397b902010-04-09 19:05:07 +00004338 BUG();
Jesse Barnesde151cf2008-11-12 10:03:55 -08004339
Eric Anholt673a3942008-07-30 12:06:12 -07004340 return 0;
4341}
4342
Chris Wilsonbe726152010-07-23 23:18:50 +01004343static void i915_gem_free_object_tail(struct drm_gem_object *obj)
4344{
4345 struct drm_device *dev = obj->dev;
4346 drm_i915_private_t *dev_priv = dev->dev_private;
4347 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4348 int ret;
4349
4350 ret = i915_gem_object_unbind(obj);
4351 if (ret == -ERESTARTSYS) {
4352 list_move(&obj_priv->list,
4353 &dev_priv->mm.deferred_free_list);
4354 return;
4355 }
4356
4357 if (obj_priv->mmap_offset)
4358 i915_gem_free_mmap_offset(obj);
4359
4360 drm_gem_object_release(obj);
4361
4362 kfree(obj_priv->page_cpu_valid);
4363 kfree(obj_priv->bit_17);
4364 kfree(obj_priv);
4365}
4366
Eric Anholt673a3942008-07-30 12:06:12 -07004367void i915_gem_free_object(struct drm_gem_object *obj)
4368{
Jesse Barnesde151cf2008-11-12 10:03:55 -08004369 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01004370 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004371
Chris Wilson1c5d22f2009-08-25 11:15:50 +01004372 trace_i915_gem_object_destroy(obj);
4373
Eric Anholt673a3942008-07-30 12:06:12 -07004374 while (obj_priv->pin_count > 0)
4375 i915_gem_object_unpin(obj);
4376
Dave Airlie71acb5e2008-12-30 20:31:46 +10004377 if (obj_priv->phys_obj)
4378 i915_gem_detach_phys_object(dev, obj);
4379
Chris Wilsonbe726152010-07-23 23:18:50 +01004380 i915_gem_free_object_tail(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004381}
4382
Jesse Barnes5669fca2009-02-17 15:13:31 -08004383int
Eric Anholt673a3942008-07-30 12:06:12 -07004384i915_gem_idle(struct drm_device *dev)
4385{
4386 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilson29105cc2010-01-07 10:39:13 +00004387 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07004388
Keith Packard6dbe2772008-10-14 21:41:13 -07004389 mutex_lock(&dev->struct_mutex);
4390
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004391 if (dev_priv->mm.suspended ||
Zou Nan haid1b851f2010-05-21 09:08:57 +08004392 (dev_priv->render_ring.gem_object == NULL) ||
4393 (HAS_BSD(dev) &&
4394 dev_priv->bsd_ring.gem_object == NULL)) {
Keith Packard6dbe2772008-10-14 21:41:13 -07004395 mutex_unlock(&dev->struct_mutex);
Eric Anholt673a3942008-07-30 12:06:12 -07004396 return 0;
Keith Packard6dbe2772008-10-14 21:41:13 -07004397 }
Eric Anholt673a3942008-07-30 12:06:12 -07004398
Chris Wilson29105cc2010-01-07 10:39:13 +00004399 ret = i915_gpu_idle(dev);
Keith Packard6dbe2772008-10-14 21:41:13 -07004400 if (ret) {
4401 mutex_unlock(&dev->struct_mutex);
Eric Anholt673a3942008-07-30 12:06:12 -07004402 return ret;
Keith Packard6dbe2772008-10-14 21:41:13 -07004403 }
Eric Anholt673a3942008-07-30 12:06:12 -07004404
Chris Wilson29105cc2010-01-07 10:39:13 +00004405 /* Under UMS, be paranoid and evict. */
4406 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01004407 ret = i915_gem_evict_inactive(dev);
Chris Wilson29105cc2010-01-07 10:39:13 +00004408 if (ret) {
4409 mutex_unlock(&dev->struct_mutex);
4410 return ret;
4411 }
4412 }
4413
4414 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4415 * We need to replace this with a semaphore, or something.
4416 * And not confound mm.suspended!
4417 */
4418 dev_priv->mm.suspended = 1;
Daniel Vetterbc0c7f12010-08-20 18:18:48 +02004419 del_timer_sync(&dev_priv->hangcheck_timer);
Chris Wilson29105cc2010-01-07 10:39:13 +00004420
4421 i915_kernel_lost_context(dev);
Keith Packard6dbe2772008-10-14 21:41:13 -07004422 i915_gem_cleanup_ringbuffer(dev);
Chris Wilson29105cc2010-01-07 10:39:13 +00004423
Keith Packard6dbe2772008-10-14 21:41:13 -07004424 mutex_unlock(&dev->struct_mutex);
4425
Chris Wilson29105cc2010-01-07 10:39:13 +00004426 /* Cancel the retire work handler, which should be idle now. */
4427 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4428
Eric Anholt673a3942008-07-30 12:06:12 -07004429 return 0;
4430}
4431
Jesse Barnese552eb72010-04-21 11:39:23 -07004432/*
4433 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4434 * over cache flushing.
4435 */
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004436static int
Jesse Barnese552eb72010-04-21 11:39:23 -07004437i915_gem_init_pipe_control(struct drm_device *dev)
4438{
4439 drm_i915_private_t *dev_priv = dev->dev_private;
4440 struct drm_gem_object *obj;
4441 struct drm_i915_gem_object *obj_priv;
4442 int ret;
4443
Eric Anholt34dc4d42010-05-07 14:30:03 -07004444 obj = i915_gem_alloc_object(dev, 4096);
Jesse Barnese552eb72010-04-21 11:39:23 -07004445 if (obj == NULL) {
4446 DRM_ERROR("Failed to allocate seqno page\n");
4447 ret = -ENOMEM;
4448 goto err;
4449 }
4450 obj_priv = to_intel_bo(obj);
4451 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4452
4453 ret = i915_gem_object_pin(obj, 4096);
4454 if (ret)
4455 goto err_unref;
4456
4457 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4458 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4459 if (dev_priv->seqno_page == NULL)
4460 goto err_unpin;
4461
4462 dev_priv->seqno_obj = obj;
4463 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4464
4465 return 0;
4466
4467err_unpin:
4468 i915_gem_object_unpin(obj);
4469err_unref:
4470 drm_gem_object_unreference(obj);
4471err:
4472 return ret;
4473}
4474
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004475
4476static void
Jesse Barnese552eb72010-04-21 11:39:23 -07004477i915_gem_cleanup_pipe_control(struct drm_device *dev)
4478{
4479 drm_i915_private_t *dev_priv = dev->dev_private;
4480 struct drm_gem_object *obj;
4481 struct drm_i915_gem_object *obj_priv;
4482
4483 obj = dev_priv->seqno_obj;
4484 obj_priv = to_intel_bo(obj);
4485 kunmap(obj_priv->pages[0]);
4486 i915_gem_object_unpin(obj);
4487 drm_gem_object_unreference(obj);
4488 dev_priv->seqno_obj = NULL;
4489
4490 dev_priv->seqno_page = NULL;
Eric Anholt673a3942008-07-30 12:06:12 -07004491}
4492
Eric Anholt673a3942008-07-30 12:06:12 -07004493int
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004494i915_gem_init_ringbuffer(struct drm_device *dev)
4495{
4496 drm_i915_private_t *dev_priv = dev->dev_private;
4497 int ret;
Chris Wilson68f95ba2010-05-27 13:18:22 +01004498
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004499 if (HAS_PIPE_CONTROL(dev)) {
4500 ret = i915_gem_init_pipe_control(dev);
4501 if (ret)
4502 return ret;
4503 }
Chris Wilson68f95ba2010-05-27 13:18:22 +01004504
Xiang, Haihao5c1143b2010-09-16 10:43:11 +08004505 ret = intel_init_render_ring_buffer(dev);
Chris Wilson68f95ba2010-05-27 13:18:22 +01004506 if (ret)
4507 goto cleanup_pipe_control;
4508
4509 if (HAS_BSD(dev)) {
Xiang, Haihao5c1143b2010-09-16 10:43:11 +08004510 ret = intel_init_bsd_ring_buffer(dev);
Chris Wilson68f95ba2010-05-27 13:18:22 +01004511 if (ret)
4512 goto cleanup_render_ring;
Zou Nan haid1b851f2010-05-21 09:08:57 +08004513 }
Chris Wilson68f95ba2010-05-27 13:18:22 +01004514
Chris Wilson6f392d52010-08-07 11:01:22 +01004515 dev_priv->next_seqno = 1;
4516
Chris Wilson68f95ba2010-05-27 13:18:22 +01004517 return 0;
4518
4519cleanup_render_ring:
4520 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4521cleanup_pipe_control:
4522 if (HAS_PIPE_CONTROL(dev))
4523 i915_gem_cleanup_pipe_control(dev);
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004524 return ret;
4525}
4526
4527void
4528i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4529{
4530 drm_i915_private_t *dev_priv = dev->dev_private;
4531
4532 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
Zou Nan haid1b851f2010-05-21 09:08:57 +08004533 if (HAS_BSD(dev))
4534 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004535 if (HAS_PIPE_CONTROL(dev))
4536 i915_gem_cleanup_pipe_control(dev);
4537}
4538
4539int
Eric Anholt673a3942008-07-30 12:06:12 -07004540i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4541 struct drm_file *file_priv)
4542{
4543 drm_i915_private_t *dev_priv = dev->dev_private;
4544 int ret;
4545
Jesse Barnes79e53942008-11-07 14:24:08 -08004546 if (drm_core_check_feature(dev, DRIVER_MODESET))
4547 return 0;
4548
Ben Gamariba1234d2009-09-14 17:48:47 -04004549 if (atomic_read(&dev_priv->mm.wedged)) {
Eric Anholt673a3942008-07-30 12:06:12 -07004550 DRM_ERROR("Reenabling wedged hardware, good luck\n");
Ben Gamariba1234d2009-09-14 17:48:47 -04004551 atomic_set(&dev_priv->mm.wedged, 0);
Eric Anholt673a3942008-07-30 12:06:12 -07004552 }
4553
Eric Anholt673a3942008-07-30 12:06:12 -07004554 mutex_lock(&dev->struct_mutex);
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08004555 dev_priv->mm.suspended = 0;
4556
4557 ret = i915_gem_init_ringbuffer(dev);
Wu Fengguangd816f6a2009-04-18 10:43:32 +08004558 if (ret != 0) {
4559 mutex_unlock(&dev->struct_mutex);
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08004560 return ret;
Wu Fengguangd816f6a2009-04-18 10:43:32 +08004561 }
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08004562
Zou Nan hai852835f2010-05-21 09:08:56 +08004563 BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
Zou Nan haid1b851f2010-05-21 09:08:57 +08004564 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
Eric Anholt673a3942008-07-30 12:06:12 -07004565 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4566 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
Zou Nan hai852835f2010-05-21 09:08:56 +08004567 BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
Zou Nan haid1b851f2010-05-21 09:08:57 +08004568 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
Eric Anholt673a3942008-07-30 12:06:12 -07004569 mutex_unlock(&dev->struct_mutex);
Kristian Høgsbergdbb19d32008-08-20 11:04:27 -04004570
Chris Wilson5f353082010-06-07 14:03:03 +01004571 ret = drm_irq_install(dev);
4572 if (ret)
4573 goto cleanup_ringbuffer;
Kristian Høgsbergdbb19d32008-08-20 11:04:27 -04004574
Eric Anholt673a3942008-07-30 12:06:12 -07004575 return 0;
Chris Wilson5f353082010-06-07 14:03:03 +01004576
4577cleanup_ringbuffer:
4578 mutex_lock(&dev->struct_mutex);
4579 i915_gem_cleanup_ringbuffer(dev);
4580 dev_priv->mm.suspended = 1;
4581 mutex_unlock(&dev->struct_mutex);
4582
4583 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -07004584}
4585
4586int
4587i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4588 struct drm_file *file_priv)
4589{
Jesse Barnes79e53942008-11-07 14:24:08 -08004590 if (drm_core_check_feature(dev, DRIVER_MODESET))
4591 return 0;
4592
Kristian Høgsbergdbb19d32008-08-20 11:04:27 -04004593 drm_irq_uninstall(dev);
Linus Torvaldse6890f62009-09-08 17:09:24 -07004594 return i915_gem_idle(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07004595}
4596
4597void
4598i915_gem_lastclose(struct drm_device *dev)
4599{
4600 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07004601
Eric Anholte806b492009-01-22 09:56:58 -08004602 if (drm_core_check_feature(dev, DRIVER_MODESET))
4603 return;
4604
Keith Packard6dbe2772008-10-14 21:41:13 -07004605 ret = i915_gem_idle(dev);
4606 if (ret)
4607 DRM_ERROR("failed to idle hardware: %d\n", ret);
Eric Anholt673a3942008-07-30 12:06:12 -07004608}
4609
4610void
4611i915_gem_load(struct drm_device *dev)
4612{
Grégoire Henryb5aa8a02009-06-23 15:41:02 +02004613 int i;
Eric Anholt673a3942008-07-30 12:06:12 -07004614 drm_i915_private_t *dev_priv = dev->dev_private;
4615
Eric Anholt673a3942008-07-30 12:06:12 -07004616 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
Daniel Vetter99fcb762010-02-07 16:20:18 +01004617 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
Eric Anholt673a3942008-07-30 12:06:12 -07004618 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
Eric Anholta09ba7f2009-08-29 12:49:51 -07004619 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
Chris Wilsonbe726152010-07-23 23:18:50 +01004620 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
Zou Nan hai852835f2010-05-21 09:08:56 +08004621 INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4622 INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
Zou Nan haid1b851f2010-05-21 09:08:57 +08004623 if (HAS_BSD(dev)) {
4624 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4625 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4626 }
Daniel Vetter007cc8a2010-04-28 11:02:31 +02004627 for (i = 0; i < 16; i++)
4628 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
Eric Anholt673a3942008-07-30 12:06:12 -07004629 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4630 i915_gem_retire_work_handler);
Chris Wilson31169712009-09-14 16:50:28 +01004631 spin_lock(&shrink_list_lock);
4632 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4633 spin_unlock(&shrink_list_lock);
4634
Dave Airlie94400122010-07-20 13:15:31 +10004635 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4636 if (IS_GEN3(dev)) {
4637 u32 tmp = I915_READ(MI_ARB_STATE);
4638 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4639 /* arb state is a masked write, so set bit + bit in mask */
4640 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4641 I915_WRITE(MI_ARB_STATE, tmp);
4642 }
4643 }
4644
Jesse Barnesde151cf2008-11-12 10:03:55 -08004645 /* Old X drivers will take 0-2 for front, back, depth buffers */
Eric Anholtb397c832010-01-26 09:43:10 -08004646 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4647 dev_priv->fence_reg_start = 3;
Jesse Barnesde151cf2008-11-12 10:03:55 -08004648
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004649 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
Jesse Barnesde151cf2008-11-12 10:03:55 -08004650 dev_priv->num_fence_regs = 16;
4651 else
4652 dev_priv->num_fence_regs = 8;
4653
Grégoire Henryb5aa8a02009-06-23 15:41:02 +02004654 /* Initialize fence registers to zero */
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004655 switch (INTEL_INFO(dev)->gen) {
4656 case 6:
4657 for (i = 0; i < 16; i++)
4658 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
4659 break;
4660 case 5:
4661 case 4:
Grégoire Henryb5aa8a02009-06-23 15:41:02 +02004662 for (i = 0; i < 16; i++)
4663 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004664 break;
4665 case 3:
Grégoire Henryb5aa8a02009-06-23 15:41:02 +02004666 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4667 for (i = 0; i < 8; i++)
4668 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004669 case 2:
4670 for (i = 0; i < 8; i++)
4671 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4672 break;
Grégoire Henryb5aa8a02009-06-23 15:41:02 +02004673 }
Eric Anholt673a3942008-07-30 12:06:12 -07004674 i915_gem_detect_bit_6_swizzle(dev);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004675 init_waitqueue_head(&dev_priv->pending_flip_queue);
Eric Anholt673a3942008-07-30 12:06:12 -07004676}
Dave Airlie71acb5e2008-12-30 20:31:46 +10004677
4678/*
4679 * Create a physically contiguous memory object for this object
4680 * e.g. for cursor + overlay regs
4681 */
Chris Wilson995b6762010-08-20 13:23:26 +01004682static int i915_gem_init_phys_object(struct drm_device *dev,
4683 int id, int size, int align)
Dave Airlie71acb5e2008-12-30 20:31:46 +10004684{
4685 drm_i915_private_t *dev_priv = dev->dev_private;
4686 struct drm_i915_gem_phys_object *phys_obj;
4687 int ret;
4688
4689 if (dev_priv->mm.phys_objs[id - 1] || !size)
4690 return 0;
4691
Eric Anholt9a298b22009-03-24 12:23:04 -07004692 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004693 if (!phys_obj)
4694 return -ENOMEM;
4695
4696 phys_obj->id = id;
4697
Chris Wilson6eeefaf2010-08-07 11:01:39 +01004698 phys_obj->handle = drm_pci_alloc(dev, size, align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004699 if (!phys_obj->handle) {
4700 ret = -ENOMEM;
4701 goto kfree_obj;
4702 }
4703#ifdef CONFIG_X86
4704 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4705#endif
4706
4707 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4708
4709 return 0;
4710kfree_obj:
Eric Anholt9a298b22009-03-24 12:23:04 -07004711 kfree(phys_obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004712 return ret;
4713}
4714
Chris Wilson995b6762010-08-20 13:23:26 +01004715static void i915_gem_free_phys_object(struct drm_device *dev, int id)
Dave Airlie71acb5e2008-12-30 20:31:46 +10004716{
4717 drm_i915_private_t *dev_priv = dev->dev_private;
4718 struct drm_i915_gem_phys_object *phys_obj;
4719
4720 if (!dev_priv->mm.phys_objs[id - 1])
4721 return;
4722
4723 phys_obj = dev_priv->mm.phys_objs[id - 1];
4724 if (phys_obj->cur_obj) {
4725 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4726 }
4727
4728#ifdef CONFIG_X86
4729 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4730#endif
4731 drm_pci_free(dev, phys_obj->handle);
4732 kfree(phys_obj);
4733 dev_priv->mm.phys_objs[id - 1] = NULL;
4734}
4735
4736void i915_gem_free_all_phys_object(struct drm_device *dev)
4737{
4738 int i;
4739
Dave Airlie260883c2009-01-22 17:58:49 +10004740 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
Dave Airlie71acb5e2008-12-30 20:31:46 +10004741 i915_gem_free_phys_object(dev, i);
4742}
4743
4744void i915_gem_detach_phys_object(struct drm_device *dev,
4745 struct drm_gem_object *obj)
4746{
4747 struct drm_i915_gem_object *obj_priv;
4748 int i;
4749 int ret;
4750 int page_count;
4751
Daniel Vetter23010e42010-03-08 13:35:02 +01004752 obj_priv = to_intel_bo(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004753 if (!obj_priv->phys_obj)
4754 return;
4755
Chris Wilson4bdadb92010-01-27 13:36:32 +00004756 ret = i915_gem_object_get_pages(obj, 0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004757 if (ret)
4758 goto out;
4759
4760 page_count = obj->size / PAGE_SIZE;
4761
4762 for (i = 0; i < page_count; i++) {
Eric Anholt856fa192009-03-19 14:10:50 -07004763 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004764 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4765
4766 memcpy(dst, src, PAGE_SIZE);
4767 kunmap_atomic(dst, KM_USER0);
4768 }
Eric Anholt856fa192009-03-19 14:10:50 -07004769 drm_clflush_pages(obj_priv->pages, page_count);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004770 drm_agp_chipset_flush(dev);
Chris Wilsond78b47b2009-06-17 21:52:49 +01004771
4772 i915_gem_object_put_pages(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004773out:
4774 obj_priv->phys_obj->cur_obj = NULL;
4775 obj_priv->phys_obj = NULL;
4776}
4777
4778int
4779i915_gem_attach_phys_object(struct drm_device *dev,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01004780 struct drm_gem_object *obj,
4781 int id,
4782 int align)
Dave Airlie71acb5e2008-12-30 20:31:46 +10004783{
4784 drm_i915_private_t *dev_priv = dev->dev_private;
4785 struct drm_i915_gem_object *obj_priv;
4786 int ret = 0;
4787 int page_count;
4788 int i;
4789
4790 if (id > I915_MAX_PHYS_OBJECT)
4791 return -EINVAL;
4792
Daniel Vetter23010e42010-03-08 13:35:02 +01004793 obj_priv = to_intel_bo(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004794
4795 if (obj_priv->phys_obj) {
4796 if (obj_priv->phys_obj->id == id)
4797 return 0;
4798 i915_gem_detach_phys_object(dev, obj);
4799 }
4800
Dave Airlie71acb5e2008-12-30 20:31:46 +10004801 /* create a new object */
4802 if (!dev_priv->mm.phys_objs[id - 1]) {
4803 ret = i915_gem_init_phys_object(dev, id,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01004804 obj->size, align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004805 if (ret) {
Linus Torvaldsaeb565d2009-01-26 10:01:53 -08004806 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004807 goto out;
4808 }
4809 }
4810
4811 /* bind to the object */
4812 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4813 obj_priv->phys_obj->cur_obj = obj;
4814
Chris Wilson4bdadb92010-01-27 13:36:32 +00004815 ret = i915_gem_object_get_pages(obj, 0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004816 if (ret) {
4817 DRM_ERROR("failed to get page list\n");
4818 goto out;
4819 }
4820
4821 page_count = obj->size / PAGE_SIZE;
4822
4823 for (i = 0; i < page_count; i++) {
Eric Anholt856fa192009-03-19 14:10:50 -07004824 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004825 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4826
4827 memcpy(dst, src, PAGE_SIZE);
4828 kunmap_atomic(src, KM_USER0);
4829 }
4830
Chris Wilsond78b47b2009-06-17 21:52:49 +01004831 i915_gem_object_put_pages(obj);
4832
Dave Airlie71acb5e2008-12-30 20:31:46 +10004833 return 0;
4834out:
4835 return ret;
4836}
4837
4838static int
4839i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4840 struct drm_i915_gem_pwrite *args,
4841 struct drm_file *file_priv)
4842{
Daniel Vetter23010e42010-03-08 13:35:02 +01004843 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004844 void *obj_addr;
4845 int ret;
4846 char __user *user_data;
4847
4848 user_data = (char __user *) (uintptr_t) args->data_ptr;
4849 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4850
Zhao Yakui44d98a62009-10-09 11:39:40 +08004851 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004852 ret = copy_from_user(obj_addr, user_data, args->size);
4853 if (ret)
4854 return -EFAULT;
4855
4856 drm_agp_chipset_flush(dev);
4857 return 0;
4858}
Eric Anholtb9624422009-06-03 07:27:35 +00004859
4860void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4861{
4862 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4863
4864 /* Clean up our request list when the client is going away, so that
4865 * later retire_requests won't dereference our soon-to-be-gone
4866 * file_priv.
4867 */
4868 mutex_lock(&dev->struct_mutex);
4869 while (!list_empty(&i915_file_priv->mm.request_list))
4870 list_del_init(i915_file_priv->mm.request_list.next);
4871 mutex_unlock(&dev->struct_mutex);
4872}
Chris Wilson31169712009-09-14 16:50:28 +01004873
Chris Wilson31169712009-09-14 16:50:28 +01004874static int
Chris Wilson1637ef42010-04-20 17:10:35 +01004875i915_gpu_is_active(struct drm_device *dev)
4876{
4877 drm_i915_private_t *dev_priv = dev->dev_private;
4878 int lists_empty;
4879
Chris Wilson1637ef42010-04-20 17:10:35 +01004880 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
Zou Nan hai852835f2010-05-21 09:08:56 +08004881 list_empty(&dev_priv->render_ring.active_list);
Zou Nan haid1b851f2010-05-21 09:08:57 +08004882 if (HAS_BSD(dev))
4883 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
Chris Wilson1637ef42010-04-20 17:10:35 +01004884
4885 return !lists_empty;
4886}
4887
4888static int
Dave Chinner7f8275d2010-07-19 14:56:17 +10004889i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
Chris Wilson31169712009-09-14 16:50:28 +01004890{
4891 drm_i915_private_t *dev_priv, *next_dev;
4892 struct drm_i915_gem_object *obj_priv, *next_obj;
4893 int cnt = 0;
4894 int would_deadlock = 1;
4895
4896 /* "fast-path" to count number of available objects */
4897 if (nr_to_scan == 0) {
4898 spin_lock(&shrink_list_lock);
4899 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4900 struct drm_device *dev = dev_priv->dev;
4901
4902 if (mutex_trylock(&dev->struct_mutex)) {
4903 list_for_each_entry(obj_priv,
4904 &dev_priv->mm.inactive_list,
4905 list)
4906 cnt++;
4907 mutex_unlock(&dev->struct_mutex);
4908 }
4909 }
4910 spin_unlock(&shrink_list_lock);
4911
4912 return (cnt / 100) * sysctl_vfs_cache_pressure;
4913 }
4914
4915 spin_lock(&shrink_list_lock);
4916
Chris Wilson1637ef42010-04-20 17:10:35 +01004917rescan:
Chris Wilson31169712009-09-14 16:50:28 +01004918 /* first scan for clean buffers */
4919 list_for_each_entry_safe(dev_priv, next_dev,
4920 &shrink_list, mm.shrink_list) {
4921 struct drm_device *dev = dev_priv->dev;
4922
4923 if (! mutex_trylock(&dev->struct_mutex))
4924 continue;
4925
4926 spin_unlock(&shrink_list_lock);
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01004927 i915_gem_retire_requests(dev);
Zou Nan haid1b851f2010-05-21 09:08:57 +08004928
Chris Wilson31169712009-09-14 16:50:28 +01004929 list_for_each_entry_safe(obj_priv, next_obj,
4930 &dev_priv->mm.inactive_list,
4931 list) {
4932 if (i915_gem_object_is_purgeable(obj_priv)) {
Daniel Vettera8089e82010-04-09 19:05:09 +00004933 i915_gem_object_unbind(&obj_priv->base);
Chris Wilson31169712009-09-14 16:50:28 +01004934 if (--nr_to_scan <= 0)
4935 break;
4936 }
4937 }
4938
4939 spin_lock(&shrink_list_lock);
4940 mutex_unlock(&dev->struct_mutex);
4941
Chris Wilson963b4832009-09-20 23:03:54 +01004942 would_deadlock = 0;
4943
Chris Wilson31169712009-09-14 16:50:28 +01004944 if (nr_to_scan <= 0)
4945 break;
4946 }
4947
4948 /* second pass, evict/count anything still on the inactive list */
4949 list_for_each_entry_safe(dev_priv, next_dev,
4950 &shrink_list, mm.shrink_list) {
4951 struct drm_device *dev = dev_priv->dev;
4952
4953 if (! mutex_trylock(&dev->struct_mutex))
4954 continue;
4955
4956 spin_unlock(&shrink_list_lock);
4957
4958 list_for_each_entry_safe(obj_priv, next_obj,
4959 &dev_priv->mm.inactive_list,
4960 list) {
4961 if (nr_to_scan > 0) {
Daniel Vettera8089e82010-04-09 19:05:09 +00004962 i915_gem_object_unbind(&obj_priv->base);
Chris Wilson31169712009-09-14 16:50:28 +01004963 nr_to_scan--;
4964 } else
4965 cnt++;
4966 }
4967
4968 spin_lock(&shrink_list_lock);
4969 mutex_unlock(&dev->struct_mutex);
4970
4971 would_deadlock = 0;
4972 }
4973
Chris Wilson1637ef42010-04-20 17:10:35 +01004974 if (nr_to_scan) {
4975 int active = 0;
4976
4977 /*
4978 * We are desperate for pages, so as a last resort, wait
4979 * for the GPU to finish and discard whatever we can.
4980 * This has a dramatic impact to reduce the number of
4981 * OOM-killer events whilst running the GPU aggressively.
4982 */
4983 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4984 struct drm_device *dev = dev_priv->dev;
4985
4986 if (!mutex_trylock(&dev->struct_mutex))
4987 continue;
4988
4989 spin_unlock(&shrink_list_lock);
4990
4991 if (i915_gpu_is_active(dev)) {
4992 i915_gpu_idle(dev);
4993 active++;
4994 }
4995
4996 spin_lock(&shrink_list_lock);
4997 mutex_unlock(&dev->struct_mutex);
4998 }
4999
5000 if (active)
5001 goto rescan;
5002 }
5003
Chris Wilson31169712009-09-14 16:50:28 +01005004 spin_unlock(&shrink_list_lock);
5005
5006 if (would_deadlock)
5007 return -1;
5008 else if (cnt > 0)
5009 return (cnt / 100) * sysctl_vfs_cache_pressure;
5010 else
5011 return 0;
5012}
5013
5014static struct shrinker shrinker = {
5015 .shrink = i915_gem_shrink,
5016 .seeks = DEFAULT_SEEKS,
5017};
5018
5019__init void
5020i915_gem_shrinker_init(void)
5021{
5022 register_shrinker(&shrinker);
5023}
5024
5025__exit void
5026i915_gem_shrinker_exit(void)
5027{
5028 unregister_shrinker(&shrinker);
5029}