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Jia Liu31d157a2012-02-18 12:03:15 +00001//===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===//
Anton Korobeynikovd49ea772009-06-26 21:28:53 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
David Goodwinb50ea5c2009-07-02 22:18:33 +000010// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000011//
12//===----------------------------------------------------------------------===//
13
Evan Chengb9803a82009-11-06 23:52:48 +000014#include "Thumb1InstrInfo.h"
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000015#include "ARM.h"
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000016#include "llvm/CodeGen/MachineFrameInfo.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
Evan Cheng2457f2c2010-05-22 01:47:14 +000018#include "llvm/CodeGen/MachineRegisterInfo.h"
Evan Chenge3ce8aa2009-11-01 22:04:35 +000019#include "llvm/CodeGen/MachineMemOperand.h"
Jim Grosbachc01810e2012-02-28 23:53:30 +000020#include "llvm/MC/MCInst.h"
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000021
22using namespace llvm;
23
Anton Korobeynikovf95215f2009-11-02 00:10:38 +000024Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
25 : ARMBaseInstrInfo(STI), RI(*this, STI) {
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000026}
27
Jim Grosbachc01810e2012-02-28 23:53:30 +000028/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
29void Thumb1InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
30 NopInst.setOpcode(ARM::tMOVr);
31 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
32 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
33 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
34 NopInst.addOperand(MCOperand::CreateReg(0));
35}
36
Evan Cheng446c4282009-07-11 06:43:01 +000037unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
David Goodwin334c2642009-07-08 16:09:28 +000038 return 0;
39}
40
Jakob Stoklund Olesenac273662010-07-11 06:33:54 +000041void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
42 MachineBasicBlock::iterator I, DebugLoc DL,
43 unsigned DestReg, unsigned SrcReg,
44 bool KillSrc) const {
Jim Grosbach2a7b41b2011-06-30 23:38:17 +000045 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
Jim Grosbach63b46fa2011-06-30 22:10:46 +000046 .addReg(SrcReg, getKillRegState(KillSrc)));
Jakob Stoklund Olesenac273662010-07-11 06:33:54 +000047 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
48 "Thumb1 can only copy GPR registers");
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000049}
50
David Goodwinb50ea5c2009-07-02 22:18:33 +000051void Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000052storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
53 unsigned SrcReg, bool isKill, int FI,
Evan Cheng746ad692010-05-06 19:06:44 +000054 const TargetRegisterClass *RC,
55 const TargetRegisterInfo *TRI) const {
Evan Cheng86e5f7b2009-08-13 05:40:51 +000056 assert((RC == ARM::tGPRRegisterClass ||
57 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
58 isARMLowRegister(SrcReg))) && "Unknown regclass!");
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000059
Jim Grosbach98793b92010-01-15 22:21:03 +000060 if (RC == ARM::tGPRRegisterClass ||
61 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
62 isARMLowRegister(SrcReg))) {
Evan Cheng746ad692010-05-06 19:06:44 +000063 DebugLoc DL;
64 if (I != MBB.end()) DL = I->getDebugLoc();
65
Evan Chenge3ce8aa2009-11-01 22:04:35 +000066 MachineFunction &MF = *MBB.getParent();
67 MachineFrameInfo &MFI = *MF.getFrameInfo();
68 MachineMemOperand *MMO =
Jay Foad978e0df2011-11-15 07:34:52 +000069 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
Chris Lattner59db5492010-09-21 04:39:43 +000070 MachineMemOperand::MOStore,
Evan Chenge3ce8aa2009-11-01 22:04:35 +000071 MFI.getObjectSize(FI),
72 MFI.getObjectAlignment(FI));
Jim Grosbach74472b42011-06-29 20:26:39 +000073 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi))
Evan Cheng446c4282009-07-11 06:43:01 +000074 .addReg(SrcReg, getKillRegState(isKill))
Evan Chenge3ce8aa2009-11-01 22:04:35 +000075 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000076 }
77}
78
David Goodwinb50ea5c2009-07-02 22:18:33 +000079void Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000080loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
81 unsigned DestReg, int FI,
Evan Cheng746ad692010-05-06 19:06:44 +000082 const TargetRegisterClass *RC,
83 const TargetRegisterInfo *TRI) const {
Evan Cheng86e5f7b2009-08-13 05:40:51 +000084 assert((RC == ARM::tGPRRegisterClass ||
85 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
86 isARMLowRegister(DestReg))) && "Unknown regclass!");
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000087
Jim Grosbach98793b92010-01-15 22:21:03 +000088 if (RC == ARM::tGPRRegisterClass ||
89 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
90 isARMLowRegister(DestReg))) {
Evan Cheng746ad692010-05-06 19:06:44 +000091 DebugLoc DL;
92 if (I != MBB.end()) DL = I->getDebugLoc();
93
Evan Chenge3ce8aa2009-11-01 22:04:35 +000094 MachineFunction &MF = *MBB.getParent();
95 MachineFrameInfo &MFI = *MF.getFrameInfo();
96 MachineMemOperand *MMO =
Jay Foad978e0df2011-11-15 07:34:52 +000097 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
Chris Lattner59db5492010-09-21 04:39:43 +000098 MachineMemOperand::MOLoad,
Evan Chenge3ce8aa2009-11-01 22:04:35 +000099 MFI.getObjectSize(FI),
100 MFI.getObjectAlignment(FI));
Jim Grosbach74472b42011-06-29 20:26:39 +0000101 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
Evan Chenge3ce8aa2009-11-01 22:04:35 +0000102 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000103 }
104}