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Jim Grosbach31c24bf2009-11-07 22:00:39 +00001//===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
Anton Korobeynikovd49ea772009-06-26 21:28:53 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
David Goodwinb50ea5c2009-07-02 22:18:33 +000010// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000011//
12//===----------------------------------------------------------------------===//
13
Evan Chengb9803a82009-11-06 23:52:48 +000014#include "Thumb1InstrInfo.h"
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000015#include "ARM.h"
16#include "ARMGenInstrInfo.inc"
17#include "ARMMachineFunctionInfo.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
Evan Cheng2457f2c2010-05-22 01:47:14 +000020#include "llvm/CodeGen/MachineRegisterInfo.h"
Evan Chenge3ce8aa2009-11-01 22:04:35 +000021#include "llvm/CodeGen/MachineMemOperand.h"
22#include "llvm/CodeGen/PseudoSourceValue.h"
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000023#include "llvm/ADT/SmallVector.h"
David Goodwinb50ea5c2009-07-02 22:18:33 +000024#include "Thumb1InstrInfo.h"
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000025
26using namespace llvm;
27
Anton Korobeynikovf95215f2009-11-02 00:10:38 +000028Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
29 : ARMBaseInstrInfo(STI), RI(*this, STI) {
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000030}
31
Evan Cheng446c4282009-07-11 06:43:01 +000032unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
David Goodwin334c2642009-07-08 16:09:28 +000033 return 0;
34}
35
Jakob Stoklund Olesenac273662010-07-11 06:33:54 +000036void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
37 MachineBasicBlock::iterator I, DebugLoc DL,
38 unsigned DestReg, unsigned SrcReg,
39 bool KillSrc) const {
40 bool tDest = ARM::tGPRRegClass.contains(DestReg);
41 bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
42 unsigned Opc = ARM::tMOVgpr2gpr;
43 if (tDest && tSrc)
44 Opc = ARM::tMOVr;
45 else if (tSrc)
46 Opc = ARM::tMOVtgpr2gpr;
47 else if (tDest)
48 Opc = ARM::tMOVgpr2tgpr;
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000049
Jakob Stoklund Olesenac273662010-07-11 06:33:54 +000050 BuildMI(MBB, I, DL, get(Opc), DestReg)
51 .addReg(SrcReg, getKillRegState(KillSrc));
52 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
53 "Thumb1 can only copy GPR registers");
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000054}
55
David Goodwinb50ea5c2009-07-02 22:18:33 +000056void Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000057storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
58 unsigned SrcReg, bool isKill, int FI,
Evan Cheng746ad692010-05-06 19:06:44 +000059 const TargetRegisterClass *RC,
60 const TargetRegisterInfo *TRI) const {
Evan Cheng86e5f7b2009-08-13 05:40:51 +000061 assert((RC == ARM::tGPRRegisterClass ||
62 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
63 isARMLowRegister(SrcReg))) && "Unknown regclass!");
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000064
Jim Grosbach98793b92010-01-15 22:21:03 +000065 if (RC == ARM::tGPRRegisterClass ||
66 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
67 isARMLowRegister(SrcReg))) {
Evan Cheng746ad692010-05-06 19:06:44 +000068 DebugLoc DL;
69 if (I != MBB.end()) DL = I->getDebugLoc();
70
Evan Chenge3ce8aa2009-11-01 22:04:35 +000071 MachineFunction &MF = *MBB.getParent();
72 MachineFrameInfo &MFI = *MF.getFrameInfo();
73 MachineMemOperand *MMO =
Chris Lattner59db5492010-09-21 04:39:43 +000074 MF.getMachineMemOperand(
75 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
76 MachineMemOperand::MOStore,
Evan Chenge3ce8aa2009-11-01 22:04:35 +000077 MFI.getObjectSize(FI),
78 MFI.getObjectAlignment(FI));
Evan Cheng446c4282009-07-11 06:43:01 +000079 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
80 .addReg(SrcReg, getKillRegState(isKill))
Evan Chenge3ce8aa2009-11-01 22:04:35 +000081 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000082 }
83}
84
David Goodwinb50ea5c2009-07-02 22:18:33 +000085void Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000086loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
87 unsigned DestReg, int FI,
Evan Cheng746ad692010-05-06 19:06:44 +000088 const TargetRegisterClass *RC,
89 const TargetRegisterInfo *TRI) const {
Evan Cheng86e5f7b2009-08-13 05:40:51 +000090 assert((RC == ARM::tGPRRegisterClass ||
91 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
92 isARMLowRegister(DestReg))) && "Unknown regclass!");
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000093
Jim Grosbach98793b92010-01-15 22:21:03 +000094 if (RC == ARM::tGPRRegisterClass ||
95 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
96 isARMLowRegister(DestReg))) {
Evan Cheng746ad692010-05-06 19:06:44 +000097 DebugLoc DL;
98 if (I != MBB.end()) DL = I->getDebugLoc();
99
Evan Chenge3ce8aa2009-11-01 22:04:35 +0000100 MachineFunction &MF = *MBB.getParent();
101 MachineFrameInfo &MFI = *MF.getFrameInfo();
102 MachineMemOperand *MMO =
Chris Lattner59db5492010-09-21 04:39:43 +0000103 MF.getMachineMemOperand(
104 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
105 MachineMemOperand::MOLoad,
Evan Chenge3ce8aa2009-11-01 22:04:35 +0000106 MFI.getObjectSize(FI),
107 MFI.getObjectAlignment(FI));
Evan Cheng446c4282009-07-11 06:43:01 +0000108 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
Evan Chenge3ce8aa2009-11-01 22:04:35 +0000109 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000110 }
111}