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3<html>
4<head>
5 <title>The LLVM Target-Independent Code Generator</title>
6 <link rel="stylesheet" href="llvm.css" type="text/css">
7</head>
8<body>
9
10<div class="doc_title">
11 The LLVM Target-Independent Code Generator
12</div>
13
14<ol>
15 <li><a href="#introduction">Introduction</a>
16 <ul>
17 <li><a href="#required">Required components in the code generator</a></li>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]18 <li><a href="#high-level-design">The high-level design of the code
19 generator</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]20 <li><a href="#tablegen">Using TableGen for target description</a></li>
21 </ul>
22 </li>
23 <li><a href="#targetdesc">Target description classes</a>
24 <ul>
25 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
26 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]27 <li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]28 <li><a href="#mregisterinfo">The <tt>MRegisterInfo</tt> class</a></li>
29 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
30 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]31 <li><a href="#targetsubtarget">The <tt>TargetSubtarget</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]32 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
33 </ul>
34 </li>
35 <li><a href="#codegendesc">Machine code description classes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]36 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]37 <li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]38 <li><a href="#machinebasicblock">The <tt>MachineBasicBlock</tt>
39 class</a></li>
40 <li><a href="#machinefunction">The <tt>MachineFunction</tt> class</a></li>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]41 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]42 </li>
43 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]44 <ul>
45 <li><a href="#instselect">Instruction Selection</a>
46 <ul>
47 <li><a href="#selectiondag_intro">Introduction to SelectionDAGs</a></li>
48 <li><a href="#selectiondag_process">SelectionDAG Code Generation
49 Process</a></li>
50 <li><a href="#selectiondag_build">Initial SelectionDAG
51 Construction</a></li>
52 <li><a href="#selectiondag_legalize">SelectionDAG Legalize Phase</a></li>
53 <li><a href="#selectiondag_optimize">SelectionDAG Optimization
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]54 Phase: the DAG Combiner</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]55 <li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]56 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]57 Phase</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]58 <li><a href="#selectiondag_future">Future directions for the
59 SelectionDAG</a></li>
60 </ul></li>
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]61 <li><a href="#liveintervals">Live Intervals</a>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]62 <ul>
63 <li><a href="#livevariable_analysis">Live Variable Analysis</a></li>
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]64 <li><a href="#liveintervals_analysis">Live Intervals Analysis</a></li>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]65 </ul></li>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]66 <li><a href="#regalloc">Register Allocation</a>
67 <ul>
68 <li><a href="#regAlloc_represent">How registers are represented in
69 LLVM</a></li>
70 <li><a href="#regAlloc_howTo">Mapping virtual registers to physical
71 registers</a></li>
72 <li><a href="#regAlloc_twoAddr">Handling two address instructions</a></li>
73 <li><a href="#regAlloc_ssaDecon">The SSA deconstruction phase</a></li>
74 <li><a href="#regAlloc_fold">Instruction folding</a></li>
75 <li><a href="#regAlloc_builtIn">Built in register allocators</a></li>
76 </ul></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]77 <li><a href="#codeemit">Code Emission</a>
78 <ul>
79 <li><a href="#codeemit_asm">Generating Assembly Code</a></li>
80 <li><a href="#codeemit_bin">Generating Binary Machine Code</a></li>
81 </ul></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]82 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]83 </li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]84 <li><a href="#targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]85 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]86 <li><a href="#x86">The X86 backend</a></li>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]87 <li><a href="#ppc">The PowerPC backend</a></li>
88 <ul>
89 <li><a href="#ppc_abi">LLVM PowerPC ABI</a></li>
90 <li><a href="#ppc_frame">Frame Layout</a></li>
91 <li><a href="#ppc_prolog">Prolog/Epilog</a></li>
92 <li><a href="#ppc_dynamic">Dynamic Allocation</a></li>
93 </ul>
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]94 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]95 </li>
96
97</ol>
98
99<div class="doc_author">
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]100 <p>Written by <a href="mailto:sabre@nondot.org">Chris Lattner</a>,
101 <a href="mailto:isanbard@gmail.com">Bill Wendling</a>, and
102 <a href="mailto:pronesto@gmail.com">Fernando Magno Quintao
103 Pereira</a></p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]104</div>
105
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]106<div class="doc_warning">
107 <p>Warning: This is a work in progress.</p>
108</div>
109
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]110<!-- *********************************************************************** -->
111<div class="doc_section">
112 <a name="introduction">Introduction</a>
113</div>
114<!-- *********************************************************************** -->
115
116<div class="doc_text">
117
118<p>The LLVM target-independent code generator is a framework that provides a
119suite of reusable components for translating the LLVM internal representation to
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]120the machine code for a specified target&mdash;either in assembly form (suitable
121for a static compiler) or in binary machine code format (usable for a JIT
122compiler). The LLVM target-independent code generator consists of five main
123components:</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]124
125<ol>
126<li><a href="#targetdesc">Abstract target description</a> interfaces which
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]127capture important properties about various aspects of the machine, independently
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]128of how they will be used. These interfaces are defined in
129<tt>include/llvm/Target/</tt>.</li>
130
131<li>Classes used to represent the <a href="#codegendesc">machine code</a> being
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]132generated for a target. These classes are intended to be abstract enough to
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]133represent the machine code for <i>any</i> target machine. These classes are
134defined in <tt>include/llvm/CodeGen/</tt>.</li>
135
136<li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
137various phases of native code generation (register allocation, scheduling, stack
138frame representation, etc). This code lives in <tt>lib/CodeGen/</tt>.</li>
139
140<li><a href="#targetimpls">Implementations of the abstract target description
141interfaces</a> for particular targets. These machine descriptions make use of
142the components provided by LLVM, and can optionally provide custom
143target-specific passes, to build complete code generators for a specific target.
144Target descriptions live in <tt>lib/Target/</tt>.</li>
145
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]146<li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
147completely target independent (it uses the <tt>TargetJITInfo</tt> structure to
148interface for target-specific issues. The code for the target-independent
149JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
150
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]151</ol>
152
153<p>
154Depending on which part of the code generator you are interested in working on,
155different pieces of this will be useful to you. In any case, you should be
156familiar with the <a href="#targetdesc">target description</a> and <a
157href="#codegendesc">machine code representation</a> classes. If you want to add
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]158a backend for a new target, you will need to <a href="#targetimpls">implement the
159target description</a> classes for your new target and understand the <a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]160href="LangRef.html">LLVM code representation</a>. If you are interested in
161implementing a new <a href="#codegenalgs">code generation algorithm</a>, it
162should only depend on the target-description and machine code representation
163classes, ensuring that it is portable.
164</p>
165
166</div>
167
168<!-- ======================================================================= -->
169<div class="doc_subsection">
170 <a name="required">Required components in the code generator</a>
171</div>
172
173<div class="doc_text">
174
175<p>The two pieces of the LLVM code generator are the high-level interface to the
176code generator and the set of reusable components that can be used to build
177target-specific backends. The two most important interfaces (<a
178href="#targetmachine"><tt>TargetMachine</tt></a> and <a
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]179href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]180required to be defined for a backend to fit into the LLVM system, but the others
181must be defined if the reusable code generator components are going to be
182used.</p>
183
184<p>This design has two important implications. The first is that LLVM can
185support completely non-traditional code generation targets. For example, the C
186backend does not require register allocation, instruction selection, or any of
187the other standard components provided by the system. As such, it only
188implements these two interfaces, and does its own thing. Another example of a
189code generator like this is a (purely hypothetical) backend that converts LLVM
190to the GCC RTL form and uses GCC to emit machine code for a target.</p>
191
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]192<p>This design also implies that it is possible to design and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]193implement radically different code generators in the LLVM system that do not
194make use of any of the built-in components. Doing so is not recommended at all,
195but could be required for radically different targets that do not fit into the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]196LLVM machine description model: FPGAs for example.</p>
Chris Lattner900bf8c2004-06-02 07:06:06 +0000[diff] [blame]197
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]198</div>
199
200<!-- ======================================================================= -->
201<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]202 <a name="high-level-design">The high-level design of the code generator</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]203</div>
204
205<div class="doc_text">
206
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]207<p>The LLVM target-independent code generator is designed to support efficient and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]208quality code generation for standard register-based microprocessors. Code
209generation in this model is divided into the following stages:</p>
210
211<ol>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]212<li><b><a href="#instselect">Instruction Selection</a></b> - This phase
213determines an efficient way to express the input LLVM code in the target
214instruction set.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]215This stage produces the initial code for the program in the target instruction
216set, then makes use of virtual registers in SSA form and physical registers that
217represent any required register assignments due to target constraints or calling
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]218conventions. This step turns the LLVM code into a DAG of target
219instructions.</li>
220
221<li><b><a href="#selectiondag_sched">Scheduling and Formation</a></b> - This
222phase takes the DAG of target instructions produced by the instruction selection
223phase, determines an ordering of the instructions, then emits the instructions
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]224as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering. Note
225that we describe this in the <a href="#instselect">instruction selection
226section</a> because it operates on a <a
227href="#selectiondag_intro">SelectionDAG</a>.
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]228</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]229
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]230<li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> - This
231optional stage consists of a series of machine-code optimizations that
232operate on the SSA-form produced by the instruction selector. Optimizations
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]233like modulo-scheduling or peephole optimization work here.
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]234</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]235
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]236<li><b><a href="#regalloc">Register Allocation</a></b> - The
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]237target code is transformed from an infinite virtual register file in SSA form
238to the concrete register file used by the target. This phase introduces spill
239code and eliminates all virtual register references from the program.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]240
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]241<li><b><a href="#proepicode">Prolog/Epilog Code Insertion</a></b> - Once the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]242machine code has been generated for the function and the amount of stack space
243required is known (used for LLVM alloca's and spill slots), the prolog and
244epilog code for the function can be inserted and "abstract stack location
245references" can be eliminated. This stage is responsible for implementing
246optimizations like frame-pointer elimination and stack packing.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]247
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]248<li><b><a href="#latemco">Late Machine Code Optimizations</a></b> - Optimizations
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]249that operate on "final" machine code can go here, such as spill code scheduling
250and peephole optimizations.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]251
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]252<li><b><a href="#codeemit">Code Emission</a></b> - The final stage actually
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]253puts out the code for the current function, either in the target assembler
254format or in machine code.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]255
256</ol>
257
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]258<p>The code generator is based on the assumption that the instruction selector
259will use an optimal pattern matching selector to create high-quality sequences of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]260native instructions. Alternative code generator designs based on pattern
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]261expansion and aggressive iterative peephole optimization are much slower. This
262design permits efficient compilation (important for JIT environments) and
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]263aggressive optimization (used when generating code offline) by allowing
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]264components of varying levels of sophistication to be used for any step of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]265compilation.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]266
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]267<p>In addition to these stages, target implementations can insert arbitrary
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]268target-specific passes into the flow. For example, the X86 target uses a
269special pass to handle the 80x87 floating point stack architecture. Other
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]270targets with unusual requirements can be supported with custom passes as
271needed.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]272
273</div>
274
275
276<!-- ======================================================================= -->
277<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]278 <a name="tablegen">Using TableGen for target description</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]279</div>
280
281<div class="doc_text">
282
Chris Lattner5489e932004-06-01 18:35:00 +0000[diff] [blame]283<p>The target description classes require a detailed description of the target
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]284architecture. These target descriptions often have a large amount of common
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]285information (e.g., an <tt>add</tt> instruction is almost identical to a
286<tt>sub</tt> instruction).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]287In order to allow the maximum amount of commonality to be factored out, the LLVM
288code generator uses the <a href="TableGenFundamentals.html">TableGen</a> tool to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]289describe big chunks of the target machine, which allows the use of
290domain-specific and target-specific abstractions to reduce the amount of
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]291repetition.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]292
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]293<p>As LLVM continues to be developed and refined, we plan to move more and more
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]294of the target description to the <tt>.td</tt> form. Doing so gives us a
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]295number of advantages. The most important is that it makes it easier to port
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]296LLVM because it reduces the amount of C++ code that has to be written, and the
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]297surface area of the code generator that needs to be understood before someone
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]298can get something working. Second, it makes it easier to change things. In
299particular, if tables and other things are all emitted by <tt>tblgen</tt>, we
300only need a change in one place (<tt>tblgen</tt>) to update all of the targets
301to a new interface.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]302
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]303</div>
304
305<!-- *********************************************************************** -->
306<div class="doc_section">
307 <a name="targetdesc">Target description classes</a>
308</div>
309<!-- *********************************************************************** -->
310
311<div class="doc_text">
312
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]313<p>The LLVM target description classes (located in the
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]314<tt>include/llvm/Target</tt> directory) provide an abstract description of the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]315target machine independent of any particular client. These classes are
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]316designed to capture the <i>abstract</i> properties of the target (such as the
317instructions and registers it has), and do not incorporate any particular pieces
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]318of code generation algorithms.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]319
320<p>All of the target description classes (except the <tt><a
321href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
322the concrete target implementation, and have virtual methods implemented. To
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]323get to these implementations, the <tt><a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]324href="#targetmachine">TargetMachine</a></tt> class provides accessors that
325should be implemented by the target.</p>
326
327</div>
328
329<!-- ======================================================================= -->
330<div class="doc_subsection">
331 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
332</div>
333
334<div class="doc_text">
335
336<p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
337access the target-specific implementations of the various target description
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]338classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
339<tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
340designed to be specialized by
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]341a concrete target implementation (e.g., <tt>X86TargetMachine</tt>) which
342implements the various virtual methods. The only required target description
343class is the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the
344code generator components are to be used, the other interfaces should be
345implemented as well.</p>
346
347</div>
348
349
350<!-- ======================================================================= -->
351<div class="doc_subsection">
352 <a name="targetdata">The <tt>TargetData</tt> class</a>
353</div>
354
355<div class="doc_text">
356
357<p>The <tt>TargetData</tt> class is the only required target description class,
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]358and it is the only class that is not extensible (you cannot derived a new
359class from it). <tt>TargetData</tt> specifies information about how the target
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]360lays out memory for structures, the alignment requirements for various data
361types, the size of pointers in the target, and whether the target is
362little-endian or big-endian.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]363
364</div>
365
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]366<!-- ======================================================================= -->
367<div class="doc_subsection">
368 <a name="targetlowering">The <tt>TargetLowering</tt> class</a>
369</div>
370
371<div class="doc_text">
372
373<p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
374selectors primarily to describe how LLVM code should be lowered to SelectionDAG
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]375operations. Among other things, this class indicates:</p>
376
377<ul>
378 <li>an initial register class to use for various <tt>ValueType</tt>s</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]379 <li>which operations are natively supported by the target machine</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]380 <li>the return type of <tt>setcc</tt> operations</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]381 <li>the type to use for shift amounts</li>
382 <li>various high-level characteristics, like whether it is profitable to turn
383 division by a constant into a multiplication sequence</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]384</ol>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]385
386</div>
387
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]388<!-- ======================================================================= -->
389<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]390 <a name="mregisterinfo">The <tt>MRegisterInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]391</div>
392
393<div class="doc_text">
394
395<p>The <tt>MRegisterInfo</tt> class (which will eventually be renamed to
396<tt>TargetRegisterInfo</tt>) is used to describe the register file of the
397target and any interactions between the registers.</p>
398
399<p>Registers in the code generator are represented in the code generator by
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]400unsigned integers. Physical registers (those that actually exist in the target
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]401description) are unique small numbers, and virtual registers are generally
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]402large. Note that register #0 is reserved as a flag value.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]403
404<p>Each register in the processor description has an associated
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]405<tt>TargetRegisterDesc</tt> entry, which provides a textual name for the
406register (used for assembly output and debugging dumps) and a set of aliases
407(used to indicate whether one register overlaps with another).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]408</p>
409
410<p>In addition to the per-register description, the <tt>MRegisterInfo</tt> class
411exposes a set of processor specific register classes (instances of the
412<tt>TargetRegisterClass</tt> class). Each register class contains sets of
413registers that have the same properties (for example, they are all 32-bit
414integer registers). Each SSA virtual register created by the instruction
415selector has an associated register class. When the register allocator runs, it
416replaces virtual registers with a physical register in the set.</p>
417
418<p>
419The target-specific implementations of these classes is auto-generated from a <a
420href="TableGenFundamentals.html">TableGen</a> description of the register file.
421</p>
422
423</div>
424
425<!-- ======================================================================= -->
426<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]427 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]428</div>
429
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]430<div class="doc_text">
431 <p>The <tt>TargetInstrInfo</tt> class is used to describe the machine
432 instructions supported by the target. It is essentially an array of
433 <tt>TargetInstrDescriptor</tt> objects, each of which describes one
434 instruction the target supports. Descriptors define things like the mnemonic
Chris Lattnera3079782005-07-19 03:37:48 +0000[diff] [blame]435 for the opcode, the number of operands, the list of implicit register uses
436 and defs, whether the instruction has certain target-independent properties
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]437 (accesses memory, is commutable, etc), and holds any target-specific
438 flags.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]439</div>
440
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]441<!-- ======================================================================= -->
442<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]443 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]444</div>
445
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]446<div class="doc_text">
447 <p>The <tt>TargetFrameInfo</tt> class is used to provide information about the
448 stack frame layout of the target. It holds the direction of stack growth,
449 the known stack alignment on entry to each function, and the offset to the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]450 local area. The offset to the local area is the offset from the stack
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]451 pointer on function entry to the first location where function data (local
452 variables, spill locations) can be stored.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]453</div>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]454
455<!-- ======================================================================= -->
456<div class="doc_subsection">
457 <a name="targetsubtarget">The <tt>TargetSubtarget</tt> class</a>
458</div>
459
460<div class="doc_text">
Jim Laskey82d61a12005-10-17 12:19:10 +0000[diff] [blame]461 <p>The <tt>TargetSubtarget</tt> class is used to provide information about the
462 specific chip set being targeted. A sub-target informs code generation of
463 which instructions are supported, instruction latencies and instruction
464 execution itinerary; i.e., which processing units are used, in what order, and
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]465 for how long.</p>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]466</div>
467
468
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]469<!-- ======================================================================= -->
470<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]471 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]472</div>
473
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]474<div class="doc_text">
475 <p>The <tt>TargetJITInfo</tt> class exposes an abstract interface used by the
476 Just-In-Time code generator to perform target-specific activities, such as
477 emitting stubs. If a <tt>TargetMachine</tt> supports JIT code generation, it
478 should provide one of these objects through the <tt>getJITInfo</tt>
479 method.</p>
480</div>
481
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]482<!-- *********************************************************************** -->
483<div class="doc_section">
484 <a name="codegendesc">Machine code description classes</a>
485</div>
486<!-- *********************************************************************** -->
487
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]488<div class="doc_text">
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]489
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]490<p>At the high-level, LLVM code is translated to a machine specific
491representation formed out of
492<a href="#machinefunction"><tt>MachineFunction</tt></a>,
493<a href="#machinebasicblock"><tt>MachineBasicBlock</tt></a>, and <a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]494href="#machineinstr"><tt>MachineInstr</tt></a> instances
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]495(defined in <tt>include/llvm/CodeGen</tt>). This representation is completely
496target agnostic, representing instructions in their most abstract form: an
497opcode and a series of operands. This representation is designed to support
498both an SSA representation for machine code, as well as a register allocated,
499non-SSA form.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]500
501</div>
502
503<!-- ======================================================================= -->
504<div class="doc_subsection">
505 <a name="machineinstr">The <tt>MachineInstr</tt> class</a>
506</div>
507
508<div class="doc_text">
509
510<p>Target machine instructions are represented as instances of the
511<tt>MachineInstr</tt> class. This class is an extremely abstract way of
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]512representing machine instructions. In particular, it only keeps track of
513an opcode number and a set of operands.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]514
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]515<p>The opcode number is a simple unsigned integer that only has meaning to a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]516specific backend. All of the instructions for a target should be defined in
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]517the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]518are auto-generated from this description. The <tt>MachineInstr</tt> class does
519not have any information about how to interpret the instruction (i.e., what the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]520semantics of the instruction are); for that you must refer to the
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]521<tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
522
523<p>The operands of a machine instruction can be of several different types:
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]524a register reference, a constant integer, a basic block reference, etc. In
525addition, a machine operand should be marked as a def or a use of the value
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]526(though only registers are allowed to be defs).</p>
527
528<p>By convention, the LLVM code generator orders instruction operands so that
529all register definitions come before the register uses, even on architectures
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]530that are normally printed in other orders. For example, the SPARC add
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]531instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
532and stores the result into the "%i3" register. In the LLVM code generator,
533the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the destination
534first.</p>
535
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]536<p>Keeping destination (definition) operands at the beginning of the operand
537list has several advantages. In particular, the debugging printer will print
538the instruction like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]539
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]540<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]541<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]542%r3 = add %i1, %i2
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]543</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]544</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]545
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]546<p>Also if the first operand is a def, it is easier to <a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]547href="#buildmi">create instructions</a> whose only def is the first
548operand.</p>
549
550</div>
551
552<!-- _______________________________________________________________________ -->
553<div class="doc_subsubsection">
554 <a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
555</div>
556
557<div class="doc_text">
558
559<p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
560located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
561<tt>BuildMI</tt> functions make it easy to build arbitrary machine
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]562instructions. Usage of the <tt>BuildMI</tt> functions look like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]563
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]564<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]565<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]566// Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
567// instruction. The '1' specifies how many operands will be added.
568MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]569
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]570// Create the same instr, but insert it at the end of a basic block.
571MachineBasicBlock &amp;MBB = ...
572BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]573
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]574// Create the same instr, but insert it before a specified iterator point.
575MachineBasicBlock::iterator MBBI = ...
576BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]577
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]578// Create a 'cmp Reg, 0' instruction, no destination reg.
579MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
580// Create an 'sahf' instruction which takes no operands and stores nothing.
581MI = BuildMI(X86::SAHF, 0);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]582
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]583// Create a self looping branch instruction.
584BuildMI(MBB, X86::JNE, 1).addMBB(&amp;MBB);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]585</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]586</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]587
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]588<p>The key thing to remember with the <tt>BuildMI</tt> functions is that you
589have to specify the number of operands that the machine instruction will take.
590This allows for efficient memory allocation. You also need to specify if
591operands default to be uses of values, not definitions. If you need to add a
592definition operand (other than the optional destination register), you must
593explicitly mark it as such:</p>
594
595<div class="doc_code">
596<pre>
597MI.addReg(Reg, MachineOperand::Def);
598</pre>
599</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]600
601</div>
602
603<!-- _______________________________________________________________________ -->
604<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]605 <a name="fixedregs">Fixed (preassigned) registers</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]606</div>
607
608<div class="doc_text">
609
610<p>One important issue that the code generator needs to be aware of is the
611presence of fixed registers. In particular, there are often places in the
612instruction stream where the register allocator <em>must</em> arrange for a
613particular value to be in a particular register. This can occur due to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]614limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]615with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like calling
616conventions. In any case, the instruction selector should emit code that
617copies a virtual register into or out of a physical register when needed.</p>
618
619<p>For example, consider this simple LLVM example:</p>
620
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]621<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]622<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]623int %test(int %X, int %Y) {
624 %Z = div int %X, %Y
625 ret int %Z
626}
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]627</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]628</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]629
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]630<p>The X86 instruction selector produces this machine code for the <tt>div</tt>
631and <tt>ret</tt> (use
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]632"<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to get this):</p>
633
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]634<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]635<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]636;; Start of div
637%EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
638%reg1027 = sar %reg1024, 31
639%EDX = mov %reg1027 ;; Sign extend X into EDX
640idiv %reg1025 ;; Divide by Y (in reg1025)
641%reg1026 = mov %EAX ;; Read the result (Z) out of EAX
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]642
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]643;; Start of ret
644%EAX = mov %reg1026 ;; 32-bit return value goes in EAX
645ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]646</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]647</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]648
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]649<p>By the end of code generation, the register allocator has coalesced
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]650the registers and deleted the resultant identity moves producing the
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]651following code:</p>
652
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]653<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]654<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]655;; X is in EAX, Y is in ECX
656mov %EAX, %EDX
657sar %EDX, 31
658idiv %ECX
659ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]660</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]661</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]662
663<p>This approach is extremely general (if it can handle the X86 architecture,
664it can handle anything!) and allows all of the target specific
665knowledge about the instruction stream to be isolated in the instruction
666selector. Note that physical registers should have a short lifetime for good
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]667code generation, and all physical registers are assumed dead on entry to and
668exit from basic blocks (before register allocation). Thus, if you need a value
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]669to be live across basic block boundaries, it <em>must</em> live in a virtual
670register.</p>
671
672</div>
673
674<!-- _______________________________________________________________________ -->
675<div class="doc_subsubsection">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]676 <a name="ssa">Machine code in SSA form</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]677</div>
678
679<div class="doc_text">
680
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]681<p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]682are maintained in SSA-form until register allocation happens. For the most
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]683part, this is trivially simple since LLVM is already in SSA form; LLVM PHI nodes
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]684become machine code PHI nodes, and virtual registers are only allowed to have a
685single definition.</p>
686
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]687<p>After register allocation, machine code is no longer in SSA-form because there
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]688are no virtual registers left in the code.</p>
689
690</div>
691
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]692<!-- ======================================================================= -->
693<div class="doc_subsection">
694 <a name="machinebasicblock">The <tt>MachineBasicBlock</tt> class</a>
695</div>
696
697<div class="doc_text">
698
699<p>The <tt>MachineBasicBlock</tt> class contains a list of machine instructions
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]700(<tt><a href="#machineinstr">MachineInstr</a></tt> instances). It roughly
701corresponds to the LLVM code input to the instruction selector, but there can be
702a one-to-many mapping (i.e. one LLVM basic block can map to multiple machine
703basic blocks). The <tt>MachineBasicBlock</tt> class has a
704"<tt>getBasicBlock</tt>" method, which returns the LLVM basic block that it
705comes from.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]706
707</div>
708
709<!-- ======================================================================= -->
710<div class="doc_subsection">
711 <a name="machinefunction">The <tt>MachineFunction</tt> class</a>
712</div>
713
714<div class="doc_text">
715
716<p>The <tt>MachineFunction</tt> class contains a list of machine basic blocks
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]717(<tt><a href="#machinebasicblock">MachineBasicBlock</a></tt> instances). It
718corresponds one-to-one with the LLVM function input to the instruction selector.
719In addition to a list of basic blocks, the <tt>MachineFunction</tt> contains a
720a <tt>MachineConstantPool</tt>, a <tt>MachineFrameInfo</tt>, a
721<tt>MachineFunctionInfo</tt>, a <tt>SSARegMap</tt>, and a set of live in and
722live out registers for the function. See
723<tt>include/llvm/CodeGen/MachineFunction.h</tt> for more information.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]724
725</div>
726
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]727<!-- *********************************************************************** -->
728<div class="doc_section">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]729 <a name="codegenalgs">Target-independent code generation algorithms</a>
730</div>
731<!-- *********************************************************************** -->
732
733<div class="doc_text">
734
735<p>This section documents the phases described in the <a
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]736href="#high-level-design">high-level design of the code generator</a>. It
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]737explains how they work and some of the rationale behind their design.</p>
738
739</div>
740
741<!-- ======================================================================= -->
742<div class="doc_subsection">
743 <a name="instselect">Instruction Selection</a>
744</div>
745
746<div class="doc_text">
747<p>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]748Instruction Selection is the process of translating LLVM code presented to the
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]749code generator into target-specific machine instructions. There are several
750well-known ways to do this in the literature. In LLVM there are two main forms:
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]751the SelectionDAG based instruction selector framework and an old-style 'simple'
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]752instruction selector, which effectively peephole selects each LLVM instruction
753into a series of machine instructions. We recommend that all targets use the
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]754SelectionDAG infrastructure.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]755</p>
756
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]757<p>Portions of the DAG instruction selector are generated from the target
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]758description (<tt>*.td</tt>) files. Our goal is for the entire instruction
759selector to be generated from these <tt>.td</tt> files.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]760</div>
761
762<!-- _______________________________________________________________________ -->
763<div class="doc_subsubsection">
764 <a name="selectiondag_intro">Introduction to SelectionDAGs</a>
765</div>
766
767<div class="doc_text">
768
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]769<p>The SelectionDAG provides an abstraction for code representation in a way
770that is amenable to instruction selection using automatic techniques
771(e.g. dynamic-programming based optimal pattern matching selectors). It is also
772well-suited to other phases of code generation; in particular,
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]773instruction scheduling (SelectionDAG's are very close to scheduling DAGs
774post-selection). Additionally, the SelectionDAG provides a host representation
775where a large variety of very-low-level (but target-independent)
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]776<a href="#selectiondag_optimize">optimizations</a> may be
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]777performed; ones which require extensive information about the instructions
778efficiently supported by the target.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]779
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]780<p>The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]781<tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]782operation code (Opcode) that indicates what operation the node performs and
783the operands to the operation.
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]784The various operation node types are described at the top of the
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]785<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt> file.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]786
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]787<p>Although most operations define a single value, each node in the graph may
788define multiple values. For example, a combined div/rem operation will define
789both the dividend and the remainder. Many other situations require multiple
790values as well. Each node also has some number of operands, which are edges
791to the node defining the used value. Because nodes may define multiple values,
792edges are represented by instances of the <tt>SDOperand</tt> class, which is
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]793a <tt>&lt;SDNode, unsigned&gt;</tt> pair, indicating the node and result
794value being used, respectively. Each value produced by an <tt>SDNode</tt> has
795an associated <tt>MVT::ValueType</tt> indicating what type the value is.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]796
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]797<p>SelectionDAGs contain two different kinds of values: those that represent
798data flow and those that represent control flow dependencies. Data values are
799simple edges with an integer or floating point value type. Control edges are
800represented as "chain" edges which are of type <tt>MVT::Other</tt>. These edges
801provide an ordering between nodes that have side effects (such as
802loads, stores, calls, returns, etc). All nodes that have side effects should
803take a token chain as input and produce a new one as output. By convention,
804token chain inputs are always operand #0, and chain results are always the last
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]805value produced by an operation.</p>
806
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]807<p>A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
808always a marker node with an Opcode of <tt>ISD::EntryToken</tt>. The Root node
809is the final side-effecting node in the token chain. For example, in a single
810basic block function it would be the return node.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]811
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]812<p>One important concept for SelectionDAGs is the notion of a "legal" vs.
813"illegal" DAG. A legal DAG for a target is one that only uses supported
814operations and supported types. On a 32-bit PowerPC, for example, a DAG with
815a value of type i1, i8, i16, or i64 would be illegal, as would a DAG that uses a
816SREM or UREM operation. The
817<a href="#selectiondag_legalize">legalize</a> phase is responsible for turning
818an illegal DAG into a legal DAG.</p>
819
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]820</div>
821
822<!-- _______________________________________________________________________ -->
823<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]824 <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]825</div>
826
827<div class="doc_text">
828
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]829<p>SelectionDAG-based instruction selection consists of the following steps:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]830
831<ol>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]832<li><a href="#selectiondag_build">Build initial DAG</a> - This stage
833 performs a simple translation from the input LLVM code to an illegal
834 SelectionDAG.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]835<li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> - This stage
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]836 performs simple optimizations on the SelectionDAG to simplify it, and
837 recognize meta instructions (like rotates and <tt>div</tt>/<tt>rem</tt>
838 pairs) for targets that support these meta operations. This makes the
839 resultant code more efficient and the <a href="#selectiondag_select">select
840 instructions from DAG</a> phase (below) simpler.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]841<li><a href="#selectiondag_legalize">Legalize SelectionDAG</a> - This stage
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]842 converts the illegal SelectionDAG to a legal SelectionDAG by eliminating
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]843 unsupported operations and data types.</li>
844<li><a href="#selectiondag_optimize">Optimize SelectionDAG (#2)</a> - This
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]845 second run of the SelectionDAG optimizes the newly legalized DAG to
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]846 eliminate inefficiencies introduced by legalization.</li>
847<li><a href="#selectiondag_select">Select instructions from DAG</a> - Finally,
848 the target instruction selector matches the DAG operations to target
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]849 instructions. This process translates the target-independent input DAG into
850 another DAG of target instructions.</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]851<li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]852 - The last phase assigns a linear order to the instructions in the
853 target-instruction DAG and emits them into the MachineFunction being
854 compiled. This step uses traditional prepass scheduling techniques.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]855</ol>
856
857<p>After all of these steps are complete, the SelectionDAG is destroyed and the
858rest of the code generation passes are run.</p>
859
Chris Lattnerdf921f02005-10-17 01:40:33 +0000[diff] [blame]860<p>One great way to visualize what is going on here is to take advantage of a
861few LLC command line options. In particular, the <tt>-view-isel-dags</tt>
862option pops up a window with the SelectionDAG input to the Select phase for all
863of the code compiled (if you only get errors printed to the console while using
864this, you probably <a href="ProgrammersManual.html#ViewGraph">need to configure
865your system</a> to add support for it). The <tt>-view-sched-dags</tt> option
866views the SelectionDAG output from the Select phase and input to the Scheduler
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]867phase.</p>
868
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]869</div>
870
871<!-- _______________________________________________________________________ -->
872<div class="doc_subsubsection">
873 <a name="selectiondag_build">Initial SelectionDAG Construction</a>
874</div>
875
876<div class="doc_text">
877
Bill Wendling16448772006-08-28 03:04:05 +0000[diff] [blame]878<p>The initial SelectionDAG is na&iuml;vely peephole expanded from the LLVM
879input by the <tt>SelectionDAGLowering</tt> class in the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]880<tt>lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp</tt> file. The intent of this
881pass is to expose as much low-level, target-specific details to the SelectionDAG
882as possible. This pass is mostly hard-coded (e.g. an LLVM <tt>add</tt> turns
883into an <tt>SDNode add</tt> while a <tt>geteelementptr</tt> is expanded into the
884obvious arithmetic). This pass requires target-specific hooks to lower calls,
885returns, varargs, etc. For these features, the
886<tt><a href="#targetlowering">TargetLowering</a></tt> interface is used.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]887
888</div>
889
890<!-- _______________________________________________________________________ -->
891<div class="doc_subsubsection">
892 <a name="selectiondag_legalize">SelectionDAG Legalize Phase</a>
893</div>
894
895<div class="doc_text">
896
897<p>The Legalize phase is in charge of converting a DAG to only use the types and
898operations that are natively supported by the target. This involves two major
899tasks:</p>
900
901<ol>
902<li><p>Convert values of unsupported types to values of supported types.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]903 <p>There are two main ways of doing this: converting small types to
904 larger types ("promoting"), and breaking up large integer types
905 into smaller ones ("expanding"). For example, a target might require
906 that all f32 values are promoted to f64 and that all i1/i8/i16 values
907 are promoted to i32. The same target might require that all i64 values
908 be expanded into i32 values. These changes can insert sign and zero
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]909 extensions as needed to make sure that the final code has the same
910 behavior as the input.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]911 <p>A target implementation tells the legalizer which types are supported
912 (and which register class to use for them) by calling the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]913 <tt>addRegisterClass</tt> method in its TargetLowering constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]914</li>
915
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]916<li><p>Eliminate operations that are not supported by the target.</p>
917 <p>Targets often have weird constraints, such as not supporting every
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]918 operation on every supported datatype (e.g. X86 does not support byte
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]919 conditional moves and PowerPC does not support sign-extending loads from
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]920 a 16-bit memory location). Legalize takes care of this by open-coding
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]921 another sequence of operations to emulate the operation ("expansion"), by
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]922 promoting one type to a larger type that supports the operation
923 ("promotion"), or by using a target-specific hook to implement the
924 legalization ("custom").</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]925 <p>A target implementation tells the legalizer which operations are not
926 supported (and which of the above three actions to take) by calling the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]927 <tt>setOperationAction</tt> method in its <tt>TargetLowering</tt>
928 constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]929</li>
930</ol>
931
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]932<p>Prior to the existance of the Legalize pass, we required that every target
933<a href="#selectiondag_optimize">selector</a> supported and handled every
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]934operator and type even if they are not natively supported. The introduction of
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]935the Legalize phase allows all of the cannonicalization patterns to be shared
936across targets, and makes it very easy to optimize the cannonicalized code
937because it is still in the form of a DAG.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]938
939</div>
940
941<!-- _______________________________________________________________________ -->
942<div class="doc_subsubsection">
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]943 <a name="selectiondag_optimize">SelectionDAG Optimization Phase: the DAG
944 Combiner</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]945</div>
946
947<div class="doc_text">
948
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]949<p>The SelectionDAG optimization phase is run twice for code generation: once
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]950immediately after the DAG is built and once after legalization. The first run
951of the pass allows the initial code to be cleaned up (e.g. performing
952optimizations that depend on knowing that the operators have restricted type
953inputs). The second run of the pass cleans up the messy code generated by the
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]954Legalize pass, which allows Legalize to be very simple (it can focus on making
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]955code legal instead of focusing on generating <em>good</em> and legal code).</p>
956
957<p>One important class of optimizations performed is optimizing inserted sign
958and zero extension instructions. We currently use ad-hoc techniques, but could
959move to more rigorous techniques in the future. Here are some good papers on
960the subject:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]961
962<p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]963 "<a href="http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html">Widening
964 integer arithmetic</a>"<br>
965 Kevin Redwine and Norman Ramsey<br>
966 International Conference on Compiler Construction (CC) 2004
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]967</p>
968
969
970<p>
971 "<a href="http://portal.acm.org/citation.cfm?doid=512529.512552">Effective
972 sign extension elimination</a>"<br>
973 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
974 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
975 and Implementation.
976</p>
977
978</div>
979
980<!-- _______________________________________________________________________ -->
981<div class="doc_subsubsection">
982 <a name="selectiondag_select">SelectionDAG Select Phase</a>
983</div>
984
985<div class="doc_text">
986
987<p>The Select phase is the bulk of the target-specific code for instruction
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]988selection. This phase takes a legal SelectionDAG as input, pattern matches the
989instructions supported by the target to this DAG, and produces a new DAG of
990target code. For example, consider the following LLVM fragment:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]991
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]992<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]993<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]994%t1 = add float %W, %X
995%t2 = mul float %t1, %Y
996%t3 = add float %t2, %Z
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]997</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]998</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]999
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1000<p>This LLVM code corresponds to a SelectionDAG that looks basically like
1001this:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1002
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1003<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1004<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1005(fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1006</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1007</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1008
Chris Lattnera1ff9312005-10-17 15:19:24 +0000[diff] [blame]1009<p>If a target supports floating point multiply-and-add (FMA) operations, one
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1010of the adds can be merged with the multiply. On the PowerPC, for example, the
1011output of the instruction selector might look like this DAG:</p>
1012
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1013<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1014<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1015(FMADDS (FADDS W, X), Y, Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1016</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1017</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1018
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1019<p>The <tt>FMADDS</tt> instruction is a ternary instruction that multiplies its
1020first two operands and adds the third (as single-precision floating-point
1021numbers). The <tt>FADDS</tt> instruction is a simple binary single-precision
1022add instruction. To perform this pattern match, the PowerPC backend includes
1023the following instruction definitions:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1024
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1025<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1026<pre>
1027def FMADDS : AForm_1&lt;59, 29,
1028 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1029 "fmadds $FRT, $FRA, $FRC, $FRB",
1030 [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1031 F4RC:$FRB))</b>]&gt;;
1032def FADDS : AForm_2&lt;59, 21,
1033 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1034 "fadds $FRT, $FRA, $FRB",
1035 [<b>(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))</b>]&gt;;
1036</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1037</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1038
1039<p>The portion of the instruction definition in bold indicates the pattern used
1040to match the instruction. The DAG operators (like <tt>fmul</tt>/<tt>fadd</tt>)
1041are defined in the <tt>lib/Target/TargetSelectionDAG.td</tt> file.
1042"<tt>F4RC</tt>" is the register class of the input and result values.<p>
1043
1044<p>The TableGen DAG instruction selector generator reads the instruction
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1045patterns in the <tt>.td</tt> file and automatically builds parts of the pattern
1046matching code for your target. It has the following strengths:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1047
1048<ul>
1049<li>At compiler-compiler time, it analyzes your instruction patterns and tells
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1050 you if your patterns make sense or not.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1051<li>It can handle arbitrary constraints on operands for the pattern match. In
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1052 particular, it is straight-forward to say things like "match any immediate
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1053 that is a 13-bit sign-extended value". For examples, see the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1054 <tt>immSExt16</tt> and related <tt>tblgen</tt> classes in the PowerPC
1055 backend.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1056<li>It knows several important identities for the patterns defined. For
1057 example, it knows that addition is commutative, so it allows the
1058 <tt>FMADDS</tt> pattern above to match "<tt>(fadd X, (fmul Y, Z))</tt>" as
1059 well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
1060 to specially handle this case.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1061<li>It has a full-featured type-inferencing system. In particular, you should
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1062 rarely have to explicitly tell the system what type parts of your patterns
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1063 are. In the <tt>FMADDS</tt> case above, we didn't have to tell
1064 <tt>tblgen</tt> that all of the nodes in the pattern are of type 'f32'. It
1065 was able to infer and propagate this knowledge from the fact that
1066 <tt>F4RC</tt> has type 'f32'.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1067<li>Targets can define their own (and rely on built-in) "pattern fragments".
1068 Pattern fragments are chunks of reusable patterns that get inlined into your
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1069 patterns during compiler-compiler time. For example, the integer
1070 "<tt>(not x)</tt>" operation is actually defined as a pattern fragment that
1071 expands as "<tt>(xor x, -1)</tt>", since the SelectionDAG does not have a
1072 native '<tt>not</tt>' operation. Targets can define their own short-hand
1073 fragments as they see fit. See the definition of '<tt>not</tt>' and
1074 '<tt>ineg</tt>' for examples.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1075<li>In addition to instructions, targets can specify arbitrary patterns that
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1076 map to one or more instructions using the 'Pat' class. For example,
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1077 the PowerPC has no way to load an arbitrary integer immediate into a
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1078 register in one instruction. To tell tblgen how to do this, it defines:
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1079 <br>
1080 <br>
1081 <div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1082 <pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1083// Arbitrary immediate support. Implement in terms of LIS/ORI.
1084def : Pat&lt;(i32 imm:$imm),
1085 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))&gt;;
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1086 </pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1087 </div>
1088 <br>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1089 If none of the single-instruction patterns for loading an immediate into a
1090 register match, this will be used. This rule says "match an arbitrary i32
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1091 immediate, turning it into an <tt>ORI</tt> ('or a 16-bit immediate') and an
1092 <tt>LIS</tt> ('load 16-bit immediate, where the immediate is shifted to the
1093 left 16 bits') instruction". To make this work, the
1094 <tt>LO16</tt>/<tt>HI16</tt> node transformations are used to manipulate the
1095 input immediate (in this case, take the high or low 16-bits of the
1096 immediate).</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1097<li>While the system does automate a lot, it still allows you to write custom
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1098 C++ code to match special cases if there is something that is hard to
1099 express.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1100</ul>
1101
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1102<p>While it has many strengths, the system currently has some limitations,
1103primarily because it is a work in progress and is not yet finished:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1104
1105<ul>
1106<li>Overall, there is no way to define or match SelectionDAG nodes that define
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1107 multiple values (e.g. <tt>ADD_PARTS</tt>, <tt>LOAD</tt>, <tt>CALL</tt>,
1108 etc). This is the biggest reason that you currently still <em>have to</em>
1109 write custom C++ code for your instruction selector.</li>
1110<li>There is no great way to support matching complex addressing modes yet. In
1111 the future, we will extend pattern fragments to allow them to define
1112 multiple values (e.g. the four operands of the <a href="#x86_memory">X86
1113 addressing mode</a>). In addition, we'll extend fragments so that a
1114 fragment can match multiple different patterns.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1115<li>We don't automatically infer flags like isStore/isLoad yet.</li>
1116<li>We don't automatically generate the set of supported registers and
1117 operations for the <a href="#"selectiondag_legalize>Legalizer</a> yet.</li>
1118<li>We don't have a way of tying in custom legalized nodes yet.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1119</ul>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1120
1121<p>Despite these limitations, the instruction selector generator is still quite
1122useful for most of the binary and logical operations in typical instruction
1123sets. If you run into any problems or can't figure out how to do something,
1124please let Chris know!</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1125
1126</div>
1127
1128<!-- _______________________________________________________________________ -->
1129<div class="doc_subsubsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1130 <a name="selectiondag_sched">SelectionDAG Scheduling and Formation Phase</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1131</div>
1132
1133<div class="doc_text">
1134
1135<p>The scheduling phase takes the DAG of target instructions from the selection
1136phase and assigns an order. The scheduler can pick an order depending on
1137various constraints of the machines (i.e. order for minimal register pressure or
1138try to cover instruction latencies). Once an order is established, the DAG is
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1139converted to a list of <tt><a href="#machineinstr">MachineInstr</a></tt>s and
1140the SelectionDAG is destroyed.</p>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1141
Jeff Cohen0b81cda2005-10-24 16:54:55 +0000[diff] [blame]1142<p>Note that this phase is logically separate from the instruction selection
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]1143phase, but is tied to it closely in the code because it operates on
1144SelectionDAGs.</p>
1145
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1146</div>
1147
1148<!-- _______________________________________________________________________ -->
1149<div class="doc_subsubsection">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1150 <a name="selectiondag_future">Future directions for the SelectionDAG</a>
1151</div>
1152
1153<div class="doc_text">
1154
1155<ol>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1156<li>Optional function-at-a-time selection.</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1157<li>Auto-generate entire selector from <tt>.td</tt> file.</li>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1158</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1159</ol>
1160
1161</div>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1162
1163<!-- ======================================================================= -->
1164<div class="doc_subsection">
1165 <a name="ssamco">SSA-based Machine Code Optimizations</a>
1166</div>
1167<div class="doc_text"><p>To Be Written</p></div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1168
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1169<!-- ======================================================================= -->
1170<div class="doc_subsection">
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1171 <a name="liveintervals">Live Intervals</a>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1172</div>
1173
1174<div class="doc_text">
1175
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1176<p>Live Intervals are the ranges (intervals) where a variable is <i>live</i>.
1177They are used by some <a href="#regalloc">register allocator</a> passes to
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1178determine if two or more virtual registers which require the same physical
Bill Wendling41b32522006-09-07 08:39:35 +0000[diff] [blame]1179register are live at the same point in the program (i.e., they conflict). When
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1180this situation occurs, one virtual register must be <i>spilled</i>.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1181
1182</div>
1183
1184<!-- _______________________________________________________________________ -->
1185<div class="doc_subsubsection">
1186 <a name="livevariable_analysis">Live Variable Analysis</a>
1187</div>
1188
1189<div class="doc_text">
1190
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1191<p>The first step in determining the live intervals of variables is to
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1192calculate the set of registers that are immediately dead after the
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1193instruction (i.e., the instruction calculates the value, but it is
1194never used) and the set of registers that are used by the instruction,
1195but are never used after the instruction (i.e., they are killed). Live
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1196variable information is computed for each <i>virtual</i> register and
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1197<i>register allocatable</i> physical register in the function. This
1198is done in a very efficient manner because it uses SSA to sparsely
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1199compute lifetime information for virtual registers (which are in SSA
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1200form) and only has to track physical registers within a block. Before
1201register allocation, LLVM can assume that physical registers are only
1202live within a single basic block. This allows it to do a single,
1203local analysis to resolve physical register lifetimes within each
1204basic block. If a physical register is not register allocatable (e.g.,
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1205a stack pointer or condition codes), it is not tracked.</p>
1206
1207<p>Physical registers may be live in to or out of a function. Live in values
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1208are typically arguments in registers. Live out values are typically return
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1209values in registers. Live in values are marked as such, and are given a dummy
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1210"defining" instruction during live intervals analysis. If the last basic block
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1211of a function is a <tt>return</tt>, then it's marked as using all live out
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1212values in the function.</p>
1213
1214<p><tt>PHI</tt> nodes need to be handled specially, because the calculation
1215of the live variable information from a depth first traversal of the CFG of
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1216the function won't guarantee that a virtual register used by the <tt>PHI</tt>
1217node is defined before it's used. When a <tt>PHI</tt> node is encounted, only
1218the definition is handled, because the uses will be handled in other basic
1219blocks.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1220
1221<p>For each <tt>PHI</tt> node of the current basic block, we simulate an
1222assignment at the end of the current basic block and traverse the successor
1223basic blocks. If a successor basic block has a <tt>PHI</tt> node and one of
1224the <tt>PHI</tt> node's operands is coming from the current basic block,
1225then the variable is marked as <i>alive</i> within the current basic block
1226and all of its predecessor basic blocks, until the basic block with the
1227defining instruction is encountered.</p>
1228
1229</div>
1230
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1231<!-- _______________________________________________________________________ -->
1232<div class="doc_subsubsection">
1233 <a name="liveintervals_analysis">Live Intervals Analysis</a>
1234</div>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1235
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1236<div class="doc_text">
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1237
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1238<p>We now have the information available to perform the live intervals analysis
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1239and build the live intervals themselves. We start off by numbering the basic
1240blocks and machine instructions. We then handle the "live-in" values. These
1241are in physical registers, so the physical register is assumed to be killed by
1242the end of the basic block. Live intervals for virtual registers are computed
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1243for some ordering of the machine instructions <tt>[1, N]</tt>. A live interval
1244is an interval <tt>[i, j)</tt>, where <tt>1 <= i <= j < N</tt>, for which a
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1245variable is live.</p>
1246
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1247<p><i><b>More to come...</b></i></p>
1248
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1249</ol>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1250
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1251</div>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1252
1253<!-- ======================================================================= -->
1254<div class="doc_subsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1255 <a name="regalloc">Register Allocation</a>
1256</div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1257
1258<div class="doc_text">
1259
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1260<p>The <i>Register Allocation problem</i> consists in mapping a program
1261<i>P<sub>v</sub></i>, that can use an unbounded number of virtual
1262registers, to a program <i>P<sub>p</sub></i> that contains a finite
1263(possibly small) number of physical registers. Each target architecture has
1264a different number of physical registers. If the number of physical
1265registers is not enough to accommodate all the virtual registers, some of
1266them will have to be mapped into memory. These virtuals are called
1267<i>spilled virtuals</i>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1268
1269</div>
1270
1271<!-- _______________________________________________________________________ -->
1272
1273<div class="doc_subsubsection">
1274 <a name="regAlloc_represent">How registers are represented in LLVM</a>
1275</div>
1276
1277<div class="doc_text">
1278
1279<p>In LLVM, physical registers are denoted by integer numbers that
1280normally range from 1 to 1023. To see how this numbering is defined
1281for a particular architecture, you can read the
1282<tt>GenRegisterNames.inc</tt> file for that architecture. For
1283instance, by inspecting
1284<tt>lib/Target/X86/X86GenRegisterNames.inc</tt> we see that the 32-bit
1285register <tt>EAX</tt> is denoted by 15, and the MMX register
1286<tt>MM0</tt> is mapped to 48.</p>
1287
1288<p>Some architectures contain registers that share the same physical
1289location. A notable example is the X86 platform. For instance, in the
1290X86 architecture, the registers <tt>EAX</tt>, <tt>AX</tt> and
1291<tt>AL</tt> share the first eight bits. These physical registers are
1292marked as <i>aliased</i> in LLVM. Given a particular architecture, you
1293can check which registers are aliased by inspecting its
1294<tt>RegisterInfo.td</tt> file. Moreover, the method
1295<tt>MRegisterInfo::getAliasSet(p_reg)</tt> returns an array containing
1296all the physical registers aliased to the register <tt>p_reg</tt>.</p>
1297
1298<p>Physical registers, in LLVM, are grouped in <i>Register Classes</i>.
1299Elements in the same register class are functionally equivalent, and can
1300be interchangeably used. Each virtual register can only be mapped to
1301physical registers of a particular class. For instance, in the X86
1302architecture, some virtuals can only be allocated to 8 bit registers.
1303A register class is described by <tt>TargetRegisterClass</tt> objects.
1304To discover if a virtual register is compatible with a given physical,
1305this code can be used:
1306</p>
1307
1308<div class="doc_code">
1309<pre>
1310bool RegMapping_Fer::compatible_class(MachineFunction &mf,
1311 unsigned v_reg,
1312 unsigned p_reg) {
1313 assert(MRegisterInfo::isPhysicalRegister(p_reg) &&
1314 "Target register must be physical");
1315 const TargetRegisterClass *trc = mf.getSSARegMap()->getRegClass(v_reg);
1316 return trc->contains(p_reg);
1317}
1318</pre>
1319</div>
1320
1321<p>Sometimes, mostly for debugging purposes, it is useful to change
1322the number of physical registers available in the target
1323architecture. This must be done statically, inside the
1324<tt>TargetRegsterInfo.td</tt> file. Just <tt>grep</tt> for
1325<tt>RegisterClass</tt>, the last parameter of which is a list of
1326registers. Just commenting some out is one simple way to avoid them
1327being used. A more polite way is to explicitly exclude some registers
1328from the <i>allocation order</i>. See the definition of the
1329<tt>GR</tt> register class in
1330<tt>lib/Target/IA64/IA64RegisterInfo.td</tt> for an example of this
1331(e.g., <tt>numReservedRegs</tt> registers are hidden.)</p>
1332
1333<p>Virtual registers are also denoted by integer numbers. Contrary to
1334physical registers, different virtual registers never share the same
1335number. The smallest virtual register is normally assigned the number
13361024. This may change, so, in order to know which is the first virtual
1337register, you should access
1338<tt>MRegisterInfo::FirstVirtualRegister</tt>. Any register whose
1339number is greater than or equal to
1340<tt>MRegisterInfo::FirstVirtualRegister</tt> is considered a virtual
1341register. Whereas physical registers are statically defined in a
1342<tt>TargetRegisterInfo.td</tt> file and cannot be created by the
1343application developer, that is not the case with virtual registers.
1344In order to create new virtual registers, use the method
1345<tt>SSARegMap::createVirtualRegister()</tt>. This method will return a
1346virtual register with the highest code.
1347</p>
1348
1349<p>Before register allocation, the operands of an instruction are
1350mostly virtual registers, although physical registers may also be
1351used. In order to check if a given machine operand is a register, use
1352the boolean function <tt>MachineOperand::isRegister()</tt>. To obtain
1353the integer code of a register, use
1354<tt>MachineOperand::getReg()</tt>. An instruction may define or use a
1355register. For instance, <tt>ADD reg:1026 := reg:1025 reg:1024</tt>
1356defines the registers 1024, and uses registers 1025 and 1026. Given a
1357register operand, the method <tt>MachineOperand::isUse()</tt> informs
1358if that register is being used by the instruction. The method
1359<tt>MachineOperand::isDef()</tt> informs if that registers is being
1360defined.</p>
1361
1362<p>We will call physical registers present in the LLVM bytecode before
1363register allocation <i>pre-colored registers</i>. Pre-colored
1364registers are used in many different situations, for instance, to pass
1365parameters of functions calls, and to store results of particular
1366instructions. There are two types of pre-colored registers: the ones
1367<i>implicitly</i> defined, and those <i>explicitly</i>
1368defined. Explicitly defined registers are normal operands, and can be
1369accessed with <tt>MachineInstr::getOperand(int)::getReg()</tt>. In
1370order to check which registers are implicitly defined by an
1371instruction, use the
1372<tt>TargetInstrInfo::get(opcode)::ImplicitDefs</tt>, where
1373<tt>opcode</tt> is the opcode of the target instruction. One important
1374difference between explicit and implicit physical registers is that
1375the latter are defined statically for each instruction, whereas the
1376former may vary depending on the program being compiled. For example,
1377an instruction that represents a function call will always implicitly
1378define or use the same set of physical registers. To read the
1379registers implicitly used by an instruction, use
1380<tt>TargetInstrInfo::get(opcode)::ImplicitUses</tt>. Pre-colored
1381registers impose constraints on any register allocation algorithm. The
1382register allocator must make sure that none of them is been
1383overwritten by the values of virtual registers while still alive.</p>
1384
1385</div>
1386
1387<!-- _______________________________________________________________________ -->
1388
1389<div class="doc_subsubsection">
1390 <a name="regAlloc_howTo">Mapping virtual registers to physical registers</a>
1391</div>
1392
1393<div class="doc_text">
1394
1395<p>There are two ways to map virtual registers to physical registers (or to
1396memory slots). The first way, that we will call <i>direct mapping</i>,
1397is based on the use of methods of the classes <tt>MRegisterInfo</tt>,
1398and <tt>MachineOperand</tt>. The second way, that we will call
1399<i>indirect mapping</i>, relies on the <tt>VirtRegMap</tt> class in
1400order to insert loads and stores sending and getting values to and from
1401memory.</p>
1402
1403<p>The direct mapping provides more flexibility to the developer of
1404the register allocator; however, it is more error prone, and demands
1405more implementation work. Basically, the programmer will have to
1406specify where load and store instructions should be inserted in the
1407target function being compiled in order to get and store values in
1408memory. To assign a physical register to a virtual register present in
1409a given operand, use <tt>MachineOperand::setReg(p_reg)</tt>. To insert
1410a store instruction, use
1411<tt>MRegisterInfo::storeRegToStackSlot(...)</tt>, and to insert a load
1412instruction, use <tt>MRegisterInfo::loadRegFromStackSlot</tt>.</p>
1413
1414<p>The indirect mapping shields the application developer from the
1415complexities of inserting load and store instructions. In order to map
1416a virtual register to a physical one, use
1417<tt>VirtRegMap::assignVirt2Phys(vreg, preg)</tt>. In order to map a
1418certain virtual register to memory, use
1419<tt>VirtRegMap::assignVirt2StackSlot(vreg)</tt>. This method will
1420return the stack slot where <tt>vreg</tt>'s value will be located. If
1421it is necessary to map another virtual register to the same stack
1422slot, use <tt>VirtRegMap::assignVirt2StackSlot(vreg,
1423stack_location)</tt>. One important point to consider when using the
1424indirect mapping, is that even if a virtual register is mapped to
1425memory, it still needs to be mapped to a physical register. This
1426physical register is the location where the virtual register is
1427supposed to be found before being stored or after being reloaded.</p>
1428
1429<p>If the indirect strategy is used, after all the virtual registers
1430have been mapped to physical registers or stack slots, it is necessary
1431to use a spiller object to place load and store instructions in the
1432code. Every virtual that has been mapped to a stack slot will be
1433stored to memory after been defined and will be loaded before being
1434used. The implementation of the spiller tries to recycle load/store
1435instructions, avoiding unnecessary instructions. For an example of how
1436to invoke the spiller, see
1437<tt>RegAllocLinearScan::runOnMachineFunction</tt> in
1438<tt>lib/CodeGen/RegAllocLinearScan.cpp</tt>.</p>
1439
1440</div>
1441
1442<!-- _______________________________________________________________________ -->
1443<div class="doc_subsubsection">
1444 <a name="regAlloc_twoAddr">Handling two address instructions</a>
1445</div>
1446
1447<div class="doc_text">
1448
1449<p>With very rare exceptions (e.g., function calls), the LLVM machine
1450code instructions are three address instructions. That is, each
1451instruction is expected to define at most one register, and to use at
1452most two registers. However, some architectures use two address
1453instructions. In this case, the defined register is also one of the
1454used register. For instance, an instruction such as <tt>ADD %EAX,
1455%EBX</tt>, in X86 is actually equivalent to <tt>%EAX = %EAX +
1456%EBX</tt>.</p>
1457
1458<p>In order to produce correct code, LLVM must convert three address
1459instructions that represent two address instructions into true two
1460address instructions. LLVM provides the pass
1461<tt>TwoAddressInstructionPass</tt> for this specific purpose. It must
1462be run before register allocation takes place. After its execution,
1463the resulting code may no longer be in SSA form. This happens, for
1464instance, in situations where an instruction such as <tt>%a = ADD %b
1465%c</tt> is converted to two instructions such as:</p>
1466
1467<div class="doc_code">
1468<pre>
1469%a = MOVE %b
1470%a = ADD %a %b
1471</pre>
1472</div>
1473
1474<p>Notice that, internally, the second instruction is represented as
1475<tt>ADD %a[def/use] %b</tt>. I.e., the register operand <tt>%a</tt> is
1476both used and defined by the instruction.</p>
1477
1478</div>
1479
1480<!-- _______________________________________________________________________ -->
1481<div class="doc_subsubsection">
1482 <a name="regAlloc_ssaDecon">The SSA deconstruction phase</a>
1483</div>
1484
1485<div class="doc_text">
1486
1487<p>An important transformation that happens during register allocation is called
1488the <i>SSA Deconstruction Phase</i>. The SSA form simplifies many
1489analyses that are performed on the control flow graph of
1490programs. However, traditional instruction sets do not implement
1491PHI instructions. Thus, in order to generate executable code, compilers
1492must replace PHI instructions with other instructions that preserve their
1493semantics.</p>
1494
1495<p>There are many ways in which PHI instructions can safely be removed
1496from the target code. The most traditional PHI deconstruction
1497algorithm replaces PHI instructions with copy instructions. That is
1498the strategy adopted by LLVM. The SSA deconstruction algorithm is
1499implemented in n<tt>lib/CodeGen/>PHIElimination.cpp</tt>. In order to
1500invoke this pass, the identifier <tt>PHIEliminationID</tt> must be
1501marked as required in the code of the register allocator.</p>
1502
1503</div>
1504
1505<!-- _______________________________________________________________________ -->
1506<div class="doc_subsubsection">
1507 <a name="regAlloc_fold">Instruction folding</a>
1508</div>
1509
1510<div class="doc_text">
1511
1512<p><i>Instruction folding</i> is an optimization performed during
1513register allocation that removes unnecessary copy instructions. For
1514instance, a sequence of instructions such as:</p>
1515
1516<div class="doc_code">
1517<pre>
1518%EBX = LOAD %mem_address
1519%EAX = COPY %EBX
1520</pre>
1521</div>
1522
1523<p>can be safely substituted by the single instruction:
1524
1525<div class="doc_code">
1526<pre>
1527%EAX = LOAD %mem_address
1528</pre>
1529</div>
1530
1531<p>Instructions can be folded with the
1532<tt>MRegisterInfo::foldMemoryOperand(...)</tt> method. Care must be
1533taken when folding instructions; a folded instruction can be quite
1534different from the original instruction. See
1535<tt>LiveIntervals::addIntervalsForSpills</tt> in
1536<tt>lib/CodeGen/LiveIntervalAnalysis.cpp</tt> for an example of its use.</p>
1537
1538</div>
1539
1540<!-- _______________________________________________________________________ -->
1541
1542<div class="doc_subsubsection">
1543 <a name="regAlloc_builtIn">Built in register allocators</a>
1544</div>
1545
1546<div class="doc_text">
1547
1548<p>The LLVM infrastructure provides the application developer with
1549three different register allocators:</p>
1550
1551<ul>
1552 <li><i>Simple</i> - This is a very simple implementation that does
1553 not keep values in registers across instructions. This register
1554 allocator immediately spills every value right after it is
1555 computed, and reloads all used operands from memory to temporary
1556 registers before each instruction.</li>
1557 <li><i>Local</i> - This register allocator is an improvement on the
1558 <i>Simple</i> implementation. It allocates registers on a basic
1559 block level, attempting to keep values in registers and reusing
1560 registers as appropriate.</li>
1561 <li><i>Linear Scan</i> - <i>The default allocator</i>. This is the
1562 well-know linear scan register allocator. Whereas the
1563 <i>Simple</i> and <i>Local</i> algorithms use a direct mapping
1564 implementation technique, the <i>Linear Scan</i> implementation
1565 uses a spiller in order to place load and stores.</li>
1566</ul>
1567
1568<p>The type of register allocator used in <tt>llc</tt> can be chosen with the
1569command line option <tt>-regalloc=...</tt>:</p>
1570
1571<div class="doc_code">
1572<pre>
1573$ llc -f -regalloc=simple file.bc -o sp.s;
1574$ llc -f -regalloc=local file.bc -o lc.s;
1575$ llc -f -regalloc=linearscan file.bc -o ln.s;
1576</pre>
1577</div>
1578
1579</div>
1580
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1581<!-- ======================================================================= -->
1582<div class="doc_subsection">
1583 <a name="proepicode">Prolog/Epilog Code Insertion</a>
1584</div>
1585<div class="doc_text"><p>To Be Written</p></div>
1586<!-- ======================================================================= -->
1587<div class="doc_subsection">
1588 <a name="latemco">Late Machine Code Optimizations</a>
1589</div>
1590<div class="doc_text"><p>To Be Written</p></div>
1591<!-- ======================================================================= -->
1592<div class="doc_subsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1593 <a name="codeemit">Code Emission</a>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1594</div>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1595<div class="doc_text"><p>To Be Written</p></div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1596<!-- _______________________________________________________________________ -->
1597<div class="doc_subsubsection">
1598 <a name="codeemit_asm">Generating Assembly Code</a>
1599</div>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1600<div class="doc_text"><p>To Be Written</p></div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1601<!-- _______________________________________________________________________ -->
1602<div class="doc_subsubsection">
1603 <a name="codeemit_bin">Generating Binary Machine Code</a>
1604</div>
1605
1606<div class="doc_text">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1607 <p>For the JIT or <tt>.o</tt> file writer</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1608</div>
1609
1610
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1611<!-- *********************************************************************** -->
1612<div class="doc_section">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1613 <a name="targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1614</div>
1615<!-- *********************************************************************** -->
1616
1617<div class="doc_text">
1618
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1619<p>This section of the document explains features or design decisions that
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1620are specific to the code generator for a particular target.</p>
1621
1622</div>
1623
1624
1625<!-- ======================================================================= -->
1626<div class="doc_subsection">
1627 <a name="x86">The X86 backend</a>
1628</div>
1629
1630<div class="doc_text">
1631
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1632<p>The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1633code generator currently targets a generic P6-like processor. As such, it
1634produces a few P6-and-above instructions (like conditional moves), but it does
1635not make use of newer features like MMX or SSE. In the future, the X86 backend
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1636will have sub-target support added for specific processor families and
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1637implementations.</p>
1638
1639</div>
1640
1641<!-- _______________________________________________________________________ -->
1642<div class="doc_subsubsection">
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1643 <a name="x86_tt">X86 Target Triples Supported</a>
1644</div>
1645
1646<div class="doc_text">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1647
1648<p>The following are the known target triples that are supported by the X86
1649backend. This is not an exhaustive list, and it would be useful to add those
1650that people test.</p>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1651
1652<ul>
1653<li><b>i686-pc-linux-gnu</b> - Linux</li>
1654<li><b>i386-unknown-freebsd5.3</b> - FreeBSD 5.3</li>
1655<li><b>i686-pc-cygwin</b> - Cygwin on Win32</li>
1656<li><b>i686-pc-mingw32</b> - MingW on Win32</li>
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]1657<li><b>i386-pc-mingw32msvc</b> - MingW crosscompiler on Linux</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1658<li><b>i686-apple-darwin*</b> - Apple Darwin on X86</li>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1659</ul>
1660
1661</div>
1662
1663<!-- _______________________________________________________________________ -->
1664<div class="doc_subsubsection">
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]1665 <a name="x86_cc">X86 Calling Conventions supported</a>
1666</div>
1667
1668
1669<div class="doc_text">
1670
1671<p>The folowing target-specific calling conventions are known to backend:</p>
1672
1673<ul>
1674<li><b>x86_StdCall</b> - stdcall calling convention seen on Microsoft Windows
1675platform (CC ID = 64).</li>
1676<li><b>x86_FastCall</b> - fastcall calling convention seen on Microsoft Windows
1677platform (CC ID = 65).</li>
1678</ul>
1679
1680</div>
1681
1682<!-- _______________________________________________________________________ -->
1683<div class="doc_subsubsection">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1684 <a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
1685</div>
1686
1687<div class="doc_text">
1688
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1689<p>The x86 has a very flexible way of accessing memory. It is capable of
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1690forming memory addresses of the following expression directly in integer
1691instructions (which use ModR/M addressing):</p>
1692
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1693<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1694<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1695Base + [1,2,4,8] * IndexReg + Disp32
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1696</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1697</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1698
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1699<p>In order to represent this, LLVM tracks no less than 4 operands for each
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1700memory operand of this form. This means that the "load" form of '<tt>mov</tt>'
1701has the following <tt>MachineOperand</tt>s in this order:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1702
1703<pre>
1704Index: 0 | 1 2 3 4
1705Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement
1706OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
1707</pre>
1708
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1709<p>Stores, and all other instructions, treat the four memory operands in the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1710same way and in the same order.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1711
1712</div>
1713
1714<!-- _______________________________________________________________________ -->
1715<div class="doc_subsubsection">
1716 <a name="x86_names">Instruction naming</a>
1717</div>
1718
1719<div class="doc_text">
1720
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1721<p>An instruction name consists of the base name, a default operand size, and a
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1722a character per operand with an optional special size. For example:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1723
1724<p>
1725<tt>ADD8rr</tt> -&gt; add, 8-bit register, 8-bit register<br>
1726<tt>IMUL16rmi</tt> -&gt; imul, 16-bit register, 16-bit memory, 16-bit immediate<br>
1727<tt>IMUL16rmi8</tt> -&gt; imul, 16-bit register, 16-bit memory, 8-bit immediate<br>
1728<tt>MOVSX32rm16</tt> -&gt; movsx, 32-bit register, 16-bit memory
1729</p>
1730
1731</div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1732
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]1733<!-- ======================================================================= -->
1734<div class="doc_subsection">
1735 <a name="ppc">The PowerPC backend</a>
1736</div>
1737
1738<div class="doc_text">
1739<p>The PowerPC code generator lives in the lib/Target/PowerPC directory. The
1740code generation is retargetable to several variations or <i>subtargets</i> of
1741the PowerPC ISA; including ppc32, ppc64 and altivec.
1742</p>
1743</div>
1744
1745<!-- _______________________________________________________________________ -->
1746<div class="doc_subsubsection">
1747 <a name="ppc_abi">LLVM PowerPC ABI</a>
1748</div>
1749
1750<div class="doc_text">
1751<p>LLVM follows the AIX PowerPC ABI, with two deviations. LLVM uses a PC
1752relative (PIC) or static addressing for accessing global values, so no TOC (r2)
1753is used. Second, r31 is used as a frame pointer to allow dynamic growth of a
1754stack frame. LLVM takes advantage of having no TOC to provide space to save
1755the frame pointer in the PowerPC linkage area of the caller frame. Other
1756details of PowerPC ABI can be found at <a
1757href="http://developer.apple.com/documentation/DeveloperTools/Conceptual/
1758LowLevelABI/Articles/32bitPowerPC.html" target="_blank">PowerPC ABI.</a> Note:
1759This link describes the 32 bit ABI. The 64 bit ABI is similar except space for
1760GPRs are 8 bytes wide (not 4) and r13 is reserved for system use.</p>
1761</div>
1762
1763<!-- _______________________________________________________________________ -->
1764<div class="doc_subsubsection">
1765 <a name="ppc_frame">Frame Layout</a>
1766</div>
1767
1768<div class="doc_text">
1769<p>The size of a PowerPC frame is usually fixed for the duration of a
1770function&apos;s invocation. Since the frame is fixed size, all references into
1771the frame can be accessed via fixed offsets from the stack pointer. The
1772exception to this is when dynamic alloca or variable sized arrays are present,
1773then a base pointer (r31) is used as a proxy for the stack pointer and stack
1774pointer is free to grow or shrink. A base pointer is also used if llvm-gcc is
1775not passed the -fomit-frame-pointer flag. The stack pointer is always aligned to
177616 bytes, so that space allocated for altivec vectors will be properly
1777aligned.</p>
1778<p>An invocation frame is layed out as follows (low memory at top);</p>
1779</div>
1780
1781<div class="doc_text">
1782<table class="layout">
1783 <tr>
1784 <td>Linkage<br><br></td>
1785 </tr>
1786 <tr>
1787 <td>Parameter area<br><br></td>
1788 </tr>
1789 <tr>
1790 <td>Dynamic area<br><br></td>
1791 </tr>
1792 <tr>
1793 <td>Locals area<br><br></td>
1794 </tr>
1795 <tr>
1796 <td>Saved registers area<br><br></td>
1797 </tr>
1798 <tr style="border-style: none hidden none hidden;">
1799 <td><br></td>
1800 </tr>
1801 <tr>
1802 <td>Previous Frame<br><br></td>
1803 </tr>
1804</table>
1805</div>
1806
1807<div class="doc_text">
1808<p>The <i>linkage</i> area is used by a callee to save special registers prior
1809to allocating its own frame. Only three entries are relevant to LLVM. The
1810first entry is the previous stack pointer (sp), aka link. This allows probing
1811tools like gdb or exception handlers to quickly scan the frames in the stack. A
1812function epilog can also use the link to pop the frame from the stack. The
1813third entry in the linkage area is used to save the return address from the lr
1814register. Finally, as mentioned above, the last entry is used to save the
1815previous frame pointer (r31.) The entries in the linkage area are the size of a
1816GPR, thus the linkage area is 24 bytes long in 32 bit mode and 48 bytes in 64
1817bit mode.</p>
1818</div>
1819
1820<div class="doc_text">
1821<p>32 bit linkage area</p>
1822<table class="layout">
1823 <tr>
1824 <td>0</td>
1825 <td>Saved SP (r1)</td>
1826 </tr>
1827 <tr>
1828 <td>4</td>
1829 <td>Saved CR</td>
1830 </tr>
1831 <tr>
1832 <td>8</td>
1833 <td>Saved LR</td>
1834 </tr>
1835 <tr>
1836 <td>12</td>
1837 <td>Reserved</td>
1838 </tr>
1839 <tr>
1840 <td>16</td>
1841 <td>Reserved</td>
1842 </tr>
1843 <tr>
1844 <td>20</td>
1845 <td>Saved FP (r31)</td>
1846 </tr>
1847</table>
1848</div>
1849
1850<div class="doc_text">
1851<p>64 bit linkage area</p>
1852<table class="layout">
1853 <tr>
1854 <td>0</td>
1855 <td>Saved SP (r1)</td>
1856 </tr>
1857 <tr>
1858 <td>8</td>
1859 <td>Saved CR</td>
1860 </tr>
1861 <tr>
1862 <td>16</td>
1863 <td>Saved LR</td>
1864 </tr>
1865 <tr>
1866 <td>24</td>
1867 <td>Reserved</td>
1868 </tr>
1869 <tr>
1870 <td>32</td>
1871 <td>Reserved</td>
1872 </tr>
1873 <tr>
1874 <td>40</td>
1875 <td>Saved FP (r31)</td>
1876 </tr>
1877</table>
1878</div>
1879
1880<div class="doc_text">
1881<p>The <i>parameter area</i> is used to store arguments being passed to a callee
1882function. Following the PowerPC ABI, the first few arguments are actually
1883passed in registers, with the space in the parameter area unused. However, if
1884there are not enough registers or the callee is a thunk or vararg function,
1885these register arguments can be spilled into the parameter area. Thus, the
1886parameter area must be large enough to store all the parameters for the largest
1887call sequence made by the caller. The size must also be mimimally large enough
1888to spill registers r3-r10. This allows callees blind to the call signature,
1889such as thunks and vararg functions, enough space to cache the argument
1890registers. Therefore, the parameter area is minimally 32 bytes (64 bytes in 64
1891bit mode.) Also note that since the parameter area is a fixed offset from the
1892top of the frame, that a callee can access its spilt arguments using fixed
1893offsets from the stack pointer (or base pointer.)</p>
1894</div>
1895
1896<div class="doc_text">
1897<p>Combining the information about the linkage, parameter areas and alignment. A
1898stack frame is minimally 64 bytes in 32 bit mode and 128 bytes in 64 bit
1899mode.</p>
1900</div>
1901
1902<div class="doc_text">
1903<p>The <i>dynamic area</i> starts out as size zero. If a function uses dynamic
1904alloca then space is added to the stack, the linkage and parameter areas are
1905shifted to top of stack, and the new space is available immediately below the
1906linkage and parameter areas. The cost of shifting the linkage and parameter
1907areas is minor since only the link value needs to be copied. The link value can
1908be easily fetched by adding the original frame size to the base pointer. Note
1909that allocations in the dynamic space need to observe 16 byte aligment.</p>
1910</div>
1911
1912<div class="doc_text">
1913<p>The <i>locals area</i> is where the llvm compiler reserves space for local
1914variables.</p>
1915</div>
1916
1917<div class="doc_text">
1918<p>The <i>saved registers area</i> is where the llvm compiler spills callee saved
1919registers on entry to the callee.</p>
1920</div>
1921
1922<!-- _______________________________________________________________________ -->
1923<div class="doc_subsubsection">
1924 <a name="ppc_prolog">Prolog/Epilog</a>
1925</div>
1926
1927<div class="doc_text">
1928<p>The llvm prolog and epilog are the same as described in the PowerPC ABI, with
1929the following exceptions. Callee saved registers are spilled after the frame is
1930created. This allows the llvm epilog/prolog support to be common with other
1931targets. The base pointer callee saved register r31 is saved in the TOC slot of
1932linkage area. This simplifies allocation of space for the base pointer and
1933makes it convenient to locate programatically and during debugging.</p>
1934</div>
1935
1936<!-- _______________________________________________________________________ -->
1937<div class="doc_subsubsection">
1938 <a name="ppc_dynamic">Dynamic Allocation</a>
1939</div>
1940
1941<div class="doc_text">
1942<p></p>
1943</div>
1944
1945<i>TODO - More to come.</i>
1946
1947
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