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4<head>
5 <title>The LLVM Target-Independent Code Generator</title>
6 <link rel="stylesheet" href="llvm.css" type="text/css">
7</head>
8<body>
9
10<div class="doc_title">
11 The LLVM Target-Independent Code Generator
12</div>
13
14<ol>
15 <li><a href="#introduction">Introduction</a>
16 <ul>
17 <li><a href="#required">Required components in the code generator</a></li>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]18 <li><a href="#high-level-design">The high-level design of the code
19 generator</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]20 <li><a href="#tablegen">Using TableGen for target description</a></li>
21 </ul>
22 </li>
23 <li><a href="#targetdesc">Target description classes</a>
24 <ul>
25 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
26 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]27 <li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]28 <li><a href="#mregisterinfo">The <tt>MRegisterInfo</tt> class</a></li>
29 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
30 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]31 <li><a href="#targetsubtarget">The <tt>TargetSubtarget</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]32 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
33 </ul>
34 </li>
35 <li><a href="#codegendesc">Machine code description classes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]36 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]37 <li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]38 <li><a href="#machinebasicblock">The <tt>MachineBasicBlock</tt>
39 class</a></li>
40 <li><a href="#machinefunction">The <tt>MachineFunction</tt> class</a></li>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]41 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]42 </li>
43 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]44 <ul>
45 <li><a href="#instselect">Instruction Selection</a>
46 <ul>
47 <li><a href="#selectiondag_intro">Introduction to SelectionDAGs</a></li>
48 <li><a href="#selectiondag_process">SelectionDAG Code Generation
49 Process</a></li>
50 <li><a href="#selectiondag_build">Initial SelectionDAG
51 Construction</a></li>
52 <li><a href="#selectiondag_legalize">SelectionDAG Legalize Phase</a></li>
53 <li><a href="#selectiondag_optimize">SelectionDAG Optimization
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]54 Phase: the DAG Combiner</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]55 <li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]56 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]57 Phase</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]58 <li><a href="#selectiondag_future">Future directions for the
59 SelectionDAG</a></li>
60 </ul></li>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame^]61 <li><a href="#liveinterval_analysis">Live Interval Analysis</a>
62 <ul>
63 <li><a href="#livevariable_analysis">Live Variable Analysis</a></li>
64 </ul></li>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]65 <li><a href="#regalloc">Register Allocation</a>
66 <ul>
67 <li><a href="#regAlloc_represent">How registers are represented in
68 LLVM</a></li>
69 <li><a href="#regAlloc_howTo">Mapping virtual registers to physical
70 registers</a></li>
71 <li><a href="#regAlloc_twoAddr">Handling two address instructions</a></li>
72 <li><a href="#regAlloc_ssaDecon">The SSA deconstruction phase</a></li>
73 <li><a href="#regAlloc_fold">Instruction folding</a></li>
74 <li><a href="#regAlloc_builtIn">Built in register allocators</a></li>
75 </ul></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]76 <li><a href="#codeemit">Code Emission</a>
77 <ul>
78 <li><a href="#codeemit_asm">Generating Assembly Code</a></li>
79 <li><a href="#codeemit_bin">Generating Binary Machine Code</a></li>
80 </ul></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]81 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]82 </li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]83 <li><a href="#targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]84 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]85 <li><a href="#x86">The X86 backend</a></li>
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]86 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]87 </li>
88
89</ol>
90
91<div class="doc_author">
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]92 <p>Written by <a href="mailto:sabre@nondot.org">Chris Lattner</a>,
93 <a href="mailto:isanbard@gmail.com">Bill Wendling</a>, and
94 <a href="mailto:pronesto@gmail.com">Fernando Magno Quintao
95 Pereira</a></p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]96</div>
97
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]98<div class="doc_warning">
99 <p>Warning: This is a work in progress.</p>
100</div>
101
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]102<!-- *********************************************************************** -->
103<div class="doc_section">
104 <a name="introduction">Introduction</a>
105</div>
106<!-- *********************************************************************** -->
107
108<div class="doc_text">
109
110<p>The LLVM target-independent code generator is a framework that provides a
111suite of reusable components for translating the LLVM internal representation to
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]112the machine code for a specified target&mdash;either in assembly form (suitable
113for a static compiler) or in binary machine code format (usable for a JIT
114compiler). The LLVM target-independent code generator consists of five main
115components:</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]116
117<ol>
118<li><a href="#targetdesc">Abstract target description</a> interfaces which
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]119capture important properties about various aspects of the machine, independently
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]120of how they will be used. These interfaces are defined in
121<tt>include/llvm/Target/</tt>.</li>
122
123<li>Classes used to represent the <a href="#codegendesc">machine code</a> being
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]124generated for a target. These classes are intended to be abstract enough to
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]125represent the machine code for <i>any</i> target machine. These classes are
126defined in <tt>include/llvm/CodeGen/</tt>.</li>
127
128<li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
129various phases of native code generation (register allocation, scheduling, stack
130frame representation, etc). This code lives in <tt>lib/CodeGen/</tt>.</li>
131
132<li><a href="#targetimpls">Implementations of the abstract target description
133interfaces</a> for particular targets. These machine descriptions make use of
134the components provided by LLVM, and can optionally provide custom
135target-specific passes, to build complete code generators for a specific target.
136Target descriptions live in <tt>lib/Target/</tt>.</li>
137
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]138<li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
139completely target independent (it uses the <tt>TargetJITInfo</tt> structure to
140interface for target-specific issues. The code for the target-independent
141JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
142
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]143</ol>
144
145<p>
146Depending on which part of the code generator you are interested in working on,
147different pieces of this will be useful to you. In any case, you should be
148familiar with the <a href="#targetdesc">target description</a> and <a
149href="#codegendesc">machine code representation</a> classes. If you want to add
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]150a backend for a new target, you will need to <a href="#targetimpls">implement the
151target description</a> classes for your new target and understand the <a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]152href="LangRef.html">LLVM code representation</a>. If you are interested in
153implementing a new <a href="#codegenalgs">code generation algorithm</a>, it
154should only depend on the target-description and machine code representation
155classes, ensuring that it is portable.
156</p>
157
158</div>
159
160<!-- ======================================================================= -->
161<div class="doc_subsection">
162 <a name="required">Required components in the code generator</a>
163</div>
164
165<div class="doc_text">
166
167<p>The two pieces of the LLVM code generator are the high-level interface to the
168code generator and the set of reusable components that can be used to build
169target-specific backends. The two most important interfaces (<a
170href="#targetmachine"><tt>TargetMachine</tt></a> and <a
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]171href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]172required to be defined for a backend to fit into the LLVM system, but the others
173must be defined if the reusable code generator components are going to be
174used.</p>
175
176<p>This design has two important implications. The first is that LLVM can
177support completely non-traditional code generation targets. For example, the C
178backend does not require register allocation, instruction selection, or any of
179the other standard components provided by the system. As such, it only
180implements these two interfaces, and does its own thing. Another example of a
181code generator like this is a (purely hypothetical) backend that converts LLVM
182to the GCC RTL form and uses GCC to emit machine code for a target.</p>
183
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]184<p>This design also implies that it is possible to design and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]185implement radically different code generators in the LLVM system that do not
186make use of any of the built-in components. Doing so is not recommended at all,
187but could be required for radically different targets that do not fit into the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]188LLVM machine description model: FPGAs for example.</p>
Chris Lattner900bf8c2004-06-02 07:06:06 +0000[diff] [blame]189
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]190</div>
191
192<!-- ======================================================================= -->
193<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]194 <a name="high-level-design">The high-level design of the code generator</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]195</div>
196
197<div class="doc_text">
198
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]199<p>The LLVM target-independent code generator is designed to support efficient and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]200quality code generation for standard register-based microprocessors. Code
201generation in this model is divided into the following stages:</p>
202
203<ol>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]204<li><b><a href="#instselect">Instruction Selection</a></b> - This phase
205determines an efficient way to express the input LLVM code in the target
206instruction set.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]207This stage produces the initial code for the program in the target instruction
208set, then makes use of virtual registers in SSA form and physical registers that
209represent any required register assignments due to target constraints or calling
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]210conventions. This step turns the LLVM code into a DAG of target
211instructions.</li>
212
213<li><b><a href="#selectiondag_sched">Scheduling and Formation</a></b> - This
214phase takes the DAG of target instructions produced by the instruction selection
215phase, determines an ordering of the instructions, then emits the instructions
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]216as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering. Note
217that we describe this in the <a href="#instselect">instruction selection
218section</a> because it operates on a <a
219href="#selectiondag_intro">SelectionDAG</a>.
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]220</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]221
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]222<li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> - This
223optional stage consists of a series of machine-code optimizations that
224operate on the SSA-form produced by the instruction selector. Optimizations
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]225like modulo-scheduling or peephole optimization work here.
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]226</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]227
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]228<li><b><a href="#regalloc">Register Allocation</a></b> - The
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]229target code is transformed from an infinite virtual register file in SSA form
230to the concrete register file used by the target. This phase introduces spill
231code and eliminates all virtual register references from the program.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]232
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]233<li><b><a href="#proepicode">Prolog/Epilog Code Insertion</a></b> - Once the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]234machine code has been generated for the function and the amount of stack space
235required is known (used for LLVM alloca's and spill slots), the prolog and
236epilog code for the function can be inserted and "abstract stack location
237references" can be eliminated. This stage is responsible for implementing
238optimizations like frame-pointer elimination and stack packing.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]239
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]240<li><b><a href="#latemco">Late Machine Code Optimizations</a></b> - Optimizations
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]241that operate on "final" machine code can go here, such as spill code scheduling
242and peephole optimizations.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]243
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]244<li><b><a href="#codeemit">Code Emission</a></b> - The final stage actually
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]245puts out the code for the current function, either in the target assembler
246format or in machine code.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]247
248</ol>
249
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]250<p>The code generator is based on the assumption that the instruction selector
251will use an optimal pattern matching selector to create high-quality sequences of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]252native instructions. Alternative code generator designs based on pattern
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]253expansion and aggressive iterative peephole optimization are much slower. This
254design permits efficient compilation (important for JIT environments) and
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]255aggressive optimization (used when generating code offline) by allowing
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]256components of varying levels of sophistication to be used for any step of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]257compilation.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]258
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]259<p>In addition to these stages, target implementations can insert arbitrary
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]260target-specific passes into the flow. For example, the X86 target uses a
261special pass to handle the 80x87 floating point stack architecture. Other
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]262targets with unusual requirements can be supported with custom passes as
263needed.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]264
265</div>
266
267
268<!-- ======================================================================= -->
269<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]270 <a name="tablegen">Using TableGen for target description</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]271</div>
272
273<div class="doc_text">
274
Chris Lattner5489e932004-06-01 18:35:00 +0000[diff] [blame]275<p>The target description classes require a detailed description of the target
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]276architecture. These target descriptions often have a large amount of common
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]277information (e.g., an <tt>add</tt> instruction is almost identical to a
278<tt>sub</tt> instruction).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]279In order to allow the maximum amount of commonality to be factored out, the LLVM
280code generator uses the <a href="TableGenFundamentals.html">TableGen</a> tool to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]281describe big chunks of the target machine, which allows the use of
282domain-specific and target-specific abstractions to reduce the amount of
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]283repetition.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]284
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]285<p>As LLVM continues to be developed and refined, we plan to move more and more
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]286of the target description to the <tt>.td</tt> form. Doing so gives us a
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]287number of advantages. The most important is that it makes it easier to port
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]288LLVM because it reduces the amount of C++ code that has to be written, and the
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]289surface area of the code generator that needs to be understood before someone
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]290can get something working. Second, it makes it easier to change things. In
291particular, if tables and other things are all emitted by <tt>tblgen</tt>, we
292only need a change in one place (<tt>tblgen</tt>) to update all of the targets
293to a new interface.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]294
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]295</div>
296
297<!-- *********************************************************************** -->
298<div class="doc_section">
299 <a name="targetdesc">Target description classes</a>
300</div>
301<!-- *********************************************************************** -->
302
303<div class="doc_text">
304
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]305<p>The LLVM target description classes (located in the
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]306<tt>include/llvm/Target</tt> directory) provide an abstract description of the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]307target machine independent of any particular client. These classes are
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]308designed to capture the <i>abstract</i> properties of the target (such as the
309instructions and registers it has), and do not incorporate any particular pieces
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]310of code generation algorithms.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]311
312<p>All of the target description classes (except the <tt><a
313href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
314the concrete target implementation, and have virtual methods implemented. To
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]315get to these implementations, the <tt><a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]316href="#targetmachine">TargetMachine</a></tt> class provides accessors that
317should be implemented by the target.</p>
318
319</div>
320
321<!-- ======================================================================= -->
322<div class="doc_subsection">
323 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
324</div>
325
326<div class="doc_text">
327
328<p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
329access the target-specific implementations of the various target description
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]330classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
331<tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
332designed to be specialized by
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]333a concrete target implementation (e.g., <tt>X86TargetMachine</tt>) which
334implements the various virtual methods. The only required target description
335class is the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the
336code generator components are to be used, the other interfaces should be
337implemented as well.</p>
338
339</div>
340
341
342<!-- ======================================================================= -->
343<div class="doc_subsection">
344 <a name="targetdata">The <tt>TargetData</tt> class</a>
345</div>
346
347<div class="doc_text">
348
349<p>The <tt>TargetData</tt> class is the only required target description class,
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]350and it is the only class that is not extensible (you cannot derived a new
351class from it). <tt>TargetData</tt> specifies information about how the target
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]352lays out memory for structures, the alignment requirements for various data
353types, the size of pointers in the target, and whether the target is
354little-endian or big-endian.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]355
356</div>
357
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]358<!-- ======================================================================= -->
359<div class="doc_subsection">
360 <a name="targetlowering">The <tt>TargetLowering</tt> class</a>
361</div>
362
363<div class="doc_text">
364
365<p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
366selectors primarily to describe how LLVM code should be lowered to SelectionDAG
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]367operations. Among other things, this class indicates:</p>
368
369<ul>
370 <li>an initial register class to use for various <tt>ValueType</tt>s</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]371 <li>which operations are natively supported by the target machine</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]372 <li>the return type of <tt>setcc</tt> operations</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]373 <li>the type to use for shift amounts</li>
374 <li>various high-level characteristics, like whether it is profitable to turn
375 division by a constant into a multiplication sequence</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]376</ol>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]377
378</div>
379
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]380<!-- ======================================================================= -->
381<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]382 <a name="mregisterinfo">The <tt>MRegisterInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]383</div>
384
385<div class="doc_text">
386
387<p>The <tt>MRegisterInfo</tt> class (which will eventually be renamed to
388<tt>TargetRegisterInfo</tt>) is used to describe the register file of the
389target and any interactions between the registers.</p>
390
391<p>Registers in the code generator are represented in the code generator by
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]392unsigned integers. Physical registers (those that actually exist in the target
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]393description) are unique small numbers, and virtual registers are generally
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]394large. Note that register #0 is reserved as a flag value.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]395
396<p>Each register in the processor description has an associated
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]397<tt>TargetRegisterDesc</tt> entry, which provides a textual name for the
398register (used for assembly output and debugging dumps) and a set of aliases
399(used to indicate whether one register overlaps with another).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]400</p>
401
402<p>In addition to the per-register description, the <tt>MRegisterInfo</tt> class
403exposes a set of processor specific register classes (instances of the
404<tt>TargetRegisterClass</tt> class). Each register class contains sets of
405registers that have the same properties (for example, they are all 32-bit
406integer registers). Each SSA virtual register created by the instruction
407selector has an associated register class. When the register allocator runs, it
408replaces virtual registers with a physical register in the set.</p>
409
410<p>
411The target-specific implementations of these classes is auto-generated from a <a
412href="TableGenFundamentals.html">TableGen</a> description of the register file.
413</p>
414
415</div>
416
417<!-- ======================================================================= -->
418<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]419 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]420</div>
421
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]422<div class="doc_text">
423 <p>The <tt>TargetInstrInfo</tt> class is used to describe the machine
424 instructions supported by the target. It is essentially an array of
425 <tt>TargetInstrDescriptor</tt> objects, each of which describes one
426 instruction the target supports. Descriptors define things like the mnemonic
Chris Lattnera3079782005-07-19 03:37:48 +0000[diff] [blame]427 for the opcode, the number of operands, the list of implicit register uses
428 and defs, whether the instruction has certain target-independent properties
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]429 (accesses memory, is commutable, etc), and holds any target-specific
430 flags.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]431</div>
432
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]433<!-- ======================================================================= -->
434<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]435 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]436</div>
437
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]438<div class="doc_text">
439 <p>The <tt>TargetFrameInfo</tt> class is used to provide information about the
440 stack frame layout of the target. It holds the direction of stack growth,
441 the known stack alignment on entry to each function, and the offset to the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]442 local area. The offset to the local area is the offset from the stack
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]443 pointer on function entry to the first location where function data (local
444 variables, spill locations) can be stored.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]445</div>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]446
447<!-- ======================================================================= -->
448<div class="doc_subsection">
449 <a name="targetsubtarget">The <tt>TargetSubtarget</tt> class</a>
450</div>
451
452<div class="doc_text">
Jim Laskey82d61a12005-10-17 12:19:10 +0000[diff] [blame]453 <p>The <tt>TargetSubtarget</tt> class is used to provide information about the
454 specific chip set being targeted. A sub-target informs code generation of
455 which instructions are supported, instruction latencies and instruction
456 execution itinerary; i.e., which processing units are used, in what order, and
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]457 for how long.</p>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]458</div>
459
460
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]461<!-- ======================================================================= -->
462<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]463 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]464</div>
465
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]466<div class="doc_text">
467 <p>The <tt>TargetJITInfo</tt> class exposes an abstract interface used by the
468 Just-In-Time code generator to perform target-specific activities, such as
469 emitting stubs. If a <tt>TargetMachine</tt> supports JIT code generation, it
470 should provide one of these objects through the <tt>getJITInfo</tt>
471 method.</p>
472</div>
473
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]474<!-- *********************************************************************** -->
475<div class="doc_section">
476 <a name="codegendesc">Machine code description classes</a>
477</div>
478<!-- *********************************************************************** -->
479
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]480<div class="doc_text">
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]481
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]482<p>At the high-level, LLVM code is translated to a machine specific
483representation formed out of
484<a href="#machinefunction"><tt>MachineFunction</tt></a>,
485<a href="#machinebasicblock"><tt>MachineBasicBlock</tt></a>, and <a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]486href="#machineinstr"><tt>MachineInstr</tt></a> instances
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]487(defined in <tt>include/llvm/CodeGen</tt>). This representation is completely
488target agnostic, representing instructions in their most abstract form: an
489opcode and a series of operands. This representation is designed to support
490both an SSA representation for machine code, as well as a register allocated,
491non-SSA form.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]492
493</div>
494
495<!-- ======================================================================= -->
496<div class="doc_subsection">
497 <a name="machineinstr">The <tt>MachineInstr</tt> class</a>
498</div>
499
500<div class="doc_text">
501
502<p>Target machine instructions are represented as instances of the
503<tt>MachineInstr</tt> class. This class is an extremely abstract way of
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]504representing machine instructions. In particular, it only keeps track of
505an opcode number and a set of operands.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]506
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]507<p>The opcode number is a simple unsigned integer that only has meaning to a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]508specific backend. All of the instructions for a target should be defined in
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]509the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]510are auto-generated from this description. The <tt>MachineInstr</tt> class does
511not have any information about how to interpret the instruction (i.e., what the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]512semantics of the instruction are); for that you must refer to the
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]513<tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
514
515<p>The operands of a machine instruction can be of several different types:
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]516a register reference, a constant integer, a basic block reference, etc. In
517addition, a machine operand should be marked as a def or a use of the value
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]518(though only registers are allowed to be defs).</p>
519
520<p>By convention, the LLVM code generator orders instruction operands so that
521all register definitions come before the register uses, even on architectures
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]522that are normally printed in other orders. For example, the SPARC add
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]523instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
524and stores the result into the "%i3" register. In the LLVM code generator,
525the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the destination
526first.</p>
527
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]528<p>Keeping destination (definition) operands at the beginning of the operand
529list has several advantages. In particular, the debugging printer will print
530the instruction like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]531
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]532<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]533<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]534%r3 = add %i1, %i2
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]535</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]536</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]537
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]538<p>Also if the first operand is a def, it is easier to <a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]539href="#buildmi">create instructions</a> whose only def is the first
540operand.</p>
541
542</div>
543
544<!-- _______________________________________________________________________ -->
545<div class="doc_subsubsection">
546 <a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
547</div>
548
549<div class="doc_text">
550
551<p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
552located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
553<tt>BuildMI</tt> functions make it easy to build arbitrary machine
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]554instructions. Usage of the <tt>BuildMI</tt> functions look like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]555
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]556<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]557<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]558// Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
559// instruction. The '1' specifies how many operands will be added.
560MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]561
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]562// Create the same instr, but insert it at the end of a basic block.
563MachineBasicBlock &amp;MBB = ...
564BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]565
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]566// Create the same instr, but insert it before a specified iterator point.
567MachineBasicBlock::iterator MBBI = ...
568BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]569
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]570// Create a 'cmp Reg, 0' instruction, no destination reg.
571MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
572// Create an 'sahf' instruction which takes no operands and stores nothing.
573MI = BuildMI(X86::SAHF, 0);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]574
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]575// Create a self looping branch instruction.
576BuildMI(MBB, X86::JNE, 1).addMBB(&amp;MBB);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]577</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]578</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]579
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]580<p>The key thing to remember with the <tt>BuildMI</tt> functions is that you
581have to specify the number of operands that the machine instruction will take.
582This allows for efficient memory allocation. You also need to specify if
583operands default to be uses of values, not definitions. If you need to add a
584definition operand (other than the optional destination register), you must
585explicitly mark it as such:</p>
586
587<div class="doc_code">
588<pre>
589MI.addReg(Reg, MachineOperand::Def);
590</pre>
591</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]592
593</div>
594
595<!-- _______________________________________________________________________ -->
596<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]597 <a name="fixedregs">Fixed (preassigned) registers</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]598</div>
599
600<div class="doc_text">
601
602<p>One important issue that the code generator needs to be aware of is the
603presence of fixed registers. In particular, there are often places in the
604instruction stream where the register allocator <em>must</em> arrange for a
605particular value to be in a particular register. This can occur due to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]606limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]607with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like calling
608conventions. In any case, the instruction selector should emit code that
609copies a virtual register into or out of a physical register when needed.</p>
610
611<p>For example, consider this simple LLVM example:</p>
612
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]613<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]614<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]615int %test(int %X, int %Y) {
616 %Z = div int %X, %Y
617 ret int %Z
618}
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]619</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]620</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]621
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]622<p>The X86 instruction selector produces this machine code for the <tt>div</tt>
623and <tt>ret</tt> (use
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]624"<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to get this):</p>
625
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]626<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]627<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]628;; Start of div
629%EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
630%reg1027 = sar %reg1024, 31
631%EDX = mov %reg1027 ;; Sign extend X into EDX
632idiv %reg1025 ;; Divide by Y (in reg1025)
633%reg1026 = mov %EAX ;; Read the result (Z) out of EAX
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]634
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]635;; Start of ret
636%EAX = mov %reg1026 ;; 32-bit return value goes in EAX
637ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]638</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]639</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]640
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]641<p>By the end of code generation, the register allocator has coalesced
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]642the registers and deleted the resultant identity moves producing the
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]643following code:</p>
644
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]645<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]646<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]647;; X is in EAX, Y is in ECX
648mov %EAX, %EDX
649sar %EDX, 31
650idiv %ECX
651ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]652</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]653</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]654
655<p>This approach is extremely general (if it can handle the X86 architecture,
656it can handle anything!) and allows all of the target specific
657knowledge about the instruction stream to be isolated in the instruction
658selector. Note that physical registers should have a short lifetime for good
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]659code generation, and all physical registers are assumed dead on entry to and
660exit from basic blocks (before register allocation). Thus, if you need a value
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]661to be live across basic block boundaries, it <em>must</em> live in a virtual
662register.</p>
663
664</div>
665
666<!-- _______________________________________________________________________ -->
667<div class="doc_subsubsection">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]668 <a name="ssa">Machine code in SSA form</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]669</div>
670
671<div class="doc_text">
672
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]673<p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]674are maintained in SSA-form until register allocation happens. For the most
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]675part, this is trivially simple since LLVM is already in SSA form; LLVM PHI nodes
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]676become machine code PHI nodes, and virtual registers are only allowed to have a
677single definition.</p>
678
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]679<p>After register allocation, machine code is no longer in SSA-form because there
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]680are no virtual registers left in the code.</p>
681
682</div>
683
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]684<!-- ======================================================================= -->
685<div class="doc_subsection">
686 <a name="machinebasicblock">The <tt>MachineBasicBlock</tt> class</a>
687</div>
688
689<div class="doc_text">
690
691<p>The <tt>MachineBasicBlock</tt> class contains a list of machine instructions
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]692(<tt><a href="#machineinstr">MachineInstr</a></tt> instances). It roughly
693corresponds to the LLVM code input to the instruction selector, but there can be
694a one-to-many mapping (i.e. one LLVM basic block can map to multiple machine
695basic blocks). The <tt>MachineBasicBlock</tt> class has a
696"<tt>getBasicBlock</tt>" method, which returns the LLVM basic block that it
697comes from.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]698
699</div>
700
701<!-- ======================================================================= -->
702<div class="doc_subsection">
703 <a name="machinefunction">The <tt>MachineFunction</tt> class</a>
704</div>
705
706<div class="doc_text">
707
708<p>The <tt>MachineFunction</tt> class contains a list of machine basic blocks
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]709(<tt><a href="#machinebasicblock">MachineBasicBlock</a></tt> instances). It
710corresponds one-to-one with the LLVM function input to the instruction selector.
711In addition to a list of basic blocks, the <tt>MachineFunction</tt> contains a
712a <tt>MachineConstantPool</tt>, a <tt>MachineFrameInfo</tt>, a
713<tt>MachineFunctionInfo</tt>, a <tt>SSARegMap</tt>, and a set of live in and
714live out registers for the function. See
715<tt>include/llvm/CodeGen/MachineFunction.h</tt> for more information.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]716
717</div>
718
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]719<!-- *********************************************************************** -->
720<div class="doc_section">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]721 <a name="codegenalgs">Target-independent code generation algorithms</a>
722</div>
723<!-- *********************************************************************** -->
724
725<div class="doc_text">
726
727<p>This section documents the phases described in the <a
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]728href="#high-level-design">high-level design of the code generator</a>. It
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]729explains how they work and some of the rationale behind their design.</p>
730
731</div>
732
733<!-- ======================================================================= -->
734<div class="doc_subsection">
735 <a name="instselect">Instruction Selection</a>
736</div>
737
738<div class="doc_text">
739<p>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]740Instruction Selection is the process of translating LLVM code presented to the
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]741code generator into target-specific machine instructions. There are several
742well-known ways to do this in the literature. In LLVM there are two main forms:
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]743the SelectionDAG based instruction selector framework and an old-style 'simple'
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]744instruction selector, which effectively peephole selects each LLVM instruction
745into a series of machine instructions. We recommend that all targets use the
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]746SelectionDAG infrastructure.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]747</p>
748
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]749<p>Portions of the DAG instruction selector are generated from the target
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]750description (<tt>*.td</tt>) files. Our goal is for the entire instruction
751selector to be generated from these <tt>.td</tt> files.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]752</div>
753
754<!-- _______________________________________________________________________ -->
755<div class="doc_subsubsection">
756 <a name="selectiondag_intro">Introduction to SelectionDAGs</a>
757</div>
758
759<div class="doc_text">
760
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]761<p>The SelectionDAG provides an abstraction for code representation in a way
762that is amenable to instruction selection using automatic techniques
763(e.g. dynamic-programming based optimal pattern matching selectors). It is also
764well-suited to other phases of code generation; in particular,
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]765instruction scheduling (SelectionDAG's are very close to scheduling DAGs
766post-selection). Additionally, the SelectionDAG provides a host representation
767where a large variety of very-low-level (but target-independent)
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]768<a href="#selectiondag_optimize">optimizations</a> may be
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]769performed; ones which require extensive information about the instructions
770efficiently supported by the target.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]771
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]772<p>The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]773<tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]774operation code (Opcode) that indicates what operation the node performs and
775the operands to the operation.
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]776The various operation node types are described at the top of the
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]777<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt> file.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]778
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]779<p>Although most operations define a single value, each node in the graph may
780define multiple values. For example, a combined div/rem operation will define
781both the dividend and the remainder. Many other situations require multiple
782values as well. Each node also has some number of operands, which are edges
783to the node defining the used value. Because nodes may define multiple values,
784edges are represented by instances of the <tt>SDOperand</tt> class, which is
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]785a <tt>&lt;SDNode, unsigned&gt;</tt> pair, indicating the node and result
786value being used, respectively. Each value produced by an <tt>SDNode</tt> has
787an associated <tt>MVT::ValueType</tt> indicating what type the value is.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]788
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]789<p>SelectionDAGs contain two different kinds of values: those that represent
790data flow and those that represent control flow dependencies. Data values are
791simple edges with an integer or floating point value type. Control edges are
792represented as "chain" edges which are of type <tt>MVT::Other</tt>. These edges
793provide an ordering between nodes that have side effects (such as
794loads, stores, calls, returns, etc). All nodes that have side effects should
795take a token chain as input and produce a new one as output. By convention,
796token chain inputs are always operand #0, and chain results are always the last
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]797value produced by an operation.</p>
798
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]799<p>A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
800always a marker node with an Opcode of <tt>ISD::EntryToken</tt>. The Root node
801is the final side-effecting node in the token chain. For example, in a single
802basic block function it would be the return node.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]803
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]804<p>One important concept for SelectionDAGs is the notion of a "legal" vs.
805"illegal" DAG. A legal DAG for a target is one that only uses supported
806operations and supported types. On a 32-bit PowerPC, for example, a DAG with
807a value of type i1, i8, i16, or i64 would be illegal, as would a DAG that uses a
808SREM or UREM operation. The
809<a href="#selectiondag_legalize">legalize</a> phase is responsible for turning
810an illegal DAG into a legal DAG.</p>
811
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]812</div>
813
814<!-- _______________________________________________________________________ -->
815<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]816 <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]817</div>
818
819<div class="doc_text">
820
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]821<p>SelectionDAG-based instruction selection consists of the following steps:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]822
823<ol>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]824<li><a href="#selectiondag_build">Build initial DAG</a> - This stage
825 performs a simple translation from the input LLVM code to an illegal
826 SelectionDAG.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]827<li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> - This stage
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]828 performs simple optimizations on the SelectionDAG to simplify it, and
829 recognize meta instructions (like rotates and <tt>div</tt>/<tt>rem</tt>
830 pairs) for targets that support these meta operations. This makes the
831 resultant code more efficient and the <a href="#selectiondag_select">select
832 instructions from DAG</a> phase (below) simpler.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]833<li><a href="#selectiondag_legalize">Legalize SelectionDAG</a> - This stage
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]834 converts the illegal SelectionDAG to a legal SelectionDAG by eliminating
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]835 unsupported operations and data types.</li>
836<li><a href="#selectiondag_optimize">Optimize SelectionDAG (#2)</a> - This
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]837 second run of the SelectionDAG optimizes the newly legalized DAG to
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]838 eliminate inefficiencies introduced by legalization.</li>
839<li><a href="#selectiondag_select">Select instructions from DAG</a> - Finally,
840 the target instruction selector matches the DAG operations to target
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]841 instructions. This process translates the target-independent input DAG into
842 another DAG of target instructions.</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]843<li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]844 - The last phase assigns a linear order to the instructions in the
845 target-instruction DAG and emits them into the MachineFunction being
846 compiled. This step uses traditional prepass scheduling techniques.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]847</ol>
848
849<p>After all of these steps are complete, the SelectionDAG is destroyed and the
850rest of the code generation passes are run.</p>
851
Chris Lattnerdf921f02005-10-17 01:40:33 +0000[diff] [blame]852<p>One great way to visualize what is going on here is to take advantage of a
853few LLC command line options. In particular, the <tt>-view-isel-dags</tt>
854option pops up a window with the SelectionDAG input to the Select phase for all
855of the code compiled (if you only get errors printed to the console while using
856this, you probably <a href="ProgrammersManual.html#ViewGraph">need to configure
857your system</a> to add support for it). The <tt>-view-sched-dags</tt> option
858views the SelectionDAG output from the Select phase and input to the Scheduler
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]859phase.</p>
860
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]861</div>
862
863<!-- _______________________________________________________________________ -->
864<div class="doc_subsubsection">
865 <a name="selectiondag_build">Initial SelectionDAG Construction</a>
866</div>
867
868<div class="doc_text">
869
Bill Wendling16448772006-08-28 03:04:05 +0000[diff] [blame]870<p>The initial SelectionDAG is na&iuml;vely peephole expanded from the LLVM
871input by the <tt>SelectionDAGLowering</tt> class in the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]872<tt>lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp</tt> file. The intent of this
873pass is to expose as much low-level, target-specific details to the SelectionDAG
874as possible. This pass is mostly hard-coded (e.g. an LLVM <tt>add</tt> turns
875into an <tt>SDNode add</tt> while a <tt>geteelementptr</tt> is expanded into the
876obvious arithmetic). This pass requires target-specific hooks to lower calls,
877returns, varargs, etc. For these features, the
878<tt><a href="#targetlowering">TargetLowering</a></tt> interface is used.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]879
880</div>
881
882<!-- _______________________________________________________________________ -->
883<div class="doc_subsubsection">
884 <a name="selectiondag_legalize">SelectionDAG Legalize Phase</a>
885</div>
886
887<div class="doc_text">
888
889<p>The Legalize phase is in charge of converting a DAG to only use the types and
890operations that are natively supported by the target. This involves two major
891tasks:</p>
892
893<ol>
894<li><p>Convert values of unsupported types to values of supported types.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]895 <p>There are two main ways of doing this: converting small types to
896 larger types ("promoting"), and breaking up large integer types
897 into smaller ones ("expanding"). For example, a target might require
898 that all f32 values are promoted to f64 and that all i1/i8/i16 values
899 are promoted to i32. The same target might require that all i64 values
900 be expanded into i32 values. These changes can insert sign and zero
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]901 extensions as needed to make sure that the final code has the same
902 behavior as the input.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]903 <p>A target implementation tells the legalizer which types are supported
904 (and which register class to use for them) by calling the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]905 <tt>addRegisterClass</tt> method in its TargetLowering constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]906</li>
907
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]908<li><p>Eliminate operations that are not supported by the target.</p>
909 <p>Targets often have weird constraints, such as not supporting every
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]910 operation on every supported datatype (e.g. X86 does not support byte
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]911 conditional moves and PowerPC does not support sign-extending loads from
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]912 a 16-bit memory location). Legalize takes care of this by open-coding
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]913 another sequence of operations to emulate the operation ("expansion"), by
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]914 promoting one type to a larger type that supports the operation
915 ("promotion"), or by using a target-specific hook to implement the
916 legalization ("custom").</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]917 <p>A target implementation tells the legalizer which operations are not
918 supported (and which of the above three actions to take) by calling the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]919 <tt>setOperationAction</tt> method in its <tt>TargetLowering</tt>
920 constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]921</li>
922</ol>
923
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]924<p>Prior to the existance of the Legalize pass, we required that every target
925<a href="#selectiondag_optimize">selector</a> supported and handled every
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]926operator and type even if they are not natively supported. The introduction of
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]927the Legalize phase allows all of the cannonicalization patterns to be shared
928across targets, and makes it very easy to optimize the cannonicalized code
929because it is still in the form of a DAG.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]930
931</div>
932
933<!-- _______________________________________________________________________ -->
934<div class="doc_subsubsection">
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]935 <a name="selectiondag_optimize">SelectionDAG Optimization Phase: the DAG
936 Combiner</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]937</div>
938
939<div class="doc_text">
940
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]941<p>The SelectionDAG optimization phase is run twice for code generation: once
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]942immediately after the DAG is built and once after legalization. The first run
943of the pass allows the initial code to be cleaned up (e.g. performing
944optimizations that depend on knowing that the operators have restricted type
945inputs). The second run of the pass cleans up the messy code generated by the
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]946Legalize pass, which allows Legalize to be very simple (it can focus on making
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]947code legal instead of focusing on generating <em>good</em> and legal code).</p>
948
949<p>One important class of optimizations performed is optimizing inserted sign
950and zero extension instructions. We currently use ad-hoc techniques, but could
951move to more rigorous techniques in the future. Here are some good papers on
952the subject:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]953
954<p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]955 "<a href="http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html">Widening
956 integer arithmetic</a>"<br>
957 Kevin Redwine and Norman Ramsey<br>
958 International Conference on Compiler Construction (CC) 2004
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]959</p>
960
961
962<p>
963 "<a href="http://portal.acm.org/citation.cfm?doid=512529.512552">Effective
964 sign extension elimination</a>"<br>
965 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
966 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
967 and Implementation.
968</p>
969
970</div>
971
972<!-- _______________________________________________________________________ -->
973<div class="doc_subsubsection">
974 <a name="selectiondag_select">SelectionDAG Select Phase</a>
975</div>
976
977<div class="doc_text">
978
979<p>The Select phase is the bulk of the target-specific code for instruction
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]980selection. This phase takes a legal SelectionDAG as input, pattern matches the
981instructions supported by the target to this DAG, and produces a new DAG of
982target code. For example, consider the following LLVM fragment:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]983
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]984<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]985<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]986%t1 = add float %W, %X
987%t2 = mul float %t1, %Y
988%t3 = add float %t2, %Z
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]989</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]990</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]991
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]992<p>This LLVM code corresponds to a SelectionDAG that looks basically like
993this:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]994
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]995<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]996<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]997(fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]998</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]999</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1000
Chris Lattnera1ff9312005-10-17 15:19:24 +0000[diff] [blame]1001<p>If a target supports floating point multiply-and-add (FMA) operations, one
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1002of the adds can be merged with the multiply. On the PowerPC, for example, the
1003output of the instruction selector might look like this DAG:</p>
1004
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1005<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1006<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1007(FMADDS (FADDS W, X), Y, Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1008</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1009</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1010
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1011<p>The <tt>FMADDS</tt> instruction is a ternary instruction that multiplies its
1012first two operands and adds the third (as single-precision floating-point
1013numbers). The <tt>FADDS</tt> instruction is a simple binary single-precision
1014add instruction. To perform this pattern match, the PowerPC backend includes
1015the following instruction definitions:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1016
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1017<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1018<pre>
1019def FMADDS : AForm_1&lt;59, 29,
1020 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1021 "fmadds $FRT, $FRA, $FRC, $FRB",
1022 [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1023 F4RC:$FRB))</b>]&gt;;
1024def FADDS : AForm_2&lt;59, 21,
1025 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1026 "fadds $FRT, $FRA, $FRB",
1027 [<b>(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))</b>]&gt;;
1028</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1029</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1030
1031<p>The portion of the instruction definition in bold indicates the pattern used
1032to match the instruction. The DAG operators (like <tt>fmul</tt>/<tt>fadd</tt>)
1033are defined in the <tt>lib/Target/TargetSelectionDAG.td</tt> file.
1034"<tt>F4RC</tt>" is the register class of the input and result values.<p>
1035
1036<p>The TableGen DAG instruction selector generator reads the instruction
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1037patterns in the <tt>.td</tt> file and automatically builds parts of the pattern
1038matching code for your target. It has the following strengths:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1039
1040<ul>
1041<li>At compiler-compiler time, it analyzes your instruction patterns and tells
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1042 you if your patterns make sense or not.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1043<li>It can handle arbitrary constraints on operands for the pattern match. In
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1044 particular, it is straight-forward to say things like "match any immediate
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1045 that is a 13-bit sign-extended value". For examples, see the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1046 <tt>immSExt16</tt> and related <tt>tblgen</tt> classes in the PowerPC
1047 backend.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1048<li>It knows several important identities for the patterns defined. For
1049 example, it knows that addition is commutative, so it allows the
1050 <tt>FMADDS</tt> pattern above to match "<tt>(fadd X, (fmul Y, Z))</tt>" as
1051 well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
1052 to specially handle this case.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1053<li>It has a full-featured type-inferencing system. In particular, you should
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1054 rarely have to explicitly tell the system what type parts of your patterns
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1055 are. In the <tt>FMADDS</tt> case above, we didn't have to tell
1056 <tt>tblgen</tt> that all of the nodes in the pattern are of type 'f32'. It
1057 was able to infer and propagate this knowledge from the fact that
1058 <tt>F4RC</tt> has type 'f32'.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1059<li>Targets can define their own (and rely on built-in) "pattern fragments".
1060 Pattern fragments are chunks of reusable patterns that get inlined into your
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1061 patterns during compiler-compiler time. For example, the integer
1062 "<tt>(not x)</tt>" operation is actually defined as a pattern fragment that
1063 expands as "<tt>(xor x, -1)</tt>", since the SelectionDAG does not have a
1064 native '<tt>not</tt>' operation. Targets can define their own short-hand
1065 fragments as they see fit. See the definition of '<tt>not</tt>' and
1066 '<tt>ineg</tt>' for examples.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1067<li>In addition to instructions, targets can specify arbitrary patterns that
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1068 map to one or more instructions using the 'Pat' class. For example,
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1069 the PowerPC has no way to load an arbitrary integer immediate into a
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1070 register in one instruction. To tell tblgen how to do this, it defines:
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1071 <br>
1072 <br>
1073 <div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1074 <pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1075// Arbitrary immediate support. Implement in terms of LIS/ORI.
1076def : Pat&lt;(i32 imm:$imm),
1077 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))&gt;;
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1078 </pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1079 </div>
1080 <br>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1081 If none of the single-instruction patterns for loading an immediate into a
1082 register match, this will be used. This rule says "match an arbitrary i32
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1083 immediate, turning it into an <tt>ORI</tt> ('or a 16-bit immediate') and an
1084 <tt>LIS</tt> ('load 16-bit immediate, where the immediate is shifted to the
1085 left 16 bits') instruction". To make this work, the
1086 <tt>LO16</tt>/<tt>HI16</tt> node transformations are used to manipulate the
1087 input immediate (in this case, take the high or low 16-bits of the
1088 immediate).</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1089<li>While the system does automate a lot, it still allows you to write custom
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1090 C++ code to match special cases if there is something that is hard to
1091 express.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1092</ul>
1093
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1094<p>While it has many strengths, the system currently has some limitations,
1095primarily because it is a work in progress and is not yet finished:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1096
1097<ul>
1098<li>Overall, there is no way to define or match SelectionDAG nodes that define
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1099 multiple values (e.g. <tt>ADD_PARTS</tt>, <tt>LOAD</tt>, <tt>CALL</tt>,
1100 etc). This is the biggest reason that you currently still <em>have to</em>
1101 write custom C++ code for your instruction selector.</li>
1102<li>There is no great way to support matching complex addressing modes yet. In
1103 the future, we will extend pattern fragments to allow them to define
1104 multiple values (e.g. the four operands of the <a href="#x86_memory">X86
1105 addressing mode</a>). In addition, we'll extend fragments so that a
1106 fragment can match multiple different patterns.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1107<li>We don't automatically infer flags like isStore/isLoad yet.</li>
1108<li>We don't automatically generate the set of supported registers and
1109 operations for the <a href="#"selectiondag_legalize>Legalizer</a> yet.</li>
1110<li>We don't have a way of tying in custom legalized nodes yet.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1111</ul>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1112
1113<p>Despite these limitations, the instruction selector generator is still quite
1114useful for most of the binary and logical operations in typical instruction
1115sets. If you run into any problems or can't figure out how to do something,
1116please let Chris know!</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1117
1118</div>
1119
1120<!-- _______________________________________________________________________ -->
1121<div class="doc_subsubsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1122 <a name="selectiondag_sched">SelectionDAG Scheduling and Formation Phase</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1123</div>
1124
1125<div class="doc_text">
1126
1127<p>The scheduling phase takes the DAG of target instructions from the selection
1128phase and assigns an order. The scheduler can pick an order depending on
1129various constraints of the machines (i.e. order for minimal register pressure or
1130try to cover instruction latencies). Once an order is established, the DAG is
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1131converted to a list of <tt><a href="#machineinstr">MachineInstr</a></tt>s and
1132the SelectionDAG is destroyed.</p>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1133
Jeff Cohen0b81cda2005-10-24 16:54:55 +0000[diff] [blame]1134<p>Note that this phase is logically separate from the instruction selection
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]1135phase, but is tied to it closely in the code because it operates on
1136SelectionDAGs.</p>
1137
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1138</div>
1139
1140<!-- _______________________________________________________________________ -->
1141<div class="doc_subsubsection">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1142 <a name="selectiondag_future">Future directions for the SelectionDAG</a>
1143</div>
1144
1145<div class="doc_text">
1146
1147<ol>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1148<li>Optional function-at-a-time selection.</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1149<li>Auto-generate entire selector from <tt>.td</tt> file.</li>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1150</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1151</ol>
1152
1153</div>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1154
1155<!-- ======================================================================= -->
1156<div class="doc_subsection">
1157 <a name="ssamco">SSA-based Machine Code Optimizations</a>
1158</div>
1159<div class="doc_text"><p>To Be Written</p></div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1160
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1161<!-- ======================================================================= -->
1162<div class="doc_subsection">
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame^]1163 <a name="liveinterval_analysis">Live Interval Analysis</a>
1164</div>
1165
1166<div class="doc_text">
1167
1168<p>Live Interval Analysis identifies the ranges where a variable is <i>live</i>.
1169It's used by the <a href="#regalloc">register allocator pass</a> to determine
1170if two or more virtual registers which require the same register are live at
1171the same point in the program (conflict). When this situation occurs, one
1172virtual register must be <i>spilt</i>.</p>
1173
1174</div>
1175
1176<!-- _______________________________________________________________________ -->
1177<div class="doc_subsubsection">
1178 <a name="livevariable_analysis">Live Variable Analysis</a>
1179</div>
1180
1181<div class="doc_text">
1182
1183<p>The first step to determining the live intervals of variables is to
1184calculate the set of registers that are immediately dead after the
1185instruction (i.e., the instruction calculates the value, but it is never
1186used) and the set of registers that are used by the instruction, but are
1187never used after the instruction (i.e., they are killed). Live variable
1188information is computed for each <i>virtual</i> and <i>register
1189allocatable</i> physical register in the function. LLVM assumes that
1190physical registers are only live within a single basic block. This allows
1191it to do a single, local analysis to resolve physical register lifetimes in
1192each basic block. If a physical register is not register allocatable (e.g.,
1193a stack pointer or condition codes), it is not tracked.</p>
1194
1195<p>Physical registers may be live in to or out of a function. Live in values
1196are typically arguments in register. Live out values are typically return
1197values in registers. Live in values are marked as such, and are given a dummy
1198"defining" instruction during live interval analysis. If the last basic block
1199of a function is a <tt>return</tt>, then it's marked as using all live-out
1200values in the function.</p>
1201
1202<p><tt>PHI</tt> nodes need to be handled specially, because the calculation
1203of the live variable information from a depth first traversal of the CFG of
1204the function won't guarantee that a virtual register is defined before it's
1205used. When a <tt>PHI</tt> node is encounted, only the definition is
1206handled, because the uses will be handled in other basic blocks.</p>
1207
1208<p>For each <tt>PHI</tt> node of the current basic block, we simulate an
1209assignment at the end of the current basic block and traverse the successor
1210basic blocks. If a successor basic block has a <tt>PHI</tt> node and one of
1211the <tt>PHI</tt> node's operands is coming from the current basic block,
1212then the variable is marked as <i>alive</i> within the current basic block
1213and all of its predecessor basic blocks, until the basic block with the
1214defining instruction is encountered.</p>
1215
1216</div>
1217
1218<!-- FIXME:
1219
1220A. General Overview
1221B. Describe Default RA (Linear Scan)
1222 1. LiveVariable Analysis
1223 a. All physical register references presumed dead across BBs
1224 b. Mark live-in regs as live-in
1225 c. Calculate LV info in DFS order
1226 1) We'll see def of vreg before its uses
1227 2) PHI nodes are treated specially
1228 a) Only handle its def
1229 b) Uses handled in other BBs
1230 3) Handle all uses and defs
1231 a) Handle implicit preg uses
1232 (1) "TargetInstrDescriptor" from "TargetInstructionInfo"
1233 b) Handle explicit preg and vreg uses
1234 c) Handle implicit preg defs
1235 (1) "TargetInstrDescriptor" from "TargetInstructionInfo"
1236 d) Handle explicit preg and vreg defs
1237 4) Use of vreg marks it killed (last use in BB)
1238 a) Updates (expands) live range
1239 b) Marks vreg as alive in dominating blocks
1240 5) Use of preg updates info and used tables
1241 6) Def of vreg defaults to "dead"
1242 a) Expanded later (see B.1.c.4)
1243 7) Def of preg updates info, used, RegsKilled, and RegsDead tables.
1244 8) Handle virt assigns from PHI nodes at the bottom of the BB
1245 a) If successor block has PHI nodes
1246 (1) Simulate an assignment at the end of current BB
1247 (i.e., mark it as alive in current BB)
1248 9) If last block is a "return"
1249 a) Mark it as using all live-out values
1250 10) Kill all pregs available at the end of the BB
1251 d. Update "RegistersDead" and "RegistersKilled"
1252 1) RegistersDead - This map keeps track of all of the registers that
1253 are dead immediately after an instruction executes, which are not
1254 dead after the operands are evaluated. In practice, this only
1255 contains registers which are defined by an instruction, but never
1256 used.
1257 2) RegistersKilled - This map keeps track of all of the registers that
1258 are dead immediately after an instruction reads its operands. If an
1259 instruction does not have an entry in this map, it kills no
1260 registers.
1261 2. LiveInterval Analysis
1262 a. Use LV pass to conservatively compute live intervals for vregs and pregs
1263 b. For some ordering of the machine instrs [1,N], a live interval is an
1264 interval [i,j) where 1 <= i <= j < N for which a variable is live
1265 c. Function has live ins
1266 1) Insert dummy instr at beginning
1267 2) Pretend dummy instr "defines" values
1268 d. Number each machine instruction -- depth-first order
1269 1) An interval [i, j) == Live interval for reg v if there is no
1270 instr with num j' > j s.t. v is live at j' and there is no instr
1271 with number i' < i s.t. v is live at i'
1272 2) Intervals can have holes: [1,20), [50,65), [1000,1001)
1273 e. Handle line-in values
1274 f. Compute live intervals
1275 1) Each live range is assigned a value num within the live interval
1276 2) vreg
1277 a) May be defined multiple times (due to phi and 2-addr elimination)
1278 b) Live only within defining BB
1279 (1) Single kill after def in BB
1280 c) Lives to end of defining BB, potentially across some BBs
1281 (1) Add range that goes from def to end of defining BB
1282 (2) Iterate over all BBs that the var is completely live in
1283 (a) add [instrIndex(begin), InstrIndex(end)+4) to LI
1284 (3) Vreg is live from start of any killing block to 'use'
1285 d) If seeing vreg again (because of phi or 2-addr elimination)
1286 (1) If 2-addr elim, then vreg is 1st op and a def-and-use
1287 (a) Didn't realize there are 2 values in LI
1288 (b) Need to take LR that defs vreg and split it into 2 vals
1289 (1) Delete initial value (from first def to redef)
1290 (2) Get new value num (#1)
1291 (3) Value#0 is now defined by the 2-addr instr
1292 (4) Add new LR which replaces the range for input copy
1293 (2) Else phi-elimination
1294 (a) If first redef of vreg, change LR in PHI block to be
1295 a different Value Number
1296 (b) Each variable def is only live until the end of the BB
1297 3) preg
1298 a) Cannot be live across BB
1299 b) Lifetime must end somewhere in its defining BB
1300 c) Dead at def instr, if not used after def
1301 (1) Interval: [defSlot(def), defSlot(def) + 1)
1302 d) Killed by subsequent instr, if not dead on def
1303 (1) Interval: [defSlot(def), useSlot(kill) + 1)
1304 e) If neither, then it's live-in to func and never used
1305 (1) Interval: [start, start + 1)
1306 e. Join intervals
1307 f. Compute spill weights
1308 g. Coalesce vregs
1309 h. Remove identity moves
1310 3. Linear Scan RA
1311 a.
1312
1313
1314 /// VarInfo - This represents the regions where a virtual register is live in
1315 /// the program. We represent this with three different pieces of
1316 /// information: the instruction that uniquely defines the value, the set of
1317 /// blocks the instruction is live into and live out of, and the set of
1318 /// non-phi instructions that are the last users of the value.
1319 ///
1320 /// In the common case where a value is defined and killed in the same block,
1321 /// DefInst is the defining inst, there is one killing instruction, and
1322 /// AliveBlocks is empty.
1323 ///
1324 /// Otherwise, the value is live out of the block. If the value is live
1325 /// across any blocks, these blocks are listed in AliveBlocks. Blocks where
1326 /// the liveness range ends are not included in AliveBlocks, instead being
1327 /// captured by the Kills set. In these blocks, the value is live into the
1328 /// block (unless the value is defined and killed in the same block) and lives
1329 /// until the specified instruction. Note that there cannot ever be a value
1330 /// whose Kills set contains two instructions from the same basic block.
1331 ///
1332 /// PHI nodes complicate things a bit. If a PHI node is the last user of a
1333 /// value in one of its predecessor blocks, it is not listed in the kills set,
1334 /// but does include the predecessor block in the AliveBlocks set (unless that
1335 /// block also defines the value). This leads to the (perfectly sensical)
1336 /// situation where a value is defined in a block, and the last use is a phi
1337 /// node in the successor. In this case, DefInst will be the defining
1338 /// instruction, AliveBlocks is empty (the value is not live across any
1339 /// blocks) and Kills is empty (phi nodes are not included). This is sensical
1340 /// because the value must be live to the end of the block, but is not live in
1341 /// any successor blocks.
1342
1343 -->
1344
1345<!-- ======================================================================= -->
1346<div class="doc_subsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1347 <a name="regalloc">Register Allocation</a>
1348</div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1349
1350<div class="doc_text">
1351
1352<p>The <i>Register Allocation problem</i> consists in mapping a
1353program <i>P<sub>v</sub></i>, that can use an unbounded number of
1354virtual registers, to a program <i>P<sub>p</sub></i> that contains a
1355finite (possibly small) number of physical registers. Each target
1356architecture has a different number of physical registers. If the
1357number of physical registers is not enough to accommodate all the
1358virtual registers, some of them will have to be mapped into
1359memory. These virtuals are called <i>spilled virtuals</i>.</p>
1360
1361</div>
1362
1363<!-- _______________________________________________________________________ -->
1364
1365<div class="doc_subsubsection">
1366 <a name="regAlloc_represent">How registers are represented in LLVM</a>
1367</div>
1368
1369<div class="doc_text">
1370
1371<p>In LLVM, physical registers are denoted by integer numbers that
1372normally range from 1 to 1023. To see how this numbering is defined
1373for a particular architecture, you can read the
1374<tt>GenRegisterNames.inc</tt> file for that architecture. For
1375instance, by inspecting
1376<tt>lib/Target/X86/X86GenRegisterNames.inc</tt> we see that the 32-bit
1377register <tt>EAX</tt> is denoted by 15, and the MMX register
1378<tt>MM0</tt> is mapped to 48.</p>
1379
1380<p>Some architectures contain registers that share the same physical
1381location. A notable example is the X86 platform. For instance, in the
1382X86 architecture, the registers <tt>EAX</tt>, <tt>AX</tt> and
1383<tt>AL</tt> share the first eight bits. These physical registers are
1384marked as <i>aliased</i> in LLVM. Given a particular architecture, you
1385can check which registers are aliased by inspecting its
1386<tt>RegisterInfo.td</tt> file. Moreover, the method
1387<tt>MRegisterInfo::getAliasSet(p_reg)</tt> returns an array containing
1388all the physical registers aliased to the register <tt>p_reg</tt>.</p>
1389
1390<p>Physical registers, in LLVM, are grouped in <i>Register Classes</i>.
1391Elements in the same register class are functionally equivalent, and can
1392be interchangeably used. Each virtual register can only be mapped to
1393physical registers of a particular class. For instance, in the X86
1394architecture, some virtuals can only be allocated to 8 bit registers.
1395A register class is described by <tt>TargetRegisterClass</tt> objects.
1396To discover if a virtual register is compatible with a given physical,
1397this code can be used:
1398</p>
1399
1400<div class="doc_code">
1401<pre>
1402bool RegMapping_Fer::compatible_class(MachineFunction &mf,
1403 unsigned v_reg,
1404 unsigned p_reg) {
1405 assert(MRegisterInfo::isPhysicalRegister(p_reg) &&
1406 "Target register must be physical");
1407 const TargetRegisterClass *trc = mf.getSSARegMap()->getRegClass(v_reg);
1408 return trc->contains(p_reg);
1409}
1410</pre>
1411</div>
1412
1413<p>Sometimes, mostly for debugging purposes, it is useful to change
1414the number of physical registers available in the target
1415architecture. This must be done statically, inside the
1416<tt>TargetRegsterInfo.td</tt> file. Just <tt>grep</tt> for
1417<tt>RegisterClass</tt>, the last parameter of which is a list of
1418registers. Just commenting some out is one simple way to avoid them
1419being used. A more polite way is to explicitly exclude some registers
1420from the <i>allocation order</i>. See the definition of the
1421<tt>GR</tt> register class in
1422<tt>lib/Target/IA64/IA64RegisterInfo.td</tt> for an example of this
1423(e.g., <tt>numReservedRegs</tt> registers are hidden.)</p>
1424
1425<p>Virtual registers are also denoted by integer numbers. Contrary to
1426physical registers, different virtual registers never share the same
1427number. The smallest virtual register is normally assigned the number
14281024. This may change, so, in order to know which is the first virtual
1429register, you should access
1430<tt>MRegisterInfo::FirstVirtualRegister</tt>. Any register whose
1431number is greater than or equal to
1432<tt>MRegisterInfo::FirstVirtualRegister</tt> is considered a virtual
1433register. Whereas physical registers are statically defined in a
1434<tt>TargetRegisterInfo.td</tt> file and cannot be created by the
1435application developer, that is not the case with virtual registers.
1436In order to create new virtual registers, use the method
1437<tt>SSARegMap::createVirtualRegister()</tt>. This method will return a
1438virtual register with the highest code.
1439</p>
1440
1441<p>Before register allocation, the operands of an instruction are
1442mostly virtual registers, although physical registers may also be
1443used. In order to check if a given machine operand is a register, use
1444the boolean function <tt>MachineOperand::isRegister()</tt>. To obtain
1445the integer code of a register, use
1446<tt>MachineOperand::getReg()</tt>. An instruction may define or use a
1447register. For instance, <tt>ADD reg:1026 := reg:1025 reg:1024</tt>
1448defines the registers 1024, and uses registers 1025 and 1026. Given a
1449register operand, the method <tt>MachineOperand::isUse()</tt> informs
1450if that register is being used by the instruction. The method
1451<tt>MachineOperand::isDef()</tt> informs if that registers is being
1452defined.</p>
1453
1454<p>We will call physical registers present in the LLVM bytecode before
1455register allocation <i>pre-colored registers</i>. Pre-colored
1456registers are used in many different situations, for instance, to pass
1457parameters of functions calls, and to store results of particular
1458instructions. There are two types of pre-colored registers: the ones
1459<i>implicitly</i> defined, and those <i>explicitly</i>
1460defined. Explicitly defined registers are normal operands, and can be
1461accessed with <tt>MachineInstr::getOperand(int)::getReg()</tt>. In
1462order to check which registers are implicitly defined by an
1463instruction, use the
1464<tt>TargetInstrInfo::get(opcode)::ImplicitDefs</tt>, where
1465<tt>opcode</tt> is the opcode of the target instruction. One important
1466difference between explicit and implicit physical registers is that
1467the latter are defined statically for each instruction, whereas the
1468former may vary depending on the program being compiled. For example,
1469an instruction that represents a function call will always implicitly
1470define or use the same set of physical registers. To read the
1471registers implicitly used by an instruction, use
1472<tt>TargetInstrInfo::get(opcode)::ImplicitUses</tt>. Pre-colored
1473registers impose constraints on any register allocation algorithm. The
1474register allocator must make sure that none of them is been
1475overwritten by the values of virtual registers while still alive.</p>
1476
1477</div>
1478
1479<!-- _______________________________________________________________________ -->
1480
1481<div class="doc_subsubsection">
1482 <a name="regAlloc_howTo">Mapping virtual registers to physical registers</a>
1483</div>
1484
1485<div class="doc_text">
1486
1487<p>There are two ways to map virtual registers to physical registers (or to
1488memory slots). The first way, that we will call <i>direct mapping</i>,
1489is based on the use of methods of the classes <tt>MRegisterInfo</tt>,
1490and <tt>MachineOperand</tt>. The second way, that we will call
1491<i>indirect mapping</i>, relies on the <tt>VirtRegMap</tt> class in
1492order to insert loads and stores sending and getting values to and from
1493memory.</p>
1494
1495<p>The direct mapping provides more flexibility to the developer of
1496the register allocator; however, it is more error prone, and demands
1497more implementation work. Basically, the programmer will have to
1498specify where load and store instructions should be inserted in the
1499target function being compiled in order to get and store values in
1500memory. To assign a physical register to a virtual register present in
1501a given operand, use <tt>MachineOperand::setReg(p_reg)</tt>. To insert
1502a store instruction, use
1503<tt>MRegisterInfo::storeRegToStackSlot(...)</tt>, and to insert a load
1504instruction, use <tt>MRegisterInfo::loadRegFromStackSlot</tt>.</p>
1505
1506<p>The indirect mapping shields the application developer from the
1507complexities of inserting load and store instructions. In order to map
1508a virtual register to a physical one, use
1509<tt>VirtRegMap::assignVirt2Phys(vreg, preg)</tt>. In order to map a
1510certain virtual register to memory, use
1511<tt>VirtRegMap::assignVirt2StackSlot(vreg)</tt>. This method will
1512return the stack slot where <tt>vreg</tt>'s value will be located. If
1513it is necessary to map another virtual register to the same stack
1514slot, use <tt>VirtRegMap::assignVirt2StackSlot(vreg,
1515stack_location)</tt>. One important point to consider when using the
1516indirect mapping, is that even if a virtual register is mapped to
1517memory, it still needs to be mapped to a physical register. This
1518physical register is the location where the virtual register is
1519supposed to be found before being stored or after being reloaded.</p>
1520
1521<p>If the indirect strategy is used, after all the virtual registers
1522have been mapped to physical registers or stack slots, it is necessary
1523to use a spiller object to place load and store instructions in the
1524code. Every virtual that has been mapped to a stack slot will be
1525stored to memory after been defined and will be loaded before being
1526used. The implementation of the spiller tries to recycle load/store
1527instructions, avoiding unnecessary instructions. For an example of how
1528to invoke the spiller, see
1529<tt>RegAllocLinearScan::runOnMachineFunction</tt> in
1530<tt>lib/CodeGen/RegAllocLinearScan.cpp</tt>.</p>
1531
1532</div>
1533
1534<!-- _______________________________________________________________________ -->
1535<div class="doc_subsubsection">
1536 <a name="regAlloc_twoAddr">Handling two address instructions</a>
1537</div>
1538
1539<div class="doc_text">
1540
1541<p>With very rare exceptions (e.g., function calls), the LLVM machine
1542code instructions are three address instructions. That is, each
1543instruction is expected to define at most one register, and to use at
1544most two registers. However, some architectures use two address
1545instructions. In this case, the defined register is also one of the
1546used register. For instance, an instruction such as <tt>ADD %EAX,
1547%EBX</tt>, in X86 is actually equivalent to <tt>%EAX = %EAX +
1548%EBX</tt>.</p>
1549
1550<p>In order to produce correct code, LLVM must convert three address
1551instructions that represent two address instructions into true two
1552address instructions. LLVM provides the pass
1553<tt>TwoAddressInstructionPass</tt> for this specific purpose. It must
1554be run before register allocation takes place. After its execution,
1555the resulting code may no longer be in SSA form. This happens, for
1556instance, in situations where an instruction such as <tt>%a = ADD %b
1557%c</tt> is converted to two instructions such as:</p>
1558
1559<div class="doc_code">
1560<pre>
1561%a = MOVE %b
1562%a = ADD %a %b
1563</pre>
1564</div>
1565
1566<p>Notice that, internally, the second instruction is represented as
1567<tt>ADD %a[def/use] %b</tt>. I.e., the register operand <tt>%a</tt> is
1568both used and defined by the instruction.</p>
1569
1570</div>
1571
1572<!-- _______________________________________________________________________ -->
1573<div class="doc_subsubsection">
1574 <a name="regAlloc_ssaDecon">The SSA deconstruction phase</a>
1575</div>
1576
1577<div class="doc_text">
1578
1579<p>An important transformation that happens during register allocation is called
1580the <i>SSA Deconstruction Phase</i>. The SSA form simplifies many
1581analyses that are performed on the control flow graph of
1582programs. However, traditional instruction sets do not implement
1583PHI instructions. Thus, in order to generate executable code, compilers
1584must replace PHI instructions with other instructions that preserve their
1585semantics.</p>
1586
1587<p>There are many ways in which PHI instructions can safely be removed
1588from the target code. The most traditional PHI deconstruction
1589algorithm replaces PHI instructions with copy instructions. That is
1590the strategy adopted by LLVM. The SSA deconstruction algorithm is
1591implemented in n<tt>lib/CodeGen/>PHIElimination.cpp</tt>. In order to
1592invoke this pass, the identifier <tt>PHIEliminationID</tt> must be
1593marked as required in the code of the register allocator.</p>
1594
1595</div>
1596
1597<!-- _______________________________________________________________________ -->
1598<div class="doc_subsubsection">
1599 <a name="regAlloc_fold">Instruction folding</a>
1600</div>
1601
1602<div class="doc_text">
1603
1604<p><i>Instruction folding</i> is an optimization performed during
1605register allocation that removes unnecessary copy instructions. For
1606instance, a sequence of instructions such as:</p>
1607
1608<div class="doc_code">
1609<pre>
1610%EBX = LOAD %mem_address
1611%EAX = COPY %EBX
1612</pre>
1613</div>
1614
1615<p>can be safely substituted by the single instruction:
1616
1617<div class="doc_code">
1618<pre>
1619%EAX = LOAD %mem_address
1620</pre>
1621</div>
1622
1623<p>Instructions can be folded with the
1624<tt>MRegisterInfo::foldMemoryOperand(...)</tt> method. Care must be
1625taken when folding instructions; a folded instruction can be quite
1626different from the original instruction. See
1627<tt>LiveIntervals::addIntervalsForSpills</tt> in
1628<tt>lib/CodeGen/LiveIntervalAnalysis.cpp</tt> for an example of its use.</p>
1629
1630</div>
1631
1632<!-- _______________________________________________________________________ -->
1633
1634<div class="doc_subsubsection">
1635 <a name="regAlloc_builtIn">Built in register allocators</a>
1636</div>
1637
1638<div class="doc_text">
1639
1640<p>The LLVM infrastructure provides the application developer with
1641three different register allocators:</p>
1642
1643<ul>
1644 <li><i>Simple</i> - This is a very simple implementation that does
1645 not keep values in registers across instructions. This register
1646 allocator immediately spills every value right after it is
1647 computed, and reloads all used operands from memory to temporary
1648 registers before each instruction.</li>
1649 <li><i>Local</i> - This register allocator is an improvement on the
1650 <i>Simple</i> implementation. It allocates registers on a basic
1651 block level, attempting to keep values in registers and reusing
1652 registers as appropriate.</li>
1653 <li><i>Linear Scan</i> - <i>The default allocator</i>. This is the
1654 well-know linear scan register allocator. Whereas the
1655 <i>Simple</i> and <i>Local</i> algorithms use a direct mapping
1656 implementation technique, the <i>Linear Scan</i> implementation
1657 uses a spiller in order to place load and stores.</li>
1658</ul>
1659
1660<p>The type of register allocator used in <tt>llc</tt> can be chosen with the
1661command line option <tt>-regalloc=...</tt>:</p>
1662
1663<div class="doc_code">
1664<pre>
1665$ llc -f -regalloc=simple file.bc -o sp.s;
1666$ llc -f -regalloc=local file.bc -o lc.s;
1667$ llc -f -regalloc=linearscan file.bc -o ln.s;
1668</pre>
1669</div>
1670
1671</div>
1672
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1673<!-- ======================================================================= -->
1674<div class="doc_subsection">
1675 <a name="proepicode">Prolog/Epilog Code Insertion</a>
1676</div>
1677<div class="doc_text"><p>To Be Written</p></div>
1678<!-- ======================================================================= -->
1679<div class="doc_subsection">
1680 <a name="latemco">Late Machine Code Optimizations</a>
1681</div>
1682<div class="doc_text"><p>To Be Written</p></div>
1683<!-- ======================================================================= -->
1684<div class="doc_subsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1685 <a name="codeemit">Code Emission</a>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1686</div>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1687<div class="doc_text"><p>To Be Written</p></div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1688<!-- _______________________________________________________________________ -->
1689<div class="doc_subsubsection">
1690 <a name="codeemit_asm">Generating Assembly Code</a>
1691</div>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1692<div class="doc_text"><p>To Be Written</p></div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1693<!-- _______________________________________________________________________ -->
1694<div class="doc_subsubsection">
1695 <a name="codeemit_bin">Generating Binary Machine Code</a>
1696</div>
1697
1698<div class="doc_text">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1699 <p>For the JIT or <tt>.o</tt> file writer</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1700</div>
1701
1702
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1703<!-- *********************************************************************** -->
1704<div class="doc_section">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1705 <a name="targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1706</div>
1707<!-- *********************************************************************** -->
1708
1709<div class="doc_text">
1710
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1711<p>This section of the document explains features or design decisions that
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1712are specific to the code generator for a particular target.</p>
1713
1714</div>
1715
1716
1717<!-- ======================================================================= -->
1718<div class="doc_subsection">
1719 <a name="x86">The X86 backend</a>
1720</div>
1721
1722<div class="doc_text">
1723
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1724<p>The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1725code generator currently targets a generic P6-like processor. As such, it
1726produces a few P6-and-above instructions (like conditional moves), but it does
1727not make use of newer features like MMX or SSE. In the future, the X86 backend
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1728will have sub-target support added for specific processor families and
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1729implementations.</p>
1730
1731</div>
1732
1733<!-- _______________________________________________________________________ -->
1734<div class="doc_subsubsection">
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1735 <a name="x86_tt">X86 Target Triples Supported</a>
1736</div>
1737
1738<div class="doc_text">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1739
1740<p>The following are the known target triples that are supported by the X86
1741backend. This is not an exhaustive list, and it would be useful to add those
1742that people test.</p>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1743
1744<ul>
1745<li><b>i686-pc-linux-gnu</b> - Linux</li>
1746<li><b>i386-unknown-freebsd5.3</b> - FreeBSD 5.3</li>
1747<li><b>i686-pc-cygwin</b> - Cygwin on Win32</li>
1748<li><b>i686-pc-mingw32</b> - MingW on Win32</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1749<li><b>i686-apple-darwin*</b> - Apple Darwin on X86</li>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1750</ul>
1751
1752</div>
1753
1754<!-- _______________________________________________________________________ -->
1755<div class="doc_subsubsection">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1756 <a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
1757</div>
1758
1759<div class="doc_text">
1760
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1761<p>The x86 has a very flexible way of accessing memory. It is capable of
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1762forming memory addresses of the following expression directly in integer
1763instructions (which use ModR/M addressing):</p>
1764
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1765<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1766<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1767Base + [1,2,4,8] * IndexReg + Disp32
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1768</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1769</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1770
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1771<p>In order to represent this, LLVM tracks no less than 4 operands for each
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1772memory operand of this form. This means that the "load" form of '<tt>mov</tt>'
1773has the following <tt>MachineOperand</tt>s in this order:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1774
1775<pre>
1776Index: 0 | 1 2 3 4
1777Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement
1778OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
1779</pre>
1780
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1781<p>Stores, and all other instructions, treat the four memory operands in the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1782same way and in the same order.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1783
1784</div>
1785
1786<!-- _______________________________________________________________________ -->
1787<div class="doc_subsubsection">
1788 <a name="x86_names">Instruction naming</a>
1789</div>
1790
1791<div class="doc_text">
1792
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1793<p>An instruction name consists of the base name, a default operand size, and a
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1794a character per operand with an optional special size. For example:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1795
1796<p>
1797<tt>ADD8rr</tt> -&gt; add, 8-bit register, 8-bit register<br>
1798<tt>IMUL16rmi</tt> -&gt; imul, 16-bit register, 16-bit memory, 16-bit immediate<br>
1799<tt>IMUL16rmi8</tt> -&gt; imul, 16-bit register, 16-bit memory, 8-bit immediate<br>
1800<tt>MOVSX32rm16</tt> -&gt; movsx, 32-bit register, 16-bit memory
1801</p>
1802
1803</div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1804
1805<!-- *********************************************************************** -->
1806<hr>
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1812
1813 <a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
Reid Spencer05fe4b02006-03-14 05:39:39 +0000[diff] [blame]1814 <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1815 Last modified: $Date$
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