Arnold Schwaighofer | 48abc5c | 2007-10-12 21:30:57 +0000 | [diff] [blame] | 1 | //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===// |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 9 | // |
| 10 | // This file describes the X86 instruction set, defining the instructions, and |
| 11 | // properties of the instructions which are needed for code generation, machine |
| 12 | // code emission, and analysis. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 16 | //===----------------------------------------------------------------------===// |
| 17 | // X86 specific DAG Nodes. |
| 18 | // |
| 19 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 20 | def SDTIntShiftDOp: SDTypeProfile<1, 3, |
| 21 | [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, |
| 22 | SDTCisInt<0>, SDTCisInt<3>]>; |
| 23 | |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 24 | def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 25 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 26 | def SDTX86Cmov : SDTypeProfile<1, 4, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 27 | [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, |
| 28 | SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 29 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 30 | // Unary and binary operator instructions that set EFLAGS as a side-effect. |
| 31 | def SDTUnaryArithWithFlags : SDTypeProfile<1, 1, |
| 32 | [SDTCisInt<0>]>; |
| 33 | def SDTBinaryArithWithFlags : SDTypeProfile<1, 2, |
| 34 | [SDTCisSameAs<0, 1>, |
| 35 | SDTCisSameAs<0, 2>, |
| 36 | SDTCisInt<0>]>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 37 | def SDTX86BrCond : SDTypeProfile<0, 3, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 38 | [SDTCisVT<0, OtherVT>, |
| 39 | SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 40 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 41 | def SDTX86SetCC : SDTypeProfile<1, 2, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 42 | [SDTCisVT<0, i8>, |
| 43 | SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 44 | |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 45 | def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, |
| 46 | SDTCisVT<2, i8>]>; |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 47 | def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 48 | |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 49 | def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>, |
| 50 | SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>; |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 51 | def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 52 | |
Sean Callanan | 1c97ceb | 2009-06-23 23:25:37 +0000 | [diff] [blame] | 53 | def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; |
| 54 | def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, |
| 55 | SDTCisVT<1, i32>]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 56 | |
Dan Gohman | d35121a | 2008-05-29 19:57:41 +0000 | [diff] [blame] | 57 | def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 58 | |
Dan Gohman | d6708ea | 2009-08-15 01:38:56 +0000 | [diff] [blame] | 59 | def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, |
| 60 | SDTCisVT<1, iPTR>, |
| 61 | SDTCisVT<2, iPTR>]>; |
| 62 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 63 | def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; |
| 64 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 65 | def SDTX86RdTsc : SDTypeProfile<0, 0, []>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 66 | |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 67 | def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; |
| 68 | |
Rafael Espindola | 2ee3db3 | 2009-04-17 14:35:58 +0000 | [diff] [blame] | 69 | def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 70 | |
Rafael Espindola | 094fad3 | 2009-04-08 21:14:34 +0000 | [diff] [blame] | 71 | def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 72 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 73 | def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; |
| 74 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 75 | def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; |
| 76 | |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 77 | def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>; |
| 78 | def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 79 | def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; |
| 80 | def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 81 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 82 | def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 83 | |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 84 | def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; |
| 85 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 86 | def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 87 | def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 88 | [SDNPHasChain]>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 89 | def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 90 | |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 91 | def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, |
| 92 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore, |
| 93 | SDNPMayLoad]>; |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 94 | def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8, |
| 95 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore, |
| 96 | SDNPMayLoad]>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 97 | def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary, |
| 98 | [SDNPHasChain, SDNPMayStore, |
| 99 | SDNPMayLoad, SDNPMemOperand]>; |
| 100 | def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary, |
| 101 | [SDNPHasChain, SDNPMayStore, |
| 102 | SDNPMayLoad, SDNPMemOperand]>; |
| 103 | def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary, |
| 104 | [SDNPHasChain, SDNPMayStore, |
| 105 | SDNPMayLoad, SDNPMemOperand]>; |
| 106 | def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary, |
| 107 | [SDNPHasChain, SDNPMayStore, |
| 108 | SDNPMayLoad, SDNPMemOperand]>; |
| 109 | def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary, |
| 110 | [SDNPHasChain, SDNPMayStore, |
| 111 | SDNPMayLoad, SDNPMemOperand]>; |
| 112 | def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary, |
| 113 | [SDNPHasChain, SDNPMayStore, |
| 114 | SDNPMayLoad, SDNPMemOperand]>; |
Dale Johannesen | 880ae36 | 2008-10-03 22:25:52 +0000 | [diff] [blame] | 115 | def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary, |
| 116 | [SDNPHasChain, SDNPMayStore, |
| 117 | SDNPMayLoad, SDNPMemOperand]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 118 | def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, |
| 119 | [SDNPHasChain, SDNPOptInFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 120 | |
Dan Gohman | d6708ea | 2009-08-15 01:38:56 +0000 | [diff] [blame] | 121 | def X86vastart_save_xmm_regs : |
| 122 | SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", |
| 123 | SDT_X86VASTART_SAVE_XMM_REGS, |
| 124 | [SDNPHasChain]>; |
| 125 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 126 | def X86callseq_start : |
| 127 | SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, |
Evan Cheng | bb7b844 | 2006-08-11 09:03:33 +0000 | [diff] [blame] | 128 | [SDNPHasChain, SDNPOutFlag]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 129 | def X86callseq_end : |
| 130 | SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 131 | [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 132 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 133 | def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, |
| 134 | [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 135 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 136 | def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, |
Chris Lattner | 9b37aaf | 2008-01-10 05:12:37 +0000 | [diff] [blame] | 137 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 138 | def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, |
Chris Lattner | 9b37aaf | 2008-01-10 05:12:37 +0000 | [diff] [blame] | 139 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore, |
| 140 | SDNPMayLoad]>; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 141 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 142 | def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc, |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 143 | [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 144 | |
Evan Cheng | 0085a28 | 2006-11-30 21:55:46 +0000 | [diff] [blame] | 145 | def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; |
| 146 | def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 147 | |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 148 | def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, |
Anton Korobeynikov | 6625eff | 2008-05-04 21:36:32 +0000 | [diff] [blame] | 149 | [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; |
Rafael Espindola | 094fad3 | 2009-04-08 21:14:34 +0000 | [diff] [blame] | 150 | def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress", |
| 151 | SDT_X86SegmentBaseAddress, []>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 152 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 153 | def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, |
| 154 | [SDNPHasChain]>; |
| 155 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 156 | def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, |
| 157 | [SDNPHasChain, SDNPOptInFlag]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 158 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 159 | def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags>; |
| 160 | def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; |
| 161 | def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags>; |
| 162 | def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>; |
| 163 | def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; |
| 164 | def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; |
Dan Gohman | e220c4b | 2009-09-18 19:59:53 +0000 | [diff] [blame] | 165 | def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags>; |
| 166 | def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags>; |
| 167 | def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 168 | |
Evan Cheng | 73f24c9 | 2009-03-30 21:36:47 +0000 | [diff] [blame] | 169 | def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; |
| 170 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 171 | //===----------------------------------------------------------------------===// |
| 172 | // X86 Operand Definitions. |
| 173 | // |
| 174 | |
Chris Lattner | 7680e73 | 2009-06-20 19:34:09 +0000 | [diff] [blame] | 175 | def i32imm_pcrel : Operand<i32> { |
| 176 | let PrintMethod = "print_pcrel_imm"; |
| 177 | } |
| 178 | |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 179 | // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for |
| 180 | // the index operand of an address, to conform to x86 encoding restrictions. |
| 181 | def ptr_rc_nosp : PointerLikeRegClass<1>; |
Chris Lattner | 7680e73 | 2009-06-20 19:34:09 +0000 | [diff] [blame] | 182 | |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 183 | // *mem - Operand definitions for the funky X86 addressing mode operands. |
| 184 | // |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 185 | def X86MemAsmOperand : AsmOperandClass { |
| 186 | let Name = "Mem"; |
Daniel Dunbar | 8e00117 | 2009-08-10 19:08:02 +0000 | [diff] [blame] | 187 | let SuperClass = ?; |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 188 | } |
Evan Cheng | af78ef5 | 2006-05-17 21:21:41 +0000 | [diff] [blame] | 189 | class X86MemOperand<string printMethod> : Operand<iPTR> { |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 190 | let PrintMethod = printMethod; |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 191 | let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 192 | let ParserMatchClass = X86MemAsmOperand; |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 193 | } |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 194 | |
Sean Callanan | 9947bbb | 2009-09-03 00:04:47 +0000 | [diff] [blame] | 195 | def opaque32mem : X86MemOperand<"printopaquemem">; |
| 196 | def opaque48mem : X86MemOperand<"printopaquemem">; |
| 197 | def opaque80mem : X86MemOperand<"printopaquemem">; |
| 198 | |
Chris Lattner | 4543251 | 2005-12-17 19:47:05 +0000 | [diff] [blame] | 199 | def i8mem : X86MemOperand<"printi8mem">; |
| 200 | def i16mem : X86MemOperand<"printi16mem">; |
| 201 | def i32mem : X86MemOperand<"printi32mem">; |
| 202 | def i64mem : X86MemOperand<"printi64mem">; |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 203 | def i128mem : X86MemOperand<"printi128mem">; |
Chris Lattner | e895c61 | 2009-09-20 07:17:49 +0000 | [diff] [blame^] | 204 | //def i256mem : X86MemOperand<"printi256mem">; |
Chris Lattner | 4543251 | 2005-12-17 19:47:05 +0000 | [diff] [blame] | 205 | def f32mem : X86MemOperand<"printf32mem">; |
| 206 | def f64mem : X86MemOperand<"printf64mem">; |
Dale Johannesen | 59a5873 | 2007-08-05 18:49:15 +0000 | [diff] [blame] | 207 | def f80mem : X86MemOperand<"printf80mem">; |
Evan Cheng | 223547a | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 208 | def f128mem : X86MemOperand<"printf128mem">; |
Chris Lattner | e895c61 | 2009-09-20 07:17:49 +0000 | [diff] [blame^] | 209 | //def f256mem : X86MemOperand<"printf256mem">; |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 210 | |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 211 | // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of |
| 212 | // plain GR64, so that it doesn't potentially require a REX prefix. |
| 213 | def i8mem_NOREX : Operand<i64> { |
| 214 | let PrintMethod = "printi8mem"; |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 215 | let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm); |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 216 | let ParserMatchClass = X86MemAsmOperand; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 217 | } |
| 218 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 219 | def lea32mem : Operand<i32> { |
Rafael Espindola | 094fad3 | 2009-04-08 21:14:34 +0000 | [diff] [blame] | 220 | let PrintMethod = "printlea32mem"; |
Dan Gohman | 74f6f9a | 2009-08-05 17:40:24 +0000 | [diff] [blame] | 221 | let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm); |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 222 | let ParserMatchClass = X86MemAsmOperand; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 223 | } |
| 224 | |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 225 | def SSECC : Operand<i8> { |
| 226 | let PrintMethod = "printSSECC"; |
| 227 | } |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 228 | |
Evan Cheng | 7ccced6 | 2006-02-18 00:15:05 +0000 | [diff] [blame] | 229 | def piclabel: Operand<i32> { |
| 230 | let PrintMethod = "printPICLabel"; |
| 231 | } |
| 232 | |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 233 | def ImmSExt8AsmOperand : AsmOperandClass { |
| 234 | let Name = "ImmSExt8"; |
| 235 | let SuperClass = ImmAsmOperand; |
| 236 | } |
| 237 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 238 | // A couple of more descriptive operand definitions. |
| 239 | // 16-bits but only 8 bits are significant. |
Daniel Dunbar | 5fe6338 | 2009-08-09 07:20:21 +0000 | [diff] [blame] | 240 | def i16i8imm : Operand<i16> { |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 241 | let ParserMatchClass = ImmSExt8AsmOperand; |
Daniel Dunbar | 5fe6338 | 2009-08-09 07:20:21 +0000 | [diff] [blame] | 242 | } |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 243 | // 32-bits but only 8 bits are significant. |
Daniel Dunbar | 5fe6338 | 2009-08-09 07:20:21 +0000 | [diff] [blame] | 244 | def i32i8imm : Operand<i32> { |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 245 | let ParserMatchClass = ImmSExt8AsmOperand; |
Daniel Dunbar | 5fe6338 | 2009-08-09 07:20:21 +0000 | [diff] [blame] | 246 | } |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 247 | |
Chris Lattner | 7680e73 | 2009-06-20 19:34:09 +0000 | [diff] [blame] | 248 | // Branch targets have OtherVT type and print as pc-relative values. |
| 249 | def brtarget : Operand<OtherVT> { |
| 250 | let PrintMethod = "print_pcrel_imm"; |
| 251 | } |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 252 | |
Evan Cheng | 77159e3 | 2009-07-21 06:00:18 +0000 | [diff] [blame] | 253 | def brtarget8 : Operand<OtherVT> { |
| 254 | let PrintMethod = "print_pcrel_imm"; |
| 255 | } |
| 256 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 257 | //===----------------------------------------------------------------------===// |
| 258 | // X86 Complex Pattern Definitions. |
| 259 | // |
| 260 | |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 261 | // Define X86 specific addressing mode. |
Rafael Espindola | 094fad3 | 2009-04-08 21:14:34 +0000 | [diff] [blame] | 262 | def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 263 | def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr", |
Dan Gohman | a98634b | 2009-08-02 16:09:17 +0000 | [diff] [blame] | 264 | [add, sub, mul, X86mul_imm, shl, or, frameindex], |
| 265 | []>; |
Chris Lattner | 5c0b16d | 2009-06-20 20:38:48 +0000 | [diff] [blame] | 266 | def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr", |
| 267 | [tglobaltlsaddr], []>; |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 268 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 269 | //===----------------------------------------------------------------------===// |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 270 | // X86 Instruction Predicate Definitions. |
Evan Cheng | 28b51439 | 2006-12-05 19:50:18 +0000 | [diff] [blame] | 271 | def HasMMX : Predicate<"Subtarget->hasMMX()">; |
| 272 | def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; |
| 273 | def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; |
| 274 | def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; |
Bill Wendling | bb1ee05 | 2007-04-10 22:10:25 +0000 | [diff] [blame] | 275 | def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; |
Nate Begeman | 63ec90a | 2008-02-03 07:18:54 +0000 | [diff] [blame] | 276 | def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; |
| 277 | def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; |
David Greene | 343dadb | 2009-06-26 22:46:54 +0000 | [diff] [blame] | 278 | def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; |
| 279 | def HasAVX : Predicate<"Subtarget->hasAVX()">; |
| 280 | def HasFMA3 : Predicate<"Subtarget->hasFMA3()">; |
| 281 | def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 282 | def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; |
| 283 | def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; |
Evan Cheng | 28b51439 | 2006-12-05 19:50:18 +0000 | [diff] [blame] | 284 | def In32BitMode : Predicate<"!Subtarget->is64Bit()">; |
| 285 | def In64BitMode : Predicate<"Subtarget->is64Bit()">; |
Anton Korobeynikov | cf6b739 | 2009-08-03 08:12:53 +0000 | [diff] [blame] | 286 | def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; |
| 287 | def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; |
Anton Korobeynikov | d7697d0 | 2009-08-06 11:23:24 +0000 | [diff] [blame] | 288 | def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; |
| 289 | def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; |
| 290 | def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&" |
Anton Korobeynikov | 186fa1d | 2009-08-06 09:11:19 +0000 | [diff] [blame] | 291 | "TM.getCodeModel() != CodeModel::Kernel">; |
Anton Korobeynikov | d7697d0 | 2009-08-06 11:23:24 +0000 | [diff] [blame] | 292 | def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" |
| 293 | "TM.getCodeModel() == CodeModel::Kernel">; |
Evan Cheng | 28b51439 | 2006-12-05 19:50:18 +0000 | [diff] [blame] | 294 | def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; |
Evan Cheng | b7a75a5 | 2008-09-26 23:41:32 +0000 | [diff] [blame] | 295 | def OptForSpeed : Predicate<"!OptForSize">; |
Evan Cheng | ccb6976 | 2009-01-02 05:35:45 +0000 | [diff] [blame] | 296 | def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">; |
Evan Cheng | d7f666a | 2009-05-20 04:53:57 +0000 | [diff] [blame] | 297 | def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 298 | |
| 299 | //===----------------------------------------------------------------------===// |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 300 | // X86 Instruction Format Definitions. |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 301 | // |
| 302 | |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 303 | include "X86InstrFormats.td" |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 304 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 305 | //===----------------------------------------------------------------------===// |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 306 | // Pattern fragments... |
| 307 | // |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 308 | |
| 309 | // X86 specific condition code. These correspond to CondCode in |
Nate Begeman | 9a22530 | 2007-05-06 04:00:55 +0000 | [diff] [blame] | 310 | // X86InstrInfo.h. They must be kept in synch. |
Dan Gohman | 653456c | 2009-01-07 00:15:08 +0000 | [diff] [blame] | 311 | def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE |
| 312 | def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC |
| 313 | def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C |
| 314 | def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA |
| 315 | def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z |
| 316 | def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE |
| 317 | def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL |
| 318 | def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE |
| 319 | def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG |
| 320 | def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 321 | def X86_COND_NO : PatLeaf<(i8 10)>; |
Dan Gohman | 653456c | 2009-01-07 00:15:08 +0000 | [diff] [blame] | 322 | def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 323 | def X86_COND_NS : PatLeaf<(i8 12)>; |
Dan Gohman | 653456c | 2009-01-07 00:15:08 +0000 | [diff] [blame] | 324 | def X86_COND_O : PatLeaf<(i8 13)>; |
| 325 | def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE |
| 326 | def X86_COND_S : PatLeaf<(i8 15)>; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 327 | |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 328 | def i16immSExt8 : PatLeaf<(i16 imm), [{ |
| 329 | // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 330 | // sign extended field. |
Dan Gohman | f5aeb1a | 2008-09-12 16:56:44 +0000 | [diff] [blame] | 331 | return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue(); |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 332 | }]>; |
| 333 | |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 334 | def i32immSExt8 : PatLeaf<(i32 imm), [{ |
| 335 | // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 336 | // sign extended field. |
Dan Gohman | f5aeb1a | 2008-09-12 16:56:44 +0000 | [diff] [blame] | 337 | return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue(); |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 338 | }]>; |
| 339 | |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 340 | // Helper fragments for loads. |
Evan Cheng | b656443 | 2008-05-13 18:59:59 +0000 | [diff] [blame] | 341 | // It's always safe to treat a anyext i16 load as a i32 load if the i16 is |
| 342 | // known to be 32-bit aligned or better. Ditto for i8 to i16. |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 343 | def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 344 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 345 | if (const Value *Src = LD->getSrcValue()) |
| 346 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
Mon P Wang | a7e01d7 | 2009-04-27 07:22:10 +0000 | [diff] [blame] | 347 | if (PT->getAddressSpace() > 255) |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 348 | return false; |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 349 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 350 | if (ExtType == ISD::NON_EXTLOAD) |
| 351 | return true; |
| 352 | if (ExtType == ISD::EXTLOAD) |
| 353 | return LD->getAlignment() >= 2 && !LD->isVolatile(); |
Evan Cheng | fa7fd33 | 2008-05-13 00:54:02 +0000 | [diff] [blame] | 354 | return false; |
| 355 | }]>; |
| 356 | |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 357 | def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 358 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 359 | if (const Value *Src = LD->getSrcValue()) |
| 360 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
Mon P Wang | a7e01d7 | 2009-04-27 07:22:10 +0000 | [diff] [blame] | 361 | if (PT->getAddressSpace() > 255) |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 362 | return false; |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 363 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 364 | if (ExtType == ISD::EXTLOAD) |
| 365 | return LD->getAlignment() >= 2 && !LD->isVolatile(); |
| 366 | return false; |
| 367 | }]>; |
| 368 | |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 369 | def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 370 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 371 | if (const Value *Src = LD->getSrcValue()) |
| 372 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
Mon P Wang | a7e01d7 | 2009-04-27 07:22:10 +0000 | [diff] [blame] | 373 | if (PT->getAddressSpace() > 255) |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 374 | return false; |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 375 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 376 | if (ExtType == ISD::NON_EXTLOAD) |
| 377 | return true; |
| 378 | if (ExtType == ISD::EXTLOAD) |
| 379 | return LD->getAlignment() >= 4 && !LD->isVolatile(); |
Evan Cheng | fa7fd33 | 2008-05-13 00:54:02 +0000 | [diff] [blame] | 380 | return false; |
| 381 | }]>; |
| 382 | |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 383 | def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ |
Evan Cheng | d47e0b6 | 2008-09-29 17:26:18 +0000 | [diff] [blame] | 384 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 385 | if (const Value *Src = LD->getSrcValue()) |
| 386 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
Mon P Wang | a7e01d7 | 2009-04-27 07:22:10 +0000 | [diff] [blame] | 387 | if (PT->getAddressSpace() > 255) |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 388 | return false; |
Evan Cheng | d47e0b6 | 2008-09-29 17:26:18 +0000 | [diff] [blame] | 389 | if (LD->isVolatile()) |
| 390 | return false; |
Evan Cheng | d47e0b6 | 2008-09-29 17:26:18 +0000 | [diff] [blame] | 391 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 392 | if (ExtType == ISD::NON_EXTLOAD) |
| 393 | return true; |
| 394 | if (ExtType == ISD::EXTLOAD) |
| 395 | return LD->getAlignment() >= 4; |
| 396 | return false; |
| 397 | }]>; |
| 398 | |
Nate Begeman | 51a0437 | 2009-01-26 01:24:32 +0000 | [diff] [blame] | 399 | def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 400 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) |
| 401 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
| 402 | return PT->getAddressSpace() == 256; |
Nate Begeman | 51a0437 | 2009-01-26 01:24:32 +0000 | [diff] [blame] | 403 | return false; |
| 404 | }]>; |
| 405 | |
Chris Lattner | 1777d0c | 2009-05-05 18:52:19 +0000 | [diff] [blame] | 406 | def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ |
| 407 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) |
| 408 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
| 409 | return PT->getAddressSpace() == 257; |
| 410 | return false; |
| 411 | }]>; |
| 412 | |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 413 | def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{ |
| 414 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) |
| 415 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
Mon P Wang | a7e01d7 | 2009-04-27 07:22:10 +0000 | [diff] [blame] | 416 | if (PT->getAddressSpace() > 255) |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 417 | return false; |
| 418 | return true; |
| 419 | }]>; |
| 420 | def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{ |
| 421 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) |
| 422 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
Mon P Wang | a7e01d7 | 2009-04-27 07:22:10 +0000 | [diff] [blame] | 423 | if (PT->getAddressSpace() > 255) |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 424 | return false; |
| 425 | return true; |
| 426 | }]>; |
Evan Cheng | 06a8aa1 | 2006-03-17 19:55:52 +0000 | [diff] [blame] | 427 | |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 428 | def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{ |
| 429 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) |
| 430 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
Mon P Wang | a7e01d7 | 2009-04-27 07:22:10 +0000 | [diff] [blame] | 431 | if (PT->getAddressSpace() > 255) |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 432 | return false; |
| 433 | return true; |
| 434 | }]>; |
| 435 | def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{ |
| 436 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) |
| 437 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
Mon P Wang | a7e01d7 | 2009-04-27 07:22:10 +0000 | [diff] [blame] | 438 | if (PT->getAddressSpace() > 255) |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 439 | return false; |
| 440 | return true; |
| 441 | }]>; |
| 442 | def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{ |
| 443 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue()) |
| 444 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) |
Mon P Wang | a7e01d7 | 2009-04-27 07:22:10 +0000 | [diff] [blame] | 445 | if (PT->getAddressSpace() > 255) |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 446 | return false; |
| 447 | return true; |
| 448 | }]>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 449 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 450 | def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; |
| 451 | def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; |
| 452 | def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 453 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 454 | def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; |
| 455 | def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; |
| 456 | def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; |
| 457 | def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; |
| 458 | def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; |
| 459 | def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 460 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 461 | def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; |
| 462 | def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; |
| 463 | def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; |
| 464 | def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; |
| 465 | def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; |
| 466 | def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 467 | |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 468 | |
| 469 | // An 'and' node with a single use. |
| 470 | def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ |
Evan Cheng | 07b7ea1 | 2008-03-04 00:40:35 +0000 | [diff] [blame] | 471 | return N->hasOneUse(); |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 472 | }]>; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 473 | // An 'srl' node with a single use. |
| 474 | def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ |
| 475 | return N->hasOneUse(); |
| 476 | }]>; |
| 477 | // An 'trunc' node with a single use. |
| 478 | def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ |
| 479 | return N->hasOneUse(); |
| 480 | }]>; |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 481 | |
Dan Gohman | 74feef2 | 2008-10-17 01:23:35 +0000 | [diff] [blame] | 482 | // 'shld' and 'shrd' instruction patterns. Note that even though these have |
| 483 | // the srl and shl in their patterns, the C++ code must still check for them, |
| 484 | // because predicates are tested before children nodes are explored. |
| 485 | |
| 486 | def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2), |
| 487 | (or (srl node:$src1, node:$amt1), |
| 488 | (shl node:$src2, node:$amt2)), [{ |
| 489 | assert(N->getOpcode() == ISD::OR); |
| 490 | return N->getOperand(0).getOpcode() == ISD::SRL && |
| 491 | N->getOperand(1).getOpcode() == ISD::SHL && |
| 492 | isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) && |
| 493 | isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) && |
| 494 | N->getOperand(0).getConstantOperandVal(1) == |
| 495 | N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1); |
| 496 | }]>; |
| 497 | |
| 498 | def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2), |
| 499 | (or (shl node:$src1, node:$amt1), |
| 500 | (srl node:$src2, node:$amt2)), [{ |
| 501 | assert(N->getOpcode() == ISD::OR); |
| 502 | return N->getOperand(0).getOpcode() == ISD::SHL && |
| 503 | N->getOperand(1).getOpcode() == ISD::SRL && |
| 504 | isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) && |
| 505 | isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) && |
| 506 | N->getOperand(0).getConstantOperandVal(1) == |
| 507 | N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1); |
| 508 | }]>; |
| 509 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 510 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 511 | // Instruction list... |
| 512 | // |
| 513 | |
Chris Lattner | f18c074 | 2006-10-12 17:42:56 +0000 | [diff] [blame] | 514 | // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into |
| 515 | // a stack adjustment and the codegen must know that they may modify the stack |
| 516 | // pointer before prolog-epilog rewriting occurs. |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 517 | // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become |
| 518 | // sub / add which can clobber EFLAGS. |
Evan Cheng | 8decf6b | 2007-09-28 01:19:48 +0000 | [diff] [blame] | 519 | let Defs = [ESP, EFLAGS], Uses = [ESP] in { |
Dan Gohman | 6d4b052 | 2008-10-01 18:28:06 +0000 | [diff] [blame] | 520 | def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt), |
| 521 | "#ADJCALLSTACKDOWN", |
Chris Lattner | e563bbc | 2008-10-11 22:08:30 +0000 | [diff] [blame] | 522 | [(X86callseq_start timm:$amt)]>, |
Dan Gohman | 6d4b052 | 2008-10-01 18:28:06 +0000 | [diff] [blame] | 523 | Requires<[In32BitMode]>; |
| 524 | def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), |
| 525 | "#ADJCALLSTACKUP", |
Chris Lattner | e563bbc | 2008-10-11 22:08:30 +0000 | [diff] [blame] | 526 | [(X86callseq_end timm:$amt1, timm:$amt2)]>, |
Dan Gohman | 6d4b052 | 2008-10-01 18:28:06 +0000 | [diff] [blame] | 527 | Requires<[In32BitMode]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 528 | } |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 529 | |
Dan Gohman | d6708ea | 2009-08-15 01:38:56 +0000 | [diff] [blame] | 530 | // x86-64 va_start lowering magic. |
| 531 | let usesCustomDAGSchedInserter = 1 in |
| 532 | def VASTART_SAVE_XMM_REGS : I<0, Pseudo, |
| 533 | (outs), |
| 534 | (ins GR8:$al, |
| 535 | i64imm:$regsavefi, i64imm:$offset, |
| 536 | variable_ops), |
| 537 | "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset", |
| 538 | [(X86vastart_save_xmm_regs GR8:$al, |
| 539 | imm:$regsavefi, |
| 540 | imm:$offset)]>; |
| 541 | |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 542 | // Nop |
Sean Callanan | 74e5210 | 2009-07-23 23:39:34 +0000 | [diff] [blame] | 543 | let neverHasSideEffects = 1 in { |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 544 | def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>; |
Sean Callanan | 74e5210 | 2009-07-23 23:39:34 +0000 | [diff] [blame] | 545 | def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero), |
| 546 | "nopl\t$zero", []>, TB; |
| 547 | } |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 548 | |
Sean Callanan | 1c5cf1b | 2009-08-11 01:09:06 +0000 | [diff] [blame] | 549 | // Trap |
| 550 | def INT3 : I<0xcc, RawFrm, (outs), (ins), "int 3", []>; |
| 551 | def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>; |
| 552 | |
Evan Cheng | 0475ab5 | 2008-01-05 00:41:47 +0000 | [diff] [blame] | 553 | // PIC base |
Dan Gohman | 2662d55 | 2008-10-01 04:14:30 +0000 | [diff] [blame] | 554 | let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 555 | def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label), |
Dan Gohman | 4d47b9b | 2009-04-27 15:13:28 +0000 | [diff] [blame] | 556 | "call\t$label\n\t" |
| 557 | "pop{l}\t$reg", []>; |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 558 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 559 | //===----------------------------------------------------------------------===// |
| 560 | // Control Flow Instructions... |
| 561 | // |
| 562 | |
Chris Lattner | 1be4811 | 2005-05-13 17:56:48 +0000 | [diff] [blame] | 563 | // Return instructions. |
Evan Cheng | 2b4ea79 | 2005-12-26 09:11:45 +0000 | [diff] [blame] | 564 | let isTerminator = 1, isReturn = 1, isBarrier = 1, |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 565 | hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in { |
Dan Gohman | e4c67cd | 2008-05-31 02:11:25 +0000 | [diff] [blame] | 566 | def RET : I <0xC3, RawFrm, (outs), (ins variable_ops), |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 567 | "ret", |
Dan Gohman | e4c67cd | 2008-05-31 02:11:25 +0000 | [diff] [blame] | 568 | [(X86retflag 0)]>; |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 569 | def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), |
| 570 | "ret\t$amt", |
Dan Gohman | 2f67df7 | 2009-09-03 17:18:51 +0000 | [diff] [blame] | 571 | [(X86retflag timm:$amt)]>; |
Sean Callanan | 356aed5 | 2009-09-15 23:37:51 +0000 | [diff] [blame] | 572 | def LRET : I <0xCB, RawFrm, (outs), (ins), |
| 573 | "lret", []>; |
| 574 | def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), |
| 575 | "lret\t$amt", []>; |
Evan Cheng | 171049d | 2005-12-23 22:14:32 +0000 | [diff] [blame] | 576 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 577 | |
| 578 | // All branches are RawFrm, Void, Branch, and Terminators |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 579 | let isBranch = 1, isTerminator = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 580 | class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> : |
| 581 | I<opcode, RawFrm, (outs), ins, asm, pattern>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 582 | |
Sean Callanan | 5292588 | 2009-07-22 01:05:20 +0000 | [diff] [blame] | 583 | let isBranch = 1, isBarrier = 1 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 584 | def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>; |
Sean Callanan | 5292588 | 2009-07-22 01:05:20 +0000 | [diff] [blame] | 585 | def JMP8 : IBr<0xEB, (ins brtarget8:$dst), "jmp\t$dst", []>; |
| 586 | } |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 587 | |
Owen Anderson | 20ab290 | 2007-11-12 07:39:39 +0000 | [diff] [blame] | 588 | // Indirect branches |
| 589 | let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 590 | def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 591 | [(brind GR32:$dst)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 592 | def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 593 | [(brind (loadi32 addr:$dst))]>; |
Sean Callanan | 76f14be | 2009-09-15 00:35:17 +0000 | [diff] [blame] | 594 | |
| 595 | def FARJMP16i : Iseg16<0xEA, RawFrm, (outs), |
| 596 | (ins i16imm:$seg, i16imm:$off), |
| 597 | "ljmp{w}\t$seg, $off", []>, OpSize; |
| 598 | def FARJMP32i : Iseg32<0xEA, RawFrm, (outs), |
| 599 | (ins i16imm:$seg, i32imm:$off), |
| 600 | "ljmp{l}\t$seg, $off", []>; |
| 601 | |
| 602 | def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst), |
Sean Callanan | 9947bbb | 2009-09-03 00:04:47 +0000 | [diff] [blame] | 603 | "ljmp{w}\t{*}$dst", []>, OpSize; |
Sean Callanan | 76f14be | 2009-09-15 00:35:17 +0000 | [diff] [blame] | 604 | def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst), |
Sean Callanan | 9947bbb | 2009-09-03 00:04:47 +0000 | [diff] [blame] | 605 | "ljmp{l}\t{*}$dst", []>; |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 606 | } |
| 607 | |
| 608 | // Conditional branches |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 609 | let Uses = [EFLAGS] in { |
Evan Cheng | 77159e3 | 2009-07-21 06:00:18 +0000 | [diff] [blame] | 610 | // Short conditional jumps |
| 611 | def JO8 : IBr<0x70, (ins brtarget8:$dst), "jo\t$dst", []>; |
| 612 | def JNO8 : IBr<0x71, (ins brtarget8:$dst), "jno\t$dst", []>; |
| 613 | def JB8 : IBr<0x72, (ins brtarget8:$dst), "jb\t$dst", []>; |
| 614 | def JAE8 : IBr<0x73, (ins brtarget8:$dst), "jae\t$dst", []>; |
| 615 | def JE8 : IBr<0x74, (ins brtarget8:$dst), "je\t$dst", []>; |
| 616 | def JNE8 : IBr<0x75, (ins brtarget8:$dst), "jne\t$dst", []>; |
| 617 | def JBE8 : IBr<0x76, (ins brtarget8:$dst), "jbe\t$dst", []>; |
| 618 | def JA8 : IBr<0x77, (ins brtarget8:$dst), "ja\t$dst", []>; |
| 619 | def JS8 : IBr<0x78, (ins brtarget8:$dst), "js\t$dst", []>; |
| 620 | def JNS8 : IBr<0x79, (ins brtarget8:$dst), "jns\t$dst", []>; |
| 621 | def JP8 : IBr<0x7A, (ins brtarget8:$dst), "jp\t$dst", []>; |
| 622 | def JNP8 : IBr<0x7B, (ins brtarget8:$dst), "jnp\t$dst", []>; |
| 623 | def JL8 : IBr<0x7C, (ins brtarget8:$dst), "jl\t$dst", []>; |
| 624 | def JGE8 : IBr<0x7D, (ins brtarget8:$dst), "jge\t$dst", []>; |
| 625 | def JLE8 : IBr<0x7E, (ins brtarget8:$dst), "jle\t$dst", []>; |
| 626 | def JG8 : IBr<0x7F, (ins brtarget8:$dst), "jg\t$dst", []>; |
| 627 | |
| 628 | def JCXZ8 : IBr<0xE3, (ins brtarget8:$dst), "jcxz\t$dst", []>; |
| 629 | |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 630 | def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 631 | [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 632 | def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 633 | [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 634 | def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 635 | [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 636 | def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 637 | [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 638 | def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 639 | [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 640 | def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 641 | [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 642 | |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 643 | def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 644 | [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 645 | def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 646 | [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 647 | def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 648 | [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 649 | def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 650 | [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 651 | |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 652 | def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 653 | [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 654 | def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 655 | [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 656 | def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 657 | [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 658 | def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 659 | [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 660 | def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 661 | [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 662 | def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 663 | [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB; |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 664 | } // Uses = [EFLAGS] |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 665 | |
Sean Callanan | 7e6d727 | 2009-09-16 21:50:07 +0000 | [diff] [blame] | 666 | // Loop instructions |
| 667 | |
| 668 | def LOOP : I<0xE2, RawFrm, (ins brtarget8:$dst), (outs), "loop\t$dst", []>; |
| 669 | def LOOPE : I<0xE1, RawFrm, (ins brtarget8:$dst), (outs), "loope\t$dst", []>; |
| 670 | def LOOPNE : I<0xE0, RawFrm, (ins brtarget8:$dst), (outs), "loopne\t$dst", []>; |
| 671 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 672 | //===----------------------------------------------------------------------===// |
| 673 | // Call Instructions... |
| 674 | // |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 675 | let isCall = 1 in |
Dan Gohman | 6d4b052 | 2008-10-01 18:28:06 +0000 | [diff] [blame] | 676 | // All calls clobber the non-callee saved registers. ESP is marked as |
| 677 | // a use to prevent stack-pointer assignments that appear immediately |
| 678 | // before calls from potentially appearing dead. Uses for argument |
| 679 | // registers are added manually. |
Nate Begeman | f63be7d | 2005-07-06 18:59:04 +0000 | [diff] [blame] | 680 | let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, |
Bill Wendling | 3f3a17d | 2007-04-25 21:31:48 +0000 | [diff] [blame] | 681 | MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, |
Evan Cheng | 109a562 | 2008-10-17 21:02:22 +0000 | [diff] [blame] | 682 | XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, |
| 683 | XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], |
Dan Gohman | 2662d55 | 2008-10-01 04:14:30 +0000 | [diff] [blame] | 684 | Uses = [ESP] in { |
Chris Lattner | 7680e73 | 2009-06-20 19:34:09 +0000 | [diff] [blame] | 685 | def CALLpcrel32 : Ii32<0xE8, RawFrm, |
| 686 | (outs), (ins i32imm_pcrel:$dst,variable_ops), |
| 687 | "call\t$dst", []>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 688 | def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 689 | "call\t{*}$dst", [(X86call GR32:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 690 | def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops), |
Dan Gohman | b410617 | 2008-05-29 21:50:34 +0000 | [diff] [blame] | 691 | "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>; |
Sean Callanan | 9947bbb | 2009-09-03 00:04:47 +0000 | [diff] [blame] | 692 | |
Sean Callanan | 76f14be | 2009-09-15 00:35:17 +0000 | [diff] [blame] | 693 | def FARCALL16i : Iseg16<0x9A, RawFrm, (outs), |
| 694 | (ins i16imm:$seg, i16imm:$off), |
| 695 | "lcall{w}\t$seg, $off", []>, OpSize; |
| 696 | def FARCALL32i : Iseg32<0x9A, RawFrm, (outs), |
| 697 | (ins i16imm:$seg, i32imm:$off), |
| 698 | "lcall{l}\t$seg, $off", []>; |
| 699 | |
| 700 | def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst), |
Sean Callanan | 9947bbb | 2009-09-03 00:04:47 +0000 | [diff] [blame] | 701 | "lcall{w}\t{*}$dst", []>, OpSize; |
Sean Callanan | 76f14be | 2009-09-15 00:35:17 +0000 | [diff] [blame] | 702 | def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst), |
Sean Callanan | 9947bbb | 2009-09-03 00:04:47 +0000 | [diff] [blame] | 703 | "lcall{l}\t{*}$dst", []>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 704 | } |
| 705 | |
Sean Callanan | 8d70854 | 2009-09-16 02:57:13 +0000 | [diff] [blame] | 706 | // Constructing a stack frame. |
| 707 | |
| 708 | def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl), |
| 709 | "enter\t$len, $lvl", []>; |
| 710 | |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 711 | // Tail call stuff. |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 712 | |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 713 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Arnold Schwaighofer | 4fe3073 | 2008-03-19 16:39:45 +0000 | [diff] [blame] | 714 | def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops), |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 715 | "#TC_RETURN $dst $offset", |
| 716 | []>; |
| 717 | |
| 718 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Arnold Schwaighofer | 4fe3073 | 2008-03-19 16:39:45 +0000 | [diff] [blame] | 719 | def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops), |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 720 | "#TC_RETURN $dst $offset", |
| 721 | []>; |
| 722 | |
| 723 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 724 | |
Chris Lattner | 7680e73 | 2009-06-20 19:34:09 +0000 | [diff] [blame] | 725 | def TAILJMPd : IBr<0xE9, (ins i32imm_pcrel:$dst), "jmp\t$dst # TAILCALL", |
Evan Cheng | f10c17f | 2006-09-22 21:43:59 +0000 | [diff] [blame] | 726 | []>; |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 727 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 728 | def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL", |
| 729 | []>; |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 730 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 731 | def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 732 | "jmp\t{*}$dst # TAILCALL", []>; |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 733 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 734 | //===----------------------------------------------------------------------===// |
| 735 | // Miscellaneous Instructions... |
| 736 | // |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 737 | let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 738 | def LEAVE : I<0xC9, RawFrm, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 739 | (outs), (ins), "leave", []>; |
| 740 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 741 | let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in { |
Sean Callanan | 1f24e01 | 2009-09-10 18:29:13 +0000 | [diff] [blame] | 742 | let mayLoad = 1 in { |
| 743 | def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, |
| 744 | OpSize; |
| 745 | def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>; |
| 746 | def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, |
| 747 | OpSize; |
| 748 | def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>, |
| 749 | OpSize; |
| 750 | def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>; |
| 751 | def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>; |
| 752 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 753 | |
Sean Callanan | 1f24e01 | 2009-09-10 18:29:13 +0000 | [diff] [blame] | 754 | let mayStore = 1 in { |
| 755 | def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, |
| 756 | OpSize; |
Evan Cheng | 2f245ba | 2007-09-26 01:29:06 +0000 | [diff] [blame] | 757 | def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>; |
Sean Callanan | 1f24e01 | 2009-09-10 18:29:13 +0000 | [diff] [blame] | 758 | def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, |
| 759 | OpSize; |
| 760 | def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>, |
| 761 | OpSize; |
| 762 | def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>; |
| 763 | def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>; |
| 764 | } |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 765 | } |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 766 | |
Bill Wendling | 453eb26 | 2009-06-15 19:39:04 +0000 | [diff] [blame] | 767 | let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in { |
| 768 | def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm), |
Bill Wendling | 927788c | 2009-06-15 20:59:31 +0000 | [diff] [blame] | 769 | "push{l}\t$imm", []>; |
Bill Wendling | 453eb26 | 2009-06-15 19:39:04 +0000 | [diff] [blame] | 770 | def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), |
Bill Wendling | 927788c | 2009-06-15 20:59:31 +0000 | [diff] [blame] | 771 | "push{l}\t$imm", []>; |
Bill Wendling | 453eb26 | 2009-06-15 19:39:04 +0000 | [diff] [blame] | 772 | def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), |
Bill Wendling | 927788c | 2009-06-15 20:59:31 +0000 | [diff] [blame] | 773 | "push{l}\t$imm", []>; |
Bill Wendling | 453eb26 | 2009-06-15 19:39:04 +0000 | [diff] [blame] | 774 | } |
| 775 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 776 | let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in |
Evan Cheng | bf4f89d | 2007-09-26 21:28:00 +0000 | [diff] [blame] | 777 | def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 778 | let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in |
Evan Cheng | bf4f89d | 2007-09-26 21:28:00 +0000 | [diff] [blame] | 779 | def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>; |
Evan Cheng | 2f245ba | 2007-09-26 01:29:06 +0000 | [diff] [blame] | 780 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 781 | let isTwoAddress = 1 in // GR32 = bswap GR32 |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 782 | def BSWAP32r : I<0xC8, AddRegFrm, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 783 | (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 784 | "bswap{l}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 785 | [(set GR32:$dst, (bswap GR32:$src))]>, TB; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 786 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 787 | |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 788 | // Bit scan instructions. |
| 789 | let Defs = [EFLAGS] in { |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 790 | def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 791 | "bsf{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 792 | [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 793 | def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 794 | "bsf{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 795 | [(set GR16:$dst, (X86bsf (loadi16 addr:$src))), |
| 796 | (implicit EFLAGS)]>, TB; |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 797 | def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 798 | "bsf{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 799 | [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 800 | def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 801 | "bsf{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 802 | [(set GR32:$dst, (X86bsf (loadi32 addr:$src))), |
| 803 | (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 804 | |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 805 | def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 806 | "bsr{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 807 | [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 808 | def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 809 | "bsr{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 810 | [(set GR16:$dst, (X86bsr (loadi16 addr:$src))), |
| 811 | (implicit EFLAGS)]>, TB; |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 812 | def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 813 | "bsr{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 814 | [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 815 | def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 816 | "bsr{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 817 | [(set GR32:$dst, (X86bsr (loadi32 addr:$src))), |
| 818 | (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 819 | } // Defs = [EFLAGS] |
| 820 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 821 | let neverHasSideEffects = 1 in |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 822 | def LEA16r : I<0x8D, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 823 | (outs GR16:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 824 | "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize; |
Evan Cheng | e771ebd | 2008-03-27 01:41:09 +0000 | [diff] [blame] | 825 | let isReMaterializable = 1 in |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 826 | def LEA32r : I<0x8D, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 827 | (outs GR32:$dst), (ins lea32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 828 | "lea{l}\t{$src|$dst}, {$dst|$src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 829 | [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 830 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 831 | let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 832 | def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 833 | [(X86rep_movs i8)]>, REP; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 834 | def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 835 | [(X86rep_movs i16)]>, REP, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 836 | def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 837 | [(X86rep_movs i32)]>, REP; |
| 838 | } |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 839 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 840 | let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 841 | def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 842 | [(X86rep_stos i8)]>, REP; |
| 843 | let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 844 | def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 845 | [(X86rep_stos i16)]>, REP, OpSize; |
| 846 | let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 847 | def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 848 | [(X86rep_stos i32)]>, REP; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 849 | |
Sean Callanan | a82e465 | 2009-09-12 00:37:19 +0000 | [diff] [blame] | 850 | def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>; |
| 851 | def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize; |
| 852 | def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>; |
| 853 | |
Sean Callanan | 6f8f462 | 2009-09-12 02:25:20 +0000 | [diff] [blame] | 854 | def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>; |
| 855 | def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize; |
| 856 | def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>; |
| 857 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 858 | let Defs = [RAX, RDX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 859 | def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 860 | TB; |
Chris Lattner | b89abef | 2004-02-14 04:45:37 +0000 | [diff] [blame] | 861 | |
Anton Korobeynikov | 66fac79 | 2008-01-15 07:02:33 +0000 | [diff] [blame] | 862 | let isBarrier = 1, hasCtrlDep = 1 in { |
Chris Lattner | da68d30 | 2008-01-15 21:58:22 +0000 | [diff] [blame] | 863 | def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB; |
Anton Korobeynikov | 66fac79 | 2008-01-15 07:02:33 +0000 | [diff] [blame] | 864 | } |
| 865 | |
Chris Lattner | 02552de | 2009-08-11 16:58:39 +0000 | [diff] [blame] | 866 | def SYSCALL : I<0x05, RawFrm, |
| 867 | (outs), (ins), "syscall", []>, TB; |
| 868 | def SYSRET : I<0x07, RawFrm, |
| 869 | (outs), (ins), "sysret", []>, TB; |
| 870 | def SYSENTER : I<0x34, RawFrm, |
| 871 | (outs), (ins), "sysenter", []>, TB; |
| 872 | def SYSEXIT : I<0x35, RawFrm, |
| 873 | (outs), (ins), "sysexit", []>, TB; |
| 874 | |
Sean Callanan | 2a46f36 | 2009-09-12 02:52:41 +0000 | [diff] [blame] | 875 | def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>; |
Chris Lattner | 02552de | 2009-08-11 16:58:39 +0000 | [diff] [blame] | 876 | |
| 877 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 878 | //===----------------------------------------------------------------------===// |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 879 | // Input/Output Instructions... |
| 880 | // |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 881 | let Defs = [AL], Uses = [DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 882 | def IN8rr : I<0xEC, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 883 | "in{b}\t{%dx, %al|%AL, %DX}", []>; |
| 884 | let Defs = [AX], Uses = [DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 885 | def IN16rr : I<0xED, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 886 | "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize; |
| 887 | let Defs = [EAX], Uses = [DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 888 | def IN32rr : I<0xED, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 889 | "in{l}\t{%dx, %eax|%EAX, %DX}", []>; |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 890 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 891 | let Defs = [AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 892 | def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 893 | "in{b}\t{$port, %al|%AL, $port}", []>; |
| 894 | let Defs = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 895 | def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 896 | "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize; |
| 897 | let Defs = [EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 898 | def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 899 | "in{l}\t{$port, %eax|%EAX, $port}", []>; |
Chris Lattner | 440bbc2 | 2004-04-13 17:19:31 +0000 | [diff] [blame] | 900 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 901 | let Uses = [DX, AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 902 | def OUT8rr : I<0xEE, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 903 | "out{b}\t{%al, %dx|%DX, %AL}", []>; |
| 904 | let Uses = [DX, AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 905 | def OUT16rr : I<0xEF, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 906 | "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize; |
| 907 | let Uses = [DX, EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 908 | def OUT32rr : I<0xEF, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 909 | "out{l}\t{%eax, %dx|%DX, %EAX}", []>; |
Chris Lattner | ffff708 | 2004-08-01 07:44:35 +0000 | [diff] [blame] | 910 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 911 | let Uses = [AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 912 | def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 913 | "out{b}\t{%al, $port|$port, %AL}", []>; |
| 914 | let Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 915 | def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 916 | "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize; |
| 917 | let Uses = [EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 918 | def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 919 | "out{l}\t{%eax, $port|$port, %EAX}", []>; |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 920 | |
| 921 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 922 | // Move Instructions... |
| 923 | // |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 924 | let neverHasSideEffects = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 925 | def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 926 | "mov{b}\t{$src, $dst|$dst, $src}", []>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 927 | def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 928 | "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 929 | def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 930 | "mov{l}\t{$src, $dst|$dst, $src}", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 931 | } |
Evan Cheng | 359e937 | 2008-06-18 08:13:07 +0000 | [diff] [blame] | 932 | let isReMaterializable = 1, isAsCheapAsAMove = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 933 | def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 934 | "mov{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 935 | [(set GR8:$dst, imm:$src)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 936 | def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 937 | "mov{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 938 | [(set GR16:$dst, imm:$src)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 939 | def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 940 | "mov{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 941 | [(set GR32:$dst, imm:$src)]>; |
Dan Gohman | d45eddd | 2007-06-26 00:48:07 +0000 | [diff] [blame] | 942 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 943 | def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 944 | "mov{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 945 | [(store (i8 imm:$src), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 946 | def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 947 | "mov{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 948 | [(store (i16 imm:$src), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 949 | def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 950 | "mov{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 951 | [(store (i32 imm:$src), addr:$dst)]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 952 | |
Sean Callanan | 2f34a13 | 2009-09-10 18:33:42 +0000 | [diff] [blame] | 953 | def MOV8o8a : Ii8 <0xA0, RawFrm, (outs), (ins i8imm:$src), |
| 954 | "mov{b}\t{$src, %al|%al, $src}", []>; |
| 955 | def MOV16o16a : Ii16 <0xA1, RawFrm, (outs), (ins i16imm:$src), |
| 956 | "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 957 | def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins i32imm:$src), |
| 958 | "mov{l}\t{$src, %eax|%eax, $src}", []>; |
| 959 | |
| 960 | def MOV8ao8 : Ii8 <0xA2, RawFrm, (outs i8imm:$dst), (ins), |
| 961 | "mov{b}\t{%al, $dst|$dst, %al}", []>; |
| 962 | def MOV16ao16 : Ii16 <0xA3, RawFrm, (outs i16imm:$dst), (ins), |
| 963 | "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize; |
| 964 | def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs i32imm:$dst), (ins), |
| 965 | "mov{l}\t{%eax, $dst|$dst, %eax}", []>; |
| 966 | |
Sean Callanan | 38fee0e | 2009-09-15 18:47:29 +0000 | [diff] [blame] | 967 | // Moves to and from segment registers |
| 968 | def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src), |
| 969 | "mov{w}\t{$src, $dst|$dst, $src}", []>; |
| 970 | def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src), |
| 971 | "mov{w}\t{$src, $dst|$dst, $src}", []>; |
| 972 | def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src), |
| 973 | "mov{w}\t{$src, $dst|$dst, $src}", []>; |
| 974 | def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src), |
| 975 | "mov{w}\t{$src, $dst|$dst, $src}", []>; |
| 976 | |
Dan Gohman | 15511cf | 2008-12-03 18:15:48 +0000 | [diff] [blame] | 977 | let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 978 | def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 979 | "mov{b}\t{$src, $dst|$dst, $src}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 980 | [(set GR8:$dst, (loadi8 addr:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 981 | def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 982 | "mov{w}\t{$src, $dst|$dst, $src}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 983 | [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 984 | def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 985 | "mov{l}\t{$src, $dst|$dst, $src}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 986 | [(set GR32:$dst, (loadi32 addr:$src))]>; |
Evan Cheng | 2f39426 | 2007-08-30 05:49:43 +0000 | [diff] [blame] | 987 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 988 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 989 | def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 990 | "mov{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 991 | [(store GR8:$src, addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 992 | def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 993 | "mov{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 994 | [(store GR16:$src, addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 995 | def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 996 | "mov{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 997 | [(store GR32:$src, addr:$dst)]>; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 998 | |
Dan Gohman | 4af325d | 2009-04-27 16:41:36 +0000 | [diff] [blame] | 999 | // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so |
| 1000 | // that they can be used for copying and storing h registers, which can't be |
| 1001 | // encoded when a REX prefix is present. |
Dan Gohman | 6d9305c | 2009-04-15 00:04:23 +0000 | [diff] [blame] | 1002 | let neverHasSideEffects = 1 in |
Dan Gohman | df7dfc7 | 2009-04-15 19:48:57 +0000 | [diff] [blame] | 1003 | def MOV8rr_NOREX : I<0x88, MRMDestReg, |
| 1004 | (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), |
Dan Gohman | 6d9305c | 2009-04-15 00:04:23 +0000 | [diff] [blame] | 1005 | "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>; |
Evan Cheng | 8c14740 | 2009-04-30 00:58:57 +0000 | [diff] [blame] | 1006 | let mayStore = 1 in |
Dan Gohman | 6d9305c | 2009-04-15 00:04:23 +0000 | [diff] [blame] | 1007 | def MOV8mr_NOREX : I<0x88, MRMDestMem, |
| 1008 | (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), |
| 1009 | "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>; |
Evan Cheng | 8c14740 | 2009-04-30 00:58:57 +0000 | [diff] [blame] | 1010 | let mayLoad = 1, |
| 1011 | canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in |
Dan Gohman | 4af325d | 2009-04-27 16:41:36 +0000 | [diff] [blame] | 1012 | def MOV8rm_NOREX : I<0x8A, MRMSrcMem, |
| 1013 | (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), |
| 1014 | "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 1015 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1016 | //===----------------------------------------------------------------------===// |
| 1017 | // Fixed-Register Multiplication and Division Instructions... |
| 1018 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1019 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 1020 | // Extra precision multiplication |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1021 | let Defs = [AL,AH,EFLAGS], Uses = [AL] in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1022 | def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src", |
Evan Cheng | cf74a7c | 2006-01-15 10:05:20 +0000 | [diff] [blame] | 1023 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits. |
| 1024 | // This probably ought to be moved to a def : Pat<> if the |
| 1025 | // syntax can be accepted. |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1026 | [(set AL, (mul AL, GR8:$src)), |
| 1027 | (implicit EFLAGS)]>; // AL,AH = AL*GR8 |
| 1028 | |
Chris Lattner | a731c9f | 2008-01-11 07:18:17 +0000 | [diff] [blame] | 1029 | let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1030 | def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), |
| 1031 | "mul{w}\t$src", |
| 1032 | []>, OpSize; // AX,DX = AX*GR16 |
| 1033 | |
Chris Lattner | a731c9f | 2008-01-11 07:18:17 +0000 | [diff] [blame] | 1034 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1035 | def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), |
| 1036 | "mul{l}\t$src", |
| 1037 | []>; // EAX,EDX = EAX*GR32 |
| 1038 | |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1039 | let Defs = [AL,AH,EFLAGS], Uses = [AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1040 | def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1041 | "mul{b}\t$src", |
Evan Cheng | cf74a7c | 2006-01-15 10:05:20 +0000 | [diff] [blame] | 1042 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits. |
| 1043 | // This probably ought to be moved to a def : Pat<> if the |
| 1044 | // syntax can be accepted. |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1045 | [(set AL, (mul AL, (loadi8 addr:$src))), |
| 1046 | (implicit EFLAGS)]>; // AL,AH = AL*[mem8] |
| 1047 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1048 | let mayLoad = 1, neverHasSideEffects = 1 in { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1049 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1050 | def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1051 | "mul{w}\t$src", |
| 1052 | []>, OpSize; // AX,DX = AX*[mem16] |
| 1053 | |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1054 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1055 | def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1056 | "mul{l}\t$src", |
| 1057 | []>; // EAX,EDX = EAX*[mem32] |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1058 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1059 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1060 | let neverHasSideEffects = 1 in { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1061 | let Defs = [AL,AH,EFLAGS], Uses = [AL] in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1062 | def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>; |
| 1063 | // AL,AH = AL*GR8 |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1064 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1065 | def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1066 | OpSize; // AX,DX = AX*GR16 |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1067 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1068 | def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>; |
| 1069 | // EAX,EDX = EAX*GR32 |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1070 | let mayLoad = 1 in { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1071 | let Defs = [AL,AH,EFLAGS], Uses = [AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1072 | def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1073 | "imul{b}\t$src", []>; // AL,AH = AL*[mem8] |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1074 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1075 | def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1076 | "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16] |
| 1077 | let Defs = [EAX,EDX], Uses = [EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1078 | def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1079 | "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32] |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1080 | } |
Dan Gohman | c99da13 | 2008-11-18 21:29:14 +0000 | [diff] [blame] | 1081 | } // neverHasSideEffects |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 1082 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 1083 | // unsigned division/remainder |
Dale Johannesen | 2cb48ea | 2008-10-07 18:54:28 +0000 | [diff] [blame] | 1084 | let Defs = [AL,AH,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1085 | def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1086 | "div{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1087 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1088 | def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1089 | "div{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1090 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1091 | def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1092 | "div{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1093 | let mayLoad = 1 in { |
Dale Johannesen | 2cb48ea | 2008-10-07 18:54:28 +0000 | [diff] [blame] | 1094 | let Defs = [AL,AH,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1095 | def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1096 | "div{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1097 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1098 | def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1099 | "div{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1100 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1101 | def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1102 | "div{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1103 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1104 | |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 1105 | // Signed division/remainder. |
Dale Johannesen | 2cb48ea | 2008-10-07 18:54:28 +0000 | [diff] [blame] | 1106 | let Defs = [AL,AH,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1107 | def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1108 | "idiv{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1109 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1110 | def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1111 | "idiv{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1112 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1113 | def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1114 | "idiv{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1115 | let mayLoad = 1, mayLoad = 1 in { |
Dale Johannesen | 2cb48ea | 2008-10-07 18:54:28 +0000 | [diff] [blame] | 1116 | let Defs = [AL,AH,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1117 | def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1118 | "idiv{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1119 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1120 | def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1121 | "idiv{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1122 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1123 | def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1124 | "idiv{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1125 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1126 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1127 | //===----------------------------------------------------------------------===// |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1128 | // Two address Instructions. |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1129 | // |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1130 | let isTwoAddress = 1 in { |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1131 | |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 1132 | // Conditional moves |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 1133 | let Uses = [EFLAGS] in { |
Dan Gohman | cbbea0f | 2009-08-27 00:14:12 +0000 | [diff] [blame] | 1134 | |
| 1135 | // X86 doesn't have 8-bit conditional moves. Use a customDAGSchedInserter to |
| 1136 | // emit control flow. An alternative to this is to mark i8 SELECT as Promote, |
| 1137 | // however that requires promoting the operands, and can induce additional |
Dan Gohman | 71a258c | 2009-08-29 22:19:15 +0000 | [diff] [blame] | 1138 | // i8 register pressure. Note that CMOV_GR8 is conservatively considered to |
| 1139 | // clobber EFLAGS, because if one of the operands is zero, the expansion |
| 1140 | // could involve an xor. |
| 1141 | let usesCustomDAGSchedInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in |
Dan Gohman | cbbea0f | 2009-08-27 00:14:12 +0000 | [diff] [blame] | 1142 | def CMOV_GR8 : I<0, Pseudo, |
| 1143 | (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond), |
| 1144 | "#CMOV_GR8 PSEUDO!", |
| 1145 | [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2, |
| 1146 | imm:$cond, EFLAGS))]>; |
| 1147 | |
Dan Gohman | a4c5c33 | 2009-08-27 18:16:24 +0000 | [diff] [blame] | 1148 | let isCommutable = 1 in { |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1149 | def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1150 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1151 | "cmovb\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1152 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1153 | X86_COND_B, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1154 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1155 | def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1156 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1157 | "cmovb\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1158 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1159 | X86_COND_B, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1160 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1161 | def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1162 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1163 | "cmovae\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1164 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1165 | X86_COND_AE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1166 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1167 | def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1168 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1169 | "cmovae\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1170 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1171 | X86_COND_AE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1172 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1173 | def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1174 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1175 | "cmove\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1176 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1177 | X86_COND_E, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1178 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1179 | def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1180 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1181 | "cmove\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1182 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1183 | X86_COND_E, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1184 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1185 | def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1186 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1187 | "cmovne\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1188 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1189 | X86_COND_NE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1190 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1191 | def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1192 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1193 | "cmovne\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1194 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1195 | X86_COND_NE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1196 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1197 | def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1198 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1199 | "cmovbe\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1200 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1201 | X86_COND_BE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1202 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1203 | def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1204 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1205 | "cmovbe\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1206 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1207 | X86_COND_BE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1208 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1209 | def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1210 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1211 | "cmova\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1212 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1213 | X86_COND_A, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1214 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1215 | def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1216 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1217 | "cmova\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1218 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1219 | X86_COND_A, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1220 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1221 | def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1222 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1223 | "cmovl\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1224 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1225 | X86_COND_L, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1226 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1227 | def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1228 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1229 | "cmovl\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1230 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1231 | X86_COND_L, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1232 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1233 | def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1234 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1235 | "cmovge\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1236 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1237 | X86_COND_GE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1238 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1239 | def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1240 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1241 | "cmovge\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1242 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1243 | X86_COND_GE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1244 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1245 | def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1246 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1247 | "cmovle\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1248 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1249 | X86_COND_LE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1250 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1251 | def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1252 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1253 | "cmovle\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1254 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1255 | X86_COND_LE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1256 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1257 | def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1258 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1259 | "cmovg\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1260 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1261 | X86_COND_G, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1262 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1263 | def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1264 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1265 | "cmovg\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1266 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1267 | X86_COND_G, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1268 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1269 | def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1270 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1271 | "cmovs\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1272 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1273 | X86_COND_S, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1274 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1275 | def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1276 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1277 | "cmovs\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1278 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1279 | X86_COND_S, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1280 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1281 | def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1282 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1283 | "cmovns\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1284 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1285 | X86_COND_NS, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1286 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1287 | def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1288 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1289 | "cmovns\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1290 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1291 | X86_COND_NS, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1292 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1293 | def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1294 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1295 | "cmovp\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1296 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1297 | X86_COND_P, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1298 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1299 | def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1300 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1301 | "cmovp\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1302 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1303 | X86_COND_P, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1304 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1305 | def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1306 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1307 | "cmovnp\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1308 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1309 | X86_COND_NP, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1310 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1311 | def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1312 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1313 | "cmovnp\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1314 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1315 | X86_COND_NP, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 1316 | TB; |
Dan Gohman | 305fceb | 2009-01-07 00:35:10 +0000 | [diff] [blame] | 1317 | def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16 |
| 1318 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
| 1319 | "cmovo\t{$src2, $dst|$dst, $src2}", |
| 1320 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
| 1321 | X86_COND_O, EFLAGS))]>, |
| 1322 | TB, OpSize; |
| 1323 | def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32 |
| 1324 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
| 1325 | "cmovo\t{$src2, $dst|$dst, $src2}", |
| 1326 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
| 1327 | X86_COND_O, EFLAGS))]>, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 1328 | TB; |
Dan Gohman | 305fceb | 2009-01-07 00:35:10 +0000 | [diff] [blame] | 1329 | def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16 |
| 1330 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
| 1331 | "cmovno\t{$src2, $dst|$dst, $src2}", |
| 1332 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
| 1333 | X86_COND_NO, EFLAGS))]>, |
| 1334 | TB, OpSize; |
| 1335 | def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32 |
| 1336 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
| 1337 | "cmovno\t{$src2, $dst|$dst, $src2}", |
| 1338 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
| 1339 | X86_COND_NO, EFLAGS))]>, |
| 1340 | TB; |
| 1341 | } // isCommutable = 1 |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 1342 | |
| 1343 | def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16] |
| 1344 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1345 | "cmovb\t{$src2, $dst|$dst, $src2}", |
| 1346 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1347 | X86_COND_B, EFLAGS))]>, |
| 1348 | TB, OpSize; |
| 1349 | def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32] |
| 1350 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1351 | "cmovb\t{$src2, $dst|$dst, $src2}", |
| 1352 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1353 | X86_COND_B, EFLAGS))]>, |
| 1354 | TB; |
| 1355 | def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16] |
| 1356 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1357 | "cmovae\t{$src2, $dst|$dst, $src2}", |
| 1358 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1359 | X86_COND_AE, EFLAGS))]>, |
| 1360 | TB, OpSize; |
| 1361 | def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32] |
| 1362 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1363 | "cmovae\t{$src2, $dst|$dst, $src2}", |
| 1364 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1365 | X86_COND_AE, EFLAGS))]>, |
| 1366 | TB; |
| 1367 | def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16] |
| 1368 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1369 | "cmove\t{$src2, $dst|$dst, $src2}", |
| 1370 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1371 | X86_COND_E, EFLAGS))]>, |
| 1372 | TB, OpSize; |
| 1373 | def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32] |
| 1374 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1375 | "cmove\t{$src2, $dst|$dst, $src2}", |
| 1376 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1377 | X86_COND_E, EFLAGS))]>, |
| 1378 | TB; |
| 1379 | def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16] |
| 1380 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1381 | "cmovne\t{$src2, $dst|$dst, $src2}", |
| 1382 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1383 | X86_COND_NE, EFLAGS))]>, |
| 1384 | TB, OpSize; |
| 1385 | def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32] |
| 1386 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1387 | "cmovne\t{$src2, $dst|$dst, $src2}", |
| 1388 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1389 | X86_COND_NE, EFLAGS))]>, |
| 1390 | TB; |
| 1391 | def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16] |
| 1392 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1393 | "cmovbe\t{$src2, $dst|$dst, $src2}", |
| 1394 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1395 | X86_COND_BE, EFLAGS))]>, |
| 1396 | TB, OpSize; |
| 1397 | def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32] |
| 1398 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1399 | "cmovbe\t{$src2, $dst|$dst, $src2}", |
| 1400 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1401 | X86_COND_BE, EFLAGS))]>, |
| 1402 | TB; |
| 1403 | def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16] |
| 1404 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1405 | "cmova\t{$src2, $dst|$dst, $src2}", |
| 1406 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1407 | X86_COND_A, EFLAGS))]>, |
| 1408 | TB, OpSize; |
| 1409 | def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32] |
| 1410 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1411 | "cmova\t{$src2, $dst|$dst, $src2}", |
| 1412 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1413 | X86_COND_A, EFLAGS))]>, |
| 1414 | TB; |
| 1415 | def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16] |
| 1416 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1417 | "cmovl\t{$src2, $dst|$dst, $src2}", |
| 1418 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1419 | X86_COND_L, EFLAGS))]>, |
| 1420 | TB, OpSize; |
| 1421 | def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32] |
| 1422 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1423 | "cmovl\t{$src2, $dst|$dst, $src2}", |
| 1424 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1425 | X86_COND_L, EFLAGS))]>, |
| 1426 | TB; |
| 1427 | def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16] |
| 1428 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1429 | "cmovge\t{$src2, $dst|$dst, $src2}", |
| 1430 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1431 | X86_COND_GE, EFLAGS))]>, |
| 1432 | TB, OpSize; |
| 1433 | def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32] |
| 1434 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1435 | "cmovge\t{$src2, $dst|$dst, $src2}", |
| 1436 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1437 | X86_COND_GE, EFLAGS))]>, |
| 1438 | TB; |
| 1439 | def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16] |
| 1440 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1441 | "cmovle\t{$src2, $dst|$dst, $src2}", |
| 1442 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1443 | X86_COND_LE, EFLAGS))]>, |
| 1444 | TB, OpSize; |
| 1445 | def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32] |
| 1446 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1447 | "cmovle\t{$src2, $dst|$dst, $src2}", |
| 1448 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1449 | X86_COND_LE, EFLAGS))]>, |
| 1450 | TB; |
| 1451 | def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16] |
| 1452 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1453 | "cmovg\t{$src2, $dst|$dst, $src2}", |
| 1454 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1455 | X86_COND_G, EFLAGS))]>, |
| 1456 | TB, OpSize; |
| 1457 | def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32] |
| 1458 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1459 | "cmovg\t{$src2, $dst|$dst, $src2}", |
| 1460 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1461 | X86_COND_G, EFLAGS))]>, |
| 1462 | TB; |
| 1463 | def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16] |
| 1464 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1465 | "cmovs\t{$src2, $dst|$dst, $src2}", |
| 1466 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1467 | X86_COND_S, EFLAGS))]>, |
| 1468 | TB, OpSize; |
| 1469 | def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32] |
| 1470 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1471 | "cmovs\t{$src2, $dst|$dst, $src2}", |
| 1472 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1473 | X86_COND_S, EFLAGS))]>, |
| 1474 | TB; |
| 1475 | def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16] |
| 1476 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1477 | "cmovns\t{$src2, $dst|$dst, $src2}", |
| 1478 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1479 | X86_COND_NS, EFLAGS))]>, |
| 1480 | TB, OpSize; |
| 1481 | def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32] |
| 1482 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1483 | "cmovns\t{$src2, $dst|$dst, $src2}", |
| 1484 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1485 | X86_COND_NS, EFLAGS))]>, |
| 1486 | TB; |
| 1487 | def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16] |
| 1488 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1489 | "cmovp\t{$src2, $dst|$dst, $src2}", |
| 1490 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1491 | X86_COND_P, EFLAGS))]>, |
| 1492 | TB, OpSize; |
| 1493 | def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32] |
| 1494 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1495 | "cmovp\t{$src2, $dst|$dst, $src2}", |
| 1496 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1497 | X86_COND_P, EFLAGS))]>, |
| 1498 | TB; |
| 1499 | def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16] |
| 1500 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1501 | "cmovnp\t{$src2, $dst|$dst, $src2}", |
| 1502 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1503 | X86_COND_NP, EFLAGS))]>, |
| 1504 | TB, OpSize; |
Dan Gohman | 305fceb | 2009-01-07 00:35:10 +0000 | [diff] [blame] | 1505 | def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32] |
| 1506 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1507 | "cmovnp\t{$src2, $dst|$dst, $src2}", |
| 1508 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1509 | X86_COND_NP, EFLAGS))]>, |
| 1510 | TB; |
| 1511 | def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16] |
| 1512 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1513 | "cmovo\t{$src2, $dst|$dst, $src2}", |
| 1514 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1515 | X86_COND_O, EFLAGS))]>, |
| 1516 | TB, OpSize; |
| 1517 | def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32] |
| 1518 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1519 | "cmovo\t{$src2, $dst|$dst, $src2}", |
| 1520 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1521 | X86_COND_O, EFLAGS))]>, |
| 1522 | TB; |
| 1523 | def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16] |
| 1524 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1525 | "cmovno\t{$src2, $dst|$dst, $src2}", |
| 1526 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1527 | X86_COND_NO, EFLAGS))]>, |
| 1528 | TB, OpSize; |
| 1529 | def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32] |
| 1530 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1531 | "cmovno\t{$src2, $dst|$dst, $src2}", |
| 1532 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1533 | X86_COND_NO, EFLAGS))]>, |
| 1534 | TB; |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 1535 | } // Uses = [EFLAGS] |
| 1536 | |
| 1537 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1538 | // unary instructions |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1539 | let CodeSize = 2 in { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1540 | let Defs = [EFLAGS] in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1541 | def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1542 | [(set GR8:$dst, (ineg GR8:$src)), |
| 1543 | (implicit EFLAGS)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1544 | def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1545 | [(set GR16:$dst, (ineg GR16:$src)), |
| 1546 | (implicit EFLAGS)]>, OpSize; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1547 | def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1548 | [(set GR32:$dst, (ineg GR32:$src)), |
| 1549 | (implicit EFLAGS)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1550 | let isTwoAddress = 0 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1551 | def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1552 | [(store (ineg (loadi8 addr:$dst)), addr:$dst), |
| 1553 | (implicit EFLAGS)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1554 | def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1555 | [(store (ineg (loadi16 addr:$dst)), addr:$dst), |
| 1556 | (implicit EFLAGS)]>, OpSize; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1557 | def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1558 | [(store (ineg (loadi32 addr:$dst)), addr:$dst), |
| 1559 | (implicit EFLAGS)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1560 | } |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1561 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1562 | |
Evan Cheng | aaf414c | 2009-01-21 02:09:05 +0000 | [diff] [blame] | 1563 | // Match xor -1 to not. Favors these over a move imm + xor to save code size. |
| 1564 | let AddedComplexity = 15 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1565 | def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1566 | [(set GR8:$dst, (not GR8:$src))]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1567 | def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1568 | [(set GR16:$dst, (not GR16:$src))]>, OpSize; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1569 | def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1570 | [(set GR32:$dst, (not GR32:$src))]>; |
Evan Cheng | aaf414c | 2009-01-21 02:09:05 +0000 | [diff] [blame] | 1571 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1572 | let isTwoAddress = 0 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1573 | def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1574 | [(store (not (loadi8 addr:$dst)), addr:$dst)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1575 | def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1576 | [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1577 | def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1578 | [(store (not (loadi32 addr:$dst)), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1579 | } |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1580 | } // CodeSize |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1581 | |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 1582 | // TODO: inc/dec is slow for P4, but fast for Pentium-M. |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1583 | let Defs = [EFLAGS] in { |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1584 | let CodeSize = 2 in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1585 | def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1586 | [(set GR8:$dst, (add GR8:$src, 1)), |
| 1587 | (implicit EFLAGS)]>; |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1588 | let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1589 | def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1590 | [(set GR16:$dst, (add GR16:$src, 1)), |
| 1591 | (implicit EFLAGS)]>, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1592 | OpSize, Requires<[In32BitMode]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1593 | def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1594 | [(set GR32:$dst, (add GR32:$src, 1)), |
| 1595 | (implicit EFLAGS)]>, Requires<[In32BitMode]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1596 | } |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1597 | let isTwoAddress = 0, CodeSize = 2 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1598 | def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1599 | [(store (add (loadi8 addr:$dst), 1), addr:$dst), |
| 1600 | (implicit EFLAGS)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1601 | def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1602 | [(store (add (loadi16 addr:$dst), 1), addr:$dst), |
| 1603 | (implicit EFLAGS)]>, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1604 | OpSize, Requires<[In32BitMode]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1605 | def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1606 | [(store (add (loadi32 addr:$dst), 1), addr:$dst), |
| 1607 | (implicit EFLAGS)]>, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1608 | Requires<[In32BitMode]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1609 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1610 | |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1611 | let CodeSize = 2 in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1612 | def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1613 | [(set GR8:$dst, (add GR8:$src, -1)), |
| 1614 | (implicit EFLAGS)]>; |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1615 | let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1616 | def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1617 | [(set GR16:$dst, (add GR16:$src, -1)), |
| 1618 | (implicit EFLAGS)]>, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1619 | OpSize, Requires<[In32BitMode]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1620 | def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1621 | [(set GR32:$dst, (add GR32:$src, -1)), |
| 1622 | (implicit EFLAGS)]>, Requires<[In32BitMode]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1623 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1624 | |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1625 | let isTwoAddress = 0, CodeSize = 2 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1626 | def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1627 | [(store (add (loadi8 addr:$dst), -1), addr:$dst), |
| 1628 | (implicit EFLAGS)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1629 | def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1630 | [(store (add (loadi16 addr:$dst), -1), addr:$dst), |
| 1631 | (implicit EFLAGS)]>, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1632 | OpSize, Requires<[In32BitMode]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1633 | def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1634 | [(store (add (loadi32 addr:$dst), -1), addr:$dst), |
| 1635 | (implicit EFLAGS)]>, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1636 | Requires<[In32BitMode]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1637 | } |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1638 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1639 | |
| 1640 | // Logical operators... |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1641 | let Defs = [EFLAGS] in { |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1642 | let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1643 | def AND8rr : I<0x20, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1644 | (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1645 | "and{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1646 | [(set GR8:$dst, (and GR8:$src1, GR8:$src2)), |
| 1647 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1648 | def AND16rr : I<0x21, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1649 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1650 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1651 | [(set GR16:$dst, (and GR16:$src1, GR16:$src2)), |
| 1652 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1653 | def AND32rr : I<0x21, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1654 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1655 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1656 | [(set GR32:$dst, (and GR32:$src1, GR32:$src2)), |
| 1657 | (implicit EFLAGS)]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1658 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1659 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1660 | def AND8rm : I<0x22, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1661 | (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1662 | "and{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 1663 | [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1664 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1665 | def AND16rm : I<0x23, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1666 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1667 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 1668 | [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1669 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1670 | def AND32rm : I<0x23, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1671 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1672 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 1673 | [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1674 | (implicit EFLAGS)]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1675 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1676 | def AND8ri : Ii8<0x80, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1677 | (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1678 | "and{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1679 | [(set GR8:$dst, (and GR8:$src1, imm:$src2)), |
| 1680 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1681 | def AND16ri : Ii16<0x81, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1682 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1683 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1684 | [(set GR16:$dst, (and GR16:$src1, imm:$src2)), |
| 1685 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1686 | def AND32ri : Ii32<0x81, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1687 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1688 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1689 | [(set GR32:$dst, (and GR32:$src1, imm:$src2)), |
| 1690 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1691 | def AND16ri8 : Ii8<0x83, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1692 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1693 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1694 | [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)), |
| 1695 | (implicit EFLAGS)]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1696 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1697 | def AND32ri8 : Ii8<0x83, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1698 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1699 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1700 | [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)), |
| 1701 | (implicit EFLAGS)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1702 | |
| 1703 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1704 | def AND8mr : I<0x20, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1705 | (outs), (ins i8mem :$dst, GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1706 | "and{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1707 | [(store (and (load addr:$dst), GR8:$src), addr:$dst), |
| 1708 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1709 | def AND16mr : I<0x21, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1710 | (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1711 | "and{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1712 | [(store (and (load addr:$dst), GR16:$src), addr:$dst), |
| 1713 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1714 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1715 | def AND32mr : I<0x21, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1716 | (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1717 | "and{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1718 | [(store (and (load addr:$dst), GR32:$src), addr:$dst), |
| 1719 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1720 | def AND8mi : Ii8<0x80, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1721 | (outs), (ins i8mem :$dst, i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1722 | "and{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1723 | [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst), |
| 1724 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1725 | def AND16mi : Ii16<0x81, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1726 | (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1727 | "and{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1728 | [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst), |
| 1729 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1730 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1731 | def AND32mi : Ii32<0x81, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1732 | (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1733 | "and{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1734 | [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst), |
| 1735 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1736 | def AND16mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1737 | (outs), (ins i16mem:$dst, i16i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1738 | "and{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1739 | [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst), |
| 1740 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1741 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1742 | def AND32mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1743 | (outs), (ins i32mem:$dst, i32i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1744 | "and{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1745 | [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst), |
| 1746 | (implicit EFLAGS)]>; |
Sean Callanan | a09caa5 | 2009-09-02 00:55:49 +0000 | [diff] [blame] | 1747 | |
| 1748 | def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src), |
| 1749 | "and{b}\t{$src, %al|%al, $src}", []>; |
| 1750 | def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src), |
| 1751 | "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 1752 | def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src), |
| 1753 | "and{l}\t{$src, %eax|%eax, $src}", []>; |
| 1754 | |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1755 | } |
| 1756 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1757 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1758 | let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1759 | def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1760 | "or{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1761 | [(set GR8:$dst, (or GR8:$src1, GR8:$src2)), |
| 1762 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1763 | def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1764 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1765 | [(set GR16:$dst, (or GR16:$src1, GR16:$src2)), |
| 1766 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1767 | def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1768 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1769 | [(set GR32:$dst, (or GR32:$src1, GR32:$src2)), |
| 1770 | (implicit EFLAGS)]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1771 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1772 | def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1773 | "or{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1774 | [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))), |
| 1775 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1776 | def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1777 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1778 | [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))), |
| 1779 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1780 | def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1781 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1782 | [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))), |
| 1783 | (implicit EFLAGS)]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1784 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1785 | def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1786 | "or{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1787 | [(set GR8:$dst, (or GR8:$src1, imm:$src2)), |
| 1788 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1789 | def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1790 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1791 | [(set GR16:$dst, (or GR16:$src1, imm:$src2)), |
| 1792 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1793 | def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1794 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1795 | [(set GR32:$dst, (or GR32:$src1, imm:$src2)), |
| 1796 | (implicit EFLAGS)]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1797 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1798 | def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1799 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1800 | [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)), |
| 1801 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1802 | def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1803 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1804 | [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)), |
| 1805 | (implicit EFLAGS)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1806 | let isTwoAddress = 0 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1807 | def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1808 | "or{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1809 | [(store (or (load addr:$dst), GR8:$src), addr:$dst), |
| 1810 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1811 | def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1812 | "or{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1813 | [(store (or (load addr:$dst), GR16:$src), addr:$dst), |
| 1814 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1815 | def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1816 | "or{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1817 | [(store (or (load addr:$dst), GR32:$src), addr:$dst), |
| 1818 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1819 | def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1820 | "or{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1821 | [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst), |
| 1822 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1823 | def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1824 | "or{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1825 | [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst), |
| 1826 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1827 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1828 | def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1829 | "or{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1830 | [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst), |
| 1831 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1832 | def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1833 | "or{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1834 | [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst), |
| 1835 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1836 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1837 | def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1838 | "or{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1839 | [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst), |
| 1840 | (implicit EFLAGS)]>; |
Sean Callanan | d00025a | 2009-09-11 19:01:56 +0000 | [diff] [blame] | 1841 | |
| 1842 | def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src), |
| 1843 | "or{b}\t{$src, %al|%al, $src}", []>; |
| 1844 | def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src), |
| 1845 | "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 1846 | def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src), |
| 1847 | "or{l}\t{$src, %eax|%eax, $src}", []>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1848 | } // isTwoAddress = 0 |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1849 | |
| 1850 | |
Evan Cheng | 359e937 | 2008-06-18 08:13:07 +0000 | [diff] [blame] | 1851 | let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1852 | def XOR8rr : I<0x30, MRMDestReg, |
| 1853 | (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2), |
| 1854 | "xor{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1855 | [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)), |
| 1856 | (implicit EFLAGS)]>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1857 | def XOR16rr : I<0x31, MRMDestReg, |
| 1858 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
| 1859 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1860 | [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)), |
| 1861 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1862 | def XOR32rr : I<0x31, MRMDestReg, |
| 1863 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
| 1864 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1865 | [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)), |
| 1866 | (implicit EFLAGS)]>; |
Evan Cheng | 359e937 | 2008-06-18 08:13:07 +0000 | [diff] [blame] | 1867 | } // isCommutable = 1 |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1868 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1869 | def XOR8rm : I<0x32, MRMSrcMem , |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1870 | (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1871 | "xor{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1872 | [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))), |
| 1873 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1874 | def XOR16rm : I<0x33, MRMSrcMem , |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1875 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1876 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1877 | [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))), |
| 1878 | (implicit EFLAGS)]>, |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1879 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1880 | def XOR32rm : I<0x33, MRMSrcMem , |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1881 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1882 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1883 | [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))), |
| 1884 | (implicit EFLAGS)]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1885 | |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 1886 | def XOR8ri : Ii8<0x80, MRM6r, |
| 1887 | (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
| 1888 | "xor{b}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1889 | [(set GR8:$dst, (xor GR8:$src1, imm:$src2)), |
| 1890 | (implicit EFLAGS)]>; |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 1891 | def XOR16ri : Ii16<0x81, MRM6r, |
| 1892 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
| 1893 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1894 | [(set GR16:$dst, (xor GR16:$src1, imm:$src2)), |
| 1895 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 1896 | def XOR32ri : Ii32<0x81, MRM6r, |
| 1897 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
| 1898 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1899 | [(set GR32:$dst, (xor GR32:$src1, imm:$src2)), |
| 1900 | (implicit EFLAGS)]>; |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 1901 | def XOR16ri8 : Ii8<0x83, MRM6r, |
| 1902 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
| 1903 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1904 | [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)), |
| 1905 | (implicit EFLAGS)]>, |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 1906 | OpSize; |
| 1907 | def XOR32ri8 : Ii8<0x83, MRM6r, |
| 1908 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
| 1909 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1910 | [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)), |
| 1911 | (implicit EFLAGS)]>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1912 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1913 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1914 | def XOR8mr : I<0x30, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1915 | (outs), (ins i8mem :$dst, GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1916 | "xor{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1917 | [(store (xor (load addr:$dst), GR8:$src), addr:$dst), |
| 1918 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1919 | def XOR16mr : I<0x31, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1920 | (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1921 | "xor{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1922 | [(store (xor (load addr:$dst), GR16:$src), addr:$dst), |
| 1923 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1924 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1925 | def XOR32mr : I<0x31, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1926 | (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1927 | "xor{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1928 | [(store (xor (load addr:$dst), GR32:$src), addr:$dst), |
| 1929 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1930 | def XOR8mi : Ii8<0x80, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1931 | (outs), (ins i8mem :$dst, i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1932 | "xor{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1933 | [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst), |
| 1934 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1935 | def XOR16mi : Ii16<0x81, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1936 | (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1937 | "xor{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1938 | [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst), |
| 1939 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1940 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1941 | def XOR32mi : Ii32<0x81, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1942 | (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1943 | "xor{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1944 | [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst), |
| 1945 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1946 | def XOR16mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1947 | (outs), (ins i16mem:$dst, i16i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1948 | "xor{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1949 | [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst), |
| 1950 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1951 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1952 | def XOR32mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1953 | (outs), (ins i32mem:$dst, i32i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1954 | "xor{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1955 | [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst), |
| 1956 | (implicit EFLAGS)]>; |
Sean Callanan | 7893ec6 | 2009-09-10 19:52:26 +0000 | [diff] [blame] | 1957 | |
| 1958 | def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src), |
| 1959 | "xor{b}\t{$src, %al|%al, $src}", []>; |
| 1960 | def XOR16i16 : Ii16 <0x35, RawFrm, (outs), (ins i16imm:$src), |
| 1961 | "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 1962 | def XOR32i32 : Ii32 <0x35, RawFrm, (outs), (ins i32imm:$src), |
| 1963 | "xor{l}\t{$src, %eax|%eax, $src}", []>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1964 | } // isTwoAddress = 0 |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1965 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1966 | |
| 1967 | // Shift instructions |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1968 | let Defs = [EFLAGS] in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1969 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1970 | def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1971 | "shl{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1972 | [(set GR8:$dst, (shl GR8:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1973 | def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1974 | "shl{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1975 | [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1976 | def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1977 | "shl{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1978 | [(set GR32:$dst, (shl GR32:$src, CL))]>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1979 | } // Uses = [CL] |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1980 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1981 | def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1982 | "shl{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1983 | [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1984 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1985 | def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1986 | "shl{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1987 | [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1988 | def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1989 | "shl{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1990 | [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>; |
Sean Callanan | 13cf8e9 | 2009-09-16 02:28:43 +0000 | [diff] [blame] | 1991 | |
| 1992 | // NOTE: We don't include patterns for shifts of a register by one, because |
| 1993 | // 'add reg,reg' is cheaper. |
| 1994 | |
| 1995 | def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1), |
| 1996 | "shl{b}\t$dst", []>; |
| 1997 | def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1), |
| 1998 | "shl{w}\t$dst", []>, OpSize; |
| 1999 | def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1), |
| 2000 | "shl{l}\t$dst", []>; |
| 2001 | |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 2002 | } // isConvertibleToThreeAddress = 1 |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2003 | |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 2004 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2005 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2006 | def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2007 | "shl{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2008 | [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2009 | def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2010 | "shl{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2011 | [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2012 | def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2013 | "shl{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2014 | [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 2015 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2016 | def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2017 | "shl{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 2018 | [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2019 | def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2020 | "shl{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 2021 | [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 2022 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2023 | def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2024 | "shl{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 2025 | [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2026 | |
| 2027 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2028 | def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2029 | "shl{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2030 | [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2031 | def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2032 | "shl{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2033 | [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 2034 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2035 | def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2036 | "shl{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2037 | [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 2038 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2039 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2040 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2041 | def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2042 | "shr{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2043 | [(set GR8:$dst, (srl GR8:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2044 | def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2045 | "shr{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2046 | [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2047 | def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2048 | "shr{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2049 | [(set GR32:$dst, (srl GR32:$src, CL))]>; |
| 2050 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2051 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2052 | def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2053 | "shr{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2054 | [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2055 | def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2056 | "shr{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2057 | [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2058 | def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2059 | "shr{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2060 | [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 2061 | |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2062 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2063 | def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2064 | "shr{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2065 | [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2066 | def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2067 | "shr{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2068 | [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2069 | def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2070 | "shr{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2071 | [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>; |
| 2072 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2073 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2074 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2075 | def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2076 | "shr{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2077 | [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2078 | def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2079 | "shr{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 2080 | [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2081 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2082 | def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2083 | "shr{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2084 | [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 2085 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2086 | def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2087 | "shr{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 2088 | [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2089 | def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2090 | "shr{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 2091 | [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 2092 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2093 | def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2094 | "shr{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 2095 | [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2096 | |
| 2097 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2098 | def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2099 | "shr{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2100 | [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2101 | def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2102 | "shr{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2103 | [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2104 | def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2105 | "shr{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2106 | [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2107 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2108 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2109 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2110 | def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2111 | "sar{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2112 | [(set GR8:$dst, (sra GR8:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2113 | def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2114 | "sar{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2115 | [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2116 | def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2117 | "sar{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2118 | [(set GR32:$dst, (sra GR32:$src, CL))]>; |
| 2119 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2120 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2121 | def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2122 | "sar{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2123 | [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2124 | def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2125 | "sar{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2126 | [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>, |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 2127 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2128 | def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2129 | "sar{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2130 | [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2131 | |
| 2132 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2133 | def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2134 | "sar{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2135 | [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2136 | def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2137 | "sar{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2138 | [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2139 | def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2140 | "sar{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2141 | [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>; |
| 2142 | |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 2143 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2144 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2145 | def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2146 | "sar{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2147 | [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2148 | def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2149 | "sar{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2150 | [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2151 | def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2152 | "sar{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2153 | [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 2154 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2155 | def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2156 | "sar{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 2157 | [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2158 | def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2159 | "sar{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 2160 | [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 2161 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2162 | def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2163 | "sar{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 2164 | [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2165 | |
| 2166 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2167 | def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2168 | "sar{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2169 | [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2170 | def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2171 | "sar{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2172 | [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 2173 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2174 | def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2175 | "sar{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2176 | [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 2177 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2178 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 2179 | // Rotate instructions |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 2180 | |
| 2181 | def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src), |
| 2182 | "rcl{b}\t{1, $dst|$dst, 1}", []>; |
| 2183 | def RCL8m1 : I<0xD0, MRM2m, (outs i8mem:$dst), (ins i8mem:$src), |
| 2184 | "rcl{b}\t{1, $dst|$dst, 1}", []>; |
| 2185 | let Uses = [CL] in { |
| 2186 | def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src), |
| 2187 | "rcl{b}\t{%cl, $dst|$dst, CL}", []>; |
| 2188 | def RCL8mCL : I<0xD2, MRM2m, (outs i8mem:$dst), (ins i8mem:$src), |
| 2189 | "rcl{b}\t{%cl, $dst|$dst, CL}", []>; |
| 2190 | } |
| 2191 | def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt), |
| 2192 | "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 2193 | def RCL8mi : Ii8<0xC0, MRM2m, (outs i8mem:$dst), (ins i8mem:$src, i8imm:$cnt), |
| 2194 | "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 2195 | |
| 2196 | def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src), |
| 2197 | "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize; |
| 2198 | def RCL16m1 : I<0xD1, MRM2m, (outs i16mem:$dst), (ins i16mem:$src), |
| 2199 | "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize; |
| 2200 | let Uses = [CL] in { |
| 2201 | def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src), |
| 2202 | "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize; |
| 2203 | def RCL16mCL : I<0xD3, MRM2m, (outs i16mem:$dst), (ins i16mem:$src), |
| 2204 | "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize; |
| 2205 | } |
| 2206 | def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt), |
| 2207 | "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize; |
| 2208 | def RCL16mi : Ii8<0xC1, MRM2m, (outs i16mem:$dst), (ins i16mem:$src, i8imm:$cnt), |
| 2209 | "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize; |
| 2210 | |
| 2211 | def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src), |
| 2212 | "rcl{l}\t{1, $dst|$dst, 1}", []>; |
| 2213 | def RCL32m1 : I<0xD1, MRM2m, (outs i32mem:$dst), (ins i32mem:$src), |
| 2214 | "rcl{l}\t{1, $dst|$dst, 1}", []>; |
| 2215 | let Uses = [CL] in { |
| 2216 | def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src), |
| 2217 | "rcl{l}\t{%cl, $dst|$dst, CL}", []>; |
| 2218 | def RCL32mCL : I<0xD3, MRM2m, (outs i32mem:$dst), (ins i32mem:$src), |
| 2219 | "rcl{l}\t{%cl, $dst|$dst, CL}", []>; |
| 2220 | } |
| 2221 | def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt), |
| 2222 | "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 2223 | def RCL32mi : Ii8<0xC1, MRM2m, (outs i32mem:$dst), (ins i32mem:$src, i8imm:$cnt), |
| 2224 | "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 2225 | |
| 2226 | def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src), |
| 2227 | "rcr{b}\t{1, $dst|$dst, 1}", []>; |
| 2228 | def RCR8m1 : I<0xD0, MRM3m, (outs i8mem:$dst), (ins i8mem:$src), |
| 2229 | "rcr{b}\t{1, $dst|$dst, 1}", []>; |
| 2230 | let Uses = [CL] in { |
| 2231 | def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src), |
| 2232 | "rcr{b}\t{%cl, $dst|$dst, CL}", []>; |
| 2233 | def RCR8mCL : I<0xD2, MRM3m, (outs i8mem:$dst), (ins i8mem:$src), |
| 2234 | "rcr{b}\t{%cl, $dst|$dst, CL}", []>; |
| 2235 | } |
| 2236 | def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt), |
| 2237 | "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 2238 | def RCR8mi : Ii8<0xC0, MRM3m, (outs i8mem:$dst), (ins i8mem:$src, i8imm:$cnt), |
| 2239 | "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 2240 | |
| 2241 | def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src), |
| 2242 | "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize; |
| 2243 | def RCR16m1 : I<0xD1, MRM3m, (outs i16mem:$dst), (ins i16mem:$src), |
| 2244 | "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize; |
| 2245 | let Uses = [CL] in { |
| 2246 | def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src), |
| 2247 | "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize; |
| 2248 | def RCR16mCL : I<0xD3, MRM3m, (outs i16mem:$dst), (ins i16mem:$src), |
| 2249 | "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize; |
| 2250 | } |
| 2251 | def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt), |
| 2252 | "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize; |
| 2253 | def RCR16mi : Ii8<0xC1, MRM3m, (outs i16mem:$dst), (ins i16mem:$src, i8imm:$cnt), |
| 2254 | "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize; |
| 2255 | |
| 2256 | def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src), |
| 2257 | "rcr{l}\t{1, $dst|$dst, 1}", []>; |
| 2258 | def RCR32m1 : I<0xD1, MRM3m, (outs i32mem:$dst), (ins i32mem:$src), |
| 2259 | "rcr{l}\t{1, $dst|$dst, 1}", []>; |
| 2260 | let Uses = [CL] in { |
| 2261 | def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src), |
| 2262 | "rcr{l}\t{%cl, $dst|$dst, CL}", []>; |
| 2263 | def RCR32mCL : I<0xD3, MRM3m, (outs i32mem:$dst), (ins i32mem:$src), |
| 2264 | "rcr{l}\t{%cl, $dst|$dst, CL}", []>; |
| 2265 | } |
| 2266 | def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt), |
| 2267 | "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 2268 | def RCR32mi : Ii8<0xC1, MRM3m, (outs i32mem:$dst), (ins i32mem:$src, i8imm:$cnt), |
| 2269 | "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 2270 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 2271 | // FIXME: provide shorter instructions when imm8 == 1 |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2272 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2273 | def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2274 | "rol{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2275 | [(set GR8:$dst, (rotl GR8:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2276 | def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2277 | "rol{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2278 | [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2279 | def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2280 | "rol{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2281 | [(set GR32:$dst, (rotl GR32:$src, CL))]>; |
| 2282 | } |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 2283 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2284 | def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2285 | "rol{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2286 | [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2287 | def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2288 | "rol{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2289 | [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2290 | def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2291 | "rol{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2292 | [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 2293 | |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2294 | // Rotate by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2295 | def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2296 | "rol{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2297 | [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2298 | def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2299 | "rol{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2300 | [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2301 | def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2302 | "rol{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2303 | [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>; |
| 2304 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 2305 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2306 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2307 | def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2308 | "rol{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2309 | [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2310 | def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2311 | "rol{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2312 | [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2313 | def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2314 | "rol{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2315 | [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 2316 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2317 | def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2318 | "rol{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 2319 | [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2320 | def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2321 | "rol{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 2322 | [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 2323 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2324 | def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2325 | "rol{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 2326 | [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2327 | |
| 2328 | // Rotate by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2329 | def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2330 | "rol{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2331 | [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2332 | def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2333 | "rol{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2334 | [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 2335 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2336 | def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2337 | "rol{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2338 | [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 2339 | } |
| 2340 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2341 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2342 | def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2343 | "ror{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2344 | [(set GR8:$dst, (rotr GR8:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2345 | def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2346 | "ror{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2347 | [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2348 | def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2349 | "ror{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2350 | [(set GR32:$dst, (rotr GR32:$src, CL))]>; |
| 2351 | } |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 2352 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2353 | def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2354 | "ror{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2355 | [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2356 | def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2357 | "ror{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2358 | [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2359 | def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2360 | "ror{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2361 | [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2362 | |
| 2363 | // Rotate by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2364 | def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2365 | "ror{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2366 | [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2367 | def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2368 | "ror{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2369 | [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2370 | def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2371 | "ror{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2372 | [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>; |
| 2373 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 2374 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2375 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2376 | def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2377 | "ror{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2378 | [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2379 | def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2380 | "ror{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2381 | [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2382 | def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2383 | "ror{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2384 | [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 2385 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2386 | def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2387 | "ror{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 2388 | [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2389 | def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2390 | "ror{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 2391 | [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 2392 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2393 | def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2394 | "ror{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 2395 | [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2396 | |
| 2397 | // Rotate by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2398 | def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2399 | "ror{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2400 | [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2401 | def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2402 | "ror{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2403 | [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 2404 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2405 | def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2406 | "ror{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 2407 | [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 2408 | } |
| 2409 | |
| 2410 | |
| 2411 | |
| 2412 | // Double shift instructions (generalizations of rotate) |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2413 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2414 | def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2415 | "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2416 | [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2417 | def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2418 | "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2419 | [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2420 | def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2421 | "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2422 | [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2423 | TB, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2424 | def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2425 | "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2426 | [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2427 | TB, OpSize; |
| 2428 | } |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 2429 | |
| 2430 | let isCommutable = 1 in { // These instructions commute to each other. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2431 | def SHLD32rri8 : Ii8<0xA4, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2432 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2433 | "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2434 | [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2435 | (i8 imm:$src3)))]>, |
| 2436 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2437 | def SHRD32rri8 : Ii8<0xAC, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2438 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2439 | "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2440 | [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2441 | (i8 imm:$src3)))]>, |
| 2442 | TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 2443 | def SHLD16rri8 : Ii8<0xA4, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2444 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2445 | "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2446 | [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2447 | (i8 imm:$src3)))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 2448 | TB, OpSize; |
| 2449 | def SHRD16rri8 : Ii8<0xAC, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2450 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2451 | "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2452 | [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2453 | (i8 imm:$src3)))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 2454 | TB, OpSize; |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 2455 | } |
Chris Lattner | 0e967d4 | 2004-08-01 08:13:11 +0000 | [diff] [blame] | 2456 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2457 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2458 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2459 | def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2460 | "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2461 | [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2462 | addr:$dst)]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2463 | def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2464 | "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2465 | [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2466 | addr:$dst)]>, TB; |
| 2467 | } |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2468 | def SHLD32mri8 : Ii8<0xA4, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2469 | (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2470 | "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2471 | [(store (X86shld (loadi32 addr:$dst), GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2472 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 2473 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2474 | def SHRD32mri8 : Ii8<0xAC, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2475 | (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2476 | "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2477 | [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2478 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 2479 | TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 2480 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2481 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2482 | def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2483 | "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2484 | [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2485 | addr:$dst)]>, TB, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2486 | def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 2487 | "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2488 | [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2489 | addr:$dst)]>, TB, OpSize; |
| 2490 | } |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 2491 | def SHLD16mri8 : Ii8<0xA4, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2492 | (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2493 | "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2494 | [(store (X86shld (loadi16 addr:$dst), GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2495 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 2496 | TB, OpSize; |
| 2497 | def SHRD16mri8 : Ii8<0xAC, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2498 | (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2499 | "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2500 | [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 2501 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 2502 | TB, OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2503 | } |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2504 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2505 | |
| 2506 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2507 | // Arithmetic. |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2508 | let Defs = [EFLAGS] in { |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2509 | let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2510 | // Register-Register Addition |
| 2511 | def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst), |
| 2512 | (ins GR8 :$src1, GR8 :$src2), |
| 2513 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2514 | [(set GR8:$dst, (add GR8:$src1, GR8:$src2)), |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2515 | (implicit EFLAGS)]>; |
| 2516 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2517 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2518 | // Register-Register Addition |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2519 | def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst), |
| 2520 | (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2521 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2522 | [(set GR16:$dst, (add GR16:$src1, GR16:$src2)), |
| 2523 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2524 | def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), |
| 2525 | (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2526 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2527 | [(set GR32:$dst, (add GR32:$src1, GR32:$src2)), |
| 2528 | (implicit EFLAGS)]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2529 | } // end isConvertibleToThreeAddress |
| 2530 | } // end isCommutable |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2531 | |
| 2532 | // Register-Memory Addition |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2533 | def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst), |
| 2534 | (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2535 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2536 | [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))), |
| 2537 | (implicit EFLAGS)]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2538 | def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), |
| 2539 | (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2540 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2541 | [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))), |
| 2542 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2543 | def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), |
| 2544 | (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2545 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2546 | [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))), |
| 2547 | (implicit EFLAGS)]>; |
Sean Callanan | 37be590 | 2009-09-15 20:53:57 +0000 | [diff] [blame] | 2548 | |
Sean Callanan | 62c28e3 | 2009-09-15 21:43:27 +0000 | [diff] [blame] | 2549 | // Register-Register Addition - Equivalent to the normal rr forms (ADD8rr, |
| 2550 | // ADD16rr, and ADD32rr), but differently encoded. |
Sean Callanan | 37be590 | 2009-09-15 20:53:57 +0000 | [diff] [blame] | 2551 | def ADD8mrmrr: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 2552 | "add{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 2553 | def ADD16mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2), |
| 2554 | "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
| 2555 | def ADD32mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2), |
| 2556 | "add{l}\t{$src2, $dst|$dst, $src2}", []>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2557 | |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2558 | // Register-Integer Addition |
| 2559 | def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
| 2560 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2561 | [(set GR8:$dst, (add GR8:$src1, imm:$src2)), |
| 2562 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2563 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2564 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2565 | // Register-Integer Addition |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2566 | def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst), |
| 2567 | (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2568 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2569 | [(set GR16:$dst, (add GR16:$src1, imm:$src2)), |
| 2570 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2571 | def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst), |
| 2572 | (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2573 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2574 | [(set GR32:$dst, (add GR32:$src1, imm:$src2)), |
| 2575 | (implicit EFLAGS)]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2576 | def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst), |
| 2577 | (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2578 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2579 | [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)), |
| 2580 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2581 | def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst), |
| 2582 | (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2583 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2584 | [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)), |
| 2585 | (implicit EFLAGS)]>; |
Evan Cheng | 09e3c80 | 2006-05-19 18:40:54 +0000 | [diff] [blame] | 2586 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2587 | |
| 2588 | let isTwoAddress = 0 in { |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2589 | // Memory-Register Addition |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2590 | def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2591 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2592 | [(store (add (load addr:$dst), GR8:$src2), addr:$dst), |
| 2593 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2594 | def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2595 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2596 | [(store (add (load addr:$dst), GR16:$src2), addr:$dst), |
| 2597 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2598 | def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2599 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2600 | [(store (add (load addr:$dst), GR32:$src2), addr:$dst), |
| 2601 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2602 | def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2603 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2604 | [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst), |
| 2605 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2606 | def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2607 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2608 | [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst), |
| 2609 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2610 | def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2611 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2612 | [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst), |
| 2613 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2614 | def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2615 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2616 | [(store (add (load addr:$dst), i16immSExt8:$src2), |
| 2617 | addr:$dst), |
| 2618 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2619 | def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2620 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2621 | [(store (add (load addr:$dst), i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2622 | addr:$dst), |
| 2623 | (implicit EFLAGS)]>; |
Sean Callanan | b08ae6b | 2009-08-11 21:26:06 +0000 | [diff] [blame] | 2624 | |
| 2625 | // addition to rAX |
| 2626 | def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src), |
Sean Callanan | a09caa5 | 2009-09-02 00:55:49 +0000 | [diff] [blame] | 2627 | "add{b}\t{$src, %al|%al, $src}", []>; |
Sean Callanan | b08ae6b | 2009-08-11 21:26:06 +0000 | [diff] [blame] | 2628 | def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src), |
Sean Callanan | a09caa5 | 2009-09-02 00:55:49 +0000 | [diff] [blame] | 2629 | "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
Sean Callanan | b08ae6b | 2009-08-11 21:26:06 +0000 | [diff] [blame] | 2630 | def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src), |
Sean Callanan | a09caa5 | 2009-09-02 00:55:49 +0000 | [diff] [blame] | 2631 | "add{l}\t{$src, %eax|%eax, $src}", []>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2632 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2633 | |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 2634 | let Uses = [EFLAGS] in { |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 2635 | let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2636 | def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2637 | "adc{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2638 | [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2639 | def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst), |
| 2640 | (ins GR16:$src1, GR16:$src2), |
| 2641 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2642 | [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2643 | def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), |
| 2644 | (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2645 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2646 | [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 2647 | } |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2648 | def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst), |
| 2649 | (ins GR8:$src1, i8mem:$src2), |
| 2650 | "adc{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2651 | [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2652 | def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst), |
| 2653 | (ins GR16:$src1, i16mem:$src2), |
| 2654 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2655 | [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>, |
Dale Johannesen | 94c9cd1 | 2009-05-18 21:41:59 +0000 | [diff] [blame] | 2656 | OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2657 | def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), |
| 2658 | (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2659 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2660 | [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>; |
| 2661 | def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2662 | "adc{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2663 | [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2664 | def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst), |
| 2665 | (ins GR16:$src1, i16imm:$src2), |
| 2666 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2667 | [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2668 | def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst), |
| 2669 | (ins GR16:$src1, i16i8imm:$src2), |
| 2670 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2671 | [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>, |
| 2672 | OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2673 | def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), |
| 2674 | (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2675 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2676 | [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2677 | def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), |
| 2678 | (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2679 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2680 | [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2681 | |
| 2682 | let isTwoAddress = 0 in { |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2683 | def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2684 | "adc{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2685 | [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>; |
| 2686 | def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2687 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2688 | [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>, |
| 2689 | OpSize; |
| 2690 | def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2691 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2692 | [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>; |
| 2693 | def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2694 | "adc{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2695 | [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
| 2696 | def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2697 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2698 | [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, |
| 2699 | OpSize; |
| 2700 | def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2701 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2702 | [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, |
| 2703 | OpSize; |
| 2704 | def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2705 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2706 | [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
| 2707 | def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2708 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2709 | [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Sean Callanan | d00025a | 2009-09-11 19:01:56 +0000 | [diff] [blame] | 2710 | |
| 2711 | def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src), |
| 2712 | "adc{b}\t{$src, %al|%al, $src}", []>; |
| 2713 | def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src), |
| 2714 | "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 2715 | def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src), |
| 2716 | "adc{l}\t{$src, %eax|%eax, $src}", []>; |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2717 | } |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 2718 | } // Uses = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2719 | |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2720 | // Register-Register Subtraction |
| 2721 | def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 2722 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2723 | [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)), |
| 2724 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2725 | def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2), |
| 2726 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2727 | [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)), |
| 2728 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2729 | def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), |
| 2730 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2731 | [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)), |
| 2732 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2733 | |
| 2734 | // Register-Memory Subtraction |
| 2735 | def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), |
| 2736 | (ins GR8 :$src1, i8mem :$src2), |
| 2737 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2738 | [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))), |
| 2739 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2740 | def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), |
| 2741 | (ins GR16:$src1, i16mem:$src2), |
| 2742 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2743 | [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))), |
| 2744 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2745 | def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), |
| 2746 | (ins GR32:$src1, i32mem:$src2), |
| 2747 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2748 | [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))), |
| 2749 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2750 | |
| 2751 | // Register-Integer Subtraction |
| 2752 | def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), |
| 2753 | (ins GR8:$src1, i8imm:$src2), |
| 2754 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2755 | [(set GR8:$dst, (sub GR8:$src1, imm:$src2)), |
| 2756 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2757 | def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), |
| 2758 | (ins GR16:$src1, i16imm:$src2), |
| 2759 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2760 | [(set GR16:$dst, (sub GR16:$src1, imm:$src2)), |
| 2761 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2762 | def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), |
| 2763 | (ins GR32:$src1, i32imm:$src2), |
| 2764 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2765 | [(set GR32:$dst, (sub GR32:$src1, imm:$src2)), |
| 2766 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2767 | def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), |
| 2768 | (ins GR16:$src1, i16i8imm:$src2), |
| 2769 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2770 | [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)), |
| 2771 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2772 | def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), |
| 2773 | (ins GR32:$src1, i32i8imm:$src2), |
| 2774 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2775 | [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)), |
| 2776 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2777 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2778 | let isTwoAddress = 0 in { |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2779 | // Memory-Register Subtraction |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2780 | def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2781 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2782 | [(store (sub (load addr:$dst), GR8:$src2), addr:$dst), |
| 2783 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2784 | def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2785 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2786 | [(store (sub (load addr:$dst), GR16:$src2), addr:$dst), |
| 2787 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2788 | def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2789 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2790 | [(store (sub (load addr:$dst), GR32:$src2), addr:$dst), |
| 2791 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2792 | |
| 2793 | // Memory-Integer Subtraction |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2794 | def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2795 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2796 | [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst), |
| 2797 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2798 | def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2799 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2800 | [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst), |
| 2801 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2802 | def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2803 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2804 | [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst), |
| 2805 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2806 | def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2807 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2808 | [(store (sub (load addr:$dst), i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2809 | addr:$dst), |
| 2810 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2811 | def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2812 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2813 | [(store (sub (load addr:$dst), i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2814 | addr:$dst), |
| 2815 | (implicit EFLAGS)]>; |
Sean Callanan | d00025a | 2009-09-11 19:01:56 +0000 | [diff] [blame] | 2816 | |
| 2817 | def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src), |
| 2818 | "sub{b}\t{$src, %al|%al, $src}", []>; |
| 2819 | def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src), |
| 2820 | "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 2821 | def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src), |
| 2822 | "sub{l}\t{$src, %eax|%eax, $src}", []>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2823 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2824 | |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 2825 | let Uses = [EFLAGS] in { |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2826 | def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst), |
| 2827 | (ins GR8:$src1, GR8:$src2), |
| 2828 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2829 | [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2830 | def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst), |
| 2831 | (ins GR16:$src1, GR16:$src2), |
| 2832 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2833 | [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2834 | def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), |
| 2835 | (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2836 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2837 | [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 2838 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2839 | let isTwoAddress = 0 in { |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2840 | def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), |
| 2841 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2842 | [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2843 | def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
| 2844 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2845 | [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>, |
Dale Johannesen | 94c9cd1 | 2009-05-18 21:41:59 +0000 | [diff] [blame] | 2846 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2847 | def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2848 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2849 | [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2850 | def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2851 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2852 | [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2853 | def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2), |
| 2854 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2855 | [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, |
Dale Johannesen | 94c9cd1 | 2009-05-18 21:41:59 +0000 | [diff] [blame] | 2856 | OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2857 | def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
| 2858 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2859 | [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, |
Dale Johannesen | 94c9cd1 | 2009-05-18 21:41:59 +0000 | [diff] [blame] | 2860 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2861 | def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2862 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2863 | [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2864 | def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2865 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2866 | [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Sean Callanan | d00025a | 2009-09-11 19:01:56 +0000 | [diff] [blame] | 2867 | |
| 2868 | def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src), |
| 2869 | "sbb{b}\t{$src, %al|%al, $src}", []>; |
| 2870 | def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src), |
| 2871 | "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 2872 | def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src), |
| 2873 | "sbb{l}\t{$src, %eax|%eax, $src}", []>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2874 | } |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2875 | def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2), |
| 2876 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2877 | [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2878 | def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst), |
| 2879 | (ins GR16:$src1, i16mem:$src2), |
| 2880 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2881 | [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>, |
Dale Johannesen | 94c9cd1 | 2009-05-18 21:41:59 +0000 | [diff] [blame] | 2882 | OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2883 | def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), |
| 2884 | (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2885 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2886 | [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2887 | def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
| 2888 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2889 | [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2890 | def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst), |
| 2891 | (ins GR16:$src1, i16imm:$src2), |
| 2892 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2893 | [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2894 | def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst), |
| 2895 | (ins GR16:$src1, i16i8imm:$src2), |
| 2896 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2897 | [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>, |
| 2898 | OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2899 | def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), |
| 2900 | (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2901 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2902 | [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2903 | def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), |
| 2904 | (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2905 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2906 | [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>; |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 2907 | } // Uses = [EFLAGS] |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2908 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2909 | |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2910 | let Defs = [EFLAGS] in { |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 2911 | let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2912 | // Register-Register Signed Integer Multiply |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2913 | def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2914 | "imul{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2915 | [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)), |
| 2916 | (implicit EFLAGS)]>, TB, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2917 | def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2918 | "imul{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2919 | [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)), |
| 2920 | (implicit EFLAGS)]>, TB; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 2921 | } |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2922 | |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2923 | // Register-Memory Signed Integer Multiply |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2924 | def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), |
| 2925 | (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2926 | "imul{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2927 | [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))), |
| 2928 | (implicit EFLAGS)]>, TB, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2929 | def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2930 | "imul{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2931 | [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))), |
| 2932 | (implicit EFLAGS)]>, TB; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2933 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2934 | } // end Two Address instructions |
| 2935 | |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 2936 | // Suprisingly enough, these are not two address instructions! |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2937 | let Defs = [EFLAGS] in { |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2938 | // Register-Integer Signed Integer Multiply |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2939 | def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2940 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2941 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2942 | [(set GR16:$dst, (mul GR16:$src1, imm:$src2)), |
| 2943 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2944 | def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2945 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2946 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2947 | [(set GR32:$dst, (mul GR32:$src1, imm:$src2)), |
| 2948 | (implicit EFLAGS)]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2949 | def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2950 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2951 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2952 | [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)), |
| 2953 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2954 | def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2955 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2956 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2957 | [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)), |
| 2958 | (implicit EFLAGS)]>; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 2959 | |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2960 | // Memory-Integer Signed Integer Multiply |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2961 | def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2962 | (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2963 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2964 | [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)), |
| 2965 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2966 | def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2967 | (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2968 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2969 | [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)), |
| 2970 | (implicit EFLAGS)]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2971 | def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2972 | (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2973 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2974 | [(set GR16:$dst, (mul (load addr:$src1), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2975 | i16immSExt8:$src2)), |
| 2976 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2977 | def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2978 | (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2979 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2980 | [(set GR32:$dst, (mul (load addr:$src1), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2981 | i32immSExt8:$src2)), |
| 2982 | (implicit EFLAGS)]>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2983 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2984 | |
| 2985 | //===----------------------------------------------------------------------===// |
| 2986 | // Test instructions are just like AND, except they don't generate a result. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2987 | // |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 2988 | let Defs = [EFLAGS] in { |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2989 | let isCommutable = 1 in { // TEST X, Y --> TEST Y, X |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2990 | def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2991 | "test{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 2992 | [(X86cmp (and_su GR8:$src1, GR8:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2993 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2994 | def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2995 | "test{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 2996 | [(X86cmp (and_su GR16:$src1, GR16:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2997 | (implicit EFLAGS)]>, |
| 2998 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2999 | def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3000 | "test{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 3001 | [(X86cmp (and_su GR32:$src1, GR32:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3002 | (implicit EFLAGS)]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 3003 | } |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 3004 | |
Sean Callanan | 4a93b71 | 2009-09-01 18:14:18 +0000 | [diff] [blame] | 3005 | def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src), |
| 3006 | "test{b}\t{$src, %al|%al, $src}", []>; |
| 3007 | def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src), |
| 3008 | "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 3009 | def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src), |
| 3010 | "test{l}\t{$src, %eax|%eax, $src}", []>; |
| 3011 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3012 | def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3013 | "test{b}\t{$src2, $src1|$src1, $src2}", |
| 3014 | [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0), |
| 3015 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3016 | def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3017 | "test{w}\t{$src2, $src1|$src1, $src2}", |
| 3018 | [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0), |
| 3019 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3020 | def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3021 | "test{l}\t{$src2, $src1|$src1, $src2}", |
| 3022 | [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0), |
| 3023 | (implicit EFLAGS)]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 3024 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3025 | def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3026 | (outs), (ins GR8:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3027 | "test{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 3028 | [(X86cmp (and_su GR8:$src1, imm:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3029 | (implicit EFLAGS)]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3030 | def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3031 | (outs), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3032 | "test{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 3033 | [(X86cmp (and_su GR16:$src1, imm:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3034 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3035 | def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3036 | (outs), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3037 | "test{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 3038 | [(X86cmp (and_su GR32:$src1, imm:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3039 | (implicit EFLAGS)]>; |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 3040 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3041 | def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3042 | (outs), (ins i8mem:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3043 | "test{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3044 | [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0), |
| 3045 | (implicit EFLAGS)]>; |
| 3046 | def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3047 | (outs), (ins i16mem:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3048 | "test{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3049 | [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0), |
| 3050 | (implicit EFLAGS)]>, OpSize; |
| 3051 | def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3052 | (outs), (ins i32mem:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3053 | "test{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3054 | [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 3055 | (implicit EFLAGS)]>; |
| 3056 | } // Defs = [EFLAGS] |
| 3057 | |
| 3058 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 3059 | // Condition code ops, incl. set if equal/not equal/... |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 3060 | let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 3061 | def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 3062 | let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 3063 | def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 3064 | |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 3065 | let Uses = [EFLAGS] in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3066 | def SETEr : I<0x94, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3067 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3068 | "sete\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3069 | [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3070 | TB; // GR8 = == |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3071 | def SETEm : I<0x94, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3072 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3073 | "sete\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3074 | [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3075 | TB; // [mem8] = == |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 3076 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3077 | def SETNEr : I<0x95, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3078 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3079 | "setne\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3080 | [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3081 | TB; // GR8 = != |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3082 | def SETNEm : I<0x95, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3083 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3084 | "setne\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3085 | [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3086 | TB; // [mem8] = != |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 3087 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3088 | def SETLr : I<0x9C, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3089 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3090 | "setl\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3091 | [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3092 | TB; // GR8 = < signed |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3093 | def SETLm : I<0x9C, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3094 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3095 | "setl\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3096 | [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3097 | TB; // [mem8] = < signed |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 3098 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3099 | def SETGEr : I<0x9D, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3100 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3101 | "setge\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3102 | [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3103 | TB; // GR8 = >= signed |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3104 | def SETGEm : I<0x9D, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3105 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3106 | "setge\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3107 | [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3108 | TB; // [mem8] = >= signed |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 3109 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3110 | def SETLEr : I<0x9E, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3111 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3112 | "setle\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3113 | [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3114 | TB; // GR8 = <= signed |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3115 | def SETLEm : I<0x9E, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3116 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3117 | "setle\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3118 | [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3119 | TB; // [mem8] = <= signed |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 3120 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3121 | def SETGr : I<0x9F, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3122 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3123 | "setg\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3124 | [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3125 | TB; // GR8 = > signed |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3126 | def SETGm : I<0x9F, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3127 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3128 | "setg\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3129 | [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3130 | TB; // [mem8] = > signed |
| 3131 | |
| 3132 | def SETBr : I<0x92, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3133 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3134 | "setb\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3135 | [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3136 | TB; // GR8 = < unsign |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3137 | def SETBm : I<0x92, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3138 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3139 | "setb\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3140 | [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3141 | TB; // [mem8] = < unsign |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 3142 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3143 | def SETAEr : I<0x93, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3144 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3145 | "setae\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3146 | [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3147 | TB; // GR8 = >= unsign |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3148 | def SETAEm : I<0x93, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3149 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3150 | "setae\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3151 | [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3152 | TB; // [mem8] = >= unsign |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 3153 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3154 | def SETBEr : I<0x96, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3155 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3156 | "setbe\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3157 | [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3158 | TB; // GR8 = <= unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3159 | def SETBEm : I<0x96, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3160 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3161 | "setbe\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3162 | [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3163 | TB; // [mem8] = <= unsign |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 3164 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3165 | def SETAr : I<0x97, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3166 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3167 | "seta\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3168 | [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3169 | TB; // GR8 = > signed |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3170 | def SETAm : I<0x97, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3171 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3172 | "seta\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3173 | [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 3174 | TB; // [mem8] = > signed |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 3175 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3176 | def SETSr : I<0x98, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3177 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3178 | "sets\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3179 | [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3180 | TB; // GR8 = <sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3181 | def SETSm : I<0x98, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3182 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3183 | "sets\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3184 | [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 3185 | TB; // [mem8] = <sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3186 | def SETNSr : I<0x99, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3187 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3188 | "setns\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3189 | [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3190 | TB; // GR8 = !<sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3191 | def SETNSm : I<0x99, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3192 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3193 | "setns\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3194 | [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 3195 | TB; // [mem8] = !<sign bit> |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 3196 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3197 | def SETPr : I<0x9A, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3198 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3199 | "setp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3200 | [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3201 | TB; // GR8 = parity |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3202 | def SETPm : I<0x9A, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3203 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3204 | "setp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3205 | [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 3206 | TB; // [mem8] = parity |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 3207 | def SETNPr : I<0x9B, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3208 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3209 | "setnp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3210 | [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3211 | TB; // GR8 = not parity |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 3212 | def SETNPm : I<0x9B, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3213 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3214 | "setnp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3215 | [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 3216 | TB; // [mem8] = not parity |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 3217 | |
| 3218 | def SETOr : I<0x90, MRM0r, |
| 3219 | (outs GR8 :$dst), (ins), |
| 3220 | "seto\t$dst", |
| 3221 | [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>, |
| 3222 | TB; // GR8 = overflow |
| 3223 | def SETOm : I<0x90, MRM0m, |
| 3224 | (outs), (ins i8mem:$dst), |
| 3225 | "seto\t$dst", |
| 3226 | [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>, |
| 3227 | TB; // [mem8] = overflow |
| 3228 | def SETNOr : I<0x91, MRM0r, |
| 3229 | (outs GR8 :$dst), (ins), |
| 3230 | "setno\t$dst", |
| 3231 | [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>, |
| 3232 | TB; // GR8 = not overflow |
| 3233 | def SETNOm : I<0x91, MRM0m, |
| 3234 | (outs), (ins i8mem:$dst), |
| 3235 | "setno\t$dst", |
| 3236 | [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>, |
| 3237 | TB; // [mem8] = not overflow |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 3238 | } // Uses = [EFLAGS] |
| 3239 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 3240 | |
| 3241 | // Integer comparisons |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 3242 | let Defs = [EFLAGS] in { |
Sean Callanan | a09caa5 | 2009-09-02 00:55:49 +0000 | [diff] [blame] | 3243 | def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src), |
| 3244 | "cmp{b}\t{$src, %al|%al, $src}", []>; |
| 3245 | def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src), |
| 3246 | "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 3247 | def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src), |
| 3248 | "cmp{l}\t{$src, %eax|%eax, $src}", []>; |
| 3249 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3250 | def CMP8rr : I<0x38, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3251 | (outs), (ins GR8 :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3252 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3253 | [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3254 | def CMP16rr : I<0x39, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3255 | (outs), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3256 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3257 | [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3258 | def CMP32rr : I<0x39, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3259 | (outs), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3260 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3261 | [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3262 | def CMP8mr : I<0x38, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3263 | (outs), (ins i8mem :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3264 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3265 | [(X86cmp (loadi8 addr:$src1), GR8:$src2), |
| 3266 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3267 | def CMP16mr : I<0x39, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3268 | (outs), (ins i16mem:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3269 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3270 | [(X86cmp (loadi16 addr:$src1), GR16:$src2), |
| 3271 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3272 | def CMP32mr : I<0x39, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3273 | (outs), (ins i32mem:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3274 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3275 | [(X86cmp (loadi32 addr:$src1), GR32:$src2), |
| 3276 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3277 | def CMP8rm : I<0x3A, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3278 | (outs), (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3279 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3280 | [(X86cmp GR8:$src1, (loadi8 addr:$src2)), |
| 3281 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3282 | def CMP16rm : I<0x3B, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3283 | (outs), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3284 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3285 | [(X86cmp GR16:$src1, (loadi16 addr:$src2)), |
| 3286 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3287 | def CMP32rm : I<0x3B, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3288 | (outs), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3289 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3290 | [(X86cmp GR32:$src1, (loadi32 addr:$src2)), |
| 3291 | (implicit EFLAGS)]>; |
Sean Callanan | d2125a0 | 2009-09-16 21:11:23 +0000 | [diff] [blame] | 3292 | def CMP8mrmrr : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2), |
| 3293 | "cmp{b}\t{$src2, $src1|$src1, $src2}", []>; |
| 3294 | def CMP16mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2), |
| 3295 | "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize; |
| 3296 | def CMP32mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2), |
| 3297 | "cmp{l}\t{$src2, $src1|$src1, $src2}", []>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3298 | def CMP8ri : Ii8<0x80, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3299 | (outs), (ins GR8:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3300 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3301 | [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3302 | def CMP16ri : Ii16<0x81, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3303 | (outs), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3304 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3305 | [(X86cmp GR16:$src1, imm:$src2), |
| 3306 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3307 | def CMP32ri : Ii32<0x81, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3308 | (outs), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3309 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3310 | [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3311 | def CMP8mi : Ii8 <0x80, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3312 | (outs), (ins i8mem :$src1, i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3313 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3314 | [(X86cmp (loadi8 addr:$src1), imm:$src2), |
| 3315 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3316 | def CMP16mi : Ii16<0x81, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3317 | (outs), (ins i16mem:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3318 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3319 | [(X86cmp (loadi16 addr:$src1), imm:$src2), |
| 3320 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 3321 | def CMP32mi : Ii32<0x81, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3322 | (outs), (ins i32mem:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3323 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3324 | [(X86cmp (loadi32 addr:$src1), imm:$src2), |
| 3325 | (implicit EFLAGS)]>; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 3326 | def CMP16ri8 : Ii8<0x83, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3327 | (outs), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3328 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3329 | [(X86cmp GR16:$src1, i16immSExt8:$src2), |
| 3330 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 3331 | def CMP16mi8 : Ii8<0x83, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3332 | (outs), (ins i16mem:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3333 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3334 | [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2), |
| 3335 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 3336 | def CMP32mi8 : Ii8<0x83, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3337 | (outs), (ins i32mem:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3338 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3339 | [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2), |
| 3340 | (implicit EFLAGS)]>; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 3341 | def CMP32ri8 : Ii8<0x83, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3342 | (outs), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3343 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3344 | [(X86cmp GR32:$src1, i32immSExt8:$src2), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 3345 | (implicit EFLAGS)]>; |
| 3346 | } // Defs = [EFLAGS] |
| 3347 | |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 3348 | // Bit tests. |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 3349 | // TODO: BTC, BTR, and BTS |
| 3350 | let Defs = [EFLAGS] in { |
Dan Gohman | 0c89b7e | 2009-01-13 20:32:45 +0000 | [diff] [blame] | 3351 | def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 3352 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
| 3353 | [(X86bt GR16:$src1, GR16:$src2), |
Chris Lattner | f1e9fd5 | 2008-12-25 01:32:49 +0000 | [diff] [blame] | 3354 | (implicit EFLAGS)]>, OpSize, TB; |
Dan Gohman | 0c89b7e | 2009-01-13 20:32:45 +0000 | [diff] [blame] | 3355 | def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 3356 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
| 3357 | [(X86bt GR32:$src1, GR32:$src2), |
Chris Lattner | f1e9fd5 | 2008-12-25 01:32:49 +0000 | [diff] [blame] | 3358 | (implicit EFLAGS)]>, TB; |
Dan Gohman | f31408d | 2009-01-13 23:23:30 +0000 | [diff] [blame] | 3359 | |
| 3360 | // Unlike with the register+register form, the memory+register form of the |
| 3361 | // bt instruction does not ignore the high bits of the index. From ISel's |
| 3362 | // perspective, this is pretty bizarre. Disable these instructions for now. |
| 3363 | //def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), |
| 3364 | // "bt{w}\t{$src2, $src1|$src1, $src2}", |
| 3365 | // [(X86bt (loadi16 addr:$src1), GR16:$src2), |
| 3366 | // (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>; |
| 3367 | //def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), |
| 3368 | // "bt{l}\t{$src2, $src1|$src1, $src2}", |
| 3369 | // [(X86bt (loadi32 addr:$src1), GR32:$src2), |
| 3370 | // (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>; |
Dan Gohman | 4afe15b | 2009-01-13 20:33:23 +0000 | [diff] [blame] | 3371 | |
| 3372 | def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), |
| 3373 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
| 3374 | [(X86bt GR16:$src1, i16immSExt8:$src2), |
| 3375 | (implicit EFLAGS)]>, OpSize, TB; |
| 3376 | def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), |
| 3377 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
| 3378 | [(X86bt GR32:$src1, i32immSExt8:$src2), |
| 3379 | (implicit EFLAGS)]>, TB; |
| 3380 | // Note that these instructions don't need FastBTMem because that |
| 3381 | // only applies when the other operand is in a register. When it's |
| 3382 | // an immediate, bt is still fast. |
| 3383 | def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), |
| 3384 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
| 3385 | [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2), |
| 3386 | (implicit EFLAGS)]>, OpSize, TB; |
| 3387 | def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), |
| 3388 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
| 3389 | [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2), |
| 3390 | (implicit EFLAGS)]>, TB; |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 3391 | } // Defs = [EFLAGS] |
| 3392 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 3393 | // Sign/Zero extenders |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 3394 | // Use movsbl intead of movsbw; we don't care about the high 16 bits |
| 3395 | // of the register here. This has a smaller encoding and avoids a |
| 3396 | // partial-register update. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3397 | def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src), |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 3398 | "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}", |
| 3399 | [(set GR16:$dst, (sext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3400 | def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src), |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 3401 | "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}", |
| 3402 | [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3403 | def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3404 | "movs{bl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3405 | [(set GR32:$dst, (sext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3406 | def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3407 | "movs{bl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3408 | [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3409 | def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3410 | "movs{wl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3411 | [(set GR32:$dst, (sext GR16:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3412 | def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3413 | "movs{wl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3414 | [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB; |
Alkis Evlogimenos | a7be982 | 2004-02-17 09:14:23 +0000 | [diff] [blame] | 3415 | |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 3416 | // Use movzbl intead of movzbw; we don't care about the high 16 bits |
| 3417 | // of the register here. This has a smaller encoding and avoids a |
| 3418 | // partial-register update. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3419 | def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src), |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 3420 | "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}", |
| 3421 | [(set GR16:$dst, (zext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3422 | def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src), |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 3423 | "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}", |
| 3424 | [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3425 | def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3426 | "movz{bl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3427 | [(set GR32:$dst, (zext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3428 | def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3429 | "movz{bl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3430 | [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3431 | def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3432 | "movz{wl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3433 | [(set GR32:$dst, (zext GR16:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3434 | def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3435 | "movz{wl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3436 | [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 3437 | |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3438 | // These are the same as the regular regular MOVZX32rr8 and MOVZX32rm8 |
| 3439 | // except that they use GR32_NOREX for the output operand register class |
| 3440 | // instead of GR32. This allows them to operate on h registers on x86-64. |
| 3441 | def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg, |
| 3442 | (outs GR32_NOREX:$dst), (ins GR8:$src), |
| 3443 | "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX", |
| 3444 | []>, TB; |
Dan Gohman | 78e04d4 | 2009-04-30 03:11:48 +0000 | [diff] [blame] | 3445 | let mayLoad = 1 in |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3446 | def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem, |
| 3447 | (outs GR32_NOREX:$dst), (ins i8mem:$src), |
| 3448 | "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX", |
| 3449 | []>, TB; |
| 3450 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 3451 | let neverHasSideEffects = 1 in { |
| 3452 | let Defs = [AX], Uses = [AL] in |
| 3453 | def CBW : I<0x98, RawFrm, (outs), (ins), |
| 3454 | "{cbtw|cbw}", []>, OpSize; // AX = signext(AL) |
| 3455 | let Defs = [EAX], Uses = [AX] in |
| 3456 | def CWDE : I<0x98, RawFrm, (outs), (ins), |
| 3457 | "{cwtl|cwde}", []>; // EAX = signext(AX) |
Evan Cheng | f91c101 | 2006-05-31 22:05:11 +0000 | [diff] [blame] | 3458 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 3459 | let Defs = [AX,DX], Uses = [AX] in |
| 3460 | def CWD : I<0x99, RawFrm, (outs), (ins), |
| 3461 | "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX) |
| 3462 | let Defs = [EAX,EDX], Uses = [EAX] in |
| 3463 | def CDQ : I<0x99, RawFrm, (outs), (ins), |
| 3464 | "{cltd|cdq}", []>; // EDX:EAX = signext(EAX) |
| 3465 | } |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 3466 | |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 3467 | //===----------------------------------------------------------------------===// |
| 3468 | // Alias Instructions |
| 3469 | //===----------------------------------------------------------------------===// |
| 3470 | |
| 3471 | // Alias instructions that map movr0 to xor. |
| 3472 | // FIXME: remove when we can teach regalloc that xor reg, reg is ok. |
Daniel Dunbar | 7417b76 | 2009-08-11 22:17:52 +0000 | [diff] [blame] | 3473 | let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, |
| 3474 | isCodeGenOnly = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3475 | def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3476 | "xor{b}\t$dst, $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3477 | [(set GR8:$dst, 0)]>; |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 3478 | // Use xorl instead of xorw since we don't care about the high 16 bits, |
| 3479 | // it's smaller, and it avoids a partial-register update. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3480 | def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins), |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 3481 | "xor{l}\t${dst:subreg32}, ${dst:subreg32}", |
| 3482 | [(set GR16:$dst, 0)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3483 | def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3484 | "xor{l}\t$dst, $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3485 | [(set GR32:$dst, 0)]>; |
Dan Gohman | 1ab7989 | 2007-09-07 21:32:51 +0000 | [diff] [blame] | 3486 | } |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 3487 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3488 | //===----------------------------------------------------------------------===// |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 3489 | // Thread Local Storage Instructions |
| 3490 | // |
| 3491 | |
Rafael Espindola | 15f1b66 | 2009-04-24 12:59:40 +0000 | [diff] [blame] | 3492 | // All calls clobber the non-callee saved registers. ESP is marked as |
| 3493 | // a use to prevent stack-pointer assignments that appear immediately |
| 3494 | // before calls from potentially appearing dead. |
| 3495 | let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, |
| 3496 | MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, |
| 3497 | XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, |
| 3498 | XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], |
Chris Lattner | 5c0b16d | 2009-06-20 20:38:48 +0000 | [diff] [blame] | 3499 | Uses = [ESP] in |
| 3500 | def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym), |
| 3501 | "leal\t$sym, %eax; " |
Dan Gohman | 4d47b9b | 2009-04-27 15:13:28 +0000 | [diff] [blame] | 3502 | "call\t___tls_get_addr@PLT", |
Chris Lattner | 5c0b16d | 2009-06-20 20:38:48 +0000 | [diff] [blame] | 3503 | [(X86tlsaddr tls32addr:$sym)]>, |
Rafael Espindola | 2ee3db3 | 2009-04-17 14:35:58 +0000 | [diff] [blame] | 3504 | Requires<[In32BitMode]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 3505 | |
Daniel Dunbar | 0c420fc | 2009-08-11 22:24:40 +0000 | [diff] [blame] | 3506 | let AddedComplexity = 5, isCodeGenOnly = 1 in |
Nate Begeman | 51a0437 | 2009-01-26 01:24:32 +0000 | [diff] [blame] | 3507 | def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
| 3508 | "movl\t%gs:$src, $dst", |
| 3509 | [(set GR32:$dst, (gsload addr:$src))]>, SegGS; |
| 3510 | |
Daniel Dunbar | 0c420fc | 2009-08-11 22:24:40 +0000 | [diff] [blame] | 3511 | let AddedComplexity = 5, isCodeGenOnly = 1 in |
Chris Lattner | 1777d0c | 2009-05-05 18:52:19 +0000 | [diff] [blame] | 3512 | def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
| 3513 | "movl\t%fs:$src, $dst", |
| 3514 | [(set GR32:$dst, (fsload addr:$src))]>, SegFS; |
| 3515 | |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 3516 | //===----------------------------------------------------------------------===// |
Evan Cheng | 3c992d2 | 2006-03-07 02:02:57 +0000 | [diff] [blame] | 3517 | // DWARF Pseudo Instructions |
| 3518 | // |
| 3519 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3520 | def DWARF_LOC : I<0, Pseudo, (outs), |
| 3521 | (ins i32imm:$line, i32imm:$col, i32imm:$file), |
Chris Lattner | 226b608 | 2009-07-10 22:34:11 +0000 | [diff] [blame] | 3522 | ".loc\t$file $line $col", |
Evan Cheng | 3c992d2 | 2006-03-07 02:02:57 +0000 | [diff] [blame] | 3523 | [(dwarf_loc (i32 imm:$line), (i32 imm:$col), |
| 3524 | (i32 imm:$file))]>; |
| 3525 | |
Evan Cheng | 3c992d2 | 2006-03-07 02:02:57 +0000 | [diff] [blame] | 3526 | //===----------------------------------------------------------------------===// |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 3527 | // EH Pseudo Instructions |
| 3528 | // |
| 3529 | let isTerminator = 1, isReturn = 1, isBarrier = 1, |
Daniel Dunbar | 1ca3a0b | 2009-08-27 07:58:05 +0000 | [diff] [blame] | 3530 | hasCtrlDep = 1, isCodeGenOnly = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 3531 | def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 3532 | "ret\t#eh_return, addr: $addr", |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 3533 | [(X86ehret GR32:$addr)]>; |
| 3534 | |
| 3535 | } |
| 3536 | |
| 3537 | //===----------------------------------------------------------------------===// |
Andrew Lenharth | ab0b949 | 2008-02-21 06:45:13 +0000 | [diff] [blame] | 3538 | // Atomic support |
| 3539 | // |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 3540 | |
Evan Cheng | bb6939d | 2008-04-19 01:20:30 +0000 | [diff] [blame] | 3541 | // Atomic swap. These are just normal xchg instructions. But since a memory |
| 3542 | // operand is referenced, the atomicity is ensured. |
Dan Gohman | 165660e | 2008-08-06 15:52:50 +0000 | [diff] [blame] | 3543 | let Constraints = "$val = $dst" in { |
Evan Cheng | bb6939d | 2008-04-19 01:20:30 +0000 | [diff] [blame] | 3544 | def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val), |
| 3545 | "xchg{l}\t{$val, $ptr|$ptr, $val}", |
| 3546 | [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>; |
| 3547 | def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val), |
| 3548 | "xchg{w}\t{$val, $ptr|$ptr, $val}", |
| 3549 | [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>, |
| 3550 | OpSize; |
| 3551 | def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val), |
| 3552 | "xchg{b}\t{$val, $ptr|$ptr, $val}", |
| 3553 | [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>; |
| 3554 | } |
| 3555 | |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3556 | // Atomic compare and swap. |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 3557 | let Defs = [EAX, EFLAGS], Uses = [EAX] in { |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3558 | def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap), |
Dan Gohman | 4d47b9b | 2009-04-27 15:13:28 +0000 | [diff] [blame] | 3559 | "lock\n\t" |
| 3560 | "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}", |
Evan Cheng | 32967d2 | 2008-03-04 03:20:06 +0000 | [diff] [blame] | 3561 | [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK; |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 3562 | } |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 3563 | let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in { |
Anton Korobeynikov | f88a6fa | 2008-07-22 16:22:48 +0000 | [diff] [blame] | 3564 | def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr), |
Dan Gohman | 4d47b9b | 2009-04-27 15:13:28 +0000 | [diff] [blame] | 3565 | "lock\n\t" |
| 3566 | "cmpxchg8b\t$ptr", |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 3567 | [(X86cas8 addr:$ptr)]>, TB, LOCK; |
| 3568 | } |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 3569 | |
| 3570 | let Defs = [AX, EFLAGS], Uses = [AX] in { |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3571 | def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap), |
Dan Gohman | 4d47b9b | 2009-04-27 15:13:28 +0000 | [diff] [blame] | 3572 | "lock\n\t" |
| 3573 | "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}", |
Evan Cheng | 32967d2 | 2008-03-04 03:20:06 +0000 | [diff] [blame] | 3574 | [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK; |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 3575 | } |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 3576 | let Defs = [AL, EFLAGS], Uses = [AL] in { |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3577 | def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap), |
Dan Gohman | 4d47b9b | 2009-04-27 15:13:28 +0000 | [diff] [blame] | 3578 | "lock\n\t" |
| 3579 | "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}", |
Evan Cheng | 32967d2 | 2008-03-04 03:20:06 +0000 | [diff] [blame] | 3580 | [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK; |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 3581 | } |
| 3582 | |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3583 | // Atomic exchange and add |
| 3584 | let Constraints = "$val = $dst", Defs = [EFLAGS] in { |
| 3585 | def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val), |
Dan Gohman | 4d47b9b | 2009-04-27 15:13:28 +0000 | [diff] [blame] | 3586 | "lock\n\t" |
| 3587 | "xadd{l}\t{$val, $ptr|$ptr, $val}", |
Mon P Wang | 2887310 | 2008-06-25 08:15:39 +0000 | [diff] [blame] | 3588 | [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>, |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3589 | TB, LOCK; |
| 3590 | def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val), |
Dan Gohman | 4d47b9b | 2009-04-27 15:13:28 +0000 | [diff] [blame] | 3591 | "lock\n\t" |
| 3592 | "xadd{w}\t{$val, $ptr|$ptr, $val}", |
Mon P Wang | 2887310 | 2008-06-25 08:15:39 +0000 | [diff] [blame] | 3593 | [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>, |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3594 | TB, OpSize, LOCK; |
| 3595 | def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val), |
Dan Gohman | 4d47b9b | 2009-04-27 15:13:28 +0000 | [diff] [blame] | 3596 | "lock\n\t" |
| 3597 | "xadd{b}\t{$val, $ptr|$ptr, $val}", |
Mon P Wang | 2887310 | 2008-06-25 08:15:39 +0000 | [diff] [blame] | 3598 | [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>, |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 3599 | TB, LOCK; |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 3600 | } |
| 3601 | |
Evan Cheng | 37b7387 | 2009-07-30 08:33:02 +0000 | [diff] [blame] | 3602 | // Optimized codegen when the non-memory output is not used. |
| 3603 | // FIXME: Use normal add / sub instructions and add lock prefix dynamically. |
| 3604 | def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), |
| 3605 | "lock\n\t" |
| 3606 | "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
| 3607 | def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
| 3608 | "lock\n\t" |
| 3609 | "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK; |
| 3610 | def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
| 3611 | "lock\n\t" |
| 3612 | "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
| 3613 | def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2), |
| 3614 | "lock\n\t" |
| 3615 | "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
| 3616 | def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2), |
| 3617 | "lock\n\t" |
| 3618 | "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
| 3619 | def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2), |
| 3620 | "lock\n\t" |
| 3621 | "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
| 3622 | def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
| 3623 | "lock\n\t" |
| 3624 | "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK; |
| 3625 | def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
| 3626 | "lock\n\t" |
| 3627 | "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
| 3628 | |
| 3629 | def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), |
| 3630 | "lock\n\t" |
| 3631 | "inc{b}\t$dst", []>, LOCK; |
| 3632 | def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), |
| 3633 | "lock\n\t" |
| 3634 | "inc{w}\t$dst", []>, OpSize, LOCK; |
| 3635 | def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), |
| 3636 | "lock\n\t" |
| 3637 | "inc{l}\t$dst", []>, LOCK; |
| 3638 | |
| 3639 | def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2), |
| 3640 | "lock\n\t" |
| 3641 | "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
| 3642 | def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
| 3643 | "lock\n\t" |
| 3644 | "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK; |
| 3645 | def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
| 3646 | "lock\n\t" |
| 3647 | "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
| 3648 | def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2), |
| 3649 | "lock\n\t" |
| 3650 | "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
| 3651 | def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2), |
| 3652 | "lock\n\t" |
| 3653 | "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK; |
| 3654 | def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2), |
| 3655 | "lock\n\t" |
| 3656 | "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
| 3657 | def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
| 3658 | "lock\n\t" |
| 3659 | "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK; |
| 3660 | def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
| 3661 | "lock\n\t" |
| 3662 | "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK; |
| 3663 | |
| 3664 | def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), |
| 3665 | "lock\n\t" |
| 3666 | "dec{b}\t$dst", []>, LOCK; |
| 3667 | def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), |
| 3668 | "lock\n\t" |
| 3669 | "dec{w}\t$dst", []>, OpSize, LOCK; |
| 3670 | def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), |
| 3671 | "lock\n\t" |
| 3672 | "dec{l}\t$dst", []>, LOCK; |
| 3673 | |
Mon P Wang | 2887310 | 2008-06-25 08:15:39 +0000 | [diff] [blame] | 3674 | // Atomic exchange, and, or, xor |
Mon P Wang | 63307c3 | 2008-05-05 19:05:59 +0000 | [diff] [blame] | 3675 | let Constraints = "$val = $dst", Defs = [EFLAGS], |
| 3676 | usesCustomDAGSchedInserter = 1 in { |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 3677 | def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3678 | "#ATOMAND32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3679 | [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 3680 | def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3681 | "#ATOMOR32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3682 | [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 3683 | def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3684 | "#ATOMXOR32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3685 | [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>; |
Andrew Lenharth | 507a58a | 2008-06-14 05:48:15 +0000 | [diff] [blame] | 3686 | def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3687 | "#ATOMNAND32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3688 | [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 3689 | def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3690 | "#ATOMMIN32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3691 | [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 3692 | def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3693 | "#ATOMMAX32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3694 | [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 3695 | def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3696 | "#ATOMUMIN32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3697 | [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 3698 | def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3699 | "#ATOMUMAX32 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3700 | [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3701 | |
| 3702 | def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3703 | "#ATOMAND16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3704 | [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3705 | def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3706 | "#ATOMOR16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3707 | [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3708 | def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3709 | "#ATOMXOR16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3710 | [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3711 | def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3712 | "#ATOMNAND16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3713 | [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3714 | def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3715 | "#ATOMMIN16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3716 | [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3717 | def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3718 | "#ATOMMAX16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3719 | [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3720 | def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3721 | "#ATOMUMIN16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3722 | [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3723 | def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3724 | "#ATOMUMAX16 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3725 | [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3726 | |
| 3727 | def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3728 | "#ATOMAND8 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3729 | [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3730 | def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3731 | "#ATOMOR8 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3732 | [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3733 | def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3734 | "#ATOMXOR8 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3735 | [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 3736 | def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3737 | "#ATOMNAND8 PSEUDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 3738 | [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>; |
Mon P Wang | 63307c3 | 2008-05-05 19:05:59 +0000 | [diff] [blame] | 3739 | } |
| 3740 | |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 3741 | let Constraints = "$val1 = $dst1, $val2 = $dst2", |
| 3742 | Defs = [EFLAGS, EAX, EBX, ECX, EDX], |
| 3743 | Uses = [EAX, EBX, ECX, EDX], |
Dale Johannesen | 1b54c7f | 2008-10-03 19:41:08 +0000 | [diff] [blame] | 3744 | mayLoad = 1, mayStore = 1, |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 3745 | usesCustomDAGSchedInserter = 1 in { |
| 3746 | def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 3747 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3748 | "#ATOMAND6432 PSEUDO!", []>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 3749 | def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 3750 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3751 | "#ATOMOR6432 PSEUDO!", []>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 3752 | def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 3753 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3754 | "#ATOMXOR6432 PSEUDO!", []>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 3755 | def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 3756 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3757 | "#ATOMNAND6432 PSEUDO!", []>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 3758 | def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 3759 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3760 | "#ATOMADD6432 PSEUDO!", []>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 3761 | def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 3762 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3763 | "#ATOMSUB6432 PSEUDO!", []>; |
Dale Johannesen | 880ae36 | 2008-10-03 22:25:52 +0000 | [diff] [blame] | 3764 | def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 3765 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
Nick Lewycky | 6ecf5ce | 2008-12-07 03:49:52 +0000 | [diff] [blame] | 3766 | "#ATOMSWAP6432 PSEUDO!", []>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 3767 | } |
| 3768 | |
Sean Callanan | 358f1ef | 2009-09-16 21:55:34 +0000 | [diff] [blame] | 3769 | // Segmentation support instructions. |
| 3770 | |
| 3771 | def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
| 3772 | "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 3773 | def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
| 3774 | "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 3775 | |
| 3776 | // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo. |
| 3777 | def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), |
| 3778 | "lar{l}\t{$src, $dst|$dst, $src}", []>, TB; |
| 3779 | def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
| 3780 | "lar{l}\t{$src, $dst|$dst, $src}", []>, TB; |
Sean Callanan | 9a86f10 | 2009-09-16 22:59:28 +0000 | [diff] [blame] | 3781 | |
| 3782 | // String manipulation instructions |
| 3783 | |
| 3784 | def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>; |
| 3785 | def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize; |
| 3786 | def LODSD : I<0xAD, RawFrm, (outs), (ins), "lodsd", []>; |
Sean Callanan | 358f1ef | 2009-09-16 21:55:34 +0000 | [diff] [blame] | 3787 | |
Andrew Lenharth | ab0b949 | 2008-02-21 06:45:13 +0000 | [diff] [blame] | 3788 | //===----------------------------------------------------------------------===// |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3789 | // Non-Instruction Patterns |
| 3790 | //===----------------------------------------------------------------------===// |
| 3791 | |
Bill Wendling | 056292f | 2008-09-16 21:48:12 +0000 | [diff] [blame] | 3792 | // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 3793 | def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>; |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 3794 | def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>; |
Nate Begeman | 6795ebb | 2008-04-12 00:47:57 +0000 | [diff] [blame] | 3795 | def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>; |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 3796 | def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>; |
| 3797 | def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>; |
| 3798 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3799 | def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)), |
| 3800 | (ADD32ri GR32:$src1, tconstpool:$src2)>; |
| 3801 | def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)), |
| 3802 | (ADD32ri GR32:$src1, tjumptable:$src2)>; |
| 3803 | def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)), |
| 3804 | (ADD32ri GR32:$src1, tglobaladdr:$src2)>; |
| 3805 | def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)), |
| 3806 | (ADD32ri GR32:$src1, texternalsym:$src2)>; |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 3807 | |
Evan Cheng | fc8feb1 | 2006-05-19 07:30:36 +0000 | [diff] [blame] | 3808 | def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst), |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 3809 | (MOV32mi addr:$dst, tglobaladdr:$src)>; |
Evan Cheng | fc8feb1 | 2006-05-19 07:30:36 +0000 | [diff] [blame] | 3810 | def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst), |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 3811 | (MOV32mi addr:$dst, texternalsym:$src)>; |
| 3812 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3813 | // Calls |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 3814 | // tailcall stuff |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 3815 | def : Pat<(X86tcret GR32:$dst, imm:$off), |
| 3816 | (TCRETURNri GR32:$dst, imm:$off)>; |
| 3817 | |
| 3818 | def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off), |
| 3819 | (TCRETURNdi texternalsym:$dst, imm:$off)>; |
| 3820 | |
| 3821 | def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off), |
| 3822 | (TCRETURNdi texternalsym:$dst, imm:$off)>; |
Evan Cheng | fea89c1 | 2006-04-27 08:40:39 +0000 | [diff] [blame] | 3823 | |
Dan Gohman | cadb226 | 2009-08-02 16:10:01 +0000 | [diff] [blame] | 3824 | // Normal calls, with various flavors of addresses. |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 3825 | def : Pat<(X86call (i32 tglobaladdr:$dst)), |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3826 | (CALLpcrel32 tglobaladdr:$dst)>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 3827 | def : Pat<(X86call (i32 texternalsym:$dst)), |
Evan Cheng | 8700e14 | 2006-01-11 06:09:51 +0000 | [diff] [blame] | 3828 | (CALLpcrel32 texternalsym:$dst)>; |
Evan Cheng | d7f666a | 2009-05-20 04:53:57 +0000 | [diff] [blame] | 3829 | def : Pat<(X86call (i32 imm:$dst)), |
| 3830 | (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3831 | |
| 3832 | // X86 specific add which produces a flag. |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3833 | def : Pat<(addc GR32:$src1, GR32:$src2), |
| 3834 | (ADD32rr GR32:$src1, GR32:$src2)>; |
| 3835 | def : Pat<(addc GR32:$src1, (load addr:$src2)), |
| 3836 | (ADD32rm GR32:$src1, addr:$src2)>; |
| 3837 | def : Pat<(addc GR32:$src1, imm:$src2), |
| 3838 | (ADD32ri GR32:$src1, imm:$src2)>; |
| 3839 | def : Pat<(addc GR32:$src1, i32immSExt8:$src2), |
| 3840 | (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3841 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3842 | def : Pat<(subc GR32:$src1, GR32:$src2), |
| 3843 | (SUB32rr GR32:$src1, GR32:$src2)>; |
| 3844 | def : Pat<(subc GR32:$src1, (load addr:$src2)), |
| 3845 | (SUB32rm GR32:$src1, addr:$src2)>; |
| 3846 | def : Pat<(subc GR32:$src1, imm:$src2), |
| 3847 | (SUB32ri GR32:$src1, imm:$src2)>; |
| 3848 | def : Pat<(subc GR32:$src1, i32immSExt8:$src2), |
| 3849 | (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3850 | |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 3851 | // Comparisons. |
| 3852 | |
| 3853 | // TEST R,R is smaller than CMP R,0 |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3854 | def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 3855 | (TEST8rr GR8:$src1, GR8:$src1)>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3856 | def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)), |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 3857 | (TEST16rr GR16:$src1, GR16:$src1)>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 3858 | def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)), |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 3859 | (TEST32rr GR32:$src1, GR32:$src1)>; |
| 3860 | |
Dan Gohman | fbb7486 | 2009-01-07 01:00:24 +0000 | [diff] [blame] | 3861 | // Conditional moves with folded loads with operands swapped and conditions |
| 3862 | // inverted. |
| 3863 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS), |
| 3864 | (CMOVAE16rm GR16:$src2, addr:$src1)>; |
| 3865 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS), |
| 3866 | (CMOVAE32rm GR32:$src2, addr:$src1)>; |
| 3867 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS), |
| 3868 | (CMOVB16rm GR16:$src2, addr:$src1)>; |
| 3869 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS), |
| 3870 | (CMOVB32rm GR32:$src2, addr:$src1)>; |
| 3871 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS), |
| 3872 | (CMOVNE16rm GR16:$src2, addr:$src1)>; |
| 3873 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS), |
| 3874 | (CMOVNE32rm GR32:$src2, addr:$src1)>; |
| 3875 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS), |
| 3876 | (CMOVE16rm GR16:$src2, addr:$src1)>; |
| 3877 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS), |
| 3878 | (CMOVE32rm GR32:$src2, addr:$src1)>; |
| 3879 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS), |
| 3880 | (CMOVA16rm GR16:$src2, addr:$src1)>; |
| 3881 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS), |
| 3882 | (CMOVA32rm GR32:$src2, addr:$src1)>; |
| 3883 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS), |
| 3884 | (CMOVBE16rm GR16:$src2, addr:$src1)>; |
| 3885 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS), |
| 3886 | (CMOVBE32rm GR32:$src2, addr:$src1)>; |
| 3887 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS), |
| 3888 | (CMOVGE16rm GR16:$src2, addr:$src1)>; |
| 3889 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS), |
| 3890 | (CMOVGE32rm GR32:$src2, addr:$src1)>; |
| 3891 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS), |
| 3892 | (CMOVL16rm GR16:$src2, addr:$src1)>; |
| 3893 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS), |
| 3894 | (CMOVL32rm GR32:$src2, addr:$src1)>; |
| 3895 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS), |
| 3896 | (CMOVG16rm GR16:$src2, addr:$src1)>; |
| 3897 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS), |
| 3898 | (CMOVG32rm GR32:$src2, addr:$src1)>; |
| 3899 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS), |
| 3900 | (CMOVLE16rm GR16:$src2, addr:$src1)>; |
| 3901 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS), |
| 3902 | (CMOVLE32rm GR32:$src2, addr:$src1)>; |
| 3903 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS), |
| 3904 | (CMOVNP16rm GR16:$src2, addr:$src1)>; |
| 3905 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS), |
| 3906 | (CMOVNP32rm GR32:$src2, addr:$src1)>; |
| 3907 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS), |
| 3908 | (CMOVP16rm GR16:$src2, addr:$src1)>; |
| 3909 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS), |
| 3910 | (CMOVP32rm GR32:$src2, addr:$src1)>; |
| 3911 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS), |
| 3912 | (CMOVNS16rm GR16:$src2, addr:$src1)>; |
| 3913 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS), |
| 3914 | (CMOVNS32rm GR32:$src2, addr:$src1)>; |
| 3915 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS), |
| 3916 | (CMOVS16rm GR16:$src2, addr:$src1)>; |
| 3917 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS), |
| 3918 | (CMOVS32rm GR32:$src2, addr:$src1)>; |
| 3919 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS), |
| 3920 | (CMOVNO16rm GR16:$src2, addr:$src1)>; |
| 3921 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS), |
| 3922 | (CMOVNO32rm GR32:$src2, addr:$src1)>; |
| 3923 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS), |
| 3924 | (CMOVO16rm GR16:$src2, addr:$src1)>; |
| 3925 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS), |
| 3926 | (CMOVO32rm GR32:$src2, addr:$src1)>; |
| 3927 | |
Duncan Sands | f9c98e6 | 2008-01-23 20:39:46 +0000 | [diff] [blame] | 3928 | // zextload bool -> zextload byte |
Evan Cheng | e5d9343 | 2006-01-17 07:02:46 +0000 | [diff] [blame] | 3929 | def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3930 | def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; |
| 3931 | def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; |
| 3932 | |
| 3933 | // extload bool -> extload byte |
Evan Cheng | 4713724 | 2006-05-05 08:23:07 +0000 | [diff] [blame] | 3934 | def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; |
Dan Gohman | af70e5c | 2009-08-26 14:59:13 +0000 | [diff] [blame] | 3935 | def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; |
Evan Cheng | 4713724 | 2006-05-05 08:23:07 +0000 | [diff] [blame] | 3936 | def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; |
Dan Gohman | af70e5c | 2009-08-26 14:59:13 +0000 | [diff] [blame] | 3937 | def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; |
Evan Cheng | 4713724 | 2006-05-05 08:23:07 +0000 | [diff] [blame] | 3938 | def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; |
| 3939 | def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3940 | |
Dan Gohman | af70e5c | 2009-08-26 14:59:13 +0000 | [diff] [blame] | 3941 | // anyext. Define these to do an explicit zero-extend to |
| 3942 | // avoid partial-register updates. |
| 3943 | def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>; |
| 3944 | def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; |
| 3945 | def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 3946 | |
Evan Cheng | 1314b00 | 2007-12-13 00:43:27 +0000 | [diff] [blame] | 3947 | // (and (i32 load), 255) -> (zextload i8) |
Evan Cheng | d47e0b6 | 2008-09-29 17:26:18 +0000 | [diff] [blame] | 3948 | def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))), |
| 3949 | (MOVZX32rm8 addr:$src)>; |
| 3950 | def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))), |
| 3951 | (MOVZX32rm16 addr:$src)>; |
Evan Cheng | 1314b00 | 2007-12-13 00:43:27 +0000 | [diff] [blame] | 3952 | |
Evan Cheng | cfa260b | 2006-01-06 02:31:59 +0000 | [diff] [blame] | 3953 | //===----------------------------------------------------------------------===// |
| 3954 | // Some peepholes |
| 3955 | //===----------------------------------------------------------------------===// |
| 3956 | |
Dan Gohman | 63f9720 | 2008-10-17 01:33:43 +0000 | [diff] [blame] | 3957 | // Odd encoding trick: -128 fits into an 8-bit immediate field while |
| 3958 | // +128 doesn't, so in this special case use a sub instead of an add. |
| 3959 | def : Pat<(add GR16:$src1, 128), |
| 3960 | (SUB16ri8 GR16:$src1, -128)>; |
| 3961 | def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), |
| 3962 | (SUB16mi8 addr:$dst, -128)>; |
| 3963 | def : Pat<(add GR32:$src1, 128), |
| 3964 | (SUB32ri8 GR32:$src1, -128)>; |
| 3965 | def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), |
| 3966 | (SUB32mi8 addr:$dst, -128)>; |
| 3967 | |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 3968 | // r & (2^16-1) ==> movz |
| 3969 | def : Pat<(and GR32:$src1, 0xffff), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3970 | (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>; |
Dan Gohman | 8a1510d | 2008-08-06 18:27:21 +0000 | [diff] [blame] | 3971 | // r & (2^8-1) ==> movz |
| 3972 | def : Pat<(and GR32:$src1, 0xff), |
Dan Gohman | 6241762 | 2009-04-27 16:33:14 +0000 | [diff] [blame] | 3973 | (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_ABCD), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3974 | x86_subreg_8bit))>, |
Dan Gohman | 8a1510d | 2008-08-06 18:27:21 +0000 | [diff] [blame] | 3975 | Requires<[In32BitMode]>; |
| 3976 | // r & (2^8-1) ==> movz |
| 3977 | def : Pat<(and GR16:$src1, 0xff), |
Dan Gohman | 6241762 | 2009-04-27 16:33:14 +0000 | [diff] [blame] | 3978 | (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3979 | x86_subreg_8bit))>, |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 3980 | Requires<[In32BitMode]>; |
| 3981 | |
| 3982 | // sext_inreg patterns |
| 3983 | def : Pat<(sext_inreg GR32:$src, i16), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3984 | (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>; |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 3985 | def : Pat<(sext_inreg GR32:$src, i8), |
Dan Gohman | 6241762 | 2009-04-27 16:33:14 +0000 | [diff] [blame] | 3986 | (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3987 | x86_subreg_8bit))>, |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 3988 | Requires<[In32BitMode]>; |
| 3989 | def : Pat<(sext_inreg GR16:$src, i8), |
Dan Gohman | 6241762 | 2009-04-27 16:33:14 +0000 | [diff] [blame] | 3990 | (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3991 | x86_subreg_8bit))>, |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 3992 | Requires<[In32BitMode]>; |
| 3993 | |
| 3994 | // trunc patterns |
| 3995 | def : Pat<(i16 (trunc GR32:$src)), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3996 | (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>; |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 3997 | def : Pat<(i8 (trunc GR32:$src)), |
Dan Gohman | 6241762 | 2009-04-27 16:33:14 +0000 | [diff] [blame] | 3998 | (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 3999 | x86_subreg_8bit)>, |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 4000 | Requires<[In32BitMode]>; |
| 4001 | def : Pat<(i8 (trunc GR16:$src)), |
Dan Gohman | 6241762 | 2009-04-27 16:33:14 +0000 | [diff] [blame] | 4002 | (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 4003 | x86_subreg_8bit)>, |
| 4004 | Requires<[In32BitMode]>; |
| 4005 | |
| 4006 | // h-register tricks |
| 4007 | def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), |
Dan Gohman | 6241762 | 2009-04-27 16:33:14 +0000 | [diff] [blame] | 4008 | (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 4009 | x86_subreg_8bit_hi)>, |
| 4010 | Requires<[In32BitMode]>; |
| 4011 | def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), |
Dan Gohman | 6241762 | 2009-04-27 16:33:14 +0000 | [diff] [blame] | 4012 | (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 4013 | x86_subreg_8bit_hi)>, |
| 4014 | Requires<[In32BitMode]>; |
| 4015 | def : Pat<(srl_su GR16:$src, (i8 8)), |
| 4016 | (EXTRACT_SUBREG |
| 4017 | (MOVZX32rr8 |
Dan Gohman | 6241762 | 2009-04-27 16:33:14 +0000 | [diff] [blame] | 4018 | (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 4019 | x86_subreg_8bit_hi)), |
| 4020 | x86_subreg_16bit)>, |
| 4021 | Requires<[In32BitMode]>; |
Evan Cheng | cb219f0 | 2009-05-29 01:44:43 +0000 | [diff] [blame] | 4022 | def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), |
| 4023 | (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD), |
| 4024 | x86_subreg_8bit_hi))>, |
| 4025 | Requires<[In32BitMode]>; |
Dan Gohman | af70e5c | 2009-08-26 14:59:13 +0000 | [diff] [blame] | 4026 | def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), |
| 4027 | (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD), |
| 4028 | x86_subreg_8bit_hi))>, |
| 4029 | Requires<[In32BitMode]>; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 4030 | def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), |
Dan Gohman | 6241762 | 2009-04-27 16:33:14 +0000 | [diff] [blame] | 4031 | (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD), |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 4032 | x86_subreg_8bit_hi))>, |
Dan Gohman | 8a1510d | 2008-08-06 18:27:21 +0000 | [diff] [blame] | 4033 | Requires<[In32BitMode]>; |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 4034 | |
Evan Cheng | cfa260b | 2006-01-06 02:31:59 +0000 | [diff] [blame] | 4035 | // (shl x, 1) ==> (add x, x) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 4036 | def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; |
| 4037 | def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; |
| 4038 | def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; |
Evan Cheng | 68b951a | 2006-01-19 01:56:29 +0000 | [diff] [blame] | 4039 | |
Evan Cheng | eb9f892 | 2008-08-30 02:03:58 +0000 | [diff] [blame] | 4040 | // (shl x (and y, 31)) ==> (shl x, y) |
| 4041 | def : Pat<(shl GR8:$src1, (and CL:$amt, 31)), |
| 4042 | (SHL8rCL GR8:$src1)>; |
| 4043 | def : Pat<(shl GR16:$src1, (and CL:$amt, 31)), |
| 4044 | (SHL16rCL GR16:$src1)>; |
| 4045 | def : Pat<(shl GR32:$src1, (and CL:$amt, 31)), |
| 4046 | (SHL32rCL GR32:$src1)>; |
| 4047 | def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 4048 | (SHL8mCL addr:$dst)>; |
| 4049 | def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 4050 | (SHL16mCL addr:$dst)>; |
| 4051 | def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 4052 | (SHL32mCL addr:$dst)>; |
| 4053 | |
| 4054 | def : Pat<(srl GR8:$src1, (and CL:$amt, 31)), |
| 4055 | (SHR8rCL GR8:$src1)>; |
| 4056 | def : Pat<(srl GR16:$src1, (and CL:$amt, 31)), |
| 4057 | (SHR16rCL GR16:$src1)>; |
| 4058 | def : Pat<(srl GR32:$src1, (and CL:$amt, 31)), |
| 4059 | (SHR32rCL GR32:$src1)>; |
| 4060 | def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 4061 | (SHR8mCL addr:$dst)>; |
| 4062 | def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 4063 | (SHR16mCL addr:$dst)>; |
| 4064 | def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 4065 | (SHR32mCL addr:$dst)>; |
| 4066 | |
| 4067 | def : Pat<(sra GR8:$src1, (and CL:$amt, 31)), |
| 4068 | (SAR8rCL GR8:$src1)>; |
| 4069 | def : Pat<(sra GR16:$src1, (and CL:$amt, 31)), |
| 4070 | (SAR16rCL GR16:$src1)>; |
| 4071 | def : Pat<(sra GR32:$src1, (and CL:$amt, 31)), |
| 4072 | (SAR32rCL GR32:$src1)>; |
| 4073 | def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 4074 | (SAR8mCL addr:$dst)>; |
| 4075 | def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 4076 | (SAR16mCL addr:$dst)>; |
| 4077 | def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 4078 | (SAR32mCL addr:$dst)>; |
| 4079 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 4080 | // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 4081 | def : Pat<(or (srl GR32:$src1, CL:$amt), |
| 4082 | (shl GR32:$src2, (sub 32, CL:$amt))), |
| 4083 | (SHRD32rrCL GR32:$src1, GR32:$src2)>; |
Evan Cheng | 68b951a | 2006-01-19 01:56:29 +0000 | [diff] [blame] | 4084 | |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 4085 | def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt), |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 4086 | (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst), |
| 4087 | (SHRD32mrCL addr:$dst, GR32:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 4088 | |
Dan Gohman | 74feef2 | 2008-10-17 01:23:35 +0000 | [diff] [blame] | 4089 | def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))), |
| 4090 | (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))), |
| 4091 | (SHRD32rrCL GR32:$src1, GR32:$src2)>; |
| 4092 | |
| 4093 | def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))), |
| 4094 | (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))), |
| 4095 | addr:$dst), |
| 4096 | (SHRD32mrCL addr:$dst, GR32:$src2)>; |
| 4097 | |
| 4098 | def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)), |
| 4099 | (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>; |
| 4100 | |
| 4101 | def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1), |
| 4102 | GR32:$src2, (i8 imm:$amt2)), addr:$dst), |
| 4103 | (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>; |
| 4104 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 4105 | // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 4106 | def : Pat<(or (shl GR32:$src1, CL:$amt), |
| 4107 | (srl GR32:$src2, (sub 32, CL:$amt))), |
| 4108 | (SHLD32rrCL GR32:$src1, GR32:$src2)>; |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 4109 | |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 4110 | def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt), |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 4111 | (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst), |
| 4112 | (SHLD32mrCL addr:$dst, GR32:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 4113 | |
Dan Gohman | 74feef2 | 2008-10-17 01:23:35 +0000 | [diff] [blame] | 4114 | def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))), |
| 4115 | (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))), |
| 4116 | (SHLD32rrCL GR32:$src1, GR32:$src2)>; |
| 4117 | |
| 4118 | def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))), |
| 4119 | (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))), |
| 4120 | addr:$dst), |
| 4121 | (SHLD32mrCL addr:$dst, GR32:$src2)>; |
| 4122 | |
| 4123 | def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)), |
| 4124 | (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>; |
| 4125 | |
| 4126 | def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1), |
| 4127 | GR32:$src2, (i8 imm:$amt2)), addr:$dst), |
| 4128 | (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>; |
| 4129 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 4130 | // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 4131 | def : Pat<(or (srl GR16:$src1, CL:$amt), |
| 4132 | (shl GR16:$src2, (sub 16, CL:$amt))), |
| 4133 | (SHRD16rrCL GR16:$src1, GR16:$src2)>; |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 4134 | |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 4135 | def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt), |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 4136 | (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst), |
| 4137 | (SHRD16mrCL addr:$dst, GR16:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 4138 | |
Dan Gohman | 74feef2 | 2008-10-17 01:23:35 +0000 | [diff] [blame] | 4139 | def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))), |
| 4140 | (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))), |
| 4141 | (SHRD16rrCL GR16:$src1, GR16:$src2)>; |
| 4142 | |
| 4143 | def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))), |
| 4144 | (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))), |
| 4145 | addr:$dst), |
| 4146 | (SHRD16mrCL addr:$dst, GR16:$src2)>; |
| 4147 | |
| 4148 | def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)), |
| 4149 | (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>; |
| 4150 | |
| 4151 | def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1), |
| 4152 | GR16:$src2, (i8 imm:$amt2)), addr:$dst), |
| 4153 | (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>; |
| 4154 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 4155 | // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 4156 | def : Pat<(or (shl GR16:$src1, CL:$amt), |
| 4157 | (srl GR16:$src2, (sub 16, CL:$amt))), |
| 4158 | (SHLD16rrCL GR16:$src1, GR16:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 4159 | |
| 4160 | def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt), |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 4161 | (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst), |
| 4162 | (SHLD16mrCL addr:$dst, GR16:$src2)>; |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 4163 | |
Dan Gohman | 74feef2 | 2008-10-17 01:23:35 +0000 | [diff] [blame] | 4164 | def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))), |
| 4165 | (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))), |
| 4166 | (SHLD16rrCL GR16:$src1, GR16:$src2)>; |
| 4167 | |
| 4168 | def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))), |
| 4169 | (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))), |
| 4170 | addr:$dst), |
| 4171 | (SHLD16mrCL addr:$dst, GR16:$src2)>; |
| 4172 | |
| 4173 | def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)), |
| 4174 | (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>; |
| 4175 | |
| 4176 | def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1), |
| 4177 | GR16:$src2, (i8 imm:$amt2)), addr:$dst), |
| 4178 | (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>; |
| 4179 | |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 4180 | //===----------------------------------------------------------------------===// |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4181 | // EFLAGS-defining Patterns |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4182 | //===----------------------------------------------------------------------===// |
| 4183 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4184 | // Register-Register Addition with EFLAGS result |
| 4185 | def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4186 | (implicit EFLAGS)), |
| 4187 | (ADD8rr GR8:$src1, GR8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4188 | def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4189 | (implicit EFLAGS)), |
| 4190 | (ADD16rr GR16:$src1, GR16:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4191 | def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4192 | (implicit EFLAGS)), |
| 4193 | (ADD32rr GR32:$src1, GR32:$src2)>; |
| 4194 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4195 | // Register-Memory Addition with EFLAGS result |
| 4196 | def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4197 | (implicit EFLAGS)), |
| 4198 | (ADD8rm GR8:$src1, addr:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4199 | def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4200 | (implicit EFLAGS)), |
| 4201 | (ADD16rm GR16:$src1, addr:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4202 | def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4203 | (implicit EFLAGS)), |
| 4204 | (ADD32rm GR32:$src1, addr:$src2)>; |
| 4205 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4206 | // Register-Integer Addition with EFLAGS result |
| 4207 | def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4208 | (implicit EFLAGS)), |
| 4209 | (ADD8ri GR8:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4210 | def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4211 | (implicit EFLAGS)), |
| 4212 | (ADD16ri GR16:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4213 | def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4214 | (implicit EFLAGS)), |
| 4215 | (ADD32ri GR32:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4216 | def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4217 | (implicit EFLAGS)), |
| 4218 | (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4219 | def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4220 | (implicit EFLAGS)), |
| 4221 | (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; |
| 4222 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4223 | // Memory-Register Addition with EFLAGS result |
| 4224 | def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4225 | addr:$dst), |
| 4226 | (implicit EFLAGS)), |
| 4227 | (ADD8mr addr:$dst, GR8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4228 | def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4229 | addr:$dst), |
| 4230 | (implicit EFLAGS)), |
| 4231 | (ADD16mr addr:$dst, GR16:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4232 | def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4233 | addr:$dst), |
| 4234 | (implicit EFLAGS)), |
| 4235 | (ADD32mr addr:$dst, GR32:$src2)>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 4236 | |
| 4237 | // Memory-Integer Addition with EFLAGS result |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4238 | def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4239 | addr:$dst), |
| 4240 | (implicit EFLAGS)), |
| 4241 | (ADD8mi addr:$dst, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4242 | def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4243 | addr:$dst), |
| 4244 | (implicit EFLAGS)), |
| 4245 | (ADD16mi addr:$dst, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4246 | def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4247 | addr:$dst), |
| 4248 | (implicit EFLAGS)), |
| 4249 | (ADD32mi addr:$dst, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4250 | def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4251 | addr:$dst), |
| 4252 | (implicit EFLAGS)), |
| 4253 | (ADD16mi8 addr:$dst, i16immSExt8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4254 | def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4255 | addr:$dst), |
| 4256 | (implicit EFLAGS)), |
| 4257 | (ADD32mi8 addr:$dst, i32immSExt8:$src2)>; |
| 4258 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4259 | // Register-Register Subtraction with EFLAGS result |
| 4260 | def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4261 | (implicit EFLAGS)), |
| 4262 | (SUB8rr GR8:$src1, GR8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4263 | def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4264 | (implicit EFLAGS)), |
| 4265 | (SUB16rr GR16:$src1, GR16:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4266 | def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4267 | (implicit EFLAGS)), |
| 4268 | (SUB32rr GR32:$src1, GR32:$src2)>; |
| 4269 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4270 | // Register-Memory Subtraction with EFLAGS result |
| 4271 | def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4272 | (implicit EFLAGS)), |
| 4273 | (SUB8rm GR8:$src1, addr:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4274 | def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4275 | (implicit EFLAGS)), |
| 4276 | (SUB16rm GR16:$src1, addr:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4277 | def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4278 | (implicit EFLAGS)), |
| 4279 | (SUB32rm GR32:$src1, addr:$src2)>; |
| 4280 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4281 | // Register-Integer Subtraction with EFLAGS result |
| 4282 | def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4283 | (implicit EFLAGS)), |
| 4284 | (SUB8ri GR8:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4285 | def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4286 | (implicit EFLAGS)), |
| 4287 | (SUB16ri GR16:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4288 | def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4289 | (implicit EFLAGS)), |
| 4290 | (SUB32ri GR32:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4291 | def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4292 | (implicit EFLAGS)), |
| 4293 | (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4294 | def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4295 | (implicit EFLAGS)), |
| 4296 | (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; |
| 4297 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4298 | // Memory-Register Subtraction with EFLAGS result |
| 4299 | def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4300 | addr:$dst), |
| 4301 | (implicit EFLAGS)), |
| 4302 | (SUB8mr addr:$dst, GR8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4303 | def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4304 | addr:$dst), |
| 4305 | (implicit EFLAGS)), |
| 4306 | (SUB16mr addr:$dst, GR16:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4307 | def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4308 | addr:$dst), |
| 4309 | (implicit EFLAGS)), |
| 4310 | (SUB32mr addr:$dst, GR32:$src2)>; |
| 4311 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4312 | // Memory-Integer Subtraction with EFLAGS result |
| 4313 | def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4314 | addr:$dst), |
| 4315 | (implicit EFLAGS)), |
| 4316 | (SUB8mi addr:$dst, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4317 | def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4318 | addr:$dst), |
| 4319 | (implicit EFLAGS)), |
| 4320 | (SUB16mi addr:$dst, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4321 | def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4322 | addr:$dst), |
| 4323 | (implicit EFLAGS)), |
| 4324 | (SUB32mi addr:$dst, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4325 | def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4326 | addr:$dst), |
| 4327 | (implicit EFLAGS)), |
| 4328 | (SUB16mi8 addr:$dst, i16immSExt8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4329 | def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4330 | addr:$dst), |
| 4331 | (implicit EFLAGS)), |
| 4332 | (SUB32mi8 addr:$dst, i32immSExt8:$src2)>; |
| 4333 | |
| 4334 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4335 | // Register-Register Signed Integer Multiply with EFLAGS result |
| 4336 | def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4337 | (implicit EFLAGS)), |
| 4338 | (IMUL16rr GR16:$src1, GR16:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4339 | def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4340 | (implicit EFLAGS)), |
| 4341 | (IMUL32rr GR32:$src1, GR32:$src2)>; |
| 4342 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4343 | // Register-Memory Signed Integer Multiply with EFLAGS result |
| 4344 | def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4345 | (implicit EFLAGS)), |
| 4346 | (IMUL16rm GR16:$src1, addr:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4347 | def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4348 | (implicit EFLAGS)), |
| 4349 | (IMUL32rm GR32:$src1, addr:$src2)>; |
| 4350 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4351 | // Register-Integer Signed Integer Multiply with EFLAGS result |
| 4352 | def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4353 | (implicit EFLAGS)), |
| 4354 | (IMUL16rri GR16:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4355 | def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4356 | (implicit EFLAGS)), |
| 4357 | (IMUL32rri GR32:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4358 | def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4359 | (implicit EFLAGS)), |
| 4360 | (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4361 | def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4362 | (implicit EFLAGS)), |
| 4363 | (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>; |
| 4364 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4365 | // Memory-Integer Signed Integer Multiply with EFLAGS result |
| 4366 | def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4367 | (implicit EFLAGS)), |
| 4368 | (IMUL16rmi addr:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4369 | def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4370 | (implicit EFLAGS)), |
| 4371 | (IMUL32rmi addr:$src1, imm:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4372 | def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4373 | (implicit EFLAGS)), |
| 4374 | (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4375 | def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4376 | (implicit EFLAGS)), |
| 4377 | (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>; |
| 4378 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4379 | // Optimize multiply by 2 with EFLAGS result. |
Evan Cheng | 6a86bd7 | 2009-01-27 03:30:42 +0000 | [diff] [blame] | 4380 | let AddedComplexity = 2 in { |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4381 | def : Pat<(parallel (X86smul_flag GR16:$src1, 2), |
Evan Cheng | 6a86bd7 | 2009-01-27 03:30:42 +0000 | [diff] [blame] | 4382 | (implicit EFLAGS)), |
| 4383 | (ADD16rr GR16:$src1, GR16:$src1)>; |
| 4384 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4385 | def : Pat<(parallel (X86smul_flag GR32:$src1, 2), |
Evan Cheng | 6a86bd7 | 2009-01-27 03:30:42 +0000 | [diff] [blame] | 4386 | (implicit EFLAGS)), |
| 4387 | (ADD32rr GR32:$src1, GR32:$src1)>; |
| 4388 | } |
| 4389 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4390 | // INC and DEC with EFLAGS result. Note that these do not set CF. |
| 4391 | def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)), |
| 4392 | (INC8r GR8:$src)>; |
| 4393 | def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst), |
| 4394 | (implicit EFLAGS)), |
| 4395 | (INC8m addr:$dst)>; |
| 4396 | def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)), |
| 4397 | (DEC8r GR8:$src)>; |
| 4398 | def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst), |
| 4399 | (implicit EFLAGS)), |
| 4400 | (DEC8m addr:$dst)>; |
| 4401 | |
| 4402 | def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 4403 | (INC16r GR16:$src)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4404 | def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst), |
| 4405 | (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 4406 | (INC16m addr:$dst)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4407 | def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 4408 | (DEC16r GR16:$src)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4409 | def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst), |
| 4410 | (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 4411 | (DEC16m addr:$dst)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4412 | |
| 4413 | def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 4414 | (INC32r GR32:$src)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4415 | def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst), |
| 4416 | (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 4417 | (INC32m addr:$dst)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4418 | def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 4419 | (DEC32r GR32:$src)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4420 | def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst), |
| 4421 | (implicit EFLAGS)), |
Dan Gohman | 1f4af26 | 2009-03-05 21:32:23 +0000 | [diff] [blame] | 4422 | (DEC32m addr:$dst)>, Requires<[In32BitMode]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 4423 | |
Dan Gohman | e220c4b | 2009-09-18 19:59:53 +0000 | [diff] [blame] | 4424 | // Register-Register Or with EFLAGS result |
| 4425 | def : Pat<(parallel (X86or_flag GR8:$src1, GR8:$src2), |
| 4426 | (implicit EFLAGS)), |
| 4427 | (OR8rr GR8:$src1, GR8:$src2)>; |
| 4428 | def : Pat<(parallel (X86or_flag GR16:$src1, GR16:$src2), |
| 4429 | (implicit EFLAGS)), |
| 4430 | (OR16rr GR16:$src1, GR16:$src2)>; |
| 4431 | def : Pat<(parallel (X86or_flag GR32:$src1, GR32:$src2), |
| 4432 | (implicit EFLAGS)), |
| 4433 | (OR32rr GR32:$src1, GR32:$src2)>; |
| 4434 | |
| 4435 | // Register-Memory Or with EFLAGS result |
| 4436 | def : Pat<(parallel (X86or_flag GR8:$src1, (loadi8 addr:$src2)), |
| 4437 | (implicit EFLAGS)), |
| 4438 | (OR8rm GR8:$src1, addr:$src2)>; |
| 4439 | def : Pat<(parallel (X86or_flag GR16:$src1, (loadi16 addr:$src2)), |
| 4440 | (implicit EFLAGS)), |
| 4441 | (OR16rm GR16:$src1, addr:$src2)>; |
| 4442 | def : Pat<(parallel (X86or_flag GR32:$src1, (loadi32 addr:$src2)), |
| 4443 | (implicit EFLAGS)), |
| 4444 | (OR32rm GR32:$src1, addr:$src2)>; |
| 4445 | |
| 4446 | // Register-Integer Or with EFLAGS result |
| 4447 | def : Pat<(parallel (X86or_flag GR8:$src1, imm:$src2), |
| 4448 | (implicit EFLAGS)), |
| 4449 | (OR8ri GR8:$src1, imm:$src2)>; |
| 4450 | def : Pat<(parallel (X86or_flag GR16:$src1, imm:$src2), |
| 4451 | (implicit EFLAGS)), |
| 4452 | (OR16ri GR16:$src1, imm:$src2)>; |
| 4453 | def : Pat<(parallel (X86or_flag GR32:$src1, imm:$src2), |
| 4454 | (implicit EFLAGS)), |
| 4455 | (OR32ri GR32:$src1, imm:$src2)>; |
| 4456 | def : Pat<(parallel (X86or_flag GR16:$src1, i16immSExt8:$src2), |
| 4457 | (implicit EFLAGS)), |
| 4458 | (OR16ri8 GR16:$src1, i16immSExt8:$src2)>; |
| 4459 | def : Pat<(parallel (X86or_flag GR32:$src1, i32immSExt8:$src2), |
| 4460 | (implicit EFLAGS)), |
| 4461 | (OR32ri8 GR32:$src1, i32immSExt8:$src2)>; |
| 4462 | |
| 4463 | // Memory-Register Or with EFLAGS result |
| 4464 | def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), GR8:$src2), |
| 4465 | addr:$dst), |
| 4466 | (implicit EFLAGS)), |
| 4467 | (OR8mr addr:$dst, GR8:$src2)>; |
| 4468 | def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), GR16:$src2), |
| 4469 | addr:$dst), |
| 4470 | (implicit EFLAGS)), |
| 4471 | (OR16mr addr:$dst, GR16:$src2)>; |
| 4472 | def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), GR32:$src2), |
| 4473 | addr:$dst), |
| 4474 | (implicit EFLAGS)), |
| 4475 | (OR32mr addr:$dst, GR32:$src2)>; |
| 4476 | |
| 4477 | // Memory-Integer Or with EFLAGS result |
| 4478 | def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), imm:$src2), |
| 4479 | addr:$dst), |
| 4480 | (implicit EFLAGS)), |
| 4481 | (OR8mi addr:$dst, imm:$src2)>; |
| 4482 | def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), imm:$src2), |
| 4483 | addr:$dst), |
| 4484 | (implicit EFLAGS)), |
| 4485 | (OR16mi addr:$dst, imm:$src2)>; |
| 4486 | def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), imm:$src2), |
| 4487 | addr:$dst), |
| 4488 | (implicit EFLAGS)), |
| 4489 | (OR32mi addr:$dst, imm:$src2)>; |
| 4490 | def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), i16immSExt8:$src2), |
| 4491 | addr:$dst), |
| 4492 | (implicit EFLAGS)), |
| 4493 | (OR16mi8 addr:$dst, i16immSExt8:$src2)>; |
| 4494 | def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), i32immSExt8:$src2), |
| 4495 | addr:$dst), |
| 4496 | (implicit EFLAGS)), |
| 4497 | (OR32mi8 addr:$dst, i32immSExt8:$src2)>; |
| 4498 | |
| 4499 | // Register-Register XOr with EFLAGS result |
| 4500 | def : Pat<(parallel (X86xor_flag GR8:$src1, GR8:$src2), |
| 4501 | (implicit EFLAGS)), |
| 4502 | (XOR8rr GR8:$src1, GR8:$src2)>; |
| 4503 | def : Pat<(parallel (X86xor_flag GR16:$src1, GR16:$src2), |
| 4504 | (implicit EFLAGS)), |
| 4505 | (XOR16rr GR16:$src1, GR16:$src2)>; |
| 4506 | def : Pat<(parallel (X86xor_flag GR32:$src1, GR32:$src2), |
| 4507 | (implicit EFLAGS)), |
| 4508 | (XOR32rr GR32:$src1, GR32:$src2)>; |
| 4509 | |
| 4510 | // Register-Memory XOr with EFLAGS result |
| 4511 | def : Pat<(parallel (X86xor_flag GR8:$src1, (loadi8 addr:$src2)), |
| 4512 | (implicit EFLAGS)), |
| 4513 | (XOR8rm GR8:$src1, addr:$src2)>; |
| 4514 | def : Pat<(parallel (X86xor_flag GR16:$src1, (loadi16 addr:$src2)), |
| 4515 | (implicit EFLAGS)), |
| 4516 | (XOR16rm GR16:$src1, addr:$src2)>; |
| 4517 | def : Pat<(parallel (X86xor_flag GR32:$src1, (loadi32 addr:$src2)), |
| 4518 | (implicit EFLAGS)), |
| 4519 | (XOR32rm GR32:$src1, addr:$src2)>; |
| 4520 | |
| 4521 | // Register-Integer XOr with EFLAGS result |
| 4522 | def : Pat<(parallel (X86xor_flag GR8:$src1, imm:$src2), |
| 4523 | (implicit EFLAGS)), |
| 4524 | (XOR8ri GR8:$src1, imm:$src2)>; |
| 4525 | def : Pat<(parallel (X86xor_flag GR16:$src1, imm:$src2), |
| 4526 | (implicit EFLAGS)), |
| 4527 | (XOR16ri GR16:$src1, imm:$src2)>; |
| 4528 | def : Pat<(parallel (X86xor_flag GR32:$src1, imm:$src2), |
| 4529 | (implicit EFLAGS)), |
| 4530 | (XOR32ri GR32:$src1, imm:$src2)>; |
| 4531 | def : Pat<(parallel (X86xor_flag GR16:$src1, i16immSExt8:$src2), |
| 4532 | (implicit EFLAGS)), |
| 4533 | (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>; |
| 4534 | def : Pat<(parallel (X86xor_flag GR32:$src1, i32immSExt8:$src2), |
| 4535 | (implicit EFLAGS)), |
| 4536 | (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; |
| 4537 | |
| 4538 | // Memory-Register XOr with EFLAGS result |
| 4539 | def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), GR8:$src2), |
| 4540 | addr:$dst), |
| 4541 | (implicit EFLAGS)), |
| 4542 | (XOR8mr addr:$dst, GR8:$src2)>; |
| 4543 | def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), GR16:$src2), |
| 4544 | addr:$dst), |
| 4545 | (implicit EFLAGS)), |
| 4546 | (XOR16mr addr:$dst, GR16:$src2)>; |
| 4547 | def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), GR32:$src2), |
| 4548 | addr:$dst), |
| 4549 | (implicit EFLAGS)), |
| 4550 | (XOR32mr addr:$dst, GR32:$src2)>; |
| 4551 | |
| 4552 | // Memory-Integer XOr with EFLAGS result |
| 4553 | def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), imm:$src2), |
| 4554 | addr:$dst), |
| 4555 | (implicit EFLAGS)), |
| 4556 | (XOR8mi addr:$dst, imm:$src2)>; |
| 4557 | def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), imm:$src2), |
| 4558 | addr:$dst), |
| 4559 | (implicit EFLAGS)), |
| 4560 | (XOR16mi addr:$dst, imm:$src2)>; |
| 4561 | def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), imm:$src2), |
| 4562 | addr:$dst), |
| 4563 | (implicit EFLAGS)), |
| 4564 | (XOR32mi addr:$dst, imm:$src2)>; |
| 4565 | def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), i16immSExt8:$src2), |
| 4566 | addr:$dst), |
| 4567 | (implicit EFLAGS)), |
| 4568 | (XOR16mi8 addr:$dst, i16immSExt8:$src2)>; |
| 4569 | def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), i32immSExt8:$src2), |
| 4570 | addr:$dst), |
| 4571 | (implicit EFLAGS)), |
| 4572 | (XOR32mi8 addr:$dst, i32immSExt8:$src2)>; |
| 4573 | |
| 4574 | // Register-Register And with EFLAGS result |
| 4575 | def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2), |
| 4576 | (implicit EFLAGS)), |
| 4577 | (AND8rr GR8:$src1, GR8:$src2)>; |
| 4578 | def : Pat<(parallel (X86and_flag GR16:$src1, GR16:$src2), |
| 4579 | (implicit EFLAGS)), |
| 4580 | (AND16rr GR16:$src1, GR16:$src2)>; |
| 4581 | def : Pat<(parallel (X86and_flag GR32:$src1, GR32:$src2), |
| 4582 | (implicit EFLAGS)), |
| 4583 | (AND32rr GR32:$src1, GR32:$src2)>; |
| 4584 | |
| 4585 | // Register-Memory And with EFLAGS result |
| 4586 | def : Pat<(parallel (X86and_flag GR8:$src1, (loadi8 addr:$src2)), |
| 4587 | (implicit EFLAGS)), |
| 4588 | (AND8rm GR8:$src1, addr:$src2)>; |
| 4589 | def : Pat<(parallel (X86and_flag GR16:$src1, (loadi16 addr:$src2)), |
| 4590 | (implicit EFLAGS)), |
| 4591 | (AND16rm GR16:$src1, addr:$src2)>; |
| 4592 | def : Pat<(parallel (X86and_flag GR32:$src1, (loadi32 addr:$src2)), |
| 4593 | (implicit EFLAGS)), |
| 4594 | (AND32rm GR32:$src1, addr:$src2)>; |
| 4595 | |
| 4596 | // Register-Integer And with EFLAGS result |
| 4597 | def : Pat<(parallel (X86and_flag GR8:$src1, imm:$src2), |
| 4598 | (implicit EFLAGS)), |
| 4599 | (AND8ri GR8:$src1, imm:$src2)>; |
| 4600 | def : Pat<(parallel (X86and_flag GR16:$src1, imm:$src2), |
| 4601 | (implicit EFLAGS)), |
| 4602 | (AND16ri GR16:$src1, imm:$src2)>; |
| 4603 | def : Pat<(parallel (X86and_flag GR32:$src1, imm:$src2), |
| 4604 | (implicit EFLAGS)), |
| 4605 | (AND32ri GR32:$src1, imm:$src2)>; |
| 4606 | def : Pat<(parallel (X86and_flag GR16:$src1, i16immSExt8:$src2), |
| 4607 | (implicit EFLAGS)), |
| 4608 | (AND16ri8 GR16:$src1, i16immSExt8:$src2)>; |
| 4609 | def : Pat<(parallel (X86and_flag GR32:$src1, i32immSExt8:$src2), |
| 4610 | (implicit EFLAGS)), |
| 4611 | (AND32ri8 GR32:$src1, i32immSExt8:$src2)>; |
| 4612 | |
| 4613 | // Memory-Register And with EFLAGS result |
| 4614 | def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), GR8:$src2), |
| 4615 | addr:$dst), |
| 4616 | (implicit EFLAGS)), |
| 4617 | (AND8mr addr:$dst, GR8:$src2)>; |
| 4618 | def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), GR16:$src2), |
| 4619 | addr:$dst), |
| 4620 | (implicit EFLAGS)), |
| 4621 | (AND16mr addr:$dst, GR16:$src2)>; |
| 4622 | def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), GR32:$src2), |
| 4623 | addr:$dst), |
| 4624 | (implicit EFLAGS)), |
| 4625 | (AND32mr addr:$dst, GR32:$src2)>; |
| 4626 | |
| 4627 | // Memory-Integer And with EFLAGS result |
| 4628 | def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), imm:$src2), |
| 4629 | addr:$dst), |
| 4630 | (implicit EFLAGS)), |
| 4631 | (AND8mi addr:$dst, imm:$src2)>; |
| 4632 | def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), imm:$src2), |
| 4633 | addr:$dst), |
| 4634 | (implicit EFLAGS)), |
| 4635 | (AND16mi addr:$dst, imm:$src2)>; |
| 4636 | def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), imm:$src2), |
| 4637 | addr:$dst), |
| 4638 | (implicit EFLAGS)), |
| 4639 | (AND32mi addr:$dst, imm:$src2)>; |
| 4640 | def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), i16immSExt8:$src2), |
| 4641 | addr:$dst), |
| 4642 | (implicit EFLAGS)), |
| 4643 | (AND16mi8 addr:$dst, i16immSExt8:$src2)>; |
| 4644 | def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), i32immSExt8:$src2), |
| 4645 | addr:$dst), |
| 4646 | (implicit EFLAGS)), |
| 4647 | (AND32mi8 addr:$dst, i32immSExt8:$src2)>; |
| 4648 | |
Dan Gohman | 2f67df7 | 2009-09-03 17:18:51 +0000 | [diff] [blame] | 4649 | // -disable-16bit support. |
| 4650 | def : Pat<(truncstorei16 (i32 imm:$src), addr:$dst), |
| 4651 | (MOV16mi addr:$dst, imm:$src)>; |
| 4652 | def : Pat<(truncstorei16 GR32:$src, addr:$dst), |
| 4653 | (MOV16mr addr:$dst, (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>; |
| 4654 | def : Pat<(i32 (sextloadi16 addr:$dst)), |
| 4655 | (MOVSX32rm16 addr:$dst)>; |
| 4656 | def : Pat<(i32 (zextloadi16 addr:$dst)), |
| 4657 | (MOVZX32rm16 addr:$dst)>; |
| 4658 | def : Pat<(i32 (extloadi16 addr:$dst)), |
| 4659 | (MOVZX32rm16 addr:$dst)>; |
| 4660 | |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 4661 | //===----------------------------------------------------------------------===// |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 4662 | // Floating Point Stack Support |
| 4663 | //===----------------------------------------------------------------------===// |
| 4664 | |
| 4665 | include "X86InstrFPStack.td" |
| 4666 | |
| 4667 | //===----------------------------------------------------------------------===// |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 4668 | // X86-64 Support |
| 4669 | //===----------------------------------------------------------------------===// |
| 4670 | |
Chris Lattner | 36fe6d2 | 2008-01-10 05:50:42 +0000 | [diff] [blame] | 4671 | include "X86Instr64bit.td" |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 4672 | |
| 4673 | //===----------------------------------------------------------------------===// |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 4674 | // XMM Floating point support (requires SSE / SSE2) |
| 4675 | //===----------------------------------------------------------------------===// |
| 4676 | |
| 4677 | include "X86InstrSSE.td" |
Evan Cheng | 80f5404 | 2008-04-25 18:19:54 +0000 | [diff] [blame] | 4678 | |
| 4679 | //===----------------------------------------------------------------------===// |
| 4680 | // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2) |
| 4681 | //===----------------------------------------------------------------------===// |
| 4682 | |
| 4683 | include "X86InstrMMX.td" |