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gerrit-public.fairphone.software / kernel / lk / 38a86bca3ac4e6c8db57c10a0d53650170f46dc6 / . / platform / msm8952 / include / platform / iomap.h
blob: 6f4b28f1914b513018f5129b4f93b5d87be5e43d [file] [log] [blame]
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]1/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef _PLATFORM_MSM8952_IOMAP_H_
30#define _PLATFORM_MSM8952_IOMAP_H_
31
32#define MSM_IOMAP_BASE 0x00000000
33#define MSM_IOMAP_END 0x08000000
34
35#define SDRAM_START_ADDR 0x80000000
36
Aparna Mallavarapue9bdacd2015-03-15 14:24:21 +0530[diff] [blame]37#define DDR_START get_ddr_start()
38#define ABOOT_FORCE_KERNEL_ADDR DDR_START + 0x8000
39#define ABOOT_FORCE_KERNEL64_ADDR DDR_START + 0x80000
Parth Dixit14946f02015-12-03 18:32:06 +0530[diff] [blame]40#define ABOOT_FORCE_TAGS_ADDR DDR_START + 0x3400000
41#define ABOOT_FORCE_RAMDISK_ADDR DDR_START + 0x3600000
Aparna Mallavarapue9bdacd2015-03-15 14:24:21 +0530[diff] [blame]42
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]43#define MSM_SHARED_BASE 0x86300000
44#define MSM_SHARED_IMEM_BASE 0x08600000
45
46#define BS_INFO_OFFSET (0x6B0)
47#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
48
49#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
50
51#define APPS_SS_BASE 0x0B000000
Aparna Mallavarapue9bdacd2015-03-15 14:24:21 +0530[diff] [blame]52#define APPS_SS_END 0x0B200000
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]53
54#define MSM_GIC_DIST_BASE APPS_SS_BASE
55#define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000)
56#define APPS_APCS_QTMR_AC_BASE (APPS_SS_BASE + 0x00020000)
57#define APPS_APCS_F0_QTMR_V1_BASE (APPS_SS_BASE + 0x00021000)
58#define QTMR_BASE APPS_APCS_F0_QTMR_V1_BASE
Parth Dixit75dc1292016-01-12 14:44:40 +0530[diff] [blame]59#define APCS_ALIAS1_IPC_INTERRUPT_1 (APPS_SS_BASE + 0x00011008)
60#define APCS_ALIAS0_IPC_INTERRUPT_2 (APPS_SS_BASE + 0x00111008)
61#define APCS_ALIAS0_IPC_INTERRUPT platform_get_apcs_ipc_base()
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]62
63#define PERIPH_SS_BASE 0x07800000
64
65#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000)
66#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x00064000)
67
Aparna Mallavarapu7b638e62015-03-26 05:51:57 +0530[diff] [blame]68/* UART */
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]69#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x000AF000)
70#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x000B0000)
71#define MSM_USB_BASE (PERIPH_SS_BASE + 0x000DB000)
72
73#define CLK_CTL_BASE 0x1800000
74
c_wufeng78f7a5f2015-09-21 13:02:06 +0800[diff] [blame]75#define PMI_SLAVE_BASE 2
76#define PMI_FIRST_SLAVE_OFFSET 0
77#define PMI_SECOND_SLAVE_OFFSET 1
78
79#define PMI_FIRST_SLAVE_ADDR_BASE (( PMI_SLAVE_BASE + PMI_FIRST_SLAVE_OFFSET ) << 16)
80#define PMI_SECOND_SLAVE_ADDR_BASE (( PMI_SLAVE_BASE + PMI_SECOND_SLAVE_OFFSET) << 16)
Matthew Qin7afa8492015-06-26 17:05:18 +0800[diff] [blame]81
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]82#define SPMI_BASE 0x02000000
83#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
84#define SPMI_PIC_BASE (SPMI_BASE + 0x01800000)
85#define PMIC_ARB_CORE 0x200F000
86
87#define TLMM_BASE_ADDR 0x1000000
88#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000)
89#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x00000004 + (x)*0x1000)
90
91#define MPM2_MPM_CTRL_BASE 0x004A0000
92#define MPM2_MPM_PS_HOLD 0x004AB000
93#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x004A3000
94
95/* CRYPTO ENGINE */
96#define MSM_CE1_BASE 0x073A000
97#define MSM_CE1_BAM_BASE 0x0704000
Aparna Mallavarapu7b638e62015-03-26 05:51:57 +0530[diff] [blame]98#define GCC_CRYPTO_BCR (CLK_CTL_BASE + 0x16000)
99#define GCC_CRYPTO_CMD_RCGR (CLK_CTL_BASE + 0x16004)
100#define GCC_CRYPTO_CFG_RCGR (CLK_CTL_BASE + 0x16008)
101#define GCC_CRYPTO_CBCR (CLK_CTL_BASE + 0x1601C)
102#define GCC_CRYPTO_AXI_CBCR (CLK_CTL_BASE + 0x16020)
103#define GCC_CRYPTO_AHB_CBCR (CLK_CTL_BASE + 0x16024)
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]104
105/* GPLL */
106#define GPLL0_STATUS (CLK_CTL_BASE + 0x2101C)
vijay kumara0a74722015-09-04 15:45:49 +0530[diff] [blame]107#define GPLL2_STATUS (CLK_CTL_BASE + 0x4A01C)
Parth Dixit5817c022015-11-07 16:23:57 +0530[diff] [blame]108#define GPLL0_MODE (CLK_CTL_BASE + 0x21000)
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]109#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000)
110#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004)
Aparna Mallavarapu7b638e62015-03-26 05:51:57 +0530[diff] [blame]111#define GPLL4_MODE (CLK_CTL_BASE + 0x24000)
Unnati Gandhi81b77062015-05-28 14:23:39 +0530[diff] [blame]112#define GPLL4_STATUS (CLK_CTL_BASE + 0x24024)
Padmanabhan Komanduru2655ea62015-06-08 12:23:32 +0530[diff] [blame]113#define GPLL6_STATUS (CLK_CTL_BASE + 0x3701C)
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]114
115/* SDCC */
116#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x10A000)
117#define SDCC1_BCR (CLK_CTL_BASE + 0x42000) /* block reset*/
118#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x42018) /* branch ontrol */
119#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4201C)
120#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x42004) /* cmd */
121#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x42008) /* cfg */
122#define SDCC1_M (CLK_CTL_BASE + 0x4200C) /* m */
123#define SDCC1_N (CLK_CTL_BASE + 0x42010) /* n */
124#define SDCC1_D (CLK_CTL_BASE + 0x42014) /* d */
125
Aparna Mallavarapu7b638e62015-03-26 05:51:57 +0530[diff] [blame]126/* SDHCI */
127#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900)
128#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900)
129
130#define SDCC_MCI_HC_MODE (0x00000078)
131#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
132#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
133#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
134#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
135
136#define SDCC2_BCR (CLK_CTL_BASE + 0x43000) /* block reset */
137#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x43018) /* branch control */
138#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x4301C)
139#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x43004) /* cmd */
140#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x43008) /* cfg */
141#define SDCC2_M (CLK_CTL_BASE + 0x4300C) /* m */
142#define SDCC2_N (CLK_CTL_BASE + 0x43010) /* n */
143#define SDCC2_D (CLK_CTL_BASE + 0x43014) /* d */
144
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]145/* UART */
146#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x1008)
147#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x302C)
148#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x3034)
149#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x3038)
150#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x303C)
151#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x3040)
152#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x3044)
153
154/* USB */
155#define USB_HS_BCR (CLK_CTL_BASE + 0x41000)
156#define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x41004)
157#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x41008)
158#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x41010)
159#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x41014)
160
Parth Dixit23d23442015-07-30 18:47:38 +0530[diff] [blame]161
162/* RPMB send receive buffer needs to be mapped
163 * as device memory, define the start address
164 * and size in MB
165 */
Parth Dixit80b58442016-05-17 10:54:09 +0530[diff] [blame]166#define RPMB_SND_RCV_BUF 0xA0000000
Parth Dixit70623202016-12-21 15:45:27 +0530[diff] [blame]167#define RPMB_SND_RCV_BUF_512 0x9FE00000
Parth Dixit23d23442015-07-30 18:47:38 +0530[diff] [blame]168#define RPMB_SND_RCV_BUF_SZ 0x1
169
170/* QSEECOM: Secure app region notification */
Parth Dixit4734bd62016-01-13 11:06:28 +0530[diff] [blame]171#define APP_REGION_ADDR platform_get_tz_app_add()
172#define APP_REGION_SIZE platform_get_tz_app_size()
173#define APP_REGION_ADDR_8952 0x85E00000
174#define APP_REGION_SIZE_8952 0x500000
175#define APP_REGION_ADDR_8937 0x85B00000
176#define APP_REGION_SIZE_8937 0x800000
Parth Dixit23d23442015-07-30 18:47:38 +0530[diff] [blame]177
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]178/* MDSS */
179#define MIPI_DSI_BASE (0x1A98000)
180#define MIPI_DSI0_BASE MIPI_DSI_BASE
Padmanabhan Komanduru6cabd5a2015-06-08 14:13:04 +0530[diff] [blame]181#define MIPI_DSI1_BASE (0x1A96000)
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]182#define DSI0_PHY_BASE (0x1A98500)
Padmanabhan Komanduru6cabd5a2015-06-08 14:13:04 +0530[diff] [blame]183#define DSI1_PHY_BASE (0x1A96400)
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]184#define DSI0_PLL_BASE (0x1A98300)
Padmanabhan Komanduru6cabd5a2015-06-08 14:13:04 +0530[diff] [blame]185#define DSI1_PLL_BASE (0x1A96A00)
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]186#define DSI0_REGULATOR_BASE (0x1A98780)
187#define DSI1_REGULATOR_BASE DSI0_REGULATOR_BASE
188#define MDP_BASE (0x1A00000)
189#define REG_MDP(off) (MDP_BASE + (off))
190
191#ifdef MDP_HW_REV
192#undef MDP_HW_REV
193#endif
194#define MDP_HW_REV REG_MDP(0x1000)
195
196#ifdef MDP_INTR_EN
197#undef MDP_INTR_EN
198#endif
199#define MDP_INTR_EN REG_MDP(0x1010)
200
201#ifdef MDP_INTR_CLEAR
202#undef MDP_INTR_CLEAR
203#endif
204#define MDP_INTR_CLEAR REG_MDP(0x1018)
205
206#ifdef MDP_HIST_INTR_EN
207#undef MDP_HIST_INTR_EN
208#endif
209#define MDP_HIST_INTR_EN REG_MDP(0x101C)
210
211#ifdef MDP_VP_0_VIG_0_BASE
212#undef MDP_VP_0_VIG_0_BASE
213#endif
214#define MDP_VP_0_VIG_0_BASE REG_MDP(0x5000)
215
216#ifdef MDP_VP_0_VIG_1_BASE
217#undef MDP_VP_0_VIG_1_BASE
218#endif
219#define MDP_VP_0_VIG_1_BASE REG_MDP(0x7000)
220
221#ifdef MDP_VP_0_RGB_0_BASE
222#undef MDP_VP_0_RGB_0_BASE
223#endif
224#define MDP_VP_0_RGB_0_BASE REG_MDP(0x15000)
225
226#ifdef MDP_VP_0_RGB_1_BASE
227#undef MDP_VP_0_RGB_1_BASE
228#endif
229#define MDP_VP_0_RGB_1_BASE REG_MDP(0x17000)
230
231#ifdef MDP_VP_0_DMA_0_BASE
232#undef MDP_VP_0_DMA_0_BASE
233#endif
234#define MDP_VP_0_DMA_0_BASE REG_MDP(0x25000)
235
236#ifdef MDP_VP_0_DMA_1_BASE
237#undef MDP_VP_0_DMA_1_BASE
238#endif
239#define MDP_VP_0_DMA_1_BASE REG_MDP(0x27000)
240
241#ifdef MDP_VP_0_MIXER_0_BASE
242#undef MDP_VP_0_MIXER_0_BASE
243#endif
244#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x45000)
245
246#ifdef MDP_VP_0_MIXER_1_BASE
247#undef MDP_VP_0_MIXER_1_BASE
248#endif
249#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x46000)
250
251#ifdef MDP_DISP_INTF_SEL
252#undef MDP_DISP_INTF_SEL
253#endif
254#define MDP_DISP_INTF_SEL REG_MDP(0x1004)
255
256#ifdef MDP_VIDEO_INTF_UNDERFLOW_CTL
257#undef MDP_VIDEO_INTF_UNDERFLOW_CTL
258#endif
259#define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x12E0)
260
261#ifdef MDP_UPPER_NEW_ROI_PRIOR_RO_START
262#undef MDP_UPPER_NEW_ROI_PRIOR_RO_START
263#endif
264#define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x11EC)
265
266#ifdef MDP_LOWER_NEW_ROI_PRIOR_TO_START
267#undef MDP_LOWER_NEW_ROI_PRIOR_TO_START
268#endif
269#define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x13F8)
270
271#ifdef MDP_CTL_0_BASE
272#undef MDP_CTL_0_BASE
273#endif
274#define MDP_CTL_0_BASE REG_MDP(0x2000)
275
276#ifdef MDP_CTL_1_BASE
277#undef MDP_CTL_1_BASE
278#endif
279#define MDP_CTL_1_BASE REG_MDP(0x2200)
280
281#ifdef MDP_CLK_CTRL0
282#undef MDP_CLK_CTRL0
283#endif
284#define MDP_CLK_CTRL0 REG_MDP(0x012AC)
285
286#ifdef MDP_CLK_CTRL1
287#undef MDP_CLK_CTRL1
288#endif
289#define MDP_CLK_CTRL1 REG_MDP(0x012B4)
290
291#ifdef MDP_CLK_CTRL2
292#undef MDP_CLK_CTRL2
293#endif
294#define MDP_CLK_CTRL2 REG_MDP(0x012BC)
295
296#ifdef MDP_CLK_CTRL3
297#undef MDP_CLK_CTRL3
298#endif
299#define MDP_CLK_CTRL3 REG_MDP(0x013A8)
300
301#ifdef MDP_CLK_CTRL4
302#undef MDP_CLK_CTRL4
303#endif
304#define MDP_CLK_CTRL4 REG_MDP(0x013B0)
305
306#ifdef MDP_CLK_CTRL5
307#undef MDP_CLK_CTRL5
308#endif
309#define MDP_CLK_CTRL5 REG_MDP(0x013B8)
310
311#ifdef MDP_INTF_1_BASE
312#undef MDP_INTF_1_BASE
313#endif
314#define MDP_INTF_1_BASE REG_MDP(0x12700)
315
Padmanabhan Komanduruf912cfb2015-06-08 16:36:58 +0530[diff] [blame]316#ifdef MDP_INTF_2_BASE
317#undef MDP_INTF_2_BASE
318#endif
319#define MDP_INTF_2_BASE REG_MDP(0x12F00)
320
321#ifdef MDP_REG_SPLIT_DISPLAY_EN
322#undef MDP_REG_SPLIT_DISPLAY_EN
323#endif
324#define MDP_REG_SPLIT_DISPLAY_EN REG_MDP(0x12F4)
325
326#ifdef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
327#undef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
328#endif
329#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x12F8)
330
331#ifdef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
332#undef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
333#endif
334#define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL REG_MDP(0x13F0)
335
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]336#ifdef MMSS_MDP_SMP_ALLOC_W_BASE
337#undef MMSS_MDP_SMP_ALLOC_W_BASE
338#endif
339#define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x1080)
340
341#ifdef MMSS_MDP_SMP_ALLOC_R_BASE
342#undef MMSS_MDP_SMP_ALLOC_R_BASE
343#endif
344#define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x1130)
345
346#ifdef MDP_QOS_REMAPPER_CLASS_0
347#undef MDP_QOS_REMAPPER_CLASS_0
348#endif
349#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x11E0)
350
351#ifdef VBIF_VBIF_DDR_FORCE_CLK_ON
352#undef VBIF_VBIF_DDR_FORCE_CLK_ON
353#endif
354#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0xc8004)
355
356#ifdef VBIF_VBIF_DDR_OUT_MAX_BURST
357#undef VBIF_VBIF_DDR_OUT_MAX_BURST
358#endif
359#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0xc80D8)
360
361#ifdef VBIF_VBIF_DDR_ARB_CTRL
362#undef VBIF_VBIF_DDR_ARB_CTRL
363#endif
364#define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0xc80F0)
365
366#ifdef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
367#undef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
368#endif
369#define VBIF_VBIF_DDR_RND_RBN_QOS_ARB REG_MDP(0xc8124)
370
371#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
372#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
373#endif
374#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0 REG_MDP(0xc8160)
375
376#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
377#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
378#endif
379#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1 REG_MDP(0xc8164)
380
381#ifdef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
382#undef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
383#endif
384#define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN REG_MDP(0xc8178)
385
386#ifdef VBIF_VBIF_DDR_OUT_AX_AOOO
387#undef VBIF_VBIF_DDR_OUT_AX_AOOO
388#endif
389#define VBIF_VBIF_DDR_OUT_AX_AOOO REG_MDP(0xc817C)
390
391#ifdef VBIF_VBIF_IN_RD_LIM_CONF0
392#undef VBIF_VBIF_IN_RD_LIM_CONF0
393#endif
394#define VBIF_VBIF_IN_RD_LIM_CONF0 REG_MDP(0xc80B0)
395
396#ifdef VBIF_VBIF_IN_RD_LIM_CONF1
397#undef VBIF_VBIF_IN_RD_LIM_CONF1
398#endif
399#define VBIF_VBIF_IN_RD_LIM_CONF1 REG_MDP(0xc80B4)
400
401#ifdef VBIF_VBIF_IN_WR_LIM_CONF0
402#undef VBIF_VBIF_IN_WR_LIM_CONF0
403#endif
404#define VBIF_VBIF_IN_WR_LIM_CONF0 REG_MDP(0xc80C0)
405
406#ifdef VBIF_VBIF_IN_WR_LIM_CONF1
407#undef VBIF_VBIF_IN_WR_LIM_CONF1
408#endif
409#define VBIF_VBIF_IN_WR_LIM_CONF1 REG_MDP(0xc80C4)
410
Sandeep Pandae0b27712015-07-31 16:41:13 +0530[diff] [blame]411#ifdef MDP_INTF_2_TIMING_ENGINE_EN
412#undef MDP_INTF_2_TIMING_ENGINE_EN
413#endif
414#define MDP_INTF_2_TIMING_ENGINE_EN REG_MDP(0x12F00)
415
416#ifdef MDP_PP_0_BASE
417#undef MDP_PP_0_BASE
418#endif
419#define MDP_PP_0_BASE REG_MDP(0x71000)
420
421#ifdef MDP_PP_1_BASE
422#undef MDP_PP_1_BASE
423#endif
424#define MDP_PP_1_BASE REG_MDP(0x71800)
425
426#ifdef MDSS_MDP_REG_DCE_SEL
427#undef MDSS_MDP_REG_DCE_SEL
428#endif
429#define MDSS_MDP_REG_DCE_SEL REG_MDP(0x1428)
430
431#ifdef MDSS_MDP_PP_DCE_DATA_OUT_SWAP
432#undef MDSS_MDP_PP_DCE_DATA_OUT_SWAP
433#endif
434#define MDSS_MDP_PP_DCE_DATA_OUT_SWAP 0x0CC
435
Ujwal Patel41a665a2015-07-17 13:51:30 -0700[diff] [blame]436#ifdef MDP_DSC_0_BASE
437#undef MDP_DSC_0_BASE
438#endif
439#define MDP_DSC_0_BASE REG_MDP(0x81000)
Sandeep Pandae0b27712015-07-31 16:41:13 +0530[diff] [blame]440
Ujwal Patel41a665a2015-07-17 13:51:30 -0700[diff] [blame]441#ifdef MDP_DSC_1_BASE
442#undef MDP_DSC_1_BASE
443#endif
444#define MDP_DSC_1_BASE REG_MDP(0x81400)
Sandeep Pandae0b27712015-07-31 16:41:13 +0530[diff] [blame]445
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]446#define SOFT_RESET 0x118
447#define CLK_CTRL 0x11C
448#define TRIG_CTRL 0x084
449#define CTRL 0x004
450#define COMMAND_MODE_DMA_CTRL 0x03C
451#define COMMAND_MODE_MDP_CTRL 0x040
452#define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044
453#define COMMAND_MODE_MDP_STREAM0_CTRL 0x058
454#define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C
455#define COMMAND_MODE_MDP_STREAM1_CTRL 0x060
456#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
457#define ERR_INT_MASK0 0x10C
458
459#define LANE_CTL 0x0AC
460#define LANE_SWAP_CTL 0x0B0
461#define TIMING_CTL 0x0C4
462
463#define VIDEO_MODE_ACTIVE_H 0x024
464#define VIDEO_MODE_ACTIVE_V 0x028
465#define VIDEO_MODE_TOTAL 0x02C
466#define VIDEO_MODE_HSYNC 0x030
467#define VIDEO_MODE_VSYNC 0x034
468#define VIDEO_MODE_VSYNC_VPOS 0x038
469
470#define DMA_CMD_OFFSET 0x048
471#define DMA_CMD_LENGTH 0x04C
472
473#define INT_CTRL 0x110
474#define CMD_MODE_DMA_SW_TRIGGER 0x090
475
476#define EOT_PACKET_CTRL 0x0CC
477#define MISR_CMD_CTRL 0x0A0
478#define MISR_VIDEO_CTRL 0x0A4
479#define VIDEO_MODE_CTRL 0x010
480#define HS_TIMER_CTRL 0x0BC
481
Sandeep Pandae0b27712015-07-31 16:41:13 +0530[diff] [blame]482#define VIDEO_COMPRESSION_MODE_CTRL 0x2A0
483#define VIDEO_COMPRESSION_MODE_CTRL_2 0x2A4
484#define CMD_COMPRESSION_MODE_CTRL 0x2A8
485#define CMD_COMPRESSION_MODE_CTRL_2 0x2AC
486#define CMD_COMPRESSION_MODE_CTRL_3 0x2B0
487
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]488#define TCSR_TZ_WONCE 0x193D000
489#define TCSR_BOOT_MISC_DETECT 0x193D100
Aparna Mallavarapu59914502015-06-01 15:31:28 +0530[diff] [blame]490
491#define APPS_WDOG_BARK_VAL_REG 0x0B017010
492#define APPS_WDOG_BITE_VAL_REG 0x0B017014
493#define APPS_WDOG_RESET_REG 0x0B017008
494#define APPS_WDOG_CTL_REG 0x0B017004
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]495#endif