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gerrit-public.fairphone.software / kernel / lk / 44979803f30b1927bcad971a404b15340abeaaad / . / platform / msm8952 / include / platform / iomap.h
blob: 5a92c585a289996171176d007b7e645240d0c098 [file] [log] [blame]
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]1/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef _PLATFORM_MSM8952_IOMAP_H_
30#define _PLATFORM_MSM8952_IOMAP_H_
31
32#define MSM_IOMAP_BASE 0x00000000
33#define MSM_IOMAP_END 0x08000000
34
35#define SDRAM_START_ADDR 0x80000000
36
Aparna Mallavarapue9bdacd2015-03-15 14:24:21 +0530[diff] [blame]37#define DDR_START get_ddr_start()
38#define ABOOT_FORCE_KERNEL_ADDR DDR_START + 0x8000
39#define ABOOT_FORCE_KERNEL64_ADDR DDR_START + 0x80000
40#define ABOOT_FORCE_RAMDISK_ADDR DDR_START + 0x2000000
41#define ABOOT_FORCE_TAGS_ADDR DDR_START + 0x1E00000
42
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]43#define MSM_SHARED_BASE 0x86300000
44#define MSM_SHARED_IMEM_BASE 0x08600000
45
46#define BS_INFO_OFFSET (0x6B0)
47#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
48
49#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
50
51#define APPS_SS_BASE 0x0B000000
Aparna Mallavarapue9bdacd2015-03-15 14:24:21 +0530[diff] [blame]52#define APPS_SS_END 0x0B200000
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]53
54#define MSM_GIC_DIST_BASE APPS_SS_BASE
55#define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000)
56#define APPS_APCS_QTMR_AC_BASE (APPS_SS_BASE + 0x00020000)
57#define APPS_APCS_F0_QTMR_V1_BASE (APPS_SS_BASE + 0x00021000)
58#define QTMR_BASE APPS_APCS_F0_QTMR_V1_BASE
Aparna Mallavarapufa5f8a72015-03-31 06:21:36 +0530[diff] [blame]59#define APCS_ALIAS0_IPC_INTERRUPT (APPS_SS_BASE + 0x00111008)
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]60
61#define PERIPH_SS_BASE 0x07800000
62
63#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000)
64#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x00064000)
65
Aparna Mallavarapu7b638e62015-03-26 05:51:57 +0530[diff] [blame]66/* UART */
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]67#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x000AF000)
68#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x000B0000)
69#define MSM_USB_BASE (PERIPH_SS_BASE + 0x000DB000)
70
71#define CLK_CTL_BASE 0x1800000
72
c_wufeng78f7a5f2015-09-21 13:02:06 +0800[diff] [blame]73#define PMI_SLAVE_BASE 2
74#define PMI_FIRST_SLAVE_OFFSET 0
75#define PMI_SECOND_SLAVE_OFFSET 1
76
77#define PMI_FIRST_SLAVE_ADDR_BASE (( PMI_SLAVE_BASE + PMI_FIRST_SLAVE_OFFSET ) << 16)
78#define PMI_SECOND_SLAVE_ADDR_BASE (( PMI_SLAVE_BASE + PMI_SECOND_SLAVE_OFFSET) << 16)
Matthew Qin7afa8492015-06-26 17:05:18 +0800[diff] [blame]79
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]80#define SPMI_BASE 0x02000000
81#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
82#define SPMI_PIC_BASE (SPMI_BASE + 0x01800000)
83#define PMIC_ARB_CORE 0x200F000
84
85#define TLMM_BASE_ADDR 0x1000000
86#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000)
87#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x00000004 + (x)*0x1000)
88
89#define MPM2_MPM_CTRL_BASE 0x004A0000
90#define MPM2_MPM_PS_HOLD 0x004AB000
91#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x004A3000
92
93/* CRYPTO ENGINE */
94#define MSM_CE1_BASE 0x073A000
95#define MSM_CE1_BAM_BASE 0x0704000
Aparna Mallavarapu7b638e62015-03-26 05:51:57 +0530[diff] [blame]96#define GCC_CRYPTO_BCR (CLK_CTL_BASE + 0x16000)
97#define GCC_CRYPTO_CMD_RCGR (CLK_CTL_BASE + 0x16004)
98#define GCC_CRYPTO_CFG_RCGR (CLK_CTL_BASE + 0x16008)
99#define GCC_CRYPTO_CBCR (CLK_CTL_BASE + 0x1601C)
100#define GCC_CRYPTO_AXI_CBCR (CLK_CTL_BASE + 0x16020)
101#define GCC_CRYPTO_AHB_CBCR (CLK_CTL_BASE + 0x16024)
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]102
103/* GPLL */
104#define GPLL0_STATUS (CLK_CTL_BASE + 0x2101C)
vijay kumara0a74722015-09-04 15:45:49 +0530[diff] [blame]105#define GPLL2_STATUS (CLK_CTL_BASE + 0x4A01C)
Parth Dixit5817c022015-11-07 16:23:57 +0530[diff] [blame]106#define GPLL0_MODE (CLK_CTL_BASE + 0x21000)
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]107#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000)
108#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004)
Aparna Mallavarapu7b638e62015-03-26 05:51:57 +0530[diff] [blame]109#define GPLL4_MODE (CLK_CTL_BASE + 0x24000)
Unnati Gandhi81b77062015-05-28 14:23:39 +0530[diff] [blame]110#define GPLL4_STATUS (CLK_CTL_BASE + 0x24024)
Padmanabhan Komanduru2655ea62015-06-08 12:23:32 +0530[diff] [blame]111#define GPLL6_STATUS (CLK_CTL_BASE + 0x3701C)
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]112
113/* SDCC */
114#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x10A000)
115#define SDCC1_BCR (CLK_CTL_BASE + 0x42000) /* block reset*/
116#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x42018) /* branch ontrol */
117#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4201C)
118#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x42004) /* cmd */
119#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x42008) /* cfg */
120#define SDCC1_M (CLK_CTL_BASE + 0x4200C) /* m */
121#define SDCC1_N (CLK_CTL_BASE + 0x42010) /* n */
122#define SDCC1_D (CLK_CTL_BASE + 0x42014) /* d */
123
Aparna Mallavarapu7b638e62015-03-26 05:51:57 +0530[diff] [blame]124/* SDHCI */
125#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900)
126#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900)
127
128#define SDCC_MCI_HC_MODE (0x00000078)
129#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
130#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
131#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
132#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
133
134#define SDCC2_BCR (CLK_CTL_BASE + 0x43000) /* block reset */
135#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x43018) /* branch control */
136#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x4301C)
137#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x43004) /* cmd */
138#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x43008) /* cfg */
139#define SDCC2_M (CLK_CTL_BASE + 0x4300C) /* m */
140#define SDCC2_N (CLK_CTL_BASE + 0x43010) /* n */
141#define SDCC2_D (CLK_CTL_BASE + 0x43014) /* d */
142
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]143/* UART */
144#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x1008)
145#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x302C)
146#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x3034)
147#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x3038)
148#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x303C)
149#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x3040)
150#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x3044)
151
152/* USB */
153#define USB_HS_BCR (CLK_CTL_BASE + 0x41000)
154#define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x41004)
155#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x41008)
156#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x41010)
157#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x41014)
158
Parth Dixit23d23442015-07-30 18:47:38 +0530[diff] [blame]159
160/* RPMB send receive buffer needs to be mapped
161 * as device memory, define the start address
162 * and size in MB
163 */
164#define RPMB_SND_RCV_BUF 0x90000000
165#define RPMB_SND_RCV_BUF_SZ 0x1
166
167/* QSEECOM: Secure app region notification */
168#define APP_REGION_ADDR 0x85E00000
169#define APP_REGION_SIZE 0x500000
170
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]171/* MDSS */
172#define MIPI_DSI_BASE (0x1A98000)
173#define MIPI_DSI0_BASE MIPI_DSI_BASE
Padmanabhan Komanduru6cabd5a2015-06-08 14:13:04 +0530[diff] [blame]174#define MIPI_DSI1_BASE (0x1A96000)
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]175#define DSI0_PHY_BASE (0x1A98500)
Padmanabhan Komanduru6cabd5a2015-06-08 14:13:04 +0530[diff] [blame]176#define DSI1_PHY_BASE (0x1A96400)
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]177#define DSI0_PLL_BASE (0x1A98300)
Padmanabhan Komanduru6cabd5a2015-06-08 14:13:04 +0530[diff] [blame]178#define DSI1_PLL_BASE (0x1A96A00)
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]179#define DSI0_REGULATOR_BASE (0x1A98780)
180#define DSI1_REGULATOR_BASE DSI0_REGULATOR_BASE
181#define MDP_BASE (0x1A00000)
182#define REG_MDP(off) (MDP_BASE + (off))
183
184#ifdef MDP_HW_REV
185#undef MDP_HW_REV
186#endif
187#define MDP_HW_REV REG_MDP(0x1000)
188
189#ifdef MDP_INTR_EN
190#undef MDP_INTR_EN
191#endif
192#define MDP_INTR_EN REG_MDP(0x1010)
193
194#ifdef MDP_INTR_CLEAR
195#undef MDP_INTR_CLEAR
196#endif
197#define MDP_INTR_CLEAR REG_MDP(0x1018)
198
199#ifdef MDP_HIST_INTR_EN
200#undef MDP_HIST_INTR_EN
201#endif
202#define MDP_HIST_INTR_EN REG_MDP(0x101C)
203
204#ifdef MDP_VP_0_VIG_0_BASE
205#undef MDP_VP_0_VIG_0_BASE
206#endif
207#define MDP_VP_0_VIG_0_BASE REG_MDP(0x5000)
208
209#ifdef MDP_VP_0_VIG_1_BASE
210#undef MDP_VP_0_VIG_1_BASE
211#endif
212#define MDP_VP_0_VIG_1_BASE REG_MDP(0x7000)
213
214#ifdef MDP_VP_0_RGB_0_BASE
215#undef MDP_VP_0_RGB_0_BASE
216#endif
217#define MDP_VP_0_RGB_0_BASE REG_MDP(0x15000)
218
219#ifdef MDP_VP_0_RGB_1_BASE
220#undef MDP_VP_0_RGB_1_BASE
221#endif
222#define MDP_VP_0_RGB_1_BASE REG_MDP(0x17000)
223
224#ifdef MDP_VP_0_DMA_0_BASE
225#undef MDP_VP_0_DMA_0_BASE
226#endif
227#define MDP_VP_0_DMA_0_BASE REG_MDP(0x25000)
228
229#ifdef MDP_VP_0_DMA_1_BASE
230#undef MDP_VP_0_DMA_1_BASE
231#endif
232#define MDP_VP_0_DMA_1_BASE REG_MDP(0x27000)
233
234#ifdef MDP_VP_0_MIXER_0_BASE
235#undef MDP_VP_0_MIXER_0_BASE
236#endif
237#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x45000)
238
239#ifdef MDP_VP_0_MIXER_1_BASE
240#undef MDP_VP_0_MIXER_1_BASE
241#endif
242#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x46000)
243
244#ifdef MDP_DISP_INTF_SEL
245#undef MDP_DISP_INTF_SEL
246#endif
247#define MDP_DISP_INTF_SEL REG_MDP(0x1004)
248
249#ifdef MDP_VIDEO_INTF_UNDERFLOW_CTL
250#undef MDP_VIDEO_INTF_UNDERFLOW_CTL
251#endif
252#define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x12E0)
253
254#ifdef MDP_UPPER_NEW_ROI_PRIOR_RO_START
255#undef MDP_UPPER_NEW_ROI_PRIOR_RO_START
256#endif
257#define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x11EC)
258
259#ifdef MDP_LOWER_NEW_ROI_PRIOR_TO_START
260#undef MDP_LOWER_NEW_ROI_PRIOR_TO_START
261#endif
262#define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x13F8)
263
264#ifdef MDP_CTL_0_BASE
265#undef MDP_CTL_0_BASE
266#endif
267#define MDP_CTL_0_BASE REG_MDP(0x2000)
268
269#ifdef MDP_CTL_1_BASE
270#undef MDP_CTL_1_BASE
271#endif
272#define MDP_CTL_1_BASE REG_MDP(0x2200)
273
274#ifdef MDP_CLK_CTRL0
275#undef MDP_CLK_CTRL0
276#endif
277#define MDP_CLK_CTRL0 REG_MDP(0x012AC)
278
279#ifdef MDP_CLK_CTRL1
280#undef MDP_CLK_CTRL1
281#endif
282#define MDP_CLK_CTRL1 REG_MDP(0x012B4)
283
284#ifdef MDP_CLK_CTRL2
285#undef MDP_CLK_CTRL2
286#endif
287#define MDP_CLK_CTRL2 REG_MDP(0x012BC)
288
289#ifdef MDP_CLK_CTRL3
290#undef MDP_CLK_CTRL3
291#endif
292#define MDP_CLK_CTRL3 REG_MDP(0x013A8)
293
294#ifdef MDP_CLK_CTRL4
295#undef MDP_CLK_CTRL4
296#endif
297#define MDP_CLK_CTRL4 REG_MDP(0x013B0)
298
299#ifdef MDP_CLK_CTRL5
300#undef MDP_CLK_CTRL5
301#endif
302#define MDP_CLK_CTRL5 REG_MDP(0x013B8)
303
304#ifdef MDP_INTF_1_BASE
305#undef MDP_INTF_1_BASE
306#endif
307#define MDP_INTF_1_BASE REG_MDP(0x12700)
308
Padmanabhan Komanduruf912cfb2015-06-08 16:36:58 +0530[diff] [blame]309#ifdef MDP_INTF_2_BASE
310#undef MDP_INTF_2_BASE
311#endif
312#define MDP_INTF_2_BASE REG_MDP(0x12F00)
313
314#ifdef MDP_REG_SPLIT_DISPLAY_EN
315#undef MDP_REG_SPLIT_DISPLAY_EN
316#endif
317#define MDP_REG_SPLIT_DISPLAY_EN REG_MDP(0x12F4)
318
319#ifdef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
320#undef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
321#endif
322#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x12F8)
323
324#ifdef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
325#undef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
326#endif
327#define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL REG_MDP(0x13F0)
328
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]329#ifdef MMSS_MDP_SMP_ALLOC_W_BASE
330#undef MMSS_MDP_SMP_ALLOC_W_BASE
331#endif
332#define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x1080)
333
334#ifdef MMSS_MDP_SMP_ALLOC_R_BASE
335#undef MMSS_MDP_SMP_ALLOC_R_BASE
336#endif
337#define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x1130)
338
339#ifdef MDP_QOS_REMAPPER_CLASS_0
340#undef MDP_QOS_REMAPPER_CLASS_0
341#endif
342#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x11E0)
343
344#ifdef VBIF_VBIF_DDR_FORCE_CLK_ON
345#undef VBIF_VBIF_DDR_FORCE_CLK_ON
346#endif
347#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0xc8004)
348
349#ifdef VBIF_VBIF_DDR_OUT_MAX_BURST
350#undef VBIF_VBIF_DDR_OUT_MAX_BURST
351#endif
352#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0xc80D8)
353
354#ifdef VBIF_VBIF_DDR_ARB_CTRL
355#undef VBIF_VBIF_DDR_ARB_CTRL
356#endif
357#define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0xc80F0)
358
359#ifdef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
360#undef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
361#endif
362#define VBIF_VBIF_DDR_RND_RBN_QOS_ARB REG_MDP(0xc8124)
363
364#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
365#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
366#endif
367#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0 REG_MDP(0xc8160)
368
369#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
370#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
371#endif
372#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1 REG_MDP(0xc8164)
373
374#ifdef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
375#undef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
376#endif
377#define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN REG_MDP(0xc8178)
378
379#ifdef VBIF_VBIF_DDR_OUT_AX_AOOO
380#undef VBIF_VBIF_DDR_OUT_AX_AOOO
381#endif
382#define VBIF_VBIF_DDR_OUT_AX_AOOO REG_MDP(0xc817C)
383
384#ifdef VBIF_VBIF_IN_RD_LIM_CONF0
385#undef VBIF_VBIF_IN_RD_LIM_CONF0
386#endif
387#define VBIF_VBIF_IN_RD_LIM_CONF0 REG_MDP(0xc80B0)
388
389#ifdef VBIF_VBIF_IN_RD_LIM_CONF1
390#undef VBIF_VBIF_IN_RD_LIM_CONF1
391#endif
392#define VBIF_VBIF_IN_RD_LIM_CONF1 REG_MDP(0xc80B4)
393
394#ifdef VBIF_VBIF_IN_WR_LIM_CONF0
395#undef VBIF_VBIF_IN_WR_LIM_CONF0
396#endif
397#define VBIF_VBIF_IN_WR_LIM_CONF0 REG_MDP(0xc80C0)
398
399#ifdef VBIF_VBIF_IN_WR_LIM_CONF1
400#undef VBIF_VBIF_IN_WR_LIM_CONF1
401#endif
402#define VBIF_VBIF_IN_WR_LIM_CONF1 REG_MDP(0xc80C4)
403
Sandeep Pandae0b27712015-07-31 16:41:13 +0530[diff] [blame]404#ifdef MDP_INTF_2_TIMING_ENGINE_EN
405#undef MDP_INTF_2_TIMING_ENGINE_EN
406#endif
407#define MDP_INTF_2_TIMING_ENGINE_EN REG_MDP(0x12F00)
408
409#ifdef MDP_PP_0_BASE
410#undef MDP_PP_0_BASE
411#endif
412#define MDP_PP_0_BASE REG_MDP(0x71000)
413
414#ifdef MDP_PP_1_BASE
415#undef MDP_PP_1_BASE
416#endif
417#define MDP_PP_1_BASE REG_MDP(0x71800)
418
419#ifdef MDSS_MDP_REG_DCE_SEL
420#undef MDSS_MDP_REG_DCE_SEL
421#endif
422#define MDSS_MDP_REG_DCE_SEL REG_MDP(0x1428)
423
424#ifdef MDSS_MDP_PP_DCE_DATA_OUT_SWAP
425#undef MDSS_MDP_PP_DCE_DATA_OUT_SWAP
426#endif
427#define MDSS_MDP_PP_DCE_DATA_OUT_SWAP 0x0CC
428
Ujwal Patel41a665a2015-07-17 13:51:30 -0700[diff] [blame]429#ifdef MDP_DSC_0_BASE
430#undef MDP_DSC_0_BASE
431#endif
432#define MDP_DSC_0_BASE REG_MDP(0x81000)
Sandeep Pandae0b27712015-07-31 16:41:13 +0530[diff] [blame]433
Ujwal Patel41a665a2015-07-17 13:51:30 -0700[diff] [blame]434#ifdef MDP_DSC_1_BASE
435#undef MDP_DSC_1_BASE
436#endif
437#define MDP_DSC_1_BASE REG_MDP(0x81400)
Sandeep Pandae0b27712015-07-31 16:41:13 +0530[diff] [blame]438
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]439#define SOFT_RESET 0x118
440#define CLK_CTRL 0x11C
441#define TRIG_CTRL 0x084
442#define CTRL 0x004
443#define COMMAND_MODE_DMA_CTRL 0x03C
444#define COMMAND_MODE_MDP_CTRL 0x040
445#define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044
446#define COMMAND_MODE_MDP_STREAM0_CTRL 0x058
447#define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C
448#define COMMAND_MODE_MDP_STREAM1_CTRL 0x060
449#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
450#define ERR_INT_MASK0 0x10C
451
452#define LANE_CTL 0x0AC
453#define LANE_SWAP_CTL 0x0B0
454#define TIMING_CTL 0x0C4
455
456#define VIDEO_MODE_ACTIVE_H 0x024
457#define VIDEO_MODE_ACTIVE_V 0x028
458#define VIDEO_MODE_TOTAL 0x02C
459#define VIDEO_MODE_HSYNC 0x030
460#define VIDEO_MODE_VSYNC 0x034
461#define VIDEO_MODE_VSYNC_VPOS 0x038
462
463#define DMA_CMD_OFFSET 0x048
464#define DMA_CMD_LENGTH 0x04C
465
466#define INT_CTRL 0x110
467#define CMD_MODE_DMA_SW_TRIGGER 0x090
468
469#define EOT_PACKET_CTRL 0x0CC
470#define MISR_CMD_CTRL 0x0A0
471#define MISR_VIDEO_CTRL 0x0A4
472#define VIDEO_MODE_CTRL 0x010
473#define HS_TIMER_CTRL 0x0BC
474
Sandeep Pandae0b27712015-07-31 16:41:13 +0530[diff] [blame]475#define VIDEO_COMPRESSION_MODE_CTRL 0x2A0
476#define VIDEO_COMPRESSION_MODE_CTRL_2 0x2A4
477#define CMD_COMPRESSION_MODE_CTRL 0x2A8
478#define CMD_COMPRESSION_MODE_CTRL_2 0x2AC
479#define CMD_COMPRESSION_MODE_CTRL_3 0x2B0
480
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]481#define TCSR_TZ_WONCE 0x193D000
482#define TCSR_BOOT_MISC_DETECT 0x193D100
Aparna Mallavarapu59914502015-06-01 15:31:28 +0530[diff] [blame]483
484#define APPS_WDOG_BARK_VAL_REG 0x0B017010
485#define APPS_WDOG_BITE_VAL_REG 0x0B017014
486#define APPS_WDOG_RESET_REG 0x0B017008
487#define APPS_WDOG_CTL_REG 0x0B017004
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]488#endif