Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved. |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 12 | * * Neither the name of The Linux Foundation nor the names of its |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #include <reg.h> |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 31 | #include <endian.h> |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 32 | #include <mipi_dsi.h> |
| 33 | #include <dev/fbcon.h> |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 34 | #include <stdlib.h> |
Greg Grisco | 1073a5e | 2011-07-28 18:59:18 -0700 | [diff] [blame] | 35 | #include <string.h> |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 36 | #include <debug.h> |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 37 | #include <target/display.h> |
Veera Sundaram Sankaran | 602d95a | 2014-12-09 17:55:04 -0800 | [diff] [blame] | 38 | #include <mdp5.h> |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 39 | #include <platform/iomap.h> |
| 40 | #include <platform/clock.h> |
Greg Grisco | 1073a5e | 2011-07-28 18:59:18 -0700 | [diff] [blame] | 41 | #include <platform/timer.h> |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 42 | #include <err.h> |
| 43 | #include <msm_panel.h> |
Matthew Qin | 81933ce | 2015-02-03 17:58:52 +0800 | [diff] [blame^] | 44 | #include <arch/ops.h> |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 45 | |
| 46 | extern void mdp_disable(void); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 47 | extern int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg, |
| 48 | unsigned short num_of_lanes); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 49 | extern void mdp_shutdown(void); |
| 50 | extern void mdp_start_dma(void); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 51 | |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 52 | #if (DISPLAY_TYPE_MDSS == 0) |
| 53 | #define MIPI_DSI0_BASE MIPI_DSI_BASE |
| 54 | #define MIPI_DSI1_BASE MIPI_DSI_BASE |
| 55 | #endif |
| 56 | |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 57 | struct fbcon_config mipi_fb_cfg = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 58 | .height = 0, |
| 59 | .width = 0, |
| 60 | .stride = 0, |
| 61 | .format = 0, |
| 62 | .bpp = 0, |
| 63 | .update_start = NULL, |
| 64 | .update_done = NULL, |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 65 | }; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 66 | |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 67 | static char read_id_a1h_cmd[4] = { 0xA1, 0x00, 0x06, 0xA0 }; /* DTYPE_DCS_READ */ |
| 68 | static struct mipi_dsi_cmd read_ddb_start_cmd = |
| 69 | {sizeof(read_id_a1h_cmd), read_id_a1h_cmd, 0x00}; |
| 70 | |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 71 | void secure_writel(uint32_t, uint32_t); |
| 72 | uint32_t secure_readl(uint32_t); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 73 | |
Shivaraj Shetty | 6460403 | 2013-11-14 16:44:10 +0530 | [diff] [blame] | 74 | static uint32_t response_value = 0; |
| 75 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 76 | static uint32_t mdss_dsi_read_panel_signature(struct mipi_panel_info *mipi) |
Shivaraj Shetty | 6460403 | 2013-11-14 16:44:10 +0530 | [diff] [blame] | 77 | { |
| 78 | uint32_t rec_buf[1]; |
| 79 | uint32_t *lp = rec_buf, data; |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 80 | uint32_t ret = response_value; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 81 | uint32_t panel_signature = mipi->signature; |
Shivaraj Shetty | 6460403 | 2013-11-14 16:44:10 +0530 | [diff] [blame] | 82 | |
| 83 | #if (DISPLAY_TYPE_MDSS == 1) |
| 84 | if (ret && ret != panel_signature) |
| 85 | goto exit_read_signature; |
| 86 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 87 | ret = mdss_dsi_cmds_tx(mipi, &read_ddb_start_cmd, 1, 0); |
Shivaraj Shetty | 6460403 | 2013-11-14 16:44:10 +0530 | [diff] [blame] | 88 | if (ret) |
| 89 | goto exit_read_signature; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 90 | if (!mdss_dsi_cmds_rx(mipi, &lp, 1, 1)) |
Shivaraj Shetty | 6460403 | 2013-11-14 16:44:10 +0530 | [diff] [blame] | 91 | goto exit_read_signature; |
| 92 | |
| 93 | data = ntohl(*lp); |
| 94 | data = data >> 8; |
| 95 | response_value = data; |
| 96 | if (response_value != panel_signature) |
| 97 | ret = response_value; |
| 98 | |
| 99 | exit_read_signature: |
| 100 | /* Keep the non detectable panel at the end and set panel signature 0xFFFF */ |
Vineet Bajaj | c0d150d | 2014-11-07 17:04:44 +0530 | [diff] [blame] | 101 | if ((panel_signature == 0) || (panel_signature == 0xFFFF)) |
Shivaraj Shetty | 6460403 | 2013-11-14 16:44:10 +0530 | [diff] [blame] | 102 | ret = 0; |
| 103 | #endif |
| 104 | return ret; |
| 105 | } |
| 106 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 107 | static int mdss_dsi_cmd_dma_trigger_for_panel(char dual_dsi, |
| 108 | uint32_t ctl_base, uint32_t sctl_base) |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 109 | { |
| 110 | uint32_t ReadValue; |
| 111 | uint32_t count = 0; |
| 112 | int status = 0; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 113 | uint32_t base = dual_dsi ? sctl_base : ctl_base; |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 114 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 115 | #if (DISPLAY_TYPE_MDSS == 1) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 116 | writel(0x03030303, ctl_base + INT_CTRL); |
| 117 | writel(0x1, ctl_base + CMD_MODE_DMA_SW_TRIGGER); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 118 | dsb(); |
| 119 | |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 120 | if (dual_dsi) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 121 | writel(0x03030303, sctl_base + INT_CTRL); |
| 122 | writel(0x1, sctl_base + CMD_MODE_DMA_SW_TRIGGER); |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 123 | dsb(); |
| 124 | } |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 125 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 126 | ReadValue = readl(base + INT_CTRL) & 0x00000001; |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 127 | while (ReadValue != 0x00000001) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 128 | ReadValue = readl(base + INT_CTRL) & 0x00000001; |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 129 | count++; |
| 130 | if (count > 0xffff) { |
| 131 | status = FAIL; |
| 132 | dprintf(CRITICAL, |
| 133 | "Panel CMD: command mode dma test failed\n"); |
| 134 | return status; |
| 135 | } |
| 136 | } |
| 137 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 138 | writel((readl(base + INT_CTRL) | 0x01000001), base + INT_CTRL); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 139 | dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n"); |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 140 | #endif |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 141 | return status; |
| 142 | } |
| 143 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 144 | static int mdss_dsi_wait4_video_done(uint32_t ctl_base) |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 145 | { |
| 146 | unsigned long read; |
| 147 | unsigned long count = 0; |
| 148 | int status = 0; |
| 149 | |
Padmanabhan Komanduru | 66459a9 | 2014-11-04 00:05:08 +0530 | [diff] [blame] | 150 | /* If video mode is not enabled, return here */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 151 | if ((readl(ctl_base + CTRL) & BIT(1)) == 0) |
Padmanabhan Komanduru | 66459a9 | 2014-11-04 00:05:08 +0530 | [diff] [blame] | 152 | return 0; |
| 153 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 154 | read = readl(ctl_base + INT_CTRL); |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 155 | /* Enable VIDEO MODE DONE MASK and clear the interrupt */ |
| 156 | read = read | DSI_VIDEO_MODE_DONE_MASK | DSI_VIDEO_MODE_DONE_AK; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 157 | writel(read, ctl_base + INT_CTRL); |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 158 | dsb(); |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 159 | do { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 160 | read = readl(ctl_base + INT_CTRL) & |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 161 | DSI_VIDEO_MODE_DONE_STAT; |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 162 | count++; |
| 163 | if (count > 0xffff) { |
| 164 | status = FAIL; |
| 165 | dprintf(CRITICAL, |
| 166 | "Panel CMD: Did not recieve video mode done interrupt\n"); |
| 167 | return status; |
| 168 | } |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 169 | } while (!read); |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 170 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 171 | writel((readl(ctl_base + INT_CTRL) | 0x01000001), ctl_base + INT_CTRL); |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 172 | dprintf(SPEW, "Panel wait_4_video_done: Recieved video mode done ack\n"); |
Padmanabhan Komanduru | 66459a9 | 2014-11-04 00:05:08 +0530 | [diff] [blame] | 173 | |
| 174 | /* Skip BLLP 4ms */ |
| 175 | mdelay(4); |
| 176 | |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 177 | return status; |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 178 | } |
| 179 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 180 | int mdss_dsi_cmds_tx(struct mipi_panel_info *mipi, |
| 181 | struct mipi_dsi_cmd *cmds, int count, char dual_dsi) |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 182 | { |
| 183 | int ret = 0; |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 184 | #if (DISPLAY_TYPE_MDSS == 1) |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 185 | struct mipi_dsi_cmd *cm; |
| 186 | int i = 0; |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 187 | uint8_t pload[256]; |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 188 | uint32_t off; |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 189 | uint32_t size; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 190 | uint32_t ctl_base, sctl_base; |
| 191 | |
| 192 | /* if dest controller is not specified, default to DSI0 */ |
| 193 | if (!mipi) { |
| 194 | ctl_base = MIPI_DSI0_BASE; |
| 195 | sctl_base = MIPI_DSI1_BASE; |
| 196 | } else { |
| 197 | ctl_base = mipi->ctl_base; |
| 198 | sctl_base = mipi->sctl_base; |
| 199 | } |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 200 | |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 201 | /* Align pload at 8 byte boundary */ |
| 202 | off = (uint32_t) pload; |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 203 | off &= 0x07; |
| 204 | if (off) |
| 205 | off = 8 - off; |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 206 | off += (uint32_t) pload; |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 207 | |
| 208 | cm = cmds; |
| 209 | for (i = 0; i < count; i++) { |
Padmanabhan Komanduru | 66459a9 | 2014-11-04 00:05:08 +0530 | [diff] [blame] | 210 | /* Wait for VIDEO_MODE_DONE */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 211 | ret = mdss_dsi_wait4_video_done(ctl_base); |
Padmanabhan Komanduru | 66459a9 | 2014-11-04 00:05:08 +0530 | [diff] [blame] | 212 | if (ret) |
| 213 | goto wait4video_error; |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 214 | |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 215 | /* The payload size has to be a multiple of 4 */ |
| 216 | size = cm->size; |
| 217 | size &= 0x03; |
| 218 | if (size) |
| 219 | size = 4 - size; |
| 220 | size += cm->size; |
| 221 | memcpy((uint8_t *)off, (cm->payload), size); |
Matthew Qin | 81933ce | 2015-02-03 17:58:52 +0800 | [diff] [blame^] | 222 | arch_clean_invalidate_cache_range((addr_t)(off), size); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 223 | writel(off, ctl_base + DMA_CMD_OFFSET); |
| 224 | writel(size, ctl_base + DMA_CMD_LENGTH); |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 225 | if (dual_dsi) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 226 | writel(off, sctl_base + DMA_CMD_OFFSET); |
| 227 | writel(size, sctl_base + DMA_CMD_LENGTH); |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 228 | } |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 229 | dsb(); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 230 | ret += mdss_dsi_cmd_dma_trigger_for_panel(dual_dsi, ctl_base, |
| 231 | sctl_base); |
Dhaval Patel | 607a624 | 2013-10-29 12:37:24 -0700 | [diff] [blame] | 232 | if (cm->wait) |
| 233 | mdelay(cm->wait); |
| 234 | else |
| 235 | udelay(80); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 236 | cm++; |
| 237 | } |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 238 | wait4video_error: |
Padmanabhan Komanduru | 66459a9 | 2014-11-04 00:05:08 +0530 | [diff] [blame] | 239 | #endif |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 240 | return ret; |
| 241 | } |
| 242 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 243 | int mdss_dsi_cmds_rx(struct mipi_panel_info *mipi, uint32_t **rp, int rp_len, |
| 244 | int rdbk_len) |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 245 | { |
| 246 | uint32_t *lp, data; |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 247 | uint32_t *dp; |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 248 | int i, off; |
| 249 | int rlen, res; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 250 | uint32_t ctl_base; |
| 251 | |
| 252 | /* if dest controller is not specified, default to DSI0 */ |
| 253 | if (!mipi) |
| 254 | ctl_base = MIPI_DSI0_BASE; |
| 255 | else |
| 256 | ctl_base = mipi->ctl_base; |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 257 | |
| 258 | if (rdbk_len > rp_len) { |
| 259 | return 0; |
| 260 | } |
| 261 | |
| 262 | if (rdbk_len <= 2) |
| 263 | rlen = 4; /* short read */ |
| 264 | else |
| 265 | rlen = MIPI_DSI_MRPS + 6; /* 4 bytes header + 2 bytes crc */ |
| 266 | |
| 267 | if (rlen > MIPI_DSI_REG_LEN) { |
| 268 | return 0; |
| 269 | } |
| 270 | |
| 271 | res = rlen & 0x03; |
| 272 | |
| 273 | rlen += res; /* 4 byte align */ |
| 274 | lp = *rp; |
| 275 | |
| 276 | rlen += 3; |
| 277 | rlen >>= 2; |
| 278 | |
| 279 | if (rlen > 4) |
| 280 | rlen = 4; /* 4 x 32 bits registers only */ |
| 281 | |
Shivaraj Shetty | 3c77da6 | 2013-12-09 15:58:16 +0530 | [diff] [blame] | 282 | off = RDBK_DATA0; |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 283 | off += ((rlen - 1) * 4); |
| 284 | |
| 285 | for (i = 0; i < rlen; i++) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 286 | data = readl(ctl_base + off); |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 287 | *lp = ntohl(data); /* to network byte order */ |
| 288 | lp++; |
| 289 | |
| 290 | off -= 4; |
| 291 | } |
| 292 | |
| 293 | if (rdbk_len > 2) { |
| 294 | /*First 4 bytes + paded bytes will be header next len bytes would be payload */ |
| 295 | for (i = 0; i < rdbk_len; i++) { |
| 296 | dp = *rp; |
| 297 | dp[i] = dp[(res + i) >> 2]; |
| 298 | } |
| 299 | } |
| 300 | return rdbk_len; |
| 301 | } |
| 302 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 303 | static int mdss_dsi_cmd_bta_sw_trigger(uint32_t ctl_base) |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 304 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 305 | uint32_t data; |
| 306 | int cnt = 0; |
| 307 | int err = 0; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 308 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 309 | writel(0x01, ctl_base + 0x094); /* trigger */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 310 | while (cnt < 10000) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 311 | data = readl(ctl_base + 0x0004); /*DSI_STATUS */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 312 | if ((data & 0x0010) == 0) |
| 313 | break; |
| 314 | cnt++; |
| 315 | } |
| 316 | if (cnt == 10000) |
| 317 | err = 1; |
| 318 | return err; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 319 | } |
| 320 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 321 | int mdss_dsi_host_init(struct mipi_panel_info *mipi, uint32_t |
Dhaval Patel | 9207dec | 2014-04-16 10:45:32 -0700 | [diff] [blame] | 322 | dual_dsi, uint32_t broadcast) |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 323 | { |
| 324 | uint8_t DMA_STREAM1 = 0; // for mdp display processor path |
| 325 | uint8_t EMBED_MODE1 = 1; // from frame buffer |
| 326 | uint8_t POWER_MODE2 = 1; // from frame buffer |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 327 | uint8_t PACK_TYPE1 = 0; // long packet |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 328 | uint8_t VC1 = 0; |
| 329 | uint8_t DT1 = 0; // non embedded mode |
| 330 | uint8_t WC1 = 0; // for non embedded mode only |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 331 | uint8_t DLNx_EN; |
Siddhartha Agrawal | 2679a82 | 2013-05-31 19:15:12 -0700 | [diff] [blame] | 332 | uint8_t lane_swap = 0; |
Siddhartha Agrawal | b6c861f | 2013-05-31 19:36:44 -0700 | [diff] [blame] | 333 | uint32_t timing_ctl = 0; |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 334 | uint32_t lane_swap_dsi1 = 0; |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 335 | uint32_t ctrl_mode = 0x105; //Default is command mode to send cmds. |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 336 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 337 | #if (DISPLAY_TYPE_MDSS == 1) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 338 | switch (mipi->num_of_lanes) { |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 339 | default: |
| 340 | case 1: |
| 341 | DLNx_EN = 1; // 1 lane |
| 342 | break; |
| 343 | case 2: |
| 344 | DLNx_EN = 3; // 2 lane |
| 345 | break; |
| 346 | case 3: |
| 347 | DLNx_EN = 7; // 3 lane |
| 348 | break; |
| 349 | case 4: |
| 350 | DLNx_EN = 0x0F; /* 4 lanes */ |
| 351 | break; |
| 352 | } |
| 353 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 354 | lane_swap = mipi->lane_swap; |
| 355 | timing_ctl = ((mipi->t_clk_post << 8) | mipi->t_clk_pre); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 356 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 357 | if (mipi->cmds_post_tg) { |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 358 | /* |
| 359 | * Need to send pixel data before sending the ON commands |
| 360 | * so need to configure controller to VIDEO MODE. |
| 361 | */ |
| 362 | ctrl_mode = 0x103; |
| 363 | } |
| 364 | |
Dhaval Patel | 9207dec | 2014-04-16 10:45:32 -0700 | [diff] [blame] | 365 | if (dual_dsi) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 366 | writel(0x0001, mipi->sctl_base + SOFT_RESET); |
| 367 | writel(0x0000, mipi->sctl_base + SOFT_RESET); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 368 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 369 | /* Turn on all DSI Clks */ |
| 370 | writel((0 << 16) | 0x3f, mipi->sctl_base + CLK_CTRL); |
| 371 | writel(DMA_STREAM1 << 8 | 0x04, mipi->sctl_base + TRIG_CTRL); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 372 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 373 | writel(0 << 30 | DLNx_EN << 4 | ctrl_mode, mipi->sctl_base + CTRL); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 374 | writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26 |
| 375 | | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 376 | mipi->sctl_base + COMMAND_MODE_DMA_CTRL); |
Siddhartha Agrawal | 2679a82 | 2013-05-31 19:15:12 -0700 | [diff] [blame] | 377 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 378 | /* for 8939 hw dsi1 has Lane_map as 3210 */ |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 379 | if (readl(mipi->ctl_base) == DSI_HW_REV_103_1) |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 380 | lane_swap_dsi1 = 0x7; |
| 381 | else |
| 382 | lane_swap_dsi1 = lane_swap; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 383 | writel(lane_swap_dsi1, mipi->sctl_base + LANE_SWAP_CTL); |
| 384 | writel(timing_ctl, mipi->sctl_base + TIMING_CTL); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 385 | } |
| 386 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 387 | writel(0x0001, mipi->ctl_base + SOFT_RESET); |
| 388 | writel(0x0000, mipi->ctl_base + SOFT_RESET); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 389 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 390 | /* Turn on all DSI Clks */ |
| 391 | writel((0 << 16) | 0x3f, mipi->ctl_base + CLK_CTRL); |
| 392 | writel(DMA_STREAM1 << 8 | 0x04, mipi->ctl_base + TRIG_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 393 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 394 | writel(0 << 30 | DLNx_EN << 4 | ctrl_mode, mipi->ctl_base + CTRL); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 395 | writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26 |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 396 | | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 397 | mipi->ctl_base + COMMAND_MODE_DMA_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 398 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 399 | writel(lane_swap, mipi->ctl_base + LANE_SWAP_CTL); |
| 400 | writel(timing_ctl, mipi->ctl_base + TIMING_CTL); |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 401 | #endif |
Siddhartha Agrawal | 2679a82 | 2013-05-31 19:15:12 -0700 | [diff] [blame] | 402 | |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 403 | return 0; |
| 404 | } |
| 405 | |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 406 | void mdss_dsi_panel_shutdown(struct msm_panel_info *pinfo) |
| 407 | { |
| 408 | #if (DISPLAY_TYPE_MDSS == 1) |
| 409 | unsigned long read_val = 0; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 410 | uint32_t ctl_base = pinfo->mipi.ctl_base; |
| 411 | uint32_t sctl_base = pinfo->mipi.sctl_base; |
| 412 | |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 413 | if (pinfo->mipi.panel_off_cmds) { |
| 414 | /* |
| 415 | * Once MDP TG is disabled, reset of DSI controller is |
| 416 | * needed before we send panel OFF commands. |
| 417 | */ |
| 418 | if (pinfo->type == MIPI_VIDEO_PANEL) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 419 | read_val = readl(ctl_base + CTRL); |
| 420 | writel((read_val & ~BIT(0)), ctl_base + CTRL); |
| 421 | writel(0x0001, ctl_base + SOFT_RESET); |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 422 | dsb(); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 423 | writel(0x0000, ctl_base + SOFT_RESET); |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 424 | dsb(); |
| 425 | /* Enable cmd mode only */ |
| 426 | writel(((read_val & ~BIT(1)) | BIT(2)), |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 427 | ctl_base + CTRL); |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 428 | } |
| 429 | |
| 430 | if (pinfo->mipi.broadcast) { |
| 431 | if (pinfo->type == MIPI_VIDEO_PANEL) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 432 | read_val = readl(sctl_base + CTRL); |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 433 | writel((read_val & ~BIT(0)), |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 434 | sctl_base + CTRL); |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 435 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 436 | writel(0x0001, sctl_base + SOFT_RESET); |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 437 | dsb(); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 438 | writel(0x0000, sctl_base + SOFT_RESET); |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 439 | dsb(); |
| 440 | |
| 441 | writel(((read_val & ~BIT(1)) | BIT(2)), |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 442 | sctl_base + CTRL); |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 443 | } |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 444 | } |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 445 | mdss_dsi_cmds_tx(&pinfo->mipi, pinfo->mipi.panel_off_cmds, |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 446 | pinfo->mipi.num_of_panel_off_cmds, |
| 447 | pinfo->mipi.broadcast); |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 448 | } |
| 449 | #endif |
| 450 | } |
| 451 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 452 | int mdss_dsi_panel_initialize(struct mipi_panel_info *mipi, uint32_t |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 453 | broadcast) |
| 454 | { |
| 455 | int status = 0; |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 456 | uint32_t ctrl_mode = 0; |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 457 | |
| 458 | #if (DISPLAY_TYPE_MDSS == 1) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 459 | if (!mipi->panel_on_cmds) |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 460 | goto end; |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 461 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 462 | ctrl_mode = readl(mipi->ctl_base + CTRL); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 463 | |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 464 | /* Enable command mode before sending the commands. */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 465 | writel(ctrl_mode | 0x04, mipi->ctl_base + CTRL); |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 466 | if (broadcast) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 467 | writel(ctrl_mode | 0x04, mipi->sctl_base + CTRL); |
| 468 | status = mdss_dsi_cmds_tx(mipi, mipi->panel_on_cmds, |
| 469 | mipi->num_of_panel_on_cmds, broadcast); |
| 470 | writel(ctrl_mode, mipi->ctl_base + CTRL); |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 471 | if (broadcast) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 472 | writel(ctrl_mode, mipi->sctl_base + CTRL); |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 473 | |
| 474 | if (!broadcast && !status && target_panel_auto_detect_enabled()) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 475 | status = mdss_dsi_read_panel_signature(mipi); |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 476 | |
| 477 | end: |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 478 | #endif |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 479 | return status; |
| 480 | } |
| 481 | |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 482 | int mdss_dsi_video_mode_config(uint16_t disp_width, |
| 483 | uint16_t disp_height, |
| 484 | uint16_t img_width, |
| 485 | uint16_t img_height, |
| 486 | uint16_t hsync_porch0_fp, |
| 487 | uint16_t hsync_porch0_bp, |
| 488 | uint16_t vsync_porch0_fp, |
| 489 | uint16_t vsync_porch0_bp, |
| 490 | uint16_t hsync_width, |
| 491 | uint16_t vsync_width, |
| 492 | uint16_t dst_format, |
| 493 | uint16_t traffic_mode, |
| 494 | uint8_t lane_en, |
Padmanabhan Komanduru | e320987 | 2015-01-12 16:33:16 +0530 | [diff] [blame] | 495 | uint8_t pulse_mode_hsa_he, |
| 496 | uint32_t low_pwr_stop_mode, |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 497 | uint8_t eof_bllp_pwr, |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 498 | uint8_t interleav, |
| 499 | uint32_t ctl_base) |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 500 | { |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 501 | int status = 0; |
| 502 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 503 | #if (DISPLAY_TYPE_MDSS == 1) |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 504 | /* disable mdp first */ |
| 505 | mdp_disable(); |
| 506 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 507 | writel(0x00000000, ctl_base + CLK_CTRL); |
| 508 | writel(0x00000002, ctl_base + CLK_CTRL); |
| 509 | writel(0x00000006, ctl_base + CLK_CTRL); |
| 510 | writel(0x0000000e, ctl_base + CLK_CTRL); |
| 511 | writel(0x0000001e, ctl_base + CLK_CTRL); |
| 512 | writel(0x0000023f, ctl_base + CLK_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 513 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 514 | writel(0, ctl_base + CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 515 | |
Padmanabhan Komanduru | 2f8e0bc | 2014-11-27 18:25:36 +0530 | [diff] [blame] | 516 | writel(0x03f03fe0, ctl_base + ERR_INT_MASK0); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 517 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 518 | writel(0x02020202, ctl_base + INT_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 519 | |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 520 | /* For 8916/8939, enable DSI timing double buffering */ |
Kuogee Hsieh | 861e25d | 2014-10-29 16:50:15 -0700 | [diff] [blame] | 521 | if (readl(ctl_base) >= DSI_HW_REV_103 && |
Shivaraj Shetty | 41d2d48 | 2014-11-04 16:07:32 +0530 | [diff] [blame] | 522 | mdp_get_revision() != MDP_REV_305) |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 523 | writel(0x1, ctl_base + TIMING_DB_MODE); |
| 524 | |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 525 | writel(((disp_width + hsync_porch0_bp) << 16) | hsync_porch0_bp, |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 526 | ctl_base + VIDEO_MODE_ACTIVE_H); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 527 | |
| 528 | writel(((disp_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp), |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 529 | ctl_base + VIDEO_MODE_ACTIVE_V); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 530 | |
Terence Hampson | 7385f6a | 2013-08-16 15:31:25 -0400 | [diff] [blame] | 531 | if (mdp_get_revision() >= MDP_REV_41 || |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 532 | mdp_get_revision() == MDP_REV_304 || |
| 533 | mdp_get_revision() == MDP_REV_305) { |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 534 | writel(((disp_height + vsync_porch0_fp |
| 535 | + vsync_porch0_bp - 1) << 16) |
| 536 | | (disp_width + hsync_porch0_fp |
| 537 | + hsync_porch0_bp - 1), |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 538 | ctl_base + VIDEO_MODE_TOTAL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 539 | } else { |
| 540 | writel(((disp_height + vsync_porch0_fp |
| 541 | + vsync_porch0_bp) << 16) |
| 542 | | (disp_width + hsync_porch0_fp |
| 543 | + hsync_porch0_bp), |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 544 | ctl_base + VIDEO_MODE_TOTAL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 545 | } |
| 546 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 547 | writel((hsync_width << 16) | 0, ctl_base + VIDEO_MODE_HSYNC); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 548 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 549 | writel(0 << 16 | 0, ctl_base + VIDEO_MODE_VSYNC); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 550 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 551 | writel(vsync_width << 16 | 0, ctl_base + VIDEO_MODE_VSYNC_VPOS); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 552 | |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 553 | /* For 8916/8939, flush the DSI timing registers */ |
Kuogee Hsieh | 861e25d | 2014-10-29 16:50:15 -0700 | [diff] [blame] | 554 | if (readl(ctl_base) >= DSI_HW_REV_103 && |
Shivaraj Shetty | 41d2d48 | 2014-11-04 16:07:32 +0530 | [diff] [blame] | 555 | mdp_get_revision() != MDP_REV_305) |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 556 | writel(0x1, ctl_base + TIMING_FLUSH); |
| 557 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 558 | writel(0x0, ctl_base + EOT_PACKET_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 559 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 560 | writel(0x00000100, ctl_base + MISR_VIDEO_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 561 | |
Shivaraj Shetty | 41d2d48 | 2014-11-04 16:07:32 +0530 | [diff] [blame] | 562 | if (mdp_get_revision() >= MDP_REV_41 || mdp_get_revision() == MDP_REV_305) { |
Padmanabhan Komanduru | e320987 | 2015-01-12 16:33:16 +0530 | [diff] [blame] | 563 | writel(pulse_mode_hsa_he << 28 | low_pwr_stop_mode << 16 | |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 564 | eof_bllp_pwr << 12 | traffic_mode << 8 |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 565 | | dst_format << 4 | 0x0, ctl_base + VIDEO_MODE_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 566 | } else { |
| 567 | writel(1 << 28 | 1 << 24 | 1 << 20 | low_pwr_stop_mode << 16 | |
| 568 | eof_bllp_pwr << 12 | traffic_mode << 8 |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 569 | | dst_format << 4 | 0x0, ctl_base + VIDEO_MODE_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 570 | } |
| 571 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 572 | writel(0x3fd08, ctl_base + HS_TIMER_CTRL); |
| 573 | writel(0x00010100, ctl_base + MISR_VIDEO_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 574 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 575 | writel(0x00010100, ctl_base + INT_CTRL); |
| 576 | writel(0x02010202, ctl_base + INT_CTRL); |
| 577 | writel(0x02030303, ctl_base + INT_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 578 | |
| 579 | writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 580 | | 0x103, ctl_base + CTRL); |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 581 | #endif |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 582 | |
| 583 | return status; |
| 584 | } |
| 585 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 586 | int mdss_dsi_config(struct msm_fb_panel_data *panel) |
| 587 | { |
| 588 | int ret = NO_ERROR; |
| 589 | struct msm_panel_info *pinfo; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 590 | struct mipi_panel_info *mipi; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 591 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 592 | #if (DISPLAY_TYPE_MDSS == 1) |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 593 | if (!panel) |
| 594 | return ERR_INVALID_ARGS; |
| 595 | |
| 596 | pinfo = &(panel->panel_info); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 597 | mipi = &(pinfo->mipi); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 598 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 599 | dprintf(SPEW, "ctl_base=0x%08x, phy_base=0x%08x\n", mipi->ctl_base, |
| 600 | mipi->phy_base); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 601 | |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 602 | mdss_dsi_phy_init(mipi); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 603 | |
| 604 | ret = mdss_dsi_host_init(mipi, mipi->dual_dsi, |
| 605 | mipi->broadcast); |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 606 | if (ret) { |
| 607 | dprintf(CRITICAL, "dsi host init error\n"); |
| 608 | goto error; |
| 609 | } |
| 610 | |
Aravind Venkateswaran | 51e5755 | 2014-12-09 13:23:19 -0800 | [diff] [blame] | 611 | mdss_dsi_phy_contention_detection(mipi, mipi->phy_base); |
| 612 | if (mipi->dual_dsi) |
| 613 | mdss_dsi_phy_contention_detection(mipi, mipi->sphy_base); |
Xiaoming Zhou | 03fd48b | 2014-07-31 15:24:41 -0400 | [diff] [blame] | 614 | |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 615 | if (panel->pre_init_func) { |
| 616 | ret = panel->pre_init_func(); |
| 617 | if (ret) { |
| 618 | dprintf(CRITICAL, "pre_init_func error\n"); |
| 619 | goto error; |
| 620 | } |
| 621 | } |
| 622 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 623 | if (!mipi->cmds_post_tg) { |
| 624 | ret = mdss_dsi_panel_initialize(mipi, mipi->broadcast); |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 625 | if (ret) { |
| 626 | dprintf(CRITICAL, "dsi panel init error\n"); |
| 627 | goto error; |
| 628 | } |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 629 | } |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 630 | |
| 631 | if (pinfo->rotate && panel->rotate) |
| 632 | pinfo->rotate(); |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 633 | #endif |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 634 | |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 635 | error: |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 636 | return ret; |
| 637 | } |
| 638 | |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 639 | int mdss_dsi_post_on(struct msm_fb_panel_data *panel) |
| 640 | { |
| 641 | int ret = 0; |
| 642 | struct msm_panel_info *pinfo = &(panel->panel_info); |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 643 | |
| 644 | if (pinfo->mipi.cmds_post_tg) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 645 | ret = mdss_dsi_panel_initialize(&pinfo->mipi, pinfo->mipi.broadcast); |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 646 | if (ret) { |
| 647 | dprintf(CRITICAL, "dsi panel init error\n"); |
| 648 | } |
| 649 | } |
| 650 | return ret; |
| 651 | } |
| 652 | |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 653 | int mdss_dsi_cmd_mode_config(uint16_t disp_width, |
| 654 | uint16_t disp_height, |
| 655 | uint16_t img_width, |
| 656 | uint16_t img_height, |
| 657 | uint16_t dst_format, |
Xiaoming Zhou | 8d534dd | 2013-07-29 15:49:19 -0400 | [diff] [blame] | 658 | uint8_t ystride, |
| 659 | uint8_t lane_en, |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 660 | uint8_t interleav, |
| 661 | uint32_t ctl_base) |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 662 | { |
Xiaoming Zhou | 8d534dd | 2013-07-29 15:49:19 -0400 | [diff] [blame] | 663 | uint16_t dst_fmt = 0; |
| 664 | |
| 665 | switch (dst_format) { |
| 666 | case DSI_VIDEO_DST_FORMAT_RGB565: |
| 667 | dst_fmt = DSI_CMD_DST_FORMAT_RGB565; |
| 668 | break; |
| 669 | case DSI_VIDEO_DST_FORMAT_RGB666: |
| 670 | case DSI_VIDEO_DST_FORMAT_RGB666_LOOSE: |
| 671 | dst_fmt = DSI_CMD_DST_FORMAT_RGB666; |
| 672 | break; |
| 673 | case DSI_VIDEO_DST_FORMAT_RGB888: |
| 674 | dst_fmt = DSI_CMD_DST_FORMAT_RGB888; |
| 675 | break; |
| 676 | default: |
| 677 | dprintf(CRITICAL, "unsupported dst format\n"); |
| 678 | return ERROR; |
| 679 | } |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 680 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 681 | #if (DISPLAY_TYPE_MDSS == 1) |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 682 | writel(0x00000000, ctl_base + CLK_CTRL); |
| 683 | writel(0x00000000, ctl_base + CLK_CTRL); |
| 684 | writel(0x00000000, ctl_base + CLK_CTRL); |
| 685 | writel(0x00000000, ctl_base + CLK_CTRL); |
| 686 | writel(0x00000002, ctl_base + CLK_CTRL); |
| 687 | writel(0x00000006, ctl_base + CLK_CTRL); |
| 688 | writel(0x0000000e, ctl_base + CLK_CTRL); |
| 689 | writel(0x0000001e, ctl_base + CLK_CTRL); |
| 690 | writel(0x0000023f, ctl_base + CLK_CTRL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 691 | |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 692 | writel(0, ctl_base + CTRL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 693 | |
Padmanabhan Komanduru | 2f8e0bc | 2014-11-27 18:25:36 +0530 | [diff] [blame] | 694 | writel(0x03f03fe0, ctl_base + ERR_INT_MASK0); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 695 | |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 696 | writel(0x02020202, ctl_base + INT_CTRL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 697 | |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 698 | writel(dst_fmt, ctl_base + COMMAND_MODE_MDP_CTRL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 699 | writel((img_width * ystride + 1) << 16 | 0x0039, |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 700 | ctl_base + COMMAND_MODE_MDP_STREAM0_CTRL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 701 | writel((img_width * ystride + 1) << 16 | 0x0039, |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 702 | ctl_base + COMMAND_MODE_MDP_STREAM1_CTRL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 703 | writel(img_height << 16 | img_width, |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 704 | ctl_base + COMMAND_MODE_MDP_STREAM0_TOTAL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 705 | writel(img_height << 16 | img_width, |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 706 | ctl_base + COMMAND_MODE_MDP_STREAM1_TOTAL); |
| 707 | writel(0x13c2c, ctl_base + COMMAND_MODE_MDP_DCS_CMD_CTRL); |
Xiaoming Zhou | 8d534dd | 2013-07-29 15:49:19 -0400 | [diff] [blame] | 708 | writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 | 0x105, |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 709 | ctl_base + CTRL); |
Padmanabhan Komanduru | 7860be5 | 2014-03-18 19:07:36 +0530 | [diff] [blame] | 710 | writel(0x14000000, ctl_base + COMMAND_MODE_DMA_CTRL); |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 711 | writel(0x10000000, ctl_base + MISR_CMD_CTRL); |
Xiaoming Zhou | a046933 | 2014-03-04 18:34:24 -0500 | [diff] [blame] | 712 | writel(0x1, ctl_base + EOT_PACKET_CTRL); |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 713 | #endif |
Xiaoming Zhou | 8d534dd | 2013-07-29 15:49:19 -0400 | [diff] [blame] | 714 | return 0; |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 715 | } |
| 716 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 717 | int mipi_dsi_on(struct msm_panel_info *pinfo) |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 718 | { |
| 719 | int ret = NO_ERROR; |
| 720 | unsigned long ReadValue; |
| 721 | unsigned long count = 0; |
| 722 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 723 | ReadValue = readl(pinfo->mipi.ctl_base + INT_CTRL) & 0x00010000; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 724 | |
| 725 | mdelay(10); |
| 726 | |
| 727 | while (ReadValue != 0x00010000) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 728 | ReadValue = readl(pinfo->mipi.ctl_base + INT_CTRL) & 0x00010000; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 729 | count++; |
| 730 | if (count > 0xffff) { |
| 731 | dprintf(CRITICAL, "Video lane test failed\n"); |
| 732 | return ERROR; |
| 733 | } |
| 734 | } |
| 735 | |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 736 | dprintf(INFO, "Video lane tested successfully\n"); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 737 | return ret; |
| 738 | } |
| 739 | |
Siddhartha Agrawal | 24d81b5 | 2013-07-01 11:13:32 -0700 | [diff] [blame] | 740 | int mipi_dsi_off(struct msm_panel_info *pinfo) |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 741 | { |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 742 | if(!target_cont_splash_screen()) |
| 743 | { |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 744 | mdss_dsi_panel_shutdown(pinfo); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 745 | writel(0, pinfo->mipi.ctl_base + CLK_CTRL); |
| 746 | writel(0x1F1, pinfo->mipi.ctl_base + CTRL); |
Siddhartha Agrawal | e0033a1 | 2013-02-23 15:37:42 -0800 | [diff] [blame] | 747 | } |
| 748 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 749 | writel(0x1115501, pinfo->mipi.ctl_base + INT_CTRL); |
Siddhartha Agrawal | 24d81b5 | 2013-07-01 11:13:32 -0700 | [diff] [blame] | 750 | if (pinfo->mipi.broadcast) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 751 | writel(0x1115501, pinfo->mipi.sctl_base + INT_CTRL); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 752 | |
| 753 | return NO_ERROR; |
| 754 | } |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 755 | |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 756 | #if (DISPLAY_TYPE_MDSS == 0) |
| 757 | static int dsi_cmd_dma_trigger_for_panel() |
| 758 | { |
| 759 | unsigned long ReadValue; |
| 760 | unsigned long count = 0; |
| 761 | int status = 0; |
| 762 | |
| 763 | writel(0x03030303, DSI_INT_CTRL); |
| 764 | writel(0x1, DSI_CMD_MODE_DMA_SW_TRIGGER); |
| 765 | dsb(); |
| 766 | ReadValue = readl(DSI_INT_CTRL) & 0x00000001; |
| 767 | while (ReadValue != 0x00000001) { |
| 768 | ReadValue = readl(DSI_INT_CTRL) & 0x00000001; |
| 769 | count++; |
| 770 | if (count > 0xffff) { |
| 771 | status = FAIL; |
| 772 | dprintf(CRITICAL, |
| 773 | "Panel CMD: command mode dma test failed\n"); |
| 774 | return status; |
| 775 | } |
| 776 | } |
| 777 | |
| 778 | writel((readl(DSI_INT_CTRL) | 0x01000001), DSI_INT_CTRL); |
| 779 | dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n"); |
| 780 | return status; |
| 781 | } |
| 782 | |
| 783 | int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count) |
| 784 | { |
| 785 | int ret = 0; |
| 786 | struct mipi_dsi_cmd *cm; |
| 787 | int i = 0; |
| 788 | char pload[256]; |
| 789 | uint32_t off; |
| 790 | |
| 791 | /* Align pload at 8 byte boundry */ |
| 792 | off = pload; |
| 793 | off &= 0x07; |
| 794 | if (off) |
| 795 | off = 8 - off; |
| 796 | off += pload; |
| 797 | |
| 798 | cm = cmds; |
| 799 | for (i = 0; i < count; i++) { |
| 800 | /* Wait for VIDEO_MODE_DONE */ |
| 801 | ret = mdss_dsi_wait4_video_done(); |
| 802 | if (ret) |
| 803 | goto mipi_cmds_error; |
| 804 | |
| 805 | memcpy((void *)off, (cm->payload), cm->size); |
Matthew Qin | 81933ce | 2015-02-03 17:58:52 +0800 | [diff] [blame^] | 806 | arch_clean_invalidate_cache_range((addr_t)(off), size); |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 807 | writel(off, DSI_DMA_CMD_OFFSET); |
| 808 | writel(cm->size, DSI_DMA_CMD_LENGTH); // reg 0x48 for this build |
| 809 | dsb(); |
| 810 | ret += dsi_cmd_dma_trigger_for_panel(); |
| 811 | dsb(); |
| 812 | if (cm->wait) |
| 813 | mdelay(cm->wait); |
| 814 | else |
| 815 | udelay(80); |
| 816 | cm++; |
| 817 | } |
| 818 | mipi_cmds_error: |
| 819 | return ret; |
| 820 | } |
| 821 | |
| 822 | /* |
| 823 | * mipi_dsi_cmd_rx: can receive at most 16 bytes |
| 824 | * per transaction since it only have 4 32bits reigsters |
| 825 | * to hold data. |
| 826 | * therefore Maximum Return Packet Size need to be set to 16. |
| 827 | * any return data more than MRPS need to be break down |
| 828 | * to multiple transactions. |
| 829 | */ |
| 830 | int mipi_dsi_cmds_rx(char **rp, int len) |
| 831 | { |
| 832 | uint32_t *lp, data; |
| 833 | char *dp; |
| 834 | int i, off, cnt; |
| 835 | int rlen, res; |
| 836 | |
| 837 | if (len <= 2) |
| 838 | rlen = 4; /* short read */ |
| 839 | else |
| 840 | rlen = MIPI_DSI_MRPS + 6; /* 4 bytes header + 2 bytes crc */ |
| 841 | |
| 842 | if (rlen > MIPI_DSI_REG_LEN) { |
| 843 | return 0; |
| 844 | } |
| 845 | |
| 846 | res = rlen & 0x03; |
| 847 | |
| 848 | rlen += res; /* 4 byte align */ |
| 849 | lp = (uint32_t *) (*rp); |
| 850 | |
| 851 | cnt = rlen; |
| 852 | cnt += 3; |
| 853 | cnt >>= 2; |
| 854 | |
| 855 | if (cnt > 4) |
| 856 | cnt = 4; /* 4 x 32 bits registers only */ |
| 857 | |
| 858 | off = 0x068; /* DSI_RDBK_DATA0 */ |
| 859 | off += ((cnt - 1) * 4); |
| 860 | |
| 861 | for (i = 0; i < cnt; i++) { |
| 862 | data = (uint32_t) readl(MIPI_DSI_BASE + off); |
| 863 | *lp++ = ntohl(data); /* to network byte order */ |
| 864 | off -= 4; |
| 865 | } |
| 866 | |
| 867 | if (len > 2) { |
| 868 | /*First 4 bytes + paded bytes will be header next len bytes would be payload */ |
| 869 | for (i = 0; i < len; i++) { |
| 870 | dp = *rp; |
| 871 | dp[i] = dp[4 + res + i]; |
| 872 | } |
| 873 | } |
| 874 | |
| 875 | return len; |
| 876 | } |
| 877 | |
| 878 | static int mipi_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo) |
| 879 | { |
| 880 | uint8_t DMA_STREAM1 = 0; // for mdp display processor path |
| 881 | uint8_t EMBED_MODE1 = 1; // from frame buffer |
| 882 | uint8_t POWER_MODE2 = 1; // from frame buffer |
| 883 | uint8_t PACK_TYPE1; // long packet |
| 884 | uint8_t VC1 = 0; |
| 885 | uint8_t DT1 = 0; // non embedded mode |
| 886 | uint8_t WC1 = 0; // for non embedded mode only |
| 887 | int status = 0; |
| 888 | uint8_t DLNx_EN; |
| 889 | |
| 890 | switch (pinfo->num_of_lanes) { |
| 891 | default: |
| 892 | case 1: |
| 893 | DLNx_EN = 1; // 1 lane |
| 894 | break; |
| 895 | case 2: |
| 896 | DLNx_EN = 3; // 2 lane |
| 897 | break; |
| 898 | case 3: |
| 899 | DLNx_EN = 7; // 3 lane |
| 900 | break; |
| 901 | case 4: |
| 902 | DLNx_EN = 0x0F; /* 4 lanes */ |
| 903 | break; |
| 904 | } |
| 905 | |
| 906 | PACK_TYPE1 = pinfo->pack; |
| 907 | |
| 908 | writel(0x0001, DSI_SOFT_RESET); |
| 909 | writel(0x0000, DSI_SOFT_RESET); |
| 910 | |
| 911 | writel((0 << 16) | 0x3f, DSI_CLK_CTRL); /* Turn on all DSI Clks */ |
| 912 | writel(DMA_STREAM1 << 8 | 0x04, DSI_TRIG_CTRL); // reg 0x80 dma trigger: sw |
| 913 | // trigger 0x4; dma stream1 |
| 914 | |
| 915 | writel(0 << 30 | DLNx_EN << 4 | 0x105, DSI_CTRL); // reg 0x00 for this |
| 916 | // build |
| 917 | writel(EMBED_MODE1 << 28 | POWER_MODE2 << 26 |
| 918 | | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, |
| 919 | DSI_COMMAND_MODE_DMA_CTRL); |
| 920 | |
| 921 | if (pinfo->panel_on_cmds) |
| 922 | status = mipi_dsi_cmds_tx(pinfo->panel_on_cmds, |
| 923 | pinfo->num_of_panel_on_cmds); |
| 924 | |
| 925 | return status; |
| 926 | } |
| 927 | #endif |
| 928 | |
| 929 | void mipi_dsi_shutdown(void) |
| 930 | { |
| 931 | #if (DISPLAY_TYPE_MDSS == 0) |
| 932 | if(!target_cont_splash_screen()) |
| 933 | { |
| 934 | mdp_shutdown(); |
| 935 | writel(0x01010101, DSI_INT_CTRL); |
| 936 | writel(0x13FF3BFF, DSI_ERR_INT_MASK0); |
| 937 | |
| 938 | writel(0, DSI_CLK_CTRL); |
| 939 | writel(0, DSI_CTRL); |
| 940 | writel(0, DSIPHY_PLL_CTRL(0)); |
| 941 | } |
| 942 | else |
| 943 | { |
| 944 | /* To keep the splash screen displayed till kernel driver takes |
| 945 | control, do not turn off the video mode engine and clocks. |
| 946 | Only disabling the MIPI DSI IRQs */ |
| 947 | writel(0x01010101, DSI_INT_CTRL); |
| 948 | writel(0x13FF3BFF, DSI_ERR_INT_MASK0); |
| 949 | } |
| 950 | #endif |
| 951 | } |
| 952 | |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 953 | int mipi_cmd_trigger() |
| 954 | { |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 955 | #if (DISPLAY_TYPE_MDSS == 0) |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 956 | writel(0x1, DSI_CMD_MODE_MDP_SW_TRIGGER); |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 957 | #endif |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 958 | return NO_ERROR; |
| 959 | } |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 960 | |
| 961 | int mipi_config(struct msm_fb_panel_data *panel) |
| 962 | { |
| 963 | int ret = NO_ERROR; |
| 964 | #if (DISPLAY_TYPE_MDSS == 0) |
| 965 | struct msm_panel_info *pinfo; |
| 966 | struct mipi_dsi_panel_config mipi_pinfo; |
| 967 | |
| 968 | if (!panel) |
| 969 | return ERR_INVALID_ARGS; |
| 970 | |
| 971 | pinfo = &(panel->panel_info); |
| 972 | mipi_pinfo.mode = pinfo->mipi.mode; |
| 973 | mipi_pinfo.num_of_lanes = pinfo->mipi.num_of_lanes; |
| 974 | mipi_pinfo.dsi_phy_config = pinfo->mipi.dsi_phy_db; |
| 975 | mipi_pinfo.panel_on_cmds = pinfo->mipi.panel_on_cmds; |
| 976 | mipi_pinfo.num_of_panel_on_cmds = pinfo->mipi.num_of_panel_on_cmds; |
| 977 | mipi_pinfo.lane_swap = pinfo->mipi.lane_swap; |
| 978 | mipi_pinfo.pack = 1; |
| 979 | |
| 980 | /* Enable MMSS_AHB_ARB_MATER_PORT_E for |
| 981 | arbiter master0 and master 1 request */ |
| 982 | #if (!DISPLAY_MIPI_PANEL_RENESAS && !DISPLAY_TYPE_DSI6G && !DISPLAY_TYPE_8610) |
| 983 | writel(0x00001800, MMSS_SFPB_GPREG); |
| 984 | #endif |
| 985 | |
| 986 | mipi_dsi_phy_init(&mipi_pinfo); |
| 987 | |
| 988 | ret += mipi_dsi_panel_initialize(&mipi_pinfo); |
| 989 | |
| 990 | if (pinfo->rotate && panel->rotate) |
| 991 | pinfo->rotate(); |
| 992 | #endif |
| 993 | return ret; |
| 994 | } |