Jeevan Shriram | 2d3500b | 2014-12-29 16:25:06 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions |
| 5 | * are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in |
| 10 | * the documentation and/or other materials provided with the |
| 11 | * distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 19 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 20 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 22 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 23 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 24 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 26 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #include <debug.h> |
| 31 | #include <smem.h> |
| 32 | #include <err.h> |
| 33 | #include <msm_panel.h> |
| 34 | #include <mipi_dsi.h> |
| 35 | #include <pm8x41.h> |
| 36 | #include <pm8x41_wled.h> |
| 37 | #include <board.h> |
| 38 | #include <mdp5.h> |
| 39 | #include <scm.h> |
| 40 | #include <platform/gpio.h> |
| 41 | #include <platform/iomap.h> |
| 42 | #include <target/display.h> |
Aparna Mallavarapu | 430797d | 2014-05-15 11:52:56 +0530 | [diff] [blame] | 43 | #include <i2c_qup.h> |
| 44 | #include <blsp_qup.h> |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 45 | |
| 46 | #include "include/panel.h" |
| 47 | #include "include/display_resource.h" |
Veera Sundaram Sankaran | 87f8813 | 2015-01-28 11:32:44 -0800 | [diff] [blame^] | 48 | #include "gcdb_display.h" |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 49 | |
Padmanabhan Komanduru | 18aa507 | 2014-04-17 16:52:53 +0530 | [diff] [blame] | 50 | #define VCO_DELAY_USEC 1000 |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 51 | #define GPIO_STATE_LOW 0 |
| 52 | #define GPIO_STATE_HIGH 2 |
| 53 | #define RESET_GPIO_SEQ_LEN 3 |
| 54 | #define PWM_DUTY_US 13 |
| 55 | #define PWM_PERIOD_US 27 |
| 56 | |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 57 | static void mdss_dsi_uniphy_pll_sw_reset_8916(uint32_t pll_base) |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 58 | { |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 59 | writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */ |
| 60 | mdelay(1); |
| 61 | writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */ |
| 62 | mdelay(1); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 63 | } |
| 64 | |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 65 | static uint32_t dsi_pll_enable_seq_8916(uint32_t pll_base) |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 66 | { |
| 67 | uint32_t pll_locked = 0; |
| 68 | |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 69 | writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */ |
| 70 | udelay(1); |
| 71 | writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */ |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 72 | |
| 73 | /* |
| 74 | * Add hardware recommended delays between register writes for |
| 75 | * the updates to take effect. These delays are necessary for the |
| 76 | * PLL to successfully lock |
| 77 | */ |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 78 | writel(0x34, pll_base + 0x0070); /* CAL CFG1*/ |
| 79 | udelay(1); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 80 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 81 | udelay(1); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 82 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 83 | udelay(1); |
| 84 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 85 | udelay(1); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 86 | |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 87 | writel(0x04, pll_base + 0x0064); /* LKDetect CFG2 */ |
| 88 | udelay(1); |
| 89 | writel(0x05, pll_base + 0x0064); /* LKDetect CFG2 */ |
| 90 | udelay(512); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 91 | pll_locked = readl(pll_base + 0x00c0) & 0x01; |
| 92 | |
| 93 | return pll_locked; |
| 94 | } |
| 95 | |
| 96 | int target_backlight_ctrl(struct backlight *bl, uint8_t enable) |
| 97 | { |
| 98 | struct pm8x41_mpp mpp; |
| 99 | int rc; |
| 100 | |
Shuo Yan | 123546b | 2014-05-19 19:35:41 +0800 | [diff] [blame] | 101 | if (bl->bl_interface_type == BL_DCS) |
| 102 | return 0; |
| 103 | |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 104 | mpp.base = PM8x41_MMP4_BASE; |
| 105 | mpp.vin = MPP_VIN0; |
| 106 | if (enable) { |
| 107 | pm_pwm_enable(false); |
| 108 | rc = pm_pwm_config(PWM_DUTY_US, PWM_PERIOD_US); |
| 109 | if (rc < 0) |
| 110 | mpp.mode = MPP_HIGH; |
| 111 | else { |
| 112 | mpp.mode = MPP_DTEST1; |
| 113 | pm_pwm_enable(true); |
| 114 | } |
| 115 | pm8x41_config_output_mpp(&mpp); |
| 116 | pm8x41_enable_mpp(&mpp, MPP_ENABLE); |
| 117 | } else { |
| 118 | pm_pwm_enable(false); |
| 119 | pm8x41_enable_mpp(&mpp, MPP_DISABLE); |
| 120 | } |
| 121 | mdelay(20); |
| 122 | return 0; |
| 123 | } |
| 124 | |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 125 | int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) |
| 126 | { |
| 127 | int32_t ret = 0; |
| 128 | struct mdss_dsi_pll_config *pll_data; |
| 129 | dprintf(SPEW, "target_panel_clock\n"); |
| 130 | |
| 131 | pll_data = pinfo->mipi.dsi_pll_config; |
Padmanabhan Komanduru | 18aa507 | 2014-04-17 16:52:53 +0530 | [diff] [blame] | 132 | pll_data->vco_delay = VCO_DELAY_USEC; |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 133 | |
| 134 | if (enable) { |
| 135 | mdp_gdsc_ctrl(enable); |
| 136 | mdss_bus_clocks_enable(); |
| 137 | mdp_clock_enable(); |
| 138 | ret = restore_secure_cfg(SECURE_DEVICE_MDSS); |
| 139 | if (ret) { |
| 140 | dprintf(CRITICAL, |
| 141 | "%s: Failed to restore MDP security configs", |
| 142 | __func__); |
| 143 | mdp_clock_disable(); |
| 144 | mdss_bus_clocks_disable(); |
| 145 | mdp_gdsc_ctrl(0); |
| 146 | return ret; |
| 147 | } |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 148 | mdss_dsi_uniphy_pll_sw_reset_8916(DSI0_PLL_BASE); |
Jeevan Shriram | 2d3500b | 2014-12-29 16:25:06 -0800 | [diff] [blame] | 149 | mdss_dsi_auto_pll_config(pinfo->mipi.pll_0_base, |
| 150 | pinfo->mipi.ctl_base, pll_data); |
| 151 | if (!dsi_pll_enable_seq_8916(pinfo->mipi.pll_0_base)) |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 152 | dprintf(CRITICAL, "Not able to enable the pll\n"); |
Vineet Bajaj | e022da6 | 2014-07-24 19:13:34 +0530 | [diff] [blame] | 153 | gcc_dsi_clocks_enable(pinfo->mipi.dual_dsi, pll_data->pclk_m, |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 154 | pll_data->pclk_n, |
| 155 | pll_data->pclk_d); |
| 156 | } else if(!target_cont_splash_screen()) { |
Vineet Bajaj | e022da6 | 2014-07-24 19:13:34 +0530 | [diff] [blame] | 157 | gcc_dsi_clocks_disable(pinfo->mipi.dual_dsi); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 158 | mdp_clock_disable(); |
| 159 | mdss_bus_clocks_disable(); |
| 160 | mdp_gdsc_ctrl(enable); |
| 161 | } |
| 162 | |
| 163 | return 0; |
| 164 | } |
| 165 | |
Aparna Mallavarapu | 430797d | 2014-05-15 11:52:56 +0530 | [diff] [blame] | 166 | #define QRD_LCD_I2C_ADDRESS 0x3E |
| 167 | #define QRD_LCD_VPOS_ADDRESS 0x00 |
| 168 | #define QRD_LCD_VNEG_ADDRESS 0x01 |
| 169 | #define QRD_LCD_DIS_ADDRESS 0x03 |
| 170 | #define QRD_LCD_CONTROL_ADDRESS 0xFF |
| 171 | |
| 172 | static struct qup_i2c_dev *i2c_dev; |
| 173 | static int qrd_lcd_i2c_read(uint8_t addr) |
| 174 | { |
| 175 | int ret = 0; |
| 176 | /* Create a i2c_msg buffer, that is used to put the controller into read |
| 177 | mode and then to read some data. */ |
| 178 | struct i2c_msg msg_buf[] = { |
| 179 | {QRD_LCD_I2C_ADDRESS, I2C_M_WR, 1, &addr}, |
| 180 | {QRD_LCD_I2C_ADDRESS, I2C_M_RD, 1, &ret} |
| 181 | }; |
| 182 | |
| 183 | ret = qup_i2c_xfer(i2c_dev, msg_buf, 2); |
| 184 | if(ret < 0) { |
| 185 | dprintf(CRITICAL, "qup_i2c_xfer error %d\n", ret); |
| 186 | return ret; |
| 187 | } |
| 188 | return 0; |
| 189 | } |
| 190 | |
| 191 | static int qrd_lcd_i2c_write(uint8_t addr, uint8_t val) |
| 192 | { |
| 193 | int ret = 0; |
| 194 | uint8_t data_buf[] = { addr, val }; |
| 195 | |
| 196 | /* Create a i2c_msg buffer, that is used to put the controller into write |
| 197 | mode and then to write some data. */ |
| 198 | struct i2c_msg msg_buf[] = { {QRD_LCD_I2C_ADDRESS, |
| 199 | I2C_M_WR, 2, data_buf} |
| 200 | }; |
| 201 | |
| 202 | ret = qup_i2c_xfer(i2c_dev, msg_buf, 1); |
| 203 | if(ret < 0) { |
| 204 | dprintf(CRITICAL, "qup_i2c_xfer error %d\n", ret); |
| 205 | return ret; |
| 206 | } |
| 207 | return 0; |
| 208 | } |
| 209 | |
Mao Flynn | 732e3c2 | 2014-07-02 17:39:02 +0800 | [diff] [blame] | 210 | static int target_panel_reset_skuh(uint8_t enable) |
| 211 | { |
| 212 | int ret = NO_ERROR; |
| 213 | if (enable) { |
| 214 | /* for tps65132 ENP pin */ |
| 215 | gpio_tlmm_config(enp_gpio.pin_id, 0, |
| 216 | enp_gpio.pin_direction, enp_gpio.pin_pull, |
| 217 | enp_gpio.pin_strength, |
| 218 | enp_gpio.pin_state); |
| 219 | gpio_set_dir(enp_gpio.pin_id, 2); |
| 220 | |
| 221 | /* for tps65132 ENN pin*/ |
| 222 | gpio_tlmm_config(enn_gpio.pin_id, 0, |
| 223 | enn_gpio.pin_direction, enn_gpio.pin_pull, |
| 224 | enn_gpio.pin_strength, |
| 225 | enn_gpio.pin_state); |
| 226 | gpio_set_dir(enn_gpio.pin_id, 2); |
| 227 | |
| 228 | i2c_dev = qup_blsp_i2c_init(BLSP_ID_1, QUP_ID_1, 100000, 19200000); |
| 229 | if(!i2c_dev) { |
| 230 | dprintf(CRITICAL, "qup_blsp_i2c_init failed \n"); |
| 231 | ASSERT(0); |
| 232 | } |
| 233 | |
| 234 | ret = qrd_lcd_i2c_write(QRD_LCD_VPOS_ADDRESS, 0x0E); /* 5.4V */ |
| 235 | if (ret) { |
| 236 | dprintf(CRITICAL, "VPOS Register: I2C Write failure\n"); |
| 237 | } |
| 238 | |
| 239 | ret = qrd_lcd_i2c_write(QRD_LCD_VNEG_ADDRESS, 0x0E); /* -5.4V */ |
| 240 | if (ret) { |
| 241 | dprintf(CRITICAL, "VNEG Register: I2C write failure\n"); |
| 242 | } |
| 243 | |
| 244 | ret = qrd_lcd_i2c_write(QRD_LCD_DIS_ADDRESS, 0x0F); |
| 245 | if (ret) { |
| 246 | dprintf(CRITICAL, "Apps freq DIS Register: I2C write failure\n"); |
| 247 | } |
| 248 | |
| 249 | ret = qrd_lcd_i2c_write(QRD_LCD_CONTROL_ADDRESS, 0xF0); |
| 250 | if (ret) { |
| 251 | dprintf(CRITICAL, "Control Register: I2C write failure\n"); |
| 252 | } |
| 253 | } else { |
| 254 | gpio_set_dir(enp_gpio.pin_id, 0); /* ENP */ |
| 255 | gpio_set_dir(enn_gpio.pin_id, 0); /* ENN */ |
| 256 | } |
| 257 | return 0; |
| 258 | } |
| 259 | |
| 260 | static int target_panel_reset_skuk(uint8_t enable) |
| 261 | { |
| 262 | if (enable) { |
| 263 | /* for tps65132 ENP pin*/ |
| 264 | gpio_tlmm_config(enp_gpio_skuk.pin_id, 0, |
| 265 | enp_gpio_skuk.pin_direction, enp_gpio_skuk.pin_pull, |
| 266 | enp_gpio_skuk.pin_strength, enp_gpio_skuk.pin_state); |
| 267 | gpio_set_dir(enp_gpio_skuk.pin_id, 2); |
| 268 | |
| 269 | /* for tps65132 ENN pin*/ |
| 270 | gpio_tlmm_config(enn_gpio_skuk.pin_id, 0, |
| 271 | enn_gpio_skuk.pin_direction, enn_gpio_skuk.pin_pull, |
| 272 | enn_gpio_skuk.pin_strength, enn_gpio_skuk.pin_state); |
| 273 | gpio_set_dir(enn_gpio_skuk.pin_id, 2); |
| 274 | |
| 275 | /* configure backlight gpio for SKUK */ |
| 276 | gpio_tlmm_config(bkl_gpio_skuk.pin_id, 0, |
| 277 | bkl_gpio_skuk.pin_direction, bkl_gpio_skuk.pin_pull, |
| 278 | bkl_gpio_skuk.pin_strength, bkl_gpio_skuk.pin_state); |
| 279 | gpio_set_dir(bkl_gpio_skuk.pin_id, 2); |
| 280 | } else { |
| 281 | gpio_set_dir(bkl_gpio_skuk.pin_id, 0); |
| 282 | gpio_set_dir(enp_gpio_skuk.pin_id, 0); /* ENP */ |
| 283 | gpio_set_dir(enn_gpio_skuk.pin_id, 0); /* ENN */ |
| 284 | } |
| 285 | return 0; |
| 286 | } |
| 287 | |
Vineet Bajaj | 3acf94f | 2014-12-04 19:55:03 +0530 | [diff] [blame] | 288 | int target_panel_reset_incell(uint8_t enable) |
| 289 | { |
| 290 | /*Enable the gpios in 75->97->77 order for incell panel*/ |
| 291 | if (enable) { |
| 292 | gpio_tlmm_config(enable_gpio_1.pin_id, 0, |
| 293 | enable_gpio_1.pin_direction, enable_gpio_1.pin_pull, |
| 294 | enable_gpio_1.pin_strength, enable_gpio_1.pin_state); |
| 295 | gpio_set_dir(enable_gpio_1.pin_id, 2); |
| 296 | |
| 297 | gpio_tlmm_config(enp_gpio.pin_id, 0, |
| 298 | enp_gpio.pin_direction, enp_gpio.pin_pull, |
| 299 | enp_gpio.pin_strength, enp_gpio.pin_state); |
| 300 | gpio_set_dir(enp_gpio.pin_id, 2); |
| 301 | |
| 302 | gpio_tlmm_config(enn_gpio_1.pin_id, 0, |
| 303 | enn_gpio_1.pin_direction, enn_gpio_1.pin_pull, |
| 304 | enn_gpio_1.pin_strength, enn_gpio_1.pin_state); |
| 305 | gpio_set_dir(enn_gpio_1.pin_id, 2); |
| 306 | } |
| 307 | else { |
| 308 | gpio_set_dir(enable_gpio_1.pin_id, 0); |
| 309 | gpio_set_dir(enp_gpio.pin_id, 0); /* ENP */ |
| 310 | gpio_set_dir(enn_gpio_1.pin_id, 0); /* ENN */ |
| 311 | } |
| 312 | } |
| 313 | |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 314 | int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq, |
| 315 | struct msm_panel_info *pinfo) |
| 316 | { |
| 317 | int ret = NO_ERROR; |
Mao Flynn | 8140947 | 2014-04-10 15:01:30 +0800 | [diff] [blame] | 318 | uint32_t hw_id = board_hardware_id(); |
| 319 | uint32_t hw_subtype = board_hardware_subtype(); |
Gustavo Solaira | 80c274c | 2014-10-22 16:21:27 -0300 | [diff] [blame] | 320 | uint32_t target_id, plat_hw_ver_major; |
Mao Flynn | 8140947 | 2014-04-10 15:01:30 +0800 | [diff] [blame] | 321 | |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 322 | if (enable) { |
| 323 | if (pinfo->mipi.use_enable_gpio) { |
Gustavo Solaira | fb6fdd6 | 2014-09-30 08:15:32 -0300 | [diff] [blame] | 324 | /* set enable gpio pin for SKUT1 */ |
| 325 | if ((hw_id == HW_PLATFORM_QRD) && |
Gustavo Solaira | 80c274c | 2014-10-22 16:21:27 -0300 | [diff] [blame] | 326 | (hw_subtype == HW_PLATFORM_SUBTYPE_SKUT1)) { |
| 327 | target_id = board_target_id(); |
| 328 | plat_hw_ver_major = ((target_id >> 16) & 0xFF); |
| 329 | if ((plat_hw_ver_major & 0x0F) == 0x1) |
| 330 | enable_gpio = enable_gpio_skut1; |
| 331 | else |
| 332 | enable_gpio = enable_gpio_skut2; |
| 333 | } |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 334 | gpio_tlmm_config(enable_gpio.pin_id, 0, |
| 335 | enable_gpio.pin_direction, enable_gpio.pin_pull, |
| 336 | enable_gpio.pin_strength, |
| 337 | enable_gpio.pin_state); |
| 338 | |
| 339 | gpio_set_dir(enable_gpio.pin_id, 2); |
| 340 | } |
| 341 | |
Mao Flynn | 732e3c2 | 2014-07-02 17:39:02 +0800 | [diff] [blame] | 342 | if (platform_is_msm8939()) { |
| 343 | if ((hw_id == HW_PLATFORM_QRD) && |
| 344 | (hw_subtype == HW_PLATFORM_SUBTYPE_SKUK)) |
| 345 | target_panel_reset_skuk(enable); |
Vineet Bajaj | 3acf94f | 2014-12-04 19:55:03 +0530 | [diff] [blame] | 346 | if ((hw_subtype == HW_PLATFORM_SUBTYPE_CDP_1) || |
| 347 | (hw_subtype == HW_PLATFORM_SUBTYPE_MTP_3)) |
| 348 | target_panel_reset_incell(enable); |
Mao Flynn | 732e3c2 | 2014-07-02 17:39:02 +0800 | [diff] [blame] | 349 | } else { /* msm8916 */ |
| 350 | if ((hw_id == HW_PLATFORM_QRD) && |
| 351 | (hw_subtype == HW_PLATFORM_SUBTYPE_SKUH)) |
| 352 | target_panel_reset_skuh(enable); |
Mao Flynn | 8140947 | 2014-04-10 15:01:30 +0800 | [diff] [blame] | 353 | } |
| 354 | |
Shuo Yan | c8a417f | 2014-05-20 14:44:56 +0800 | [diff] [blame] | 355 | if (hw_id == HW_PLATFORM_MTP || hw_id == HW_PLATFORM_SURF) { |
| 356 | /* configure backlight gpio for MTP & CDP */ |
Vineet Bajaj | 3acf94f | 2014-12-04 19:55:03 +0530 | [diff] [blame] | 357 | gpio_tlmm_config(bkl_gpio.pin_id, 0, |
| 358 | bkl_gpio.pin_direction, bkl_gpio.pin_pull, |
| 359 | bkl_gpio.pin_strength, bkl_gpio.pin_state); |
| 360 | gpio_set_dir(bkl_gpio.pin_id, 2); |
Shuo Yan | c8a417f | 2014-05-20 14:44:56 +0800 | [diff] [blame] | 361 | } |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 362 | |
| 363 | gpio_tlmm_config(reset_gpio.pin_id, 0, |
| 364 | reset_gpio.pin_direction, reset_gpio.pin_pull, |
| 365 | reset_gpio.pin_strength, reset_gpio.pin_state); |
| 366 | |
| 367 | gpio_set_dir(reset_gpio.pin_id, 2); |
| 368 | |
| 369 | /* reset */ |
| 370 | for (int i = 0; i < RESET_GPIO_SEQ_LEN; i++) { |
| 371 | if (resetseq->pin_state[i] == GPIO_STATE_LOW) |
| 372 | gpio_set_dir(reset_gpio.pin_id, GPIO_STATE_LOW); |
| 373 | else |
| 374 | gpio_set_dir(reset_gpio.pin_id, GPIO_STATE_HIGH); |
| 375 | mdelay(resetseq->sleep[i]); |
| 376 | } |
| 377 | } else if(!target_cont_splash_screen()) { |
| 378 | gpio_set_dir(reset_gpio.pin_id, 0); |
| 379 | if (pinfo->mipi.use_enable_gpio) |
| 380 | gpio_set_dir(enable_gpio.pin_id, 0); |
Mao Flynn | 8140947 | 2014-04-10 15:01:30 +0800 | [diff] [blame] | 381 | |
Mao Flynn | 732e3c2 | 2014-07-02 17:39:02 +0800 | [diff] [blame] | 382 | if (platform_is_msm8939()) { |
| 383 | if ((hw_id == HW_PLATFORM_QRD) && |
| 384 | (hw_subtype == HW_PLATFORM_SUBTYPE_SKUK)) |
| 385 | target_panel_reset_skuk(enable); |
| 386 | } else { /* msm8916 */ |
| 387 | if ((hw_id == HW_PLATFORM_QRD) && |
| 388 | (hw_subtype == HW_PLATFORM_SUBTYPE_SKUH)) |
| 389 | target_panel_reset_skuh(enable); |
Mao Flynn | 8140947 | 2014-04-10 15:01:30 +0800 | [diff] [blame] | 390 | } |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 391 | } |
| 392 | |
| 393 | return ret; |
| 394 | } |
| 395 | |
Kuogee Hsieh | 93bcff6 | 2014-08-22 14:02:08 -0700 | [diff] [blame] | 396 | int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo) |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 397 | { |
Padmanabhan Komanduru | 0ed51fb | 2014-06-04 12:22:08 +0530 | [diff] [blame] | 398 | /* |
| 399 | * The PMIC regulators needed for display are enabled in SBL. |
| 400 | * There is no access to the regulators is LK. |
| 401 | */ |
| 402 | return NO_ERROR; |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 403 | } |
| 404 | |
| 405 | bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size) |
| 406 | { |
Veera Sundaram Sankaran | c95d675 | 2014-07-31 11:49:52 -0700 | [diff] [blame] | 407 | return gcdb_display_cmdline_arg(panel_name, pbuf, buf_size); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 408 | } |
| 409 | |
| 410 | void target_display_init(const char *panel_name) |
| 411 | { |
Padmanabhan Komanduru | 1869a76 | 2014-04-01 20:12:05 +0530 | [diff] [blame] | 412 | uint32_t panel_loop = 0; |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 413 | uint32_t ret = 0; |
Veera Sundaram Sankaran | 7868d54 | 2015-01-02 14:48:47 -0800 | [diff] [blame] | 414 | char cont_splash = '\0'; |
Jeevan Shriram | b0d523a | 2014-05-30 12:55:17 -0700 | [diff] [blame] | 415 | |
Veera Sundaram Sankaran | 7868d54 | 2015-01-02 14:48:47 -0800 | [diff] [blame] | 416 | set_panel_cmd_string(panel_name, &cont_splash); |
Sandeep Panda | e07c07b | 2014-08-25 17:04:17 +0530 | [diff] [blame] | 417 | panel_name += strspn(panel_name, " "); |
Veera Sundaram Sankaran | 3b75882 | 2014-10-17 12:15:39 -0700 | [diff] [blame] | 418 | |
| 419 | if (!strcmp(panel_name, NO_PANEL_CONFIG) |
| 420 | || !strcmp(panel_name, SIM_VIDEO_PANEL) |
| 421 | || !strcmp(panel_name, SIM_CMD_PANEL)) { |
Veera Sundaram Sankaran | c95d675 | 2014-07-31 11:49:52 -0700 | [diff] [blame] | 422 | dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n", |
Veera Sundaram Sankaran | 3b75882 | 2014-10-17 12:15:39 -0700 | [diff] [blame] | 423 | panel_name); |
Jeevan Shriram | b0d523a | 2014-05-30 12:55:17 -0700 | [diff] [blame] | 424 | return; |
| 425 | } |
| 426 | |
Padmanabhan Komanduru | 1869a76 | 2014-04-01 20:12:05 +0530 | [diff] [blame] | 427 | do { |
Justin Philip | be9de5c | 2014-09-17 12:26:49 +0530 | [diff] [blame] | 428 | target_force_cont_splash_disable(false); |
Padmanabhan Komanduru | 1869a76 | 2014-04-01 20:12:05 +0530 | [diff] [blame] | 429 | ret = gcdb_display_init(panel_name, MDP_REV_50, MIPI_FB_ADDR); |
| 430 | if (!ret || ret == ERR_NOT_SUPPORTED) { |
| 431 | break; |
| 432 | } else { |
| 433 | target_force_cont_splash_disable(true); |
| 434 | msm_display_off(); |
Padmanabhan Komanduru | 1869a76 | 2014-04-01 20:12:05 +0530 | [diff] [blame] | 435 | } |
| 436 | } while (++panel_loop <= oem_panel_max_auto_detect_panels()); |
Veera Sundaram Sankaran | 7868d54 | 2015-01-02 14:48:47 -0800 | [diff] [blame] | 437 | |
| 438 | if (cont_splash == '0') { |
| 439 | dprintf(INFO, "Forcing continuous splash disable\n"); |
| 440 | target_force_cont_splash_disable(true); |
| 441 | } |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 442 | } |
| 443 | |
| 444 | void target_display_shutdown(void) |
| 445 | { |
| 446 | gcdb_display_shutdown(); |
| 447 | } |