blob: 1ab632a94db37b4bf175c19c7ff41f17e39ed438 [file] [log] [blame]
Thomas Petazzonif6e916b2012-11-20 23:00:52 +01001config IRQCHIP
2 def_bool y
3 depends on OF_IRQ
4
Rob Herring81243e42012-11-20 21:21:40 -06005config ARM_GIC
6 bool
7 select IRQ_DOMAIN
Yingjoe Chen9a1091e2014-11-25 16:04:19 +08008 select IRQ_DOMAIN_HIERARCHY
Rob Herring81243e42012-11-20 21:21:40 -06009 select MULTI_IRQ_HANDLER
10
Linus Walleija27d21e2015-12-18 10:44:53 +010011config ARM_GIC_MAX_NR
12 int
13 default 2 if ARCH_REALVIEW
14 default 1
15
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000016config ARM_GIC_V2M
17 bool
18 depends on ARM_GIC
19 depends on PCI && PCI_MSI
20 select PCI_MSI_IRQ_DOMAIN
21
Rob Herring81243e42012-11-20 21:21:40 -060022config GIC_NON_BANKED
23 bool
24
Marc Zyngier021f6532014-06-30 16:01:31 +010025config ARM_GIC_V3
26 bool
27 select IRQ_DOMAIN
28 select MULTI_IRQ_HANDLER
Marc Zyngier443acc42014-11-24 14:35:09 +000029 select IRQ_DOMAIN_HIERARCHY
Marc Zyngier021f6532014-06-30 16:01:31 +010030
Marc Zyngier19812722014-11-24 14:35:19 +000031config ARM_GIC_V3_ITS
32 bool
33 select PCI_MSI_IRQ_DOMAIN
Uwe Kleine-König292ec082013-06-26 09:18:48 +020034
Rob Herring44430ec2012-10-27 17:25:26 -050035config ARM_NVIC
36 bool
37 select IRQ_DOMAIN
Stefan Agner2d9f59f2015-05-16 11:44:16 +020038 select IRQ_DOMAIN_HIERARCHY
Rob Herring44430ec2012-10-27 17:25:26 -050039 select GENERIC_IRQ_CHIP
40
41config ARM_VIC
42 bool
43 select IRQ_DOMAIN
44 select MULTI_IRQ_HANDLER
45
46config ARM_VIC_NR
47 int
48 default 4 if ARCH_S5PV210
Rob Herring44430ec2012-10-27 17:25:26 -050049 default 2
50 depends on ARM_VIC
51 help
52 The maximum number of VICs available in the system, for
53 power management.
54
Thomas Petazzonifed6d332016-02-10 15:46:56 +010055config ARMADA_370_XP_IRQ
56 bool
Thomas Petazzonifed6d332016-02-10 15:46:56 +010057 select GENERIC_IRQ_CHIP
Thomas Petazzonifcc392d2016-02-10 15:46:57 +010058 select PCI_MSI_IRQ_DOMAIN if PCI_MSI
Thomas Petazzonifed6d332016-02-10 15:46:56 +010059
Antoine Tenarte6b78f22016-02-19 16:22:44 +010060config ALPINE_MSI
61 bool
62 depends on PCI && PCI_MSI
63 select GENERIC_IRQ_CHIP
64 select PCI_MSI_IRQ_DOMAIN
65
Boris BREZILLONb1479eb2014-07-10 19:14:18 +020066config ATMEL_AIC_IRQ
67 bool
68 select GENERIC_IRQ_CHIP
69 select IRQ_DOMAIN
70 select MULTI_IRQ_HANDLER
71 select SPARSE_IRQ
72
73config ATMEL_AIC5_IRQ
74 bool
75 select GENERIC_IRQ_CHIP
76 select IRQ_DOMAIN
77 select MULTI_IRQ_HANDLER
78 select SPARSE_IRQ
79
Ralf Baechle0509cfd2015-07-08 14:46:08 +020080config I8259
81 bool
82 select IRQ_DOMAIN
83
Simon Arlottc7c42ec2015-11-22 14:30:14 +000084config BCM6345_L1_IRQ
85 bool
86 select GENERIC_IRQ_CHIP
87 select IRQ_DOMAIN
88
Kevin Cernekee5f7f0312014-12-25 09:49:06 -080089config BCM7038_L1_IRQ
90 bool
91 select GENERIC_IRQ_CHIP
92 select IRQ_DOMAIN
93
Kevin Cernekeea4fcbb82014-11-06 22:44:27 -080094config BCM7120_L2_IRQ
95 bool
96 select GENERIC_IRQ_CHIP
97 select IRQ_DOMAIN
98
Florian Fainelli7f646e92014-05-23 17:40:53 -070099config BRCMSTB_L2_IRQ
100 bool
Florian Fainelli7f646e92014-05-23 17:40:53 -0700101 select GENERIC_IRQ_CHIP
102 select IRQ_DOMAIN
103
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200104config DW_APB_ICTL
105 bool
Jisheng Zhange1588492014-10-22 20:59:10 +0800106 select GENERIC_IRQ_CHIP
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200107 select IRQ_DOMAIN
108
MaJun9a7c4ab2016-03-23 17:06:33 +0800109config HISILICON_IRQ_MBIGEN
110 bool
111 select ARM_GIC_V3
112 select ARM_GIC_V3_ITS
113 select GENERIC_MSI_IRQ_DOMAIN
114
James Hoganb6ef9162013-04-22 15:43:50 +0100115config IMGPDC_IRQ
116 bool
117 select GENERIC_IRQ_CHIP
118 select IRQ_DOMAIN
119
Ralf Baechle67e38cf2015-05-26 18:20:06 +0200120config IRQ_MIPS_CPU
121 bool
122 select GENERIC_IRQ_CHIP
123 select IRQ_DOMAIN
124
Alexander Shiyanafc98d92014-02-02 12:07:46 +0400125config CLPS711X_IRQCHIP
126 bool
127 depends on ARCH_CLPS711X
128 select IRQ_DOMAIN
129 select MULTI_IRQ_HANDLER
130 select SPARSE_IRQ
131 default y
132
Stefan Kristiansson4db8e6d2014-05-26 23:31:42 +0300133config OR1K_PIC
134 bool
135 select IRQ_DOMAIN
136
Felipe Balbi85980662014-09-15 16:15:02 -0500137config OMAP_IRQCHIP
138 bool
139 select GENERIC_IRQ_CHIP
140 select IRQ_DOMAIN
141
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200142config ORION_IRQCHIP
143 bool
144 select IRQ_DOMAIN
145 select MULTI_IRQ_HANDLER
146
Cristian Birsanaaa86662016-01-13 18:15:35 -0700147config PIC32_EVIC
148 bool
149 select GENERIC_IRQ_CHIP
150 select IRQ_DOMAIN
151
Magnus Damm44358042013-02-18 23:28:34 +0900152config RENESAS_INTC_IRQPIN
153 bool
154 select IRQ_DOMAIN
155
Magnus Dammfbc83b72013-02-27 17:15:01 +0900156config RENESAS_IRQC
157 bool
Magnus Damm99c221d2015-09-28 18:42:37 +0900158 select GENERIC_IRQ_CHIP
Magnus Dammfbc83b72013-02-27 17:15:01 +0900159 select IRQ_DOMAIN
160
Lee Jones07088482015-02-18 15:13:58 +0000161config ST_IRQCHIP
162 bool
163 select REGMAP
164 select MFD_SYSCON
165 help
166 Enables SysCfg Controlled IRQs on STi based platforms.
167
Mans Rullgard4bba6682016-01-20 18:07:17 +0000168config TANGO_IRQ
169 bool
170 select IRQ_DOMAIN
171 select GENERIC_IRQ_CHIP
172
Christian Ruppertb06eb012013-06-25 18:29:57 +0200173config TB10X_IRQC
174 bool
175 select IRQ_DOMAIN
176 select GENERIC_IRQ_CHIP
177
Damien Riegeld01f8632015-12-21 15:11:23 -0500178config TS4800_IRQ
179 tristate "TS-4800 IRQ controller"
180 select IRQ_DOMAIN
Richard Weinberger0df337c2016-01-25 23:24:17 +0100181 depends on HAS_IOMEM
Jean Delvared2b383d2016-02-09 11:19:20 +0100182 depends on SOC_IMX51 || COMPILE_TEST
Damien Riegeld01f8632015-12-21 15:11:23 -0500183 help
184 Support for the TS-4800 FPGA IRQ controller
185
Linus Walleij2389d502012-10-31 22:04:31 +0100186config VERSATILE_FPGA_IRQ
187 bool
188 select IRQ_DOMAIN
189
190config VERSATILE_FPGA_IRQ_NR
191 int
192 default 4
193 depends on VERSATILE_FPGA_IRQ
Max Filippov26a8e962013-12-01 12:04:57 +0400194
195config XTENSA_MX
196 bool
197 select IRQ_DOMAIN
Sricharan R96ca8482013-12-03 15:57:23 +0530198
199config IRQ_CROSSBAR
200 bool
201 help
Masanari Iidaf54619f2014-09-18 12:09:42 +0900202 Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R96ca8482013-12-03 15:57:23 +0530203 The primary irqchip invokes the crossbar's callback which inturn allocates
204 a free irq and configures the IP. Thus the peripheral interrupts are
205 routed to one of the free irqchip interrupt lines.
Grygorii Strashko89323f82014-07-23 17:40:30 +0300206
207config KEYSTONE_IRQ
208 tristate "Keystone 2 IRQ controller IP"
209 depends on ARCH_KEYSTONE
210 help
211 Support for Texas Instruments Keystone 2 IRQ controller IP which
212 is part of the Keystone 2 IPC mechanism
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700213
214config MIPS_GIC
215 bool
Qais Yousefbb11cff2015-12-08 13:20:28 +0000216 select GENERIC_IRQ_IPI
Qais Yousef2af70a92015-12-08 13:20:23 +0000217 select IRQ_DOMAIN_HIERARCHY
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700218 select MIPS_CM
Yoshinori Sato8a764482015-05-10 02:30:47 +0900219
Paul Burton44e08e72015-05-24 16:11:31 +0100220config INGENIC_IRQ
221 bool
222 depends on MACH_INGENIC
223 default y
Linus Torvalds78c10e52015-06-27 12:44:34 -0700224
Yoshinori Sato8a764482015-05-10 02:30:47 +0900225config RENESAS_H8300H_INTC
226 bool
227 select IRQ_DOMAIN
228
229config RENESAS_H8S_INTC
230 bool
Linus Torvalds78c10e52015-06-27 12:44:34 -0700231 select IRQ_DOMAIN
Shenwei Wange324c4d2015-08-24 14:04:15 -0500232
233config IMX_GPCV2
234 bool
235 select IRQ_DOMAIN
236 help
237 Enables the wakeup IRQs for IMX platforms with GPCv2 block
Oleksij Rempel7e4ac672015-10-12 21:15:34 +0200238
239config IRQ_MXS
240 def_bool y if MACH_ASM9260 || ARCH_MXS
241 select IRQ_DOMAIN
242 select STMP_DEVICE
Thomas Petazzonic27f29b2016-02-19 14:34:43 +0100243
244config MVEBU_ODMI
245 bool
246 select GENERIC_MSI_IRQ_DOMAIN
Noam Camus44df427c2015-10-29 00:26:22 +0200247
248config EZNPS_GIC
249 bool "NPS400 Global Interrupt Manager (GIM)"
250 select IRQ_DOMAIN
251 help
252 Support the EZchip NPS400 global interrupt controller