Thomas Petazzoni | f6e916b | 2012-11-20 23:00:52 +0100 | [diff] [blame] | 1 | config IRQCHIP |
2 | def_bool y | ||||
3 | depends on OF_IRQ | ||||
4 | |||||
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 5 | config ARM_GIC |
6 | bool | ||||
7 | select IRQ_DOMAIN | ||||
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 8 | select IRQ_DOMAIN_HIERARCHY |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 9 | select MULTI_IRQ_HANDLER |
10 | |||||
Linus Walleij | a27d21e | 2015-12-18 10:44:53 +0100 | [diff] [blame] | 11 | config ARM_GIC_MAX_NR |
12 | int | ||||
13 | default 2 if ARCH_REALVIEW | ||||
14 | default 1 | ||||
15 | |||||
Suravee Suthikulpanit | 853a33c | 2014-11-25 18:47:22 +0000 | [diff] [blame] | 16 | config ARM_GIC_V2M |
17 | bool | ||||
18 | depends on ARM_GIC | ||||
19 | depends on PCI && PCI_MSI | ||||
20 | select PCI_MSI_IRQ_DOMAIN | ||||
21 | |||||
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 22 | config GIC_NON_BANKED |
23 | bool | ||||
24 | |||||
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 25 | config ARM_GIC_V3 |
26 | bool | ||||
27 | select IRQ_DOMAIN | ||||
28 | select MULTI_IRQ_HANDLER | ||||
Marc Zyngier | 443acc4 | 2014-11-24 14:35:09 +0000 | [diff] [blame] | 29 | select IRQ_DOMAIN_HIERARCHY |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 30 | |
Marc Zyngier | 1981272 | 2014-11-24 14:35:19 +0000 | [diff] [blame] | 31 | config ARM_GIC_V3_ITS |
32 | bool | ||||
33 | select PCI_MSI_IRQ_DOMAIN | ||||
Uwe Kleine-König | 292ec08 | 2013-06-26 09:18:48 +0200 | [diff] [blame] | 34 | |
Ma Jun | 717c3db | 2015-12-17 19:56:35 +0800 | [diff] [blame] | 35 | config HISILICON_IRQ_MBIGEN |
36 | bool "Support mbigen interrupt controller" | ||||
37 | default n | ||||
38 | depends on ARM_GIC_V3 && ARM_GIC_V3_ITS && GENERIC_MSI_IRQ_DOMAIN | ||||
39 | help | ||||
40 | Enable the mbigen interrupt controller used on | ||||
41 | Hisilicon platform. | ||||
42 | |||||
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 43 | config ARM_NVIC |
44 | bool | ||||
45 | select IRQ_DOMAIN | ||||
Stefan Agner | 2d9f59f | 2015-05-16 11:44:16 +0200 | [diff] [blame] | 46 | select IRQ_DOMAIN_HIERARCHY |
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 47 | select GENERIC_IRQ_CHIP |
48 | |||||
49 | config ARM_VIC | ||||
50 | bool | ||||
51 | select IRQ_DOMAIN | ||||
52 | select MULTI_IRQ_HANDLER | ||||
53 | |||||
54 | config ARM_VIC_NR | ||||
55 | int | ||||
56 | default 4 if ARCH_S5PV210 | ||||
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 57 | default 2 |
58 | depends on ARM_VIC | ||||
59 | help | ||||
60 | The maximum number of VICs available in the system, for | ||||
61 | power management. | ||||
62 | |||||
Thomas Petazzoni | fed6d33 | 2016-02-10 15:46:56 +0100 | [diff] [blame] | 63 | config ARMADA_370_XP_IRQ |
64 | bool | ||||
Thomas Petazzoni | fed6d33 | 2016-02-10 15:46:56 +0100 | [diff] [blame] | 65 | select GENERIC_IRQ_CHIP |
Thomas Petazzoni | fcc392d | 2016-02-10 15:46:57 +0100 | [diff] [blame] | 66 | select PCI_MSI_IRQ_DOMAIN if PCI_MSI |
Thomas Petazzoni | fed6d33 | 2016-02-10 15:46:56 +0100 | [diff] [blame] | 67 | |
Antoine Tenart | e6b78f2 | 2016-02-19 16:22:44 +0100 | [diff] [blame^] | 68 | config ALPINE_MSI |
69 | bool | ||||
70 | depends on PCI && PCI_MSI | ||||
71 | select GENERIC_IRQ_CHIP | ||||
72 | select PCI_MSI_IRQ_DOMAIN | ||||
73 | |||||
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 74 | config ATMEL_AIC_IRQ |
75 | bool | ||||
76 | select GENERIC_IRQ_CHIP | ||||
77 | select IRQ_DOMAIN | ||||
78 | select MULTI_IRQ_HANDLER | ||||
79 | select SPARSE_IRQ | ||||
80 | |||||
81 | config ATMEL_AIC5_IRQ | ||||
82 | bool | ||||
83 | select GENERIC_IRQ_CHIP | ||||
84 | select IRQ_DOMAIN | ||||
85 | select MULTI_IRQ_HANDLER | ||||
86 | select SPARSE_IRQ | ||||
87 | |||||
Ralf Baechle | 0509cfd | 2015-07-08 14:46:08 +0200 | [diff] [blame] | 88 | config I8259 |
89 | bool | ||||
90 | select IRQ_DOMAIN | ||||
91 | |||||
Simon Arlott | c7c42ec | 2015-11-22 14:30:14 +0000 | [diff] [blame] | 92 | config BCM6345_L1_IRQ |
93 | bool | ||||
94 | select GENERIC_IRQ_CHIP | ||||
95 | select IRQ_DOMAIN | ||||
96 | |||||
Kevin Cernekee | 5f7f031 | 2014-12-25 09:49:06 -0800 | [diff] [blame] | 97 | config BCM7038_L1_IRQ |
98 | bool | ||||
99 | select GENERIC_IRQ_CHIP | ||||
100 | select IRQ_DOMAIN | ||||
101 | |||||
Kevin Cernekee | a4fcbb8 | 2014-11-06 22:44:27 -0800 | [diff] [blame] | 102 | config BCM7120_L2_IRQ |
103 | bool | ||||
104 | select GENERIC_IRQ_CHIP | ||||
105 | select IRQ_DOMAIN | ||||
106 | |||||
Florian Fainelli | 7f646e9 | 2014-05-23 17:40:53 -0700 | [diff] [blame] | 107 | config BRCMSTB_L2_IRQ |
108 | bool | ||||
Florian Fainelli | 7f646e9 | 2014-05-23 17:40:53 -0700 | [diff] [blame] | 109 | select GENERIC_IRQ_CHIP |
110 | select IRQ_DOMAIN | ||||
111 | |||||
Sebastian Hesselbarth | 350d71b9 | 2013-09-09 14:01:20 +0200 | [diff] [blame] | 112 | config DW_APB_ICTL |
113 | bool | ||||
Jisheng Zhang | e158849 | 2014-10-22 20:59:10 +0800 | [diff] [blame] | 114 | select GENERIC_IRQ_CHIP |
Sebastian Hesselbarth | 350d71b9 | 2013-09-09 14:01:20 +0200 | [diff] [blame] | 115 | select IRQ_DOMAIN |
116 | |||||
James Hogan | b6ef916 | 2013-04-22 15:43:50 +0100 | [diff] [blame] | 117 | config IMGPDC_IRQ |
118 | bool | ||||
119 | select GENERIC_IRQ_CHIP | ||||
120 | select IRQ_DOMAIN | ||||
121 | |||||
Ralf Baechle | 67e38cf | 2015-05-26 18:20:06 +0200 | [diff] [blame] | 122 | config IRQ_MIPS_CPU |
123 | bool | ||||
124 | select GENERIC_IRQ_CHIP | ||||
125 | select IRQ_DOMAIN | ||||
126 | |||||
Alexander Shiyan | afc98d9 | 2014-02-02 12:07:46 +0400 | [diff] [blame] | 127 | config CLPS711X_IRQCHIP |
128 | bool | ||||
129 | depends on ARCH_CLPS711X | ||||
130 | select IRQ_DOMAIN | ||||
131 | select MULTI_IRQ_HANDLER | ||||
132 | select SPARSE_IRQ | ||||
133 | default y | ||||
134 | |||||
Stefan Kristiansson | 4db8e6d | 2014-05-26 23:31:42 +0300 | [diff] [blame] | 135 | config OR1K_PIC |
136 | bool | ||||
137 | select IRQ_DOMAIN | ||||
138 | |||||
Felipe Balbi | 8598066 | 2014-09-15 16:15:02 -0500 | [diff] [blame] | 139 | config OMAP_IRQCHIP |
140 | bool | ||||
141 | select GENERIC_IRQ_CHIP | ||||
142 | select IRQ_DOMAIN | ||||
143 | |||||
Sebastian Hesselbarth | 9dbd90f | 2013-06-06 18:27:09 +0200 | [diff] [blame] | 144 | config ORION_IRQCHIP |
145 | bool | ||||
146 | select IRQ_DOMAIN | ||||
147 | select MULTI_IRQ_HANDLER | ||||
148 | |||||
Cristian Birsan | aaa8666 | 2016-01-13 18:15:35 -0700 | [diff] [blame] | 149 | config PIC32_EVIC |
150 | bool | ||||
151 | select GENERIC_IRQ_CHIP | ||||
152 | select IRQ_DOMAIN | ||||
153 | |||||
Magnus Damm | 4435804 | 2013-02-18 23:28:34 +0900 | [diff] [blame] | 154 | config RENESAS_INTC_IRQPIN |
155 | bool | ||||
156 | select IRQ_DOMAIN | ||||
157 | |||||
Magnus Damm | fbc83b7 | 2013-02-27 17:15:01 +0900 | [diff] [blame] | 158 | config RENESAS_IRQC |
159 | bool | ||||
Magnus Damm | 99c221d | 2015-09-28 18:42:37 +0900 | [diff] [blame] | 160 | select GENERIC_IRQ_CHIP |
Magnus Damm | fbc83b7 | 2013-02-27 17:15:01 +0900 | [diff] [blame] | 161 | select IRQ_DOMAIN |
162 | |||||
Lee Jones | 0708848 | 2015-02-18 15:13:58 +0000 | [diff] [blame] | 163 | config ST_IRQCHIP |
164 | bool | ||||
165 | select REGMAP | ||||
166 | select MFD_SYSCON | ||||
167 | help | ||||
168 | Enables SysCfg Controlled IRQs on STi based platforms. | ||||
169 | |||||
Mans Rullgard | 4bba668 | 2016-01-20 18:07:17 +0000 | [diff] [blame] | 170 | config TANGO_IRQ |
171 | bool | ||||
172 | select IRQ_DOMAIN | ||||
173 | select GENERIC_IRQ_CHIP | ||||
174 | |||||
Christian Ruppert | b06eb01 | 2013-06-25 18:29:57 +0200 | [diff] [blame] | 175 | config TB10X_IRQC |
176 | bool | ||||
177 | select IRQ_DOMAIN | ||||
178 | select GENERIC_IRQ_CHIP | ||||
179 | |||||
Damien Riegel | d01f863 | 2015-12-21 15:11:23 -0500 | [diff] [blame] | 180 | config TS4800_IRQ |
181 | tristate "TS-4800 IRQ controller" | ||||
182 | select IRQ_DOMAIN | ||||
Richard Weinberger | 0df337c | 2016-01-25 23:24:17 +0100 | [diff] [blame] | 183 | depends on HAS_IOMEM |
Jean Delvare | d2b383d | 2016-02-09 11:19:20 +0100 | [diff] [blame] | 184 | depends on SOC_IMX51 || COMPILE_TEST |
Damien Riegel | d01f863 | 2015-12-21 15:11:23 -0500 | [diff] [blame] | 185 | help |
186 | Support for the TS-4800 FPGA IRQ controller | ||||
187 | |||||
Linus Walleij | 2389d50 | 2012-10-31 22:04:31 +0100 | [diff] [blame] | 188 | config VERSATILE_FPGA_IRQ |
189 | bool | ||||
190 | select IRQ_DOMAIN | ||||
191 | |||||
192 | config VERSATILE_FPGA_IRQ_NR | ||||
193 | int | ||||
194 | default 4 | ||||
195 | depends on VERSATILE_FPGA_IRQ | ||||
Max Filippov | 26a8e96 | 2013-12-01 12:04:57 +0400 | [diff] [blame] | 196 | |
197 | config XTENSA_MX | ||||
198 | bool | ||||
199 | select IRQ_DOMAIN | ||||
Sricharan R | 96ca848 | 2013-12-03 15:57:23 +0530 | [diff] [blame] | 200 | |
201 | config IRQ_CROSSBAR | ||||
202 | bool | ||||
203 | help | ||||
Masanari Iida | f54619f | 2014-09-18 12:09:42 +0900 | [diff] [blame] | 204 | Support for a CROSSBAR ip that precedes the main interrupt controller. |
Sricharan R | 96ca848 | 2013-12-03 15:57:23 +0530 | [diff] [blame] | 205 | The primary irqchip invokes the crossbar's callback which inturn allocates |
206 | a free irq and configures the IP. Thus the peripheral interrupts are | ||||
207 | routed to one of the free irqchip interrupt lines. | ||||
Grygorii Strashko | 89323f8 | 2014-07-23 17:40:30 +0300 | [diff] [blame] | 208 | |
209 | config KEYSTONE_IRQ | ||||
210 | tristate "Keystone 2 IRQ controller IP" | ||||
211 | depends on ARCH_KEYSTONE | ||||
212 | help | ||||
213 | Support for Texas Instruments Keystone 2 IRQ controller IP which | ||||
214 | is part of the Keystone 2 IPC mechanism | ||||
Andrew Bresticker | 8a19b8f | 2014-09-18 14:47:19 -0700 | [diff] [blame] | 215 | |
216 | config MIPS_GIC | ||||
217 | bool | ||||
Qais Yousef | bb11cff | 2015-12-08 13:20:28 +0000 | [diff] [blame] | 218 | select GENERIC_IRQ_IPI |
Qais Yousef | 2af70a9 | 2015-12-08 13:20:23 +0000 | [diff] [blame] | 219 | select IRQ_DOMAIN_HIERARCHY |
Andrew Bresticker | 8a19b8f | 2014-09-18 14:47:19 -0700 | [diff] [blame] | 220 | select MIPS_CM |
Yoshinori Sato | 8a76448 | 2015-05-10 02:30:47 +0900 | [diff] [blame] | 221 | |
Paul Burton | 44e08e7 | 2015-05-24 16:11:31 +0100 | [diff] [blame] | 222 | config INGENIC_IRQ |
223 | bool | ||||
224 | depends on MACH_INGENIC | ||||
225 | default y | ||||
Linus Torvalds | 78c10e5 | 2015-06-27 12:44:34 -0700 | [diff] [blame] | 226 | |
Yoshinori Sato | 8a76448 | 2015-05-10 02:30:47 +0900 | [diff] [blame] | 227 | config RENESAS_H8300H_INTC |
228 | bool | ||||
229 | select IRQ_DOMAIN | ||||
230 | |||||
231 | config RENESAS_H8S_INTC | ||||
232 | bool | ||||
Linus Torvalds | 78c10e5 | 2015-06-27 12:44:34 -0700 | [diff] [blame] | 233 | select IRQ_DOMAIN |
Shenwei Wang | e324c4d | 2015-08-24 14:04:15 -0500 | [diff] [blame] | 234 | |
235 | config IMX_GPCV2 | ||||
236 | bool | ||||
237 | select IRQ_DOMAIN | ||||
238 | help | ||||
239 | Enables the wakeup IRQs for IMX platforms with GPCv2 block | ||||
Oleksij Rempel | 7e4ac67 | 2015-10-12 21:15:34 +0200 | [diff] [blame] | 240 | |
241 | config IRQ_MXS | ||||
242 | def_bool y if MACH_ASM9260 || ARCH_MXS | ||||
243 | select IRQ_DOMAIN | ||||
244 | select STMP_DEVICE | ||||
Thomas Petazzoni | c27f29b | 2016-02-19 14:34:43 +0100 | [diff] [blame] | 245 | |
246 | config MVEBU_ODMI | ||||
247 | bool | ||||
248 | select GENERIC_MSI_IRQ_DOMAIN |