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Thomas Petazzonif6e916b2012-11-20 23:00:52 +01001config IRQCHIP
2 def_bool y
3 depends on OF_IRQ
4
Rob Herring81243e42012-11-20 21:21:40 -06005config ARM_GIC
6 bool
7 select IRQ_DOMAIN
Yingjoe Chen9a1091e2014-11-25 16:04:19 +08008 select IRQ_DOMAIN_HIERARCHY
Rob Herring81243e42012-11-20 21:21:40 -06009 select MULTI_IRQ_HANDLER
10
Linus Walleija27d21e2015-12-18 10:44:53 +010011config ARM_GIC_MAX_NR
12 int
13 default 2 if ARCH_REALVIEW
14 default 1
15
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000016config ARM_GIC_V2M
17 bool
18 depends on ARM_GIC
19 depends on PCI && PCI_MSI
20 select PCI_MSI_IRQ_DOMAIN
21
Rob Herring81243e42012-11-20 21:21:40 -060022config GIC_NON_BANKED
23 bool
24
Marc Zyngier021f6532014-06-30 16:01:31 +010025config ARM_GIC_V3
26 bool
27 select IRQ_DOMAIN
28 select MULTI_IRQ_HANDLER
Marc Zyngier443acc42014-11-24 14:35:09 +000029 select IRQ_DOMAIN_HIERARCHY
Marc Zyngier021f6532014-06-30 16:01:31 +010030
Marc Zyngier19812722014-11-24 14:35:19 +000031config ARM_GIC_V3_ITS
32 bool
33 select PCI_MSI_IRQ_DOMAIN
Uwe Kleine-König292ec082013-06-26 09:18:48 +020034
Ma Jun717c3db2015-12-17 19:56:35 +080035config HISILICON_IRQ_MBIGEN
36 bool "Support mbigen interrupt controller"
37 default n
38 depends on ARM_GIC_V3 && ARM_GIC_V3_ITS && GENERIC_MSI_IRQ_DOMAIN
39 help
40 Enable the mbigen interrupt controller used on
41 Hisilicon platform.
42
Rob Herring44430ec2012-10-27 17:25:26 -050043config ARM_NVIC
44 bool
45 select IRQ_DOMAIN
Stefan Agner2d9f59f2015-05-16 11:44:16 +020046 select IRQ_DOMAIN_HIERARCHY
Rob Herring44430ec2012-10-27 17:25:26 -050047 select GENERIC_IRQ_CHIP
48
49config ARM_VIC
50 bool
51 select IRQ_DOMAIN
52 select MULTI_IRQ_HANDLER
53
54config ARM_VIC_NR
55 int
56 default 4 if ARCH_S5PV210
Rob Herring44430ec2012-10-27 17:25:26 -050057 default 2
58 depends on ARM_VIC
59 help
60 The maximum number of VICs available in the system, for
61 power management.
62
Thomas Petazzonifed6d332016-02-10 15:46:56 +010063config ARMADA_370_XP_IRQ
64 bool
Thomas Petazzonifed6d332016-02-10 15:46:56 +010065 select GENERIC_IRQ_CHIP
Thomas Petazzonifcc392d2016-02-10 15:46:57 +010066 select PCI_MSI_IRQ_DOMAIN if PCI_MSI
Thomas Petazzonifed6d332016-02-10 15:46:56 +010067
Antoine Tenarte6b78f22016-02-19 16:22:44 +010068config ALPINE_MSI
69 bool
70 depends on PCI && PCI_MSI
71 select GENERIC_IRQ_CHIP
72 select PCI_MSI_IRQ_DOMAIN
73
Boris BREZILLONb1479eb2014-07-10 19:14:18 +020074config ATMEL_AIC_IRQ
75 bool
76 select GENERIC_IRQ_CHIP
77 select IRQ_DOMAIN
78 select MULTI_IRQ_HANDLER
79 select SPARSE_IRQ
80
81config ATMEL_AIC5_IRQ
82 bool
83 select GENERIC_IRQ_CHIP
84 select IRQ_DOMAIN
85 select MULTI_IRQ_HANDLER
86 select SPARSE_IRQ
87
Ralf Baechle0509cfd2015-07-08 14:46:08 +020088config I8259
89 bool
90 select IRQ_DOMAIN
91
Simon Arlottc7c42ec2015-11-22 14:30:14 +000092config BCM6345_L1_IRQ
93 bool
94 select GENERIC_IRQ_CHIP
95 select IRQ_DOMAIN
96
Kevin Cernekee5f7f0312014-12-25 09:49:06 -080097config BCM7038_L1_IRQ
98 bool
99 select GENERIC_IRQ_CHIP
100 select IRQ_DOMAIN
101
Kevin Cernekeea4fcbb82014-11-06 22:44:27 -0800102config BCM7120_L2_IRQ
103 bool
104 select GENERIC_IRQ_CHIP
105 select IRQ_DOMAIN
106
Florian Fainelli7f646e92014-05-23 17:40:53 -0700107config BRCMSTB_L2_IRQ
108 bool
Florian Fainelli7f646e92014-05-23 17:40:53 -0700109 select GENERIC_IRQ_CHIP
110 select IRQ_DOMAIN
111
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200112config DW_APB_ICTL
113 bool
Jisheng Zhange1588492014-10-22 20:59:10 +0800114 select GENERIC_IRQ_CHIP
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200115 select IRQ_DOMAIN
116
James Hoganb6ef9162013-04-22 15:43:50 +0100117config IMGPDC_IRQ
118 bool
119 select GENERIC_IRQ_CHIP
120 select IRQ_DOMAIN
121
Ralf Baechle67e38cf2015-05-26 18:20:06 +0200122config IRQ_MIPS_CPU
123 bool
124 select GENERIC_IRQ_CHIP
125 select IRQ_DOMAIN
126
Alexander Shiyanafc98d92014-02-02 12:07:46 +0400127config CLPS711X_IRQCHIP
128 bool
129 depends on ARCH_CLPS711X
130 select IRQ_DOMAIN
131 select MULTI_IRQ_HANDLER
132 select SPARSE_IRQ
133 default y
134
Stefan Kristiansson4db8e6d2014-05-26 23:31:42 +0300135config OR1K_PIC
136 bool
137 select IRQ_DOMAIN
138
Felipe Balbi85980662014-09-15 16:15:02 -0500139config OMAP_IRQCHIP
140 bool
141 select GENERIC_IRQ_CHIP
142 select IRQ_DOMAIN
143
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200144config ORION_IRQCHIP
145 bool
146 select IRQ_DOMAIN
147 select MULTI_IRQ_HANDLER
148
Cristian Birsanaaa86662016-01-13 18:15:35 -0700149config PIC32_EVIC
150 bool
151 select GENERIC_IRQ_CHIP
152 select IRQ_DOMAIN
153
Magnus Damm44358042013-02-18 23:28:34 +0900154config RENESAS_INTC_IRQPIN
155 bool
156 select IRQ_DOMAIN
157
Magnus Dammfbc83b72013-02-27 17:15:01 +0900158config RENESAS_IRQC
159 bool
Magnus Damm99c221d2015-09-28 18:42:37 +0900160 select GENERIC_IRQ_CHIP
Magnus Dammfbc83b72013-02-27 17:15:01 +0900161 select IRQ_DOMAIN
162
Lee Jones07088482015-02-18 15:13:58 +0000163config ST_IRQCHIP
164 bool
165 select REGMAP
166 select MFD_SYSCON
167 help
168 Enables SysCfg Controlled IRQs on STi based platforms.
169
Mans Rullgard4bba6682016-01-20 18:07:17 +0000170config TANGO_IRQ
171 bool
172 select IRQ_DOMAIN
173 select GENERIC_IRQ_CHIP
174
Christian Ruppertb06eb012013-06-25 18:29:57 +0200175config TB10X_IRQC
176 bool
177 select IRQ_DOMAIN
178 select GENERIC_IRQ_CHIP
179
Damien Riegeld01f8632015-12-21 15:11:23 -0500180config TS4800_IRQ
181 tristate "TS-4800 IRQ controller"
182 select IRQ_DOMAIN
Richard Weinberger0df337c2016-01-25 23:24:17 +0100183 depends on HAS_IOMEM
Jean Delvared2b383d2016-02-09 11:19:20 +0100184 depends on SOC_IMX51 || COMPILE_TEST
Damien Riegeld01f8632015-12-21 15:11:23 -0500185 help
186 Support for the TS-4800 FPGA IRQ controller
187
Linus Walleij2389d502012-10-31 22:04:31 +0100188config VERSATILE_FPGA_IRQ
189 bool
190 select IRQ_DOMAIN
191
192config VERSATILE_FPGA_IRQ_NR
193 int
194 default 4
195 depends on VERSATILE_FPGA_IRQ
Max Filippov26a8e962013-12-01 12:04:57 +0400196
197config XTENSA_MX
198 bool
199 select IRQ_DOMAIN
Sricharan R96ca8482013-12-03 15:57:23 +0530200
201config IRQ_CROSSBAR
202 bool
203 help
Masanari Iidaf54619f2014-09-18 12:09:42 +0900204 Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R96ca8482013-12-03 15:57:23 +0530205 The primary irqchip invokes the crossbar's callback which inturn allocates
206 a free irq and configures the IP. Thus the peripheral interrupts are
207 routed to one of the free irqchip interrupt lines.
Grygorii Strashko89323f82014-07-23 17:40:30 +0300208
209config KEYSTONE_IRQ
210 tristate "Keystone 2 IRQ controller IP"
211 depends on ARCH_KEYSTONE
212 help
213 Support for Texas Instruments Keystone 2 IRQ controller IP which
214 is part of the Keystone 2 IPC mechanism
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700215
216config MIPS_GIC
217 bool
Qais Yousefbb11cff2015-12-08 13:20:28 +0000218 select GENERIC_IRQ_IPI
Qais Yousef2af70a92015-12-08 13:20:23 +0000219 select IRQ_DOMAIN_HIERARCHY
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700220 select MIPS_CM
Yoshinori Sato8a764482015-05-10 02:30:47 +0900221
Paul Burton44e08e72015-05-24 16:11:31 +0100222config INGENIC_IRQ
223 bool
224 depends on MACH_INGENIC
225 default y
Linus Torvalds78c10e52015-06-27 12:44:34 -0700226
Yoshinori Sato8a764482015-05-10 02:30:47 +0900227config RENESAS_H8300H_INTC
228 bool
229 select IRQ_DOMAIN
230
231config RENESAS_H8S_INTC
232 bool
Linus Torvalds78c10e52015-06-27 12:44:34 -0700233 select IRQ_DOMAIN
Shenwei Wange324c4d2015-08-24 14:04:15 -0500234
235config IMX_GPCV2
236 bool
237 select IRQ_DOMAIN
238 help
239 Enables the wakeup IRQs for IMX platforms with GPCv2 block
Oleksij Rempel7e4ac672015-10-12 21:15:34 +0200240
241config IRQ_MXS
242 def_bool y if MACH_ASM9260 || ARCH_MXS
243 select IRQ_DOMAIN
244 select STMP_DEVICE
Thomas Petazzonic27f29b2016-02-19 14:34:43 +0100245
246config MVEBU_ODMI
247 bool
248 select GENERIC_MSI_IRQ_DOMAIN