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Andrew Victor62c16602006-11-30 12:27:38 +01001/*
Andrew Victor9d041262007-02-05 11:42:07 +01002 * arch/arm/mach-at91/at91sam9260.c
Andrew Victor62c16602006-11-30 12:27:38 +01003 *
4 * Copyright (C) 2006 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/module.h>
Andrew Victor3ef2fb42008-04-02 21:36:06 +010014#include <linux/pm.h>
Andrew Victor62c16602006-11-30 12:27:38 +010015
Russell King80b02c12009-01-08 10:01:47 +000016#include <asm/irq.h>
Andrew Victor62c16602006-11-30 12:27:38 +010017#include <asm/mach/arch.h>
18#include <asm/mach/map.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010019#include <mach/cpu.h>
Jean-Christophe PLAGNIOL-VILLARD8c3583b2011-04-23 22:12:57 +080020#include <mach/at91_dbgu.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010021#include <mach/at91sam9260.h>
22#include <mach/at91_pmc.h>
23#include <mach/at91_rstc.h>
24#include <mach/at91_shdwc.h>
Andrew Victor62c16602006-11-30 12:27:38 +010025
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +080026#include "soc.h"
Andrew Victor62c16602006-11-30 12:27:38 +010027#include "generic.h"
28#include "clock.h"
29
Andrew Victor62c16602006-11-30 12:27:38 +010030/* --------------------------------------------------------------------
31 * Clocks
32 * -------------------------------------------------------------------- */
33
34/*
35 * The peripheral clocks.
36 */
37static struct clk pioA_clk = {
38 .name = "pioA_clk",
39 .pmc_mask = 1 << AT91SAM9260_ID_PIOA,
40 .type = CLK_TYPE_PERIPHERAL,
41};
42static struct clk pioB_clk = {
43 .name = "pioB_clk",
44 .pmc_mask = 1 << AT91SAM9260_ID_PIOB,
45 .type = CLK_TYPE_PERIPHERAL,
46};
47static struct clk pioC_clk = {
48 .name = "pioC_clk",
49 .pmc_mask = 1 << AT91SAM9260_ID_PIOC,
50 .type = CLK_TYPE_PERIPHERAL,
51};
52static struct clk adc_clk = {
53 .name = "adc_clk",
54 .pmc_mask = 1 << AT91SAM9260_ID_ADC,
55 .type = CLK_TYPE_PERIPHERAL,
56};
57static struct clk usart0_clk = {
58 .name = "usart0_clk",
59 .pmc_mask = 1 << AT91SAM9260_ID_US0,
60 .type = CLK_TYPE_PERIPHERAL,
61};
62static struct clk usart1_clk = {
63 .name = "usart1_clk",
64 .pmc_mask = 1 << AT91SAM9260_ID_US1,
65 .type = CLK_TYPE_PERIPHERAL,
66};
67static struct clk usart2_clk = {
68 .name = "usart2_clk",
69 .pmc_mask = 1 << AT91SAM9260_ID_US2,
70 .type = CLK_TYPE_PERIPHERAL,
71};
72static struct clk mmc_clk = {
73 .name = "mci_clk",
74 .pmc_mask = 1 << AT91SAM9260_ID_MCI,
75 .type = CLK_TYPE_PERIPHERAL,
76};
77static struct clk udc_clk = {
78 .name = "udc_clk",
79 .pmc_mask = 1 << AT91SAM9260_ID_UDP,
80 .type = CLK_TYPE_PERIPHERAL,
81};
82static struct clk twi_clk = {
83 .name = "twi_clk",
84 .pmc_mask = 1 << AT91SAM9260_ID_TWI,
85 .type = CLK_TYPE_PERIPHERAL,
86};
87static struct clk spi0_clk = {
88 .name = "spi0_clk",
89 .pmc_mask = 1 << AT91SAM9260_ID_SPI0,
90 .type = CLK_TYPE_PERIPHERAL,
91};
92static struct clk spi1_clk = {
93 .name = "spi1_clk",
94 .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
95 .type = CLK_TYPE_PERIPHERAL,
96};
Andrew Victore8788ba2007-05-02 17:14:57 +010097static struct clk ssc_clk = {
98 .name = "ssc_clk",
99 .pmc_mask = 1 << AT91SAM9260_ID_SSC,
100 .type = CLK_TYPE_PERIPHERAL,
101};
Andrew Victorc177a1e2007-02-08 10:25:38 +0100102static struct clk tc0_clk = {
103 .name = "tc0_clk",
104 .pmc_mask = 1 << AT91SAM9260_ID_TC0,
105 .type = CLK_TYPE_PERIPHERAL,
106};
107static struct clk tc1_clk = {
108 .name = "tc1_clk",
109 .pmc_mask = 1 << AT91SAM9260_ID_TC1,
110 .type = CLK_TYPE_PERIPHERAL,
111};
112static struct clk tc2_clk = {
113 .name = "tc2_clk",
114 .pmc_mask = 1 << AT91SAM9260_ID_TC2,
115 .type = CLK_TYPE_PERIPHERAL,
116};
Andrew Victor62c16602006-11-30 12:27:38 +0100117static struct clk ohci_clk = {
118 .name = "ohci_clk",
119 .pmc_mask = 1 << AT91SAM9260_ID_UHP,
120 .type = CLK_TYPE_PERIPHERAL,
121};
Andrew Victor69b2e992007-02-14 08:44:43 +0100122static struct clk macb_clk = {
123 .name = "macb_clk",
Andrew Victor62c16602006-11-30 12:27:38 +0100124 .pmc_mask = 1 << AT91SAM9260_ID_EMAC,
125 .type = CLK_TYPE_PERIPHERAL,
126};
127static struct clk isi_clk = {
128 .name = "isi_clk",
129 .pmc_mask = 1 << AT91SAM9260_ID_ISI,
130 .type = CLK_TYPE_PERIPHERAL,
131};
132static struct clk usart3_clk = {
133 .name = "usart3_clk",
134 .pmc_mask = 1 << AT91SAM9260_ID_US3,
135 .type = CLK_TYPE_PERIPHERAL,
136};
137static struct clk usart4_clk = {
138 .name = "usart4_clk",
139 .pmc_mask = 1 << AT91SAM9260_ID_US4,
140 .type = CLK_TYPE_PERIPHERAL,
141};
142static struct clk usart5_clk = {
143 .name = "usart5_clk",
144 .pmc_mask = 1 << AT91SAM9260_ID_US5,
145 .type = CLK_TYPE_PERIPHERAL,
146};
Andrew Victorc177a1e2007-02-08 10:25:38 +0100147static struct clk tc3_clk = {
148 .name = "tc3_clk",
149 .pmc_mask = 1 << AT91SAM9260_ID_TC3,
150 .type = CLK_TYPE_PERIPHERAL,
151};
152static struct clk tc4_clk = {
153 .name = "tc4_clk",
154 .pmc_mask = 1 << AT91SAM9260_ID_TC4,
155 .type = CLK_TYPE_PERIPHERAL,
156};
157static struct clk tc5_clk = {
158 .name = "tc5_clk",
159 .pmc_mask = 1 << AT91SAM9260_ID_TC5,
160 .type = CLK_TYPE_PERIPHERAL,
161};
Andrew Victor62c16602006-11-30 12:27:38 +0100162
163static struct clk *periph_clocks[] __initdata = {
164 &pioA_clk,
165 &pioB_clk,
166 &pioC_clk,
167 &adc_clk,
168 &usart0_clk,
169 &usart1_clk,
170 &usart2_clk,
171 &mmc_clk,
172 &udc_clk,
173 &twi_clk,
174 &spi0_clk,
175 &spi1_clk,
Andrew Victore8788ba2007-05-02 17:14:57 +0100176 &ssc_clk,
Andrew Victorc177a1e2007-02-08 10:25:38 +0100177 &tc0_clk,
178 &tc1_clk,
179 &tc2_clk,
Andrew Victor62c16602006-11-30 12:27:38 +0100180 &ohci_clk,
Andrew Victor69b2e992007-02-14 08:44:43 +0100181 &macb_clk,
Andrew Victor62c16602006-11-30 12:27:38 +0100182 &isi_clk,
183 &usart3_clk,
184 &usart4_clk,
185 &usart5_clk,
Andrew Victorc177a1e2007-02-08 10:25:38 +0100186 &tc3_clk,
187 &tc4_clk,
188 &tc5_clk,
Andrew Victor62c16602006-11-30 12:27:38 +0100189 // irq0 .. irq2
190};
191
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100192static struct clk_lookup periph_clocks_lookups[] = {
193 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
194 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
195 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
196 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
197 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
Jean-Christophe PLAGNIOL-VILLARD18089582011-11-28 12:53:08 +0100198 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
199 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
200 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100201 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
Jean-Christophe PLAGNIOL-VILLARDfea31582011-10-14 09:40:52 +0800202 /* more usart lookup table for DT entries */
203 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
204 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
205 CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
206 CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
207 CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
208 CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
209 CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
Jean-Christophe PLAGNIOL-VILLARD0af43162011-08-30 03:29:28 +0200210 /* fake hclk clock */
211 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100212};
213
214static struct clk_lookup usart_clocks_lookups[] = {
215 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
216 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
217 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
218 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
219 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
220 CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
221 CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
222};
223
Andrew Victor62c16602006-11-30 12:27:38 +0100224/*
225 * The two programmable clocks.
226 * You must configure pin multiplexing to bring these signals out.
227 */
228static struct clk pck0 = {
229 .name = "pck0",
230 .pmc_mask = AT91_PMC_PCK0,
231 .type = CLK_TYPE_PROGRAMMABLE,
232 .id = 0,
233};
234static struct clk pck1 = {
235 .name = "pck1",
236 .pmc_mask = AT91_PMC_PCK1,
237 .type = CLK_TYPE_PROGRAMMABLE,
238 .id = 1,
239};
240
241static void __init at91sam9260_register_clocks(void)
242{
243 int i;
244
245 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
246 clk_register(periph_clocks[i]);
247
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100248 clkdev_add_table(periph_clocks_lookups,
249 ARRAY_SIZE(periph_clocks_lookups));
250 clkdev_add_table(usart_clocks_lookups,
251 ARRAY_SIZE(usart_clocks_lookups));
252
Andrew Victor62c16602006-11-30 12:27:38 +0100253 clk_register(&pck0);
254 clk_register(&pck1);
255}
256
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100257static struct clk_lookup console_clock_lookup;
258
259void __init at91sam9260_set_console_clock(int id)
260{
261 if (id >= ARRAY_SIZE(usart_clocks_lookups))
262 return;
263
264 console_clock_lookup.con_id = "usart";
265 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
266 clkdev_add(&console_clock_lookup);
267}
268
Andrew Victor62c16602006-11-30 12:27:38 +0100269/* --------------------------------------------------------------------
270 * GPIO
271 * -------------------------------------------------------------------- */
272
273static struct at91_gpio_bank at91sam9260_gpio[] = {
274 {
275 .id = AT91SAM9260_ID_PIOA,
276 .offset = AT91_PIOA,
277 .clock = &pioA_clk,
278 }, {
279 .id = AT91SAM9260_ID_PIOB,
280 .offset = AT91_PIOB,
281 .clock = &pioB_clk,
282 }, {
283 .id = AT91SAM9260_ID_PIOC,
284 .offset = AT91_PIOC,
285 .clock = &pioC_clk,
286 }
287};
288
Andrew Victor3ef2fb42008-04-02 21:36:06 +0100289static void at91sam9260_poweroff(void)
290{
291 at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
292}
293
Andrew Victor62c16602006-11-30 12:27:38 +0100294
295/* --------------------------------------------------------------------
296 * AT91SAM9260 processor initialization
297 * -------------------------------------------------------------------- */
298
Jean-Christophe PLAGNIOL-VILLARD1b021a32011-04-28 20:19:32 +0800299static void __init at91sam9xe_map_io(void)
Andrew Victorf7eee892007-02-15 08:17:38 +0100300{
Jean-Christophe PLAGNIOL-VILLARD8c3583b2011-04-23 22:12:57 +0800301 unsigned long sram_size;
Andrew Victorf7eee892007-02-15 08:17:38 +0100302
Jean-Christophe PLAGNIOL-VILLARD8c3583b2011-04-23 22:12:57 +0800303 switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
Andrew Victorf7eee892007-02-15 08:17:38 +0100304 case AT91_CIDR_SRAMSIZ_32K:
305 sram_size = 2 * SZ_16K;
306 break;
307 case AT91_CIDR_SRAMSIZ_16K:
308 default:
309 sram_size = SZ_16K;
310 }
311
Jean-Christophe PLAGNIOL-VILLARDf0051d82011-05-10 03:20:09 +0800312 at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
Andrew Victorf7eee892007-02-15 08:17:38 +0100313}
314
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800315static void __init at91sam9260_map_io(void)
Andrew Victor62c16602006-11-30 12:27:38 +0100316{
Jean-Christophe PLAGNIOL-VILLARDf0051d82011-05-10 03:20:09 +0800317 if (cpu_is_at91sam9xe()) {
Jean-Christophe PLAGNIOL-VILLARD1b021a32011-04-28 20:19:32 +0800318 at91sam9xe_map_io();
Jean-Christophe PLAGNIOL-VILLARDf0051d82011-05-10 03:20:09 +0800319 } else if (cpu_is_at91sam9g20()) {
320 at91_init_sram(0, AT91SAM9G20_SRAM0_BASE, AT91SAM9G20_SRAM0_SIZE);
321 at91_init_sram(1, AT91SAM9G20_SRAM1_BASE, AT91SAM9G20_SRAM1_SIZE);
322 } else {
323 at91_init_sram(0, AT91SAM9260_SRAM0_BASE, AT91SAM9260_SRAM0_SIZE);
324 at91_init_sram(1, AT91SAM9260_SRAM1_BASE, AT91SAM9260_SRAM1_SIZE);
325 }
Jean-Christophe PLAGNIOL-VILLARD1b021a32011-04-28 20:19:32 +0800326}
Andrew Victorf7eee892007-02-15 08:17:38 +0100327
Jean-Christophe PLAGNIOL-VILLARD46539372011-04-24 18:20:28 +0800328static void __init at91sam9260_initialize(void)
Jean-Christophe PLAGNIOL-VILLARD1b021a32011-04-28 20:19:32 +0800329{
Russell King1b2073e2011-11-03 09:53:29 +0000330 arm_pm_restart = at91sam9_alt_restart;
Andrew Victor3ef2fb42008-04-02 21:36:06 +0100331 pm_power_off = at91sam9260_poweroff;
Andrew Victor62c16602006-11-30 12:27:38 +0100332 at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
333 | (1 << AT91SAM9260_ID_IRQ2);
334
Andrew Victor62c16602006-11-30 12:27:38 +0100335 /* Register GPIO subsystem */
336 at91_gpio_init(at91sam9260_gpio, 3);
337}
338
339/* --------------------------------------------------------------------
340 * Interrupt initialization
341 * -------------------------------------------------------------------- */
342
343/*
344 * The default interrupt priority levels (0 = lowest, 7 = highest).
345 */
346static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
347 7, /* Advanced Interrupt Controller */
348 7, /* System Peripherals */
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100349 1, /* Parallel IO Controller A */
350 1, /* Parallel IO Controller B */
351 1, /* Parallel IO Controller C */
Andrew Victor62c16602006-11-30 12:27:38 +0100352 0, /* Analog-to-Digital Converter */
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100353 5, /* USART 0 */
354 5, /* USART 1 */
355 5, /* USART 2 */
Andrew Victor62c16602006-11-30 12:27:38 +0100356 0, /* Multimedia Card Interface */
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100357 2, /* USB Device Port */
358 6, /* Two-Wire Interface */
359 5, /* Serial Peripheral Interface 0 */
360 5, /* Serial Peripheral Interface 1 */
Andrew Victor62c16602006-11-30 12:27:38 +0100361 5, /* Serial Synchronous Controller */
362 0,
363 0,
364 0, /* Timer Counter 0 */
365 0, /* Timer Counter 1 */
366 0, /* Timer Counter 2 */
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100367 2, /* USB Host port */
Andrew Victor62c16602006-11-30 12:27:38 +0100368 3, /* Ethernet */
369 0, /* Image Sensor Interface */
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100370 5, /* USART 3 */
371 5, /* USART 4 */
372 5, /* USART 5 */
Andrew Victor62c16602006-11-30 12:27:38 +0100373 0, /* Timer Counter 3 */
374 0, /* Timer Counter 4 */
375 0, /* Timer Counter 5 */
376 0, /* Advanced Interrupt Controller */
377 0, /* Advanced Interrupt Controller */
378 0, /* Advanced Interrupt Controller */
379};
380
Jean-Christophe PLAGNIOL-VILLARD8c3583b2011-04-23 22:12:57 +0800381struct at91_init_soc __initdata at91sam9260_soc = {
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800382 .map_io = at91sam9260_map_io,
Jean-Christophe PLAGNIOL-VILLARD92100c12011-04-23 15:28:34 +0800383 .default_irq_priority = at91sam9260_default_irq_priority,
Jean-Christophe PLAGNIOL-VILLARD51ddec72011-04-24 18:15:34 +0800384 .register_clocks = at91sam9260_register_clocks,
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800385 .init = at91sam9260_initialize,
386};