Blame - drivers/irqchip/Kconfig - kernel/msm-4.19

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Thomas Petazzoni	f6e916b	2012-11-20 23:00:52 +0100	[diff] [blame]	1	config IRQCHIP
				2	def_bool y
				3	depends on OF_IRQ
				4
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	5	config ARM_GIC
				6	bool
				7	select IRQ_DOMAIN
Yingjoe Chen	9a1091e	2014-11-25 16:04:19 +0800	[diff] [blame]	8	select IRQ_DOMAIN_HIERARCHY
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	9	select MULTI_IRQ_HANDLER
				10
Linus Walleij	a27d21e	2015-12-18 10:44:53 +0100	[diff] [blame]	11	config ARM_GIC_MAX_NR
				12	int
				13	default 2 if ARCH_REALVIEW
				14	default 1
				15
Suravee Suthikulpanit	853a33c	2014-11-25 18:47:22 +0000	[diff] [blame]	16	config ARM_GIC_V2M
				17	bool
Arnd Bergmann	3ee8036	2016-06-15 15:47:33 -0500	[diff] [blame^]	18	depends on PCI
				19	select ARM_GIC
				20	select PCI_MSI
Suravee Suthikulpanit	853a33c	2014-11-25 18:47:22 +0000	[diff] [blame]	21
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	22	config GIC_NON_BANKED
				23	bool
				24
Marc Zyngier	021f653	2014-06-30 16:01:31 +0100	[diff] [blame]	25	config ARM_GIC_V3
				26	bool
				27	select IRQ_DOMAIN
				28	select MULTI_IRQ_HANDLER
Marc Zyngier	443acc4	2014-11-24 14:35:09 +0000	[diff] [blame]	29	select IRQ_DOMAIN_HIERARCHY
Marc Zyngier	e3825ba	2016-04-11 09:57:54 +0100	[diff] [blame]	30	select PARTITION_PERCPU
Marc Zyngier	021f653	2014-06-30 16:01:31 +0100	[diff] [blame]	31
Marc Zyngier	1981272	2014-11-24 14:35:19 +0000	[diff] [blame]	32	config ARM_GIC_V3_ITS
				33	bool
Arnd Bergmann	3ee8036	2016-06-15 15:47:33 -0500	[diff] [blame^]	34	depends on PCI
				35	depends on PCI_MSI
Uwe Kleine-König	292ec08	2013-06-26 09:18:48 +0200	[diff] [blame]	36
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	37	config ARM_NVIC
				38	bool
				39	select IRQ_DOMAIN
Stefan Agner	2d9f59f	2015-05-16 11:44:16 +0200	[diff] [blame]	40	select IRQ_DOMAIN_HIERARCHY
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	41	select GENERIC_IRQ_CHIP
				42
				43	config ARM_VIC
				44	bool
				45	select IRQ_DOMAIN
				46	select MULTI_IRQ_HANDLER
				47
				48	config ARM_VIC_NR
				49	int
				50	default 4 if ARCH_S5PV210
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	51	default 2
				52	depends on ARM_VIC
				53	help
				54	The maximum number of VICs available in the system, for
				55	power management.
				56
Thomas Petazzoni	fed6d33	2016-02-10 15:46:56 +0100	[diff] [blame]	57	config ARMADA_370_XP_IRQ
				58	bool
Thomas Petazzoni	fed6d33	2016-02-10 15:46:56 +0100	[diff] [blame]	59	select GENERIC_IRQ_CHIP
Arnd Bergmann	3ee8036	2016-06-15 15:47:33 -0500	[diff] [blame^]	60	select PCI_MSI if PCI
Thomas Petazzoni	fed6d33	2016-02-10 15:46:56 +0100	[diff] [blame]	61
Antoine Tenart	e6b78f2	2016-02-19 16:22:44 +0100	[diff] [blame]	62	config ALPINE_MSI
				63	bool
Arnd Bergmann	3ee8036	2016-06-15 15:47:33 -0500	[diff] [blame^]	64	depends on PCI
				65	select PCI_MSI
Antoine Tenart	e6b78f2	2016-02-19 16:22:44 +0100	[diff] [blame]	66	select GENERIC_IRQ_CHIP
Antoine Tenart	e6b78f2	2016-02-19 16:22:44 +0100	[diff] [blame]	67
Boris BREZILLON	b1479eb	2014-07-10 19:14:18 +0200	[diff] [blame]	68	config ATMEL_AIC_IRQ
				69	bool
				70	select GENERIC_IRQ_CHIP
				71	select IRQ_DOMAIN
				72	select MULTI_IRQ_HANDLER
				73	select SPARSE_IRQ
				74
				75	config ATMEL_AIC5_IRQ
				76	bool
				77	select GENERIC_IRQ_CHIP
				78	select IRQ_DOMAIN
				79	select MULTI_IRQ_HANDLER
				80	select SPARSE_IRQ
				81
Ralf Baechle	0509cfd	2015-07-08 14:46:08 +0200	[diff] [blame]	82	config I8259
				83	bool
				84	select IRQ_DOMAIN
				85
Simon Arlott	c7c42ec	2015-11-22 14:30:14 +0000	[diff] [blame]	86	config BCM6345_L1_IRQ
				87	bool
				88	select GENERIC_IRQ_CHIP
				89	select IRQ_DOMAIN
				90
Kevin Cernekee	5f7f031	2014-12-25 09:49:06 -0800	[diff] [blame]	91	config BCM7038_L1_IRQ
				92	bool
				93	select GENERIC_IRQ_CHIP
				94	select IRQ_DOMAIN
				95
Kevin Cernekee	a4fcbb8	2014-11-06 22:44:27 -0800	[diff] [blame]	96	config BCM7120_L2_IRQ
				97	bool
				98	select GENERIC_IRQ_CHIP
				99	select IRQ_DOMAIN
				100
Florian Fainelli	7f646e9	2014-05-23 17:40:53 -0700	[diff] [blame]	101	config BRCMSTB_L2_IRQ
				102	bool
Florian Fainelli	7f646e9	2014-05-23 17:40:53 -0700	[diff] [blame]	103	select GENERIC_IRQ_CHIP
				104	select IRQ_DOMAIN
				105
Sebastian Hesselbarth	350d71b9	2013-09-09 14:01:20 +0200	[diff] [blame]	106	config DW_APB_ICTL
				107	bool
Jisheng Zhang	e158849	2014-10-22 20:59:10 +0800	[diff] [blame]	108	select GENERIC_IRQ_CHIP
Sebastian Hesselbarth	350d71b9	2013-09-09 14:01:20 +0200	[diff] [blame]	109	select IRQ_DOMAIN
				110
MaJun	9a7c4ab	2016-03-23 17:06:33 +0800	[diff] [blame]	111	config HISILICON_IRQ_MBIGEN
				112	bool
				113	select ARM_GIC_V3
				114	select ARM_GIC_V3_ITS
MaJun	9a7c4ab	2016-03-23 17:06:33 +0800	[diff] [blame]	115
James Hogan	b6ef916	2013-04-22 15:43:50 +0100	[diff] [blame]	116	config IMGPDC_IRQ
				117	bool
				118	select GENERIC_IRQ_CHIP
				119	select IRQ_DOMAIN
				120
Ralf Baechle	67e38cf	2015-05-26 18:20:06 +0200	[diff] [blame]	121	config IRQ_MIPS_CPU
				122	bool
				123	select GENERIC_IRQ_CHIP
				124	select IRQ_DOMAIN
				125
Alexander Shiyan	afc98d9	2014-02-02 12:07:46 +0400	[diff] [blame]	126	config CLPS711X_IRQCHIP
				127	bool
				128	depends on ARCH_CLPS711X
				129	select IRQ_DOMAIN
				130	select MULTI_IRQ_HANDLER
				131	select SPARSE_IRQ
				132	default y
				133
Stefan Kristiansson	4db8e6d	2014-05-26 23:31:42 +0300	[diff] [blame]	134	config OR1K_PIC
				135	bool
				136	select IRQ_DOMAIN
				137
Felipe Balbi	8598066	2014-09-15 16:15:02 -0500	[diff] [blame]	138	config OMAP_IRQCHIP
				139	bool
				140	select GENERIC_IRQ_CHIP
				141	select IRQ_DOMAIN
				142
Sebastian Hesselbarth	9dbd90f	2013-06-06 18:27:09 +0200	[diff] [blame]	143	config ORION_IRQCHIP
				144	bool
				145	select IRQ_DOMAIN
				146	select MULTI_IRQ_HANDLER
				147
Cristian Birsan	aaa8666	2016-01-13 18:15:35 -0700	[diff] [blame]	148	config PIC32_EVIC
				149	bool
				150	select GENERIC_IRQ_CHIP
				151	select IRQ_DOMAIN
				152
Magnus Damm	4435804	2013-02-18 23:28:34 +0900	[diff] [blame]	153	config RENESAS_INTC_IRQPIN
				154	bool
				155	select IRQ_DOMAIN
				156
Magnus Damm	fbc83b7	2013-02-27 17:15:01 +0900	[diff] [blame]	157	config RENESAS_IRQC
				158	bool
Magnus Damm	99c221d	2015-09-28 18:42:37 +0900	[diff] [blame]	159	select GENERIC_IRQ_CHIP
Magnus Damm	fbc83b7	2013-02-27 17:15:01 +0900	[diff] [blame]	160	select IRQ_DOMAIN
				161
Lee Jones	0708848	2015-02-18 15:13:58 +0000	[diff] [blame]	162	config ST_IRQCHIP
				163	bool
				164	select REGMAP
				165	select MFD_SYSCON
				166	help
				167	Enables SysCfg Controlled IRQs on STi based platforms.
				168
Mans Rullgard	4bba668	2016-01-20 18:07:17 +0000	[diff] [blame]	169	config TANGO_IRQ
				170	bool
				171	select IRQ_DOMAIN
				172	select GENERIC_IRQ_CHIP
				173
Christian Ruppert	b06eb01	2013-06-25 18:29:57 +0200	[diff] [blame]	174	config TB10X_IRQC
				175	bool
				176	select IRQ_DOMAIN
				177	select GENERIC_IRQ_CHIP
				178
Damien Riegel	d01f863	2015-12-21 15:11:23 -0500	[diff] [blame]	179	config TS4800_IRQ
				180	tristate "TS-4800 IRQ controller"
				181	select IRQ_DOMAIN
Richard Weinberger	0df337c	2016-01-25 23:24:17 +0100	[diff] [blame]	182	depends on HAS_IOMEM
Jean Delvare	d2b383d	2016-02-09 11:19:20 +0100	[diff] [blame]	183	depends on SOC_IMX51 \|\| COMPILE_TEST
Damien Riegel	d01f863	2015-12-21 15:11:23 -0500	[diff] [blame]	184	help
				185	Support for the TS-4800 FPGA IRQ controller
				186
Linus Walleij	2389d50	2012-10-31 22:04:31 +0100	[diff] [blame]	187	config VERSATILE_FPGA_IRQ
				188	bool
				189	select IRQ_DOMAIN
				190
				191	config VERSATILE_FPGA_IRQ_NR
				192	int
				193	default 4
				194	depends on VERSATILE_FPGA_IRQ
Max Filippov	26a8e96	2013-12-01 12:04:57 +0400	[diff] [blame]	195
				196	config XTENSA_MX
				197	bool
				198	select IRQ_DOMAIN
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	199
				200	config IRQ_CROSSBAR
				201	bool
				202	help
Masanari Iida	f54619f	2014-09-18 12:09:42 +0900	[diff] [blame]	203	Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	204	The primary irqchip invokes the crossbar's callback which inturn allocates
				205	a free irq and configures the IP. Thus the peripheral interrupts are
				206	routed to one of the free irqchip interrupt lines.
Grygorii Strashko	89323f8	2014-07-23 17:40:30 +0300	[diff] [blame]	207
				208	config KEYSTONE_IRQ
				209	tristate "Keystone 2 IRQ controller IP"
				210	depends on ARCH_KEYSTONE
				211	help
				212	Support for Texas Instruments Keystone 2 IRQ controller IP which
				213	is part of the Keystone 2 IPC mechanism
Andrew Bresticker	8a19b8f	2014-09-18 14:47:19 -0700	[diff] [blame]	214
				215	config MIPS_GIC
				216	bool
Qais Yousef	bb11cff	2015-12-08 13:20:28 +0000	[diff] [blame]	217	select GENERIC_IRQ_IPI
Qais Yousef	2af70a9	2015-12-08 13:20:23 +0000	[diff] [blame]	218	select IRQ_DOMAIN_HIERARCHY
Andrew Bresticker	8a19b8f	2014-09-18 14:47:19 -0700	[diff] [blame]	219	select MIPS_CM
Yoshinori Sato	8a76448	2015-05-10 02:30:47 +0900	[diff] [blame]	220
Paul Burton	44e08e7	2015-05-24 16:11:31 +0100	[diff] [blame]	221	config INGENIC_IRQ
				222	bool
				223	depends on MACH_INGENIC
				224	default y
Linus Torvalds	78c10e5	2015-06-27 12:44:34 -0700	[diff] [blame]	225
Yoshinori Sato	8a76448	2015-05-10 02:30:47 +0900	[diff] [blame]	226	config RENESAS_H8300H_INTC
				227	bool
				228	select IRQ_DOMAIN
				229
				230	config RENESAS_H8S_INTC
				231	bool
Linus Torvalds	78c10e5	2015-06-27 12:44:34 -0700	[diff] [blame]	232	select IRQ_DOMAIN
Shenwei Wang	e324c4d	2015-08-24 14:04:15 -0500	[diff] [blame]	233
				234	config IMX_GPCV2
				235	bool
				236	select IRQ_DOMAIN
				237	help
				238	Enables the wakeup IRQs for IMX platforms with GPCv2 block
Oleksij Rempel	7e4ac67	2015-10-12 21:15:34 +0200	[diff] [blame]	239
				240	config IRQ_MXS
				241	def_bool y if MACH_ASM9260 \|\| ARCH_MXS
				242	select IRQ_DOMAIN
				243	select STMP_DEVICE
Thomas Petazzoni	c27f29b	2016-02-19 14:34:43 +0100	[diff] [blame]	244
				245	config MVEBU_ODMI
				246	bool
Marc Zyngier	9e2c986	2016-04-11 09:57:53 +0100	[diff] [blame]	247
Minghuan Lian	b8f3ebe	2016-03-23 19:08:20 +0800	[diff] [blame]	248	config LS_SCFG_MSI
				249	def_bool y if SOC_LS1021A \|\| ARCH_LAYERSCAPE
				250	depends on PCI && PCI_MSI
Minghuan Lian	b8f3ebe	2016-03-23 19:08:20 +0800	[diff] [blame]	251
Marc Zyngier	9e2c986	2016-04-11 09:57:53 +0100	[diff] [blame]	252	config PARTITION_PERCPU
				253	bool
Linus Torvalds	0efacbb	2016-05-19 09:46:18 -0700	[diff] [blame]	254
Noam Camus	44df427c	2015-10-29 00:26:22 +0200	[diff] [blame]	255	config EZNPS_GIC
				256	bool "NPS400 Global Interrupt Manager (GIM)"
Arnd Bergmann	ffd565e	2016-05-12 23:03:35 +0200	[diff] [blame]	257	depends on ARC \|\| (COMPILE_TEST && !64BIT)
Noam Camus	44df427c	2015-10-29 00:26:22 +0200	[diff] [blame]	258	select IRQ_DOMAIN
				259	help
				260	Support the EZchip NPS400 global interrupt controller