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gerrit-public.fairphone.software / kernel / msm-4.19 / 55b4452b4b7082ecf3cc2095bc21762a901a8ca2 / . / arch / arm / boot / dts / am33xx.dtsi
blob: 553adc6b535e775774bc4a99a0ffcab314642137 [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard6a8a6b62013-06-03 16:12:25 +0200[diff] [blame]12#include <dt-bindings/pinctrl/am33xx.h>
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]13
Florian Vaussardeb33ef662013-06-03 16:12:22 +0200[diff] [blame]14#include "skeleton.dtsi"
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]15
16/ {
17 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]18 interrupt-parent = <&intc>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]19
20 aliases {
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]21 serial0 = &uart0;
22 serial1 = &uart1;
23 serial2 = &uart2;
24 serial3 = &uart3;
25 serial4 = &uart4;
26 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]27 d_can0 = &dcan0;
28 d_can1 = &dcan1;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]29 usb0 = &usb0;
30 usb1 = &usb1;
31 phy0 = &usb0_phy;
32 phy1 = &usb1_phy;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]33 };
34
35 cpus {
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]36 #address-cells = <1>;
37 #size-cells = <0>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]38 cpu@0 {
39 compatible = "arm,cortex-a8";
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]40 device_type = "cpu";
41 reg = <0>;
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]42
43 /*
44 * To consider voltage drop between PMIC and SoC,
45 * tolerance value is reduced to 2% from 4% and
46 * voltage value is increased as a precaution.
47 */
48 operating-points = <
49 /* kHz uV */
50 720000 1285000
51 600000 1225000
52 500000 1125000
53 275000 1125000
54 >;
55 voltage-tolerance = <2>; /* 2 percentage */
56 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]57 };
58 };
59
Alexandre Belloni6797cdb2013-08-03 20:00:54 +0200[diff] [blame]60 pmu {
61 compatible = "arm,cortex-a8-pmu";
62 interrupts = <3>;
63 };
64
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]65 /*
66 * The soc node represents the soc top level view. It is uses for IPs
67 * that are not memory mapped in the MPU view or for the MPU itself.
68 */
69 soc {
70 compatible = "ti,omap-infra";
71 mpu {
72 compatible = "ti,omap3-mpu";
73 ti,hwmods = "mpu";
74 };
75 };
76
AnilKumar Chb552dfc2012-09-20 02:49:26 +0530[diff] [blame]77 am33xx_pinmux: pinmux@44e10800 {
78 compatible = "pinctrl-single";
79 reg = <0x44e10800 0x0238>;
80 #address-cells = <1>;
81 #size-cells = <0>;
82 pinctrl-single,register-width = <32>;
83 pinctrl-single,function-mask = <0x7f>;
84 };
85
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]86 /*
87 * XXX: Use a flat representation of the AM33XX interconnect.
88 * The real AM33XX interconnect network is quite complex.Since
89 * that will not bring real advantage to represent that in DT
90 * for the moment, just use a fake OCP bus entry to represent
91 * the whole bus hierarchy.
92 */
93 ocp {
94 compatible = "simple-bus";
95 #address-cells = <1>;
96 #size-cells = <1>;
97 ranges;
98 ti,hwmods = "l3_main";
99
100 intc: interrupt-controller@48200000 {
101 compatible = "ti,omap2-intc";
102 interrupt-controller;
103 #interrupt-cells = <1>;
104 ti,intc-size = <128>;
105 reg = <0x48200000 0x1000>;
106 };
107
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]108 edma: edma@49000000 {
109 compatible = "ti,edma3";
110 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
111 reg = <0x49000000 0x10000>,
112 <0x44e10f90 0x10>;
113 interrupts = <12 13 14>;
114 #dma-cells = <1>;
115 dma-channels = <64>;
116 ti,edma-regions = <4>;
117 ti,edma-slots = <256>;
118 };
119
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]120 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]121 compatible = "ti,omap4-gpio";
122 ti,hwmods = "gpio1";
123 gpio-controller;
124 #gpio-cells = <2>;
125 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]126 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]127 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]128 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]129 };
130
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]131 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]132 compatible = "ti,omap4-gpio";
133 ti,hwmods = "gpio2";
134 gpio-controller;
135 #gpio-cells = <2>;
136 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]137 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]138 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]139 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]140 };
141
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]142 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]143 compatible = "ti,omap4-gpio";
144 ti,hwmods = "gpio3";
145 gpio-controller;
146 #gpio-cells = <2>;
147 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]148 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]149 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]150 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]151 };
152
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]153 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]154 compatible = "ti,omap4-gpio";
155 ti,hwmods = "gpio4";
156 gpio-controller;
157 #gpio-cells = <2>;
158 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]159 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]160 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]161 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]162 };
163
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]164 uart0: serial@44e09000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]165 compatible = "ti,omap3-uart";
166 ti,hwmods = "uart1";
167 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]168 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]169 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]170 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]171 };
172
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]173 uart1: serial@48022000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]174 compatible = "ti,omap3-uart";
175 ti,hwmods = "uart2";
176 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]177 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]178 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]179 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]180 };
181
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]182 uart2: serial@48024000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]183 compatible = "ti,omap3-uart";
184 ti,hwmods = "uart3";
185 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]186 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]187 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]188 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]189 };
190
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]191 uart3: serial@481a6000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]192 compatible = "ti,omap3-uart";
193 ti,hwmods = "uart4";
194 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]195 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]196 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]197 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]198 };
199
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]200 uart4: serial@481a8000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]201 compatible = "ti,omap3-uart";
202 ti,hwmods = "uart5";
203 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]204 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]205 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]206 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]207 };
208
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]209 uart5: serial@481aa000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]210 compatible = "ti,omap3-uart";
211 ti,hwmods = "uart6";
212 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]213 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]214 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]215 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]216 };
217
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]218 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]219 compatible = "ti,omap4-i2c";
220 #address-cells = <1>;
221 #size-cells = <0>;
222 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]223 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]224 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]225 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]226 };
227
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]228 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]229 compatible = "ti,omap4-i2c";
230 #address-cells = <1>;
231 #size-cells = <0>;
232 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]233 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]234 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]235 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]236 };
237
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]238 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]239 compatible = "ti,omap4-i2c";
240 #address-cells = <1>;
241 #size-cells = <0>;
242 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]243 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]244 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]245 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]246 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]247
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame^]248 mmc1: mmc@48060000 {
249 compatible = "ti,omap4-hsmmc";
250 ti,hwmods = "mmc1";
251 ti,dual-volt;
252 ti,needs-special-reset;
253 ti,needs-special-hs-handling;
254 dmas = <&edma 24
255 &edma 25>;
256 dma-names = "tx", "rx";
257 interrupts = <64>;
258 interrupt-parent = <&intc>;
259 reg = <0x48060000 0x1000>;
260 status = "disabled";
261 };
262
263 mmc2: mmc@481d8000 {
264 compatible = "ti,omap4-hsmmc";
265 ti,hwmods = "mmc2";
266 ti,needs-special-reset;
267 dmas = <&edma 2
268 &edma 3>;
269 dma-names = "tx", "rx";
270 interrupts = <28>;
271 interrupt-parent = <&intc>;
272 reg = <0x481d8000 0x1000>;
273 status = "disabled";
274 };
275
276 mmc3: mmc@47810000 {
277 compatible = "ti,omap4-hsmmc";
278 ti,hwmods = "mmc3";
279 ti,needs-special-reset;
280 interrupts = <29>;
281 interrupt-parent = <&intc>;
282 reg = <0x47810000 0x1000>;
283 status = "disabled";
284 };
285
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]286 wdt2: wdt@44e35000 {
287 compatible = "ti,omap3-wdt";
288 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]289 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]290 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]291 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]292
293 dcan0: d_can@481cc000 {
294 compatible = "bosch,d_can";
295 ti,hwmods = "d_can0";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]296 reg = <0x481cc000 0x2000
297 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]298 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]299 status = "disabled";
300 };
301
302 dcan1: d_can@481d0000 {
303 compatible = "bosch,d_can";
304 ti,hwmods = "d_can1";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]305 reg = <0x481d0000 0x2000
306 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]307 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]308 status = "disabled";
309 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]310
311 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]312 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]313 reg = <0x44e31000 0x400>;
314 interrupts = <67>;
315 ti,hwmods = "timer1";
316 ti,timer-alwon;
317 };
318
319 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]320 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]321 reg = <0x48040000 0x400>;
322 interrupts = <68>;
323 ti,hwmods = "timer2";
324 };
325
326 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]327 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]328 reg = <0x48042000 0x400>;
329 interrupts = <69>;
330 ti,hwmods = "timer3";
331 };
332
333 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]334 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]335 reg = <0x48044000 0x400>;
336 interrupts = <92>;
337 ti,hwmods = "timer4";
338 ti,timer-pwm;
339 };
340
341 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]342 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]343 reg = <0x48046000 0x400>;
344 interrupts = <93>;
345 ti,hwmods = "timer5";
346 ti,timer-pwm;
347 };
348
349 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]350 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]351 reg = <0x48048000 0x400>;
352 interrupts = <94>;
353 ti,hwmods = "timer6";
354 ti,timer-pwm;
355 };
356
357 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]358 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]359 reg = <0x4804a000 0x400>;
360 interrupts = <95>;
361 ti,hwmods = "timer7";
362 ti,timer-pwm;
363 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]364
365 rtc@44e3e000 {
366 compatible = "ti,da830-rtc";
367 reg = <0x44e3e000 0x1000>;
368 interrupts = <75
369 76>;
370 ti,hwmods = "rtc";
371 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]372
373 spi0: spi@48030000 {
374 compatible = "ti,omap4-mcspi";
375 #address-cells = <1>;
376 #size-cells = <0>;
377 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]378 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]379 ti,spi-num-cs = <2>;
380 ti,hwmods = "spi0";
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]381 dmas = <&edma 16
382 &edma 17
383 &edma 18
384 &edma 19>;
385 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]386 status = "disabled";
387 };
388
389 spi1: spi@481a0000 {
390 compatible = "ti,omap4-mcspi";
391 #address-cells = <1>;
392 #size-cells = <0>;
393 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]394 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]395 ti,spi-num-cs = <2>;
396 ti,hwmods = "spi1";
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]397 dmas = <&edma 42
398 &edma 43
399 &edma 44
400 &edma 45>;
401 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]402 status = "disabled";
403 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]404
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]405 usb: usb@47400000 {
406 compatible = "ti,am33xx-usb";
407 reg = <0x47400000 0x1000>;
408 ranges;
409 #address-cells = <1>;
410 #size-cells = <1>;
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]411 ti,hwmods = "usb_otg_hs";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]412 status = "disabled";
413
414 ctrl_mod: control@44e10000 {
415 compatible = "ti,am335x-usb-ctrl-module";
416 reg = <0x44e10620 0x10
417 0x44e10648 0x4>;
418 reg-names = "phy_ctrl", "wakeup";
419 status = "disabled";
420 };
421
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]422 usb0_phy: usb-phy@47401300 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]423 compatible = "ti,am335x-usb-phy";
424 reg = <0x47401300 0x100>;
425 reg-names = "phy";
426 status = "disabled";
427 ti,ctrl_mod = <&ctrl_mod>;
428 };
429
430 usb0: usb@47401000 {
431 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]432 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]433 reg = <0x47401400 0x400
434 0x47401000 0x200>;
435 reg-names = "mc", "control";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]436
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]437 interrupts = <18>;
438 interrupt-names = "mc";
439 dr_mode = "otg";
440 mentor,multipoint = <1>;
441 mentor,num-eps = <16>;
442 mentor,ram-bits = <12>;
443 mentor,power = <500>;
444 phys = <&usb0_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]445
446 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
447 &cppi41dma 2 0 &cppi41dma 3 0
448 &cppi41dma 4 0 &cppi41dma 5 0
449 &cppi41dma 6 0 &cppi41dma 7 0
450 &cppi41dma 8 0 &cppi41dma 9 0
451 &cppi41dma 10 0 &cppi41dma 11 0
452 &cppi41dma 12 0 &cppi41dma 13 0
453 &cppi41dma 14 0 &cppi41dma 0 1
454 &cppi41dma 1 1 &cppi41dma 2 1
455 &cppi41dma 3 1 &cppi41dma 4 1
456 &cppi41dma 5 1 &cppi41dma 6 1
457 &cppi41dma 7 1 &cppi41dma 8 1
458 &cppi41dma 9 1 &cppi41dma 10 1
459 &cppi41dma 11 1 &cppi41dma 12 1
460 &cppi41dma 13 1 &cppi41dma 14 1>;
461 dma-names =
462 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
463 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
464 "rx14", "rx15",
465 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
466 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
467 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]468 };
469
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]470 usb1_phy: usb-phy@47401b00 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]471 compatible = "ti,am335x-usb-phy";
472 reg = <0x47401b00 0x100>;
473 reg-names = "phy";
474 status = "disabled";
475 ti,ctrl_mod = <&ctrl_mod>;
476 };
477
478 usb1: usb@47401800 {
479 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]480 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]481 reg = <0x47401c00 0x400
482 0x47401800 0x200>;
483 reg-names = "mc", "control";
484 interrupts = <19>;
485 interrupt-names = "mc";
486 dr_mode = "otg";
487 mentor,multipoint = <1>;
488 mentor,num-eps = <16>;
489 mentor,ram-bits = <12>;
490 mentor,power = <500>;
491 phys = <&usb1_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]492
493 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
494 &cppi41dma 17 0 &cppi41dma 18 0
495 &cppi41dma 19 0 &cppi41dma 20 0
496 &cppi41dma 21 0 &cppi41dma 22 0
497 &cppi41dma 23 0 &cppi41dma 24 0
498 &cppi41dma 25 0 &cppi41dma 26 0
499 &cppi41dma 27 0 &cppi41dma 28 0
500 &cppi41dma 29 0 &cppi41dma 15 1
501 &cppi41dma 16 1 &cppi41dma 17 1
502 &cppi41dma 18 1 &cppi41dma 19 1
503 &cppi41dma 20 1 &cppi41dma 21 1
504 &cppi41dma 22 1 &cppi41dma 23 1
505 &cppi41dma 24 1 &cppi41dma 25 1
506 &cppi41dma 26 1 &cppi41dma 27 1
507 &cppi41dma 28 1 &cppi41dma 29 1>;
508 dma-names =
509 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
510 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
511 "rx14", "rx15",
512 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
513 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
514 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]515 };
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]516
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]517 cppi41dma: dma-controller@07402000 {
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]518 compatible = "ti,am3359-cppi41";
519 reg = <0x47400000 0x1000
520 0x47402000 0x1000
521 0x47403000 0x1000
522 0x47404000 0x4000>;
Sebastian Andrzej Siewior3b6394b2013-08-20 18:35:45 +0200[diff] [blame]523 reg-names = "glue", "controller", "scheduler", "queuemgr";
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]524 interrupts = <17>;
525 interrupt-names = "glue";
526 #dma-cells = <2>;
527 #dma-channels = <30>;
528 #dma-requests = <256>;
529 status = "disabled";
530 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]531 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]532
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]533 epwmss0: epwmss@48300000 {
534 compatible = "ti,am33xx-pwmss";
535 reg = <0x48300000 0x10>;
536 ti,hwmods = "epwmss0";
537 #address-cells = <1>;
538 #size-cells = <1>;
539 status = "disabled";
540 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
541 0x48300180 0x48300180 0x80 /* EQEP */
542 0x48300200 0x48300200 0x80>; /* EHRPWM */
543
544 ecap0: ecap@48300100 {
545 compatible = "ti,am33xx-ecap";
546 #pwm-cells = <3>;
547 reg = <0x48300100 0x80>;
548 ti,hwmods = "ecap0";
549 status = "disabled";
550 };
551
552 ehrpwm0: ehrpwm@48300200 {
553 compatible = "ti,am33xx-ehrpwm";
554 #pwm-cells = <3>;
555 reg = <0x48300200 0x80>;
556 ti,hwmods = "ehrpwm0";
557 status = "disabled";
558 };
559 };
560
561 epwmss1: epwmss@48302000 {
562 compatible = "ti,am33xx-pwmss";
563 reg = <0x48302000 0x10>;
564 ti,hwmods = "epwmss1";
565 #address-cells = <1>;
566 #size-cells = <1>;
567 status = "disabled";
568 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
569 0x48302180 0x48302180 0x80 /* EQEP */
570 0x48302200 0x48302200 0x80>; /* EHRPWM */
571
572 ecap1: ecap@48302100 {
573 compatible = "ti,am33xx-ecap";
574 #pwm-cells = <3>;
575 reg = <0x48302100 0x80>;
576 ti,hwmods = "ecap1";
577 status = "disabled";
578 };
579
580 ehrpwm1: ehrpwm@48302200 {
581 compatible = "ti,am33xx-ehrpwm";
582 #pwm-cells = <3>;
583 reg = <0x48302200 0x80>;
584 ti,hwmods = "ehrpwm1";
585 status = "disabled";
586 };
587 };
588
589 epwmss2: epwmss@48304000 {
590 compatible = "ti,am33xx-pwmss";
591 reg = <0x48304000 0x10>;
592 ti,hwmods = "epwmss2";
593 #address-cells = <1>;
594 #size-cells = <1>;
595 status = "disabled";
596 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
597 0x48304180 0x48304180 0x80 /* EQEP */
598 0x48304200 0x48304200 0x80>; /* EHRPWM */
599
600 ecap2: ecap@48304100 {
601 compatible = "ti,am33xx-ecap";
602 #pwm-cells = <3>;
603 reg = <0x48304100 0x80>;
604 ti,hwmods = "ecap2";
605 status = "disabled";
606 };
607
608 ehrpwm2: ehrpwm@48304200 {
609 compatible = "ti,am33xx-ehrpwm";
610 #pwm-cells = <3>;
611 reg = <0x48304200 0x80>;
612 ti,hwmods = "ehrpwm2";
613 status = "disabled";
614 };
615 };
616
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]617 mac: ethernet@4a100000 {
618 compatible = "ti,cpsw";
619 ti,hwmods = "cpgmac0";
620 cpdma_channels = <8>;
621 ale_entries = <1024>;
622 bd_ram_size = <0x2000>;
623 no_bd_ram = <0>;
624 rx_descs = <64>;
625 mac_control = <0x20>;
626 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]627 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]628 cpts_clock_mult = <0x80000000>;
629 cpts_clock_shift = <29>;
630 reg = <0x4a100000 0x800
631 0x4a101200 0x100>;
632 #address-cells = <1>;
633 #size-cells = <1>;
634 interrupt-parent = <&intc>;
635 /*
636 * c0_rx_thresh_pend
637 * c0_rx_pend
638 * c0_tx_pend
639 * c0_misc_pend
640 */
641 interrupts = <40 41 42 43>;
642 ranges;
643
644 davinci_mdio: mdio@4a101000 {
645 compatible = "ti,davinci_mdio";
646 #address-cells = <1>;
647 #size-cells = <0>;
648 ti,hwmods = "davinci_mdio";
649 bus_freq = <1000000>;
650 reg = <0x4a101000 0x100>;
651 };
652
653 cpsw_emac0: slave@4a100200 {
654 /* Filled in by U-Boot */
655 mac-address = [ 00 00 00 00 00 00 ];
656 };
657
658 cpsw_emac1: slave@4a100300 {
659 /* Filled in by U-Boot */
660 mac-address = [ 00 00 00 00 00 00 ];
661 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]662 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]663
664 ocmcram: ocmcram@40300000 {
665 compatible = "ti,am3352-ocmcram";
666 reg = <0x40300000 0x10000>;
667 ti,hwmods = "ocmcram";
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]668 };
669
670 wkup_m3: wkup_m3@44d00000 {
671 compatible = "ti,am3353-wkup-m3";
672 reg = <0x44d00000 0x4000 /* M3 UMEM */
673 0x44d80000 0x2000>; /* M3 DMEM */
674 ti,hwmods = "wkup_m3";
675 };
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]676
Philip, Avinash15e82462013-05-31 13:19:03 +0530[diff] [blame]677 elm: elm@48080000 {
678 compatible = "ti,am3352-elm";
679 reg = <0x48080000 0x2000>;
680 interrupts = <4>;
681 ti,hwmods = "elm";
682 status = "disabled";
683 };
684
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]685 tscadc: tscadc@44e0d000 {
686 compatible = "ti,am3359-tscadc";
687 reg = <0x44e0d000 0x1000>;
688 interrupt-parent = <&intc>;
689 interrupts = <16>;
690 ti,hwmods = "adc_tsc";
691 status = "disabled";
692
693 tsc {
694 compatible = "ti,am3359-tsc";
695 };
696 am335x_adc: adc {
697 #io-channel-cells = <1>;
698 compatible = "ti,am3359-adc";
699 };
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]700 };
701
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]702 gpmc: gpmc@50000000 {
703 compatible = "ti,am3352-gpmc";
704 ti,hwmods = "gpmc";
705 reg = <0x50000000 0x2000>;
706 interrupts = <100>;
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]707 gpmc,num-cs = <7>;
708 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]709 #address-cells = <2>;
710 #size-cells = <1>;
711 status = "disabled";
712 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]713 };
714};