blob: 4654c2761b7cc6e3910b75d0db5a45bdeac73803 [file] [log] [blame]
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001config ARM64
2 def_bool y
Suthikulpanit, Suraveeb6197b92015-06-10 11:08:53 -05003 select ACPI_CCA_REQUIRED if ACPI
Lorenzo Pieralisid8f4f162015-03-24 17:58:51 +00004 select ACPI_GENERIC_GSI if ACPI
Al Stone6933de02015-03-24 14:02:51 +00005 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01006 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
Kees Cook2b68f6c2015-04-14 15:48:00 -07007 select ARCH_HAS_ELF_RANDOMIZE
Riku Voipio957e3fa2014-12-12 16:57:44 -08008 select ARCH_HAS_GCOV_PROFILE_ALL
Laura Abbott308c09f2014-08-08 14:23:25 -07009 select ARCH_HAS_SG_CHAIN
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010010 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
Sudeep Hollac63c8702014-05-09 10:33:01 +010011 select ARCH_USE_CMPXCHG_LOCKREF
Peter Zijlstra4badad32014-06-06 19:53:16 +020012 select ARCH_SUPPORTS_ATOMIC_RMW
Arnd Bergmann91701002013-02-21 11:42:57 +010013 select ARCH_WANT_OPTIONAL_GPIOLIB
Will Deacon6212a512012-11-07 14:16:28 +000014 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
Catalin Marinasb6f35982013-01-29 18:25:41 +000015 select ARCH_WANT_FRAME_POINTERS
Catalin Marinas25c92a32012-12-18 15:26:13 +000016 select ARM_AMBA
Mark Rutland1aee5d72012-11-20 10:06:00 +000017 select ARM_ARCH_TIMER
Catalin Marinasc4188ed2013-01-14 12:39:31 +000018 select ARM_GIC
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010019 select AUDIT_ARCH_COMPAT_GENERIC
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000020 select ARM_GIC_V2M if PCI_MSI
Marc Zyngier021f6532014-06-30 16:01:31 +010021 select ARM_GIC_V3
Marc Zyngier19812722014-11-24 14:35:19 +000022 select ARM_GIC_V3_ITS if PCI_MSI
Mark Rutlandbff60792015-07-31 15:46:16 +010023 select ARM_PSCI_FW
Will Deaconadace892013-05-08 17:29:24 +010024 select BUILDTIME_EXTABLE_SORT
Catalin Marinasdb2789b2012-12-18 15:27:25 +000025 select CLONE_BACKWARDS
Deepak Saxena7ca2ef32012-09-22 10:33:36 -070026 select COMMON_CLK
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +000027 select CPU_PM if (SUSPEND || CPU_IDLE)
Will Deacon7bc13fd2013-11-06 19:32:13 +000028 select DCACHE_WORD_ACCESS
Catalin Marinasef375662015-07-07 17:15:39 +010029 select EDAC_SUPPORT
Laura Abbottd4932f92014-10-09 15:26:44 -070030 select GENERIC_ALLOCATOR
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010031 select GENERIC_CLOCKEVENTS
Will Deacon4b3dc962015-05-29 18:28:44 +010032 select GENERIC_CLOCKEVENTS_BROADCAST
Ard Biesheuvel3be1a5c2014-03-04 01:10:04 +000033 select GENERIC_CPU_AUTOPROBE
Mark Salterbf4b5582014-04-07 15:39:52 -070034 select GENERIC_EARLY_IOREMAP
Leo Yan2314ee42015-08-21 04:40:22 +010035 select GENERIC_IDLE_POLL_SETUP
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010036 select GENERIC_IRQ_PROBE
37 select GENERIC_IRQ_SHOW
Sudeep Holla6544e672015-04-22 18:16:33 +010038 select GENERIC_IRQ_SHOW_LEVEL
Arnd Bergmanncb61f672014-11-19 14:09:07 +010039 select GENERIC_PCI_IOMAP
Stephen Boyd65cd4f62013-07-18 16:21:18 -070040 select GENERIC_SCHED_CLOCK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010041 select GENERIC_SMP_IDLE_THREAD
Will Deacon12a0ef72013-11-06 17:20:22 +000042 select GENERIC_STRNCPY_FROM_USER
43 select GENERIC_STRNLEN_USER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010044 select GENERIC_TIME_VSYSCALL
Marc Zyngiera1ddc742014-08-26 11:03:17 +010045 select HANDLE_DOMAIN_IRQ
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010046 select HARDIRQS_SW_RESEND
Steve Capper5284e1b2014-10-24 13:22:20 +010047 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010048 select HAVE_ARCH_AUDITSYSCALL
Yalin Wang8e7a4ce2014-11-03 03:02:23 +010049 select HAVE_ARCH_BITREVERSE
Jiang Liu9732caf2014-01-07 22:17:13 +080050 select HAVE_ARCH_JUMP_LABEL
Andrey Ryabinin39d114d2015-10-12 18:52:58 +030051 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP
Vijaya Kumar K95292472014-01-28 11:20:22 +000052 select HAVE_ARCH_KGDB
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +000053 select HAVE_ARCH_SECCOMP_FILTER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010054 select HAVE_ARCH_TRACEHOOK
Zi Shen Lime54bcde2014-08-26 21:15:30 -070055 select HAVE_BPF_JIT
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010056 select HAVE_C_RECORDMCOUNT
Laura Abbottc0c264a2014-06-25 23:55:03 +010057 select HAVE_CC_STACKPROTECTOR
Steve Capper5284e1b2014-10-24 13:22:20 +010058 select HAVE_CMPXCHG_DOUBLE
Will Deacon95eff6b2015-05-29 14:57:47 +010059 select HAVE_CMPXCHG_LOCAL
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070060 select HAVE_DEBUG_BUGVERBOSE
Catalin Marinasb69ec422012-10-08 16:28:11 -070061 select HAVE_DEBUG_KMEMLEAK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010062 select HAVE_DMA_API_DEBUG
63 select HAVE_DMA_ATTRS
Laura Abbott6ac21042013-12-12 19:28:33 +000064 select HAVE_DMA_CONTIGUOUS
AKASHI Takahirobd7d38d2014-04-30 10:54:34 +010065 select HAVE_DYNAMIC_FTRACE
Will Deacon50afc332013-12-16 17:50:08 +000066 select HAVE_EFFICIENT_UNALIGNED_ACCESS
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010067 select HAVE_FTRACE_MCOUNT_RECORD
AKASHI Takahiro819e50e2014-04-30 18:54:33 +090068 select HAVE_FUNCTION_TRACER
69 select HAVE_FUNCTION_GRAPH_TRACER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010070 select HAVE_GENERIC_DMA_COHERENT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010071 select HAVE_HW_BREAKPOINT if PERF_EVENTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010072 select HAVE_MEMBLOCK
Mark Rutland55834a72014-02-07 17:12:45 +000073 select HAVE_PATA_PLATFORM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010074 select HAVE_PERF_EVENTS
Jean Pihet2ee0d7f2014-02-03 19:18:27 +010075 select HAVE_PERF_REGS
76 select HAVE_PERF_USER_STACK_DUMP
Steve Capper5e5f6dc2014-10-09 15:29:23 -070077 select HAVE_RCU_TABLE_FREE
AKASHI Takahiro055b1212014-04-30 10:54:36 +010078 select HAVE_SYSCALL_TRACEPOINTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010079 select IRQ_DOMAIN
Anders Roxelle8557d12015-04-27 22:53:09 +020080 select IRQ_FORCED_THREADING
Catalin Marinasfea2aca2012-10-16 11:26:57 +010081 select MODULES_USE_ELF_RELA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010082 select NO_BOOTMEM
83 select OF
84 select OF_EARLY_FLATTREE
Marek Szyprowski9bf14b72014-02-28 14:42:55 +010085 select OF_RESERVED_MEM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010086 select PERF_USE_VMALLOC
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +000087 select POWER_RESET
88 select POWER_SUPPLY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010089 select RTC_LIB
90 select SPARSE_IRQ
Catalin Marinas7ac57a82012-10-08 16:28:16 -070091 select SYSCTL_EXCEPTION_TRACE
Larry Bassel6c81fe72014-05-30 12:34:15 -070092 select HAVE_CONTEXT_TRACKING
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010093 help
94 ARM 64-bit (AArch64) Linux support.
95
96config 64BIT
97 def_bool y
98
99config ARCH_PHYS_ADDR_T_64BIT
100 def_bool y
101
102config MMU
103 def_bool y
104
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -0700105config NO_IOPORT_MAP
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100106 def_bool y if !PCI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100107
108config STACKTRACE_SUPPORT
109 def_bool y
110
Jeff Vander Stoepbf0c4e02015-08-18 20:50:10 +0100111config ILLEGAL_POINTER_VALUE
112 hex
113 default 0xdead000000000000
114
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100115config LOCKDEP_SUPPORT
116 def_bool y
117
118config TRACE_IRQFLAGS_SUPPORT
119 def_bool y
120
Will Deaconc209f792014-03-14 17:47:05 +0000121config RWSEM_XCHGADD_ALGORITHM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100122 def_bool y
123
Dave P Martin9fb74102015-07-24 16:37:48 +0100124config GENERIC_BUG
125 def_bool y
126 depends on BUG
127
128config GENERIC_BUG_RELATIVE_POINTERS
129 def_bool y
130 depends on GENERIC_BUG
131
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100132config GENERIC_HWEIGHT
133 def_bool y
134
135config GENERIC_CSUM
136 def_bool y
137
138config GENERIC_CALIBRATE_DELAY
139 def_bool y
140
Catalin Marinas19e76402014-02-27 12:09:22 +0000141config ZONE_DMA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100142 def_bool y
143
Steve Capper29e56942014-10-09 15:29:25 -0700144config HAVE_GENERIC_RCU_GUP
145 def_bool y
146
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100147config ARCH_DMA_ADDR_T_64BIT
148 def_bool y
149
150config NEED_DMA_MAP_STATE
151 def_bool y
152
153config NEED_SG_DMA_LENGTH
154 def_bool y
155
Will Deacon4b3dc962015-05-29 18:28:44 +0100156config SMP
157 def_bool y
158
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100159config SWIOTLB
160 def_bool y
161
162config IOMMU_HELPER
163 def_bool SWIOTLB
164
Ard Biesheuvel4cfb3612013-07-09 14:18:12 +0100165config KERNEL_MODE_NEON
166 def_bool y
167
Rob Herring92cc15f2014-04-18 17:19:59 -0500168config FIX_EARLYCON_MEM
169 def_bool y
170
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700171config PGTABLE_LEVELS
172 int
173 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
174 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
175 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
176 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
177
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100178source "init/Kconfig"
179
180source "kernel/Kconfig.freezer"
181
Olof Johansson6a377492015-07-20 12:09:16 -0700182source "arch/arm64/Kconfig.platforms"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100183
184menu "Bus support"
185
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100186config PCI
187 bool "PCI support"
188 help
189 This feature enables support for PCI bus system. If you say Y
190 here, the kernel will include drivers and infrastructure code
191 to support PCI bus devices.
192
193config PCI_DOMAINS
194 def_bool PCI
195
196config PCI_DOMAINS_GENERIC
197 def_bool PCI
198
199config PCI_SYSCALL
200 def_bool PCI
201
202source "drivers/pci/Kconfig"
203source "drivers/pci/pcie/Kconfig"
204source "drivers/pci/hotplug/Kconfig"
205
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100206endmenu
207
208menu "Kernel Features"
209
Andre Przywarac0a01b82014-11-14 15:54:12 +0000210menu "ARM errata workarounds via the alternatives framework"
211
212config ARM64_ERRATUM_826319
213 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
214 default y
215 help
216 This option adds an alternative code sequence to work around ARM
217 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
218 AXI master interface and an L2 cache.
219
220 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
221 and is unable to accept a certain write via this interface, it will
222 not progress on read data presented on the read data channel and the
223 system can deadlock.
224
225 The workaround promotes data cache clean instructions to
226 data cache clean-and-invalidate.
227 Please note that this does not necessarily enable the workaround,
228 as it depends on the alternative framework, which will only patch
229 the kernel if an affected CPU is detected.
230
231 If unsure, say Y.
232
233config ARM64_ERRATUM_827319
234 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
235 default y
236 help
237 This option adds an alternative code sequence to work around ARM
238 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
239 master interface and an L2 cache.
240
241 Under certain conditions this erratum can cause a clean line eviction
242 to occur at the same time as another transaction to the same address
243 on the AMBA 5 CHI interface, which can cause data corruption if the
244 interconnect reorders the two transactions.
245
246 The workaround promotes data cache clean instructions to
247 data cache clean-and-invalidate.
248 Please note that this does not necessarily enable the workaround,
249 as it depends on the alternative framework, which will only patch
250 the kernel if an affected CPU is detected.
251
252 If unsure, say Y.
253
254config ARM64_ERRATUM_824069
255 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
256 default y
257 help
258 This option adds an alternative code sequence to work around ARM
259 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
260 to a coherent interconnect.
261
262 If a Cortex-A53 processor is executing a store or prefetch for
263 write instruction at the same time as a processor in another
264 cluster is executing a cache maintenance operation to the same
265 address, then this erratum might cause a clean cache line to be
266 incorrectly marked as dirty.
267
268 The workaround promotes data cache clean instructions to
269 data cache clean-and-invalidate.
270 Please note that this option does not necessarily enable the
271 workaround, as it depends on the alternative framework, which will
272 only patch the kernel if an affected CPU is detected.
273
274 If unsure, say Y.
275
276config ARM64_ERRATUM_819472
277 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
278 default y
279 help
280 This option adds an alternative code sequence to work around ARM
281 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
282 present when it is connected to a coherent interconnect.
283
284 If the processor is executing a load and store exclusive sequence at
285 the same time as a processor in another cluster is executing a cache
286 maintenance operation to the same address, then this erratum might
287 cause data corruption.
288
289 The workaround promotes data cache clean instructions to
290 data cache clean-and-invalidate.
291 Please note that this does not necessarily enable the workaround,
292 as it depends on the alternative framework, which will only patch
293 the kernel if an affected CPU is detected.
294
295 If unsure, say Y.
296
297config ARM64_ERRATUM_832075
298 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
299 default y
300 help
301 This option adds an alternative code sequence to work around ARM
302 erratum 832075 on Cortex-A57 parts up to r1p2.
303
304 Affected Cortex-A57 parts might deadlock when exclusive load/store
305 instructions to Write-Back memory are mixed with Device loads.
306
307 The workaround is to promote device loads to use Load-Acquire
308 semantics.
309 Please note that this does not necessarily enable the workaround,
310 as it depends on the alternative framework, which will only patch
311 the kernel if an affected CPU is detected.
312
313 If unsure, say Y.
314
Will Deacon905e8c52015-03-23 19:07:02 +0000315config ARM64_ERRATUM_845719
316 bool "Cortex-A53: 845719: a load might read incorrect data"
317 depends on COMPAT
318 default y
319 help
320 This option adds an alternative code sequence to work around ARM
321 erratum 845719 on Cortex-A53 parts up to r0p4.
322
323 When running a compat (AArch32) userspace on an affected Cortex-A53
324 part, a load at EL0 from a virtual address that matches the bottom 32
325 bits of the virtual address used by a recent load at (AArch64) EL1
326 might return incorrect data.
327
328 The workaround is to write the contextidr_el1 register on exception
329 return to a 32-bit task.
330 Please note that this does not necessarily enable the workaround,
331 as it depends on the alternative framework, which will only patch
332 the kernel if an affected CPU is detected.
333
334 If unsure, say Y.
335
Will Deacondf057cc2015-03-17 12:15:02 +0000336config ARM64_ERRATUM_843419
337 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
338 depends on MODULES
339 default y
340 help
341 This option builds kernel modules using the large memory model in
342 order to avoid the use of the ADRP instruction, which can cause
343 a subsequent memory access to use an incorrect address on Cortex-A53
344 parts up to r0p4.
345
346 Note that the kernel itself must be linked with a version of ld
347 which fixes potentially affected ADRP instructions through the
348 use of veneers.
349
350 If unsure, say Y.
351
Andre Przywarac0a01b82014-11-14 15:54:12 +0000352endmenu
353
354
Jungseok Leee41ceed2014-05-12 10:40:38 +0100355choice
356 prompt "Page size"
357 default ARM64_4K_PAGES
358 help
359 Page size (translation granule) configuration.
360
361config ARM64_4K_PAGES
362 bool "4KB"
363 help
364 This feature enables 4KB pages support.
365
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100366config ARM64_64K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100367 bool "64KB"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100368 help
369 This feature enables 64KB pages support (4KB by default)
370 allowing only two levels of page tables and faster TLB
371 look-up. AArch32 emulation is not available when this feature
372 is enabled.
373
Jungseok Leee41ceed2014-05-12 10:40:38 +0100374endchoice
375
376choice
377 prompt "Virtual address space size"
378 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
379 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
380 help
381 Allows choosing one of multiple possible virtual address
382 space sizes. The level of translation table is determined by
383 a combination of page size and virtual address space size.
384
385config ARM64_VA_BITS_39
386 bool "39-bit"
387 depends on ARM64_4K_PAGES
388
389config ARM64_VA_BITS_42
390 bool "42-bit"
391 depends on ARM64_64K_PAGES
392
Jungseok Leec79b9542014-05-12 18:40:51 +0900393config ARM64_VA_BITS_48
394 bool "48-bit"
Jungseok Leec79b9542014-05-12 18:40:51 +0900395
Jungseok Leee41ceed2014-05-12 10:40:38 +0100396endchoice
397
398config ARM64_VA_BITS
399 int
400 default 39 if ARM64_VA_BITS_39
401 default 42 if ARM64_VA_BITS_42
Jungseok Leec79b9542014-05-12 18:40:51 +0900402 default 48 if ARM64_VA_BITS_48
Jungseok Leee41ceed2014-05-12 10:40:38 +0100403
Will Deacona8720132013-10-11 14:52:19 +0100404config CPU_BIG_ENDIAN
405 bool "Build big-endian kernel"
406 help
407 Say Y if you plan on running a kernel in big-endian mode.
408
Mark Brownf6e763b2014-03-04 07:51:17 +0000409config SCHED_MC
410 bool "Multi-core scheduler support"
Mark Brownf6e763b2014-03-04 07:51:17 +0000411 help
412 Multi-core scheduler support improves the CPU scheduler's decision
413 making when dealing with multi-core CPU chips at a cost of slightly
414 increased overhead in some places. If unsure say N here.
415
416config SCHED_SMT
417 bool "SMT scheduler support"
Mark Brownf6e763b2014-03-04 07:51:17 +0000418 help
419 Improves the CPU scheduler's decision making when dealing with
420 MultiThreading at a cost of slightly increased overhead in some
421 places. If unsure say N here.
422
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100423config NR_CPUS
Ganapatrao Kulkarni62aa9652015-03-18 11:01:18 +0000424 int "Maximum number of CPUs (2-4096)"
425 range 2 4096
Vinayak Kale15942852013-04-24 10:06:57 +0100426 # These have to remain sorted largest to smallest
Robert Richtere3672642014-09-08 12:44:48 +0100427 default "64"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100428
Mark Rutland9327e2c2013-10-24 20:30:18 +0100429config HOTPLUG_CPU
430 bool "Support for hot-pluggable CPUs"
Yang Yingliang217d4532015-09-24 17:32:14 +0800431 select GENERIC_IRQ_MIGRATION
Mark Rutland9327e2c2013-10-24 20:30:18 +0100432 help
433 Say Y here to experiment with turning CPUs off and on. CPUs
434 can be controlled through /sys/devices/system/cpu.
435
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100436source kernel/Kconfig.preempt
437
438config HZ
439 int
440 default 100
441
442config ARCH_HAS_HOLES_MEMORYMODEL
443 def_bool y if SPARSEMEM
444
445config ARCH_SPARSEMEM_ENABLE
446 def_bool y
447 select SPARSEMEM_VMEMMAP_ENABLE
448
449config ARCH_SPARSEMEM_DEFAULT
450 def_bool ARCH_SPARSEMEM_ENABLE
451
452config ARCH_SELECT_MEMORY_MODEL
453 def_bool ARCH_SPARSEMEM_ENABLE
454
455config HAVE_ARCH_PFN_VALID
456 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
457
458config HW_PERF_EVENTS
Mark Rutland6475b2d2015-10-02 10:55:03 +0100459 def_bool y
460 depends on ARM_PMU
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100461
Steve Capper084bd292013-04-10 13:48:00 +0100462config SYS_SUPPORTS_HUGETLBFS
463 def_bool y
464
465config ARCH_WANT_GENERAL_HUGETLB
466 def_bool y
467
468config ARCH_WANT_HUGE_PMD_SHARE
Suzuki K. Poulose755e70b2015-10-19 14:19:32 +0100469 def_bool y if ARM64_4K_PAGES
Steve Capper084bd292013-04-10 13:48:00 +0100470
Steve Capperaf074842013-04-19 16:23:57 +0100471config HAVE_ARCH_TRANSPARENT_HUGEPAGE
472 def_bool y
473
Catalin Marinasa41dc0e2014-04-03 17:48:54 +0100474config ARCH_HAS_CACHE_LINE_SIZE
475 def_bool y
476
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100477source "mm/Kconfig"
478
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +0000479config SECCOMP
480 bool "Enable seccomp to safely compute untrusted bytecode"
481 ---help---
482 This kernel feature is useful for number crunching applications
483 that may need to compute untrusted bytecode during their
484 execution. By using pipes or other transports made available to
485 the process as file descriptors supporting the read/write
486 syscalls, it's possible to isolate those applications in
487 their own address space using seccomp. Once seccomp is
488 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
489 and the task is only allowed to execute a few safe syscalls
490 defined by each seccomp mode.
491
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000492config XEN_DOM0
493 def_bool y
494 depends on XEN
495
496config XEN
Julien Grallc2ba1f72014-09-17 14:07:06 -0700497 bool "Xen guest support on ARM64"
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000498 depends on ARM64 && OF
Stefano Stabellini83862cc2013-10-10 13:40:44 +0000499 select SWIOTLB_XEN
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000500 help
501 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
502
Steve Capperd03bb142013-04-25 15:19:21 +0100503config FORCE_MAX_ZONEORDER
504 int
505 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
506 default "11"
507
Will Deacon1b907f42014-11-20 16:51:10 +0000508menuconfig ARMV8_DEPRECATED
509 bool "Emulate deprecated/obsolete ARMv8 instructions"
510 depends on COMPAT
511 help
512 Legacy software support may require certain instructions
513 that have been deprecated or obsoleted in the architecture.
514
515 Enable this config to enable selective emulation of these
516 features.
517
518 If unsure, say Y
519
520if ARMV8_DEPRECATED
521
522config SWP_EMULATION
523 bool "Emulate SWP/SWPB instructions"
524 help
525 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
526 they are always undefined. Say Y here to enable software
527 emulation of these instructions for userspace using LDXR/STXR.
528
529 In some older versions of glibc [<=2.8] SWP is used during futex
530 trylock() operations with the assumption that the code will not
531 be preempted. This invalid assumption may be more likely to fail
532 with SWP emulation enabled, leading to deadlock of the user
533 application.
534
535 NOTE: when accessing uncached shared regions, LDXR/STXR rely
536 on an external transaction monitoring block called a global
537 monitor to maintain update atomicity. If your system does not
538 implement a global monitor, this option can cause programs that
539 perform SWP operations to uncached memory to deadlock.
540
541 If unsure, say Y
542
543config CP15_BARRIER_EMULATION
544 bool "Emulate CP15 Barrier instructions"
545 help
546 The CP15 barrier instructions - CP15ISB, CP15DSB, and
547 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
548 strongly recommended to use the ISB, DSB, and DMB
549 instructions instead.
550
551 Say Y here to enable software emulation of these
552 instructions for AArch32 userspace code. When this option is
553 enabled, CP15 barrier usage is traced which can help
554 identify software that needs updating.
555
556 If unsure, say Y
557
Suzuki K. Poulose2d888f42015-01-21 12:43:11 +0000558config SETEND_EMULATION
559 bool "Emulate SETEND instruction"
560 help
561 The SETEND instruction alters the data-endianness of the
562 AArch32 EL0, and is deprecated in ARMv8.
563
564 Say Y here to enable software emulation of the instruction
565 for AArch32 userspace code.
566
567 Note: All the cpus on the system must have mixed endian support at EL0
568 for this feature to be enabled. If a new CPU - which doesn't support mixed
569 endian - is hotplugged in after this feature has been enabled, there could
570 be unexpected results in the applications.
571
572 If unsure, say Y
Will Deacon1b907f42014-11-20 16:51:10 +0000573endif
574
Will Deacon0e4a0702015-07-27 15:54:13 +0100575menu "ARMv8.1 architectural features"
576
577config ARM64_HW_AFDBM
578 bool "Support for hardware updates of the Access and Dirty page flags"
579 default y
580 help
581 The ARMv8.1 architecture extensions introduce support for
582 hardware updates of the access and dirty information in page
583 table entries. When enabled in TCR_EL1 (HA and HD bits) on
584 capable processors, accesses to pages with PTE_AF cleared will
585 set this bit instead of raising an access flag fault.
586 Similarly, writes to read-only pages with the DBM bit set will
587 clear the read-only bit (AP[2]) instead of raising a
588 permission fault.
589
590 Kernels built with this configuration option enabled continue
591 to work on pre-ARMv8.1 hardware and the performance impact is
592 minimal. If unsure, say Y.
593
594config ARM64_PAN
595 bool "Enable support for Privileged Access Never (PAN)"
596 default y
597 help
598 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
599 prevents the kernel or hypervisor from accessing user-space (EL0)
600 memory directly.
601
602 Choosing this option will cause any unprotected (not using
603 copy_to_user et al) memory access to fail with a permission fault.
604
605 The feature is detected at runtime, and will remain as a 'nop'
606 instruction if the cpu does not implement the feature.
607
608config ARM64_LSE_ATOMICS
609 bool "Atomic instructions"
610 help
611 As part of the Large System Extensions, ARMv8.1 introduces new
612 atomic instructions that are designed specifically to scale in
613 very large systems.
614
615 Say Y here to make use of these instructions for the in-kernel
616 atomic routines. This incurs a small overhead on CPUs that do
617 not support these instructions and requires the kernel to be
618 built with binutils >= 2.25.
619
620endmenu
621
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100622endmenu
623
624menu "Boot options"
625
626config CMDLINE
627 string "Default kernel command string"
628 default ""
629 help
630 Provide a set of default command-line options at build time by
631 entering them here. As a minimum, you should specify the the
632 root device (e.g. root=/dev/nfs).
633
634config CMDLINE_FORCE
635 bool "Always use the default kernel command string"
636 help
637 Always use the default kernel command string, even if the boot
638 loader passes other arguments to the kernel.
639 This is useful if you cannot or don't want to change the
640 command-line options your boot loader passes to the kernel.
641
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200642config EFI_STUB
643 bool
644
Mark Salterf84d0272014-04-15 21:59:30 -0400645config EFI
646 bool "UEFI runtime support"
647 depends on OF && !CPU_BIG_ENDIAN
648 select LIBFDT
649 select UCS2_STRING
650 select EFI_PARAMS_FROM_FDT
Ard Biesheuvele15dd492014-07-04 19:41:53 +0200651 select EFI_RUNTIME_WRAPPERS
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200652 select EFI_STUB
653 select EFI_ARMSTUB
Mark Salterf84d0272014-04-15 21:59:30 -0400654 default y
655 help
656 This option provides support for runtime services provided
657 by UEFI firmware (such as non-volatile variables, realtime
Mark Salter3c7f2552014-04-15 22:47:52 -0400658 clock, and platform reset). A UEFI stub is also provided to
659 allow the kernel to be booted as an EFI application. This
660 is only useful on systems that have UEFI firmware.
Mark Salterf84d0272014-04-15 21:59:30 -0400661
Yi Lid1ae8c02014-10-04 23:46:43 +0800662config DMI
663 bool "Enable support for SMBIOS (DMI) tables"
664 depends on EFI
665 default y
666 help
667 This enables SMBIOS/DMI feature for systems.
668
669 This option is only useful on systems that have UEFI firmware.
670 However, even with this option, the resultant kernel should
671 continue to boot on existing non-UEFI platforms.
672
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100673endmenu
674
675menu "Userspace binary formats"
676
677source "fs/Kconfig.binfmt"
678
679config COMPAT
680 bool "Kernel support for 32-bit EL0"
Suzuki K. Poulose755e70b2015-10-19 14:19:32 +0100681 depends on ARM64_4K_PAGES || EXPERT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100682 select COMPAT_BINFMT_ELF
Catalin Marinasaf1839e2012-10-08 16:28:08 -0700683 select HAVE_UID16
Al Viro84b9e9b2012-12-25 16:29:11 -0500684 select OLD_SIGSUSPEND3
Al Viro51682032012-12-25 19:31:29 -0500685 select COMPAT_OLD_SIGACTION
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100686 help
687 This option enables support for a 32-bit EL0 running under a 64-bit
688 kernel at EL1. AArch32-specific components such as system calls,
689 the user helper functions, VFP support and the ptrace interface are
690 handled appropriately by the kernel.
691
Alexander Grafa8fcd8b2015-03-16 16:32:23 +0000692 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
693 will only be able to execute AArch32 binaries that were compiled with
694 64k aligned segments.
695
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100696 If you want to execute 32-bit userspace applications, say Y.
697
698config SYSVIPC_COMPAT
699 def_bool y
700 depends on COMPAT && SYSVIPC
701
702endmenu
703
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000704menu "Power management options"
705
706source "kernel/power/Kconfig"
707
708config ARCH_SUSPEND_POSSIBLE
709 def_bool y
710
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000711endmenu
712
Lorenzo Pieralisi13072202013-07-17 14:54:21 +0100713menu "CPU Power Management"
714
715source "drivers/cpuidle/Kconfig"
716
Rob Herring52e7e812014-02-24 11:27:57 +0900717source "drivers/cpufreq/Kconfig"
718
719endmenu
720
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100721source "net/Kconfig"
722
723source "drivers/Kconfig"
724
Mark Salterf84d0272014-04-15 21:59:30 -0400725source "drivers/firmware/Kconfig"
726
Graeme Gregoryb6a02172015-03-24 14:02:53 +0000727source "drivers/acpi/Kconfig"
728
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100729source "fs/Kconfig"
730
Marc Zyngierc3eb5b12013-07-04 13:34:32 +0100731source "arch/arm64/kvm/Kconfig"
732
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100733source "arch/arm64/Kconfig.debug"
734
735source "security/Kconfig"
736
737source "crypto/Kconfig"
Ard Biesheuvel2c988332014-03-06 16:23:33 +0800738if CRYPTO
739source "arch/arm64/crypto/Kconfig"
740endif
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100741
742source "lib/Kconfig"