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Florian Fainelli246d7f72014-08-27 17:04:56 -07001/*
2 * Broadcom Starfighter 2 DSA switch driver
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/list.h>
13#include <linux/module.h>
14#include <linux/netdevice.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/of.h>
18#include <linux/phy.h>
19#include <linux/phy_fixed.h>
20#include <linux/mii.h>
21#include <linux/of.h>
22#include <linux/of_irq.h>
23#include <linux/of_address.h>
Florian Fainelli8b7c94e2015-10-23 12:11:08 -070024#include <linux/of_net.h>
Florian Fainelli461cd1b02016-06-07 16:32:43 -070025#include <linux/of_mdio.h>
Florian Fainelli246d7f72014-08-27 17:04:56 -070026#include <net/dsa.h>
Florian Fainelli96e65d72014-09-18 17:31:25 -070027#include <linux/ethtool.h>
Florian Fainelli12f460f2015-02-24 13:15:34 -080028#include <linux/if_bridge.h>
Florian Fainelliaafc66f2015-06-10 18:08:01 -070029#include <linux/brcmphy.h>
Florian Fainelli680060d2015-10-23 11:38:07 -070030#include <linux/etherdevice.h>
31#include <net/switchdev.h>
Florian Fainelli246d7f72014-08-27 17:04:56 -070032
33#include "bcm_sf2.h"
34#include "bcm_sf2_regs.h"
35
36/* String, offset, and register size in bytes if different from 4 bytes */
37static const struct bcm_sf2_hw_stats bcm_sf2_mib[] = {
38 { "TxOctets", 0x000, 8 },
39 { "TxDropPkts", 0x020 },
40 { "TxQPKTQ0", 0x030 },
41 { "TxBroadcastPkts", 0x040 },
42 { "TxMulticastPkts", 0x050 },
43 { "TxUnicastPKts", 0x060 },
44 { "TxCollisions", 0x070 },
45 { "TxSingleCollision", 0x080 },
46 { "TxMultipleCollision", 0x090 },
47 { "TxDeferredCollision", 0x0a0 },
48 { "TxLateCollision", 0x0b0 },
49 { "TxExcessiveCollision", 0x0c0 },
50 { "TxFrameInDisc", 0x0d0 },
51 { "TxPausePkts", 0x0e0 },
52 { "TxQPKTQ1", 0x0f0 },
53 { "TxQPKTQ2", 0x100 },
54 { "TxQPKTQ3", 0x110 },
55 { "TxQPKTQ4", 0x120 },
56 { "TxQPKTQ5", 0x130 },
57 { "RxOctets", 0x140, 8 },
58 { "RxUndersizePkts", 0x160 },
59 { "RxPausePkts", 0x170 },
60 { "RxPkts64Octets", 0x180 },
61 { "RxPkts65to127Octets", 0x190 },
62 { "RxPkts128to255Octets", 0x1a0 },
63 { "RxPkts256to511Octets", 0x1b0 },
64 { "RxPkts512to1023Octets", 0x1c0 },
65 { "RxPkts1024toMaxPktsOctets", 0x1d0 },
66 { "RxOversizePkts", 0x1e0 },
67 { "RxJabbers", 0x1f0 },
68 { "RxAlignmentErrors", 0x200 },
69 { "RxFCSErrors", 0x210 },
70 { "RxGoodOctets", 0x220, 8 },
71 { "RxDropPkts", 0x240 },
72 { "RxUnicastPkts", 0x250 },
73 { "RxMulticastPkts", 0x260 },
74 { "RxBroadcastPkts", 0x270 },
75 { "RxSAChanges", 0x280 },
76 { "RxFragments", 0x290 },
77 { "RxJumboPkt", 0x2a0 },
78 { "RxSymblErr", 0x2b0 },
79 { "InRangeErrCount", 0x2c0 },
80 { "OutRangeErrCount", 0x2d0 },
81 { "EEELpiEvent", 0x2e0 },
82 { "EEELpiDuration", 0x2f0 },
83 { "RxDiscard", 0x300, 8 },
84 { "TxQPKTQ6", 0x320 },
85 { "TxQPKTQ7", 0x330 },
86 { "TxPkts64Octets", 0x340 },
87 { "TxPkts65to127Octets", 0x350 },
88 { "TxPkts128to255Octets", 0x360 },
89 { "TxPkts256to511Ocets", 0x370 },
90 { "TxPkts512to1023Ocets", 0x380 },
91 { "TxPkts1024toMaxPktOcets", 0x390 },
92};
93
94#define BCM_SF2_STATS_SIZE ARRAY_SIZE(bcm_sf2_mib)
95
96static void bcm_sf2_sw_get_strings(struct dsa_switch *ds,
97 int port, uint8_t *data)
98{
99 unsigned int i;
100
101 for (i = 0; i < BCM_SF2_STATS_SIZE; i++)
102 memcpy(data + i * ETH_GSTRING_LEN,
103 bcm_sf2_mib[i].string, ETH_GSTRING_LEN);
104}
105
106static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds,
107 int port, uint64_t *data)
108{
109 struct bcm_sf2_priv *priv = ds_to_priv(ds);
110 const struct bcm_sf2_hw_stats *s;
111 unsigned int i;
112 u64 val = 0;
113 u32 offset;
114
115 mutex_lock(&priv->stats_mutex);
116
117 /* Now fetch the per-port counters */
118 for (i = 0; i < BCM_SF2_STATS_SIZE; i++) {
119 s = &bcm_sf2_mib[i];
120
121 /* Do a latched 64-bit read if needed */
122 offset = s->reg + CORE_P_MIB_OFFSET(port);
123 if (s->sizeof_stat == 8)
124 val = core_readq(priv, offset);
125 else
126 val = core_readl(priv, offset);
127
128 data[i] = (u64)val;
129 }
130
131 mutex_unlock(&priv->stats_mutex);
132}
133
134static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds)
135{
136 return BCM_SF2_STATS_SIZE;
137}
138
Andrew Lunn7b314362016-08-22 16:01:01 +0200139static enum dsa_tag_protocol bcm_sf2_sw_get_tag_protocol(struct dsa_switch *ds)
140{
141 return DSA_TAG_PROTO_BRCM;
142}
143
Florian Fainellib6d045d2014-09-24 17:05:20 -0700144static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
Florian Fainelli246d7f72014-08-27 17:04:56 -0700145{
146 struct bcm_sf2_priv *priv = ds_to_priv(ds);
147 unsigned int i;
Florian Fainellib6d045d2014-09-24 17:05:20 -0700148 u32 reg;
149
150 /* Enable the IMP Port to be in the same VLAN as the other ports
151 * on a per-port basis such that we only have Port i and IMP in
152 * the same VLAN.
153 */
154 for (i = 0; i < priv->hw_params.num_ports; i++) {
Andrew Lunn74c3e2a2016-04-13 02:40:44 +0200155 if (!((1 << i) & ds->enabled_port_mask))
Florian Fainellib6d045d2014-09-24 17:05:20 -0700156 continue;
157
158 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
159 reg |= (1 << cpu_port);
160 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
161 }
162}
163
164static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
165{
166 struct bcm_sf2_priv *priv = ds_to_priv(ds);
Florian Fainelli246d7f72014-08-27 17:04:56 -0700167 u32 reg, val;
168
169 /* Enable the port memories */
170 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
171 reg &= ~P_TXQ_PSM_VDD(port);
172 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
173
174 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
175 reg = core_readl(priv, CORE_IMP_CTL);
176 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
177 reg &= ~(RX_DIS | TX_DIS);
178 core_writel(priv, reg, CORE_IMP_CTL);
179
180 /* Enable forwarding */
181 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
182
183 /* Enable IMP port in dumb mode */
184 reg = core_readl(priv, CORE_SWITCH_CTRL);
185 reg |= MII_DUMB_FWDG_EN;
186 core_writel(priv, reg, CORE_SWITCH_CTRL);
187
188 /* Resolve which bit controls the Broadcom tag */
189 switch (port) {
190 case 8:
191 val = BRCM_HDR_EN_P8;
192 break;
193 case 7:
194 val = BRCM_HDR_EN_P7;
195 break;
196 case 5:
197 val = BRCM_HDR_EN_P5;
198 break;
199 default:
200 val = 0;
201 break;
202 }
203
204 /* Enable Broadcom tags for IMP port */
205 reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
206 reg |= val;
207 core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
208
209 /* Enable reception Broadcom tag for CPU TX (switch RX) to
210 * allow us to tag outgoing frames
211 */
212 reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
213 reg &= ~(1 << port);
214 core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
215
216 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
217 * allow delivering frames to the per-port net_devices
218 */
219 reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
220 reg &= ~(1 << port);
221 core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
222
223 /* Force link status for IMP port */
224 reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);
225 reg |= (MII_SW_OR | LINK_STS);
226 core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);
Florian Fainelli246d7f72014-08-27 17:04:56 -0700227}
228
Florian Fainelli450b05c2014-09-24 17:05:22 -0700229static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
230{
231 struct bcm_sf2_priv *priv = ds_to_priv(ds);
232 u32 reg;
233
234 reg = core_readl(priv, CORE_EEE_EN_CTRL);
235 if (enable)
236 reg |= 1 << port;
237 else
238 reg &= ~(1 << port);
239 core_writel(priv, reg, CORE_EEE_EN_CTRL);
240}
241
Florian Fainellib0836682015-02-05 11:40:41 -0800242static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
243{
244 struct bcm_sf2_priv *priv = ds_to_priv(ds);
245 u32 reg;
246
Florian Fainelli9af197a2015-02-05 11:40:42 -0800247 reg = reg_readl(priv, REG_SPHY_CNTRL);
248 if (enable) {
249 reg |= PHY_RESET;
250 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS);
251 reg_writel(priv, reg, REG_SPHY_CNTRL);
252 udelay(21);
253 reg = reg_readl(priv, REG_SPHY_CNTRL);
254 reg &= ~PHY_RESET;
255 } else {
256 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
257 reg_writel(priv, reg, REG_SPHY_CNTRL);
258 mdelay(1);
259 reg |= CK25_DIS;
260 }
261 reg_writel(priv, reg, REG_SPHY_CNTRL);
Florian Fainellib0836682015-02-05 11:40:41 -0800262
Florian Fainelli9af197a2015-02-05 11:40:42 -0800263 /* Use PHY-driven LED signaling */
264 if (!enable) {
265 reg = reg_readl(priv, REG_LED_CNTRL(0));
266 reg |= SPDLNK_SRC_SEL;
267 reg_writel(priv, reg, REG_LED_CNTRL(0));
268 }
Florian Fainellib0836682015-02-05 11:40:41 -0800269}
270
Florian Fainelli8b7c94e2015-10-23 12:11:08 -0700271static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
272 int port)
273{
274 unsigned int off;
275
276 switch (port) {
277 case 7:
278 off = P7_IRQ_OFF;
279 break;
280 case 0:
281 /* Port 0 interrupts are located on the first bank */
282 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
283 return;
284 default:
285 off = P_IRQ_OFF(port);
286 break;
287 }
288
289 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
290}
291
292static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
293 int port)
294{
295 unsigned int off;
296
297 switch (port) {
298 case 7:
299 off = P7_IRQ_OFF;
300 break;
301 case 0:
302 /* Port 0 interrupts are located on the first bank */
303 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
304 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
305 return;
306 default:
307 off = P_IRQ_OFF(port);
308 break;
309 }
310
311 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
312 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
313}
314
Florian Fainellib6d045d2014-09-24 17:05:20 -0700315static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
316 struct phy_device *phy)
Florian Fainelli246d7f72014-08-27 17:04:56 -0700317{
318 struct bcm_sf2_priv *priv = ds_to_priv(ds);
Florian Fainellib6d045d2014-09-24 17:05:20 -0700319 s8 cpu_port = ds->dst[ds->index].cpu_port;
Florian Fainelli246d7f72014-08-27 17:04:56 -0700320 u32 reg;
321
322 /* Clear the memory power down */
323 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
324 reg &= ~P_TXQ_PSM_VDD(port);
325 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
326
327 /* Clear the Rx and Tx disable bits and set to no spanning tree */
328 core_writel(priv, 0, CORE_G_PCTL_PORT(port));
329
Florian Fainelli9af197a2015-02-05 11:40:42 -0800330 /* Re-enable the GPHY and re-apply workarounds */
Florian Fainelli8b7c94e2015-10-23 12:11:08 -0700331 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
Florian Fainelli9af197a2015-02-05 11:40:42 -0800332 bcm_sf2_gphy_enable_set(ds, true);
333 if (phy) {
334 /* if phy_stop() has been called before, phy
335 * will be in halted state, and phy_start()
336 * will call resume.
337 *
338 * the resume path does not configure back
339 * autoneg settings, and since we hard reset
340 * the phy manually here, we need to reset the
341 * state machine also.
342 */
343 phy->state = PHY_READY;
344 phy_init_hw(phy);
345 }
346 }
347
Florian Fainelli8b7c94e2015-10-23 12:11:08 -0700348 /* Enable MoCA port interrupts to get notified */
349 if (port == priv->moca_port)
350 bcm_sf2_port_intr_enable(priv, port);
Florian Fainelli246d7f72014-08-27 17:04:56 -0700351
Florian Fainelli12f460f2015-02-24 13:15:34 -0800352 /* Set this port, and only this one to be in the default VLAN,
353 * if member of a bridge, restore its membership prior to
354 * bringing down this port.
355 */
Florian Fainelli246d7f72014-08-27 17:04:56 -0700356 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
357 reg &= ~PORT_VLAN_CTRL_MASK;
358 reg |= (1 << port);
Florian Fainelli12f460f2015-02-24 13:15:34 -0800359 reg |= priv->port_sts[port].vlan_ctl_mask;
Florian Fainelli246d7f72014-08-27 17:04:56 -0700360 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
Florian Fainellib6d045d2014-09-24 17:05:20 -0700361
362 bcm_sf2_imp_vlan_setup(ds, cpu_port);
363
Florian Fainelli450b05c2014-09-24 17:05:22 -0700364 /* If EEE was enabled, restore it */
365 if (priv->port_sts[port].eee.eee_enabled)
366 bcm_sf2_eee_enable_set(ds, port, true);
367
Florian Fainellib6d045d2014-09-24 17:05:20 -0700368 return 0;
Florian Fainelli246d7f72014-08-27 17:04:56 -0700369}
370
Florian Fainellib6d045d2014-09-24 17:05:20 -0700371static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
372 struct phy_device *phy)
Florian Fainelli246d7f72014-08-27 17:04:56 -0700373{
374 struct bcm_sf2_priv *priv = ds_to_priv(ds);
375 u32 off, reg;
376
Florian Fainelli96e65d72014-09-18 17:31:25 -0700377 if (priv->wol_ports_mask & (1 << port))
378 return;
379
Florian Fainelli8b7c94e2015-10-23 12:11:08 -0700380 if (port == priv->moca_port)
381 bcm_sf2_port_intr_disable(priv, port);
Florian Fainellib6d045d2014-09-24 17:05:20 -0700382
Florian Fainelli8b7c94e2015-10-23 12:11:08 -0700383 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
Florian Fainelli9af197a2015-02-05 11:40:42 -0800384 bcm_sf2_gphy_enable_set(ds, false);
385
Florian Fainelli246d7f72014-08-27 17:04:56 -0700386 if (dsa_is_cpu_port(ds, port))
387 off = CORE_IMP_CTL;
388 else
389 off = CORE_G_PCTL_PORT(port);
390
391 reg = core_readl(priv, off);
392 reg |= RX_DIS | TX_DIS;
393 core_writel(priv, reg, off);
394
395 /* Power down the port memory */
396 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
397 reg |= P_TXQ_PSM_VDD(port);
398 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
399}
400
Florian Fainelli450b05c2014-09-24 17:05:22 -0700401/* Returns 0 if EEE was not enabled, or 1 otherwise
402 */
403static int bcm_sf2_eee_init(struct dsa_switch *ds, int port,
404 struct phy_device *phy)
405{
406 struct bcm_sf2_priv *priv = ds_to_priv(ds);
407 struct ethtool_eee *p = &priv->port_sts[port].eee;
408 int ret;
409
410 p->supported = (SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full);
411
412 ret = phy_init_eee(phy, 0);
413 if (ret)
414 return 0;
415
416 bcm_sf2_eee_enable_set(ds, port, true);
417
418 return 1;
419}
420
421static int bcm_sf2_sw_get_eee(struct dsa_switch *ds, int port,
422 struct ethtool_eee *e)
423{
424 struct bcm_sf2_priv *priv = ds_to_priv(ds);
425 struct ethtool_eee *p = &priv->port_sts[port].eee;
426 u32 reg;
427
428 reg = core_readl(priv, CORE_EEE_LPI_INDICATE);
429 e->eee_enabled = p->eee_enabled;
430 e->eee_active = !!(reg & (1 << port));
431
432 return 0;
433}
434
435static int bcm_sf2_sw_set_eee(struct dsa_switch *ds, int port,
436 struct phy_device *phydev,
437 struct ethtool_eee *e)
438{
439 struct bcm_sf2_priv *priv = ds_to_priv(ds);
440 struct ethtool_eee *p = &priv->port_sts[port].eee;
441
442 p->eee_enabled = e->eee_enabled;
443
444 if (!p->eee_enabled) {
445 bcm_sf2_eee_enable_set(ds, port, false);
446 } else {
447 p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
448 if (!p->eee_enabled)
449 return -EOPNOTSUPP;
450 }
451
452 return 0;
453}
454
Florian Fainellia468ef42016-06-09 17:42:05 -0700455static int bcm_sf2_fast_age_op(struct bcm_sf2_priv *priv)
Florian Fainelli12f460f2015-02-24 13:15:34 -0800456{
Florian Fainelli12f460f2015-02-24 13:15:34 -0800457 unsigned int timeout = 1000;
458 u32 reg;
459
Florian Fainelli12f460f2015-02-24 13:15:34 -0800460 reg = core_readl(priv, CORE_FAST_AGE_CTRL);
Florian Fainelli9c57a772016-06-09 17:42:08 -0700461 reg |= EN_AGE_PORT | EN_AGE_VLAN | EN_AGE_DYNAMIC | FAST_AGE_STR_DONE;
Florian Fainelli12f460f2015-02-24 13:15:34 -0800462 core_writel(priv, reg, CORE_FAST_AGE_CTRL);
463
464 do {
465 reg = core_readl(priv, CORE_FAST_AGE_CTRL);
466 if (!(reg & FAST_AGE_STR_DONE))
467 break;
468
469 cpu_relax();
470 } while (timeout--);
471
472 if (!timeout)
473 return -ETIMEDOUT;
474
Florian Fainelli39797a22015-09-05 13:07:27 -0700475 core_writel(priv, 0, CORE_FAST_AGE_CTRL);
476
Florian Fainelli12f460f2015-02-24 13:15:34 -0800477 return 0;
478}
479
Florian Fainellia468ef42016-06-09 17:42:05 -0700480/* Fast-ageing of ARL entries for a given port, equivalent to an ARL
481 * flush for that port.
482 */
483static int bcm_sf2_sw_fast_age_port(struct dsa_switch *ds, int port)
484{
485 struct bcm_sf2_priv *priv = ds_to_priv(ds);
486
487 core_writel(priv, port, CORE_FAST_AGE_PORT);
488
489 return bcm_sf2_fast_age_op(priv);
490}
491
Florian Fainelli9c57a772016-06-09 17:42:08 -0700492static int bcm_sf2_sw_fast_age_vlan(struct bcm_sf2_priv *priv, u16 vid)
493{
494 core_writel(priv, vid, CORE_FAST_AGE_VID);
495
496 return bcm_sf2_fast_age_op(priv);
497}
498
499static int bcm_sf2_vlan_op_wait(struct bcm_sf2_priv *priv)
500{
501 unsigned int timeout = 10;
502 u32 reg;
503
504 do {
505 reg = core_readl(priv, CORE_ARLA_VTBL_RWCTRL);
506 if (!(reg & ARLA_VTBL_STDN))
507 return 0;
508
509 usleep_range(1000, 2000);
510 } while (timeout--);
511
512 return -ETIMEDOUT;
513}
514
515static int bcm_sf2_vlan_op(struct bcm_sf2_priv *priv, u8 op)
516{
517 core_writel(priv, ARLA_VTBL_STDN | op, CORE_ARLA_VTBL_RWCTRL);
518
519 return bcm_sf2_vlan_op_wait(priv);
520}
521
522static void bcm_sf2_set_vlan_entry(struct bcm_sf2_priv *priv, u16 vid,
523 struct bcm_sf2_vlan *vlan)
524{
525 int ret;
526
527 core_writel(priv, vid & VTBL_ADDR_INDEX_MASK, CORE_ARLA_VTBL_ADDR);
528 core_writel(priv, vlan->untag << UNTAG_MAP_SHIFT | vlan->members,
529 CORE_ARLA_VTBL_ENTRY);
530
531 ret = bcm_sf2_vlan_op(priv, ARLA_VTBL_CMD_WRITE);
532 if (ret)
533 pr_err("failed to write VLAN entry\n");
534}
535
536static int bcm_sf2_get_vlan_entry(struct bcm_sf2_priv *priv, u16 vid,
537 struct bcm_sf2_vlan *vlan)
538{
539 u32 entry;
540 int ret;
541
542 core_writel(priv, vid & VTBL_ADDR_INDEX_MASK, CORE_ARLA_VTBL_ADDR);
543
544 ret = bcm_sf2_vlan_op(priv, ARLA_VTBL_CMD_READ);
545 if (ret)
546 return ret;
547
548 entry = core_readl(priv, CORE_ARLA_VTBL_ENTRY);
549 vlan->members = entry & FWD_MAP_MASK;
550 vlan->untag = (entry >> UNTAG_MAP_SHIFT) & UNTAG_MAP_MASK;
551
552 return 0;
553}
554
Florian Fainelli12f460f2015-02-24 13:15:34 -0800555static int bcm_sf2_sw_br_join(struct dsa_switch *ds, int port,
Vivien Didelota6692752016-02-12 12:09:39 -0500556 struct net_device *bridge)
Florian Fainelli12f460f2015-02-24 13:15:34 -0800557{
558 struct bcm_sf2_priv *priv = ds_to_priv(ds);
Florian Fainelli9c57a772016-06-09 17:42:08 -0700559 s8 cpu_port = ds->dst->cpu_port;
Florian Fainelli12f460f2015-02-24 13:15:34 -0800560 unsigned int i;
561 u32 reg, p_ctl;
562
Florian Fainelli9c57a772016-06-09 17:42:08 -0700563 /* Make this port leave the all VLANs join since we will have proper
564 * VLAN entries from now on
565 */
566 reg = core_readl(priv, CORE_JOIN_ALL_VLAN_EN);
567 reg &= ~BIT(port);
568 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
569 reg &= ~BIT(cpu_port);
570 core_writel(priv, reg, CORE_JOIN_ALL_VLAN_EN);
571
Vivien Didelota6692752016-02-12 12:09:39 -0500572 priv->port_sts[port].bridge_dev = bridge;
Florian Fainelli12f460f2015-02-24 13:15:34 -0800573 p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
574
575 for (i = 0; i < priv->hw_params.num_ports; i++) {
Vivien Didelota6692752016-02-12 12:09:39 -0500576 if (priv->port_sts[i].bridge_dev != bridge)
Florian Fainelli12f460f2015-02-24 13:15:34 -0800577 continue;
578
579 /* Add this local port to the remote port VLAN control
580 * membership and update the remote port bitmask
581 */
582 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
583 reg |= 1 << port;
584 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
585 priv->port_sts[i].vlan_ctl_mask = reg;
586
587 p_ctl |= 1 << i;
588 }
589
590 /* Configure the local port VLAN control membership to include
591 * remote ports and update the local port bitmask
592 */
593 core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
594 priv->port_sts[port].vlan_ctl_mask = p_ctl;
595
596 return 0;
597}
598
Vivien Didelot16bfa702016-03-13 16:21:33 -0400599static void bcm_sf2_sw_br_leave(struct dsa_switch *ds, int port)
Florian Fainelli12f460f2015-02-24 13:15:34 -0800600{
601 struct bcm_sf2_priv *priv = ds_to_priv(ds);
Vivien Didelota6692752016-02-12 12:09:39 -0500602 struct net_device *bridge = priv->port_sts[port].bridge_dev;
Florian Fainelli9c57a772016-06-09 17:42:08 -0700603 s8 cpu_port = ds->dst->cpu_port;
Florian Fainelli12f460f2015-02-24 13:15:34 -0800604 unsigned int i;
605 u32 reg, p_ctl;
606
607 p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
608
609 for (i = 0; i < priv->hw_params.num_ports; i++) {
610 /* Don't touch the remaining ports */
Vivien Didelota6692752016-02-12 12:09:39 -0500611 if (priv->port_sts[i].bridge_dev != bridge)
Florian Fainelli12f460f2015-02-24 13:15:34 -0800612 continue;
613
614 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
615 reg &= ~(1 << port);
616 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
617 priv->port_sts[port].vlan_ctl_mask = reg;
618
619 /* Prevent self removal to preserve isolation */
620 if (port != i)
621 p_ctl &= ~(1 << i);
622 }
623
624 core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
625 priv->port_sts[port].vlan_ctl_mask = p_ctl;
Vivien Didelota6692752016-02-12 12:09:39 -0500626 priv->port_sts[port].bridge_dev = NULL;
Florian Fainelli9c57a772016-06-09 17:42:08 -0700627
628 /* Make this port join all VLANs without VLAN entries */
629 reg = core_readl(priv, CORE_JOIN_ALL_VLAN_EN);
630 reg |= BIT(port);
631 if (!(reg & BIT(cpu_port)))
632 reg |= BIT(cpu_port);
633 core_writel(priv, reg, CORE_JOIN_ALL_VLAN_EN);
Florian Fainelli12f460f2015-02-24 13:15:34 -0800634}
635
Vivien Didelot43c44a92016-04-06 11:55:03 -0400636static void bcm_sf2_sw_br_set_stp_state(struct dsa_switch *ds, int port,
637 u8 state)
Florian Fainelli12f460f2015-02-24 13:15:34 -0800638{
639 struct bcm_sf2_priv *priv = ds_to_priv(ds);
640 u8 hw_state, cur_hw_state;
Florian Fainelli12f460f2015-02-24 13:15:34 -0800641 u32 reg;
642
643 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
Florian Fainelli39797a22015-09-05 13:07:27 -0700644 cur_hw_state = reg & (G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT);
Florian Fainelli12f460f2015-02-24 13:15:34 -0800645
646 switch (state) {
647 case BR_STATE_DISABLED:
648 hw_state = G_MISTP_DIS_STATE;
649 break;
650 case BR_STATE_LISTENING:
651 hw_state = G_MISTP_LISTEN_STATE;
652 break;
653 case BR_STATE_LEARNING:
654 hw_state = G_MISTP_LEARN_STATE;
655 break;
656 case BR_STATE_FORWARDING:
657 hw_state = G_MISTP_FWD_STATE;
658 break;
659 case BR_STATE_BLOCKING:
660 hw_state = G_MISTP_BLOCK_STATE;
661 break;
662 default:
663 pr_err("%s: invalid STP state: %d\n", __func__, state);
Vivien Didelot43c44a92016-04-06 11:55:03 -0400664 return;
Florian Fainelli12f460f2015-02-24 13:15:34 -0800665 }
666
667 /* Fast-age ARL entries if we are moving a port from Learning or
Florian Fainelli39797a22015-09-05 13:07:27 -0700668 * Forwarding (cur_hw_state) state to Disabled, Blocking or Listening
669 * state (hw_state)
Florian Fainelli12f460f2015-02-24 13:15:34 -0800670 */
671 if (cur_hw_state != hw_state) {
Florian Fainelli39797a22015-09-05 13:07:27 -0700672 if (cur_hw_state >= G_MISTP_LEARN_STATE &&
673 hw_state <= G_MISTP_LISTEN_STATE) {
Vivien Didelot43c44a92016-04-06 11:55:03 -0400674 if (bcm_sf2_sw_fast_age_port(ds, port)) {
Florian Fainelli12f460f2015-02-24 13:15:34 -0800675 pr_err("%s: fast-ageing failed\n", __func__);
Vivien Didelot43c44a92016-04-06 11:55:03 -0400676 return;
Florian Fainelli12f460f2015-02-24 13:15:34 -0800677 }
678 }
679 }
680
681 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
682 reg &= ~(G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT);
683 reg |= hw_state;
684 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
Florian Fainelli12f460f2015-02-24 13:15:34 -0800685}
686
Florian Fainelli680060d2015-10-23 11:38:07 -0700687/* Address Resolution Logic routines */
688static int bcm_sf2_arl_op_wait(struct bcm_sf2_priv *priv)
689{
690 unsigned int timeout = 10;
691 u32 reg;
692
693 do {
694 reg = core_readl(priv, CORE_ARLA_RWCTL);
695 if (!(reg & ARL_STRTDN))
696 return 0;
697
698 usleep_range(1000, 2000);
699 } while (timeout--);
700
701 return -ETIMEDOUT;
702}
703
704static int bcm_sf2_arl_rw_op(struct bcm_sf2_priv *priv, unsigned int op)
705{
706 u32 cmd;
707
708 if (op > ARL_RW)
709 return -EINVAL;
710
711 cmd = core_readl(priv, CORE_ARLA_RWCTL);
712 cmd &= ~IVL_SVL_SELECT;
713 cmd |= ARL_STRTDN;
714 if (op)
715 cmd |= ARL_RW;
716 else
717 cmd &= ~ARL_RW;
718 core_writel(priv, cmd, CORE_ARLA_RWCTL);
719
720 return bcm_sf2_arl_op_wait(priv);
721}
722
723static int bcm_sf2_arl_read(struct bcm_sf2_priv *priv, u64 mac,
724 u16 vid, struct bcm_sf2_arl_entry *ent, u8 *idx,
725 bool is_valid)
726{
727 unsigned int i;
728 int ret;
729
730 ret = bcm_sf2_arl_op_wait(priv);
731 if (ret)
732 return ret;
733
734 /* Read the 4 bins */
735 for (i = 0; i < 4; i++) {
736 u64 mac_vid;
737 u32 fwd_entry;
738
739 mac_vid = core_readq(priv, CORE_ARLA_MACVID_ENTRY(i));
740 fwd_entry = core_readl(priv, CORE_ARLA_FWD_ENTRY(i));
741 bcm_sf2_arl_to_entry(ent, mac_vid, fwd_entry);
742
743 if (ent->is_valid && is_valid) {
744 *idx = i;
745 return 0;
746 }
747
748 /* This is the MAC we just deleted */
749 if (!is_valid && (mac_vid & mac))
750 return 0;
751 }
752
753 return -ENOENT;
754}
755
756static int bcm_sf2_arl_op(struct bcm_sf2_priv *priv, int op, int port,
757 const unsigned char *addr, u16 vid, bool is_valid)
758{
759 struct bcm_sf2_arl_entry ent;
760 u32 fwd_entry;
761 u64 mac, mac_vid = 0;
762 u8 idx = 0;
763 int ret;
764
765 /* Convert the array into a 64-bit MAC */
766 mac = bcm_sf2_mac_to_u64(addr);
767
768 /* Perform a read for the given MAC and VID */
769 core_writeq(priv, mac, CORE_ARLA_MAC);
770 core_writel(priv, vid, CORE_ARLA_VID);
771
772 /* Issue a read operation for this MAC */
773 ret = bcm_sf2_arl_rw_op(priv, 1);
774 if (ret)
775 return ret;
776
777 ret = bcm_sf2_arl_read(priv, mac, vid, &ent, &idx, is_valid);
778 /* If this is a read, just finish now */
779 if (op)
780 return ret;
781
782 /* We could not find a matching MAC, so reset to a new entry */
783 if (ret) {
784 fwd_entry = 0;
785 idx = 0;
786 }
787
788 memset(&ent, 0, sizeof(ent));
789 ent.port = port;
790 ent.is_valid = is_valid;
791 ent.vid = vid;
792 ent.is_static = true;
793 memcpy(ent.mac, addr, ETH_ALEN);
794 bcm_sf2_arl_from_entry(&mac_vid, &fwd_entry, &ent);
795
796 core_writeq(priv, mac_vid, CORE_ARLA_MACVID_ENTRY(idx));
797 core_writel(priv, fwd_entry, CORE_ARLA_FWD_ENTRY(idx));
798
799 ret = bcm_sf2_arl_rw_op(priv, 0);
800 if (ret)
801 return ret;
802
803 /* Re-read the entry to check */
804 return bcm_sf2_arl_read(priv, mac, vid, &ent, &idx, is_valid);
805}
806
807static int bcm_sf2_sw_fdb_prepare(struct dsa_switch *ds, int port,
808 const struct switchdev_obj_port_fdb *fdb,
809 struct switchdev_trans *trans)
810{
811 /* We do not need to do anything specific here yet */
812 return 0;
813}
814
Vivien Didelot8497aa62016-04-06 11:55:04 -0400815static void bcm_sf2_sw_fdb_add(struct dsa_switch *ds, int port,
816 const struct switchdev_obj_port_fdb *fdb,
817 struct switchdev_trans *trans)
Florian Fainelli680060d2015-10-23 11:38:07 -0700818{
819 struct bcm_sf2_priv *priv = ds_to_priv(ds);
820
Vivien Didelot8497aa62016-04-06 11:55:04 -0400821 if (bcm_sf2_arl_op(priv, 0, port, fdb->addr, fdb->vid, true))
822 pr_err("%s: failed to add MAC address\n", __func__);
Florian Fainelli680060d2015-10-23 11:38:07 -0700823}
824
825static int bcm_sf2_sw_fdb_del(struct dsa_switch *ds, int port,
826 const struct switchdev_obj_port_fdb *fdb)
827{
828 struct bcm_sf2_priv *priv = ds_to_priv(ds);
829
830 return bcm_sf2_arl_op(priv, 0, port, fdb->addr, fdb->vid, false);
831}
832
833static int bcm_sf2_arl_search_wait(struct bcm_sf2_priv *priv)
834{
835 unsigned timeout = 1000;
836 u32 reg;
837
838 do {
839 reg = core_readl(priv, CORE_ARLA_SRCH_CTL);
840 if (!(reg & ARLA_SRCH_STDN))
841 return 0;
842
843 if (reg & ARLA_SRCH_VLID)
844 return 0;
845
846 usleep_range(1000, 2000);
847 } while (timeout--);
848
849 return -ETIMEDOUT;
850}
851
852static void bcm_sf2_arl_search_rd(struct bcm_sf2_priv *priv, u8 idx,
853 struct bcm_sf2_arl_entry *ent)
854{
855 u64 mac_vid;
856 u32 fwd_entry;
857
858 mac_vid = core_readq(priv, CORE_ARLA_SRCH_RSLT_MACVID(idx));
859 fwd_entry = core_readl(priv, CORE_ARLA_SRCH_RSLT(idx));
860 bcm_sf2_arl_to_entry(ent, mac_vid, fwd_entry);
861}
862
863static int bcm_sf2_sw_fdb_copy(struct net_device *dev, int port,
864 const struct bcm_sf2_arl_entry *ent,
865 struct switchdev_obj_port_fdb *fdb,
866 int (*cb)(struct switchdev_obj *obj))
867{
868 if (!ent->is_valid)
869 return 0;
870
871 if (port != ent->port)
872 return 0;
873
874 ether_addr_copy(fdb->addr, ent->mac);
875 fdb->vid = ent->vid;
876 fdb->ndm_state = ent->is_static ? NUD_NOARP : NUD_REACHABLE;
877
878 return cb(&fdb->obj);
879}
880
881static int bcm_sf2_sw_fdb_dump(struct dsa_switch *ds, int port,
882 struct switchdev_obj_port_fdb *fdb,
883 int (*cb)(struct switchdev_obj *obj))
884{
885 struct bcm_sf2_priv *priv = ds_to_priv(ds);
Andrew Lunnc8b09802016-06-04 21:16:57 +0200886 struct net_device *dev = ds->ports[port].netdev;
Florian Fainelli680060d2015-10-23 11:38:07 -0700887 struct bcm_sf2_arl_entry results[2];
888 unsigned int count = 0;
889 int ret;
890
891 /* Start search operation */
892 core_writel(priv, ARLA_SRCH_STDN, CORE_ARLA_SRCH_CTL);
893
894 do {
895 ret = bcm_sf2_arl_search_wait(priv);
896 if (ret)
897 return ret;
898
899 /* Read both entries, then return their values back */
900 bcm_sf2_arl_search_rd(priv, 0, &results[0]);
901 ret = bcm_sf2_sw_fdb_copy(dev, port, &results[0], fdb, cb);
902 if (ret)
903 return ret;
904
905 bcm_sf2_arl_search_rd(priv, 1, &results[1]);
906 ret = bcm_sf2_sw_fdb_copy(dev, port, &results[1], fdb, cb);
907 if (ret)
908 return ret;
909
910 if (!results[0].is_valid && !results[1].is_valid)
911 break;
912
913 } while (count++ < CORE_ARLA_NUM_ENTRIES);
914
915 return 0;
916}
917
Florian Fainelli461cd1b02016-06-07 16:32:43 -0700918static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
919 int regnum, u16 val)
920{
921 int ret = 0;
922 u32 reg;
923
924 reg = reg_readl(priv, REG_SWITCH_CNTRL);
925 reg |= MDIO_MASTER_SEL;
926 reg_writel(priv, reg, REG_SWITCH_CNTRL);
927
928 /* Page << 8 | offset */
929 reg = 0x70;
930 reg <<= 2;
931 core_writel(priv, addr, reg);
932
933 /* Page << 8 | offset */
934 reg = 0x80 << 8 | regnum << 1;
935 reg <<= 2;
936
937 if (op)
938 ret = core_readl(priv, reg);
939 else
940 core_writel(priv, val, reg);
941
942 reg = reg_readl(priv, REG_SWITCH_CNTRL);
943 reg &= ~MDIO_MASTER_SEL;
944 reg_writel(priv, reg, REG_SWITCH_CNTRL);
945
946 return ret & 0xffff;
947}
948
949static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
950{
951 struct bcm_sf2_priv *priv = bus->priv;
952
953 /* Intercept reads from Broadcom pseudo-PHY address, else, send
954 * them to our master MDIO bus controller
955 */
956 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
957 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
958 else
959 return mdiobus_read(priv->master_mii_bus, addr, regnum);
960}
961
962static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
963 u16 val)
964{
965 struct bcm_sf2_priv *priv = bus->priv;
966
967 /* Intercept writes to the Broadcom pseudo-PHY address, else,
968 * send them to our master MDIO bus controller
969 */
970 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
971 bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
972 else
973 mdiobus_write(priv->master_mii_bus, addr, regnum, val);
974
975 return 0;
976}
977
Florian Fainelli246d7f72014-08-27 17:04:56 -0700978static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
979{
980 struct bcm_sf2_priv *priv = dev_id;
981
982 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
983 ~priv->irq0_mask;
984 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
985
986 return IRQ_HANDLED;
987}
988
989static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
990{
991 struct bcm_sf2_priv *priv = dev_id;
992
993 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
994 ~priv->irq1_mask;
995 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
996
997 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
998 priv->port_sts[7].link = 1;
999 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
1000 priv->port_sts[7].link = 0;
1001
1002 return IRQ_HANDLED;
1003}
1004
Florian Fainelli33f84612014-11-25 18:08:49 -08001005static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
1006{
1007 unsigned int timeout = 1000;
1008 u32 reg;
1009
1010 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
1011 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
1012 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
1013
1014 do {
1015 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
1016 if (!(reg & SOFTWARE_RESET))
1017 break;
1018
1019 usleep_range(1000, 2000);
1020 } while (timeout-- > 0);
1021
1022 if (timeout == 0)
1023 return -ETIMEDOUT;
1024
1025 return 0;
1026}
1027
Florian Fainelli691c9a82015-01-20 16:42:00 -08001028static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
1029{
1030 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
1031 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1032 intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1033 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
1034 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1035 intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1036}
1037
Florian Fainelli8b7c94e2015-10-23 12:11:08 -07001038static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
1039 struct device_node *dn)
1040{
1041 struct device_node *port;
1042 const char *phy_mode_str;
1043 int mode;
1044 unsigned int port_num;
1045 int ret;
1046
1047 priv->moca_port = -1;
1048
1049 for_each_available_child_of_node(dn, port) {
1050 if (of_property_read_u32(port, "reg", &port_num))
1051 continue;
1052
1053 /* Internal PHYs get assigned a specific 'phy-mode' property
1054 * value: "internal" to help flag them before MDIO probing
1055 * has completed, since they might be turned off at that
1056 * time
1057 */
1058 mode = of_get_phy_mode(port);
1059 if (mode < 0) {
1060 ret = of_property_read_string(port, "phy-mode",
1061 &phy_mode_str);
1062 if (ret < 0)
1063 continue;
1064
1065 if (!strcasecmp(phy_mode_str, "internal"))
1066 priv->int_phy_mask |= 1 << port_num;
1067 }
1068
1069 if (mode == PHY_INTERFACE_MODE_MOCA)
1070 priv->moca_port = port_num;
1071 }
1072}
1073
Florian Fainelli461cd1b02016-06-07 16:32:43 -07001074static int bcm_sf2_mdio_register(struct dsa_switch *ds)
1075{
1076 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1077 struct device_node *dn;
1078 static int index;
1079 int err;
1080
1081 /* Find our integrated MDIO bus node */
1082 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
1083 priv->master_mii_bus = of_mdio_find_bus(dn);
1084 if (!priv->master_mii_bus)
1085 return -EPROBE_DEFER;
1086
1087 get_device(&priv->master_mii_bus->dev);
1088 priv->master_mii_dn = dn;
1089
1090 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
1091 if (!priv->slave_mii_bus)
1092 return -ENOMEM;
1093
1094 priv->slave_mii_bus->priv = priv;
1095 priv->slave_mii_bus->name = "sf2 slave mii";
1096 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
1097 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
1098 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
1099 index++);
1100 priv->slave_mii_bus->dev.of_node = dn;
1101
1102 /* Include the pseudo-PHY address to divert reads towards our
1103 * workaround. This is only required for 7445D0, since 7445E0
1104 * disconnects the internal switch pseudo-PHY such that we can use the
1105 * regular SWITCH_MDIO master controller instead.
1106 *
1107 * Here we flag the pseudo PHY as needing special treatment and would
1108 * otherwise make all other PHY read/writes go to the master MDIO bus
1109 * controller that comes with this switch backed by the "mdio-unimac"
1110 * driver.
1111 */
1112 if (of_machine_is_compatible("brcm,bcm7445d0"))
1113 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
1114 else
1115 priv->indir_phy_mask = 0;
1116
1117 ds->phys_mii_mask = priv->indir_phy_mask;
1118 ds->slave_mii_bus = priv->slave_mii_bus;
1119 priv->slave_mii_bus->parent = ds->dev->parent;
1120 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
1121
1122 if (dn)
1123 err = of_mdiobus_register(priv->slave_mii_bus, dn);
1124 else
1125 err = mdiobus_register(priv->slave_mii_bus);
1126
1127 if (err)
1128 of_node_put(dn);
1129
1130 return err;
1131}
1132
1133static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
1134{
1135 mdiobus_unregister(priv->slave_mii_bus);
1136 if (priv->master_mii_dn)
1137 of_node_put(priv->master_mii_dn);
1138}
1139
Florian Fainelli246d7f72014-08-27 17:04:56 -07001140static int bcm_sf2_sw_set_addr(struct dsa_switch *ds, u8 *addr)
1141{
1142 return 0;
1143}
1144
Florian Fainelliaa9aef72014-09-19 13:07:55 -07001145static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
1146{
1147 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1148
1149 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
1150 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
1151 * the REG_PHY_REVISION register layout is.
1152 */
1153
1154 return priv->hw_params.gphy_rev;
1155}
1156
Florian Fainelli246d7f72014-08-27 17:04:56 -07001157static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
1158 struct phy_device *phydev)
1159{
1160 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1161 u32 id_mode_dis = 0, port_mode;
1162 const char *str = NULL;
1163 u32 reg;
1164
1165 switch (phydev->interface) {
1166 case PHY_INTERFACE_MODE_RGMII:
1167 str = "RGMII (no delay)";
1168 id_mode_dis = 1;
1169 case PHY_INTERFACE_MODE_RGMII_TXID:
1170 if (!str)
1171 str = "RGMII (TX delay)";
1172 port_mode = EXT_GPHY;
1173 break;
1174 case PHY_INTERFACE_MODE_MII:
1175 str = "MII";
1176 port_mode = EXT_EPHY;
1177 break;
1178 case PHY_INTERFACE_MODE_REVMII:
1179 str = "Reverse MII";
1180 port_mode = EXT_REVMII;
1181 break;
1182 default:
Florian Fainelli7de15572014-09-24 17:05:19 -07001183 /* All other PHYs: internal and MoCA */
1184 goto force_link;
1185 }
1186
1187 /* If the link is down, just disable the interface to conserve power */
1188 if (!phydev->link) {
1189 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
1190 reg &= ~RGMII_MODE_EN;
1191 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
Florian Fainelli246d7f72014-08-27 17:04:56 -07001192 goto force_link;
1193 }
1194
1195 /* Clear id_mode_dis bit, and the existing port mode, but
1196 * make sure we enable the RGMII block for data to pass
1197 */
1198 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
1199 reg &= ~ID_MODE_DIS;
1200 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
1201 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
1202
1203 reg |= port_mode | RGMII_MODE_EN;
1204 if (id_mode_dis)
1205 reg |= ID_MODE_DIS;
1206
1207 if (phydev->pause) {
1208 if (phydev->asym_pause)
1209 reg |= TX_PAUSE_EN;
1210 reg |= RX_PAUSE_EN;
1211 }
1212
1213 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
1214
1215 pr_info("Port %d configured for %s\n", port, str);
1216
1217force_link:
1218 /* Force link settings detected from the PHY */
1219 reg = SW_OVERRIDE;
1220 switch (phydev->speed) {
1221 case SPEED_1000:
1222 reg |= SPDSTS_1000 << SPEED_SHIFT;
1223 break;
1224 case SPEED_100:
1225 reg |= SPDSTS_100 << SPEED_SHIFT;
1226 break;
1227 }
1228
1229 if (phydev->link)
1230 reg |= LINK_STS;
1231 if (phydev->duplex == DUPLEX_FULL)
1232 reg |= DUPLX_MODE;
1233
1234 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
1235}
1236
1237static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
1238 struct fixed_phy_status *status)
1239{
1240 struct bcm_sf2_priv *priv = ds_to_priv(ds);
Florian Fainellid2eac982015-07-20 17:49:55 -07001241 u32 duplex, pause;
Florian Fainelli246d7f72014-08-27 17:04:56 -07001242 u32 reg;
1243
Florian Fainelli246d7f72014-08-27 17:04:56 -07001244 duplex = core_readl(priv, CORE_DUPSTS);
1245 pause = core_readl(priv, CORE_PAUSESTS);
Florian Fainelli246d7f72014-08-27 17:04:56 -07001246
1247 status->link = 0;
1248
Florian Fainelli8b7c94e2015-10-23 12:11:08 -07001249 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
Florian Fainelli246d7f72014-08-27 17:04:56 -07001250 * which means that we need to force the link at the port override
1251 * level to get the data to flow. We do use what the interrupt handler
1252 * did determine before.
Florian Fainelli7855f672014-12-11 18:12:42 -08001253 *
1254 * For the other ports, we just force the link status, since this is
1255 * a fixed PHY device.
Florian Fainelli246d7f72014-08-27 17:04:56 -07001256 */
Florian Fainelli8b7c94e2015-10-23 12:11:08 -07001257 if (port == priv->moca_port) {
Florian Fainelli246d7f72014-08-27 17:04:56 -07001258 status->link = priv->port_sts[port].link;
Florian Fainelli4ab7f912015-05-15 12:38:01 -07001259 /* For MoCA interfaces, also force a link down notification
1260 * since some version of the user-space daemon (mocad) use
1261 * cmd->autoneg to force the link, which messes up the PHY
1262 * state machine and make it go in PHY_FORCING state instead.
1263 */
1264 if (!status->link)
Andrew Lunnc8b09802016-06-04 21:16:57 +02001265 netif_carrier_off(ds->ports[port].netdev);
Florian Fainelli246d7f72014-08-27 17:04:56 -07001266 status->duplex = 1;
1267 } else {
Florian Fainelli7855f672014-12-11 18:12:42 -08001268 status->link = 1;
Florian Fainelli246d7f72014-08-27 17:04:56 -07001269 status->duplex = !!(duplex & (1 << port));
1270 }
1271
Florian Fainelli7855f672014-12-11 18:12:42 -08001272 reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(port));
1273 reg |= SW_OVERRIDE;
1274 if (status->link)
1275 reg |= LINK_STS;
1276 else
1277 reg &= ~LINK_STS;
1278 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
1279
Florian Fainelli246d7f72014-08-27 17:04:56 -07001280 if ((pause & (1 << port)) &&
1281 (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
1282 status->asym_pause = 1;
1283 status->pause = 1;
1284 }
1285
1286 if (pause & (1 << port))
1287 status->pause = 1;
1288}
1289
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001290static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
1291{
1292 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1293 unsigned int port;
1294
Florian Fainelli691c9a82015-01-20 16:42:00 -08001295 bcm_sf2_intr_disable(priv);
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001296
1297 /* Disable all ports physically present including the IMP
1298 * port, the other ones have already been disabled during
1299 * bcm_sf2_sw_setup
1300 */
1301 for (port = 0; port < DSA_MAX_PORTS; port++) {
Andrew Lunn74c3e2a2016-04-13 02:40:44 +02001302 if ((1 << port) & ds->enabled_port_mask ||
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001303 dsa_is_cpu_port(ds, port))
Florian Fainellib6d045d2014-09-24 17:05:20 -07001304 bcm_sf2_port_disable(ds, port, NULL);
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001305 }
1306
1307 return 0;
1308}
1309
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001310static int bcm_sf2_sw_resume(struct dsa_switch *ds)
1311{
1312 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1313 unsigned int port;
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001314 int ret;
1315
1316 ret = bcm_sf2_sw_rst(priv);
1317 if (ret) {
1318 pr_err("%s: failed to software reset switch\n", __func__);
1319 return ret;
1320 }
1321
Florian Fainellib0836682015-02-05 11:40:41 -08001322 if (priv->hw_params.num_gphy == 1)
1323 bcm_sf2_gphy_enable_set(ds, true);
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001324
1325 for (port = 0; port < DSA_MAX_PORTS; port++) {
Andrew Lunn74c3e2a2016-04-13 02:40:44 +02001326 if ((1 << port) & ds->enabled_port_mask)
Florian Fainellib6d045d2014-09-24 17:05:20 -07001327 bcm_sf2_port_setup(ds, port, NULL);
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001328 else if (dsa_is_cpu_port(ds, port))
1329 bcm_sf2_imp_setup(ds, port);
1330 }
1331
1332 return 0;
1333}
1334
Florian Fainelli96e65d72014-09-18 17:31:25 -07001335static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
1336 struct ethtool_wolinfo *wol)
1337{
1338 struct net_device *p = ds->dst[ds->index].master_netdev;
1339 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1340 struct ethtool_wolinfo pwol;
1341
1342 /* Get the parent device WoL settings */
1343 p->ethtool_ops->get_wol(p, &pwol);
1344
1345 /* Advertise the parent device supported settings */
1346 wol->supported = pwol.supported;
1347 memset(&wol->sopass, 0, sizeof(wol->sopass));
1348
1349 if (pwol.wolopts & WAKE_MAGICSECURE)
1350 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
1351
1352 if (priv->wol_ports_mask & (1 << port))
1353 wol->wolopts = pwol.wolopts;
1354 else
1355 wol->wolopts = 0;
1356}
1357
1358static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
1359 struct ethtool_wolinfo *wol)
1360{
1361 struct net_device *p = ds->dst[ds->index].master_netdev;
1362 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1363 s8 cpu_port = ds->dst[ds->index].cpu_port;
1364 struct ethtool_wolinfo pwol;
1365
1366 p->ethtool_ops->get_wol(p, &pwol);
1367 if (wol->wolopts & ~pwol.supported)
1368 return -EINVAL;
1369
1370 if (wol->wolopts)
1371 priv->wol_ports_mask |= (1 << port);
1372 else
1373 priv->wol_ports_mask &= ~(1 << port);
1374
1375 /* If we have at least one port enabled, make sure the CPU port
1376 * is also enabled. If the CPU port is the last one enabled, we disable
1377 * it since this configuration does not make sense.
1378 */
1379 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
1380 priv->wol_ports_mask |= (1 << cpu_port);
1381 else
1382 priv->wol_ports_mask &= ~(1 << cpu_port);
1383
1384 return p->ethtool_ops->set_wol(p, wol);
1385}
1386
Florian Fainelli9c57a772016-06-09 17:42:08 -07001387static void bcm_sf2_enable_vlan(struct bcm_sf2_priv *priv, bool enable)
1388{
1389 u32 mgmt, vc0, vc1, vc4, vc5;
1390
1391 mgmt = core_readl(priv, CORE_SWMODE);
1392 vc0 = core_readl(priv, CORE_VLAN_CTRL0);
1393 vc1 = core_readl(priv, CORE_VLAN_CTRL1);
1394 vc4 = core_readl(priv, CORE_VLAN_CTRL4);
1395 vc5 = core_readl(priv, CORE_VLAN_CTRL5);
1396
1397 mgmt &= ~SW_FWDG_MODE;
1398
1399 if (enable) {
1400 vc0 |= VLAN_EN | VLAN_LEARN_MODE_IVL;
1401 vc1 |= EN_RSV_MCAST_UNTAG | EN_RSV_MCAST_FWDMAP;
1402 vc4 &= ~(INGR_VID_CHK_MASK << INGR_VID_CHK_SHIFT);
1403 vc4 |= INGR_VID_CHK_DROP;
1404 vc5 |= DROP_VTABLE_MISS | EN_VID_FFF_FWD;
1405 } else {
1406 vc0 &= ~(VLAN_EN | VLAN_LEARN_MODE_IVL);
1407 vc1 &= ~(EN_RSV_MCAST_UNTAG | EN_RSV_MCAST_FWDMAP);
1408 vc4 &= ~(INGR_VID_CHK_MASK << INGR_VID_CHK_SHIFT);
1409 vc5 &= ~(DROP_VTABLE_MISS | EN_VID_FFF_FWD);
1410 vc4 |= INGR_VID_CHK_VID_VIOL_IMP;
1411 }
1412
1413 core_writel(priv, vc0, CORE_VLAN_CTRL0);
1414 core_writel(priv, vc1, CORE_VLAN_CTRL1);
1415 core_writel(priv, 0, CORE_VLAN_CTRL3);
1416 core_writel(priv, vc4, CORE_VLAN_CTRL4);
1417 core_writel(priv, vc5, CORE_VLAN_CTRL5);
1418 core_writel(priv, mgmt, CORE_SWMODE);
1419}
1420
1421static void bcm_sf2_sw_configure_vlan(struct dsa_switch *ds)
1422{
1423 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1424 unsigned int port;
1425
1426 /* Clear all VLANs */
1427 bcm_sf2_vlan_op(priv, ARLA_VTBL_CMD_CLEAR);
1428
1429 for (port = 0; port < priv->hw_params.num_ports; port++) {
1430 if (!((1 << port) & ds->enabled_port_mask))
1431 continue;
1432
1433 core_writel(priv, 1, CORE_DEFAULT_1Q_TAG_P(port));
1434 }
1435}
1436
1437static int bcm_sf2_sw_vlan_filtering(struct dsa_switch *ds, int port,
1438 bool vlan_filtering)
1439{
1440 return 0;
1441}
1442
1443static int bcm_sf2_sw_vlan_prepare(struct dsa_switch *ds, int port,
1444 const struct switchdev_obj_port_vlan *vlan,
1445 struct switchdev_trans *trans)
1446{
1447 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1448
1449 bcm_sf2_enable_vlan(priv, true);
1450
1451 return 0;
1452}
1453
1454static void bcm_sf2_sw_vlan_add(struct dsa_switch *ds, int port,
1455 const struct switchdev_obj_port_vlan *vlan,
1456 struct switchdev_trans *trans)
1457{
1458 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1459 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1460 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1461 s8 cpu_port = ds->dst->cpu_port;
1462 struct bcm_sf2_vlan *vl;
1463 u16 vid;
1464
1465 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1466 vl = &priv->vlans[vid];
1467
1468 bcm_sf2_get_vlan_entry(priv, vid, vl);
1469
1470 vl->members |= BIT(port) | BIT(cpu_port);
1471 if (untagged)
1472 vl->untag |= BIT(port) | BIT(cpu_port);
1473 else
1474 vl->untag &= ~(BIT(port) | BIT(cpu_port));
1475
1476 bcm_sf2_set_vlan_entry(priv, vid, vl);
1477 bcm_sf2_sw_fast_age_vlan(priv, vid);
1478 }
1479
1480 if (pvid) {
1481 core_writel(priv, vlan->vid_end, CORE_DEFAULT_1Q_TAG_P(port));
1482 core_writel(priv, vlan->vid_end,
1483 CORE_DEFAULT_1Q_TAG_P(cpu_port));
1484 bcm_sf2_sw_fast_age_vlan(priv, vid);
1485 }
1486}
1487
1488static int bcm_sf2_sw_vlan_del(struct dsa_switch *ds, int port,
1489 const struct switchdev_obj_port_vlan *vlan)
1490{
1491 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1492 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1493 s8 cpu_port = ds->dst->cpu_port;
1494 struct bcm_sf2_vlan *vl;
1495 u16 vid, pvid;
1496 int ret;
1497
1498 pvid = core_readl(priv, CORE_DEFAULT_1Q_TAG_P(port));
1499
1500 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1501 vl = &priv->vlans[vid];
1502
1503 ret = bcm_sf2_get_vlan_entry(priv, vid, vl);
1504 if (ret)
1505 return ret;
1506
1507 vl->members &= ~BIT(port);
1508 if ((vl->members & BIT(cpu_port)) == BIT(cpu_port))
1509 vl->members = 0;
1510 if (pvid == vid)
1511 pvid = 0;
1512 if (untagged) {
1513 vl->untag &= ~BIT(port);
1514 if ((vl->untag & BIT(port)) == BIT(cpu_port))
1515 vl->untag = 0;
1516 }
1517
1518 bcm_sf2_set_vlan_entry(priv, vid, vl);
1519 bcm_sf2_sw_fast_age_vlan(priv, vid);
1520 }
1521
1522 core_writel(priv, pvid, CORE_DEFAULT_1Q_TAG_P(port));
1523 core_writel(priv, pvid, CORE_DEFAULT_1Q_TAG_P(cpu_port));
1524 bcm_sf2_sw_fast_age_vlan(priv, vid);
1525
1526 return 0;
1527}
1528
1529static int bcm_sf2_sw_vlan_dump(struct dsa_switch *ds, int port,
1530 struct switchdev_obj_port_vlan *vlan,
1531 int (*cb)(struct switchdev_obj *obj))
1532{
1533 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1534 struct bcm_sf2_port_status *p = &priv->port_sts[port];
1535 struct bcm_sf2_vlan *vl;
1536 u16 vid, pvid;
1537 int err = 0;
1538
1539 pvid = core_readl(priv, CORE_DEFAULT_1Q_TAG_P(port));
1540
1541 for (vid = 0; vid < VLAN_N_VID; vid++) {
1542 vl = &priv->vlans[vid];
1543
1544 if (!(vl->members & BIT(port)))
1545 continue;
1546
1547 vlan->vid_begin = vlan->vid_end = vid;
1548 vlan->flags = 0;
1549
1550 if (vl->untag & BIT(port))
1551 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1552 if (p->pvid == vid)
1553 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1554
1555 err = cb(&vlan->obj);
1556 if (err)
1557 break;
1558 }
1559
1560 return err;
1561}
1562
Florian Fainelli7fbb1a92016-06-09 17:42:06 -07001563static int bcm_sf2_sw_setup(struct dsa_switch *ds)
1564{
Florian Fainelli7fbb1a92016-06-09 17:42:06 -07001565 struct bcm_sf2_priv *priv = ds_to_priv(ds);
Florian Fainelli7fbb1a92016-06-09 17:42:06 -07001566 unsigned int port;
Florian Fainellid9338022016-08-18 15:30:14 -07001567
1568 /* Enable all valid ports and disable those unused */
1569 for (port = 0; port < priv->hw_params.num_ports; port++) {
1570 /* IMP port receives special treatment */
1571 if ((1 << port) & ds->enabled_port_mask)
1572 bcm_sf2_port_setup(ds, port, NULL);
1573 else if (dsa_is_cpu_port(ds, port))
1574 bcm_sf2_imp_setup(ds, port);
1575 else
1576 bcm_sf2_port_disable(ds, port, NULL);
1577 }
1578
1579 bcm_sf2_sw_configure_vlan(ds);
1580
1581 return 0;
1582}
1583
1584static struct dsa_switch_driver bcm_sf2_switch_driver = {
Florian Fainellid9338022016-08-18 15:30:14 -07001585 .setup = bcm_sf2_sw_setup,
Andrew Lunn7b314362016-08-22 16:01:01 +02001586 .get_tag_protocol = bcm_sf2_sw_get_tag_protocol,
Florian Fainellid9338022016-08-18 15:30:14 -07001587 .set_addr = bcm_sf2_sw_set_addr,
1588 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
1589 .get_strings = bcm_sf2_sw_get_strings,
1590 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
1591 .get_sset_count = bcm_sf2_sw_get_sset_count,
1592 .adjust_link = bcm_sf2_sw_adjust_link,
1593 .fixed_link_update = bcm_sf2_sw_fixed_link_update,
1594 .suspend = bcm_sf2_sw_suspend,
1595 .resume = bcm_sf2_sw_resume,
1596 .get_wol = bcm_sf2_sw_get_wol,
1597 .set_wol = bcm_sf2_sw_set_wol,
1598 .port_enable = bcm_sf2_port_setup,
1599 .port_disable = bcm_sf2_port_disable,
1600 .get_eee = bcm_sf2_sw_get_eee,
1601 .set_eee = bcm_sf2_sw_set_eee,
1602 .port_bridge_join = bcm_sf2_sw_br_join,
1603 .port_bridge_leave = bcm_sf2_sw_br_leave,
1604 .port_stp_state_set = bcm_sf2_sw_br_set_stp_state,
1605 .port_fdb_prepare = bcm_sf2_sw_fdb_prepare,
1606 .port_fdb_add = bcm_sf2_sw_fdb_add,
1607 .port_fdb_del = bcm_sf2_sw_fdb_del,
1608 .port_fdb_dump = bcm_sf2_sw_fdb_dump,
1609 .port_vlan_filtering = bcm_sf2_sw_vlan_filtering,
1610 .port_vlan_prepare = bcm_sf2_sw_vlan_prepare,
1611 .port_vlan_add = bcm_sf2_sw_vlan_add,
1612 .port_vlan_del = bcm_sf2_sw_vlan_del,
1613 .port_vlan_dump = bcm_sf2_sw_vlan_dump,
1614};
1615
1616static int bcm_sf2_sw_probe(struct platform_device *pdev)
1617{
1618 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1619 struct device_node *dn = pdev->dev.of_node;
1620 struct bcm_sf2_priv *priv;
1621 struct dsa_switch *ds;
1622 void __iomem **base;
Florian Fainelli4bd11672016-08-18 15:30:15 -07001623 struct resource *r;
Florian Fainelli7fbb1a92016-06-09 17:42:06 -07001624 unsigned int i;
1625 u32 reg, rev;
1626 int ret;
1627
Florian Fainellid9338022016-08-18 15:30:14 -07001628 ds = devm_kzalloc(&pdev->dev, sizeof(*ds) + sizeof(*priv), GFP_KERNEL);
1629 if (!ds)
1630 return -ENOMEM;
1631
1632 priv = (struct bcm_sf2_priv *)(ds + 1);
1633 ds->priv = priv;
1634 ds->dev = &pdev->dev;
1635 ds->drv = &bcm_sf2_switch_driver;
1636
1637 dev_set_drvdata(&pdev->dev, ds);
1638
Florian Fainelli7fbb1a92016-06-09 17:42:06 -07001639 spin_lock_init(&priv->indir_lock);
1640 mutex_init(&priv->stats_mutex);
1641
Florian Fainellid9338022016-08-18 15:30:14 -07001642 bcm_sf2_identify_ports(priv, dn->child);
Florian Fainelli7fbb1a92016-06-09 17:42:06 -07001643
1644 priv->irq0 = irq_of_parse_and_map(dn, 0);
1645 priv->irq1 = irq_of_parse_and_map(dn, 1);
1646
1647 base = &priv->core;
1648 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
Florian Fainelli4bd11672016-08-18 15:30:15 -07001649 r = platform_get_resource(pdev, IORESOURCE_MEM, i);
1650 *base = devm_ioremap_resource(&pdev->dev, r);
1651 if (IS_ERR(*base)) {
Florian Fainelli7fbb1a92016-06-09 17:42:06 -07001652 pr_err("unable to find register: %s\n", reg_names[i]);
Florian Fainelli4bd11672016-08-18 15:30:15 -07001653 return PTR_ERR(*base);
Florian Fainelli7fbb1a92016-06-09 17:42:06 -07001654 }
1655 base++;
1656 }
1657
1658 ret = bcm_sf2_sw_rst(priv);
1659 if (ret) {
1660 pr_err("unable to software reset switch: %d\n", ret);
Florian Fainelli4bd11672016-08-18 15:30:15 -07001661 return ret;
Florian Fainelli7fbb1a92016-06-09 17:42:06 -07001662 }
1663
1664 ret = bcm_sf2_mdio_register(ds);
1665 if (ret) {
1666 pr_err("failed to register MDIO bus\n");
Florian Fainelli4bd11672016-08-18 15:30:15 -07001667 return ret;
Florian Fainelli7fbb1a92016-06-09 17:42:06 -07001668 }
1669
1670 /* Disable all interrupts and request them */
1671 bcm_sf2_intr_disable(priv);
1672
Florian Fainelli4bd11672016-08-18 15:30:15 -07001673 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1674 "switch_0", priv);
Florian Fainelli7fbb1a92016-06-09 17:42:06 -07001675 if (ret < 0) {
1676 pr_err("failed to request switch_0 IRQ\n");
Florian Fainellibb9c0fa2016-07-29 12:35:57 -07001677 goto out_mdio;
Florian Fainelli7fbb1a92016-06-09 17:42:06 -07001678 }
1679
Florian Fainelli4bd11672016-08-18 15:30:15 -07001680 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1681 "switch_1", priv);
Florian Fainelli7fbb1a92016-06-09 17:42:06 -07001682 if (ret < 0) {
1683 pr_err("failed to request switch_1 IRQ\n");
Florian Fainelli4bd11672016-08-18 15:30:15 -07001684 goto out_mdio;
Florian Fainelli7fbb1a92016-06-09 17:42:06 -07001685 }
1686
1687 /* Reset the MIB counters */
1688 reg = core_readl(priv, CORE_GMNCFGCFG);
1689 reg |= RST_MIB_CNT;
1690 core_writel(priv, reg, CORE_GMNCFGCFG);
1691 reg &= ~RST_MIB_CNT;
1692 core_writel(priv, reg, CORE_GMNCFGCFG);
1693
1694 /* Get the maximum number of ports for this switch */
1695 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1696 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1697 priv->hw_params.num_ports = DSA_MAX_PORTS;
1698
1699 /* Assume a single GPHY setup if we can't read that property */
1700 if (of_property_read_u32(dn, "brcm,num-gphy",
1701 &priv->hw_params.num_gphy))
1702 priv->hw_params.num_gphy = 1;
1703
Florian Fainelli7fbb1a92016-06-09 17:42:06 -07001704 rev = reg_readl(priv, REG_SWITCH_REVISION);
1705 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1706 SWITCH_TOP_REV_MASK;
1707 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1708
1709 rev = reg_readl(priv, REG_PHY_REVISION);
1710 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1711
Florian Fainellid9338022016-08-18 15:30:14 -07001712 ret = dsa_register_switch(ds, dn);
1713 if (ret)
Florian Fainelli4bd11672016-08-18 15:30:15 -07001714 goto out_mdio;
Florian Fainellid9338022016-08-18 15:30:14 -07001715
Florian Fainelli7fbb1a92016-06-09 17:42:06 -07001716 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
1717 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1718 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1719 priv->core, priv->irq0, priv->irq1);
1720
1721 return 0;
1722
Florian Fainellibb9c0fa2016-07-29 12:35:57 -07001723out_mdio:
1724 bcm_sf2_mdio_unregister(priv);
Florian Fainelli7fbb1a92016-06-09 17:42:06 -07001725 return ret;
1726}
1727
Florian Fainellid9338022016-08-18 15:30:14 -07001728static int bcm_sf2_sw_remove(struct platform_device *pdev)
Florian Fainelli246d7f72014-08-27 17:04:56 -07001729{
Florian Fainellid9338022016-08-18 15:30:14 -07001730 struct dsa_switch *ds = platform_get_drvdata(pdev);
1731 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1732
1733 /* Disable all ports and interrupts */
1734 priv->wol_ports_mask = 0;
1735 bcm_sf2_sw_suspend(ds);
1736 dsa_unregister_switch(ds);
1737 bcm_sf2_mdio_unregister(priv);
Florian Fainelli246d7f72014-08-27 17:04:56 -07001738
1739 return 0;
1740}
Florian Fainelli246d7f72014-08-27 17:04:56 -07001741
Florian Fainellid9338022016-08-18 15:30:14 -07001742#ifdef CONFIG_PM_SLEEP
1743static int bcm_sf2_suspend(struct device *dev)
Florian Fainelli246d7f72014-08-27 17:04:56 -07001744{
Florian Fainellid9338022016-08-18 15:30:14 -07001745 struct platform_device *pdev = to_platform_device(dev);
1746 struct dsa_switch *ds = platform_get_drvdata(pdev);
1747
1748 return dsa_switch_suspend(ds);
Florian Fainelli246d7f72014-08-27 17:04:56 -07001749}
Florian Fainellid9338022016-08-18 15:30:14 -07001750
1751static int bcm_sf2_resume(struct device *dev)
1752{
1753 struct platform_device *pdev = to_platform_device(dev);
1754 struct dsa_switch *ds = platform_get_drvdata(pdev);
1755
1756 return dsa_switch_resume(ds);
1757}
1758#endif /* CONFIG_PM_SLEEP */
1759
1760static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1761 bcm_sf2_suspend, bcm_sf2_resume);
1762
1763static const struct of_device_id bcm_sf2_of_match[] = {
1764 { .compatible = "brcm,bcm7445-switch-v4.0" },
1765 { /* sentinel */ },
1766};
1767
1768static struct platform_driver bcm_sf2_driver = {
1769 .probe = bcm_sf2_sw_probe,
1770 .remove = bcm_sf2_sw_remove,
1771 .driver = {
1772 .name = "brcm-sf2",
1773 .of_match_table = bcm_sf2_of_match,
1774 .pm = &bcm_sf2_pm_ops,
1775 },
1776};
1777module_platform_driver(bcm_sf2_driver);
Florian Fainelli246d7f72014-08-27 17:04:56 -07001778
1779MODULE_AUTHOR("Broadcom Corporation");
1780MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1781MODULE_LICENSE("GPL");
1782MODULE_ALIAS("platform:brcm-sf2");