blob: 4269dba63cf165d3590c16700896dc44726a898f [file] [log] [blame]
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001config ARM64
2 def_bool y
Lorenzo Pieralisid8f4f162015-03-24 17:58:51 +00003 select ACPI_GENERIC_GSI if ACPI
Al Stone6933de02015-03-24 14:02:51 +00004 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01005 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
Kees Cook2b68f6c2015-04-14 15:48:00 -07006 select ARCH_HAS_ELF_RANDOMIZE
Riku Voipio957e3fa2014-12-12 16:57:44 -08007 select ARCH_HAS_GCOV_PROFILE_ALL
Laura Abbott308c09f2014-08-08 14:23:25 -07008 select ARCH_HAS_SG_CHAIN
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +01009 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
Sudeep Hollac63c8702014-05-09 10:33:01 +010010 select ARCH_USE_CMPXCHG_LOCKREF
Peter Zijlstra4badad32014-06-06 19:53:16 +020011 select ARCH_SUPPORTS_ATOMIC_RMW
Arnd Bergmann91701002013-02-21 11:42:57 +010012 select ARCH_WANT_OPTIONAL_GPIOLIB
Will Deacon6212a512012-11-07 14:16:28 +000013 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
Catalin Marinasb6f35982013-01-29 18:25:41 +000014 select ARCH_WANT_FRAME_POINTERS
Catalin Marinas25c92a32012-12-18 15:26:13 +000015 select ARM_AMBA
Mark Rutland1aee5d72012-11-20 10:06:00 +000016 select ARM_ARCH_TIMER
Catalin Marinasc4188ed2013-01-14 12:39:31 +000017 select ARM_GIC
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010018 select AUDIT_ARCH_COMPAT_GENERIC
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000019 select ARM_GIC_V2M if PCI_MSI
Marc Zyngier021f6532014-06-30 16:01:31 +010020 select ARM_GIC_V3
Marc Zyngier19812722014-11-24 14:35:19 +000021 select ARM_GIC_V3_ITS if PCI_MSI
Will Deaconadace892013-05-08 17:29:24 +010022 select BUILDTIME_EXTABLE_SORT
Catalin Marinasdb2789b2012-12-18 15:27:25 +000023 select CLONE_BACKWARDS
Deepak Saxena7ca2ef32012-09-22 10:33:36 -070024 select COMMON_CLK
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +000025 select CPU_PM if (SUSPEND || CPU_IDLE)
Will Deacon7bc13fd2013-11-06 19:32:13 +000026 select DCACHE_WORD_ACCESS
Laura Abbottd4932f92014-10-09 15:26:44 -070027 select GENERIC_ALLOCATOR
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010028 select GENERIC_CLOCKEVENTS
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010029 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
Ard Biesheuvel3be1a5c2014-03-04 01:10:04 +000030 select GENERIC_CPU_AUTOPROBE
Mark Salterbf4b5582014-04-07 15:39:52 -070031 select GENERIC_EARLY_IOREMAP
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010032 select GENERIC_IRQ_PROBE
33 select GENERIC_IRQ_SHOW
Arnd Bergmanncb61f672014-11-19 14:09:07 +010034 select GENERIC_PCI_IOMAP
Stephen Boyd65cd4f62013-07-18 16:21:18 -070035 select GENERIC_SCHED_CLOCK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010036 select GENERIC_SMP_IDLE_THREAD
Will Deacon12a0ef72013-11-06 17:20:22 +000037 select GENERIC_STRNCPY_FROM_USER
38 select GENERIC_STRNLEN_USER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010039 select GENERIC_TIME_VSYSCALL
Marc Zyngiera1ddc742014-08-26 11:03:17 +010040 select HANDLE_DOMAIN_IRQ
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010041 select HARDIRQS_SW_RESEND
Steve Capper5284e1b2014-10-24 13:22:20 +010042 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010043 select HAVE_ARCH_AUDITSYSCALL
Yalin Wang8e7a4ce2014-11-03 03:02:23 +010044 select HAVE_ARCH_BITREVERSE
Jiang Liu9732caf2014-01-07 22:17:13 +080045 select HAVE_ARCH_JUMP_LABEL
Vijaya Kumar K95292472014-01-28 11:20:22 +000046 select HAVE_ARCH_KGDB
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +000047 select HAVE_ARCH_SECCOMP_FILTER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010048 select HAVE_ARCH_TRACEHOOK
Zi Shen Lime54bcde2014-08-26 21:15:30 -070049 select HAVE_BPF_JIT
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010050 select HAVE_C_RECORDMCOUNT
Laura Abbottc0c264a2014-06-25 23:55:03 +010051 select HAVE_CC_STACKPROTECTOR
Steve Capper5284e1b2014-10-24 13:22:20 +010052 select HAVE_CMPXCHG_DOUBLE
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070053 select HAVE_DEBUG_BUGVERBOSE
Catalin Marinasb69ec422012-10-08 16:28:11 -070054 select HAVE_DEBUG_KMEMLEAK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010055 select HAVE_DMA_API_DEBUG
56 select HAVE_DMA_ATTRS
Laura Abbott6ac21042013-12-12 19:28:33 +000057 select HAVE_DMA_CONTIGUOUS
AKASHI Takahirobd7d38d2014-04-30 10:54:34 +010058 select HAVE_DYNAMIC_FTRACE
Will Deacon50afc332013-12-16 17:50:08 +000059 select HAVE_EFFICIENT_UNALIGNED_ACCESS
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010060 select HAVE_FTRACE_MCOUNT_RECORD
AKASHI Takahiro819e50e2014-04-30 18:54:33 +090061 select HAVE_FUNCTION_TRACER
62 select HAVE_FUNCTION_GRAPH_TRACER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010063 select HAVE_GENERIC_DMA_COHERENT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010064 select HAVE_HW_BREAKPOINT if PERF_EVENTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010065 select HAVE_MEMBLOCK
Mark Rutland55834a72014-02-07 17:12:45 +000066 select HAVE_PATA_PLATFORM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010067 select HAVE_PERF_EVENTS
Jean Pihet2ee0d7f2014-02-03 19:18:27 +010068 select HAVE_PERF_REGS
69 select HAVE_PERF_USER_STACK_DUMP
Steve Capper5e5f6dc2014-10-09 15:29:23 -070070 select HAVE_RCU_TABLE_FREE
AKASHI Takahiro055b1212014-04-30 10:54:36 +010071 select HAVE_SYSCALL_TRACEPOINTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010072 select IRQ_DOMAIN
Catalin Marinasfea2aca2012-10-16 11:26:57 +010073 select MODULES_USE_ELF_RELA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010074 select NO_BOOTMEM
75 select OF
76 select OF_EARLY_FLATTREE
Marek Szyprowski9bf14b72014-02-28 14:42:55 +010077 select OF_RESERVED_MEM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010078 select PERF_USE_VMALLOC
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +000079 select POWER_RESET
80 select POWER_SUPPLY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010081 select RTC_LIB
82 select SPARSE_IRQ
Catalin Marinas7ac57a82012-10-08 16:28:16 -070083 select SYSCTL_EXCEPTION_TRACE
Larry Bassel6c81fe72014-05-30 12:34:15 -070084 select HAVE_CONTEXT_TRACKING
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010085 help
86 ARM 64-bit (AArch64) Linux support.
87
88config 64BIT
89 def_bool y
90
91config ARCH_PHYS_ADDR_T_64BIT
92 def_bool y
93
94config MMU
95 def_bool y
96
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -070097config NO_IOPORT_MAP
Liviu Dudaud1e6dc92014-09-29 15:29:31 +010098 def_bool y if !PCI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010099
100config STACKTRACE_SUPPORT
101 def_bool y
102
103config LOCKDEP_SUPPORT
104 def_bool y
105
106config TRACE_IRQFLAGS_SUPPORT
107 def_bool y
108
Will Deaconc209f792014-03-14 17:47:05 +0000109config RWSEM_XCHGADD_ALGORITHM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100110 def_bool y
111
112config GENERIC_HWEIGHT
113 def_bool y
114
115config GENERIC_CSUM
116 def_bool y
117
118config GENERIC_CALIBRATE_DELAY
119 def_bool y
120
Catalin Marinas19e76402014-02-27 12:09:22 +0000121config ZONE_DMA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100122 def_bool y
123
Steve Capper29e56942014-10-09 15:29:25 -0700124config HAVE_GENERIC_RCU_GUP
125 def_bool y
126
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100127config ARCH_DMA_ADDR_T_64BIT
128 def_bool y
129
130config NEED_DMA_MAP_STATE
131 def_bool y
132
133config NEED_SG_DMA_LENGTH
134 def_bool y
135
136config SWIOTLB
137 def_bool y
138
139config IOMMU_HELPER
140 def_bool SWIOTLB
141
Ard Biesheuvel4cfb3612013-07-09 14:18:12 +0100142config KERNEL_MODE_NEON
143 def_bool y
144
Rob Herring92cc15f2014-04-18 17:19:59 -0500145config FIX_EARLYCON_MEM
146 def_bool y
147
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700148config PGTABLE_LEVELS
149 int
150 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
151 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
152 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
153 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
154
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100155source "init/Kconfig"
156
157source "kernel/Kconfig.freezer"
158
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100159menu "Platform selection"
160
Alim Akhtar6f56eef2014-11-22 22:41:52 +0900161config ARCH_EXYNOS
162 bool
163 help
164 This enables support for Samsung Exynos SoC family
165
166config ARCH_EXYNOS7
167 bool "ARMv8 based Samsung Exynos7"
168 select ARCH_EXYNOS
169 select COMMON_CLK_SAMSUNG
170 select HAVE_S3C2410_WATCHDOG if WATCHDOG
171 select HAVE_S3C_RTC if RTC_CLASS
172 select PINCTRL
173 select PINCTRL_EXYNOS
174
175 help
176 This enables support for Samsung Exynos7 SoC family
177
Olof Johansson5118a6a2015-01-27 16:19:11 -0800178config ARCH_FSL_LS2085A
179 bool "Freescale LS2085A SOC"
180 help
181 This enables support for Freescale LS2085A SOC.
182
Eddie Huang4727a6f2015-12-01 10:14:00 +0100183config ARCH_MEDIATEK
184 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
185 select ARM_GIC
Yingjoe Chen0a233cd2015-03-06 14:24:50 +0800186 select PINCTRL
Eddie Huang4727a6f2015-12-01 10:14:00 +0100187 help
188 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
189
Abhimanyu Kapurd7f64a42013-10-15 21:11:09 -0700190config ARCH_QCOM
191 bool "Qualcomm Platforms"
192 select PINCTRL
193 help
194 This enables support for the ARMv8 based Qualcomm chipsets.
195
Suravee Suthikulpanit41904362014-11-26 11:51:09 +0700196config ARCH_SEATTLE
197 bool "AMD Seattle SoC Family"
198 help
199 This enables support for AMD Seattle SOC Family
200
Paul Walmsleyd035fdf2015-01-07 01:17:33 -0700201config ARCH_TEGRA
202 bool "NVIDIA Tegra SoC Family"
203 select ARCH_HAS_RESET_CONTROLLER
204 select ARCH_REQUIRE_GPIOLIB
205 select CLKDEV_LOOKUP
206 select CLKSRC_MMIO
207 select CLKSRC_OF
208 select GENERIC_CLOCKEVENTS
209 select HAVE_CLK
Paul Walmsleyd035fdf2015-01-07 01:17:33 -0700210 select PINCTRL
211 select RESET_CONTROLLER
212 help
213 This enables support for the NVIDIA Tegra SoC family.
214
215config ARCH_TEGRA_132_SOC
216 bool "NVIDIA Tegra132 SoC"
217 depends on ARCH_TEGRA
218 select PINCTRL_TEGRA124
Paul Walmsleyd035fdf2015-01-07 01:17:33 -0700219 select USB_ULPI if USB_PHY
220 select USB_ULPI_VIEWPORT if USB_PHY
221 help
222 Enable support for NVIDIA Tegra132 SoC, based on the Denver
223 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
224 but contains an NVIDIA Denver CPU complex in place of
225 Tegra124's "4+1" Cortex-A15 CPU complex.
226
Zhizhou Zhangc4bb7992015-03-11 02:27:08 +0000227config ARCH_SPRD
228 bool "Spreadtrum SoC platform"
229 help
230 Support for Spreadtrum ARM based SoCs
231
Radha Mohan Chintakuntla28f74202014-04-08 18:47:51 +0530232config ARCH_THUNDER
233 bool "Cavium Inc. Thunder SoC Family"
234 help
235 This enables support for Cavium's Thunder Family of SoCs.
236
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100237config ARCH_VEXPRESS
238 bool "ARMv8 software model (Versatile Express)"
239 select ARCH_REQUIRE_GPIOLIB
240 select COMMON_CLK_VERSATILE
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +0000241 select POWER_RESET_VEXPRESS
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100242 select VEXPRESS_CONFIG
243 help
244 This enables support for the ARMv8 software model (Versatile
245 Express).
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100246
Vinayak Kale15942852013-04-24 10:06:57 +0100247config ARCH_XGENE
248 bool "AppliedMicro X-Gene SOC Family"
249 help
250 This enables support for AppliedMicro X-Gene SOC Family
251
Michal Simek5d1b79d2015-03-09 09:41:04 +0100252config ARCH_ZYNQMP
253 bool "Xilinx ZynqMP Family"
254 help
255 This enables support for Xilinx ZynqMP Family
256
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100257endmenu
258
259menu "Bus support"
260
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100261config PCI
262 bool "PCI support"
263 help
264 This feature enables support for PCI bus system. If you say Y
265 here, the kernel will include drivers and infrastructure code
266 to support PCI bus devices.
267
268config PCI_DOMAINS
269 def_bool PCI
270
271config PCI_DOMAINS_GENERIC
272 def_bool PCI
273
274config PCI_SYSCALL
275 def_bool PCI
276
277source "drivers/pci/Kconfig"
278source "drivers/pci/pcie/Kconfig"
279source "drivers/pci/hotplug/Kconfig"
280
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100281endmenu
282
283menu "Kernel Features"
284
Andre Przywarac0a01b82014-11-14 15:54:12 +0000285menu "ARM errata workarounds via the alternatives framework"
286
287config ARM64_ERRATUM_826319
288 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
289 default y
290 help
291 This option adds an alternative code sequence to work around ARM
292 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
293 AXI master interface and an L2 cache.
294
295 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
296 and is unable to accept a certain write via this interface, it will
297 not progress on read data presented on the read data channel and the
298 system can deadlock.
299
300 The workaround promotes data cache clean instructions to
301 data cache clean-and-invalidate.
302 Please note that this does not necessarily enable the workaround,
303 as it depends on the alternative framework, which will only patch
304 the kernel if an affected CPU is detected.
305
306 If unsure, say Y.
307
308config ARM64_ERRATUM_827319
309 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
310 default y
311 help
312 This option adds an alternative code sequence to work around ARM
313 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
314 master interface and an L2 cache.
315
316 Under certain conditions this erratum can cause a clean line eviction
317 to occur at the same time as another transaction to the same address
318 on the AMBA 5 CHI interface, which can cause data corruption if the
319 interconnect reorders the two transactions.
320
321 The workaround promotes data cache clean instructions to
322 data cache clean-and-invalidate.
323 Please note that this does not necessarily enable the workaround,
324 as it depends on the alternative framework, which will only patch
325 the kernel if an affected CPU is detected.
326
327 If unsure, say Y.
328
329config ARM64_ERRATUM_824069
330 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
331 default y
332 help
333 This option adds an alternative code sequence to work around ARM
334 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
335 to a coherent interconnect.
336
337 If a Cortex-A53 processor is executing a store or prefetch for
338 write instruction at the same time as a processor in another
339 cluster is executing a cache maintenance operation to the same
340 address, then this erratum might cause a clean cache line to be
341 incorrectly marked as dirty.
342
343 The workaround promotes data cache clean instructions to
344 data cache clean-and-invalidate.
345 Please note that this option does not necessarily enable the
346 workaround, as it depends on the alternative framework, which will
347 only patch the kernel if an affected CPU is detected.
348
349 If unsure, say Y.
350
351config ARM64_ERRATUM_819472
352 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
353 default y
354 help
355 This option adds an alternative code sequence to work around ARM
356 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
357 present when it is connected to a coherent interconnect.
358
359 If the processor is executing a load and store exclusive sequence at
360 the same time as a processor in another cluster is executing a cache
361 maintenance operation to the same address, then this erratum might
362 cause data corruption.
363
364 The workaround promotes data cache clean instructions to
365 data cache clean-and-invalidate.
366 Please note that this does not necessarily enable the workaround,
367 as it depends on the alternative framework, which will only patch
368 the kernel if an affected CPU is detected.
369
370 If unsure, say Y.
371
372config ARM64_ERRATUM_832075
373 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
374 default y
375 help
376 This option adds an alternative code sequence to work around ARM
377 erratum 832075 on Cortex-A57 parts up to r1p2.
378
379 Affected Cortex-A57 parts might deadlock when exclusive load/store
380 instructions to Write-Back memory are mixed with Device loads.
381
382 The workaround is to promote device loads to use Load-Acquire
383 semantics.
384 Please note that this does not necessarily enable the workaround,
385 as it depends on the alternative framework, which will only patch
386 the kernel if an affected CPU is detected.
387
388 If unsure, say Y.
389
Will Deacon905e8c52015-03-23 19:07:02 +0000390config ARM64_ERRATUM_845719
391 bool "Cortex-A53: 845719: a load might read incorrect data"
392 depends on COMPAT
393 default y
394 help
395 This option adds an alternative code sequence to work around ARM
396 erratum 845719 on Cortex-A53 parts up to r0p4.
397
398 When running a compat (AArch32) userspace on an affected Cortex-A53
399 part, a load at EL0 from a virtual address that matches the bottom 32
400 bits of the virtual address used by a recent load at (AArch64) EL1
401 might return incorrect data.
402
403 The workaround is to write the contextidr_el1 register on exception
404 return to a 32-bit task.
405 Please note that this does not necessarily enable the workaround,
406 as it depends on the alternative framework, which will only patch
407 the kernel if an affected CPU is detected.
408
409 If unsure, say Y.
410
Andre Przywarac0a01b82014-11-14 15:54:12 +0000411endmenu
412
413
Jungseok Leee41ceed2014-05-12 10:40:38 +0100414choice
415 prompt "Page size"
416 default ARM64_4K_PAGES
417 help
418 Page size (translation granule) configuration.
419
420config ARM64_4K_PAGES
421 bool "4KB"
422 help
423 This feature enables 4KB pages support.
424
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100425config ARM64_64K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100426 bool "64KB"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100427 help
428 This feature enables 64KB pages support (4KB by default)
429 allowing only two levels of page tables and faster TLB
430 look-up. AArch32 emulation is not available when this feature
431 is enabled.
432
Jungseok Leee41ceed2014-05-12 10:40:38 +0100433endchoice
434
435choice
436 prompt "Virtual address space size"
437 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
438 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
439 help
440 Allows choosing one of multiple possible virtual address
441 space sizes. The level of translation table is determined by
442 a combination of page size and virtual address space size.
443
444config ARM64_VA_BITS_39
445 bool "39-bit"
446 depends on ARM64_4K_PAGES
447
448config ARM64_VA_BITS_42
449 bool "42-bit"
450 depends on ARM64_64K_PAGES
451
Jungseok Leec79b9542014-05-12 18:40:51 +0900452config ARM64_VA_BITS_48
453 bool "48-bit"
Jungseok Leec79b9542014-05-12 18:40:51 +0900454
Jungseok Leee41ceed2014-05-12 10:40:38 +0100455endchoice
456
457config ARM64_VA_BITS
458 int
459 default 39 if ARM64_VA_BITS_39
460 default 42 if ARM64_VA_BITS_42
Jungseok Leec79b9542014-05-12 18:40:51 +0900461 default 48 if ARM64_VA_BITS_48
Jungseok Leee41ceed2014-05-12 10:40:38 +0100462
Will Deacona8720132013-10-11 14:52:19 +0100463config CPU_BIG_ENDIAN
464 bool "Build big-endian kernel"
465 help
466 Say Y if you plan on running a kernel in big-endian mode.
467
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100468config SMP
469 bool "Symmetric Multi-Processing"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100470 help
471 This enables support for systems with more than one CPU. If
472 you say N here, the kernel will run on single and
473 multiprocessor machines, but will use only one CPU of a
474 multiprocessor machine. If you say Y here, the kernel will run
475 on many, but not all, single processor machines. On a single
476 processor machine, the kernel will run faster if you say N
477 here.
478
479 If you don't know what to do here, say N.
480
Mark Brownf6e763b2014-03-04 07:51:17 +0000481config SCHED_MC
482 bool "Multi-core scheduler support"
483 depends on SMP
484 help
485 Multi-core scheduler support improves the CPU scheduler's decision
486 making when dealing with multi-core CPU chips at a cost of slightly
487 increased overhead in some places. If unsure say N here.
488
489config SCHED_SMT
490 bool "SMT scheduler support"
491 depends on SMP
492 help
493 Improves the CPU scheduler's decision making when dealing with
494 MultiThreading at a cost of slightly increased overhead in some
495 places. If unsure say N here.
496
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100497config NR_CPUS
Ganapatrao Kulkarni62aa9652015-03-18 11:01:18 +0000498 int "Maximum number of CPUs (2-4096)"
499 range 2 4096
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100500 depends on SMP
Vinayak Kale15942852013-04-24 10:06:57 +0100501 # These have to remain sorted largest to smallest
Robert Richtere3672642014-09-08 12:44:48 +0100502 default "64"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100503
Mark Rutland9327e2c2013-10-24 20:30:18 +0100504config HOTPLUG_CPU
505 bool "Support for hot-pluggable CPUs"
506 depends on SMP
507 help
508 Say Y here to experiment with turning CPUs off and on. CPUs
509 can be controlled through /sys/devices/system/cpu.
510
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100511source kernel/Kconfig.preempt
512
Mark Rutland137650aa2015-03-13 16:14:34 +0000513config UP_LATE_INIT
514 def_bool y
515 depends on !SMP
516
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100517config HZ
518 int
519 default 100
520
521config ARCH_HAS_HOLES_MEMORYMODEL
522 def_bool y if SPARSEMEM
523
524config ARCH_SPARSEMEM_ENABLE
525 def_bool y
526 select SPARSEMEM_VMEMMAP_ENABLE
527
528config ARCH_SPARSEMEM_DEFAULT
529 def_bool ARCH_SPARSEMEM_ENABLE
530
531config ARCH_SELECT_MEMORY_MODEL
532 def_bool ARCH_SPARSEMEM_ENABLE
533
534config HAVE_ARCH_PFN_VALID
535 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
536
537config HW_PERF_EVENTS
538 bool "Enable hardware performance counter support for perf events"
539 depends on PERF_EVENTS
540 default y
541 help
542 Enable hardware performance counter support for perf events. If
543 disabled, perf events will use software events only.
544
Steve Capper084bd292013-04-10 13:48:00 +0100545config SYS_SUPPORTS_HUGETLBFS
546 def_bool y
547
548config ARCH_WANT_GENERAL_HUGETLB
549 def_bool y
550
551config ARCH_WANT_HUGE_PMD_SHARE
552 def_bool y if !ARM64_64K_PAGES
553
Steve Capperaf074842013-04-19 16:23:57 +0100554config HAVE_ARCH_TRANSPARENT_HUGEPAGE
555 def_bool y
556
Catalin Marinasa41dc0e2014-04-03 17:48:54 +0100557config ARCH_HAS_CACHE_LINE_SIZE
558 def_bool y
559
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100560source "mm/Kconfig"
561
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +0000562config SECCOMP
563 bool "Enable seccomp to safely compute untrusted bytecode"
564 ---help---
565 This kernel feature is useful for number crunching applications
566 that may need to compute untrusted bytecode during their
567 execution. By using pipes or other transports made available to
568 the process as file descriptors supporting the read/write
569 syscalls, it's possible to isolate those applications in
570 their own address space using seccomp. Once seccomp is
571 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
572 and the task is only allowed to execute a few safe syscalls
573 defined by each seccomp mode.
574
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000575config XEN_DOM0
576 def_bool y
577 depends on XEN
578
579config XEN
Julien Grallc2ba1f72014-09-17 14:07:06 -0700580 bool "Xen guest support on ARM64"
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000581 depends on ARM64 && OF
Stefano Stabellini83862cc2013-10-10 13:40:44 +0000582 select SWIOTLB_XEN
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000583 help
584 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
585
Steve Capperd03bb142013-04-25 15:19:21 +0100586config FORCE_MAX_ZONEORDER
587 int
588 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
589 default "11"
590
Will Deacon1b907f42014-11-20 16:51:10 +0000591menuconfig ARMV8_DEPRECATED
592 bool "Emulate deprecated/obsolete ARMv8 instructions"
593 depends on COMPAT
594 help
595 Legacy software support may require certain instructions
596 that have been deprecated or obsoleted in the architecture.
597
598 Enable this config to enable selective emulation of these
599 features.
600
601 If unsure, say Y
602
603if ARMV8_DEPRECATED
604
605config SWP_EMULATION
606 bool "Emulate SWP/SWPB instructions"
607 help
608 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
609 they are always undefined. Say Y here to enable software
610 emulation of these instructions for userspace using LDXR/STXR.
611
612 In some older versions of glibc [<=2.8] SWP is used during futex
613 trylock() operations with the assumption that the code will not
614 be preempted. This invalid assumption may be more likely to fail
615 with SWP emulation enabled, leading to deadlock of the user
616 application.
617
618 NOTE: when accessing uncached shared regions, LDXR/STXR rely
619 on an external transaction monitoring block called a global
620 monitor to maintain update atomicity. If your system does not
621 implement a global monitor, this option can cause programs that
622 perform SWP operations to uncached memory to deadlock.
623
624 If unsure, say Y
625
626config CP15_BARRIER_EMULATION
627 bool "Emulate CP15 Barrier instructions"
628 help
629 The CP15 barrier instructions - CP15ISB, CP15DSB, and
630 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
631 strongly recommended to use the ISB, DSB, and DMB
632 instructions instead.
633
634 Say Y here to enable software emulation of these
635 instructions for AArch32 userspace code. When this option is
636 enabled, CP15 barrier usage is traced which can help
637 identify software that needs updating.
638
639 If unsure, say Y
640
Suzuki K. Poulose2d888f42015-01-21 12:43:11 +0000641config SETEND_EMULATION
642 bool "Emulate SETEND instruction"
643 help
644 The SETEND instruction alters the data-endianness of the
645 AArch32 EL0, and is deprecated in ARMv8.
646
647 Say Y here to enable software emulation of the instruction
648 for AArch32 userspace code.
649
650 Note: All the cpus on the system must have mixed endian support at EL0
651 for this feature to be enabled. If a new CPU - which doesn't support mixed
652 endian - is hotplugged in after this feature has been enabled, there could
653 be unexpected results in the applications.
654
655 If unsure, say Y
Will Deacon1b907f42014-11-20 16:51:10 +0000656endif
657
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100658endmenu
659
660menu "Boot options"
661
662config CMDLINE
663 string "Default kernel command string"
664 default ""
665 help
666 Provide a set of default command-line options at build time by
667 entering them here. As a minimum, you should specify the the
668 root device (e.g. root=/dev/nfs).
669
670config CMDLINE_FORCE
671 bool "Always use the default kernel command string"
672 help
673 Always use the default kernel command string, even if the boot
674 loader passes other arguments to the kernel.
675 This is useful if you cannot or don't want to change the
676 command-line options your boot loader passes to the kernel.
677
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200678config EFI_STUB
679 bool
680
Mark Salterf84d0272014-04-15 21:59:30 -0400681config EFI
682 bool "UEFI runtime support"
683 depends on OF && !CPU_BIG_ENDIAN
684 select LIBFDT
685 select UCS2_STRING
686 select EFI_PARAMS_FROM_FDT
Ard Biesheuvele15dd492014-07-04 19:41:53 +0200687 select EFI_RUNTIME_WRAPPERS
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200688 select EFI_STUB
689 select EFI_ARMSTUB
Mark Salterf84d0272014-04-15 21:59:30 -0400690 default y
691 help
692 This option provides support for runtime services provided
693 by UEFI firmware (such as non-volatile variables, realtime
Mark Salter3c7f2552014-04-15 22:47:52 -0400694 clock, and platform reset). A UEFI stub is also provided to
695 allow the kernel to be booted as an EFI application. This
696 is only useful on systems that have UEFI firmware.
Mark Salterf84d0272014-04-15 21:59:30 -0400697
Yi Lid1ae8c02014-10-04 23:46:43 +0800698config DMI
699 bool "Enable support for SMBIOS (DMI) tables"
700 depends on EFI
701 default y
702 help
703 This enables SMBIOS/DMI feature for systems.
704
705 This option is only useful on systems that have UEFI firmware.
706 However, even with this option, the resultant kernel should
707 continue to boot on existing non-UEFI platforms.
708
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100709endmenu
710
711menu "Userspace binary formats"
712
713source "fs/Kconfig.binfmt"
714
715config COMPAT
716 bool "Kernel support for 32-bit EL0"
Alexander Grafa8fcd8b2015-03-16 16:32:23 +0000717 depends on !ARM64_64K_PAGES || EXPERT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100718 select COMPAT_BINFMT_ELF
Catalin Marinasaf1839e2012-10-08 16:28:08 -0700719 select HAVE_UID16
Al Viro84b9e9b2012-12-25 16:29:11 -0500720 select OLD_SIGSUSPEND3
Al Viro51682032012-12-25 19:31:29 -0500721 select COMPAT_OLD_SIGACTION
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100722 help
723 This option enables support for a 32-bit EL0 running under a 64-bit
724 kernel at EL1. AArch32-specific components such as system calls,
725 the user helper functions, VFP support and the ptrace interface are
726 handled appropriately by the kernel.
727
Alexander Grafa8fcd8b2015-03-16 16:32:23 +0000728 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
729 will only be able to execute AArch32 binaries that were compiled with
730 64k aligned segments.
731
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100732 If you want to execute 32-bit userspace applications, say Y.
733
734config SYSVIPC_COMPAT
735 def_bool y
736 depends on COMPAT && SYSVIPC
737
738endmenu
739
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000740menu "Power management options"
741
742source "kernel/power/Kconfig"
743
744config ARCH_SUSPEND_POSSIBLE
745 def_bool y
746
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000747endmenu
748
Lorenzo Pieralisi13072202013-07-17 14:54:21 +0100749menu "CPU Power Management"
750
751source "drivers/cpuidle/Kconfig"
752
Rob Herring52e7e812014-02-24 11:27:57 +0900753source "drivers/cpufreq/Kconfig"
754
755endmenu
756
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100757source "net/Kconfig"
758
759source "drivers/Kconfig"
760
Mark Salterf84d0272014-04-15 21:59:30 -0400761source "drivers/firmware/Kconfig"
762
Graeme Gregoryb6a02172015-03-24 14:02:53 +0000763source "drivers/acpi/Kconfig"
764
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100765source "fs/Kconfig"
766
Marc Zyngierc3eb5b12013-07-04 13:34:32 +0100767source "arch/arm64/kvm/Kconfig"
768
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100769source "arch/arm64/Kconfig.debug"
770
771source "security/Kconfig"
772
773source "crypto/Kconfig"
Ard Biesheuvel2c988332014-03-06 16:23:33 +0800774if CRYPTO
775source "arch/arm64/crypto/Kconfig"
776endif
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100777
778source "lib/Kconfig"