Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. |
| 3 | * |
| 4 | * This software is available to you under a choice of one of two |
| 5 | * licenses. You may choose to be licensed under the terms of the GNU |
| 6 | * General Public License (GPL) Version 2, available from the file |
| 7 | * COPYING in the main directory of this source tree, or the |
| 8 | * OpenIB.org BSD license below: |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or |
| 11 | * without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistributions of source code must retain the above |
| 15 | * copyright notice, this list of conditions and the following |
| 16 | * disclaimer. |
| 17 | * |
| 18 | * - Redistributions in binary form must reproduce the above |
| 19 | * copyright notice, this list of conditions and the following |
| 20 | * disclaimer in the documentation and/or other materials |
| 21 | * provided with the distribution. |
| 22 | * |
| 23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 30 | * SOFTWARE. |
| 31 | */ |
| 32 | |
| 33 | #ifndef MLX4_DEVICE_H |
| 34 | #define MLX4_DEVICE_H |
| 35 | |
Joe Perches | 574e2af | 2013-08-01 16:17:48 -0700 | [diff] [blame] | 36 | #include <linux/if_ether.h> |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 37 | #include <linux/pci.h> |
| 38 | #include <linux/completion.h> |
| 39 | #include <linux/radix-tree.h> |
Amir Vadai | d9236c3 | 2012-07-18 22:33:51 +0000 | [diff] [blame] | 40 | #include <linux/cpu_rmap.h> |
Amir Vadai | 48ea526 | 2014-08-25 16:06:53 +0300 | [diff] [blame] | 41 | #include <linux/crash_dump.h> |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 42 | |
Arun Sharma | 60063497 | 2011-07-26 16:09:06 -0700 | [diff] [blame] | 43 | #include <linux/atomic.h> |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 44 | |
Richard Cochran | 74d23cc | 2014-12-21 19:46:56 +0100 | [diff] [blame] | 45 | #include <linux/timecounter.h> |
Amir Vadai | ec693d4 | 2013-04-23 06:06:49 +0000 | [diff] [blame] | 46 | |
Yevgeny Petrilin | 0b7ca5a | 2011-03-22 22:37:47 +0000 | [diff] [blame] | 47 | #define MAX_MSIX_P_PORT 17 |
| 48 | #define MAX_MSIX 64 |
Yevgeny Petrilin | 0b7ca5a | 2011-03-22 22:37:47 +0000 | [diff] [blame] | 49 | #define MIN_MSIX_P_PORT 5 |
Matan Barak | c66fa19 | 2015-05-31 09:30:16 +0300 | [diff] [blame] | 50 | #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \ |
| 51 | (dev_cap).num_ports * MIN_MSIX_P_PORT) |
Yevgeny Petrilin | 0b7ca5a | 2011-03-22 22:37:47 +0000 | [diff] [blame] | 52 | |
Eugenia Emantayev | 523ece8 | 2014-07-08 11:25:19 +0300 | [diff] [blame] | 53 | #define MLX4_MAX_100M_UNITS_VAL 255 /* |
| 54 | * work around: can't set values |
| 55 | * greater then this value when |
| 56 | * using 100 Mbps units. |
| 57 | */ |
| 58 | #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */ |
| 59 | #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */ |
| 60 | #define MLX4_RATELIMIT_DEFAULT 0x00ff |
| 61 | |
Jack Morgenstein | 6ee51a4 | 2014-03-12 12:00:37 +0200 | [diff] [blame] | 62 | #define MLX4_ROCE_MAX_GIDS 128 |
Jack Morgenstein | b6ffaef | 2014-03-12 12:00:39 +0200 | [diff] [blame] | 63 | #define MLX4_ROCE_PF_GIDS 16 |
Jack Morgenstein | 6ee51a4 | 2014-03-12 12:00:37 +0200 | [diff] [blame] | 64 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 65 | enum { |
| 66 | MLX4_FLAG_MSI_X = 1 << 0, |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 67 | MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, |
Jack Morgenstein | 623ed84 | 2011-12-13 04:10:33 +0000 | [diff] [blame] | 68 | MLX4_FLAG_MASTER = 1 << 2, |
| 69 | MLX4_FLAG_SLAVE = 1 << 3, |
| 70 | MLX4_FLAG_SRIOV = 1 << 4, |
Jack Morgenstein | acddd5d | 2013-11-03 10:03:18 +0200 | [diff] [blame] | 71 | MLX4_FLAG_OLD_REG_MAC = 1 << 6, |
Moni Shoua | 53f33ae | 2015-02-03 16:48:33 +0200 | [diff] [blame] | 72 | MLX4_FLAG_BONDED = 1 << 7 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 73 | }; |
| 74 | |
| 75 | enum { |
Jack Morgenstein | efcd235 | 2012-08-03 08:40:52 +0000 | [diff] [blame] | 76 | MLX4_PORT_CAP_IS_SM = 1 << 1, |
| 77 | MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, |
| 78 | }; |
| 79 | |
| 80 | enum { |
Jack Morgenstein | fc06573 | 2012-08-03 08:40:42 +0000 | [diff] [blame] | 81 | MLX4_MAX_PORTS = 2, |
Moni Shoua | e26be1b | 2015-07-30 18:33:29 +0300 | [diff] [blame] | 82 | MLX4_MAX_PORT_PKEYS = 128, |
| 83 | MLX4_MAX_PORT_GIDS = 128 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 84 | }; |
| 85 | |
Jack Morgenstein | 396f2fe | 2012-06-19 11:21:42 +0300 | [diff] [blame] | 86 | /* base qkey for use in sriov tunnel-qp/proxy-qp communication. |
| 87 | * These qkeys must not be allowed for general use. This is a 64k range, |
| 88 | * and to test for violation, we use the mask (protect against future chg). |
| 89 | */ |
| 90 | #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) |
| 91 | #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) |
| 92 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 93 | enum { |
Jack Morgenstein | cd9281d | 2007-09-18 09:14:18 +0200 | [diff] [blame] | 94 | MLX4_BOARD_ID_LEN = 64 |
| 95 | }; |
| 96 | |
| 97 | enum { |
Jack Morgenstein | 623ed84 | 2011-12-13 04:10:33 +0000 | [diff] [blame] | 98 | MLX4_MAX_NUM_PF = 16, |
Matan Barak | de966c5 | 2014-11-13 14:45:33 +0200 | [diff] [blame] | 99 | MLX4_MAX_NUM_VF = 126, |
Matan Barak | 1ab95d3 | 2014-03-19 18:11:50 +0200 | [diff] [blame] | 100 | MLX4_MAX_NUM_VF_P_PORT = 64, |
Jack Morgenstein | 5a2e87b | 2015-02-02 15:18:42 +0200 | [diff] [blame] | 101 | MLX4_MFUNC_MAX = 128, |
Marcel Apfelbaum | 3fc929e | 2012-05-30 09:14:51 +0000 | [diff] [blame] | 102 | MLX4_MAX_EQ_NUM = 1024, |
Jack Morgenstein | 623ed84 | 2011-12-13 04:10:33 +0000 | [diff] [blame] | 103 | MLX4_MFUNC_EQ_NUM = 4, |
| 104 | MLX4_MFUNC_MAX_EQES = 8, |
| 105 | MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) |
| 106 | }; |
| 107 | |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 108 | /* Driver supports 3 diffrent device methods to manage traffic steering: |
| 109 | * -device managed - High level API for ib and eth flow steering. FW is |
| 110 | * managing flow steering tables. |
Hadar Hen Zion | c96d97f | 2012-07-05 04:03:44 +0000 | [diff] [blame] | 111 | * - B0 steering mode - Common low level API for ib and (if supported) eth. |
| 112 | * - A0 steering mode - Limited low level API for eth. In case of IB, |
| 113 | * B0 mode is in use. |
| 114 | */ |
| 115 | enum { |
| 116 | MLX4_STEERING_MODE_A0, |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 117 | MLX4_STEERING_MODE_B0, |
| 118 | MLX4_STEERING_MODE_DEVICE_MANAGED |
Hadar Hen Zion | c96d97f | 2012-07-05 04:03:44 +0000 | [diff] [blame] | 119 | }; |
| 120 | |
Matan Barak | 7d077cd | 2014-12-11 10:58:00 +0200 | [diff] [blame] | 121 | enum { |
| 122 | MLX4_STEERING_DMFS_A0_DEFAULT, |
| 123 | MLX4_STEERING_DMFS_A0_DYNAMIC, |
| 124 | MLX4_STEERING_DMFS_A0_STATIC, |
| 125 | MLX4_STEERING_DMFS_A0_DISABLE, |
| 126 | MLX4_STEERING_DMFS_A0_NOT_SUPPORTED |
| 127 | }; |
| 128 | |
Hadar Hen Zion | c96d97f | 2012-07-05 04:03:44 +0000 | [diff] [blame] | 129 | static inline const char *mlx4_steering_mode_str(int steering_mode) |
| 130 | { |
| 131 | switch (steering_mode) { |
| 132 | case MLX4_STEERING_MODE_A0: |
| 133 | return "A0 steering"; |
| 134 | |
| 135 | case MLX4_STEERING_MODE_B0: |
| 136 | return "B0 steering"; |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 137 | |
| 138 | case MLX4_STEERING_MODE_DEVICE_MANAGED: |
| 139 | return "Device managed flow steering"; |
| 140 | |
Hadar Hen Zion | c96d97f | 2012-07-05 04:03:44 +0000 | [diff] [blame] | 141 | default: |
| 142 | return "Unrecognize steering mode"; |
| 143 | } |
| 144 | } |
| 145 | |
Jack Morgenstein | 623ed84 | 2011-12-13 04:10:33 +0000 | [diff] [blame] | 146 | enum { |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 147 | MLX4_TUNNEL_OFFLOAD_MODE_NONE, |
| 148 | MLX4_TUNNEL_OFFLOAD_MODE_VXLAN |
| 149 | }; |
| 150 | |
| 151 | enum { |
Or Gerlitz | 52eafc6 | 2011-06-15 14:41:42 +0000 | [diff] [blame] | 152 | MLX4_DEV_CAP_FLAG_RC = 1LL << 0, |
| 153 | MLX4_DEV_CAP_FLAG_UC = 1LL << 1, |
| 154 | MLX4_DEV_CAP_FLAG_UD = 1LL << 2, |
Sean Hefty | 012a8ff | 2011-06-02 09:01:33 -0700 | [diff] [blame] | 155 | MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, |
Or Gerlitz | 52eafc6 | 2011-06-15 14:41:42 +0000 | [diff] [blame] | 156 | MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, |
| 157 | MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, |
| 158 | MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, |
| 159 | MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, |
| 160 | MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, |
| 161 | MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, |
| 162 | MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, |
| 163 | MLX4_DEV_CAP_FLAG_APM = 1LL << 17, |
| 164 | MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, |
| 165 | MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, |
| 166 | MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, |
| 167 | MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, |
Or Gerlitz | ccf8632 | 2011-07-07 19:19:29 +0000 | [diff] [blame] | 168 | MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, |
| 169 | MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, |
Yevgeny Petrilin | f3a9d1f | 2011-10-18 01:50:42 +0000 | [diff] [blame] | 170 | MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, |
Oren Duer | 559a9f1 | 2011-11-26 19:55:15 +0000 | [diff] [blame] | 171 | MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, |
| 172 | MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, |
Or Gerlitz | ccf8632 | 2011-07-07 19:19:29 +0000 | [diff] [blame] | 173 | MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, |
| 174 | MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, |
Or Gerlitz | f2a3f6a | 2011-06-15 14:47:14 +0000 | [diff] [blame] | 175 | MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, |
Yevgeny Petrilin | 58a6016 | 2011-12-19 04:00:26 +0000 | [diff] [blame] | 176 | MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, |
Ido Shamay | 802f42a | 2015-04-02 16:31:06 +0300 | [diff] [blame] | 177 | MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52, |
Or Gerlitz | 540b3a3 | 2013-04-07 03:44:07 +0000 | [diff] [blame] | 178 | MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, |
Jack Morgenstein | 00f5ce9 | 2012-06-19 11:21:40 +0300 | [diff] [blame] | 179 | MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, |
| 180 | MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 181 | MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, |
| 182 | MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 183 | }; |
| 184 | |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 185 | enum { |
| 186 | MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, |
| 187 | MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 188 | MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, |
Matan Barak | 955154f | 2013-01-30 23:07:10 +0000 | [diff] [blame] | 189 | MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, |
Or Gerlitz | 5930e8d | 2013-10-15 16:55:22 +0200 | [diff] [blame] | 190 | MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4, |
Rony Efraim | 3f7fb02 | 2013-04-25 05:22:28 +0000 | [diff] [blame] | 191 | MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, |
Rony Efraim | e6b6a23 | 2013-04-25 05:22:29 +0000 | [diff] [blame] | 192 | MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, |
Jack Morgenstein | b01978c | 2013-06-27 19:05:21 +0300 | [diff] [blame] | 193 | MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, |
Matan Barak | 4de6580 | 2013-11-07 15:25:14 +0200 | [diff] [blame] | 194 | MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8, |
Linus Torvalds | 4ba9920 | 2014-01-25 11:17:34 -0800 | [diff] [blame] | 195 | MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9, |
| 196 | MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, |
Jack Morgenstein | 114840c | 2014-06-01 11:53:50 +0300 | [diff] [blame] | 197 | MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11, |
Ido Shamay | 77507aa | 2014-09-18 11:50:59 +0300 | [diff] [blame] | 198 | MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12, |
Saeed Mahameed | adbc7ac | 2014-10-27 11:37:37 +0200 | [diff] [blame] | 199 | MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13, |
Saeed Mahameed | a53e3e8 | 2014-10-27 11:37:38 +0200 | [diff] [blame] | 200 | MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14, |
Matan Barak | d475c95 | 2014-11-02 16:26:17 +0200 | [diff] [blame] | 201 | MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15, |
Matan Barak | 7ae0e40 | 2014-11-13 14:45:32 +0200 | [diff] [blame] | 202 | MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16, |
Matan Barak | de966c5 | 2014-11-13 14:45:33 +0200 | [diff] [blame] | 203 | MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17, |
Matan Barak | 7d077cd | 2014-12-11 10:58:00 +0200 | [diff] [blame] | 204 | MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18, |
Jack Morgenstein | be6a6b4 | 2015-01-27 15:57:59 +0200 | [diff] [blame] | 205 | MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19, |
Moni Shoua | 59e14e3 | 2015-02-03 16:48:32 +0200 | [diff] [blame] | 206 | MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20, |
Shani Michaeli | d237baa | 2015-03-05 20:16:12 +0200 | [diff] [blame] | 207 | MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21, |
| 208 | MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22, |
Matan Barak | 0b13156 | 2015-03-30 17:45:25 +0300 | [diff] [blame] | 209 | MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23, |
Ido Shamay | d019fcb | 2015-04-02 16:31:13 +0300 | [diff] [blame] | 210 | MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24, |
| 211 | MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25, |
Ido Shamay | 3742cc6 | 2015-04-02 16:31:17 +0300 | [diff] [blame] | 212 | MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26, |
Ido Shamay | 51af33c | 2015-04-02 16:31:20 +0300 | [diff] [blame] | 213 | MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27, |
Muhammad Mahajna | 78500b8 | 2015-04-02 16:31:22 +0300 | [diff] [blame] | 214 | MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28, |
Hadar Hen Zion | 77fc29c | 2015-07-27 14:46:31 +0300 | [diff] [blame] | 215 | MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29, |
| 216 | MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30, |
Maor Gottlieb | 9a89283 | 2015-10-15 14:44:38 +0300 | [diff] [blame] | 217 | MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31, |
| 218 | MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32, |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 219 | }; |
| 220 | |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 221 | enum { |
Matan Barak | d57febe | 2014-12-11 10:57:57 +0200 | [diff] [blame] | 222 | MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0, |
| 223 | MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1 |
Eugenia Emantayev | ddae034 | 2014-12-11 10:57:54 +0200 | [diff] [blame] | 224 | }; |
| 225 | |
Yishai Hadas | 55ad359 | 2015-01-25 16:59:42 +0200 | [diff] [blame] | 226 | enum { |
| 227 | MLX4_VF_CAP_FLAG_RESET = 1 << 0 |
| 228 | }; |
| 229 | |
Eugenia Emantayev | ddae034 | 2014-12-11 10:57:54 +0200 | [diff] [blame] | 230 | /* bit enums for an 8-bit flags field indicating special use |
| 231 | * QPs which require special handling in qp_reserve_range. |
| 232 | * Currently, this only includes QPs used by the ETH interface, |
| 233 | * where we expect to use blueflame. These QPs must not have |
| 234 | * bits 6 and 7 set in their qp number. |
| 235 | * |
| 236 | * This enum may use only bits 0..7. |
| 237 | */ |
| 238 | enum { |
Matan Barak | d57febe | 2014-12-11 10:57:57 +0200 | [diff] [blame] | 239 | MLX4_RESERVE_A0_QP = 1 << 6, |
Eugenia Emantayev | ddae034 | 2014-12-11 10:57:54 +0200 | [diff] [blame] | 240 | MLX4_RESERVE_ETH_BF_QP = 1 << 7, |
| 241 | }; |
| 242 | |
| 243 | enum { |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 244 | MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, |
Ido Shamay | 77507aa | 2014-09-18 11:50:59 +0300 | [diff] [blame] | 245 | MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1, |
| 246 | MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2, |
| 247 | MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3 |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 248 | }; |
| 249 | |
| 250 | enum { |
Ido Shamay | 77507aa | 2014-09-18 11:50:59 +0300 | [diff] [blame] | 251 | MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0 |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 252 | }; |
| 253 | |
| 254 | enum { |
Ido Shamay | 77507aa | 2014-09-18 11:50:59 +0300 | [diff] [blame] | 255 | MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0, |
Matan Barak | 7d077cd | 2014-12-11 10:58:00 +0200 | [diff] [blame] | 256 | MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1, |
| 257 | MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2 |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 258 | }; |
| 259 | |
| 260 | |
Marcel Apfelbaum | 97285b7 | 2011-10-24 11:02:34 +0200 | [diff] [blame] | 261 | #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) |
| 262 | |
| 263 | enum { |
Shani Michaeli | 804d6a8 | 2013-02-06 16:19:14 +0000 | [diff] [blame] | 264 | MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, |
Roland Dreier | 95d04f0 | 2008-07-23 08:12:26 -0700 | [diff] [blame] | 265 | MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, |
| 266 | MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, |
| 267 | MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, |
| 268 | MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, |
| 269 | MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, |
Moni Shoua | 59e14e3 | 2015-02-03 16:48:32 +0200 | [diff] [blame] | 270 | MLX4_BMME_FLAG_PORT_REMAP = 1 << 24, |
Matan Barak | 09e05c3 | 2014-09-10 16:41:56 +0300 | [diff] [blame] | 271 | MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28, |
Roland Dreier | 95d04f0 | 2008-07-23 08:12:26 -0700 | [diff] [blame] | 272 | }; |
| 273 | |
Moni Shoua | 59e14e3 | 2015-02-03 16:48:32 +0200 | [diff] [blame] | 274 | enum { |
| 275 | MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP |
| 276 | }; |
| 277 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 278 | enum mlx4_event { |
| 279 | MLX4_EVENT_TYPE_COMP = 0x00, |
| 280 | MLX4_EVENT_TYPE_PATH_MIG = 0x01, |
| 281 | MLX4_EVENT_TYPE_COMM_EST = 0x02, |
| 282 | MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, |
| 283 | MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, |
| 284 | MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, |
| 285 | MLX4_EVENT_TYPE_CQ_ERROR = 0x04, |
| 286 | MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, |
| 287 | MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, |
| 288 | MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, |
| 289 | MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, |
| 290 | MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, |
| 291 | MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, |
| 292 | MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, |
| 293 | MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, |
| 294 | MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, |
| 295 | MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, |
Jack Morgenstein | 623ed84 | 2011-12-13 04:10:33 +0000 | [diff] [blame] | 296 | MLX4_EVENT_TYPE_CMD = 0x0a, |
| 297 | MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, |
| 298 | MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, |
Yevgeny Petrilin | fe6f700 | 2013-07-28 18:54:21 +0300 | [diff] [blame] | 299 | MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, |
Jack Morgenstein | 5984be9 | 2012-03-06 15:50:49 +0200 | [diff] [blame] | 300 | MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, |
Jack Morgenstein | 623ed84 | 2011-12-13 04:10:33 +0000 | [diff] [blame] | 301 | MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, |
Jack Morgenstein | 00f5ce9 | 2012-06-19 11:21:40 +0300 | [diff] [blame] | 302 | MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, |
Jack Morgenstein | be6a6b4 | 2015-01-27 15:57:59 +0200 | [diff] [blame] | 303 | MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e, |
Jack Morgenstein | 623ed84 | 2011-12-13 04:10:33 +0000 | [diff] [blame] | 304 | MLX4_EVENT_TYPE_NONE = 0xff, |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 305 | }; |
| 306 | |
| 307 | enum { |
| 308 | MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, |
| 309 | MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 |
| 310 | }; |
| 311 | |
| 312 | enum { |
Jack Morgenstein | be6a6b4 | 2015-01-27 15:57:59 +0200 | [diff] [blame] | 313 | MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1, |
| 314 | MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2, |
| 315 | }; |
| 316 | |
| 317 | enum { |
Jack Morgenstein | 5984be9 | 2012-03-06 15:50:49 +0200 | [diff] [blame] | 318 | MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, |
| 319 | }; |
| 320 | |
Jack Morgenstein | 993c401 | 2012-08-03 08:40:48 +0000 | [diff] [blame] | 321 | enum slave_port_state { |
| 322 | SLAVE_PORT_DOWN = 0, |
| 323 | SLAVE_PENDING_UP, |
| 324 | SLAVE_PORT_UP, |
| 325 | }; |
| 326 | |
| 327 | enum slave_port_gen_event { |
| 328 | SLAVE_PORT_GEN_EVENT_DOWN = 0, |
| 329 | SLAVE_PORT_GEN_EVENT_UP, |
| 330 | SLAVE_PORT_GEN_EVENT_NONE, |
| 331 | }; |
| 332 | |
| 333 | enum slave_port_state_event { |
| 334 | MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, |
| 335 | MLX4_PORT_STATE_DEV_EVENT_PORT_UP, |
| 336 | MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, |
| 337 | MLX4_PORT_STATE_IB_EVENT_GID_INVALID, |
| 338 | }; |
| 339 | |
Jack Morgenstein | 5984be9 | 2012-03-06 15:50:49 +0200 | [diff] [blame] | 340 | enum { |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 341 | MLX4_PERM_LOCAL_READ = 1 << 10, |
| 342 | MLX4_PERM_LOCAL_WRITE = 1 << 11, |
| 343 | MLX4_PERM_REMOTE_READ = 1 << 12, |
| 344 | MLX4_PERM_REMOTE_WRITE = 1 << 13, |
Shani Michaeli | 804d6a8 | 2013-02-06 16:19:14 +0000 | [diff] [blame] | 345 | MLX4_PERM_ATOMIC = 1 << 14, |
| 346 | MLX4_PERM_BIND_MW = 1 << 15, |
Matan Barak | e630664 | 2014-07-31 11:01:29 +0300 | [diff] [blame] | 347 | MLX4_PERM_MASK = 0xFC00 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 348 | }; |
| 349 | |
| 350 | enum { |
| 351 | MLX4_OPCODE_NOP = 0x00, |
| 352 | MLX4_OPCODE_SEND_INVAL = 0x01, |
| 353 | MLX4_OPCODE_RDMA_WRITE = 0x08, |
| 354 | MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, |
| 355 | MLX4_OPCODE_SEND = 0x0a, |
| 356 | MLX4_OPCODE_SEND_IMM = 0x0b, |
| 357 | MLX4_OPCODE_LSO = 0x0e, |
| 358 | MLX4_OPCODE_RDMA_READ = 0x10, |
| 359 | MLX4_OPCODE_ATOMIC_CS = 0x11, |
| 360 | MLX4_OPCODE_ATOMIC_FA = 0x12, |
Vladimir Sokolovsky | 6fa8f71 | 2010-04-14 17:23:39 +0300 | [diff] [blame] | 361 | MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, |
| 362 | MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 363 | MLX4_OPCODE_BIND_MW = 0x18, |
| 364 | MLX4_OPCODE_FMR = 0x19, |
| 365 | MLX4_OPCODE_LOCAL_INVAL = 0x1b, |
| 366 | MLX4_OPCODE_CONFIG_CMD = 0x1f, |
| 367 | |
| 368 | MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, |
| 369 | MLX4_RECV_OPCODE_SEND = 0x01, |
| 370 | MLX4_RECV_OPCODE_SEND_IMM = 0x02, |
| 371 | MLX4_RECV_OPCODE_SEND_INVAL = 0x03, |
| 372 | |
| 373 | MLX4_CQE_OPCODE_ERROR = 0x1e, |
| 374 | MLX4_CQE_OPCODE_RESIZE = 0x16, |
| 375 | }; |
| 376 | |
| 377 | enum { |
| 378 | MLX4_STAT_RATE_OFFSET = 5 |
| 379 | }; |
| 380 | |
Aleksey Senin | da995a8 | 2010-12-02 11:44:49 +0000 | [diff] [blame] | 381 | enum mlx4_protocol { |
Yevgeny Petrilin | 0345584 | 2011-03-22 22:38:17 +0000 | [diff] [blame] | 382 | MLX4_PROT_IB_IPV6 = 0, |
| 383 | MLX4_PROT_ETH, |
| 384 | MLX4_PROT_IB_IPV4, |
| 385 | MLX4_PROT_FCOE |
Aleksey Senin | da995a8 | 2010-12-02 11:44:49 +0000 | [diff] [blame] | 386 | }; |
| 387 | |
Vladimir Sokolovsky | 29bdc88 | 2008-09-15 14:25:23 -0700 | [diff] [blame] | 388 | enum { |
| 389 | MLX4_MTT_FLAG_PRESENT = 1 |
| 390 | }; |
| 391 | |
Yevgeny Petrilin | 93fc9e1 | 2008-10-22 10:25:29 -0700 | [diff] [blame] | 392 | enum mlx4_qp_region { |
| 393 | MLX4_QP_REGION_FW = 0, |
Matan Barak | d57febe | 2014-12-11 10:57:57 +0200 | [diff] [blame] | 394 | MLX4_QP_REGION_RSS_RAW_ETH, |
| 395 | MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH, |
Yevgeny Petrilin | 93fc9e1 | 2008-10-22 10:25:29 -0700 | [diff] [blame] | 396 | MLX4_QP_REGION_ETH_ADDR, |
| 397 | MLX4_QP_REGION_FC_ADDR, |
| 398 | MLX4_QP_REGION_FC_EXCH, |
| 399 | MLX4_NUM_QP_REGION |
| 400 | }; |
| 401 | |
Yevgeny Petrilin | 7ff93f8 | 2008-10-22 15:38:42 -0700 | [diff] [blame] | 402 | enum mlx4_port_type { |
Jack Morgenstein | 623ed84 | 2011-12-13 04:10:33 +0000 | [diff] [blame] | 403 | MLX4_PORT_TYPE_NONE = 0, |
Yevgeny Petrilin | 27bf91d | 2009-03-18 19:45:11 -0700 | [diff] [blame] | 404 | MLX4_PORT_TYPE_IB = 1, |
| 405 | MLX4_PORT_TYPE_ETH = 2, |
| 406 | MLX4_PORT_TYPE_AUTO = 3 |
Yevgeny Petrilin | 7ff93f8 | 2008-10-22 15:38:42 -0700 | [diff] [blame] | 407 | }; |
| 408 | |
Yevgeny Petrilin | 2a2336f | 2008-10-22 11:44:46 -0700 | [diff] [blame] | 409 | enum mlx4_special_vlan_idx { |
| 410 | MLX4_NO_VLAN_IDX = 0, |
| 411 | MLX4_VLAN_MISS_IDX, |
| 412 | MLX4_VLAN_REGULAR |
| 413 | }; |
| 414 | |
Yevgeny Petrilin | 0345584 | 2011-03-22 22:38:17 +0000 | [diff] [blame] | 415 | enum mlx4_steer_type { |
| 416 | MLX4_MC_STEER = 0, |
| 417 | MLX4_UC_STEER, |
| 418 | MLX4_NUM_STEERS |
| 419 | }; |
| 420 | |
Yevgeny Petrilin | 93fc9e1 | 2008-10-22 10:25:29 -0700 | [diff] [blame] | 421 | enum { |
| 422 | MLX4_NUM_FEXCH = 64 * 1024, |
| 423 | }; |
| 424 | |
Eli Cohen | 5a0fd09 | 2010-10-07 16:24:16 +0200 | [diff] [blame] | 425 | enum { |
| 426 | MLX4_MAX_FAST_REG_PAGES = 511, |
| 427 | }; |
| 428 | |
Jack Morgenstein | 00f5ce9 | 2012-06-19 11:21:40 +0300 | [diff] [blame] | 429 | enum { |
Sagi Grimberg | a5e14ba | 2015-10-28 13:28:15 +0200 | [diff] [blame] | 430 | /* |
| 431 | * Max wqe size for rdma read is 512 bytes, so this |
| 432 | * limits our max_sge_rd as the wqe needs to fit: |
| 433 | * - ctrl segment (16 bytes) |
| 434 | * - rdma segment (16 bytes) |
| 435 | * - scatter elements (16 bytes each) |
| 436 | */ |
| 437 | MLX4_MAX_SGE_RD = (512 - 16 - 16) / 16 |
| 438 | }; |
| 439 | |
| 440 | enum { |
Jack Morgenstein | 00f5ce9 | 2012-06-19 11:21:40 +0300 | [diff] [blame] | 441 | MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, |
| 442 | MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, |
| 443 | MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, |
| 444 | }; |
| 445 | |
| 446 | /* Port mgmt change event handling */ |
| 447 | enum { |
| 448 | MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, |
| 449 | MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, |
| 450 | MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, |
| 451 | MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, |
| 452 | MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, |
| 453 | }; |
| 454 | |
Yishai Hadas | f6bc11e | 2015-01-25 16:59:38 +0200 | [diff] [blame] | 455 | enum { |
| 456 | MLX4_DEVICE_STATE_UP = 1 << 0, |
| 457 | MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1, |
| 458 | }; |
| 459 | |
Yishai Hadas | c69453e | 2015-01-25 16:59:40 +0200 | [diff] [blame] | 460 | enum { |
| 461 | MLX4_INTERFACE_STATE_UP = 1 << 0, |
| 462 | MLX4_INTERFACE_STATE_DELETION = 1 << 1, |
| 463 | }; |
| 464 | |
Jack Morgenstein | 00f5ce9 | 2012-06-19 11:21:40 +0300 | [diff] [blame] | 465 | #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ |
| 466 | MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) |
| 467 | |
Saeed Mahameed | 32a173c | 2014-10-27 11:37:35 +0200 | [diff] [blame] | 468 | enum mlx4_module_id { |
| 469 | MLX4_MODULE_ID_SFP = 0x3, |
| 470 | MLX4_MODULE_ID_QSFP = 0xC, |
| 471 | MLX4_MODULE_ID_QSFP_PLUS = 0xD, |
| 472 | MLX4_MODULE_ID_QSFP28 = 0x11, |
| 473 | }; |
| 474 | |
Or Gerlitz | fc31e25 | 2015-03-18 14:57:34 +0200 | [diff] [blame] | 475 | enum { /* rl */ |
| 476 | MLX4_QP_RATE_LIMIT_NONE = 0, |
| 477 | MLX4_QP_RATE_LIMIT_KBS = 1, |
| 478 | MLX4_QP_RATE_LIMIT_MBS = 2, |
| 479 | MLX4_QP_RATE_LIMIT_GBS = 3 |
| 480 | }; |
| 481 | |
| 482 | struct mlx4_rate_limit_caps { |
| 483 | u16 num_rates; /* Number of different rates */ |
| 484 | u8 min_unit; |
| 485 | u16 min_val; |
| 486 | u8 max_unit; |
| 487 | u16 max_val; |
| 488 | }; |
| 489 | |
Jack Morgenstein | ea54b10 | 2008-01-28 10:40:59 +0200 | [diff] [blame] | 490 | static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) |
| 491 | { |
| 492 | return (major << 32) | (minor << 16) | subminor; |
| 493 | } |
| 494 | |
Marcel Apfelbaum | 3fc929e | 2012-05-30 09:14:51 +0000 | [diff] [blame] | 495 | struct mlx4_phys_caps { |
Jack Morgenstein | 6634961 | 2012-06-19 11:21:44 +0300 | [diff] [blame] | 496 | u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; |
| 497 | u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; |
Marcel Apfelbaum | 3fc929e | 2012-05-30 09:14:51 +0000 | [diff] [blame] | 498 | u32 num_phys_eqs; |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 499 | u32 base_sqpn; |
| 500 | u32 base_proxy_sqpn; |
| 501 | u32 base_tunnel_sqpn; |
Marcel Apfelbaum | 3fc929e | 2012-05-30 09:14:51 +0000 | [diff] [blame] | 502 | }; |
| 503 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 504 | struct mlx4_caps { |
| 505 | u64 fw_ver; |
Jack Morgenstein | 623ed84 | 2011-12-13 04:10:33 +0000 | [diff] [blame] | 506 | u32 function; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 507 | int num_ports; |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 508 | int vl_cap[MLX4_MAX_PORTS + 1]; |
Yevgeny Petrilin | b79acb4 | 2008-10-22 10:56:48 -0700 | [diff] [blame] | 509 | int ib_mtu_cap[MLX4_MAX_PORTS + 1]; |
Jack Morgenstein | 9a5aa62 | 2008-11-28 21:29:46 -0800 | [diff] [blame] | 510 | __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; |
Yevgeny Petrilin | b79acb4 | 2008-10-22 10:56:48 -0700 | [diff] [blame] | 511 | u64 def_mac[MLX4_MAX_PORTS + 1]; |
| 512 | int eth_mtu_cap[MLX4_MAX_PORTS + 1]; |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 513 | int gid_table_len[MLX4_MAX_PORTS + 1]; |
| 514 | int pkey_table_len[MLX4_MAX_PORTS + 1]; |
Yevgeny Petrilin | 7699517 | 2010-08-24 03:46:23 +0000 | [diff] [blame] | 515 | int trans_type[MLX4_MAX_PORTS + 1]; |
| 516 | int vendor_oui[MLX4_MAX_PORTS + 1]; |
| 517 | int wavelength[MLX4_MAX_PORTS + 1]; |
| 518 | u64 trans_code[MLX4_MAX_PORTS + 1]; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 519 | int local_ca_ack_delay; |
| 520 | int num_uars; |
Jack Morgenstein | f5311ac | 2011-12-13 04:12:13 +0000 | [diff] [blame] | 521 | u32 uar_page_size; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 522 | int bf_reg_size; |
| 523 | int bf_regs_per_page; |
| 524 | int max_sq_sg; |
| 525 | int max_rq_sg; |
| 526 | int num_qps; |
| 527 | int max_wqes; |
| 528 | int max_sq_desc_sz; |
| 529 | int max_rq_desc_sz; |
| 530 | int max_qp_init_rdma; |
| 531 | int max_qp_dest_rdma; |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 532 | u32 *qp0_qkey; |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 533 | u32 *qp0_proxy; |
| 534 | u32 *qp1_proxy; |
| 535 | u32 *qp0_tunnel; |
| 536 | u32 *qp1_tunnel; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 537 | int num_srqs; |
| 538 | int max_srq_wqes; |
| 539 | int max_srq_sge; |
| 540 | int reserved_srqs; |
| 541 | int num_cqs; |
| 542 | int max_cqes; |
| 543 | int reserved_cqs; |
Matan Barak | 7ae0e40 | 2014-11-13 14:45:32 +0200 | [diff] [blame] | 544 | int num_sys_eqs; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 545 | int num_eqs; |
| 546 | int reserved_eqs; |
Yevgeny Petrilin | b8dd786 | 2008-12-22 07:15:03 -0800 | [diff] [blame] | 547 | int num_comp_vectors; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 548 | int num_mpts; |
Eli Cohen | a5bbe89 | 2012-02-09 18:10:06 +0200 | [diff] [blame] | 549 | int max_fmr_maps; |
Marcel Apfelbaum | 2b8fb28 | 2011-12-13 04:16:56 +0000 | [diff] [blame] | 550 | int num_mtts; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 551 | int fmr_reserved_mtts; |
| 552 | int reserved_mtts; |
| 553 | int reserved_mrws; |
| 554 | int reserved_uars; |
| 555 | int num_mgms; |
| 556 | int num_amgms; |
| 557 | int reserved_mcgs; |
| 558 | int num_qp_per_mgm; |
Hadar Hen Zion | c96d97f | 2012-07-05 04:03:44 +0000 | [diff] [blame] | 559 | int steering_mode; |
Matan Barak | 7d077cd | 2014-12-11 10:58:00 +0200 | [diff] [blame] | 560 | int dmfs_high_steer_mode; |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 561 | int fs_log_max_ucast_qp_range_size; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 562 | int num_pds; |
| 563 | int reserved_pds; |
Sean Hefty | 012a8ff | 2011-06-02 09:01:33 -0700 | [diff] [blame] | 564 | int max_xrcds; |
| 565 | int reserved_xrcds; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 566 | int mtt_entry_sz; |
Dotan Barak | 149983af | 2007-06-26 15:55:28 +0300 | [diff] [blame] | 567 | u32 max_msg_sz; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 568 | u32 page_size_cap; |
Or Gerlitz | 52eafc6 | 2011-06-15 14:41:42 +0000 | [diff] [blame] | 569 | u64 flags; |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 570 | u64 flags2; |
Roland Dreier | 95d04f0 | 2008-07-23 08:12:26 -0700 | [diff] [blame] | 571 | u32 bmme_flags; |
| 572 | u32 reserved_lkey; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 573 | u16 stat_rate_support; |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 574 | u8 port_width_cap[MLX4_MAX_PORTS + 1]; |
Eli Cohen | b832be1 | 2008-04-16 21:09:27 -0700 | [diff] [blame] | 575 | int max_gso_sz; |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 576 | int max_rss_tbl_sz; |
Yevgeny Petrilin | 93fc9e1 | 2008-10-22 10:25:29 -0700 | [diff] [blame] | 577 | int reserved_qps_cnt[MLX4_NUM_QP_REGION]; |
| 578 | int reserved_qps; |
| 579 | int reserved_qps_base[MLX4_NUM_QP_REGION]; |
| 580 | int log_num_macs; |
| 581 | int log_num_vlans; |
Yevgeny Petrilin | 7ff93f8 | 2008-10-22 15:38:42 -0700 | [diff] [blame] | 582 | enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; |
| 583 | u8 supported_type[MLX4_MAX_PORTS + 1]; |
Yevgeny Petrilin | 8d0fc7b | 2011-12-19 04:00:34 +0000 | [diff] [blame] | 584 | u8 suggested_type[MLX4_MAX_PORTS + 1]; |
| 585 | u8 default_sense[MLX4_MAX_PORTS + 1]; |
Jack Morgenstein | 65dab25 | 2011-12-13 04:10:41 +0000 | [diff] [blame] | 586 | u32 port_mask[MLX4_MAX_PORTS + 1]; |
Yevgeny Petrilin | 27bf91d | 2009-03-18 19:45:11 -0700 | [diff] [blame] | 587 | enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; |
Or Gerlitz | f2a3f6a | 2011-06-15 14:47:14 +0000 | [diff] [blame] | 588 | u32 max_counters; |
Or Gerlitz | 096335b | 2012-01-11 19:02:17 +0200 | [diff] [blame] | 589 | u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; |
Jack Morgenstein | 1ffeb2e | 2012-08-03 08:40:40 +0000 | [diff] [blame] | 590 | u16 sqp_demux; |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 591 | u32 eqe_size; |
| 592 | u32 cqe_size; |
| 593 | u8 eqe_factor; |
| 594 | u32 userspace_caps; /* userspace must be aware of these */ |
| 595 | u32 function_caps; /* VFs must be aware of these */ |
Eugenia Emantayev | ddd8a6c | 2013-04-23 06:06:48 +0000 | [diff] [blame] | 596 | u16 hca_core_clock; |
Hadar Hen Zion | 8e1a28e | 2013-12-19 21:20:12 +0200 | [diff] [blame] | 597 | u64 phys_port_id[MLX4_MAX_PORTS + 1]; |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 598 | int tunnel_offload_mode; |
Shani Michaeli | f8c6455 | 2014-11-09 13:51:53 +0200 | [diff] [blame] | 599 | u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1]; |
Hadar Hen Zion | 77fc29c | 2015-07-27 14:46:31 +0300 | [diff] [blame] | 600 | u8 phv_bit[MLX4_MAX_PORTS + 1]; |
Eugenia Emantayev | ddae034 | 2014-12-11 10:57:54 +0200 | [diff] [blame] | 601 | u8 alloc_res_qp_mask; |
Matan Barak | 7d077cd | 2014-12-11 10:58:00 +0200 | [diff] [blame] | 602 | u32 dmfs_high_rate_qpn_base; |
| 603 | u32 dmfs_high_rate_qpn_range; |
Yishai Hadas | 55ad359 | 2015-01-25 16:59:42 +0200 | [diff] [blame] | 604 | u32 vf_caps; |
Or Gerlitz | fc31e25 | 2015-03-18 14:57:34 +0200 | [diff] [blame] | 605 | struct mlx4_rate_limit_caps rl_caps; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 606 | }; |
| 607 | |
| 608 | struct mlx4_buf_list { |
| 609 | void *buf; |
| 610 | dma_addr_t map; |
| 611 | }; |
| 612 | |
| 613 | struct mlx4_buf { |
Roland Dreier | b57aacf | 2008-02-06 21:17:59 -0800 | [diff] [blame] | 614 | struct mlx4_buf_list direct; |
| 615 | struct mlx4_buf_list *page_list; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 616 | int nbufs; |
| 617 | int npages; |
| 618 | int page_shift; |
| 619 | }; |
| 620 | |
| 621 | struct mlx4_mtt { |
Marcel Apfelbaum | 2b8fb28 | 2011-12-13 04:16:56 +0000 | [diff] [blame] | 622 | u32 offset; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 623 | int order; |
| 624 | int page_shift; |
| 625 | }; |
| 626 | |
Yevgeny Petrilin | 6296883 | 2008-04-23 11:55:45 -0700 | [diff] [blame] | 627 | enum { |
| 628 | MLX4_DB_PER_PAGE = PAGE_SIZE / 4 |
| 629 | }; |
| 630 | |
| 631 | struct mlx4_db_pgdir { |
| 632 | struct list_head list; |
| 633 | DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); |
| 634 | DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); |
| 635 | unsigned long *bits[2]; |
| 636 | __be32 *db_page; |
| 637 | dma_addr_t db_dma; |
| 638 | }; |
| 639 | |
| 640 | struct mlx4_ib_user_db_page; |
| 641 | |
| 642 | struct mlx4_db { |
| 643 | __be32 *db; |
| 644 | union { |
| 645 | struct mlx4_db_pgdir *pgdir; |
| 646 | struct mlx4_ib_user_db_page *user_page; |
| 647 | } u; |
| 648 | dma_addr_t dma; |
| 649 | int index; |
| 650 | int order; |
| 651 | }; |
| 652 | |
Yevgeny Petrilin | 38ae6a5 | 2008-04-25 14:27:08 -0700 | [diff] [blame] | 653 | struct mlx4_hwq_resources { |
| 654 | struct mlx4_db db; |
| 655 | struct mlx4_mtt mtt; |
| 656 | struct mlx4_buf buf; |
| 657 | }; |
| 658 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 659 | struct mlx4_mr { |
| 660 | struct mlx4_mtt mtt; |
| 661 | u64 iova; |
| 662 | u64 size; |
| 663 | u32 key; |
| 664 | u32 pd; |
| 665 | u32 access; |
| 666 | int enabled; |
| 667 | }; |
| 668 | |
Shani Michaeli | 804d6a8 | 2013-02-06 16:19:14 +0000 | [diff] [blame] | 669 | enum mlx4_mw_type { |
| 670 | MLX4_MW_TYPE_1 = 1, |
| 671 | MLX4_MW_TYPE_2 = 2, |
| 672 | }; |
| 673 | |
| 674 | struct mlx4_mw { |
| 675 | u32 key; |
| 676 | u32 pd; |
| 677 | enum mlx4_mw_type type; |
| 678 | int enabled; |
| 679 | }; |
| 680 | |
Jack Morgenstein | 8ad11fb | 2007-08-01 12:29:05 +0300 | [diff] [blame] | 681 | struct mlx4_fmr { |
| 682 | struct mlx4_mr mr; |
| 683 | struct mlx4_mpt_entry *mpt; |
| 684 | __be64 *mtts; |
| 685 | dma_addr_t dma_handle; |
| 686 | int max_pages; |
| 687 | int max_maps; |
| 688 | int maps; |
| 689 | u8 page_shift; |
| 690 | }; |
| 691 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 692 | struct mlx4_uar { |
| 693 | unsigned long pfn; |
| 694 | int index; |
Eli Cohen | c1b43dc | 2011-03-22 22:38:41 +0000 | [diff] [blame] | 695 | struct list_head bf_list; |
| 696 | unsigned free_bf_bmap; |
| 697 | void __iomem *map; |
| 698 | void __iomem *bf_map; |
| 699 | }; |
| 700 | |
| 701 | struct mlx4_bf { |
Eric Dumazet | 7dfa4b4 | 2014-10-05 12:35:09 +0300 | [diff] [blame] | 702 | unsigned int offset; |
Eli Cohen | c1b43dc | 2011-03-22 22:38:41 +0000 | [diff] [blame] | 703 | int buf_size; |
| 704 | struct mlx4_uar *uar; |
| 705 | void __iomem *reg; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 706 | }; |
| 707 | |
| 708 | struct mlx4_cq { |
| 709 | void (*comp) (struct mlx4_cq *); |
| 710 | void (*event) (struct mlx4_cq *, enum mlx4_event); |
| 711 | |
| 712 | struct mlx4_uar *uar; |
| 713 | |
| 714 | u32 cons_index; |
| 715 | |
Yuval Atias | 2eacc23 | 2014-05-14 12:15:10 +0300 | [diff] [blame] | 716 | u16 irq; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 717 | __be32 *set_ci_db; |
| 718 | __be32 *arm_db; |
| 719 | int arm_sn; |
| 720 | |
| 721 | int cqn; |
Yevgeny Petrilin | b8dd786 | 2008-12-22 07:15:03 -0800 | [diff] [blame] | 722 | unsigned vector; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 723 | |
| 724 | atomic_t refcount; |
| 725 | struct completion free; |
Matan Barak | 3dca0f42 | 2014-12-11 10:57:53 +0200 | [diff] [blame] | 726 | struct { |
| 727 | struct list_head list; |
| 728 | void (*comp)(struct mlx4_cq *); |
| 729 | void *priv; |
| 730 | } tasklet_ctx; |
Yishai Hadas | 35f05da | 2015-02-08 11:49:34 +0200 | [diff] [blame] | 731 | int reset_notify_added; |
| 732 | struct list_head reset_notify; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 733 | }; |
| 734 | |
| 735 | struct mlx4_qp { |
| 736 | void (*event) (struct mlx4_qp *, enum mlx4_event); |
| 737 | |
| 738 | int qpn; |
| 739 | |
| 740 | atomic_t refcount; |
| 741 | struct completion free; |
| 742 | }; |
| 743 | |
| 744 | struct mlx4_srq { |
| 745 | void (*event) (struct mlx4_srq *, enum mlx4_event); |
| 746 | |
| 747 | int srqn; |
| 748 | int max; |
| 749 | int max_gs; |
| 750 | int wqe_shift; |
| 751 | |
| 752 | atomic_t refcount; |
| 753 | struct completion free; |
| 754 | }; |
| 755 | |
| 756 | struct mlx4_av { |
| 757 | __be32 port_pd; |
| 758 | u8 reserved1; |
| 759 | u8 g_slid; |
| 760 | __be16 dlid; |
| 761 | u8 reserved2; |
| 762 | u8 gid_index; |
| 763 | u8 stat_rate; |
| 764 | u8 hop_limit; |
| 765 | __be32 sl_tclass_flowlabel; |
| 766 | u8 dgid[16]; |
| 767 | }; |
| 768 | |
Eli Cohen | fa417f7 | 2010-10-24 21:08:52 -0700 | [diff] [blame] | 769 | struct mlx4_eth_av { |
| 770 | __be32 port_pd; |
| 771 | u8 reserved1; |
| 772 | u8 smac_idx; |
| 773 | u16 reserved2; |
| 774 | u8 reserved3; |
| 775 | u8 gid_index; |
| 776 | u8 stat_rate; |
| 777 | u8 hop_limit; |
| 778 | __be32 sl_tclass_flowlabel; |
| 779 | u8 dgid[16]; |
Jack Morgenstein | 5ea8bbf | 2014-03-12 12:00:41 +0200 | [diff] [blame] | 780 | u8 s_mac[6]; |
| 781 | u8 reserved4[2]; |
Eli Cohen | fa417f7 | 2010-10-24 21:08:52 -0700 | [diff] [blame] | 782 | __be16 vlan; |
Joe Perches | 574e2af | 2013-08-01 16:17:48 -0700 | [diff] [blame] | 783 | u8 mac[ETH_ALEN]; |
Eli Cohen | fa417f7 | 2010-10-24 21:08:52 -0700 | [diff] [blame] | 784 | }; |
| 785 | |
| 786 | union mlx4_ext_av { |
| 787 | struct mlx4_av ib; |
| 788 | struct mlx4_eth_av eth; |
| 789 | }; |
| 790 | |
Eran Ben Elisha | 9616982 | 2015-06-15 17:59:05 +0300 | [diff] [blame] | 791 | /* Counters should be saturate once they reach their maximum value */ |
| 792 | #define ASSIGN_32BIT_COUNTER(counter, value) do { \ |
| 793 | if ((value) > U32_MAX) \ |
| 794 | counter = cpu_to_be32(U32_MAX); \ |
| 795 | else \ |
| 796 | counter = cpu_to_be32(value); \ |
| 797 | } while (0) |
| 798 | |
Or Gerlitz | f2a3f6a | 2011-06-15 14:47:14 +0000 | [diff] [blame] | 799 | struct mlx4_counter { |
| 800 | u8 reserved1[3]; |
| 801 | u8 counter_mode; |
| 802 | __be32 num_ifc; |
| 803 | u32 reserved2[2]; |
| 804 | __be64 rx_frames; |
| 805 | __be64 rx_bytes; |
| 806 | __be64 tx_frames; |
| 807 | __be64 tx_bytes; |
| 808 | }; |
| 809 | |
Jack Morgenstein | 5a0d0a6 | 2013-11-03 10:03:23 +0200 | [diff] [blame] | 810 | struct mlx4_quotas { |
| 811 | int qp; |
| 812 | int cq; |
| 813 | int srq; |
| 814 | int mpt; |
| 815 | int mtt; |
| 816 | int counter; |
| 817 | int xrcd; |
| 818 | }; |
| 819 | |
Matan Barak | 1ab95d3 | 2014-03-19 18:11:50 +0200 | [diff] [blame] | 820 | struct mlx4_vf_dev { |
| 821 | u8 min_port; |
| 822 | u8 n_ports; |
| 823 | }; |
| 824 | |
Yishai Hadas | 872bf2f | 2015-01-25 16:59:35 +0200 | [diff] [blame] | 825 | struct mlx4_dev_persistent { |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 826 | struct pci_dev *pdev; |
Yishai Hadas | 872bf2f | 2015-01-25 16:59:35 +0200 | [diff] [blame] | 827 | struct mlx4_dev *dev; |
| 828 | int nvfs[MLX4_MAX_PORTS + 1]; |
| 829 | int num_vfs; |
Yishai Hadas | dd0eefe | 2015-01-25 16:59:36 +0200 | [diff] [blame] | 830 | enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1]; |
| 831 | enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1]; |
Yishai Hadas | ad9a0bf | 2015-01-25 16:59:37 +0200 | [diff] [blame] | 832 | struct work_struct catas_work; |
| 833 | struct workqueue_struct *catas_wq; |
Yishai Hadas | f6bc11e | 2015-01-25 16:59:38 +0200 | [diff] [blame] | 834 | struct mutex device_state_mutex; /* protect HW state */ |
| 835 | u8 state; |
Yishai Hadas | c69453e | 2015-01-25 16:59:40 +0200 | [diff] [blame] | 836 | struct mutex interface_state_mutex; /* protect SW state */ |
| 837 | u8 interface_state; |
Yishai Hadas | 872bf2f | 2015-01-25 16:59:35 +0200 | [diff] [blame] | 838 | }; |
| 839 | |
| 840 | struct mlx4_dev { |
| 841 | struct mlx4_dev_persistent *persist; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 842 | unsigned long flags; |
Jack Morgenstein | 623ed84 | 2011-12-13 04:10:33 +0000 | [diff] [blame] | 843 | unsigned long num_slaves; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 844 | struct mlx4_caps caps; |
Marcel Apfelbaum | 3fc929e | 2012-05-30 09:14:51 +0000 | [diff] [blame] | 845 | struct mlx4_phys_caps phys_caps; |
Jack Morgenstein | 5a0d0a6 | 2013-11-03 10:03:23 +0200 | [diff] [blame] | 846 | struct mlx4_quotas quotas; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 847 | struct radix_tree_root qp_table_tree; |
Yevgeny Petrilin | 725c899 | 2011-03-22 22:38:07 +0000 | [diff] [blame] | 848 | u8 rev_id; |
Jack Morgenstein | 2b3ddf2 | 2015-10-14 17:43:48 +0300 | [diff] [blame] | 849 | u8 port_random_macs; |
Jack Morgenstein | cd9281d | 2007-09-18 09:14:18 +0200 | [diff] [blame] | 850 | char board_id[MLX4_BOARD_ID_LEN]; |
Eugenia Emantayev | 6e7136e | 2013-11-07 12:19:53 +0200 | [diff] [blame] | 851 | int numa_node; |
Jack Morgenstein | 3c439b5 | 2012-12-06 17:12:00 +0000 | [diff] [blame] | 852 | int oper_log_mgm_entry_size; |
Hadar Hen Zion | 592e49d | 2012-07-05 04:03:48 +0000 | [diff] [blame] | 853 | u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; |
| 854 | u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; |
Matan Barak | 1ab95d3 | 2014-03-19 18:11:50 +0200 | [diff] [blame] | 855 | struct mlx4_vf_dev *dev_vfs; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 856 | }; |
| 857 | |
Matan Barak | 52033cf | 2015-06-11 16:35:26 +0300 | [diff] [blame] | 858 | struct mlx4_clock_params { |
| 859 | u64 offset; |
| 860 | u8 bar; |
| 861 | u8 size; |
| 862 | }; |
| 863 | |
Jack Morgenstein | 00f5ce9 | 2012-06-19 11:21:40 +0300 | [diff] [blame] | 864 | struct mlx4_eqe { |
| 865 | u8 reserved1; |
| 866 | u8 type; |
| 867 | u8 reserved2; |
| 868 | u8 subtype; |
| 869 | union { |
| 870 | u32 raw[6]; |
| 871 | struct { |
| 872 | __be32 cqn; |
| 873 | } __packed comp; |
| 874 | struct { |
| 875 | u16 reserved1; |
| 876 | __be16 token; |
| 877 | u32 reserved2; |
| 878 | u8 reserved3[3]; |
| 879 | u8 status; |
| 880 | __be64 out_param; |
| 881 | } __packed cmd; |
| 882 | struct { |
| 883 | __be32 qpn; |
| 884 | } __packed qp; |
| 885 | struct { |
| 886 | __be32 srqn; |
| 887 | } __packed srq; |
| 888 | struct { |
| 889 | __be32 cqn; |
| 890 | u32 reserved1; |
| 891 | u8 reserved2[3]; |
| 892 | u8 syndrome; |
| 893 | } __packed cq_err; |
| 894 | struct { |
| 895 | u32 reserved1[2]; |
| 896 | __be32 port; |
| 897 | } __packed port_change; |
| 898 | struct { |
| 899 | #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 |
| 900 | u32 reserved; |
| 901 | u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; |
| 902 | } __packed comm_channel_arm; |
| 903 | struct { |
| 904 | u8 port; |
| 905 | u8 reserved[3]; |
| 906 | __be64 mac; |
| 907 | } __packed mac_update; |
| 908 | struct { |
| 909 | __be32 slave_id; |
| 910 | } __packed flr_event; |
| 911 | struct { |
| 912 | __be16 current_temperature; |
| 913 | __be16 warning_threshold; |
| 914 | } __packed warming; |
| 915 | struct { |
| 916 | u8 reserved[3]; |
| 917 | u8 port; |
| 918 | union { |
| 919 | struct { |
| 920 | __be16 mstr_sm_lid; |
| 921 | __be16 port_lid; |
| 922 | __be32 changed_attr; |
| 923 | u8 reserved[3]; |
| 924 | u8 mstr_sm_sl; |
| 925 | __be64 gid_prefix; |
| 926 | } __packed port_info; |
| 927 | struct { |
| 928 | __be32 block_ptr; |
| 929 | __be32 tbl_entries_mask; |
| 930 | } __packed tbl_change_info; |
| 931 | } params; |
| 932 | } __packed port_mgmt_change; |
Jack Morgenstein | be6a6b4 | 2015-01-27 15:57:59 +0200 | [diff] [blame] | 933 | struct { |
| 934 | u8 reserved[3]; |
| 935 | u8 port; |
| 936 | u32 reserved1[5]; |
| 937 | } __packed bad_cable; |
Jack Morgenstein | 00f5ce9 | 2012-06-19 11:21:40 +0300 | [diff] [blame] | 938 | } event; |
| 939 | u8 slave_id; |
| 940 | u8 reserved3[2]; |
| 941 | u8 owner; |
| 942 | } __packed; |
| 943 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 944 | struct mlx4_init_port_param { |
| 945 | int set_guid0; |
| 946 | int set_node_guid; |
| 947 | int set_si_guid; |
| 948 | u16 mtu; |
| 949 | int port_width_cap; |
| 950 | u16 vl_cap; |
| 951 | u16 max_gid; |
| 952 | u16 max_pkey; |
| 953 | u64 guid0; |
| 954 | u64 node_guid; |
| 955 | u64 si_guid; |
| 956 | }; |
| 957 | |
Saeed Mahameed | 32a173c | 2014-10-27 11:37:35 +0200 | [diff] [blame] | 958 | #define MAD_IFC_DATA_SZ 192 |
| 959 | /* MAD IFC Mailbox */ |
| 960 | struct mlx4_mad_ifc { |
| 961 | u8 base_version; |
| 962 | u8 mgmt_class; |
| 963 | u8 class_version; |
| 964 | u8 method; |
| 965 | __be16 status; |
| 966 | __be16 class_specific; |
| 967 | __be64 tid; |
| 968 | __be16 attr_id; |
| 969 | __be16 resv; |
| 970 | __be32 attr_mod; |
| 971 | __be64 mkey; |
| 972 | __be16 dr_slid; |
| 973 | __be16 dr_dlid; |
| 974 | u8 reserved[28]; |
| 975 | u8 data[MAD_IFC_DATA_SZ]; |
| 976 | } __packed; |
| 977 | |
Yevgeny Petrilin | 7ff93f8 | 2008-10-22 15:38:42 -0700 | [diff] [blame] | 978 | #define mlx4_foreach_port(port, dev, type) \ |
| 979 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ |
Jack Morgenstein | 65dab25 | 2011-12-13 04:10:41 +0000 | [diff] [blame] | 980 | if ((type) == (dev)->caps.port_mask[(port)]) |
Yevgeny Petrilin | 7ff93f8 | 2008-10-22 15:38:42 -0700 | [diff] [blame] | 981 | |
Jack Morgenstein | 026149c | 2012-08-03 08:40:55 +0000 | [diff] [blame] | 982 | #define mlx4_foreach_non_ib_transport_port(port, dev) \ |
| 983 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ |
| 984 | if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB)) |
| 985 | |
Jack Morgenstein | 65dab25 | 2011-12-13 04:10:41 +0000 | [diff] [blame] | 986 | #define mlx4_foreach_ib_transport_port(port, dev) \ |
| 987 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ |
| 988 | if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ |
| 989 | ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) |
Eli Cohen | fa417f7 | 2010-10-24 21:08:52 -0700 | [diff] [blame] | 990 | |
Jack Morgenstein | 752a50c | 2012-06-19 11:21:33 +0300 | [diff] [blame] | 991 | #define MLX4_INVALID_SLAVE_ID 0xFF |
Eran Ben Elisha | 47d8417 | 2015-06-15 17:58:58 +0300 | [diff] [blame] | 992 | #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1) |
Jack Morgenstein | 752a50c | 2012-06-19 11:21:33 +0300 | [diff] [blame] | 993 | |
Jack Morgenstein | 00f5ce9 | 2012-06-19 11:21:40 +0300 | [diff] [blame] | 994 | void handle_port_mgmt_change_event(struct work_struct *work); |
| 995 | |
Jack Morgenstein | 2aca117 | 2012-06-19 11:21:41 +0300 | [diff] [blame] | 996 | static inline int mlx4_master_func_num(struct mlx4_dev *dev) |
| 997 | { |
| 998 | return dev->caps.function; |
| 999 | } |
| 1000 | |
Jack Morgenstein | 623ed84 | 2011-12-13 04:10:33 +0000 | [diff] [blame] | 1001 | static inline int mlx4_is_master(struct mlx4_dev *dev) |
| 1002 | { |
| 1003 | return dev->flags & MLX4_FLAG_MASTER; |
| 1004 | } |
| 1005 | |
Jack Morgenstein | 5a0d0a6 | 2013-11-03 10:03:23 +0200 | [diff] [blame] | 1006 | static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) |
| 1007 | { |
| 1008 | return dev->phys_caps.base_sqpn + 8 + |
| 1009 | 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); |
| 1010 | } |
| 1011 | |
Jack Morgenstein | 623ed84 | 2011-12-13 04:10:33 +0000 | [diff] [blame] | 1012 | static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) |
| 1013 | { |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 1014 | return (qpn < dev->phys_caps.base_sqpn + 8 + |
Matan Barak | d57febe | 2014-12-11 10:57:57 +0200 | [diff] [blame] | 1015 | 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) && |
| 1016 | qpn >= dev->phys_caps.base_sqpn) || |
| 1017 | (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]); |
Jack Morgenstein | e2c7682 | 2012-08-03 08:40:41 +0000 | [diff] [blame] | 1018 | } |
| 1019 | |
| 1020 | static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) |
| 1021 | { |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 1022 | int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; |
Jack Morgenstein | e2c7682 | 2012-08-03 08:40:41 +0000 | [diff] [blame] | 1023 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 1024 | if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) |
Jack Morgenstein | e2c7682 | 2012-08-03 08:40:41 +0000 | [diff] [blame] | 1025 | return 1; |
| 1026 | |
| 1027 | return 0; |
Jack Morgenstein | 623ed84 | 2011-12-13 04:10:33 +0000 | [diff] [blame] | 1028 | } |
| 1029 | |
| 1030 | static inline int mlx4_is_mfunc(struct mlx4_dev *dev) |
| 1031 | { |
| 1032 | return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); |
| 1033 | } |
| 1034 | |
| 1035 | static inline int mlx4_is_slave(struct mlx4_dev *dev) |
| 1036 | { |
| 1037 | return dev->flags & MLX4_FLAG_SLAVE; |
| 1038 | } |
Eli Cohen | fa417f7 | 2010-10-24 21:08:52 -0700 | [diff] [blame] | 1039 | |
Ido Shamay | fccea64 | 2015-04-02 16:31:08 +0300 | [diff] [blame] | 1040 | static inline int mlx4_is_eth(struct mlx4_dev *dev, int port) |
| 1041 | { |
| 1042 | return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1; |
| 1043 | } |
| 1044 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1045 | int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, |
Jiri Kosina | 40f2287 | 2014-05-11 15:15:12 +0300 | [diff] [blame] | 1046 | struct mlx4_buf *buf, gfp_t gfp); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1047 | void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); |
Roland Dreier | 1c69fc2 | 2008-02-06 21:07:54 -0800 | [diff] [blame] | 1048 | static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) |
| 1049 | { |
Jack Morgenstein | 313abe5 | 2008-01-28 10:40:51 +0200 | [diff] [blame] | 1050 | if (BITS_PER_LONG == 64 || buf->nbufs == 1) |
Roland Dreier | b57aacf | 2008-02-06 21:17:59 -0800 | [diff] [blame] | 1051 | return buf->direct.buf + offset; |
Roland Dreier | 1c69fc2 | 2008-02-06 21:07:54 -0800 | [diff] [blame] | 1052 | else |
Roland Dreier | b57aacf | 2008-02-06 21:17:59 -0800 | [diff] [blame] | 1053 | return buf->page_list[offset >> PAGE_SHIFT].buf + |
Roland Dreier | 1c69fc2 | 2008-02-06 21:07:54 -0800 | [diff] [blame] | 1054 | (offset & (PAGE_SIZE - 1)); |
| 1055 | } |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1056 | |
| 1057 | int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); |
| 1058 | void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); |
Sean Hefty | 012a8ff | 2011-06-02 09:01:33 -0700 | [diff] [blame] | 1059 | int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); |
| 1060 | void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1061 | |
| 1062 | int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); |
| 1063 | void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); |
Eugenia Emantayev | 163561a | 2013-11-07 12:19:54 +0200 | [diff] [blame] | 1064 | int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); |
Eli Cohen | c1b43dc | 2011-03-22 22:38:41 +0000 | [diff] [blame] | 1065 | void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1066 | |
| 1067 | int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, |
| 1068 | struct mlx4_mtt *mtt); |
| 1069 | void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); |
| 1070 | u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); |
| 1071 | |
| 1072 | int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, |
| 1073 | int npages, int page_shift, struct mlx4_mr *mr); |
Shani Michaeli | 6108372 | 2013-02-06 16:19:09 +0000 | [diff] [blame] | 1074 | int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1075 | int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); |
Shani Michaeli | 804d6a8 | 2013-02-06 16:19:14 +0000 | [diff] [blame] | 1076 | int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, |
| 1077 | struct mlx4_mw *mw); |
| 1078 | void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); |
| 1079 | int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1080 | int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
| 1081 | int start_index, int npages, u64 *page_list); |
| 1082 | int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
Jiri Kosina | 40f2287 | 2014-05-11 15:15:12 +0300 | [diff] [blame] | 1083 | struct mlx4_buf *buf, gfp_t gfp); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1084 | |
Jiri Kosina | 40f2287 | 2014-05-11 15:15:12 +0300 | [diff] [blame] | 1085 | int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order, |
| 1086 | gfp_t gfp); |
Yevgeny Petrilin | 6296883 | 2008-04-23 11:55:45 -0700 | [diff] [blame] | 1087 | void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); |
| 1088 | |
Yevgeny Petrilin | 38ae6a5 | 2008-04-25 14:27:08 -0700 | [diff] [blame] | 1089 | int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, |
| 1090 | int size, int max_direct); |
| 1091 | void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, |
| 1092 | int size); |
| 1093 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1094 | int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, |
Yevgeny Petrilin | e463c7b | 2008-04-29 13:46:50 -0700 | [diff] [blame] | 1095 | struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, |
Amir Vadai | ec693d4 | 2013-04-23 06:06:49 +0000 | [diff] [blame] | 1096 | unsigned vector, int collapsed, int timestamp_en); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1097 | void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); |
Eugenia Emantayev | ddae034 | 2014-12-11 10:57:54 +0200 | [diff] [blame] | 1098 | int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, |
| 1099 | int *base, u8 flags); |
Yevgeny Petrilin | a3cdcbf | 2008-10-10 12:01:37 -0700 | [diff] [blame] | 1100 | void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); |
| 1101 | |
Jiri Kosina | 40f2287 | 2014-05-11 15:15:12 +0300 | [diff] [blame] | 1102 | int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp, |
| 1103 | gfp_t gfp); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1104 | void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); |
| 1105 | |
Sean Hefty | 18abd5e | 2011-06-02 10:43:26 -0700 | [diff] [blame] | 1106 | int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, |
| 1107 | struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1108 | void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); |
| 1109 | int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); |
Jack Morgenstein | 65541cb | 2007-06-21 13:03:11 +0300 | [diff] [blame] | 1110 | int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1111 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1112 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1113 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); |
| 1114 | |
Eugenia Emantayev | ffe455a | 2011-12-13 04:16:21 +0000 | [diff] [blame] | 1115 | int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
| 1116 | int block_mcast_loopback, enum mlx4_protocol prot); |
| 1117 | int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
| 1118 | enum mlx4_protocol prot); |
Ron Livne | 521e575 | 2008-07-14 23:48:48 -0700 | [diff] [blame] | 1119 | int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1120 | u8 port, int block_mcast_loopback, |
| 1121 | enum mlx4_protocol protocol, u64 *reg_id); |
Aleksey Senin | da995a8 | 2010-12-02 11:44:49 +0000 | [diff] [blame] | 1122 | int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1123 | enum mlx4_protocol protocol, u64 reg_id); |
| 1124 | |
| 1125 | enum { |
| 1126 | MLX4_DOMAIN_UVERBS = 0x1000, |
| 1127 | MLX4_DOMAIN_ETHTOOL = 0x2000, |
| 1128 | MLX4_DOMAIN_RFS = 0x3000, |
| 1129 | MLX4_DOMAIN_NIC = 0x5000, |
| 1130 | }; |
| 1131 | |
| 1132 | enum mlx4_net_trans_rule_id { |
| 1133 | MLX4_NET_TRANS_RULE_ID_ETH = 0, |
| 1134 | MLX4_NET_TRANS_RULE_ID_IB, |
| 1135 | MLX4_NET_TRANS_RULE_ID_IPV6, |
| 1136 | MLX4_NET_TRANS_RULE_ID_IPV4, |
| 1137 | MLX4_NET_TRANS_RULE_ID_TCP, |
| 1138 | MLX4_NET_TRANS_RULE_ID_UDP, |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 1139 | MLX4_NET_TRANS_RULE_ID_VXLAN, |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1140 | MLX4_NET_TRANS_RULE_NUM, /* should be last */ |
| 1141 | }; |
| 1142 | |
Hadar Hen Zion | a8edc3b | 2012-09-05 22:50:48 +0000 | [diff] [blame] | 1143 | extern const u16 __sw_id_hw[]; |
| 1144 | |
Hadar Hen Zion | 7fb40f8 | 2012-09-05 22:50:49 +0000 | [diff] [blame] | 1145 | static inline int map_hw_to_sw_id(u16 header_id) |
| 1146 | { |
| 1147 | |
| 1148 | int i; |
| 1149 | for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { |
| 1150 | if (header_id == __sw_id_hw[i]) |
| 1151 | return i; |
| 1152 | } |
| 1153 | return -EINVAL; |
| 1154 | } |
| 1155 | |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1156 | enum mlx4_net_trans_promisc_mode { |
Hadar Hen Zion | f916253 | 2013-04-24 13:58:45 +0000 | [diff] [blame] | 1157 | MLX4_FS_REGULAR = 1, |
| 1158 | MLX4_FS_ALL_DEFAULT, |
| 1159 | MLX4_FS_MC_DEFAULT, |
| 1160 | MLX4_FS_UC_SNIFFER, |
| 1161 | MLX4_FS_MC_SNIFFER, |
Hadar Hen Zion | c2c19dc | 2013-04-24 13:58:48 +0000 | [diff] [blame] | 1162 | MLX4_FS_MODE_NUM, /* should be last */ |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1163 | }; |
| 1164 | |
| 1165 | struct mlx4_spec_eth { |
Joe Perches | 574e2af | 2013-08-01 16:17:48 -0700 | [diff] [blame] | 1166 | u8 dst_mac[ETH_ALEN]; |
| 1167 | u8 dst_mac_msk[ETH_ALEN]; |
| 1168 | u8 src_mac[ETH_ALEN]; |
| 1169 | u8 src_mac_msk[ETH_ALEN]; |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1170 | u8 ether_type_enable; |
| 1171 | __be16 ether_type; |
| 1172 | __be16 vlan_id_msk; |
| 1173 | __be16 vlan_id; |
| 1174 | }; |
| 1175 | |
| 1176 | struct mlx4_spec_tcp_udp { |
| 1177 | __be16 dst_port; |
| 1178 | __be16 dst_port_msk; |
| 1179 | __be16 src_port; |
| 1180 | __be16 src_port_msk; |
| 1181 | }; |
| 1182 | |
| 1183 | struct mlx4_spec_ipv4 { |
| 1184 | __be32 dst_ip; |
| 1185 | __be32 dst_ip_msk; |
| 1186 | __be32 src_ip; |
| 1187 | __be32 src_ip_msk; |
| 1188 | }; |
| 1189 | |
| 1190 | struct mlx4_spec_ib { |
Hadar Hen Zion | ba60a35 | 2013-04-24 13:58:46 +0000 | [diff] [blame] | 1191 | __be32 l3_qpn; |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1192 | __be32 qpn_msk; |
| 1193 | u8 dst_gid[16]; |
| 1194 | u8 dst_gid_msk[16]; |
| 1195 | }; |
| 1196 | |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 1197 | struct mlx4_spec_vxlan { |
| 1198 | __be32 vni; |
| 1199 | __be32 vni_mask; |
| 1200 | |
| 1201 | }; |
| 1202 | |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1203 | struct mlx4_spec_list { |
| 1204 | struct list_head list; |
| 1205 | enum mlx4_net_trans_rule_id id; |
| 1206 | union { |
| 1207 | struct mlx4_spec_eth eth; |
| 1208 | struct mlx4_spec_ib ib; |
| 1209 | struct mlx4_spec_ipv4 ipv4; |
| 1210 | struct mlx4_spec_tcp_udp tcp_udp; |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 1211 | struct mlx4_spec_vxlan vxlan; |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1212 | }; |
| 1213 | }; |
| 1214 | |
| 1215 | enum mlx4_net_trans_hw_rule_queue { |
| 1216 | MLX4_NET_TRANS_Q_FIFO, |
| 1217 | MLX4_NET_TRANS_Q_LIFO, |
| 1218 | }; |
| 1219 | |
| 1220 | struct mlx4_net_trans_rule { |
| 1221 | struct list_head list; |
| 1222 | enum mlx4_net_trans_hw_rule_queue queue_mode; |
| 1223 | bool exclusive; |
| 1224 | bool allow_loopback; |
| 1225 | enum mlx4_net_trans_promisc_mode promisc_mode; |
| 1226 | u8 port; |
| 1227 | u16 priority; |
| 1228 | u32 qpn; |
| 1229 | }; |
| 1230 | |
Hadar Hen Zion | 3cd0e17 | 2013-04-24 13:58:44 +0000 | [diff] [blame] | 1231 | struct mlx4_net_trans_rule_hw_ctrl { |
Hadar Hen Zion | bcf3729 | 2013-04-24 13:58:47 +0000 | [diff] [blame] | 1232 | __be16 prio; |
| 1233 | u8 type; |
| 1234 | u8 flags; |
Hadar Hen Zion | 3cd0e17 | 2013-04-24 13:58:44 +0000 | [diff] [blame] | 1235 | u8 rsvd1; |
| 1236 | u8 funcid; |
| 1237 | u8 vep; |
| 1238 | u8 port; |
| 1239 | __be32 qpn; |
| 1240 | __be32 rsvd2; |
| 1241 | }; |
| 1242 | |
| 1243 | struct mlx4_net_trans_rule_hw_ib { |
| 1244 | u8 size; |
| 1245 | u8 rsvd1; |
| 1246 | __be16 id; |
| 1247 | u32 rsvd2; |
Hadar Hen Zion | ba60a35 | 2013-04-24 13:58:46 +0000 | [diff] [blame] | 1248 | __be32 l3_qpn; |
Hadar Hen Zion | 3cd0e17 | 2013-04-24 13:58:44 +0000 | [diff] [blame] | 1249 | __be32 qpn_mask; |
| 1250 | u8 dst_gid[16]; |
| 1251 | u8 dst_gid_msk[16]; |
| 1252 | } __packed; |
| 1253 | |
| 1254 | struct mlx4_net_trans_rule_hw_eth { |
| 1255 | u8 size; |
| 1256 | u8 rsvd; |
| 1257 | __be16 id; |
| 1258 | u8 rsvd1[6]; |
| 1259 | u8 dst_mac[6]; |
| 1260 | u16 rsvd2; |
| 1261 | u8 dst_mac_msk[6]; |
| 1262 | u16 rsvd3; |
| 1263 | u8 src_mac[6]; |
| 1264 | u16 rsvd4; |
| 1265 | u8 src_mac_msk[6]; |
| 1266 | u8 rsvd5; |
| 1267 | u8 ether_type_enable; |
| 1268 | __be16 ether_type; |
Hadar Hen Zion | ba60a35 | 2013-04-24 13:58:46 +0000 | [diff] [blame] | 1269 | __be16 vlan_tag_msk; |
| 1270 | __be16 vlan_tag; |
Hadar Hen Zion | 3cd0e17 | 2013-04-24 13:58:44 +0000 | [diff] [blame] | 1271 | } __packed; |
| 1272 | |
| 1273 | struct mlx4_net_trans_rule_hw_tcp_udp { |
| 1274 | u8 size; |
| 1275 | u8 rsvd; |
| 1276 | __be16 id; |
| 1277 | __be16 rsvd1[3]; |
| 1278 | __be16 dst_port; |
| 1279 | __be16 rsvd2; |
| 1280 | __be16 dst_port_msk; |
| 1281 | __be16 rsvd3; |
| 1282 | __be16 src_port; |
| 1283 | __be16 rsvd4; |
| 1284 | __be16 src_port_msk; |
| 1285 | } __packed; |
| 1286 | |
| 1287 | struct mlx4_net_trans_rule_hw_ipv4 { |
| 1288 | u8 size; |
| 1289 | u8 rsvd; |
| 1290 | __be16 id; |
| 1291 | __be32 rsvd1; |
| 1292 | __be32 dst_ip; |
| 1293 | __be32 dst_ip_msk; |
| 1294 | __be32 src_ip; |
| 1295 | __be32 src_ip_msk; |
| 1296 | } __packed; |
| 1297 | |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 1298 | struct mlx4_net_trans_rule_hw_vxlan { |
| 1299 | u8 size; |
| 1300 | u8 rsvd; |
| 1301 | __be16 id; |
| 1302 | __be32 rsvd1; |
| 1303 | __be32 vni; |
| 1304 | __be32 vni_mask; |
| 1305 | } __packed; |
| 1306 | |
Hadar Hen Zion | 3cd0e17 | 2013-04-24 13:58:44 +0000 | [diff] [blame] | 1307 | struct _rule_hw { |
| 1308 | union { |
| 1309 | struct { |
| 1310 | u8 size; |
| 1311 | u8 rsvd; |
| 1312 | __be16 id; |
| 1313 | }; |
| 1314 | struct mlx4_net_trans_rule_hw_eth eth; |
| 1315 | struct mlx4_net_trans_rule_hw_ib ib; |
| 1316 | struct mlx4_net_trans_rule_hw_ipv4 ipv4; |
| 1317 | struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 1318 | struct mlx4_net_trans_rule_hw_vxlan vxlan; |
Hadar Hen Zion | 3cd0e17 | 2013-04-24 13:58:44 +0000 | [diff] [blame] | 1319 | }; |
| 1320 | }; |
| 1321 | |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 1322 | enum { |
| 1323 | VXLAN_STEER_BY_OUTER_MAC = 1 << 0, |
| 1324 | VXLAN_STEER_BY_OUTER_VLAN = 1 << 1, |
| 1325 | VXLAN_STEER_BY_VSID_VNI = 1 << 2, |
| 1326 | VXLAN_STEER_BY_INNER_MAC = 1 << 3, |
| 1327 | VXLAN_STEER_BY_INNER_VLAN = 1 << 4, |
| 1328 | }; |
| 1329 | |
| 1330 | |
Hadar Hen Zion | 592e49d | 2012-07-05 04:03:48 +0000 | [diff] [blame] | 1331 | int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, |
| 1332 | enum mlx4_net_trans_promisc_mode mode); |
| 1333 | int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, |
| 1334 | enum mlx4_net_trans_promisc_mode mode); |
Yevgeny Petrilin | 1679200 | 2011-03-22 22:38:31 +0000 | [diff] [blame] | 1335 | int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); |
| 1336 | int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); |
| 1337 | int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); |
| 1338 | int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); |
| 1339 | int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1340 | |
Eugenia Emantayev | ffe455a | 2011-12-13 04:16:21 +0000 | [diff] [blame] | 1341 | int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); |
| 1342 | void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); |
Yan Burman | 16a10ff | 2013-02-07 02:25:22 +0000 | [diff] [blame] | 1343 | int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); |
| 1344 | int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); |
Yevgeny Petrilin | 9a9a232 | 2012-03-06 04:04:47 +0000 | [diff] [blame] | 1345 | int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, |
| 1346 | u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); |
| 1347 | int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, |
| 1348 | u8 promisc); |
Ido Shamay | 51af33c | 2015-04-02 16:31:20 +0300 | [diff] [blame] | 1349 | int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time); |
Muhammad Mahajna | 78500b8 | 2015-04-02 16:31:22 +0300 | [diff] [blame] | 1350 | int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port, |
| 1351 | u8 ignore_fcs_value); |
Or Gerlitz | 1b136de | 2014-03-27 14:02:04 +0200 | [diff] [blame] | 1352 | int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable); |
Hadar Hen Zion | 77fc29c | 2015-07-27 14:46:31 +0300 | [diff] [blame] | 1353 | int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val); |
| 1354 | int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv); |
Matan Barak | dd5f03b | 2013-12-12 18:03:11 +0200 | [diff] [blame] | 1355 | int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); |
Eli Cohen | 4c3eb3c | 2010-08-26 17:19:22 +0300 | [diff] [blame] | 1356 | int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); |
Yevgeny Petrilin | 2a2336f | 2008-10-22 11:44:46 -0700 | [diff] [blame] | 1357 | int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); |
Jack Morgenstein | 2009d00 | 2013-11-03 10:03:19 +0200 | [diff] [blame] | 1358 | void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); |
Yevgeny Petrilin | 2a2336f | 2008-10-22 11:44:46 -0700 | [diff] [blame] | 1359 | |
Jack Morgenstein | 8ad11fb | 2007-08-01 12:29:05 +0300 | [diff] [blame] | 1360 | int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, |
| 1361 | int npages, u64 iova, u32 *lkey, u32 *rkey); |
| 1362 | int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, |
| 1363 | int max_maps, u8 page_shift, struct mlx4_fmr *fmr); |
| 1364 | int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); |
| 1365 | void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, |
| 1366 | u32 *lkey, u32 *rkey); |
| 1367 | int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); |
| 1368 | int mlx4_SYNC_TPT(struct mlx4_dev *dev); |
Yevgeny Petrilin | e7c1c2c4 | 2010-08-24 03:46:18 +0000 | [diff] [blame] | 1369 | int mlx4_test_interrupts(struct mlx4_dev *dev); |
Matan Barak | c66fa19 | 2015-05-31 09:30:16 +0300 | [diff] [blame] | 1370 | u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port); |
| 1371 | bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector); |
| 1372 | struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port); |
| 1373 | int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector); |
Yevgeny Petrilin | 0b7ca5a | 2011-03-22 22:37:47 +0000 | [diff] [blame] | 1374 | void mlx4_release_eq(struct mlx4_dev *dev, int vec); |
Jack Morgenstein | 8ad11fb | 2007-08-01 12:29:05 +0300 | [diff] [blame] | 1375 | |
Matan Barak | c66fa19 | 2015-05-31 09:30:16 +0300 | [diff] [blame] | 1376 | int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector); |
Amir Vadai | 35f6f45 | 2014-06-29 11:54:55 +0300 | [diff] [blame] | 1377 | int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec); |
| 1378 | |
Hadar Hen Zion | 8e1a28e | 2013-12-19 21:20:12 +0200 | [diff] [blame] | 1379 | int mlx4_get_phys_port_id(struct mlx4_dev *dev); |
Yevgeny Petrilin | 14c07b1 | 2011-03-22 22:37:59 +0000 | [diff] [blame] | 1380 | int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); |
| 1381 | int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); |
| 1382 | |
Or Gerlitz | f2a3f6a | 2011-06-15 14:47:14 +0000 | [diff] [blame] | 1383 | int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); |
| 1384 | void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); |
Eran Ben Elisha | 6de5f7f | 2015-06-15 17:59:02 +0300 | [diff] [blame] | 1385 | int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port); |
Or Gerlitz | f2a3f6a | 2011-06-15 14:47:14 +0000 | [diff] [blame] | 1386 | |
Yishai Hadas | 773af94 | 2015-03-03 10:54:48 +0200 | [diff] [blame] | 1387 | void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, |
| 1388 | int port); |
| 1389 | __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port); |
Yishai Hadas | fb517a4 | 2015-03-03 11:23:32 +0200 | [diff] [blame] | 1390 | void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port); |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1391 | int mlx4_flow_attach(struct mlx4_dev *dev, |
| 1392 | struct mlx4_net_trans_rule *rule, u64 *reg_id); |
| 1393 | int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); |
Hadar Hen Zion | c2c19dc | 2013-04-24 13:58:48 +0000 | [diff] [blame] | 1394 | int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, |
| 1395 | enum mlx4_net_trans_promisc_mode flow_type); |
| 1396 | int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, |
| 1397 | enum mlx4_net_trans_rule_id id); |
| 1398 | int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1399 | |
Or Gerlitz | b95089d | 2014-08-27 16:47:48 +0300 | [diff] [blame] | 1400 | int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr, |
| 1401 | int port, int qpn, u16 prio, u64 *reg_id); |
| 1402 | |
Jack Morgenstein | 54679e1 | 2012-08-03 08:40:43 +0000 | [diff] [blame] | 1403 | void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, |
| 1404 | int i, int val); |
| 1405 | |
Jack Morgenstein | 396f2fe | 2012-06-19 11:21:42 +0300 | [diff] [blame] | 1406 | int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); |
| 1407 | |
Jack Morgenstein | 993c401 | 2012-08-03 08:40:48 +0000 | [diff] [blame] | 1408 | int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); |
| 1409 | int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); |
| 1410 | int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); |
| 1411 | int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); |
| 1412 | int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); |
| 1413 | enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); |
| 1414 | int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); |
| 1415 | |
Jack Morgenstein | afa8fd1 | 2012-08-03 08:40:56 +0000 | [diff] [blame] | 1416 | void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); |
| 1417 | __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); |
Jack Morgenstein | 9cd5935 | 2014-03-12 12:00:38 +0200 | [diff] [blame] | 1418 | |
| 1419 | int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, |
| 1420 | int *slave_id); |
| 1421 | int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, |
| 1422 | u8 *gid); |
Jack Morgenstein | 993c401 | 2012-08-03 08:40:48 +0000 | [diff] [blame] | 1423 | |
Matan Barak | 4de6580 | 2013-11-07 15:25:14 +0200 | [diff] [blame] | 1424 | int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, |
| 1425 | u32 max_range_qpn); |
| 1426 | |
Amir Vadai | ec693d4 | 2013-04-23 06:06:49 +0000 | [diff] [blame] | 1427 | cycle_t mlx4_read_clock(struct mlx4_dev *dev); |
| 1428 | |
Matan Barak | f74462a | 2014-03-19 18:11:51 +0200 | [diff] [blame] | 1429 | struct mlx4_active_ports { |
| 1430 | DECLARE_BITMAP(ports, MLX4_MAX_PORTS); |
| 1431 | }; |
| 1432 | /* Returns a bitmap of the physical ports which are assigned to slave */ |
| 1433 | struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave); |
| 1434 | |
| 1435 | /* Returns the physical port that represents the virtual port of the slave, */ |
| 1436 | /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */ |
| 1437 | /* mapping is returned. */ |
| 1438 | int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port); |
| 1439 | |
| 1440 | struct mlx4_slaves_pport { |
| 1441 | DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX); |
| 1442 | }; |
| 1443 | /* Returns a bitmap of all slaves that are assigned to port. */ |
| 1444 | struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev, |
| 1445 | int port); |
| 1446 | |
| 1447 | /* Returns a bitmap of all slaves that are assigned exactly to all the */ |
| 1448 | /* the ports that are set in crit_ports. */ |
| 1449 | struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv( |
| 1450 | struct mlx4_dev *dev, |
| 1451 | const struct mlx4_active_ports *crit_ports); |
| 1452 | |
| 1453 | /* Returns the slave's virtual port that represents the physical port. */ |
| 1454 | int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port); |
| 1455 | |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 1456 | int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port); |
Or Gerlitz | d18f141 | 2014-03-27 14:02:03 +0200 | [diff] [blame] | 1457 | |
| 1458 | int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port); |
Moni Shoua | 59e14e3 | 2015-02-03 16:48:32 +0200 | [diff] [blame] | 1459 | int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis); |
| 1460 | int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2); |
Jack Morgenstein | 97982f5 | 2014-05-29 16:31:02 +0300 | [diff] [blame] | 1461 | int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port); |
Jack Morgenstein | 65fed8a | 2014-05-29 16:31:04 +0300 | [diff] [blame] | 1462 | int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port); |
| 1463 | int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port, |
| 1464 | int enable); |
Matan Barak | e630664 | 2014-07-31 11:01:29 +0300 | [diff] [blame] | 1465 | int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, |
| 1466 | struct mlx4_mpt_entry ***mpt_entry); |
| 1467 | int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, |
| 1468 | struct mlx4_mpt_entry **mpt_entry); |
| 1469 | int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry, |
| 1470 | u32 pdn); |
| 1471 | int mlx4_mr_hw_change_access(struct mlx4_dev *dev, |
| 1472 | struct mlx4_mpt_entry *mpt_entry, |
| 1473 | u32 access); |
| 1474 | void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev, |
| 1475 | struct mlx4_mpt_entry **mpt_entry); |
| 1476 | void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr); |
| 1477 | int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr, |
| 1478 | u64 iova, u64 size, int npages, |
| 1479 | int page_shift, struct mlx4_mpt_entry *mpt_entry); |
Amir Vadai | 2599d85 | 2014-07-22 15:44:11 +0300 | [diff] [blame] | 1480 | |
Saeed Mahameed | 32a173c | 2014-10-27 11:37:35 +0200 | [diff] [blame] | 1481 | int mlx4_get_module_info(struct mlx4_dev *dev, u8 port, |
| 1482 | u16 offset, u16 size, u8 *data); |
| 1483 | |
Amir Vadai | 2599d85 | 2014-07-22 15:44:11 +0300 | [diff] [blame] | 1484 | /* Returns true if running in low memory profile (kdump kernel) */ |
| 1485 | static inline bool mlx4_low_memory_profile(void) |
| 1486 | { |
Amir Vadai | 48ea526 | 2014-08-25 16:06:53 +0300 | [diff] [blame] | 1487 | return is_kdump_kernel(); |
Amir Vadai | 2599d85 | 2014-07-22 15:44:11 +0300 | [diff] [blame] | 1488 | } |
| 1489 | |
Saeed Mahameed | adbc7ac | 2014-10-27 11:37:37 +0200 | [diff] [blame] | 1490 | /* ACCESS REG commands */ |
| 1491 | enum mlx4_access_reg_method { |
| 1492 | MLX4_ACCESS_REG_QUERY = 0x1, |
| 1493 | MLX4_ACCESS_REG_WRITE = 0x2, |
| 1494 | }; |
| 1495 | |
| 1496 | /* ACCESS PTYS Reg command */ |
| 1497 | enum mlx4_ptys_proto { |
| 1498 | MLX4_PTYS_IB = 1<<0, |
| 1499 | MLX4_PTYS_EN = 1<<2, |
| 1500 | }; |
| 1501 | |
| 1502 | struct mlx4_ptys_reg { |
| 1503 | u8 resrvd1; |
| 1504 | u8 local_port; |
| 1505 | u8 resrvd2; |
| 1506 | u8 proto_mask; |
| 1507 | __be32 resrvd3[2]; |
| 1508 | __be32 eth_proto_cap; |
| 1509 | __be16 ib_width_cap; |
| 1510 | __be16 ib_speed_cap; |
| 1511 | __be32 resrvd4; |
| 1512 | __be32 eth_proto_admin; |
| 1513 | __be16 ib_width_admin; |
| 1514 | __be16 ib_speed_admin; |
| 1515 | __be32 resrvd5; |
| 1516 | __be32 eth_proto_oper; |
| 1517 | __be16 ib_width_oper; |
| 1518 | __be16 ib_speed_oper; |
| 1519 | __be32 resrvd6; |
| 1520 | __be32 eth_proto_lp_adv; |
| 1521 | } __packed; |
| 1522 | |
| 1523 | int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, |
| 1524 | enum mlx4_access_reg_method method, |
| 1525 | struct mlx4_ptys_reg *ptys_reg); |
| 1526 | |
Matan Barak | 52033cf | 2015-06-11 16:35:26 +0300 | [diff] [blame] | 1527 | int mlx4_get_internal_clock_params(struct mlx4_dev *dev, |
| 1528 | struct mlx4_clock_params *params); |
| 1529 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1530 | #endif /* MLX4_DEVICE_H */ |