Rishabh Bhatnagar | e9a05bb | 2018-12-10 11:09:45 -0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 2 | /* |
Amir Samuelov | f52db41 | 2019-01-08 09:30:58 +0200 | [diff] [blame] | 3 | * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include "skeleton64.dtsi" |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 7 | |
| 8 | #include <dt-bindings/clock/qcom,aop-qmp.h> |
| 9 | #include <dt-bindings/clock/qcom,camcc-kona.h> |
| 10 | #include <dt-bindings/clock/qcom,cpucc-kona.h> |
| 11 | #include <dt-bindings/clock/qcom,dispcc-kona.h> |
| 12 | #include <dt-bindings/clock/qcom,gcc-kona.h> |
| 13 | #include <dt-bindings/clock/qcom,gpucc-kona.h> |
| 14 | #include <dt-bindings/clock/qcom,npucc-kona.h> |
| 15 | #include <dt-bindings/clock/qcom,rpmh.h> |
| 16 | #include <dt-bindings/clock/qcom,videocc-kona.h> |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 17 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
David Dai | b1d6848 | 2018-10-01 19:40:35 -0700 | [diff] [blame] | 18 | #include <dt-bindings/msm/msm-bus-ids.h> |
Raghavendra Rao Ananta | 0295796 | 2018-08-06 15:28:34 -0700 | [diff] [blame] | 19 | #include <dt-bindings/soc/qcom,ipcc.h> |
Lina Iyer | ea91c72 | 2018-06-20 14:58:05 -0600 | [diff] [blame] | 20 | #include <dt-bindings/soc/qcom,rpmh-rsc.h> |
Rishabh Bhatnagar | 2b66dc1 | 2018-10-18 10:36:27 -0700 | [diff] [blame] | 21 | #include <dt-bindings/gpio/gpio.h> |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 22 | |
David Collins | 54e4530 | 2018-06-29 18:46:53 -0700 | [diff] [blame] | 23 | #include "kona-regulators.dtsi" |
| 24 | |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 25 | / { |
| 26 | model = "Qualcomm Technologies, Inc. kona"; |
| 27 | compatible = "qcom,kona"; |
| 28 | qcom,msm-id = <356 0x10000>; |
| 29 | interrupt-parent = <&intc>; |
| 30 | |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 31 | aliases { |
| 32 | ufshc1 = &ufshc_mem; /* Embedded UFS slot */ |
Tony Truong | c972c64 | 2018-09-12 10:03:51 -0700 | [diff] [blame] | 33 | pci-domain2 = &pcie2; /* PCIe2 domain */ |
Vipin Deep Kaur | 9a2c13d | 2018-12-19 18:38:46 +0530 | [diff] [blame] | 34 | serial0 = &qupv3_se2_2uart; /* RUMI */ |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 35 | }; |
| 36 | |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 37 | cpus { |
| 38 | #address-cells = <2>; |
| 39 | #size-cells = <0>; |
| 40 | |
| 41 | CPU0: cpu@0 { |
| 42 | device_type = "cpu"; |
| 43 | compatible = "qcom,kryo"; |
| 44 | reg = <0x0 0x0>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 45 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 46 | cache-size = <0x8000>; |
| 47 | cpu-release-addr = <0x0 0x90000000>; |
| 48 | next-level-cache = <&L2_0>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 49 | qcom,freq-domain = <&cpufreq_hw 0 4>; |
Satya Durga Srinivasu Prabhala | 86db38d | 2018-11-06 13:21:20 -0800 | [diff] [blame] | 50 | capacity-dmips-mhz = <1024>; |
Satya Durga Srinivasu Prabhala | 50812f7 | 2018-12-13 12:50:08 -0800 | [diff] [blame] | 51 | dynamic-power-coefficient = <100>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 52 | L2_0: l2-cache { |
| 53 | compatible = "arm,arch-cache"; |
| 54 | cache-size = <0x20000>; |
| 55 | cache-level = <2>; |
| 56 | next-level-cache = <&L3_0>; |
| 57 | |
| 58 | L3_0: l3-cache { |
| 59 | compatible = "arm,arch-cache"; |
| 60 | cache-size = <0x400000>; |
| 61 | cache-level = <3>; |
| 62 | }; |
| 63 | }; |
| 64 | }; |
| 65 | |
| 66 | CPU1: cpu@100 { |
| 67 | device_type = "cpu"; |
| 68 | compatible = "qcom,kryo"; |
| 69 | reg = <0x0 0x100>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 70 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 71 | cache-size = <0x8000>; |
| 72 | cpu-release-addr = <0x0 0x90000000>; |
| 73 | next-level-cache = <&L2_1>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 74 | qcom,freq-domain = <&cpufreq_hw 0 4>; |
Satya Durga Srinivasu Prabhala | 86db38d | 2018-11-06 13:21:20 -0800 | [diff] [blame] | 75 | capacity-dmips-mhz = <1024>; |
Satya Durga Srinivasu Prabhala | 50812f7 | 2018-12-13 12:50:08 -0800 | [diff] [blame] | 76 | dynamic-power-coefficient = <100>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 77 | L2_1: l2-cache { |
| 78 | compatible = "arm,arch-cache"; |
| 79 | cache-size = <0x20000>; |
| 80 | cache-level = <2>; |
| 81 | next-level-cache = <&L3_0>; |
| 82 | }; |
| 83 | }; |
| 84 | |
| 85 | CPU2: cpu@200 { |
| 86 | device_type = "cpu"; |
| 87 | compatible = "qcom,kryo"; |
| 88 | reg = <0x0 0x200>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 89 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 90 | cache-size = <0x8000>; |
| 91 | cpu-release-addr = <0x0 0x90000000>; |
| 92 | next-level-cache = <&L2_2>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 93 | qcom,freq-domain = <&cpufreq_hw 0 4>; |
Satya Durga Srinivasu Prabhala | 86db38d | 2018-11-06 13:21:20 -0800 | [diff] [blame] | 94 | capacity-dmips-mhz = <1024>; |
Satya Durga Srinivasu Prabhala | 50812f7 | 2018-12-13 12:50:08 -0800 | [diff] [blame] | 95 | dynamic-power-coefficient = <100>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 96 | L2_2: l2-cache { |
| 97 | compatible = "arm,arch-cache"; |
| 98 | cache-size = <0x20000>; |
| 99 | cache-level = <2>; |
| 100 | next-level-cache = <&L3_0>; |
| 101 | }; |
| 102 | }; |
| 103 | |
| 104 | CPU3: cpu@300 { |
| 105 | device_type = "cpu"; |
| 106 | compatible = "qcom,kryo"; |
| 107 | reg = <0x0 0x300>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 108 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 109 | cache-size = <0x8000>; |
| 110 | cpu-release-addr = <0x0 0x90000000>; |
| 111 | next-level-cache = <&L2_3>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 112 | qcom,freq-domain = <&cpufreq_hw 0 4>; |
Satya Durga Srinivasu Prabhala | 86db38d | 2018-11-06 13:21:20 -0800 | [diff] [blame] | 113 | capacity-dmips-mhz = <1024>; |
Satya Durga Srinivasu Prabhala | 50812f7 | 2018-12-13 12:50:08 -0800 | [diff] [blame] | 114 | dynamic-power-coefficient = <100>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 115 | L2_3: l2-cache { |
| 116 | compatible = "arm,arch-cache"; |
| 117 | cache-size = <0x20000>; |
| 118 | cache-level = <2>; |
| 119 | next-level-cache = <&L3_0>; |
| 120 | }; |
| 121 | }; |
| 122 | |
| 123 | CPU4: cpu@400 { |
| 124 | device_type = "cpu"; |
| 125 | compatible = "qcom,kryo"; |
| 126 | reg = <0x0 0x400>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 127 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 128 | cache-size = <0x10000>; |
| 129 | cpu-release-addr = <0x0 0x90000000>; |
| 130 | next-level-cache = <&L2_4>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 131 | qcom,freq-domain = <&cpufreq_hw 1 4>; |
Satya Durga Srinivasu Prabhala | 86db38d | 2018-11-06 13:21:20 -0800 | [diff] [blame] | 132 | capacity-dmips-mhz = <1894>; |
Satya Durga Srinivasu Prabhala | 50812f7 | 2018-12-13 12:50:08 -0800 | [diff] [blame] | 133 | dynamic-power-coefficient = <374>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 134 | L2_4: l2-cache { |
| 135 | compatible = "arm,arch-cache"; |
| 136 | cache-size = <0x20000>; |
| 137 | cache-level = <2>; |
| 138 | next-level-cache = <&L3_0>; |
| 139 | }; |
| 140 | }; |
| 141 | |
| 142 | CPU5: cpu@500 { |
| 143 | device_type = "cpu"; |
| 144 | compatible = "qcom,kryo"; |
| 145 | reg = <0x0 0x500>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 146 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 147 | cache-size = <0x10000>; |
| 148 | cpu-release-addr = <0x0 0x90000000>; |
| 149 | next-level-cache = <&L2_5>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 150 | qcom,freq-domain = <&cpufreq_hw 1 4>; |
Satya Durga Srinivasu Prabhala | 86db38d | 2018-11-06 13:21:20 -0800 | [diff] [blame] | 151 | capacity-dmips-mhz = <1894>; |
Satya Durga Srinivasu Prabhala | 50812f7 | 2018-12-13 12:50:08 -0800 | [diff] [blame] | 152 | dynamic-power-coefficient = <374>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 153 | L2_5: l2-cache { |
| 154 | compatible = "arm,arch-cache"; |
| 155 | cache-size = <0x20000>; |
| 156 | cache-level = <2>; |
| 157 | next-level-cache = <&L3_0>; |
| 158 | }; |
| 159 | }; |
| 160 | |
| 161 | CPU6: cpu@600 { |
| 162 | device_type = "cpu"; |
| 163 | compatible = "qcom,kryo"; |
| 164 | reg = <0x0 0x600>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 165 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 166 | cache-size = <0x10000>; |
| 167 | cpu-release-addr = <0x0 0x90000000>; |
| 168 | next-level-cache = <&L2_6>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 169 | qcom,freq-domain = <&cpufreq_hw 1 4>; |
Satya Durga Srinivasu Prabhala | 86db38d | 2018-11-06 13:21:20 -0800 | [diff] [blame] | 170 | capacity-dmips-mhz = <1894>; |
Satya Durga Srinivasu Prabhala | 50812f7 | 2018-12-13 12:50:08 -0800 | [diff] [blame] | 171 | dynamic-power-coefficient = <374>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 172 | L2_6: l2-cache { |
| 173 | compatible = "arm,arch-cache"; |
| 174 | cache-size = <0x20000>; |
| 175 | cache-level = <2>; |
| 176 | next-level-cache = <&L3_0>; |
| 177 | }; |
| 178 | }; |
| 179 | |
| 180 | CPU7: cpu@700 { |
| 181 | device_type = "cpu"; |
| 182 | compatible = "qcom,kryo"; |
| 183 | reg = <0x0 0x700>; |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 184 | enable-method = "psci"; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 185 | cache-size = <0x10000>; |
| 186 | cpu-release-addr = <0x0 0x90000000>; |
| 187 | next-level-cache = <&L2_7>; |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 188 | qcom,freq-domain = <&cpufreq_hw 2 4>; |
Satya Durga Srinivasu Prabhala | 86db38d | 2018-11-06 13:21:20 -0800 | [diff] [blame] | 189 | capacity-dmips-mhz = <1894>; |
Satya Durga Srinivasu Prabhala | 50812f7 | 2018-12-13 12:50:08 -0800 | [diff] [blame] | 190 | dynamic-power-coefficient = <431>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 191 | L2_7: l2-cache { |
| 192 | compatible = "arm,arch-cache"; |
| 193 | cache-size = <0x80000>; |
| 194 | cache-level = <2>; |
| 195 | next-level-cache = <&L3_0>; |
| 196 | }; |
| 197 | }; |
| 198 | |
| 199 | cpu-map { |
| 200 | cluster0 { |
| 201 | core0 { |
| 202 | cpu = <&CPU0>; |
| 203 | }; |
| 204 | |
| 205 | core1 { |
| 206 | cpu = <&CPU1>; |
| 207 | }; |
| 208 | |
| 209 | core2 { |
| 210 | cpu = <&CPU2>; |
| 211 | }; |
| 212 | |
| 213 | core3 { |
| 214 | cpu = <&CPU3>; |
| 215 | }; |
| 216 | }; |
| 217 | |
| 218 | cluster1 { |
| 219 | core0 { |
| 220 | cpu = <&CPU4>; |
| 221 | }; |
| 222 | |
| 223 | core1 { |
| 224 | cpu = <&CPU5>; |
| 225 | }; |
| 226 | |
| 227 | core2 { |
| 228 | cpu = <&CPU6>; |
| 229 | }; |
Satya Durga Srinivasu Prabhala | 86db38d | 2018-11-06 13:21:20 -0800 | [diff] [blame] | 230 | }; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 231 | |
Satya Durga Srinivasu Prabhala | 86db38d | 2018-11-06 13:21:20 -0800 | [diff] [blame] | 232 | cluster2 { |
| 233 | core0 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 234 | cpu = <&CPU7>; |
| 235 | }; |
| 236 | }; |
| 237 | }; |
| 238 | }; |
| 239 | |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 240 | |
Channagoud Kadabi | cdd72a0 | 2018-09-21 14:46:21 -0700 | [diff] [blame] | 241 | cpu_pmu: cpu-pmu { |
| 242 | compatible = "arm,armv8-pmuv3"; |
| 243 | qcom,irq-is-percpu; |
| 244 | interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| 245 | }; |
| 246 | |
David Dai | a4635e6 | 2018-10-11 13:39:44 -0700 | [diff] [blame] | 247 | soc: soc { |
| 248 | cpufreq_hw: qcom,cpufreq-hw { |
| 249 | compatible = "qcom,cpufreq-hw"; |
| 250 | reg = <0x18591000 0x1000>, <0x18592000 0x1000>, |
| 251 | <0x18593000 0x1000>; |
| 252 | reg-names = "freq-domain0", "freq-domain1", |
| 253 | "freq-domain2"; |
| 254 | |
| 255 | clocks = <&clock_xo>, <&clock_gcc GPLL0>; |
| 256 | clock-names = "xo", "cpu_clk"; |
| 257 | |
| 258 | #freq-domain-cells = <2>; |
| 259 | }; |
| 260 | }; |
| 261 | |
Arjun Bagla | 76f02ef | 2018-09-19 10:00:29 -0700 | [diff] [blame] | 262 | psci { |
| 263 | compatible = "arm,psci-1.0"; |
| 264 | method = "smc"; |
| 265 | }; |
| 266 | |
Bruce Levy | 3bd8d1b | 2018-09-11 11:31:13 -0700 | [diff] [blame] | 267 | firmware: firmware { |
| 268 | android { |
| 269 | compatible = "android,firmware"; |
| 270 | fstab { |
| 271 | compatible = "android,fstab"; |
| 272 | vendor { |
| 273 | compatible = "android,vendor"; |
| 274 | dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; |
| 275 | type = "ext4"; |
| 276 | mnt_flags = "ro,barrier=1,discard"; |
| 277 | fsmgr_flags = "wait,slotselect,avb"; |
| 278 | status = "ok"; |
| 279 | }; |
| 280 | }; |
| 281 | }; |
| 282 | }; |
| 283 | |
Channagoud Kadabi | da4367b | 2018-09-20 15:07:04 -0700 | [diff] [blame] | 284 | psci { |
| 285 | compatible = "arm,psci-1.0"; |
| 286 | method = "smc"; |
| 287 | }; |
| 288 | |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 289 | reserved-memory { |
| 290 | #address-cells = <2>; |
| 291 | #size-cells = <2>; |
| 292 | ranges; |
| 293 | |
| 294 | hyp_mem: hyp_region@80000000 { |
| 295 | no-map; |
| 296 | reg = <0x0 0x80000000 0x0 0x600000>; |
| 297 | }; |
| 298 | |
| 299 | xbl_aop_mem: xbl_aop_region@80700000 { |
| 300 | no-map; |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 301 | reg = <0x0 0x80700000 0x0 0x120000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 302 | }; |
| 303 | |
Lina Iyer | 5d609fa | 2018-10-03 14:26:55 -0600 | [diff] [blame] | 304 | cmd_db: reserved-memory@80820000 { |
| 305 | reg = <0x0 0x80820000 0x0 0x20000>; |
| 306 | compatible = "qcom,cmd-db"; |
| 307 | no-map; |
| 308 | }; |
| 309 | |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 310 | smem_mem: smem_region@80900000 { |
| 311 | no-map; |
| 312 | reg = <0x0 0x80900000 0x0 0x200000>; |
| 313 | }; |
| 314 | |
| 315 | removed_mem: removed_region@80b00000 { |
| 316 | no-map; |
| 317 | reg = <0x0 0x80b00000 0x0 0xc00000>; |
| 318 | }; |
| 319 | |
| 320 | qtee_apps_mem: qtee_apps_region@81e00000 { |
| 321 | no-map; |
| 322 | reg = <0x0 0x81e00000 0x0 0x2600000>; |
| 323 | }; |
| 324 | |
| 325 | pil_camera_mem: pil_camera_region@86000000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 326 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 327 | no-map; |
| 328 | reg = <0x0 0x86000000 0x0 0x500000>; |
| 329 | }; |
| 330 | |
| 331 | pil_wlan_fw_mem: pil_wlan_fw_region@86500000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 332 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 333 | no-map; |
| 334 | reg = <0x0 0x86500000 0x0 0x100000>; |
| 335 | }; |
| 336 | |
| 337 | pil_ipa_fw_mem: pil_ipa_fw_region@86600000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 338 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 339 | no-map; |
| 340 | reg = <0x0 0x86600000 0x0 0x10000>; |
| 341 | }; |
| 342 | |
| 343 | pil_ipa_gsi_mem: pil_ipa_gsi_region@86610000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 344 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 345 | no-map; |
| 346 | reg = <0x0 0x86610000 0x0 0x5000>; |
| 347 | }; |
| 348 | |
| 349 | pil_gpu_mem: pil_gpu_region@86615000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 350 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 351 | no-map; |
| 352 | reg = <0x0 0x86615000 0x0 0x2000>; |
| 353 | }; |
| 354 | |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 355 | pil_npu_mem: pil_npu_region@86700000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 356 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 357 | no-map; |
| 358 | reg = <0x0 0x86700000 0x0 0x500000>; |
| 359 | }; |
| 360 | |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 361 | pil_video_mem: pil_video_region@86c00000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 362 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 363 | no-map; |
| 364 | reg = <0x0 0x86c00000 0x0 0x500000>; |
| 365 | }; |
| 366 | |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 367 | pil_cvp_mem: pil_cvp_region@87100000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 368 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 369 | no-map; |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 370 | reg = <0x0 0x87100000 0x0 0x500000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 371 | }; |
| 372 | |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 373 | pil_cdsp_mem: pil_cdsp_region@87600000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 374 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 375 | no-map; |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 376 | reg = <0x0 0x87600000 0x0 0x800000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 377 | }; |
| 378 | |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 379 | pil_slpi_mem: pil_slpi_region@87e00000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 380 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 381 | no-map; |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 382 | reg = <0x0 0x87e00000 0x0 0x1500000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 383 | }; |
| 384 | |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 385 | pil_adsp_mem: pil_adsp_region@89300000 { |
Swathi Sridhar | 2f97156 | 2018-10-02 15:43:09 -0700 | [diff] [blame] | 386 | compatible = "removed-dma-pool"; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 387 | no-map; |
Swathi Sridhar | 19db3ed | 2018-11-29 11:01:42 -0800 | [diff] [blame] | 388 | reg = <0x0 0x89300000 0x0 0x1a00000>; |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 389 | }; |
| 390 | |
Swathi Sridhar | 19db3ed | 2018-11-29 11:01:42 -0800 | [diff] [blame] | 391 | pil_spss_mem: pil_spss_region@8ad00000 { |
Swathi Sridhar | 072b0ad | 2018-10-16 22:52:57 -0700 | [diff] [blame] | 392 | compatible = "removed-dma-pool"; |
| 393 | no-map; |
Swathi Sridhar | 19db3ed | 2018-11-29 11:01:42 -0800 | [diff] [blame] | 394 | reg = <0x0 0x8ad00000 0x0 0x100000>; |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 395 | }; |
| 396 | |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 397 | adsp_mem: adsp_region { |
| 398 | compatible = "shared-dma-pool"; |
| 399 | alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| 400 | reusable; |
| 401 | alignment = <0x0 0x400000>; |
| 402 | size = <0x0 0x1000000>; |
| 403 | }; |
| 404 | |
George Shen | 9c54c66 | 2018-12-26 15:50:11 -0800 | [diff] [blame] | 405 | cdsp_mem: cdsp_region { |
| 406 | compatible = "shared-dma-pool"; |
| 407 | alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| 408 | reusable; |
| 409 | alignment = <0x0 0x400000>; |
| 410 | size = <0x0 0x400000>; |
| 411 | }; |
| 412 | |
Tingwei Zhang | d9b535f | 2018-12-03 19:14:06 -0800 | [diff] [blame] | 413 | dump_mem: mem_dump_region { |
| 414 | compatible = "shared-dma-pool"; |
| 415 | reusable; |
| 416 | size = <0 0x2400000>; |
| 417 | }; |
| 418 | |
Swathi Sridhar | a79a954 | 2018-06-21 11:40:44 -0700 | [diff] [blame] | 419 | /* global autoconfigured region for contiguous allocations */ |
| 420 | linux,cma { |
| 421 | compatible = "shared-dma-pool"; |
| 422 | alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| 423 | reusable; |
| 424 | alignment = <0x0 0x400000>; |
| 425 | size = <0x0 0x2000000>; |
| 426 | linux,cma-default; |
| 427 | }; |
| 428 | }; |
Bruce Levy | c5eb199 | 2019-01-11 12:09:18 -0800 | [diff] [blame^] | 429 | |
| 430 | vendor: vendor { |
| 431 | #address-cells = <1>; |
| 432 | #size-cells = <1>; |
| 433 | ranges = <0 0 0 0xffffffff>; |
| 434 | compatible = "simple-bus"; |
| 435 | }; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 436 | }; |
| 437 | |
| 438 | &soc { |
| 439 | #address-cells = <1>; |
| 440 | #size-cells = <1>; |
| 441 | ranges = <0 0 0 0xffffffff>; |
| 442 | compatible = "simple-bus"; |
| 443 | |
David Collins | 692dff7 | 2018-11-12 17:09:49 -0800 | [diff] [blame] | 444 | thermal_zones: thermal-zones { |
| 445 | }; |
| 446 | |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 447 | intc: interrupt-controller@17a00000 { |
| 448 | compatible = "arm,gic-v3"; |
| 449 | #interrupt-cells = <3>; |
| 450 | interrupt-controller; |
| 451 | #redistributor-regions = <1>; |
| 452 | redistributor-stride = <0x0 0x20000>; |
| 453 | reg = <0x17a00000 0x10000>, /* GICD */ |
| 454 | <0x17a60000 0x100000>; /* GICR * 8 */ |
| 455 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| 456 | }; |
| 457 | |
Rishabh Bhatnagar | fd73eb1 | 2018-09-04 15:00:46 -0700 | [diff] [blame] | 458 | qcom,chd_silver { |
| 459 | compatible = "qcom,core-hang-detect"; |
| 460 | label = "silver"; |
| 461 | qcom,threshold-arr = <0x18000058 0x18010058 |
| 462 | 0x18020058 0x18030058>; |
| 463 | qcom,config-arr = <0x18000060 0x18010060 |
| 464 | 0x18020060 0x18030060>; |
| 465 | }; |
| 466 | |
| 467 | qcom,chd_gold { |
| 468 | compatible = "qcom,core-hang-detect"; |
| 469 | label = "gold"; |
| 470 | qcom,threshold-arr = <0x18040058 0x18050058 |
| 471 | 0x18060058 0x18070058>; |
| 472 | qcom,config-arr = <0x18040060 0x18050060 |
| 473 | 0x18060060 0x18070060>; |
| 474 | }; |
| 475 | |
Rishabh Bhatnagar | 8f0dd4b | 2018-08-07 11:07:40 -0700 | [diff] [blame] | 476 | cache-controller@9200000 { |
| 477 | compatible = "qcom,kona-llcc"; |
| 478 | reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>; |
| 479 | reg-names = "llcc_base", "llcc_broadcast_base"; |
Channagoud Kadabi | a13ed0a | 2018-09-26 16:10:35 -0700 | [diff] [blame] | 480 | interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; |
Rishabh Bhatnagar | 8f0dd4b | 2018-08-07 11:07:40 -0700 | [diff] [blame] | 481 | }; |
| 482 | |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 483 | arch_timer: timer { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 484 | compatible = "arm,armv8-timer"; |
| 485 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| 486 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| 487 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| 488 | <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; |
| 489 | clock-frequency = <19200000>; |
| 490 | }; |
| 491 | |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 492 | memtimer: timer@17c20000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 493 | #address-cells = <1>; |
| 494 | #size-cells = <1>; |
| 495 | ranges; |
| 496 | compatible = "arm,armv7-timer-mem"; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 497 | reg = <0x17c20000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 498 | clock-frequency = <19200000>; |
| 499 | |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 500 | frame@17c21000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 501 | frame-number = <0>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 502 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 503 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 504 | reg = <0x17c21000 0x1000>, |
| 505 | <0x17c22000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 506 | }; |
| 507 | |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 508 | frame@17c23000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 509 | frame-number = <1>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 510 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| 511 | reg = <0x17c23000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 512 | status = "disabled"; |
| 513 | }; |
| 514 | |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 515 | frame@17c25000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 516 | frame-number = <2>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 517 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| 518 | reg = <0x17c25000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 519 | status = "disabled"; |
| 520 | }; |
| 521 | |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 522 | frame@17c27000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 523 | frame-number = <3>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 524 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| 525 | reg = <0x17c27000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 526 | status = "disabled"; |
| 527 | }; |
| 528 | |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 529 | frame@17c29000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 530 | frame-number = <4>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 531 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| 532 | reg = <0x17c29000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 533 | status = "disabled"; |
| 534 | }; |
| 535 | |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 536 | frame@17c2b000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 537 | frame-number = <5>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 538 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| 539 | reg = <0x17c2b000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 540 | status = "disabled"; |
| 541 | }; |
| 542 | |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 543 | frame@17c2d000 { |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 544 | frame-number = <6>; |
Rishabh Bhatnagar | 5c1c176 | 2018-05-29 17:04:46 -0700 | [diff] [blame] | 545 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| 546 | reg = <0x17c2d000 0x1000>; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 547 | status = "disabled"; |
| 548 | }; |
| 549 | }; |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 550 | |
Tingwei Zhang | 020594a | 2018-11-27 21:58:09 -0800 | [diff] [blame] | 551 | jtag_mm0: jtagmm@7040000 { |
| 552 | compatible = "qcom,jtagv8-mm"; |
| 553 | reg = <0x7040000 0x1000>; |
| 554 | reg-names = "etm-base"; |
| 555 | |
| 556 | clocks = <&clock_aop QDSS_CLK>; |
| 557 | clock-names = "core_clk"; |
| 558 | |
| 559 | qcom,coresight-jtagmm-cpu = <&CPU0>; |
| 560 | }; |
| 561 | |
| 562 | jtag_mm1: jtagmm@7140000 { |
| 563 | compatible = "qcom,jtagv8-mm"; |
| 564 | reg = <0x7140000 0x1000>; |
| 565 | reg-names = "etm-base"; |
| 566 | |
| 567 | clocks = <&clock_aop QDSS_CLK>; |
| 568 | clock-names = "core_clk"; |
| 569 | |
| 570 | qcom,coresight-jtagmm-cpu = <&CPU1>; |
| 571 | }; |
| 572 | |
| 573 | jtag_mm2: jtagmm@7240000 { |
| 574 | compatible = "qcom,jtagv8-mm"; |
| 575 | reg = <0x7240000 0x1000>; |
| 576 | reg-names = "etm-base"; |
| 577 | |
| 578 | clocks = <&clock_aop QDSS_CLK>; |
| 579 | clock-names = "core_clk"; |
| 580 | |
| 581 | qcom,coresight-jtagmm-cpu = <&CPU2>; |
| 582 | }; |
| 583 | |
| 584 | jtag_mm3: jtagmm@7340000 { |
| 585 | compatible = "qcom,jtagv8-mm"; |
| 586 | reg = <0x7340000 0x1000>; |
| 587 | reg-names = "etm-base"; |
| 588 | |
| 589 | clocks = <&clock_aop QDSS_CLK>; |
| 590 | clock-names = "core_clk"; |
| 591 | |
| 592 | qcom,coresight-jtagmm-cpu = <&CPU3>; |
| 593 | }; |
| 594 | |
| 595 | jtag_mm4: jtagmm@7440000 { |
| 596 | compatible = "qcom,jtagv8-mm"; |
| 597 | reg = <0x7440000 0x1000>; |
| 598 | reg-names = "etm-base"; |
| 599 | |
| 600 | clocks = <&clock_aop QDSS_CLK>; |
| 601 | clock-names = "core_clk"; |
| 602 | |
| 603 | qcom,coresight-jtagmm-cpu = <&CPU4>; |
| 604 | }; |
| 605 | |
| 606 | jtag_mm5: jtagmm@7540000 { |
| 607 | compatible = "qcom,jtagv8-mm"; |
| 608 | reg = <0x7540000 0x1000>; |
| 609 | reg-names = "etm-base"; |
| 610 | |
| 611 | clocks = <&clock_aop QDSS_CLK>; |
| 612 | clock-names = "core_clk"; |
| 613 | |
| 614 | qcom,coresight-jtagmm-cpu = <&CPU5>; |
| 615 | }; |
| 616 | |
| 617 | jtag_mm6: jtagmm@7640000 { |
| 618 | compatible = "qcom,jtagv8-mm"; |
| 619 | reg = <0x7640000 0x1000>; |
| 620 | reg-names = "etm-base"; |
| 621 | |
| 622 | clocks = <&clock_aop QDSS_CLK>; |
| 623 | clock-names = "core_clk"; |
| 624 | |
| 625 | qcom,coresight-jtagmm-cpu = <&CPU6>; |
| 626 | }; |
| 627 | |
| 628 | jtag_mm7: jtagmm@7740000 { |
| 629 | compatible = "qcom,jtagv8-mm"; |
| 630 | reg = <0x7740000 0x1000>; |
| 631 | reg-names = "etm-base"; |
| 632 | |
| 633 | clocks = <&clock_aop QDSS_CLK>; |
| 634 | clock-names = "core_clk"; |
| 635 | |
| 636 | qcom,coresight-jtagmm-cpu = <&CPU7>; |
| 637 | }; |
| 638 | |
David Dai | 3c42780 | 2018-10-17 14:40:08 -0700 | [diff] [blame] | 639 | qcom,devfreq-l3 { |
| 640 | compatible = "qcom,devfreq-fw"; |
| 641 | reg = <0x18590000 0x4>, <0x18590100 0xa0>, <0x18590320 0x4>; |
| 642 | reg-names = "en-base", "ftbl-base", "perf-base"; |
| 643 | |
| 644 | qcom,cpu0-l3 { |
| 645 | compatible = "qcom,devfreq-fw-voter"; |
| 646 | }; |
| 647 | |
| 648 | qcom,cpu4-l3 { |
| 649 | compatible = "qcom,devfreq-fw-voter"; |
| 650 | }; |
| 651 | }; |
| 652 | |
Rishabh Bhatnagar | f35ba02 | 2018-09-18 15:17:22 -0700 | [diff] [blame] | 653 | qcom,msm-imem@146bf000 { |
Rishabh Bhatnagar | 2b6a59c | 2018-09-06 11:06:16 -0700 | [diff] [blame] | 654 | compatible = "qcom,msm-imem"; |
| 655 | reg = <0x146bf000 0x1000>; |
| 656 | ranges = <0x0 0x146bf000 0x1000>; |
| 657 | #address-cells = <1>; |
| 658 | #size-cells = <1>; |
| 659 | |
Tingwei Zhang | d9b535f | 2018-12-03 19:14:06 -0800 | [diff] [blame] | 660 | mem_dump_table@10 { |
| 661 | compatible = "qcom,msm-imem-mem_dump_table"; |
| 662 | reg = <0x10 0x8>; |
| 663 | }; |
| 664 | |
Rishabh Bhatnagar | 2b6a59c | 2018-09-06 11:06:16 -0700 | [diff] [blame] | 665 | restart_reason@65c { |
| 666 | compatible = "qcom,msm-imem-restart_reason"; |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 667 | reg = <0x65c 0x4>; |
Rishabh Bhatnagar | 2b6a59c | 2018-09-06 11:06:16 -0700 | [diff] [blame] | 668 | }; |
| 669 | |
| 670 | dload_type@1c { |
| 671 | compatible = "qcom,msm-imem-dload-type"; |
| 672 | reg = <0x1c 0x4>; |
| 673 | }; |
| 674 | |
| 675 | boot_stats@6b0 { |
| 676 | compatible = "qcom,msm-imem-boot_stats"; |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 677 | reg = <0x6b0 0x20>; |
Rishabh Bhatnagar | 2b6a59c | 2018-09-06 11:06:16 -0700 | [diff] [blame] | 678 | }; |
| 679 | |
| 680 | kaslr_offset@6d0 { |
| 681 | compatible = "qcom,msm-imem-kaslr_offset"; |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 682 | reg = <0x6d0 0xc>; |
Rishabh Bhatnagar | 2b6a59c | 2018-09-06 11:06:16 -0700 | [diff] [blame] | 683 | }; |
| 684 | |
| 685 | pil@94c { |
| 686 | compatible = "qcom,msm-imem-pil"; |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 687 | reg = <0x94c 0xc8>; |
Rishabh Bhatnagar | 2b6a59c | 2018-09-06 11:06:16 -0700 | [diff] [blame] | 688 | }; |
| 689 | }; |
| 690 | |
Rishabh Bhatnagar | 811170f | 2018-11-09 13:44:32 -0800 | [diff] [blame] | 691 | restart@c264000 { |
| 692 | compatible = "qcom,pshold"; |
| 693 | reg = <0xc264000 0x4>, |
| 694 | <0x1fd3000 0x4>; |
| 695 | reg-names = "pshold-base", "tcsr-boot-misc-detect"; |
| 696 | }; |
| 697 | |
Rishabh Bhatnagar | 19ddb35e | 2018-09-18 15:53:03 -0700 | [diff] [blame] | 698 | mdm0: qcom,mdm0 { |
Rishabh Bhatnagar | 134ede8 | 2018-10-16 10:54:12 -0700 | [diff] [blame] | 699 | compatible = "qcom,ext-sdx55m"; |
Rishabh Bhatnagar | 19ddb35e | 2018-09-18 15:53:03 -0700 | [diff] [blame] | 700 | cell-index = <0>; |
| 701 | #address-cells = <0>; |
| 702 | interrupt-parent = <&mdm0>; |
| 703 | #interrupt-cells = <1>; |
| 704 | interrupt-map-mask = <0xffffffff>; |
| 705 | interrupt-names = |
| 706 | "err_fatal_irq", |
| 707 | "status_irq", |
| 708 | "mdm2ap_vddmin_irq"; |
| 709 | /* modem attributes */ |
| 710 | qcom,ramdump-delay-ms = <3000>; |
| 711 | qcom,ramdump-timeout-ms = <120000>; |
| 712 | qcom,vddmin-modes = "normal"; |
| 713 | qcom,vddmin-drive-strength = <8>; |
| 714 | qcom,sfr-query; |
| 715 | qcom,sysmon-id = <20>; |
| 716 | qcom,ssctl-instance-id = <0x10>; |
| 717 | qcom,support-shutdown; |
| 718 | qcom,pil-force-shutdown; |
| 719 | qcom,esoc-skip-restart-for-mdm-crash; |
| 720 | pinctrl-names = "default", "mdm_active", "mdm_suspend"; |
| 721 | pinctrl-0 = <&ap2mdm_pon_reset_default>; |
| 722 | pinctrl-1 = <&ap2mdm_active &mdm2ap_active>; |
| 723 | pinctrl-2 = <&ap2mdm_sleep &mdm2ap_sleep>; |
| 724 | interrupt-map = <0 &tlmm 1 0x3 |
| 725 | 1 &tlmm 3 0x3>; |
| 726 | qcom,mdm2ap-errfatal-gpio = <&tlmm 1 0x00>; |
| 727 | qcom,ap2mdm-errfatal-gpio = <&tlmm 57 0x00>; |
| 728 | qcom,mdm2ap-status-gpio = <&tlmm 3 0x00>; |
| 729 | qcom,ap2mdm-status-gpio = <&tlmm 56 0x00>; |
Rishabh Bhatnagar | 2b66dc1 | 2018-10-18 10:36:27 -0700 | [diff] [blame] | 730 | qcom,ap2mdm-soft-reset-gpio = <&tlmm 145 GPIO_ACTIVE_LOW>; |
Rishabh Bhatnagar | 19ddb35e | 2018-09-18 15:53:03 -0700 | [diff] [blame] | 731 | qcom,mdm-link-info = "0306_02.01.00"; |
| 732 | status = "ok"; |
| 733 | }; |
| 734 | |
Lina Iyer | 8551c79 | 2018-06-21 16:06:53 -0600 | [diff] [blame] | 735 | pdc: interrupt-controller@b220000 { |
| 736 | compatible = "qcom,kona-pdc"; |
| 737 | reg = <0xb220000 0x30000>; |
| 738 | qcom,pdc-ranges = <0 480 29>, <42 522 52>, <94 609 30>; |
| 739 | #interrupt-cells = <2>; |
| 740 | interrupt-parent = <&intc>; |
| 741 | interrupt-controller; |
| 742 | }; |
| 743 | |
David Collins | a6d833b | 2018-09-25 14:44:32 -0700 | [diff] [blame] | 744 | clock_xo: bi_tcxo { |
| 745 | compatible = "fixed-clock"; |
| 746 | #clock-cells = <0>; |
| 747 | clock-frequency = <19200000>; |
| 748 | clock-output-names = "bi_tcxo"; |
| 749 | }; |
| 750 | |
Vivek Aknurwar | 65bafd9 | 2018-11-01 17:27:53 -0700 | [diff] [blame] | 751 | clocks { |
| 752 | sleep_clk: sleep-clk { |
| 753 | compatible = "fixed-clock"; |
| 754 | clock-frequency = <32000>; |
| 755 | clock-output-names = "chip_sleep_clk"; |
| 756 | #clock-cells = <1>; |
| 757 | }; |
| 758 | }; |
| 759 | |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 760 | clock_rpmh: qcom,rpmhclk { |
| 761 | compatible = "qcom,dummycc"; |
| 762 | clock-output-names = "rpmh_clocks"; |
| 763 | #clock-cells = <1>; |
| 764 | }; |
| 765 | |
| 766 | clock_aop: qcom,aopclk { |
| 767 | compatible = "qcom,dummycc"; |
| 768 | clock-output-names = "qdss_clocks"; |
| 769 | #clock-cells = <1>; |
| 770 | }; |
| 771 | |
Vivek Aknurwar | 7e9ecb9 | 2018-09-07 14:27:58 -0700 | [diff] [blame] | 772 | clock_gcc: qcom,gcc@100000 { |
David Dai | 7e431ad | 2018-12-05 15:37:39 -0800 | [diff] [blame] | 773 | compatible = "qcom,gcc-kona", "syscon"; |
Vivek Aknurwar | 7e9ecb9 | 2018-09-07 14:27:58 -0700 | [diff] [blame] | 774 | reg = <0x100000 0x1f0000>; |
| 775 | reg-names = "cc_base"; |
| 776 | vdd_cx-supply = <&VDD_CX_LEVEL>; |
| 777 | vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; |
| 778 | vdd_mm-supply = <&VDD_MMCX_LEVEL>; |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 779 | #clock-cells = <1>; |
| 780 | #reset-cells = <1>; |
| 781 | }; |
| 782 | |
| 783 | clock_npucc: qcom,npucc { |
| 784 | compatible = "qcom,dummycc"; |
| 785 | clock-output-names = "npucc_clocks"; |
| 786 | #clock-cells = <1>; |
| 787 | #reset-cells = <1>; |
| 788 | }; |
| 789 | |
Vivek Aknurwar | 65bafd9 | 2018-11-01 17:27:53 -0700 | [diff] [blame] | 790 | clock_videocc: qcom,videocc@abf0000 { |
| 791 | compatible = "qcom,videocc-kona", "syscon"; |
| 792 | reg = <0xabf0000 0x10000>; |
| 793 | reg-names = "cc_base"; |
| 794 | vdd_mx-supply = <&VDD_MX_LEVEL>; |
| 795 | vdd_mm-supply = <&VDD_MMCX_LEVEL>; |
| 796 | clock-names = "cfg_ahb_clk"; |
| 797 | clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 798 | #clock-cells = <1>; |
| 799 | #reset-cells = <1>; |
| 800 | }; |
| 801 | |
Vivek Aknurwar | 86452c0 | 2018-11-05 15:20:31 -0800 | [diff] [blame] | 802 | clock_camcc: qcom,camcc@ad00000 { |
| 803 | compatible = "qcom,camcc-kona", "syscon"; |
| 804 | reg = <0xad00000 0x10000>; |
| 805 | reg-names = "cc_base"; |
| 806 | vdd_mx-supply = <&VDD_MX_LEVEL>; |
| 807 | vdd_mm-supply = <&VDD_MMCX_LEVEL>; |
| 808 | clock-names = "cfg_ahb_clk"; |
| 809 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 810 | #clock-cells = <1>; |
| 811 | #reset-cells = <1>; |
| 812 | }; |
| 813 | |
David Dai | dc93e48 | 2018-11-27 17:32:50 -0800 | [diff] [blame] | 814 | clock_dispcc: qcom,dispcc@af00000 { |
David Dai | 7e431ad | 2018-12-05 15:37:39 -0800 | [diff] [blame] | 815 | compatible = "qcom,kona-dispcc", "syscon"; |
David Dai | dc93e48 | 2018-11-27 17:32:50 -0800 | [diff] [blame] | 816 | reg = <0xaf00000 0x20000>; |
| 817 | reg-names = "cc_base"; |
| 818 | vdd_mm-supply = <&VDD_MMCX_LEVEL>; |
| 819 | clock-names = "cfg_ahb_clk"; |
| 820 | clocks = <&clock_gcc GCC_DISP_AHB_CLK>; |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 821 | #clock-cells = <1>; |
| 822 | #reset-cells = <1>; |
| 823 | }; |
| 824 | |
Vivek Aknurwar | 31c2e0f2 | 2018-11-16 17:10:12 -0800 | [diff] [blame] | 825 | clock_gpucc: qcom,gpucc@3d90000 { |
| 826 | compatible = "qcom,gpucc-kona", "syscon"; |
| 827 | reg = <0x3d90000 0x9000>; |
| 828 | reg-names = "cc_base"; |
| 829 | vdd_cx-supply = <&VDD_CX_LEVEL>; |
| 830 | vdd_mx-supply = <&VDD_MX_LEVEL>; |
Deepak Katragadda | 5bbf814 | 2018-06-20 16:12:13 -0700 | [diff] [blame] | 831 | #clock-cells = <1>; |
| 832 | #reset-cells = <1>; |
| 833 | }; |
| 834 | |
| 835 | clock_cpucc: qcom,cpucc { |
| 836 | compatible = "qcom,dummycc"; |
| 837 | clock-output-names = "cpucc_clocks"; |
| 838 | #clock-cells = <1>; |
| 839 | }; |
Raghavendra Rao Ananta | 0295796 | 2018-08-06 15:28:34 -0700 | [diff] [blame] | 840 | |
David Dai | 7e431ad | 2018-12-05 15:37:39 -0800 | [diff] [blame] | 841 | clock_debugcc: qcom,cc-debug { |
| 842 | compatible = "qcom,kona-debugcc"; |
| 843 | qcom,gcc = <&clock_gcc>; |
| 844 | qcom,videocc = <&clock_videocc>; |
| 845 | qcom,dispcc = <&clock_dispcc>; |
| 846 | qcom,camcc = <&clock_camcc>; |
| 847 | qcom,gpucc = <&clock_gpucc>; |
| 848 | clock-names = "xo_clk_src"; |
| 849 | clocks = <&clock_xo>; |
| 850 | #clock-cells = <1>; |
| 851 | }; |
| 852 | |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 853 | /* GCC GDSCs */ |
| 854 | pcie_0_gdsc: qcom,gdsc@16b004 { |
| 855 | compatible = "qcom,gdsc"; |
| 856 | reg = <0x16b004 0x4>; |
| 857 | regulator-name = "pcie_0_gdsc"; |
| 858 | }; |
| 859 | |
| 860 | pcie_1_gdsc: qcom,gdsc@18d004 { |
| 861 | compatible = "qcom,gdsc"; |
| 862 | reg = <0x18d004 0x4>; |
| 863 | regulator-name = "pcie_1_gdsc"; |
| 864 | }; |
| 865 | |
| 866 | pcie_2_gdsc: qcom,gdsc@106004 { |
| 867 | compatible = "qcom,gdsc"; |
| 868 | reg = <0x106004 0x4>; |
| 869 | regulator-name = "pcie_2_gdsc"; |
| 870 | }; |
| 871 | |
| 872 | ufs_card_gdsc: qcom,gdsc@175004 { |
| 873 | compatible = "qcom,gdsc"; |
| 874 | reg = <0x175004 0x4>; |
| 875 | regulator-name = "ufs_card_gdsc"; |
| 876 | }; |
| 877 | |
| 878 | ufs_phy_gdsc: qcom,gdsc@177004 { |
| 879 | compatible = "qcom,gdsc"; |
| 880 | reg = <0x177004 0x4>; |
| 881 | regulator-name = "ufs_phy_gdsc"; |
| 882 | }; |
| 883 | |
| 884 | usb30_prim_gdsc: qcom,gdsc@10f004 { |
| 885 | compatible = "qcom,gdsc"; |
| 886 | reg = <0x10f004 0x4>; |
| 887 | regulator-name = "usb30_prim_gdsc"; |
| 888 | }; |
| 889 | |
| 890 | usb30_sec_gdsc: qcom,gdsc@110004 { |
| 891 | compatible = "qcom,gdsc"; |
| 892 | reg = <0x110004 0x4>; |
| 893 | regulator-name = "usb30_sec_gdsc"; |
| 894 | }; |
| 895 | |
| 896 | hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 { |
| 897 | compatible = "qcom,gdsc"; |
| 898 | reg = <0x17d050 0x4>; |
| 899 | regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; |
| 900 | qcom,no-status-check-on-disable; |
| 901 | qcom,gds-timeout = <500>; |
| 902 | }; |
| 903 | |
| 904 | hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 { |
| 905 | compatible = "qcom,gdsc"; |
| 906 | reg = <0x17d058 0x4>; |
| 907 | regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc"; |
| 908 | qcom,no-status-check-on-disable; |
| 909 | qcom,gds-timeout = <500>; |
| 910 | }; |
| 911 | |
| 912 | hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@17d054 { |
| 913 | compatible = "qcom,gdsc"; |
| 914 | reg = <0x17d054 0x4>; |
| 915 | regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc"; |
| 916 | qcom,no-status-check-on-disable; |
| 917 | qcom,gds-timeout = <500>; |
| 918 | }; |
| 919 | |
| 920 | hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc: qcom,gdsc@17d06c { |
| 921 | compatible = "qcom,gdsc"; |
| 922 | reg = <0x17d06c 0x4>; |
| 923 | regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc"; |
| 924 | qcom,no-status-check-on-disable; |
| 925 | qcom,gds-timeout = <500>; |
| 926 | }; |
| 927 | |
| 928 | /* CAM_CC GDSCs */ |
| 929 | bps_gdsc: qcom,gdsc@ad07004 { |
| 930 | compatible = "qcom,gdsc"; |
| 931 | reg = <0xad07004 0x4>; |
| 932 | regulator-name = "bps_gdsc"; |
| 933 | clock-names = "ahb_clk"; |
| 934 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| 935 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 936 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 937 | qcom,support-hw-trigger; |
| 938 | }; |
| 939 | |
| 940 | ife_0_gdsc: qcom,gdsc@ad0a004 { |
| 941 | compatible = "qcom,gdsc"; |
| 942 | reg = <0xad0a004 0x4>; |
| 943 | regulator-name = "ife_0_gdsc"; |
| 944 | clock-names = "ahb_clk"; |
| 945 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| 946 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 947 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 948 | }; |
| 949 | |
| 950 | ife_1_gdsc: qcom,gdsc@ad0b004 { |
| 951 | compatible = "qcom,gdsc"; |
| 952 | reg = <0xad0b004 0x4>; |
| 953 | regulator-name = "ife_1_gdsc"; |
| 954 | clock-names = "ahb_clk"; |
| 955 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| 956 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 957 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 958 | }; |
| 959 | |
| 960 | ipe_0_gdsc: qcom,gdsc@ad08004 { |
| 961 | compatible = "qcom,gdsc"; |
| 962 | reg = <0xad08004 0x4>; |
| 963 | regulator-name = "ipe_0_gdsc"; |
| 964 | clock-names = "ahb_clk"; |
| 965 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| 966 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 967 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 968 | qcom,support-hw-trigger; |
| 969 | }; |
| 970 | |
| 971 | sbi_gdsc: qcom,gdsc@ad09004 { |
| 972 | compatible = "qcom,gdsc"; |
| 973 | reg = <0xad09004 0x4>; |
| 974 | regulator-name = "sbi_gdsc"; |
| 975 | clock-names = "ahb_clk"; |
| 976 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| 977 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 978 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 979 | }; |
| 980 | |
| 981 | titan_top_gdsc: qcom,gdsc@ad0c144 { |
| 982 | compatible = "qcom,gdsc"; |
| 983 | reg = <0xad0c144 0x4>; |
| 984 | regulator-name = "titan_top_gdsc"; |
| 985 | clock-names = "ahb_clk"; |
| 986 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| 987 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 988 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 989 | }; |
| 990 | |
| 991 | /* DISP_CC GDSC */ |
| 992 | mdss_core_gdsc: qcom,gdsc@af03000 { |
| 993 | compatible = "qcom,gdsc"; |
| 994 | reg = <0xaf03000 0x4>; |
| 995 | regulator-name = "mdss_core_gdsc"; |
| 996 | clock-names = "ahb_clk"; |
| 997 | clocks = <&clock_gcc GCC_DISP_AHB_CLK>; |
| 998 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 999 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 1000 | qcom,support-hw-trigger; |
| 1001 | }; |
| 1002 | |
| 1003 | /* GPU_CC GDSCs */ |
| 1004 | gpu_cx_hw_ctrl: syscon@3d91540 { |
| 1005 | compatible = "syscon"; |
| 1006 | reg = <0x3d91540 0x4>; |
| 1007 | }; |
| 1008 | |
| 1009 | gpu_cx_gdsc: qcom,gdsc@3d9106c { |
| 1010 | compatible = "qcom,gdsc"; |
| 1011 | reg = <0x3d9106c 0x4>; |
| 1012 | regulator-name = "gpu_cx_gdsc"; |
| 1013 | hw-ctrl-addr = <&gpu_cx_hw_ctrl>; |
| 1014 | parent-supply = <&VDD_CX_LEVEL>; |
| 1015 | qcom,no-status-check-on-disable; |
| 1016 | qcom,clk-dis-wait-val = <8>; |
| 1017 | qcom,gds-timeout = <500>; |
| 1018 | }; |
| 1019 | |
David Collins | d7eea14 | 2018-10-08 17:32:48 -0700 | [diff] [blame] | 1020 | gpu_gx_domain_addr: syscon@3d91508 { |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1021 | compatible = "syscon"; |
| 1022 | reg = <0x3d91508 0x4>; |
| 1023 | }; |
| 1024 | |
David Collins | d7eea14 | 2018-10-08 17:32:48 -0700 | [diff] [blame] | 1025 | gpu_gx_sw_reset: syscon@3d91008 { |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1026 | compatible = "syscon"; |
| 1027 | reg = <0x3d91008 0x4>; |
| 1028 | }; |
| 1029 | |
| 1030 | gpu_gx_gdsc: qcom,gdsc@3d9100c { |
| 1031 | compatible = "qcom,gdsc"; |
| 1032 | reg = <0x3d9100c 0x4>; |
| 1033 | regulator-name = "gpu_gx_gdsc"; |
| 1034 | domain-addr = <&gpu_gx_domain_addr>; |
| 1035 | sw-reset = <&gpu_gx_sw_reset>; |
| 1036 | parent-supply = <&VDD_GFX_LEVEL>; |
| 1037 | vdd_parent-supply = <&VDD_GFX_LEVEL>; |
| 1038 | qcom,reset-aon-logic; |
| 1039 | }; |
| 1040 | |
| 1041 | /* NPU GDSC */ |
| 1042 | npu_core_gdsc: qcom,gdsc@9981004 { |
| 1043 | compatible = "qcom,gdsc"; |
| 1044 | reg = <0x9981004 0x4>; |
| 1045 | regulator-name = "npu_core_gdsc"; |
| 1046 | clock-names = "ahb_clk"; |
| 1047 | clocks = <&clock_gcc GCC_NPU_CFG_AHB_CLK>; |
| 1048 | }; |
| 1049 | |
Jishnu Prakash | 793bf5b | 2018-11-09 16:28:55 +0530 | [diff] [blame] | 1050 | qcom,sps { |
| 1051 | compatible = "qcom,msm-sps-4k"; |
| 1052 | qcom,pipe-attr-ee; |
| 1053 | }; |
| 1054 | |
David Collins | a86302c | 2018-09-17 14:16:50 -0700 | [diff] [blame] | 1055 | /* VIDEO_CC GDSCs */ |
| 1056 | mvs0_gdsc: qcom,gdsc@abf0d18 { |
| 1057 | compatible = "qcom,gdsc"; |
| 1058 | reg = <0xabf0d18 0x4>; |
| 1059 | regulator-name = "mvs0_gdsc"; |
| 1060 | clock-names = "ahb_clk"; |
| 1061 | clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; |
| 1062 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 1063 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 1064 | }; |
| 1065 | |
| 1066 | mvs0c_gdsc: qcom,gdsc@abf0bf8 { |
| 1067 | compatible = "qcom,gdsc"; |
| 1068 | reg = <0xabf0bf8 0x4>; |
| 1069 | regulator-name = "mvs0c_gdsc"; |
| 1070 | clock-names = "ahb_clk"; |
| 1071 | clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; |
| 1072 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 1073 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 1074 | }; |
| 1075 | |
| 1076 | mvs1_gdsc: qcom,gdsc@abf0d98 { |
| 1077 | compatible = "qcom,gdsc"; |
| 1078 | reg = <0xabf0d98 0x4>; |
| 1079 | regulator-name = "mvs1_gdsc"; |
| 1080 | clock-names = "ahb_clk"; |
| 1081 | clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; |
| 1082 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 1083 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 1084 | }; |
| 1085 | |
| 1086 | mvs1c_gdsc: qcom,gdsc@abf0c98 { |
| 1087 | compatible = "qcom,gdsc"; |
| 1088 | reg = <0xabf0c98 0x4>; |
| 1089 | regulator-name = "mvs1c_gdsc"; |
| 1090 | clock-names = "ahb_clk"; |
| 1091 | clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; |
| 1092 | parent-supply = <&VDD_MMCX_LEVEL>; |
| 1093 | vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| 1094 | }; |
| 1095 | |
David Collins | c2c02f6 | 2018-11-05 16:23:24 -0800 | [diff] [blame] | 1096 | spmi_bus: qcom,spmi@c440000 { |
| 1097 | compatible = "qcom,spmi-pmic-arb"; |
| 1098 | reg = <0xc440000 0x1100>, |
| 1099 | <0xc600000 0x2000000>, |
| 1100 | <0xe600000 0x100000>, |
| 1101 | <0xe700000 0xa0000>, |
| 1102 | <0xc40a000 0x26000>; |
| 1103 | reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
| 1104 | interrupt-names = "periph_irq"; |
| 1105 | interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; |
| 1106 | qcom,ee = <0>; |
| 1107 | qcom,channel = <0>; |
| 1108 | #address-cells = <2>; |
| 1109 | #size-cells = <0>; |
| 1110 | interrupt-controller; |
| 1111 | #interrupt-cells = <4>; |
| 1112 | cell-index = <0>; |
| 1113 | }; |
| 1114 | |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 1115 | ufsphy_mem: ufsphy_mem@1d87000 { |
| 1116 | reg = <0x1d87000 0xe00>; /* PHY regs */ |
| 1117 | reg-names = "phy_mem"; |
| 1118 | #phy-cells = <0>; |
| 1119 | |
| 1120 | lanes-per-direction = <2>; |
| 1121 | |
| 1122 | clock-names = "ref_clk_src", |
| 1123 | "ref_clk", |
| 1124 | "ref_aux_clk"; |
| 1125 | clocks = <&clock_rpmh RPMH_CXO_CLK>, |
Vivek Aknurwar | ec5c93d | 2018-08-28 14:52:33 -0700 | [diff] [blame] | 1126 | <&clock_gcc GCC_UFS_1X_CLKREF_EN>, |
Can Guo | b04bed5 | 2018-07-10 19:27:32 -0700 | [diff] [blame] | 1127 | <&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>; |
| 1128 | |
| 1129 | status = "disabled"; |
| 1130 | }; |
| 1131 | |
| 1132 | ufshc_mem: ufshc@1d84000 { |
| 1133 | compatible = "qcom,ufshc"; |
| 1134 | reg = <0x1d84000 0x3000>; |
| 1135 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; |
| 1136 | phys = <&ufsphy_mem>; |
| 1137 | phy-names = "ufsphy"; |
| 1138 | |
| 1139 | lanes-per-direction = <2>; |
| 1140 | dev-ref-clk-freq = <0>; /* 19.2 MHz */ |
| 1141 | |
| 1142 | clock-names = |
| 1143 | "core_clk", |
| 1144 | "bus_aggr_clk", |
| 1145 | "iface_clk", |
| 1146 | "core_clk_unipro", |
| 1147 | "core_clk_ice", |
| 1148 | "ref_clk", |
| 1149 | "tx_lane0_sync_clk", |
| 1150 | "rx_lane0_sync_clk", |
| 1151 | "rx_lane1_sync_clk"; |
| 1152 | clocks = |
| 1153 | <&clock_gcc GCC_UFS_PHY_AXI_CLK>, |
| 1154 | <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, |
| 1155 | <&clock_gcc GCC_UFS_PHY_AHB_CLK>, |
| 1156 | <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, |
| 1157 | <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>, |
| 1158 | <&clock_rpmh RPMH_CXO_CLK>, |
| 1159 | <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, |
| 1160 | <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, |
| 1161 | <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; |
| 1162 | freq-table-hz = |
| 1163 | <37500000 300000000>, |
| 1164 | <0 0>, |
| 1165 | <0 0>, |
| 1166 | <37500000 300000000>, |
| 1167 | <75000000 300000000>, |
| 1168 | <0 0>, |
| 1169 | <0 0>, |
| 1170 | <0 0>, |
| 1171 | <0 0>; |
| 1172 | |
| 1173 | qcom,msm-bus,name = "ufshc_mem"; |
| 1174 | qcom,msm-bus,num-cases = <22>; |
| 1175 | qcom,msm-bus,num-paths = <2>; |
| 1176 | qcom,msm-bus,vectors-KBps = |
| 1177 | /* |
| 1178 | * During HS G3 UFS runs at nominal voltage corner, vote |
| 1179 | * higher bandwidth to push other buses in the data path |
| 1180 | * to run at nominal to achieve max throughput. |
| 1181 | * 4GBps pushes BIMC to run at nominal. |
| 1182 | * 200MBps pushes CNOC to run at nominal. |
| 1183 | * Vote for half of this bandwidth for HS G3 1-lane. |
| 1184 | * For max bandwidth, vote high enough to push the buses |
| 1185 | * to run in turbo voltage corner. |
| 1186 | */ |
| 1187 | <123 512 0 0>, <1 757 0 0>, /* No vote */ |
| 1188 | <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */ |
| 1189 | <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */ |
| 1190 | <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */ |
| 1191 | <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */ |
| 1192 | <123 512 1844 0>, <1 757 1000 0>, /* PWM G1 L2 */ |
| 1193 | <123 512 3688 0>, <1 757 1000 0>, /* PWM G2 L2 */ |
| 1194 | <123 512 7376 0>, <1 757 1000 0>, /* PWM G3 L2 */ |
| 1195 | <123 512 14752 0>, <1 757 1000 0>, /* PWM G4 L2 */ |
| 1196 | <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */ |
| 1197 | <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */ |
| 1198 | <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */ |
| 1199 | <123 512 255591 0>, <1 757 1000 0>, /* HS G1 RA L2 */ |
| 1200 | <123 512 511181 0>, <1 757 1000 0>, /* HS G2 RA L2 */ |
| 1201 | <123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */ |
| 1202 | <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */ |
| 1203 | <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */ |
| 1204 | <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */ |
| 1205 | <123 512 298189 0>, <1 757 1000 0>, /* HS G1 RB L2 */ |
| 1206 | <123 512 596378 0>, <1 757 1000 0>, /* HS G2 RB L2 */ |
| 1207 | /* As UFS working in HS G3 RB L2 mode, aggregated |
| 1208 | * bandwidth (AB) should take care of providing |
| 1209 | * optimum throughput requested. However, as tested, |
| 1210 | * in order to scale up CNOC clock, instantaneous |
| 1211 | * bindwidth (IB) needs to be given a proper value too. |
| 1212 | */ |
| 1213 | <123 512 4194304 0>, <1 757 204800 409600>, /* HS G3 RB L2 */ |
| 1214 | <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */ |
| 1215 | |
| 1216 | qcom,bus-vector-names = "MIN", |
| 1217 | "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", |
| 1218 | "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", |
| 1219 | "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", |
| 1220 | "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", |
| 1221 | "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", |
| 1222 | "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", |
| 1223 | "MAX"; |
| 1224 | |
| 1225 | /* PM QoS */ |
| 1226 | qcom,pm-qos-cpu-groups = <0x0f 0xf0>; |
| 1227 | qcom,pm-qos-cpu-group-latency-us = <44 44>; |
| 1228 | qcom,pm-qos-default-cpu = <0>; |
| 1229 | |
| 1230 | pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; |
| 1231 | pinctrl-0 = <&ufs_dev_reset_assert>; |
| 1232 | pinctrl-1 = <&ufs_dev_reset_deassert>; |
| 1233 | |
| 1234 | resets = <&clock_gcc GCC_UFS_PHY_BCR>; |
| 1235 | reset-names = "core_reset"; |
| 1236 | |
| 1237 | status = "disabled"; |
| 1238 | }; |
| 1239 | |
Raghavendra Rao Ananta | 0295796 | 2018-08-06 15:28:34 -0700 | [diff] [blame] | 1240 | ipcc_mproc: qcom,ipcc@408000 { |
| 1241 | compatible = "qcom,kona-ipcc"; |
| 1242 | reg = <0x408000 0x1000>; |
| 1243 | interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; |
| 1244 | interrupt-controller; |
| 1245 | #interrupt-cells = <3>; |
| 1246 | #mbox-cells = <2>; |
| 1247 | }; |
Lina Iyer | ea91c72 | 2018-06-20 14:58:05 -0600 | [diff] [blame] | 1248 | |
Raghavendra Rao Ananta | 5da54b3 | 2018-08-09 10:04:50 -0700 | [diff] [blame] | 1249 | ipcc_self_ping: ipcc-self-ping { |
| 1250 | compatible = "qcom,ipcc-self-ping"; |
| 1251 | interrupts-extended = <&ipcc_mproc IPCC_CLIENT_APSS |
| 1252 | IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_LEVEL_HIGH>; |
| 1253 | mboxes = <&ipcc_mproc IPCC_CLIENT_APSS IPCC_MPROC_SIGNAL_SMP2P>; |
| 1254 | }; |
| 1255 | |
Maria Neptune | 5a1428b | 2018-08-29 13:25:19 -0700 | [diff] [blame] | 1256 | apps_rsc: rsc@18200000 { |
Lina Iyer | ea91c72 | 2018-06-20 14:58:05 -0600 | [diff] [blame] | 1257 | label = "apps_rsc"; |
| 1258 | compatible = "qcom,rpmh-rsc"; |
| 1259 | reg = <0x18200000 0x10000>, |
| 1260 | <0x18210000 0x10000>, |
| 1261 | <0x18220000 0x10000>; |
| 1262 | reg-names = "drv-0", "drv-1", "drv-2"; |
| 1263 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
| 1264 | <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
| 1265 | <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| 1266 | qcom,tcs-offset = <0xd00>; |
| 1267 | qcom,drv-id = <2>; |
| 1268 | qcom,tcs-config = <ACTIVE_TCS 2>, |
| 1269 | <SLEEP_TCS 3>, |
| 1270 | <WAKE_TCS 3>, |
| 1271 | <CONTROL_TCS 1>; |
David Dai | 07c8d4e | 2018-10-09 14:22:06 -0700 | [diff] [blame] | 1272 | |
| 1273 | msm_bus_apps_rsc { |
| 1274 | compatible = "qcom,msm-bus-rsc"; |
| 1275 | qcom,msm-bus-id = <MSM_BUS_RSC_APPS>; |
| 1276 | }; |
Arjun Bagla | 76f02ef | 2018-09-19 10:00:29 -0700 | [diff] [blame] | 1277 | |
| 1278 | system_pm { |
| 1279 | compatible = "qcom,system-pm"; |
| 1280 | }; |
Lina Iyer | ea91c72 | 2018-06-20 14:58:05 -0600 | [diff] [blame] | 1281 | }; |
| 1282 | |
| 1283 | disp_rsc: rsc@af20000 { |
| 1284 | label = "disp_rsc"; |
| 1285 | compatible = "qcom,rpmh-rsc"; |
| 1286 | reg = <0xaf20000 0x10000>; |
| 1287 | reg-names = "drv-0"; |
| 1288 | interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; |
| 1289 | qcom,tcs-offset = <0x1c00>; |
| 1290 | qcom,drv-id = <0>; |
| 1291 | qcom,tcs-config = <ACTIVE_TCS 0>, |
| 1292 | <SLEEP_TCS 1>, |
| 1293 | <WAKE_TCS 1>, |
| 1294 | <CONTROL_TCS 0>; |
| 1295 | status = "disabled"; |
Dhaval Patel | f92536a | 2018-10-24 13:19:15 -0700 | [diff] [blame] | 1296 | |
| 1297 | sde_rsc_rpmh { |
| 1298 | compatible = "qcom,sde-rsc-rpmh"; |
| 1299 | cell-index = <0>; |
| 1300 | status = "disabled"; |
| 1301 | }; |
Lina Iyer | ea91c72 | 2018-06-20 14:58:05 -0600 | [diff] [blame] | 1302 | }; |
Chris Lew | 86f6bde | 2018-09-06 16:40:39 -0700 | [diff] [blame] | 1303 | |
| 1304 | tcsr_mutex_block: syscon@1f40000 { |
| 1305 | compatible = "syscon"; |
| 1306 | reg = <0x1f40000 0x20000>; |
| 1307 | }; |
| 1308 | |
| 1309 | tcsr_mutex: hwlock { |
| 1310 | compatible = "qcom,tcsr-mutex"; |
| 1311 | syscon = <&tcsr_mutex_block 0 0x1000>; |
| 1312 | #hwlock-cells = <1>; |
| 1313 | }; |
| 1314 | |
| 1315 | smem: qcom,smem { |
| 1316 | compatible = "qcom,smem"; |
| 1317 | memory-region = <&smem_mem>; |
| 1318 | hwlocks = <&tcsr_mutex 3>; |
| 1319 | }; |
Venkata Narendra Kumar Gutta | 1781e56 | 2018-10-09 14:44:10 -0700 | [diff] [blame] | 1320 | |
| 1321 | kryo-erp { |
| 1322 | compatible = "arm,arm64-kryo-cpu-erp"; |
| 1323 | interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 1324 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| 1325 | interrupt-names = "l1-l2-faultirq", |
| 1326 | "l3-scu-faultirq"; |
| 1327 | }; |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 1328 | |
Chris Lew | 3b1f098 | 2018-10-05 17:28:21 -0700 | [diff] [blame] | 1329 | sp_scsr: mailbox@188501c { |
| 1330 | compatible = "qcom,kona-spcs-global"; |
| 1331 | reg = <0x188501c 0x4>; |
| 1332 | |
| 1333 | #mbox-cells = <1>; |
| 1334 | }; |
| 1335 | |
| 1336 | sp_scsr_block: syscon@1880000 { |
| 1337 | compatible = "syscon"; |
| 1338 | reg = <0x1880000 0x10000>; |
| 1339 | }; |
| 1340 | |
| 1341 | intsp: qcom,qsee_irq { |
| 1342 | compatible = "qcom,kona-qsee-irq"; |
| 1343 | |
| 1344 | syscon = <&sp_scsr_block>; |
| 1345 | interrupts = <0 348 IRQ_TYPE_LEVEL_HIGH>, |
| 1346 | <0 349 IRQ_TYPE_LEVEL_HIGH>; |
| 1347 | |
| 1348 | interrupt-names = "sp_ipc0", |
| 1349 | "sp_ipc1"; |
| 1350 | |
| 1351 | interrupt-controller; |
| 1352 | #interrupt-cells = <3>; |
| 1353 | }; |
| 1354 | |
| 1355 | qcom,qsee_irq_bridge { |
| 1356 | compatible = "qcom,qsee-ipc-irq-bridge"; |
| 1357 | |
| 1358 | qcom,qsee-ipc-irq-spss { |
| 1359 | qcom,dev-name = "qsee_ipc_irq_spss"; |
| 1360 | label = "spss"; |
| 1361 | interrupt-parent = <&intsp>; |
| 1362 | interrupts = <1 0 IRQ_TYPE_LEVEL_HIGH>; |
| 1363 | }; |
| 1364 | }; |
| 1365 | |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 1366 | qcom,msm_gsi { |
| 1367 | compatible = "qcom,msm_gsi"; |
| 1368 | }; |
| 1369 | |
| 1370 | qcom,rmnet-ipa { |
| 1371 | compatible = "qcom,rmnet-ipa3"; |
| 1372 | qcom,rmnet-ipa-ssr; |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 1373 | qcom,ipa-advertise-sg-support; |
| 1374 | qcom,ipa-napi-enable; |
| 1375 | }; |
| 1376 | |
| 1377 | qcom,ipa_fws { |
| 1378 | compatible = "qcom,pil-tz-generic"; |
| 1379 | qcom,pas-id = <0xf>; |
| 1380 | qcom,firmware-name = "ipa_fws"; |
| 1381 | qcom,pil-force-shutdown; |
| 1382 | memory-region = <&pil_ipa_fw_mem>; |
| 1383 | }; |
| 1384 | |
| 1385 | ipa_hw: qcom,ipa@1e00000 { |
| 1386 | compatible = "qcom,ipa"; |
| 1387 | reg = |
| 1388 | <0x1e00000 0x84000>, |
| 1389 | <0x1e04000 0x23000>; |
| 1390 | reg-names = "ipa-base", "gsi-base"; |
| 1391 | interrupts = |
| 1392 | <0 311 IRQ_TYPE_LEVEL_HIGH>, |
| 1393 | <0 432 IRQ_TYPE_LEVEL_HIGH>; |
| 1394 | interrupt-names = "ipa-irq", "gsi-irq"; |
| 1395 | qcom,ipa-hw-ver = <17>; /* IPA core version = IPAv4.5 */ |
| 1396 | qcom,ipa-hw-mode = <0>; |
Ghanim Fodi | f8dcdbf | 2018-11-04 17:58:22 +0200 | [diff] [blame] | 1397 | qcom,platform-type = <2>; /* APQ platform */ |
Ghanim Fodi | 180e5aa | 2018-11-01 19:45:45 +0200 | [diff] [blame] | 1398 | qcom,ee = <0>; |
| 1399 | qcom,use-ipa-tethering-bridge; |
| 1400 | qcom,mhi-event-ring-id-limits = <9 11>; /* start and end */ |
| 1401 | qcom,modem-cfg-emb-pipe-flt; |
| 1402 | qcom,use-ipa-pm; |
| 1403 | qcom,bandwidth-vote-for-ipa; |
| 1404 | qcom,use-64-bit-dma-mask; |
| 1405 | qcom,msm-bus,name = "ipa"; |
| 1406 | qcom,msm-bus,num-cases = <5>; |
| 1407 | qcom,msm-bus,num-paths = <4>; |
| 1408 | qcom,msm-bus,vectors-KBps = |
| 1409 | /* No vote */ |
| 1410 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| 1411 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 0 0>, |
| 1412 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 0>, |
| 1413 | <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 0>, |
| 1414 | |
| 1415 | /* SVS2 */ |
| 1416 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 80000 600000>, |
| 1417 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 80000 350000>, |
| 1418 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 40000 40000>, |
| 1419 | <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 125>, |
| 1420 | |
| 1421 | /* SVS */ |
| 1422 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 80000 640000>, |
| 1423 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 80000 640000>, |
| 1424 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 80000 80000>, |
| 1425 | <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 250>, |
| 1426 | |
| 1427 | /* NOMINAL */ |
| 1428 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 206000 960000>, |
| 1429 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 206000 960000>, |
| 1430 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 206000 160000>, |
| 1431 | <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 500>, |
| 1432 | |
| 1433 | /* TURBO */ |
| 1434 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 206000 3600000>, |
| 1435 | <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 206000 3600000>, |
| 1436 | <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 206000 300000>, |
| 1437 | <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 600>; |
| 1438 | |
| 1439 | qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", |
| 1440 | "TURBO"; |
| 1441 | qcom,throughput-threshold = <310 600 1000>; |
| 1442 | qcom,scaling-exceptions = <>; |
| 1443 | }; |
| 1444 | |
| 1445 | ipa_smmu_ap: ipa_smmu_ap { |
| 1446 | compatible = "qcom,ipa-smmu-ap-cb"; |
| 1447 | iommus = <&apps_smmu 0x5C0 0x0>; |
| 1448 | qcom,iommu-dma = "bypass"; |
| 1449 | }; |
| 1450 | |
| 1451 | ipa_smmu_wlan: ipa_smmu_wlan { |
| 1452 | compatible = "qcom,ipa-smmu-wlan-cb"; |
| 1453 | iommus = <&apps_smmu 0x5C1 0x0>; |
| 1454 | qcom,iommu-dma = "bypass"; |
| 1455 | }; |
| 1456 | |
| 1457 | ipa_smmu_uc: ipa_smmu_uc { |
| 1458 | compatible = "qcom,ipa-smmu-uc-cb"; |
| 1459 | iommus = <&apps_smmu 0x5C2 0x0>; |
| 1460 | qcom,iommu-dma = "bypass"; |
| 1461 | }; |
| 1462 | |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 1463 | qcom,glink { |
| 1464 | compatible = "qcom,glink"; |
| 1465 | #address-cells = <1>; |
| 1466 | #size-cells = <1>; |
| 1467 | ranges; |
| 1468 | |
Chris Lew | b2da048 | 2018-11-16 14:50:31 -0800 | [diff] [blame] | 1469 | glink_npu: npu { |
| 1470 | qcom,remote-pid = <10>; |
| 1471 | transport = "smem"; |
| 1472 | mboxes = <&ipcc_mproc IPCC_CLIENT_NPU |
| 1473 | IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| 1474 | mbox-names = "npu_smem"; |
| 1475 | interrupt-parent = <&ipcc_mproc>; |
| 1476 | interrupts = <IPCC_CLIENT_NPU |
| 1477 | IPCC_MPROC_SIGNAL_GLINK_QMP |
| 1478 | IRQ_TYPE_EDGE_RISING>; |
| 1479 | |
| 1480 | label = "npu"; |
| 1481 | qcom,glink-label = "npu"; |
| 1482 | |
| 1483 | qcom,npu_qrtr { |
Chris Lew | c386112 | 2018-12-14 18:26:01 -0800 | [diff] [blame] | 1484 | qcom,net-id = <1>; |
Chris Lew | b2da048 | 2018-11-16 14:50:31 -0800 | [diff] [blame] | 1485 | qcom,glink-channels = "IPCRTR"; |
| 1486 | qcom,intents = <0x800 5 |
| 1487 | 0x2000 3 |
| 1488 | 0x4400 2>; |
| 1489 | }; |
| 1490 | |
| 1491 | qcom,npu_glink_ssr { |
| 1492 | qcom,glink-channels = "glink_ssr"; |
| 1493 | qcom,notify-edges = <&glink_cdsp>; |
| 1494 | }; |
| 1495 | }; |
| 1496 | |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 1497 | glink_adsp: adsp { |
| 1498 | qcom,remote-pid = <2>; |
| 1499 | transport = "smem"; |
| 1500 | mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS |
| 1501 | IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| 1502 | mbox-names = "adsp_smem"; |
| 1503 | interrupt-parent = <&ipcc_mproc>; |
| 1504 | interrupts = <IPCC_CLIENT_LPASS |
| 1505 | IPCC_MPROC_SIGNAL_GLINK_QMP |
| 1506 | IRQ_TYPE_EDGE_RISING>; |
| 1507 | |
| 1508 | label = "adsp"; |
| 1509 | qcom,glink-label = "lpass"; |
| 1510 | |
| 1511 | qcom,adsp_qrtr { |
Chris Lew | c386112 | 2018-12-14 18:26:01 -0800 | [diff] [blame] | 1512 | qcom,net-id = <2>; |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 1513 | qcom,glink-channels = "IPCRTR"; |
| 1514 | qcom,intents = <0x800 5 |
| 1515 | 0x2000 3 |
| 1516 | 0x4400 2>; |
| 1517 | }; |
| 1518 | |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1519 | qcom,msm_fastrpc_rpmsg { |
| 1520 | compatible = "qcom,msm-fastrpc-rpmsg"; |
| 1521 | qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| 1522 | qcom,intents = <0x64 64>; |
| 1523 | }; |
| 1524 | |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 1525 | qcom,adsp_glink_ssr { |
| 1526 | qcom,glink-channels = "glink_ssr"; |
| 1527 | qcom,notify-edges = <&glink_slpi>, |
| 1528 | <&glink_cdsp>; |
| 1529 | }; |
| 1530 | }; |
| 1531 | |
| 1532 | glink_slpi: dsps { |
| 1533 | qcom,remote-pid = <3>; |
| 1534 | transport = "smem"; |
| 1535 | mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI |
| 1536 | IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| 1537 | mbox-names = "dsps_smem"; |
| 1538 | interrupt-parent = <&ipcc_mproc>; |
| 1539 | interrupts = <IPCC_CLIENT_SLPI |
| 1540 | IPCC_MPROC_SIGNAL_GLINK_QMP |
| 1541 | IRQ_TYPE_EDGE_RISING>; |
| 1542 | |
| 1543 | label = "slpi"; |
| 1544 | qcom,glink-label = "dsps"; |
| 1545 | |
| 1546 | qcom,slpi_qrtr { |
Chris Lew | c386112 | 2018-12-14 18:26:01 -0800 | [diff] [blame] | 1547 | qcom,net-id = <2>; |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 1548 | qcom,glink-channels = "IPCRTR"; |
| 1549 | qcom,intents = <0x800 5 |
| 1550 | 0x2000 3 |
| 1551 | 0x4400 2>; |
| 1552 | }; |
| 1553 | |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1554 | qcom,msm_fastrpc_rpmsg { |
| 1555 | compatible = "qcom,msm-fastrpc-rpmsg"; |
| 1556 | qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| 1557 | qcom,intents = <0x64 64>; |
| 1558 | }; |
| 1559 | |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 1560 | qcom,slpi_glink_ssr { |
| 1561 | qcom,glink-channels = "glink_ssr"; |
| 1562 | qcom,notify-edges = <&glink_adsp>, |
| 1563 | <&glink_cdsp>; |
| 1564 | }; |
| 1565 | }; |
| 1566 | |
| 1567 | glink_cdsp: cdsp { |
| 1568 | qcom,remote-pid = <5>; |
| 1569 | transport = "smem"; |
| 1570 | mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP |
| 1571 | IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| 1572 | mbox-names = "dsps_smem"; |
| 1573 | interrupt-parent = <&ipcc_mproc>; |
| 1574 | interrupts = <IPCC_CLIENT_CDSP |
| 1575 | IPCC_MPROC_SIGNAL_GLINK_QMP |
| 1576 | IRQ_TYPE_EDGE_RISING>; |
| 1577 | |
| 1578 | label = "cdsp"; |
| 1579 | qcom,glink-label = "cdsp"; |
| 1580 | |
| 1581 | qcom,cdsp_qrtr { |
Chris Lew | c386112 | 2018-12-14 18:26:01 -0800 | [diff] [blame] | 1582 | qcom,net-id = <1>; |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 1583 | qcom,glink-channels = "IPCRTR"; |
| 1584 | qcom,intents = <0x800 5 |
| 1585 | 0x2000 3 |
| 1586 | 0x4400 2>; |
| 1587 | }; |
| 1588 | |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1589 | qcom,msm_fastrpc_rpmsg { |
| 1590 | compatible = "qcom,msm-fastrpc-rpmsg"; |
| 1591 | qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| 1592 | qcom,intents = <0x64 64>; |
| 1593 | }; |
| 1594 | |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 1595 | qcom,cdsp_glink_ssr { |
| 1596 | qcom,glink-channels = "glink_ssr"; |
| 1597 | qcom,notify-edges = <&glink_adsp>, |
Chris Lew | b2da048 | 2018-11-16 14:50:31 -0800 | [diff] [blame] | 1598 | <&glink_slpi>, |
| 1599 | <&glink_npu>; |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 1600 | }; |
| 1601 | }; |
Chris Lew | 3b1f098 | 2018-10-05 17:28:21 -0700 | [diff] [blame] | 1602 | |
| 1603 | glink_spss: spss { |
| 1604 | qcom,remote-pid = <8>; |
| 1605 | transport = "spss"; |
| 1606 | mboxes = <&sp_scsr 0>; |
| 1607 | mbox-names = "spss_spss"; |
| 1608 | interrupt-parent = <&intsp>; |
| 1609 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; |
| 1610 | |
| 1611 | reg = <0x1885008 0x8>, |
| 1612 | <0x1885010 0x4>; |
| 1613 | reg-names = "qcom,spss-addr", |
| 1614 | "qcom,spss-size"; |
| 1615 | |
| 1616 | label = "spss"; |
| 1617 | qcom,glink-label = "spss"; |
| 1618 | }; |
Chris Lew | 3859b1b7 | 2018-09-25 16:54:52 -0700 | [diff] [blame] | 1619 | }; |
Bruce Levy | 5122a63 | 2018-09-25 15:51:37 -0700 | [diff] [blame] | 1620 | |
Chris Lew | 3cbe403 | 2018-11-30 18:57:32 -0800 | [diff] [blame] | 1621 | qmp_aop: qcom,qmp-aop@c300000 { |
| 1622 | compatible = "qcom,qmp-mbox"; |
| 1623 | mboxes = <&ipcc_mproc IPCC_CLIENT_AOP |
| 1624 | IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| 1625 | mbox-names = "aop_qmp"; |
| 1626 | interrupt-parent = <&ipcc_mproc>; |
| 1627 | interrupts = <IPCC_CLIENT_AOP |
| 1628 | IPCC_MPROC_SIGNAL_GLINK_QMP |
| 1629 | IRQ_TYPE_EDGE_RISING>; |
| 1630 | reg = <0xc300000 0x1000>; |
| 1631 | reg-names = "msgram"; |
| 1632 | |
| 1633 | label = "aop"; |
| 1634 | qcom,early-boot; |
| 1635 | priority = <0>; |
| 1636 | mbox-desc-offset = <0x0>; |
| 1637 | #mbox-cells = <1>; |
| 1638 | }; |
| 1639 | |
Bruce Levy | 5122a63 | 2018-09-25 15:51:37 -0700 | [diff] [blame] | 1640 | qcom,lpass@17300000 { |
| 1641 | compatible = "qcom,pil-tz-generic"; |
| 1642 | reg = <0x17300000 0x00100>; |
| 1643 | |
| 1644 | vdd_cx-supply = <&VDD_CX_LEVEL>; |
| 1645 | qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>; |
| 1646 | qcom,proxy-reg-names = "vdd_cx"; |
| 1647 | |
| 1648 | clocks = <&clock_rpmh RPMH_CXO_CLK>; |
| 1649 | clock-names = "xo"; |
| 1650 | qcom,proxy-clock-names = "xo"; |
| 1651 | |
| 1652 | qcom,pas-id = <1>; |
| 1653 | qcom,proxy-timeout-ms = <10000>; |
| 1654 | qcom,smem-id = <423>; |
| 1655 | qcom,sysmon-id = <1>; |
| 1656 | qcom,ssctl-instance-id = <0x14>; |
| 1657 | qcom,firmware-name = "adsp"; |
| 1658 | memory-region = <&pil_adsp_mem>; |
| 1659 | qcom,complete-ramdump; |
| 1660 | |
| 1661 | /* Inputs from lpass */ |
| 1662 | interrupts-extended = <&pdc 96 IRQ_TYPE_LEVEL_HIGH>, |
| 1663 | <&adsp_smp2p_in 0 0>, |
| 1664 | <&adsp_smp2p_in 2 0>, |
| 1665 | <&adsp_smp2p_in 1 0>, |
| 1666 | <&adsp_smp2p_in 3 0>; |
| 1667 | |
| 1668 | interrupt-names = "qcom,wdog", |
| 1669 | "qcom,err-fatal", |
| 1670 | "qcom,proxy-unvote", |
| 1671 | "qcom,err-ready", |
| 1672 | "qcom,stop-ack"; |
| 1673 | |
| 1674 | /* Outputs to lpass */ |
| 1675 | qcom,smem-states = <&adsp_smp2p_out 0>; |
| 1676 | qcom,smem-state-names = "qcom,force-stop"; |
| 1677 | |
| 1678 | mbox-names = "adsp-pil"; |
| 1679 | }; |
| 1680 | |
| 1681 | qcom,turing@8300000 { |
| 1682 | compatible = "qcom,pil-tz-generic"; |
| 1683 | reg = <0x8300000 0x100000>; |
| 1684 | |
| 1685 | vdd_cx-supply = <&VDD_CX_LEVEL>; |
| 1686 | qcom,proxy-reg-names = "vdd_cx"; |
| 1687 | qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>; |
| 1688 | |
| 1689 | clocks = <&clock_rpmh RPMH_CXO_CLK>; |
| 1690 | clock-names = "xo"; |
| 1691 | qcom,proxy-clock-names = "xo"; |
| 1692 | |
| 1693 | qcom,pas-id = <18>; |
| 1694 | qcom,proxy-timeout-ms = <10000>; |
| 1695 | qcom,smem-id = <601>; |
| 1696 | qcom,sysmon-id = <7>; |
| 1697 | qcom,ssctl-instance-id = <0x17>; |
| 1698 | qcom,firmware-name = "cdsp"; |
| 1699 | memory-region = <&pil_cdsp_mem>; |
| 1700 | qcom,complete-ramdump; |
| 1701 | |
| 1702 | qcom,msm-bus,name = "pil-cdsp"; |
| 1703 | qcom,msm-bus,num-cases = <2>; |
| 1704 | qcom,msm-bus,num-paths = <1>; |
| 1705 | qcom,msm-bus,vectors-KBps = |
| 1706 | <154 10070 0 0>, |
| 1707 | <154 10070 0 1>; |
| 1708 | |
| 1709 | /* Inputs from turing */ |
Bruce Levy | 821133c | 2018-11-29 11:34:45 -0800 | [diff] [blame] | 1710 | interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, |
Bruce Levy | 5122a63 | 2018-09-25 15:51:37 -0700 | [diff] [blame] | 1711 | <&cdsp_smp2p_in 0 0>, |
| 1712 | <&cdsp_smp2p_in 2 0>, |
| 1713 | <&cdsp_smp2p_in 1 0>, |
| 1714 | <&cdsp_smp2p_in 3 0>; |
| 1715 | |
| 1716 | interrupt-names = "qcom,wdog", |
| 1717 | "qcom,err-fatal", |
| 1718 | "qcom,proxy-unvote", |
| 1719 | "qcom,err-ready", |
| 1720 | "qcom,stop-ack"; |
| 1721 | |
| 1722 | /* Outputs to turing */ |
| 1723 | qcom,smem-states = <&cdsp_smp2p_out 0>; |
| 1724 | qcom,smem-state-names = "qcom,force-stop"; |
| 1725 | |
| 1726 | mbox-names = "cdsp-pil"; |
| 1727 | }; |
Akshay Chandrashekhar Kalghatgi | f7905ad | 2018-11-08 16:30:42 -0800 | [diff] [blame] | 1728 | |
| 1729 | qcom,venus@aab0000 { |
| 1730 | compatible = "qcom,pil-tz-generic"; |
| 1731 | reg = <0xaab0000 0x2000>; |
Chinmay Sawarkar | 2cfeca0 | 2018-11-15 17:59:36 -0800 | [diff] [blame] | 1732 | |
| 1733 | vdd-supply = <&mvs0c_gdsc>; |
| 1734 | qcom,proxy-reg-names = "vdd"; |
| 1735 | qcom,complete-ramdump; |
| 1736 | |
| 1737 | clocks = <&clock_videocc VIDEO_CC_XO_CLK>, |
| 1738 | <&clock_videocc VIDEO_CC_MVS0C_CLK>, |
| 1739 | <&clock_videocc VIDEO_CC_AHB_CLK>; |
| 1740 | clock-names = "xo", "core", "ahb"; |
| 1741 | qcom,proxy-clock-names = "xo", "core", "ahb"; |
| 1742 | |
Akshay Chandrashekhar Kalghatgi | f7905ad | 2018-11-08 16:30:42 -0800 | [diff] [blame] | 1743 | qcom,core-freq = <200000000>; |
| 1744 | qcom,ahb-freq = <200000000>; |
| 1745 | |
| 1746 | qcom,pas-id = <9>; |
| 1747 | qcom,msm-bus,name = "pil-venus"; |
| 1748 | qcom,msm-bus,num-cases = <2>; |
| 1749 | qcom,msm-bus,num-paths = <1>; |
| 1750 | qcom,msm-bus,vectors-KBps = |
| 1751 | <63 512 0 0>, |
| 1752 | <63 512 0 304000>; |
| 1753 | qcom,proxy-timeout-ms = <100>; |
| 1754 | qcom,firmware-name = "venus"; |
| 1755 | memory-region = <&pil_video_mem>; |
| 1756 | }; |
Tharun Kumar Merugu | b8d79dd | 2018-11-02 23:07:31 +0530 | [diff] [blame] | 1757 | |
Amir Samuelov | f52db41 | 2019-01-08 09:30:58 +0200 | [diff] [blame] | 1758 | /* PIL spss node - for loading Secure Processor */ |
| 1759 | qcom,spss@1880000 { |
| 1760 | compatible = "qcom,pil-tz-generic"; |
| 1761 | reg = <0x188101c 0x4>, |
| 1762 | <0x1881024 0x4>, |
| 1763 | <0x1881028 0x4>, |
| 1764 | <0x188103c 0x4>, |
| 1765 | <0x1882014 0x4>; |
| 1766 | reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", |
| 1767 | "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2"; |
| 1768 | interrupts = <0 352 1>; |
| 1769 | |
| 1770 | vdd_cx-supply = <&VDD_CX_LEVEL>; |
| 1771 | qcom,proxy-reg-names = "vdd_cx"; |
| 1772 | qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>; |
| 1773 | vdd_mx-supply = <&VDD_MX_LEVEL>; |
| 1774 | vdd_mx-uV = <RPMH_REGULATOR_LEVEL_TURBO 100000>; |
| 1775 | |
| 1776 | clocks = <&clock_rpmh RPMH_CXO_CLK>; |
| 1777 | clock-names = "xo"; |
| 1778 | qcom,proxy-clock-names = "xo"; |
| 1779 | qcom,pil-generic-irq-handler; |
| 1780 | status = "ok"; |
| 1781 | |
| 1782 | qcom,complete-ramdump; |
| 1783 | |
| 1784 | qcom,pas-id = <14>; |
| 1785 | qcom,proxy-timeout-ms = <10000>; |
| 1786 | qcom,firmware-name = "spss"; |
| 1787 | memory-region = <&pil_spss_mem>; |
| 1788 | qcom,spss-scsr-bits = <24 25>; |
| 1789 | |
| 1790 | mbox-names = "spss-pil"; |
| 1791 | }; |
| 1792 | |
George Shen | 9c54c66 | 2018-12-26 15:50:11 -0800 | [diff] [blame] | 1793 | qcom,cvpss@abb0000 { |
| 1794 | compatible = "qcom,pil-tz-generic"; |
| 1795 | reg = <0xabb0000 0x2000>; |
| 1796 | status = "ok"; |
| 1797 | qcom,pas-id = <25>; |
| 1798 | qcom,firmware-name = "cvpss"; |
| 1799 | |
| 1800 | memory-region = <&pil_cvp_mem>; |
| 1801 | }; |
| 1802 | |
Jilai Wang | d20a529 | 2018-12-04 11:05:10 -0500 | [diff] [blame] | 1803 | qcom,npu@9800000 { |
| 1804 | compatible = "qcom,pil-tz-generic"; |
| 1805 | reg = <0x9800000 0x800000>; |
| 1806 | |
| 1807 | status = "ok"; |
| 1808 | qcom,pas-id = <23>; |
| 1809 | qcom,firmware-name = "npu"; |
| 1810 | memory-region = <&pil_npu_mem>; |
| 1811 | }; |
| 1812 | |
Tharun Kumar Merugu | b8d79dd | 2018-11-02 23:07:31 +0530 | [diff] [blame] | 1813 | qcom,msm-cdsp-loader { |
| 1814 | compatible = "qcom,cdsp-loader"; |
| 1815 | qcom,proc-img-to-load = "cdsp"; |
| 1816 | }; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1817 | |
| 1818 | qcom,msm-adsprpc-mem { |
| 1819 | compatible = "qcom,msm-adsprpc-mem-region"; |
| 1820 | memory-region = <&adsp_mem>; |
| 1821 | }; |
| 1822 | |
| 1823 | msm_fastrpc: qcom,msm_fastrpc { |
| 1824 | compatible = "qcom,msm-fastrpc-compute"; |
| 1825 | qcom,fastrpc-adsp-audio-pdr; |
| 1826 | qcom,rpc-latency-us = <235>; |
| 1827 | |
| 1828 | qcom,msm_fastrpc_compute_cb1 { |
| 1829 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1830 | label = "cdsprpc-smd"; |
| 1831 | iommus = <&apps_smmu 0x1001 0x0460>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1832 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1833 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1834 | dma-coherent; |
| 1835 | }; |
| 1836 | |
| 1837 | qcom,msm_fastrpc_compute_cb2 { |
| 1838 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1839 | label = "cdsprpc-smd"; |
| 1840 | iommus = <&apps_smmu 0x1002 0x0460>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1841 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1842 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1843 | dma-coherent; |
| 1844 | }; |
| 1845 | |
| 1846 | qcom,msm_fastrpc_compute_cb3 { |
| 1847 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1848 | label = "cdsprpc-smd"; |
| 1849 | iommus = <&apps_smmu 0x1003 0x0460>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1850 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1851 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1852 | dma-coherent; |
| 1853 | }; |
| 1854 | |
| 1855 | qcom,msm_fastrpc_compute_cb4 { |
| 1856 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1857 | label = "cdsprpc-smd"; |
| 1858 | iommus = <&apps_smmu 0x1004 0x0460>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1859 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1860 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1861 | dma-coherent; |
| 1862 | }; |
| 1863 | |
| 1864 | qcom,msm_fastrpc_compute_cb5 { |
| 1865 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1866 | label = "cdsprpc-smd"; |
| 1867 | iommus = <&apps_smmu 0x1005 0x0460>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1868 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1869 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1870 | dma-coherent; |
| 1871 | }; |
| 1872 | |
| 1873 | qcom,msm_fastrpc_compute_cb6 { |
| 1874 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1875 | label = "cdsprpc-smd"; |
| 1876 | iommus = <&apps_smmu 0x1006 0x0460>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1877 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1878 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1879 | dma-coherent; |
| 1880 | }; |
| 1881 | |
| 1882 | qcom,msm_fastrpc_compute_cb7 { |
| 1883 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1884 | label = "cdsprpc-smd"; |
| 1885 | iommus = <&apps_smmu 0x1007 0x0460>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1886 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1887 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1888 | dma-coherent; |
| 1889 | }; |
| 1890 | |
| 1891 | qcom,msm_fastrpc_compute_cb8 { |
| 1892 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1893 | label = "cdsprpc-smd"; |
| 1894 | iommus = <&apps_smmu 0x1008 0x0460>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1895 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1896 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1897 | dma-coherent; |
| 1898 | }; |
| 1899 | |
| 1900 | qcom,msm_fastrpc_compute_cb9 { |
| 1901 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1902 | label = "cdsprpc-smd"; |
| 1903 | qcom,secure-context-bank; |
| 1904 | iommus = <&apps_smmu 0x1009 0x0460>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1905 | dma-ranges = <0x60000000 0x60000000 0x78000000>; |
| 1906 | qcom,iommu-faults = "stall-disable"; |
| 1907 | qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1908 | dma-coherent; |
| 1909 | }; |
| 1910 | |
| 1911 | qcom,msm_fastrpc_compute_cb10 { |
| 1912 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1913 | label = "adsprpc-smd"; |
| 1914 | iommus = <&apps_smmu 0x1803 0x0>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1915 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1916 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1917 | dma-coherent; |
| 1918 | }; |
| 1919 | |
| 1920 | qcom,msm_fastrpc_compute_cb11 { |
| 1921 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1922 | label = "adsprpc-smd"; |
| 1923 | iommus = <&apps_smmu 0x1804 0x0>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1924 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1925 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1926 | dma-coherent; |
| 1927 | }; |
| 1928 | |
| 1929 | qcom,msm_fastrpc_compute_cb12 { |
| 1930 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1931 | label = "adsprpc-smd"; |
| 1932 | iommus = <&apps_smmu 0x1805 0x0>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1933 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1934 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1935 | dma-coherent; |
| 1936 | }; |
| 1937 | |
| 1938 | qcom,msm_fastrpc_compute_cb13 { |
| 1939 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1940 | label = "sdsprpc-smd"; |
| 1941 | iommus = <&apps_smmu 0x0541 0x0>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1942 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1943 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1944 | dma-coherent; |
| 1945 | }; |
| 1946 | |
| 1947 | qcom,msm_fastrpc_compute_cb14 { |
| 1948 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1949 | label = "sdsprpc-smd"; |
| 1950 | iommus = <&apps_smmu 0x0542 0x0>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1951 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1952 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1953 | dma-coherent; |
| 1954 | }; |
| 1955 | |
| 1956 | qcom,msm_fastrpc_compute_cb15 { |
| 1957 | compatible = "qcom,msm-fastrpc-compute-cb"; |
| 1958 | label = "sdsprpc-smd"; |
| 1959 | iommus = <&apps_smmu 0x0543 0x0>; |
Tharun Kumar Merugu | af4c92f | 2018-11-16 05:12:16 +0530 | [diff] [blame] | 1960 | dma-ranges = <0x80000000 0x80000000 0x78000000>; |
| 1961 | qcom,iommu-faults = "stall-disable"; |
Tharun Kumar Merugu | 027438b | 2018-11-09 03:24:57 +0530 | [diff] [blame] | 1962 | shared-cb = <4>; |
| 1963 | dma-coherent; |
| 1964 | }; |
| 1965 | }; |
Shaikh Shadul | bfdfdda | 2018-11-14 15:36:21 +0530 | [diff] [blame] | 1966 | |
Tingwei Zhang | d9b535f | 2018-12-03 19:14:06 -0800 | [diff] [blame] | 1967 | mem_dump { |
| 1968 | compatible = "qcom,mem-dump"; |
| 1969 | memory-region = <&dump_mem>; |
| 1970 | |
| 1971 | rpmh { |
| 1972 | qcom,dump-size = <0x2000000>; |
| 1973 | qcom,dump-id = <0xec>; |
| 1974 | }; |
| 1975 | |
| 1976 | rpm_sw { |
| 1977 | qcom,dump-size = <0x28000>; |
| 1978 | qcom,dump-id = <0xea>; |
| 1979 | }; |
| 1980 | |
| 1981 | pmic { |
| 1982 | qcom,dump-size = <0x80000>; |
| 1983 | qcom,dump-id = <0xe4>; |
| 1984 | }; |
| 1985 | |
| 1986 | fcm { |
| 1987 | qcom,dump-size = <0x8400>; |
| 1988 | qcom,dump-id = <0xee>; |
| 1989 | }; |
| 1990 | |
| 1991 | etf_swao { |
| 1992 | qcom,dump-size = <0x10000>; |
| 1993 | qcom,dump-id = <0xf1>; |
| 1994 | }; |
| 1995 | |
| 1996 | etr_reg { |
| 1997 | qcom,dump-size = <0x1000>; |
| 1998 | qcom,dump-id = <0x100>; |
| 1999 | }; |
| 2000 | |
| 2001 | etfswao_reg { |
| 2002 | qcom,dump-size = <0x1000>; |
| 2003 | qcom,dump-id = <0x102>; |
| 2004 | }; |
| 2005 | |
| 2006 | misc_data { |
| 2007 | qcom,dump-size = <0x1000>; |
| 2008 | qcom,dump-id = <0xe8>; |
| 2009 | }; |
| 2010 | }; |
| 2011 | |
Shaikh Shadul | bfdfdda | 2018-11-14 15:36:21 +0530 | [diff] [blame] | 2012 | qcom,ssc@5c00000 { |
| 2013 | compatible = "qcom,pil-tz-generic"; |
| 2014 | reg = <0x5c00000 0x4000>; |
| 2015 | |
| 2016 | vdd_cx-supply = <&VDD_CX_LEVEL>; |
| 2017 | qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>; |
| 2018 | vdd_mx-supply = <&VDD_MX_LEVEL>; |
| 2019 | qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>; |
| 2020 | |
| 2021 | qcom,proxy-reg-names = "vdd_cx", "vdd_mx"; |
| 2022 | qcom,keep-proxy-regs-on; |
| 2023 | |
| 2024 | clocks = <&clock_rpmh RPMH_CXO_CLK>; |
| 2025 | clock-names = "xo"; |
| 2026 | qcom,proxy-clock-names = "xo"; |
| 2027 | |
| 2028 | qcom,pas-id = <12>; |
| 2029 | qcom,proxy-timeout-ms = <10000>; |
| 2030 | qcom,smem-id = <424>; |
| 2031 | qcom,sysmon-id = <3>; |
| 2032 | qcom,ssctl-instance-id = <0x16>; |
| 2033 | qcom,firmware-name = "slpi"; |
| 2034 | status = "ok"; |
| 2035 | memory-region = <&pil_slpi_mem>; |
| 2036 | qcom,complete-ramdump; |
| 2037 | |
| 2038 | /* Inputs from ssc */ |
| 2039 | interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, |
| 2040 | <&dsps_smp2p_in 0 0>, |
| 2041 | <&dsps_smp2p_in 2 0>, |
| 2042 | <&dsps_smp2p_in 1 0>, |
| 2043 | <&dsps_smp2p_in 3 0>; |
| 2044 | |
| 2045 | interrupt-names = "qcom,wdog", |
| 2046 | "qcom,err-fatal", |
| 2047 | "qcom,proxy-unvote", |
| 2048 | "qcom,err-ready", |
| 2049 | "qcom,stop-ack"; |
| 2050 | |
| 2051 | /* Outputs to ssc */ |
| 2052 | qcom,smem-states = <&dsps_smp2p_out 0>; |
| 2053 | qcom,smem-state-names = "qcom,force-stop"; |
| 2054 | |
| 2055 | mbox-names = "slpi-pil"; |
| 2056 | }; |
| 2057 | |
| 2058 | ssc_sensors: qcom,msm-ssc-sensors { |
| 2059 | compatible = "qcom,msm-ssc-sensors"; |
| 2060 | status = "ok"; |
| 2061 | qcom,firmware-name = "slpi"; |
| 2062 | }; |
Siddartha Mohanadoss | 42c8d78 | 2018-12-21 14:20:33 -0800 | [diff] [blame] | 2063 | |
| 2064 | tsens0: tsens@c222000 { |
| 2065 | compatible = "qcom,tsens24xx"; |
| 2066 | reg = <0xc222000 0x4>, |
| 2067 | <0xc263000 0x1ff>; |
| 2068 | reg-names = "tsens_srot_physical", |
| 2069 | "tsens_tm_physical"; |
Siddartha Mohanadoss | 404a89a | 2019-01-04 15:29:48 -0800 | [diff] [blame] | 2070 | interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, |
| 2071 | <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; |
Siddartha Mohanadoss | 42c8d78 | 2018-12-21 14:20:33 -0800 | [diff] [blame] | 2072 | interrupt-names = "tsens-upper-lower", "tsens-critical"; |
| 2073 | #thermal-sensor-cells = <1>; |
| 2074 | }; |
| 2075 | |
| 2076 | tsens1: tsens@c223000 { |
| 2077 | compatible = "qcom,tsens24xx"; |
| 2078 | reg = <0xc223000 0x4>, |
| 2079 | <0xc265000 0x1ff>; |
| 2080 | reg-names = "tsens_srot_physical", |
| 2081 | "tsens_tm_physical"; |
Siddartha Mohanadoss | 404a89a | 2019-01-04 15:29:48 -0800 | [diff] [blame] | 2082 | interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, |
| 2083 | <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; |
Siddartha Mohanadoss | 42c8d78 | 2018-12-21 14:20:33 -0800 | [diff] [blame] | 2084 | interrupt-names = "tsens-upper-lower", "tsens-critical"; |
| 2085 | #thermal-sensor-cells = <1>; |
| 2086 | }; |
Runmin Wang | 4f5985b | 2017-04-19 15:55:12 -0700 | [diff] [blame] | 2087 | }; |
Swathi Sridhar | 4008eb4 | 2018-07-17 15:34:46 -0700 | [diff] [blame] | 2088 | |
David Dai | b1d6848 | 2018-10-01 19:40:35 -0700 | [diff] [blame] | 2089 | #include "kona-bus.dtsi" |
Swathi Sridhar | bbbc80b | 2018-07-13 10:02:08 -0700 | [diff] [blame] | 2090 | #include "kona-ion.dtsi" |
Tony Truong | c972c64 | 2018-09-12 10:03:51 -0700 | [diff] [blame] | 2091 | #include "kona-pcie.dtsi" |
Sujeev Dias | 5399e55 | 2018-09-18 17:57:54 -0700 | [diff] [blame] | 2092 | #include "kona-mhi.dtsi" |
Swathi Sridhar | 4008eb4 | 2018-07-17 15:34:46 -0700 | [diff] [blame] | 2093 | #include "msm-arm-smmu-kona.dtsi" |
Rishabh Bhatnagar | a740b0e | 2018-07-20 15:08:35 -0700 | [diff] [blame] | 2094 | #include "kona-pinctrl.dtsi" |
Chris Lew | 86f6bde | 2018-09-06 16:40:39 -0700 | [diff] [blame] | 2095 | #include "kona-smp2p.dtsi" |
Hemant Kumar | 5f58bad | 2018-08-31 14:25:23 -0700 | [diff] [blame] | 2096 | #include "kona-usb.dtsi" |
Tingwei Zhang | 564fa69 | 2018-11-28 00:31:17 -0800 | [diff] [blame] | 2097 | #include "kona-coresight.dtsi" |
Samantha Tran | 7e309f0 | 2018-08-31 17:23:00 -0700 | [diff] [blame] | 2098 | #include "kona-sde.dtsi" |
Satya Rama Aditya Pinapala | 09600b3 | 2018-10-29 10:52:37 -0700 | [diff] [blame] | 2099 | #include "kona-sde-pll.dtsi" |
Samantha Tran | 7e309f0 | 2018-08-31 17:23:00 -0700 | [diff] [blame] | 2100 | #include "kona-sde-display.dtsi" |
Vignesh Kulothungan | d728f71 | 2018-10-26 17:49:46 -0700 | [diff] [blame] | 2101 | #include "kona-audio.dtsi" |
Mukund Atre | d454ec9 | 2018-11-05 15:32:16 -0800 | [diff] [blame] | 2102 | |
Arjun Bagla | 76f02ef | 2018-09-19 10:00:29 -0700 | [diff] [blame] | 2103 | #include "kona-pm.dtsi" |
Mukund Atre | d454ec9 | 2018-11-05 15:32:16 -0800 | [diff] [blame] | 2104 | |
| 2105 | #include "kona-camera.dtsi" |
Vipin Deep Kaur | 9a2c13d | 2018-12-19 18:38:46 +0530 | [diff] [blame] | 2106 | #include "kona-qupv3.dtsi" |
Siddartha Mohanadoss | 42c8d78 | 2018-12-21 14:20:33 -0800 | [diff] [blame] | 2107 | #include "kona-thermal.dtsi" |
Chinmay Sawarkar | 83d01b4 | 2018-12-14 12:34:50 -0800 | [diff] [blame] | 2108 | #include "kona-vidc.dtsi" |
George Shen | 9c54c66 | 2018-12-26 15:50:11 -0800 | [diff] [blame] | 2109 | #include "kona-cvp.dtsi" |