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Tony Lindgren1dbae812005-11-10 14:26:51 +00001/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
Santosh Shilimkar44169072009-05-28 14:16:04 -07007 * Copyright (C) 2007-2009 Texas Instruments
Tony Lindgren646e3ed2008-10-06 15:49:36 +03008 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
Tony Lindgren1dbae812005-11-10 14:26:51 +000012 *
Santosh Shilimkar44169072009-05-28 14:16:04 -070013 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
Tony Lindgren1dbae812005-11-10 14:26:51 +000015 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
Tony Lindgren1dbae812005-11-10 14:26:51 +000019#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
Russell Kingfced80c2008-09-06 12:10:45 +010022#include <linux/io.h>
Paul Walmsley2f135ea2009-06-19 19:08:25 -060023#include <linux/clk.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000024
Tony Lindgren120db2c2006-04-02 17:46:27 +010025#include <asm/tlb.h>
Tony Lindgren120db2c2006-04-02 17:46:27 +010026#include <asm/mach/map.h>
27
Tony Lindgren45c3eb72012-11-30 08:41:50 -080028#include <linux/omap-dma.h>
Tony Lindgren646e3ed2008-10-06 15:49:36 +030029
Tony Lindgrendc843282012-10-03 11:23:43 -070030#include "omap_hwmod.h"
Tony Lindgrendbc04162012-08-31 10:59:07 -070031#include "soc.h"
Tony Lindgrenee0839c2012-02-24 10:34:35 -080032#include "iomap.h"
33#include "voltage.h"
34#include "powerdomain.h"
35#include "clockdomain.h"
36#include "common.h"
Vaibhav Hiremathe30384a2012-05-29 15:26:41 +053037#include "clock.h"
Paul Walmsleye80a9722010-01-26 20:13:12 -070038#include "clock2xxx.h"
Paul Walmsley657ebfa2010-02-22 22:09:20 -070039#include "clock3xxx.h"
Tony Lindgren1d5aef42012-10-03 16:36:40 -070040#include "omap-pm.h"
Paul Walmsley3e6ece12012-10-17 00:46:45 +000041#include "sdrc.h"
Paul Walmsleyb6a42262012-10-29 20:50:21 -060042#include "control.h"
Tony Lindgren3d82cbb2012-10-15 12:50:46 -070043#include "serial.h"
Tony Lindgrenbf027ca2012-10-29 13:54:06 -070044#include "sram.h"
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -060045#include "cm2xxx.h"
46#include "cm3xxx.h"
Tero Kristo7632a022014-10-27 08:39:23 -070047#include "cm33xx.h"
Tero Kristoab6c9bb2014-10-27 08:39:25 -070048#include "cm44xx.h"
Paul Walmsleyd9a16f92012-10-29 20:57:39 -060049#include "prm.h"
50#include "cm.h"
51#include "prcm_mpu44xx.h"
52#include "prminst44xx.h"
Paul Walmsley63a293e2012-11-21 16:15:16 -070053#include "prm2xxx.h"
54#include "prm3xxx.h"
Tero Kristod9bbe842014-10-27 08:39:24 -070055#include "prm33xx.h"
Paul Walmsley63a293e2012-11-21 16:15:16 -070056#include "prm44xx.h"
Tero Kristo69a1e7a2014-02-24 18:51:05 +020057#include "opp2xxx.h"
Tony Lindgren1dbae812005-11-10 14:26:51 +000058
Tony Lindgren1dbae812005-11-10 14:26:51 +000059/*
Tero Kristocfa96672013-10-22 11:53:02 +030060 * omap_clk_soc_init: points to a function that does the SoC-specific
Rajendra Nayakff931c82013-03-21 16:34:52 +053061 * clock initializations
62 */
Tero Kristocfa96672013-10-22 11:53:02 +030063static int (*omap_clk_soc_init)(void);
Rajendra Nayakff931c82013-03-21 16:34:52 +053064
65/*
Tony Lindgren1dbae812005-11-10 14:26:51 +000066 * The machine specific code may provide the extra mapping besides the
67 * default mapping provided here.
68 */
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030069
Tony Lindgrene48f8142012-03-06 11:49:22 -080070#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030071static struct map_desc omap24xx_io_desc[] __initdata = {
Tony Lindgren1dbae812005-11-10 14:26:51 +000072 {
73 .virtual = L3_24XX_VIRT,
74 .pfn = __phys_to_pfn(L3_24XX_PHYS),
75 .length = L3_24XX_SIZE,
76 .type = MT_DEVICE
77 },
Kyungmin Park09f21ed2008-02-20 15:30:06 -080078 {
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030079 .virtual = L4_24XX_VIRT,
80 .pfn = __phys_to_pfn(L4_24XX_PHYS),
81 .length = L4_24XX_SIZE,
Syed Mohammed Khasim72d0f1c2006-12-06 17:14:05 -080082 .type = MT_DEVICE
83 },
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030084};
85
Tony Lindgren59b479e2011-01-27 16:39:40 -080086#ifdef CONFIG_SOC_OMAP2420
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030087static struct map_desc omap242x_io_desc[] __initdata = {
Tony Lindgren1dbae812005-11-10 14:26:51 +000088 {
Paul Walmsley7adb9982010-01-08 15:23:05 -070089 .virtual = DSP_MEM_2420_VIRT,
90 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
91 .length = DSP_MEM_2420_SIZE,
Tony Lindgrenc40fae952006-12-07 13:58:10 -080092 .type = MT_DEVICE
93 },
94 {
Paul Walmsley7adb9982010-01-08 15:23:05 -070095 .virtual = DSP_IPI_2420_VIRT,
96 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
97 .length = DSP_IPI_2420_SIZE,
Tony Lindgrenc40fae952006-12-07 13:58:10 -080098 .type = MT_DEVICE
99 },
100 {
Paul Walmsley7adb9982010-01-08 15:23:05 -0700101 .virtual = DSP_MMU_2420_VIRT,
102 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
103 .length = DSP_MMU_2420_SIZE,
Tony Lindgren1dbae812005-11-10 14:26:51 +0000104 .type = MT_DEVICE
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300105 },
Tony Lindgren1dbae812005-11-10 14:26:51 +0000106};
107
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300108#endif
109
Tony Lindgren59b479e2011-01-27 16:39:40 -0800110#ifdef CONFIG_SOC_OMAP2430
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300111static struct map_desc omap243x_io_desc[] __initdata = {
112 {
113 .virtual = L4_WK_243X_VIRT,
114 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
115 .length = L4_WK_243X_SIZE,
116 .type = MT_DEVICE
117 },
118 {
119 .virtual = OMAP243X_GPMC_VIRT,
120 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
121 .length = OMAP243X_GPMC_SIZE,
122 .type = MT_DEVICE
123 },
124 {
125 .virtual = OMAP243X_SDRC_VIRT,
126 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
127 .length = OMAP243X_SDRC_SIZE,
128 .type = MT_DEVICE
129 },
130 {
131 .virtual = OMAP243X_SMS_VIRT,
132 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
133 .length = OMAP243X_SMS_SIZE,
134 .type = MT_DEVICE
135 },
136};
137#endif
138#endif
139
Tony Lindgrena8eb7ca2010-02-12 12:26:48 -0800140#ifdef CONFIG_ARCH_OMAP3
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300141static struct map_desc omap34xx_io_desc[] __initdata = {
142 {
143 .virtual = L3_34XX_VIRT,
144 .pfn = __phys_to_pfn(L3_34XX_PHYS),
145 .length = L3_34XX_SIZE,
146 .type = MT_DEVICE
147 },
148 {
149 .virtual = L4_34XX_VIRT,
150 .pfn = __phys_to_pfn(L4_34XX_PHYS),
151 .length = L4_34XX_SIZE,
152 .type = MT_DEVICE
153 },
154 {
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300155 .virtual = OMAP34XX_GPMC_VIRT,
156 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
157 .length = OMAP34XX_GPMC_SIZE,
158 .type = MT_DEVICE
159 },
160 {
161 .virtual = OMAP343X_SMS_VIRT,
162 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
163 .length = OMAP343X_SMS_SIZE,
164 .type = MT_DEVICE
165 },
166 {
167 .virtual = OMAP343X_SDRC_VIRT,
168 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
169 .length = OMAP343X_SDRC_SIZE,
170 .type = MT_DEVICE
171 },
172 {
173 .virtual = L4_PER_34XX_VIRT,
174 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
175 .length = L4_PER_34XX_SIZE,
176 .type = MT_DEVICE
177 },
178 {
179 .virtual = L4_EMU_34XX_VIRT,
180 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
181 .length = L4_EMU_34XX_SIZE,
182 .type = MT_DEVICE
183 },
184};
185#endif
Hemant Pedanekar01001712011-02-16 08:31:39 -0800186
Kevin Hilman33959552012-05-10 11:10:07 -0700187#ifdef CONFIG_SOC_TI81XX
Hemant Pedanekara9203602011-12-13 10:46:44 -0800188static struct map_desc omapti81xx_io_desc[] __initdata = {
Hemant Pedanekar01001712011-02-16 08:31:39 -0800189 {
190 .virtual = L4_34XX_VIRT,
191 .pfn = __phys_to_pfn(L4_34XX_PHYS),
192 .length = L4_34XX_SIZE,
193 .type = MT_DEVICE
Afzal Mohammed1e6cb142011-12-13 10:46:43 -0800194 }
195};
196#endif
197
Afzal Mohammedaddb1542013-05-27 20:06:13 +0530198#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
Afzal Mohammed1e6cb142011-12-13 10:46:43 -0800199static struct map_desc omapam33xx_io_desc[] __initdata = {
Hemant Pedanekar01001712011-02-16 08:31:39 -0800200 {
201 .virtual = L4_34XX_VIRT,
202 .pfn = __phys_to_pfn(L4_34XX_PHYS),
203 .length = L4_34XX_SIZE,
204 .type = MT_DEVICE
205 },
Afzal Mohammed1e6cb142011-12-13 10:46:43 -0800206 {
207 .virtual = L4_WK_AM33XX_VIRT,
208 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
209 .length = L4_WK_AM33XX_SIZE,
210 .type = MT_DEVICE
211 }
Hemant Pedanekar01001712011-02-16 08:31:39 -0800212};
213#endif
214
Santosh Shilimkar44169072009-05-28 14:16:04 -0700215#ifdef CONFIG_ARCH_OMAP4
216static struct map_desc omap44xx_io_desc[] __initdata = {
217 {
218 .virtual = L3_44XX_VIRT,
219 .pfn = __phys_to_pfn(L3_44XX_PHYS),
220 .length = L3_44XX_SIZE,
221 .type = MT_DEVICE,
222 },
223 {
224 .virtual = L4_44XX_VIRT,
225 .pfn = __phys_to_pfn(L4_44XX_PHYS),
226 .length = L4_44XX_SIZE,
227 .type = MT_DEVICE,
228 },
229 {
Santosh Shilimkar44169072009-05-28 14:16:04 -0700230 .virtual = L4_PER_44XX_VIRT,
231 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
232 .length = L4_PER_44XX_SIZE,
233 .type = MT_DEVICE,
234 },
Santosh Shilimkar44169072009-05-28 14:16:04 -0700235};
236#endif
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300237
R Sricharana3a93842013-07-03 11:52:04 +0530238#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
R Sricharan05e152c2012-06-05 16:21:32 +0530239static struct map_desc omap54xx_io_desc[] __initdata = {
240 {
241 .virtual = L3_54XX_VIRT,
242 .pfn = __phys_to_pfn(L3_54XX_PHYS),
243 .length = L3_54XX_SIZE,
244 .type = MT_DEVICE,
245 },
246 {
247 .virtual = L4_54XX_VIRT,
248 .pfn = __phys_to_pfn(L4_54XX_PHYS),
249 .length = L4_54XX_SIZE,
250 .type = MT_DEVICE,
251 },
252 {
253 .virtual = L4_WK_54XX_VIRT,
254 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
255 .length = L4_WK_54XX_SIZE,
256 .type = MT_DEVICE,
257 },
258 {
259 .virtual = L4_PER_54XX_VIRT,
260 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
261 .length = L4_PER_54XX_SIZE,
262 .type = MT_DEVICE,
263 },
264};
265#endif
266
Tony Lindgren59b479e2011-01-27 16:39:40 -0800267#ifdef CONFIG_SOC_OMAP2420
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600268void __init omap242x_map_io(void)
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800269{
270 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
271 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800272}
273#endif
274
Tony Lindgren59b479e2011-01-27 16:39:40 -0800275#ifdef CONFIG_SOC_OMAP2430
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600276void __init omap243x_map_io(void)
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800277{
278 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
279 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800280}
281#endif
282
Tony Lindgrena8eb7ca2010-02-12 12:26:48 -0800283#ifdef CONFIG_ARCH_OMAP3
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600284void __init omap3_map_io(void)
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800285{
286 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800287}
288#endif
289
Kevin Hilman33959552012-05-10 11:10:07 -0700290#ifdef CONFIG_SOC_TI81XX
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600291void __init ti81xx_map_io(void)
Hemant Pedanekar01001712011-02-16 08:31:39 -0800292{
Hemant Pedanekara9203602011-12-13 10:46:44 -0800293 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
Hemant Pedanekar01001712011-02-16 08:31:39 -0800294}
295#endif
296
Afzal Mohammedaddb1542013-05-27 20:06:13 +0530297#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600298void __init am33xx_map_io(void)
Afzal Mohammed1e6cb142011-12-13 10:46:43 -0800299{
300 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800301}
302#endif
303
304#ifdef CONFIG_ARCH_OMAP4
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600305void __init omap4_map_io(void)
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800306{
307 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800308}
309#endif
310
R Sricharana3a93842013-07-03 11:52:04 +0530311#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600312void __init omap5_map_io(void)
R Sricharan05e152c2012-06-05 16:21:32 +0530313{
314 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
315}
316#endif
Paul Walmsley2f135ea2009-06-19 19:08:25 -0600317/*
318 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
319 *
320 * Sets the CORE DPLL3 M2 divider to the same value that it's at
321 * currently. This has the effect of setting the SDRC SDRAM AC timing
322 * registers to the values currently defined by the kernel. Currently
323 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
324 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
325 * or passes along the return value of clk_set_rate().
326 */
327static int __init _omap2_init_reprogram_sdrc(void)
328{
329 struct clk *dpll3_m2_ck;
330 int v = -EINVAL;
331 long rate;
332
333 if (!cpu_is_omap34xx())
334 return 0;
335
336 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
Aaro Koskinene281f7e2010-11-30 14:17:58 +0000337 if (IS_ERR(dpll3_m2_ck))
Paul Walmsley2f135ea2009-06-19 19:08:25 -0600338 return -EINVAL;
339
340 rate = clk_get_rate(dpll3_m2_ck);
341 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
342 v = clk_set_rate(dpll3_m2_ck, rate);
343 if (v)
344 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
345
346 clk_put(dpll3_m2_ck);
347
348 return v;
349}
350
Paul Walmsley2092e5c2010-12-14 12:42:35 -0700351static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
352{
353 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
354}
355
Tony Lindgren7b250af2011-10-04 18:26:28 -0700356static void __init omap_hwmod_init_postsetup(void)
Tony Lindgren120db2c2006-04-02 17:46:27 +0100357{
Paul Walmsley2092e5c2010-12-14 12:42:35 -0700358 u8 postsetup_state;
359
Paul Walmsley2092e5c2010-12-14 12:42:35 -0700360 /* Set the default postsetup state for all hwmods */
Rafael J. Wysockibf7c5442014-12-13 00:42:49 +0100361#ifdef CONFIG_PM
Paul Walmsley2092e5c2010-12-14 12:42:35 -0700362 postsetup_state = _HWMOD_STATE_IDLE;
363#else
364 postsetup_state = _HWMOD_STATE_ENABLED;
365#endif
366 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
Benoit Cousson55d2cb02010-05-12 17:54:36 +0200367
Kevin Hilman53da4ce2010-12-09 09:13:48 -0600368 omap_pm_if_early_init();
Paul Walmsley48057342010-12-21 15:25:10 -0700369}
370
Arnd Bergmann069d0a72013-07-05 16:20:17 +0200371static void __init __maybe_unused omap_common_late_init(void)
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200372{
373 omap_mux_late_init();
374 omap2_common_pm_late_init();
Ruslan Bilovol6770b212013-02-14 13:55:24 +0200375 omap_soc_device_init();
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200376}
377
Paul Walmsley16110792012-01-25 12:57:46 -0700378#ifdef CONFIG_SOC_OMAP2420
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700379void __init omap2420_init_early(void)
380{
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600381 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
382 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
383 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
Tero Kristo2208bf12014-11-13 19:17:34 +0200384 omap2_control_base_init();
Vaibhav Hiremath4de34f32011-12-19 15:50:15 +0530385 omap2xxx_check_revision();
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200386 omap2_prcm_base_init();
Tony Lindgren7b250af2011-10-04 18:26:28 -0700387 omap2xxx_voltagedomains_init();
388 omap242x_powerdomains_init();
389 omap242x_clockdomains_init();
390 omap2420_hwmod_init();
391 omap_hwmod_init_postsetup();
Tero Kristo6a194a62014-03-04 10:53:54 +0200392 omap_clk_soc_init = omap2420_dt_clk_init;
393 rate_table = omap2420_rate_table;
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700394}
Shawn Guobbd707a2012-04-26 16:06:50 +0800395
396void __init omap2420_init_late(void)
397{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200398 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800399 omap2_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530400 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800401}
Paul Walmsley16110792012-01-25 12:57:46 -0700402#endif
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700403
Paul Walmsley16110792012-01-25 12:57:46 -0700404#ifdef CONFIG_SOC_OMAP2430
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700405void __init omap2430_init_early(void)
406{
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600407 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
408 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
409 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
Tero Kristo2208bf12014-11-13 19:17:34 +0200410 omap2_control_base_init();
Vaibhav Hiremath4de34f32011-12-19 15:50:15 +0530411 omap2xxx_check_revision();
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200412 omap2_prcm_base_init();
Tony Lindgren7b250af2011-10-04 18:26:28 -0700413 omap2xxx_voltagedomains_init();
414 omap243x_powerdomains_init();
415 omap243x_clockdomains_init();
416 omap2430_hwmod_init();
417 omap_hwmod_init_postsetup();
Tero Kristo6a194a62014-03-04 10:53:54 +0200418 omap_clk_soc_init = omap2430_dt_clk_init;
419 rate_table = omap2430_rate_table;
Tony Lindgren7b250af2011-10-04 18:26:28 -0700420}
Shawn Guobbd707a2012-04-26 16:06:50 +0800421
422void __init omap2430_init_late(void)
423{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200424 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800425 omap2_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530426 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800427}
Sanjeev Premic4e2d242011-10-13 21:44:10 +0530428#endif
Tony Lindgren7b250af2011-10-04 18:26:28 -0700429
430/*
431 * Currently only board-omap3beagle.c should call this because of the
432 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
433 */
Sanjeev Premic4e2d242011-10-13 21:44:10 +0530434#ifdef CONFIG_ARCH_OMAP3
Tony Lindgren7b250af2011-10-04 18:26:28 -0700435void __init omap3_init_early(void)
436{
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600437 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
438 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
439 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
Tero Kristo2208bf12014-11-13 19:17:34 +0200440 /* XXX: remove these once OMAP3 is DT only */
441 if (!of_have_populated_dt()) {
442 omap2_set_globals_control(
Tero Kristoefde2342015-02-20 10:08:52 +0200443 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE));
Tero Kristo2208bf12014-11-13 19:17:34 +0200444 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
445 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
446 NULL);
447 }
448 omap2_control_base_init();
Vaibhav Hiremath4de34f32011-12-19 15:50:15 +0530449 omap3xxx_check_revision();
450 omap3xxx_check_features();
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200451 omap2_prcm_base_init();
Tero Kristo425dc8b2014-11-21 15:51:37 +0200452 /* XXX: remove these once OMAP3 is DT only */
453 if (!of_have_populated_dt()) {
454 omap3xxx_prm_init(NULL);
455 omap3xxx_cm_init(NULL);
456 }
Tony Lindgren7b250af2011-10-04 18:26:28 -0700457 omap3xxx_voltagedomains_init();
458 omap3xxx_powerdomains_init();
459 omap3xxx_clockdomains_init();
460 omap3xxx_hwmod_init();
461 omap_hwmod_init_postsetup();
Tero Kristoeded36f2014-12-16 18:20:55 +0200462 if (!of_have_populated_dt()) {
Tero Kristo2208bf12014-11-13 19:17:34 +0200463 omap3_control_legacy_iomap_init();
Tero Kristoeded36f2014-12-16 18:20:55 +0200464 if (soc_is_am35xx())
465 omap_clk_soc_init = am35xx_clk_legacy_init;
466 else if (cpu_is_omap3630())
467 omap_clk_soc_init = omap36xx_clk_legacy_init;
468 else if (omap_rev() == OMAP3430_REV_ES1_0)
469 omap_clk_soc_init = omap3430es1_clk_legacy_init;
470 else
471 omap_clk_soc_init = omap3430_clk_legacy_init;
472 }
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700473}
474
475void __init omap3430_init_early(void)
476{
Tony Lindgren7b250af2011-10-04 18:26:28 -0700477 omap3_init_early();
Tero Kristo3e049152013-08-02 14:32:30 +0300478 if (of_have_populated_dt())
479 omap_clk_soc_init = omap3430_dt_clk_init;
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700480}
481
482void __init omap35xx_init_early(void)
483{
Tony Lindgren7b250af2011-10-04 18:26:28 -0700484 omap3_init_early();
Tero Kristo3e049152013-08-02 14:32:30 +0300485 if (of_have_populated_dt())
486 omap_clk_soc_init = omap3430_dt_clk_init;
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700487}
488
489void __init omap3630_init_early(void)
490{
Tony Lindgren7b250af2011-10-04 18:26:28 -0700491 omap3_init_early();
Tero Kristo3e049152013-08-02 14:32:30 +0300492 if (of_have_populated_dt())
493 omap_clk_soc_init = omap3630_dt_clk_init;
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700494}
495
496void __init am35xx_init_early(void)
497{
Tony Lindgren7b250af2011-10-04 18:26:28 -0700498 omap3_init_early();
Tero Kristo3e049152013-08-02 14:32:30 +0300499 if (of_have_populated_dt())
500 omap_clk_soc_init = am35xx_dt_clk_init;
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700501}
502
Shawn Guobbd707a2012-04-26 16:06:50 +0800503void __init omap3_init_late(void)
504{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200505 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800506 omap3_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530507 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800508}
509
510void __init omap3430_init_late(void)
511{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200512 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800513 omap3_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530514 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800515}
516
517void __init omap35xx_init_late(void)
518{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200519 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800520 omap3_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530521 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800522}
523
524void __init omap3630_init_late(void)
525{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200526 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800527 omap3_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530528 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800529}
530
531void __init am35xx_init_late(void)
532{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200533 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800534 omap3_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530535 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800536}
537
538void __init ti81xx_init_late(void)
539{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200540 omap_common_late_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530541 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800542}
Sanjeev Premic4e2d242011-10-13 21:44:10 +0530543#endif
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700544
Aida Mynzhasovaa64459c2015-01-26 09:26:32 -0800545#ifdef CONFIG_SOC_TI81XX
546void __init ti814x_init_early(void)
547{
548 omap2_set_globals_tap(TI814X_CLASS,
549 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
Tero Kristo2208bf12014-11-13 19:17:34 +0200550 omap2_control_base_init();
Aida Mynzhasovaa64459c2015-01-26 09:26:32 -0800551 omap3xxx_check_revision();
552 ti81xx_check_features();
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200553 omap2_prcm_base_init();
Aida Mynzhasovaa64459c2015-01-26 09:26:32 -0800554 omap3xxx_voltagedomains_init();
555 omap3xxx_powerdomains_init();
556 ti81xx_clockdomains_init();
Tony Lindgren4d38bd12015-01-26 09:26:32 -0800557 ti81xx_hwmod_init();
Aida Mynzhasovaa64459c2015-01-26 09:26:32 -0800558 omap_hwmod_init_postsetup();
559 if (of_have_populated_dt())
560 omap_clk_soc_init = ti81xx_dt_clk_init;
561}
562
563void __init ti816x_init_early(void)
564{
565 omap2_set_globals_tap(TI816X_CLASS,
566 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
Tero Kristo2208bf12014-11-13 19:17:34 +0200567 omap2_control_base_init();
Aida Mynzhasovaa64459c2015-01-26 09:26:32 -0800568 omap3xxx_check_revision();
569 ti81xx_check_features();
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200570 omap2_prcm_base_init();
Aida Mynzhasovaa64459c2015-01-26 09:26:32 -0800571 omap3xxx_voltagedomains_init();
572 omap3xxx_powerdomains_init();
573 ti81xx_clockdomains_init();
Tony Lindgren4d38bd12015-01-26 09:26:32 -0800574 ti81xx_hwmod_init();
Aida Mynzhasovaa64459c2015-01-26 09:26:32 -0800575 omap_hwmod_init_postsetup();
576 if (of_have_populated_dt())
577 omap_clk_soc_init = ti81xx_dt_clk_init;
578}
579#endif
580
Afzal Mohammed08f30982012-05-11 00:38:49 +0530581#ifdef CONFIG_SOC_AM33XX
582void __init am33xx_init_early(void)
583{
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600584 omap2_set_globals_tap(AM335X_CLASS,
585 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
Tero Kristo2208bf12014-11-13 19:17:34 +0200586 omap2_control_base_init();
Afzal Mohammed08f30982012-05-11 00:38:49 +0530587 omap3xxx_check_revision();
Vaibhav Hiremath7bcad172013-05-17 15:43:41 +0530588 am33xx_check_features();
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200589 omap2_prcm_base_init();
Vaibhav Hiremath3f0ea762012-06-18 00:47:27 -0600590 am33xx_powerdomains_init();
Vaibhav Hiremath9c80f3a2012-06-18 00:47:27 -0600591 am33xx_clockdomains_init();
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600592 am33xx_hwmod_init();
593 omap_hwmod_init_postsetup();
Tero Kristo149c09d2013-07-19 11:37:17 +0300594 omap_clk_soc_init = am33xx_dt_clk_init;
Afzal Mohammed08f30982012-05-11 00:38:49 +0530595}
Nishanth Menon765e7a02013-10-16 10:39:02 -0500596
597void __init am33xx_init_late(void)
598{
599 omap_common_late_init();
600}
Afzal Mohammed08f30982012-05-11 00:38:49 +0530601#endif
602
Afzal Mohammedc5107022013-05-27 20:06:23 +0530603#ifdef CONFIG_SOC_AM43XX
604void __init am43xx_init_early(void)
605{
606 omap2_set_globals_tap(AM335X_CLASS,
607 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
Tero Kristo2208bf12014-11-13 19:17:34 +0200608 omap2_control_base_init();
Afzal Mohammedc5107022013-05-27 20:06:23 +0530609 omap3xxx_check_revision();
Afzal Mohammed7a2e0512014-02-07 15:51:25 +0530610 am33xx_check_features();
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200611 omap2_prcm_base_init();
Ambresh K8835cf62013-10-12 15:46:37 +0530612 am43xx_powerdomains_init();
613 am43xx_clockdomains_init();
614 am43xx_hwmod_init();
615 omap_hwmod_init_postsetup();
Sekhar Norid941f862014-04-22 13:58:03 +0530616 omap_l2_cache_init();
Tero Kristod22031e2013-11-21 16:49:59 +0200617 omap_clk_soc_init = am43xx_dt_clk_init;
Afzal Mohammedc5107022013-05-27 20:06:23 +0530618}
Nishanth Menon765e7a02013-10-16 10:39:02 -0500619
620void __init am43xx_init_late(void)
621{
622 omap_common_late_init();
623}
Afzal Mohammedc5107022013-05-27 20:06:23 +0530624#endif
625
Sanjeev Premic4e2d242011-10-13 21:44:10 +0530626#ifdef CONFIG_ARCH_OMAP4
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700627void __init omap4430_init_early(void)
628{
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600629 omap2_set_globals_tap(OMAP443X_CLASS,
630 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
Paul Walmsleyd9a16f92012-10-29 20:57:39 -0600631 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
Tero Kristoca125b52015-02-12 11:47:04 +0200632 omap2_control_base_init();
Vaibhav Hiremath4de34f32011-12-19 15:50:15 +0530633 omap4xxx_check_revision();
634 omap4xxx_check_features();
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200635 omap2_prcm_base_init();
Nishanth Menonde70af42014-01-20 14:06:37 -0600636 omap4_pm_init_early();
Tony Lindgren7b250af2011-10-04 18:26:28 -0700637 omap44xx_voltagedomains_init();
638 omap44xx_powerdomains_init();
639 omap44xx_clockdomains_init();
640 omap44xx_hwmod_init();
641 omap_hwmod_init_postsetup();
Sekhar Norib39b14e2014-04-22 13:58:01 +0530642 omap_l2_cache_init();
Tero Kristoc8c88d82013-07-18 16:04:00 +0300643 omap_clk_soc_init = omap4xxx_dt_clk_init;
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700644}
Shawn Guobbd707a2012-04-26 16:06:50 +0800645
646void __init omap4430_init_late(void)
647{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200648 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800649 omap4_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530650 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800651}
Sanjeev Premic4e2d242011-10-13 21:44:10 +0530652#endif
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700653
R Sricharan05e152c2012-06-05 16:21:32 +0530654#ifdef CONFIG_SOC_OMAP5
655void __init omap5_init_early(void)
656{
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600657 omap2_set_globals_tap(OMAP54XX_CLASS,
658 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
Paul Walmsleyd9a16f92012-10-29 20:57:39 -0600659 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
Tero Kristoca125b52015-02-12 11:47:04 +0200660 omap2_control_base_init();
Santosh Shilimkar628ed472014-05-20 16:19:23 -0500661 omap4_pm_init_early();
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200662 omap2_prcm_base_init();
R Sricharan05e152c2012-06-05 16:21:32 +0530663 omap5xxx_check_revision();
Santosh Shilimkare4020aa2013-05-29 12:38:12 -0400664 omap54xx_voltagedomains_init();
665 omap54xx_powerdomains_init();
666 omap54xx_clockdomains_init();
667 omap54xx_hwmod_init();
668 omap_hwmod_init_postsetup();
Tero Kristocfa96672013-10-22 11:53:02 +0300669 omap_clk_soc_init = omap5xxx_dt_clk_init;
R Sricharan05e152c2012-06-05 16:21:32 +0530670}
Nishanth Menon765e7a02013-10-16 10:39:02 -0500671
672void __init omap5_init_late(void)
673{
674 omap_common_late_init();
Santosh Shilimkar628ed472014-05-20 16:19:23 -0500675 omap4_pm_init();
676 omap2_clk_enable_autoidle_all();
Nishanth Menon765e7a02013-10-16 10:39:02 -0500677}
R Sricharan05e152c2012-06-05 16:21:32 +0530678#endif
679
R Sricharana3a93842013-07-03 11:52:04 +0530680#ifdef CONFIG_SOC_DRA7XX
681void __init dra7xx_init_early(void)
682{
683 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
R Sricharana3a93842013-07-03 11:52:04 +0530684 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
Tero Kristoca125b52015-02-12 11:47:04 +0200685 omap2_control_base_init();
Rajendra Nayak6af16a12014-08-22 09:02:34 -0500686 omap4_pm_init_early();
Tero Kristoab7b2ff2014-11-20 15:02:59 +0200687 omap2_prcm_base_init();
Nishanth Menon733d20e2014-05-19 10:27:11 -0500688 dra7xxx_check_revision();
Ambresh K7de516a2013-08-23 04:05:08 -0600689 dra7xx_powerdomains_init();
690 dra7xx_clockdomains_init();
691 dra7xx_hwmod_init();
692 omap_hwmod_init_postsetup();
Tero Kristof1cf4982013-08-29 11:35:43 +0300693 omap_clk_soc_init = dra7xx_dt_clk_init;
R Sricharana3a93842013-07-03 11:52:04 +0530694}
Nishanth Menon765e7a02013-10-16 10:39:02 -0500695
696void __init dra7xx_init_late(void)
697{
698 omap_common_late_init();
Rajendra Nayak6af16a12014-08-22 09:02:34 -0500699 omap4_pm_init();
700 omap2_clk_enable_autoidle_all();
Nishanth Menon765e7a02013-10-16 10:39:02 -0500701}
R Sricharana3a93842013-07-03 11:52:04 +0530702#endif
703
704
Tony Lindgrena4ca9db2011-08-22 23:57:23 -0700705void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
Paul Walmsley48057342010-12-21 15:25:10 -0700706 struct omap_sdrc_params *sdrc_cs1)
707{
Tony Lindgrena66cb342011-10-04 13:52:57 -0700708 omap_sram_init();
709
Hemant Pedanekar01001712011-02-16 08:31:39 -0800710 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
Kevin Hilmanaa4b1f62010-03-10 17:16:31 +0000711 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
712 _omap2_init_reprogram_sdrc();
713 }
Tony Lindgren1dbae812005-11-10 14:26:51 +0000714}
Tero Kristocfa96672013-10-22 11:53:02 +0300715
716int __init omap_clk_init(void)
717{
718 int ret = 0;
719
720 if (!omap_clk_soc_init)
721 return 0;
722
Tero Kristo8111e012014-07-02 11:47:39 +0300723 ti_clk_init_features();
724
Tero Kristoe9e63082015-04-27 21:55:42 +0300725 omap2_clk_setup_ll_ops();
726
Tero Kristoeded36f2014-12-16 18:20:55 +0200727 if (of_have_populated_dt()) {
Tero Kristofe874142014-03-12 18:33:45 +0200728 ret = omap_control_init();
729 if (ret)
730 return ret;
731
Tero Kristo3a1a3882014-11-18 14:59:36 +0200732 ret = omap_prcm_init();
Tero Kristoeded36f2014-12-16 18:20:55 +0200733 if (ret)
734 return ret;
Tero Kristoc08ee142014-09-12 15:01:57 +0300735
Tero Kristoeded36f2014-12-16 18:20:55 +0200736 of_clk_init(NULL);
Tero Kristoc08ee142014-09-12 15:01:57 +0300737
Tero Kristoeded36f2014-12-16 18:20:55 +0200738 ti_dt_clk_init_retry_clks();
Tero Kristoc08ee142014-09-12 15:01:57 +0300739
Tero Kristoeded36f2014-12-16 18:20:55 +0200740 ti_dt_clockdomains_setup();
741 }
Tero Kristoc08ee142014-09-12 15:01:57 +0300742
743 ret = omap_clk_soc_init();
Tero Kristocfa96672013-10-22 11:53:02 +0300744
745 return ret;
746}