Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. |
| 3 | * Copyright 2011 Linaro Ltd. |
| 4 | * |
| 5 | * The code contained herein is licensed under the GNU General Public |
| 6 | * License. You may obtain a copy of the GNU General Public License |
| 7 | * Version 2 or later at the following locations: |
| 8 | * |
| 9 | * http://www.opensource.org/licenses/gpl-license.html |
| 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ |
| 12 | |
Shawn Guo | 36dffd8 | 2013-04-07 10:49:34 +0800 | [diff] [blame] | 13 | #include "skeleton.dtsi" |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 14 | |
| 15 | / { |
| 16 | aliases { |
Richard Zhao | 8f9ffec | 2011-12-14 09:26:45 +0800 | [diff] [blame] | 17 | serial0 = &uart1; |
| 18 | serial1 = &uart2; |
| 19 | serial2 = &uart3; |
| 20 | serial3 = &uart4; |
| 21 | serial4 = &uart5; |
Shawn Guo | 5230f8f | 2012-08-05 14:01:28 +0800 | [diff] [blame] | 22 | gpio0 = &gpio1; |
| 23 | gpio1 = &gpio2; |
| 24 | gpio2 = &gpio3; |
| 25 | gpio3 = &gpio4; |
| 26 | gpio4 = &gpio5; |
| 27 | gpio5 = &gpio6; |
| 28 | gpio6 = &gpio7; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 29 | }; |
| 30 | |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 31 | intc: interrupt-controller@00a01000 { |
| 32 | compatible = "arm,cortex-a9-gic"; |
| 33 | #interrupt-cells = <3>; |
| 34 | #address-cells = <1>; |
| 35 | #size-cells = <1>; |
| 36 | interrupt-controller; |
| 37 | reg = <0x00a01000 0x1000>, |
| 38 | <0x00a00100 0x100>; |
| 39 | }; |
| 40 | |
| 41 | clocks { |
| 42 | #address-cells = <1>; |
| 43 | #size-cells = <0>; |
| 44 | |
| 45 | ckil { |
| 46 | compatible = "fsl,imx-ckil", "fixed-clock"; |
| 47 | clock-frequency = <32768>; |
| 48 | }; |
| 49 | |
| 50 | ckih1 { |
| 51 | compatible = "fsl,imx-ckih1", "fixed-clock"; |
| 52 | clock-frequency = <0>; |
| 53 | }; |
| 54 | |
| 55 | osc { |
| 56 | compatible = "fsl,imx-osc", "fixed-clock"; |
| 57 | clock-frequency = <24000000>; |
| 58 | }; |
| 59 | }; |
| 60 | |
| 61 | soc { |
| 62 | #address-cells = <1>; |
| 63 | #size-cells = <1>; |
| 64 | compatible = "simple-bus"; |
| 65 | interrupt-parent = <&intc>; |
| 66 | ranges; |
| 67 | |
Huang Shijie | e5d0f9f | 2012-06-06 21:22:57 -0400 | [diff] [blame] | 68 | dma-apbh@00110000 { |
| 69 | compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; |
| 70 | reg = <0x00110000 0x2000>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 71 | clocks = <&clks 106>; |
Huang Shijie | e5d0f9f | 2012-06-06 21:22:57 -0400 | [diff] [blame] | 72 | }; |
| 73 | |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 74 | gpmi: gpmi-nand@00112000 { |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 75 | compatible = "fsl,imx6q-gpmi-nand"; |
| 76 | #address-cells = <1>; |
| 77 | #size-cells = <1>; |
| 78 | reg = <0x00112000 0x2000>, <0x00114000 0x2000>; |
| 79 | reg-names = "gpmi-nand", "bch"; |
| 80 | interrupts = <0 13 0x04>, <0 15 0x04>; |
| 81 | interrupt-names = "gpmi-dma", "bch"; |
| 82 | clocks = <&clks 152>, <&clks 153>, <&clks 151>, |
| 83 | <&clks 150>, <&clks 149>; |
| 84 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", |
| 85 | "gpmi_bch_apb", "per1_bch"; |
| 86 | fsl,gpmi-dma-channel = <0>; |
| 87 | status = "disabled"; |
Huang Shijie | cf922fa | 2012-07-01 23:38:46 -0400 | [diff] [blame] | 88 | }; |
| 89 | |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 90 | timer@00a00600 { |
Marc Zyngier | 58458e0 | 2012-01-10 19:44:19 +0000 | [diff] [blame] | 91 | compatible = "arm,cortex-a9-twd-timer"; |
| 92 | reg = <0x00a00600 0x20>; |
| 93 | interrupts = <1 13 0xf01>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 94 | }; |
| 95 | |
| 96 | L2: l2-cache@00a02000 { |
| 97 | compatible = "arm,pl310-cache"; |
| 98 | reg = <0x00a02000 0x1000>; |
| 99 | interrupts = <0 92 0x04>; |
| 100 | cache-unified; |
| 101 | cache-level = <2>; |
| 102 | }; |
| 103 | |
Dirk Behme | 218abe6 | 2013-02-15 15:10:01 +0100 | [diff] [blame] | 104 | pmu { |
| 105 | compatible = "arm,cortex-a9-pmu"; |
| 106 | interrupts = <0 94 0x04>; |
| 107 | }; |
| 108 | |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 109 | aips-bus@02000000 { /* AIPS1 */ |
| 110 | compatible = "fsl,aips-bus", "simple-bus"; |
| 111 | #address-cells = <1>; |
| 112 | #size-cells = <1>; |
| 113 | reg = <0x02000000 0x100000>; |
| 114 | ranges; |
| 115 | |
| 116 | spba-bus@02000000 { |
| 117 | compatible = "fsl,spba-bus", "simple-bus"; |
| 118 | #address-cells = <1>; |
| 119 | #size-cells = <1>; |
| 120 | reg = <0x02000000 0x40000>; |
| 121 | ranges; |
| 122 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 123 | spdif: spdif@02004000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 124 | reg = <0x02004000 0x4000>; |
| 125 | interrupts = <0 52 0x04>; |
| 126 | }; |
| 127 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 128 | ecspi1: ecspi@02008000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 129 | #address-cells = <1>; |
| 130 | #size-cells = <0>; |
| 131 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 132 | reg = <0x02008000 0x4000>; |
| 133 | interrupts = <0 31 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 134 | clocks = <&clks 112>, <&clks 112>; |
| 135 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 136 | status = "disabled"; |
| 137 | }; |
| 138 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 139 | ecspi2: ecspi@0200c000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 140 | #address-cells = <1>; |
| 141 | #size-cells = <0>; |
| 142 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 143 | reg = <0x0200c000 0x4000>; |
| 144 | interrupts = <0 32 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 145 | clocks = <&clks 113>, <&clks 113>; |
| 146 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 147 | status = "disabled"; |
| 148 | }; |
| 149 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 150 | ecspi3: ecspi@02010000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 151 | #address-cells = <1>; |
| 152 | #size-cells = <0>; |
| 153 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 154 | reg = <0x02010000 0x4000>; |
| 155 | interrupts = <0 33 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 156 | clocks = <&clks 114>, <&clks 114>; |
| 157 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 158 | status = "disabled"; |
| 159 | }; |
| 160 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 161 | ecspi4: ecspi@02014000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 162 | #address-cells = <1>; |
| 163 | #size-cells = <0>; |
| 164 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 165 | reg = <0x02014000 0x4000>; |
| 166 | interrupts = <0 34 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 167 | clocks = <&clks 115>, <&clks 115>; |
| 168 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 169 | status = "disabled"; |
| 170 | }; |
| 171 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 172 | uart1: serial@02020000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 173 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 174 | reg = <0x02020000 0x4000>; |
| 175 | interrupts = <0 26 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 176 | clocks = <&clks 160>, <&clks 161>; |
| 177 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 178 | status = "disabled"; |
| 179 | }; |
| 180 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 181 | esai: esai@02024000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 182 | reg = <0x02024000 0x4000>; |
| 183 | interrupts = <0 51 0x04>; |
| 184 | }; |
| 185 | |
Richard Zhao | b1a5da8 | 2012-05-02 10:29:10 +0800 | [diff] [blame] | 186 | ssi1: ssi@02028000 { |
| 187 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 188 | reg = <0x02028000 0x4000>; |
| 189 | interrupts = <0 46 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 190 | clocks = <&clks 178>; |
Richard Zhao | b1a5da8 | 2012-05-02 10:29:10 +0800 | [diff] [blame] | 191 | fsl,fifo-depth = <15>; |
| 192 | fsl,ssi-dma-events = <38 37>; |
| 193 | status = "disabled"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 194 | }; |
| 195 | |
Richard Zhao | b1a5da8 | 2012-05-02 10:29:10 +0800 | [diff] [blame] | 196 | ssi2: ssi@0202c000 { |
| 197 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 198 | reg = <0x0202c000 0x4000>; |
| 199 | interrupts = <0 47 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 200 | clocks = <&clks 179>; |
Richard Zhao | b1a5da8 | 2012-05-02 10:29:10 +0800 | [diff] [blame] | 201 | fsl,fifo-depth = <15>; |
| 202 | fsl,ssi-dma-events = <42 41>; |
| 203 | status = "disabled"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 204 | }; |
| 205 | |
Richard Zhao | b1a5da8 | 2012-05-02 10:29:10 +0800 | [diff] [blame] | 206 | ssi3: ssi@02030000 { |
| 207 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 208 | reg = <0x02030000 0x4000>; |
| 209 | interrupts = <0 48 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 210 | clocks = <&clks 180>; |
Richard Zhao | b1a5da8 | 2012-05-02 10:29:10 +0800 | [diff] [blame] | 211 | fsl,fifo-depth = <15>; |
| 212 | fsl,ssi-dma-events = <46 45>; |
| 213 | status = "disabled"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 214 | }; |
| 215 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 216 | asrc: asrc@02034000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 217 | reg = <0x02034000 0x4000>; |
| 218 | interrupts = <0 50 0x04>; |
| 219 | }; |
| 220 | |
| 221 | spba@0203c000 { |
| 222 | reg = <0x0203c000 0x4000>; |
| 223 | }; |
| 224 | }; |
| 225 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 226 | vpu: vpu@02040000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 227 | reg = <0x02040000 0x3c000>; |
| 228 | interrupts = <0 3 0x04 0 12 0x04>; |
| 229 | }; |
| 230 | |
| 231 | aipstz@0207c000 { /* AIPSTZ1 */ |
| 232 | reg = <0x0207c000 0x4000>; |
| 233 | }; |
| 234 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 235 | pwm1: pwm@02080000 { |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 236 | #pwm-cells = <2>; |
| 237 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 238 | reg = <0x02080000 0x4000>; |
| 239 | interrupts = <0 83 0x04>; |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 240 | clocks = <&clks 62>, <&clks 145>; |
| 241 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 242 | }; |
| 243 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 244 | pwm2: pwm@02084000 { |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 245 | #pwm-cells = <2>; |
| 246 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 247 | reg = <0x02084000 0x4000>; |
| 248 | interrupts = <0 84 0x04>; |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 249 | clocks = <&clks 62>, <&clks 146>; |
| 250 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 251 | }; |
| 252 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 253 | pwm3: pwm@02088000 { |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 254 | #pwm-cells = <2>; |
| 255 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 256 | reg = <0x02088000 0x4000>; |
| 257 | interrupts = <0 85 0x04>; |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 258 | clocks = <&clks 62>, <&clks 147>; |
| 259 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 260 | }; |
| 261 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 262 | pwm4: pwm@0208c000 { |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 263 | #pwm-cells = <2>; |
| 264 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 265 | reg = <0x0208c000 0x4000>; |
| 266 | interrupts = <0 86 0x04>; |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 267 | clocks = <&clks 62>, <&clks 148>; |
| 268 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 269 | }; |
| 270 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 271 | can1: flexcan@02090000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 272 | reg = <0x02090000 0x4000>; |
| 273 | interrupts = <0 110 0x04>; |
| 274 | }; |
| 275 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 276 | can2: flexcan@02094000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 277 | reg = <0x02094000 0x4000>; |
| 278 | interrupts = <0 111 0x04>; |
| 279 | }; |
| 280 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 281 | gpt: gpt@02098000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 282 | compatible = "fsl,imx6q-gpt"; |
| 283 | reg = <0x02098000 0x4000>; |
| 284 | interrupts = <0 55 0x04>; |
Sascha Hauer | 4efccad | 2013-03-14 13:09:01 +0100 | [diff] [blame] | 285 | clocks = <&clks 119>, <&clks 120>; |
| 286 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 287 | }; |
| 288 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 289 | gpio1: gpio@0209c000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 290 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 291 | reg = <0x0209c000 0x4000>; |
| 292 | interrupts = <0 66 0x04 0 67 0x04>; |
| 293 | gpio-controller; |
| 294 | #gpio-cells = <2>; |
| 295 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 296 | #interrupt-cells = <2>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 297 | }; |
| 298 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 299 | gpio2: gpio@020a0000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 300 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 301 | reg = <0x020a0000 0x4000>; |
| 302 | interrupts = <0 68 0x04 0 69 0x04>; |
| 303 | gpio-controller; |
| 304 | #gpio-cells = <2>; |
| 305 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 306 | #interrupt-cells = <2>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 307 | }; |
| 308 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 309 | gpio3: gpio@020a4000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 310 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 311 | reg = <0x020a4000 0x4000>; |
| 312 | interrupts = <0 70 0x04 0 71 0x04>; |
| 313 | gpio-controller; |
| 314 | #gpio-cells = <2>; |
| 315 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 316 | #interrupt-cells = <2>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 317 | }; |
| 318 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 319 | gpio4: gpio@020a8000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 320 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 321 | reg = <0x020a8000 0x4000>; |
| 322 | interrupts = <0 72 0x04 0 73 0x04>; |
| 323 | gpio-controller; |
| 324 | #gpio-cells = <2>; |
| 325 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 326 | #interrupt-cells = <2>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 327 | }; |
| 328 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 329 | gpio5: gpio@020ac000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 330 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 331 | reg = <0x020ac000 0x4000>; |
| 332 | interrupts = <0 74 0x04 0 75 0x04>; |
| 333 | gpio-controller; |
| 334 | #gpio-cells = <2>; |
| 335 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 336 | #interrupt-cells = <2>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 337 | }; |
| 338 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 339 | gpio6: gpio@020b0000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 340 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 341 | reg = <0x020b0000 0x4000>; |
| 342 | interrupts = <0 76 0x04 0 77 0x04>; |
| 343 | gpio-controller; |
| 344 | #gpio-cells = <2>; |
| 345 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 346 | #interrupt-cells = <2>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 347 | }; |
| 348 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 349 | gpio7: gpio@020b4000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 350 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 351 | reg = <0x020b4000 0x4000>; |
| 352 | interrupts = <0 78 0x04 0 79 0x04>; |
| 353 | gpio-controller; |
| 354 | #gpio-cells = <2>; |
| 355 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 356 | #interrupt-cells = <2>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 357 | }; |
| 358 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 359 | kpp: kpp@020b8000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 360 | reg = <0x020b8000 0x4000>; |
| 361 | interrupts = <0 82 0x04>; |
| 362 | }; |
| 363 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 364 | wdog1: wdog@020bc000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 365 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
| 366 | reg = <0x020bc000 0x4000>; |
| 367 | interrupts = <0 80 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 368 | clocks = <&clks 0>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 369 | }; |
| 370 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 371 | wdog2: wdog@020c0000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 372 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
| 373 | reg = <0x020c0000 0x4000>; |
| 374 | interrupts = <0 81 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 375 | clocks = <&clks 0>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 376 | status = "disabled"; |
| 377 | }; |
| 378 | |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 379 | clks: ccm@020c4000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 380 | compatible = "fsl,imx6q-ccm"; |
| 381 | reg = <0x020c4000 0x4000>; |
| 382 | interrupts = <0 87 0x04 0 88 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 383 | #clock-cells = <1>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 384 | }; |
| 385 | |
Dong Aisheng | baa6415 | 2012-09-05 10:57:15 +0800 | [diff] [blame] | 386 | anatop: anatop@020c8000 { |
| 387 | compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 388 | reg = <0x020c8000 0x1000>; |
| 389 | interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; |
Ying-Chun Liu (PaulLiu) | a1e327e | 2012-03-30 21:46:53 +0800 | [diff] [blame] | 390 | |
| 391 | regulator-1p1@110 { |
| 392 | compatible = "fsl,anatop-regulator"; |
| 393 | regulator-name = "vdd1p1"; |
| 394 | regulator-min-microvolt = <800000>; |
| 395 | regulator-max-microvolt = <1375000>; |
| 396 | regulator-always-on; |
| 397 | anatop-reg-offset = <0x110>; |
| 398 | anatop-vol-bit-shift = <8>; |
| 399 | anatop-vol-bit-width = <5>; |
| 400 | anatop-min-bit-val = <4>; |
| 401 | anatop-min-voltage = <800000>; |
| 402 | anatop-max-voltage = <1375000>; |
| 403 | }; |
| 404 | |
| 405 | regulator-3p0@120 { |
| 406 | compatible = "fsl,anatop-regulator"; |
| 407 | regulator-name = "vdd3p0"; |
| 408 | regulator-min-microvolt = <2800000>; |
| 409 | regulator-max-microvolt = <3150000>; |
| 410 | regulator-always-on; |
| 411 | anatop-reg-offset = <0x120>; |
| 412 | anatop-vol-bit-shift = <8>; |
| 413 | anatop-vol-bit-width = <5>; |
| 414 | anatop-min-bit-val = <0>; |
| 415 | anatop-min-voltage = <2625000>; |
| 416 | anatop-max-voltage = <3400000>; |
| 417 | }; |
| 418 | |
| 419 | regulator-2p5@130 { |
| 420 | compatible = "fsl,anatop-regulator"; |
| 421 | regulator-name = "vdd2p5"; |
| 422 | regulator-min-microvolt = <2000000>; |
| 423 | regulator-max-microvolt = <2750000>; |
| 424 | regulator-always-on; |
| 425 | anatop-reg-offset = <0x130>; |
| 426 | anatop-vol-bit-shift = <8>; |
| 427 | anatop-vol-bit-width = <5>; |
| 428 | anatop-min-bit-val = <0>; |
| 429 | anatop-min-voltage = <2000000>; |
| 430 | anatop-max-voltage = <2750000>; |
| 431 | }; |
| 432 | |
Shawn Guo | 96574a6 | 2013-01-08 14:25:14 +0800 | [diff] [blame] | 433 | reg_arm: regulator-vddcore@140 { |
Ying-Chun Liu (PaulLiu) | a1e327e | 2012-03-30 21:46:53 +0800 | [diff] [blame] | 434 | compatible = "fsl,anatop-regulator"; |
| 435 | regulator-name = "cpu"; |
| 436 | regulator-min-microvolt = <725000>; |
| 437 | regulator-max-microvolt = <1450000>; |
| 438 | regulator-always-on; |
| 439 | anatop-reg-offset = <0x140>; |
| 440 | anatop-vol-bit-shift = <0>; |
| 441 | anatop-vol-bit-width = <5>; |
Anson Huang | 46743dd | 2013-01-30 17:33:44 -0500 | [diff] [blame] | 442 | anatop-delay-reg-offset = <0x170>; |
| 443 | anatop-delay-bit-shift = <24>; |
| 444 | anatop-delay-bit-width = <2>; |
Ying-Chun Liu (PaulLiu) | a1e327e | 2012-03-30 21:46:53 +0800 | [diff] [blame] | 445 | anatop-min-bit-val = <1>; |
| 446 | anatop-min-voltage = <725000>; |
| 447 | anatop-max-voltage = <1450000>; |
| 448 | }; |
| 449 | |
Shawn Guo | 96574a6 | 2013-01-08 14:25:14 +0800 | [diff] [blame] | 450 | reg_pu: regulator-vddpu@140 { |
Ying-Chun Liu (PaulLiu) | a1e327e | 2012-03-30 21:46:53 +0800 | [diff] [blame] | 451 | compatible = "fsl,anatop-regulator"; |
| 452 | regulator-name = "vddpu"; |
| 453 | regulator-min-microvolt = <725000>; |
| 454 | regulator-max-microvolt = <1450000>; |
| 455 | regulator-always-on; |
| 456 | anatop-reg-offset = <0x140>; |
| 457 | anatop-vol-bit-shift = <9>; |
| 458 | anatop-vol-bit-width = <5>; |
Anson Huang | 46743dd | 2013-01-30 17:33:44 -0500 | [diff] [blame] | 459 | anatop-delay-reg-offset = <0x170>; |
| 460 | anatop-delay-bit-shift = <26>; |
| 461 | anatop-delay-bit-width = <2>; |
Ying-Chun Liu (PaulLiu) | a1e327e | 2012-03-30 21:46:53 +0800 | [diff] [blame] | 462 | anatop-min-bit-val = <1>; |
| 463 | anatop-min-voltage = <725000>; |
| 464 | anatop-max-voltage = <1450000>; |
| 465 | }; |
| 466 | |
Shawn Guo | 96574a6 | 2013-01-08 14:25:14 +0800 | [diff] [blame] | 467 | reg_soc: regulator-vddsoc@140 { |
Ying-Chun Liu (PaulLiu) | a1e327e | 2012-03-30 21:46:53 +0800 | [diff] [blame] | 468 | compatible = "fsl,anatop-regulator"; |
| 469 | regulator-name = "vddsoc"; |
| 470 | regulator-min-microvolt = <725000>; |
| 471 | regulator-max-microvolt = <1450000>; |
| 472 | regulator-always-on; |
| 473 | anatop-reg-offset = <0x140>; |
| 474 | anatop-vol-bit-shift = <18>; |
| 475 | anatop-vol-bit-width = <5>; |
Anson Huang | 46743dd | 2013-01-30 17:33:44 -0500 | [diff] [blame] | 476 | anatop-delay-reg-offset = <0x170>; |
| 477 | anatop-delay-bit-shift = <28>; |
| 478 | anatop-delay-bit-width = <2>; |
Ying-Chun Liu (PaulLiu) | a1e327e | 2012-03-30 21:46:53 +0800 | [diff] [blame] | 479 | anatop-min-bit-val = <1>; |
| 480 | anatop-min-voltage = <725000>; |
| 481 | anatop-max-voltage = <1450000>; |
| 482 | }; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 483 | }; |
| 484 | |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 485 | usbphy1: usbphy@020c9000 { |
| 486 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 487 | reg = <0x020c9000 0x1000>; |
| 488 | interrupts = <0 44 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 489 | clocks = <&clks 182>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 490 | }; |
| 491 | |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 492 | usbphy2: usbphy@020ca000 { |
| 493 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 494 | reg = <0x020ca000 0x1000>; |
| 495 | interrupts = <0 45 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 496 | clocks = <&clks 183>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 497 | }; |
| 498 | |
| 499 | snvs@020cc000 { |
Shawn Guo | c925038 | 2012-07-02 20:13:03 +0800 | [diff] [blame] | 500 | compatible = "fsl,sec-v4.0-mon", "simple-bus"; |
| 501 | #address-cells = <1>; |
| 502 | #size-cells = <1>; |
| 503 | ranges = <0 0x020cc000 0x4000>; |
| 504 | |
| 505 | snvs-rtc-lp@34 { |
| 506 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; |
| 507 | reg = <0x34 0x58>; |
| 508 | interrupts = <0 19 0x04 0 20 0x04>; |
| 509 | }; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 510 | }; |
| 511 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 512 | epit1: epit@020d0000 { /* EPIT1 */ |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 513 | reg = <0x020d0000 0x4000>; |
| 514 | interrupts = <0 56 0x04>; |
| 515 | }; |
| 516 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 517 | epit2: epit@020d4000 { /* EPIT2 */ |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 518 | reg = <0x020d4000 0x4000>; |
| 519 | interrupts = <0 57 0x04>; |
| 520 | }; |
| 521 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 522 | src: src@020d8000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 523 | compatible = "fsl,imx6q-src"; |
| 524 | reg = <0x020d8000 0x4000>; |
| 525 | interrupts = <0 91 0x04 0 96 0x04>; |
Philipp Zabel | 09ebf36 | 2013-03-28 17:35:20 +0100 | [diff] [blame^] | 526 | #reset-cells = <1>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 527 | }; |
| 528 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 529 | gpc: gpc@020dc000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 530 | compatible = "fsl,imx6q-gpc"; |
| 531 | reg = <0x020dc000 0x4000>; |
| 532 | interrupts = <0 89 0x04 0 90 0x04>; |
| 533 | }; |
| 534 | |
Dong Aisheng | df37e0c | 2012-09-05 10:57:14 +0800 | [diff] [blame] | 535 | gpr: iomuxc-gpr@020e0000 { |
| 536 | compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; |
| 537 | reg = <0x020e0000 0x38>; |
| 538 | }; |
| 539 | |
Steffen Trumtrar | 41c0434 | 2013-03-28 16:23:35 +0100 | [diff] [blame] | 540 | ldb: ldb@020e0008 { |
| 541 | #address-cells = <1>; |
| 542 | #size-cells = <0>; |
| 543 | compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; |
| 544 | gpr = <&gpr>; |
| 545 | status = "disabled"; |
| 546 | |
| 547 | lvds-channel@0 { |
| 548 | reg = <0>; |
| 549 | crtcs = <&ipu1 0>; |
| 550 | status = "disabled"; |
| 551 | }; |
| 552 | |
| 553 | lvds-channel@1 { |
| 554 | reg = <1>; |
| 555 | crtcs = <&ipu1 1>; |
| 556 | status = "disabled"; |
| 557 | }; |
| 558 | }; |
| 559 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 560 | dcic1: dcic@020e4000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 561 | reg = <0x020e4000 0x4000>; |
| 562 | interrupts = <0 124 0x04>; |
| 563 | }; |
| 564 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 565 | dcic2: dcic@020e8000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 566 | reg = <0x020e8000 0x4000>; |
| 567 | interrupts = <0 125 0x04>; |
| 568 | }; |
| 569 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 570 | sdma: sdma@020ec000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 571 | compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; |
| 572 | reg = <0x020ec000 0x4000>; |
| 573 | interrupts = <0 2 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 574 | clocks = <&clks 155>, <&clks 155>; |
| 575 | clock-names = "ipg", "ahb"; |
Fabio Estevam | d6b9c59 | 2013-01-17 12:13:25 -0200 | [diff] [blame] | 576 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 577 | }; |
| 578 | }; |
| 579 | |
| 580 | aips-bus@02100000 { /* AIPS2 */ |
| 581 | compatible = "fsl,aips-bus", "simple-bus"; |
| 582 | #address-cells = <1>; |
| 583 | #size-cells = <1>; |
| 584 | reg = <0x02100000 0x100000>; |
| 585 | ranges; |
| 586 | |
| 587 | caam@02100000 { |
| 588 | reg = <0x02100000 0x40000>; |
| 589 | interrupts = <0 105 0x04 0 106 0x04>; |
| 590 | }; |
| 591 | |
| 592 | aipstz@0217c000 { /* AIPSTZ2 */ |
| 593 | reg = <0x0217c000 0x4000>; |
| 594 | }; |
| 595 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 596 | usbotg: usb@02184000 { |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 597 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 598 | reg = <0x02184000 0x200>; |
| 599 | interrupts = <0 43 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 600 | clocks = <&clks 162>; |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 601 | fsl,usbphy = <&usbphy1>; |
Richard Zhao | 28342c6 | 2012-09-14 14:42:45 +0800 | [diff] [blame] | 602 | fsl,usbmisc = <&usbmisc 0>; |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 603 | status = "disabled"; |
| 604 | }; |
| 605 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 606 | usbh1: usb@02184200 { |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 607 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 608 | reg = <0x02184200 0x200>; |
| 609 | interrupts = <0 40 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 610 | clocks = <&clks 162>; |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 611 | fsl,usbphy = <&usbphy2>; |
Richard Zhao | 28342c6 | 2012-09-14 14:42:45 +0800 | [diff] [blame] | 612 | fsl,usbmisc = <&usbmisc 1>; |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 613 | status = "disabled"; |
| 614 | }; |
| 615 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 616 | usbh2: usb@02184400 { |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 617 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 618 | reg = <0x02184400 0x200>; |
| 619 | interrupts = <0 41 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 620 | clocks = <&clks 162>; |
Richard Zhao | 28342c6 | 2012-09-14 14:42:45 +0800 | [diff] [blame] | 621 | fsl,usbmisc = <&usbmisc 2>; |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 622 | status = "disabled"; |
| 623 | }; |
| 624 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 625 | usbh3: usb@02184600 { |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 626 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 627 | reg = <0x02184600 0x200>; |
| 628 | interrupts = <0 42 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 629 | clocks = <&clks 162>; |
Richard Zhao | 28342c6 | 2012-09-14 14:42:45 +0800 | [diff] [blame] | 630 | fsl,usbmisc = <&usbmisc 3>; |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 631 | status = "disabled"; |
| 632 | }; |
| 633 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 634 | usbmisc: usbmisc: usbmisc@02184800 { |
Richard Zhao | 28342c6 | 2012-09-14 14:42:45 +0800 | [diff] [blame] | 635 | #index-cells = <1>; |
| 636 | compatible = "fsl,imx6q-usbmisc"; |
| 637 | reg = <0x02184800 0x200>; |
| 638 | clocks = <&clks 162>; |
| 639 | }; |
| 640 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 641 | fec: ethernet@02188000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 642 | compatible = "fsl,imx6q-fec"; |
| 643 | reg = <0x02188000 0x4000>; |
| 644 | interrupts = <0 118 0x04 0 119 0x04>; |
Frank Li | 8dd5c66 | 2013-02-05 14:21:06 +0800 | [diff] [blame] | 645 | clocks = <&clks 117>, <&clks 117>, <&clks 190>; |
Frank Li | 7629838 | 2012-10-30 18:24:57 +0000 | [diff] [blame] | 646 | clock-names = "ipg", "ahb", "ptp"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 647 | status = "disabled"; |
| 648 | }; |
| 649 | |
| 650 | mlb@0218c000 { |
| 651 | reg = <0x0218c000 0x4000>; |
| 652 | interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>; |
| 653 | }; |
| 654 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 655 | usdhc1: usdhc@02190000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 656 | compatible = "fsl,imx6q-usdhc"; |
| 657 | reg = <0x02190000 0x4000>; |
| 658 | interrupts = <0 22 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 659 | clocks = <&clks 163>, <&clks 163>, <&clks 163>; |
| 660 | clock-names = "ipg", "ahb", "per"; |
Sascha Hauer | c104b6a | 2012-09-25 11:49:33 +0200 | [diff] [blame] | 661 | bus-width = <4>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 662 | status = "disabled"; |
| 663 | }; |
| 664 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 665 | usdhc2: usdhc@02194000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 666 | compatible = "fsl,imx6q-usdhc"; |
| 667 | reg = <0x02194000 0x4000>; |
| 668 | interrupts = <0 23 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 669 | clocks = <&clks 164>, <&clks 164>, <&clks 164>; |
| 670 | clock-names = "ipg", "ahb", "per"; |
Sascha Hauer | c104b6a | 2012-09-25 11:49:33 +0200 | [diff] [blame] | 671 | bus-width = <4>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 672 | status = "disabled"; |
| 673 | }; |
| 674 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 675 | usdhc3: usdhc@02198000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 676 | compatible = "fsl,imx6q-usdhc"; |
| 677 | reg = <0x02198000 0x4000>; |
| 678 | interrupts = <0 24 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 679 | clocks = <&clks 165>, <&clks 165>, <&clks 165>; |
| 680 | clock-names = "ipg", "ahb", "per"; |
Sascha Hauer | c104b6a | 2012-09-25 11:49:33 +0200 | [diff] [blame] | 681 | bus-width = <4>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 682 | status = "disabled"; |
| 683 | }; |
| 684 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 685 | usdhc4: usdhc@0219c000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 686 | compatible = "fsl,imx6q-usdhc"; |
| 687 | reg = <0x0219c000 0x4000>; |
| 688 | interrupts = <0 25 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 689 | clocks = <&clks 166>, <&clks 166>, <&clks 166>; |
| 690 | clock-names = "ipg", "ahb", "per"; |
Sascha Hauer | c104b6a | 2012-09-25 11:49:33 +0200 | [diff] [blame] | 691 | bus-width = <4>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 692 | status = "disabled"; |
| 693 | }; |
| 694 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 695 | i2c1: i2c@021a0000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 696 | #address-cells = <1>; |
| 697 | #size-cells = <0>; |
Shawn Guo | 5bdfba2 | 2012-09-14 15:19:00 +0800 | [diff] [blame] | 698 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 699 | reg = <0x021a0000 0x4000>; |
| 700 | interrupts = <0 36 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 701 | clocks = <&clks 125>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 702 | status = "disabled"; |
| 703 | }; |
| 704 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 705 | i2c2: i2c@021a4000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 706 | #address-cells = <1>; |
| 707 | #size-cells = <0>; |
Shawn Guo | 5bdfba2 | 2012-09-14 15:19:00 +0800 | [diff] [blame] | 708 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 709 | reg = <0x021a4000 0x4000>; |
| 710 | interrupts = <0 37 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 711 | clocks = <&clks 126>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 712 | status = "disabled"; |
| 713 | }; |
| 714 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 715 | i2c3: i2c@021a8000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 716 | #address-cells = <1>; |
| 717 | #size-cells = <0>; |
Shawn Guo | 5bdfba2 | 2012-09-14 15:19:00 +0800 | [diff] [blame] | 718 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 719 | reg = <0x021a8000 0x4000>; |
| 720 | interrupts = <0 38 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 721 | clocks = <&clks 127>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 722 | status = "disabled"; |
| 723 | }; |
| 724 | |
| 725 | romcp@021ac000 { |
| 726 | reg = <0x021ac000 0x4000>; |
| 727 | }; |
| 728 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 729 | mmdc0: mmdc@021b0000 { /* MMDC0 */ |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 730 | compatible = "fsl,imx6q-mmdc"; |
| 731 | reg = <0x021b0000 0x4000>; |
| 732 | }; |
| 733 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 734 | mmdc1: mmdc@021b4000 { /* MMDC1 */ |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 735 | reg = <0x021b4000 0x4000>; |
| 736 | }; |
| 737 | |
| 738 | weim@021b8000 { |
| 739 | reg = <0x021b8000 0x4000>; |
| 740 | interrupts = <0 14 0x04>; |
| 741 | }; |
| 742 | |
| 743 | ocotp@021bc000 { |
Shawn Guo | 96574a6 | 2013-01-08 14:25:14 +0800 | [diff] [blame] | 744 | compatible = "fsl,imx6q-ocotp"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 745 | reg = <0x021bc000 0x4000>; |
| 746 | }; |
| 747 | |
| 748 | ocotp@021c0000 { |
| 749 | reg = <0x021c0000 0x4000>; |
| 750 | interrupts = <0 21 0x04>; |
| 751 | }; |
| 752 | |
| 753 | tzasc@021d0000 { /* TZASC1 */ |
| 754 | reg = <0x021d0000 0x4000>; |
| 755 | interrupts = <0 108 0x04>; |
| 756 | }; |
| 757 | |
| 758 | tzasc@021d4000 { /* TZASC2 */ |
| 759 | reg = <0x021d4000 0x4000>; |
| 760 | interrupts = <0 109 0x04>; |
| 761 | }; |
| 762 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 763 | audmux: audmux@021d8000 { |
Richard Zhao | f965cd5 | 2012-05-02 10:32:26 +0800 | [diff] [blame] | 764 | compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 765 | reg = <0x021d8000 0x4000>; |
Richard Zhao | f965cd5 | 2012-05-02 10:32:26 +0800 | [diff] [blame] | 766 | status = "disabled"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 767 | }; |
| 768 | |
| 769 | mipi@021dc000 { /* MIPI-CSI */ |
| 770 | reg = <0x021dc000 0x4000>; |
| 771 | }; |
| 772 | |
| 773 | mipi@021e0000 { /* MIPI-DSI */ |
| 774 | reg = <0x021e0000 0x4000>; |
| 775 | }; |
| 776 | |
| 777 | vdoa@021e4000 { |
| 778 | reg = <0x021e4000 0x4000>; |
| 779 | interrupts = <0 18 0x04>; |
| 780 | }; |
| 781 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 782 | uart2: serial@021e8000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 783 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 784 | reg = <0x021e8000 0x4000>; |
| 785 | interrupts = <0 27 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 786 | clocks = <&clks 160>, <&clks 161>; |
| 787 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 788 | status = "disabled"; |
| 789 | }; |
| 790 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 791 | uart3: serial@021ec000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 792 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 793 | reg = <0x021ec000 0x4000>; |
| 794 | interrupts = <0 28 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 795 | clocks = <&clks 160>, <&clks 161>; |
| 796 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 797 | status = "disabled"; |
| 798 | }; |
| 799 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 800 | uart4: serial@021f0000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 801 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 802 | reg = <0x021f0000 0x4000>; |
| 803 | interrupts = <0 29 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 804 | clocks = <&clks 160>, <&clks 161>; |
| 805 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 806 | status = "disabled"; |
| 807 | }; |
| 808 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 809 | uart5: serial@021f4000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 810 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 811 | reg = <0x021f4000 0x4000>; |
| 812 | interrupts = <0 30 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 813 | clocks = <&clks 160>, <&clks 161>; |
| 814 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 815 | status = "disabled"; |
| 816 | }; |
| 817 | }; |
Sascha Hauer | 91660d7 | 2012-11-12 15:52:21 +0100 | [diff] [blame] | 818 | |
| 819 | ipu1: ipu@02400000 { |
| 820 | #crtc-cells = <1>; |
| 821 | compatible = "fsl,imx6q-ipu"; |
| 822 | reg = <0x02400000 0x400000>; |
| 823 | interrupts = <0 6 0x4 0 5 0x4>; |
| 824 | clocks = <&clks 130>, <&clks 131>, <&clks 132>; |
| 825 | clock-names = "bus", "di0", "di1"; |
Philipp Zabel | 09ebf36 | 2013-03-28 17:35:20 +0100 | [diff] [blame^] | 826 | resets = <&src 2>; |
Sascha Hauer | 91660d7 | 2012-11-12 15:52:21 +0100 | [diff] [blame] | 827 | }; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 828 | }; |
| 829 | }; |