Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1 | /* |
Tomoya MORINAGA | eca9dfa | 2011-10-28 09:38:50 +0900 | [diff] [blame] | 2 | *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 3 | * |
| 4 | *This program is free software; you can redistribute it and/or modify |
| 5 | *it under the terms of the GNU General Public License as published by |
| 6 | *the Free Software Foundation; version 2 of the License. |
| 7 | * |
| 8 | *This program is distributed in the hope that it will be useful, |
| 9 | *but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | *GNU General Public License for more details. |
| 12 | * |
| 13 | *You should have received a copy of the GNU General Public License |
| 14 | *along with this program; if not, write to the Free Software |
| 15 | *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. |
| 16 | */ |
Liang Li | 1f9db09 | 2013-01-19 17:52:11 +0800 | [diff] [blame] | 17 | #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
| 18 | #define SUPPORT_SYSRQ |
| 19 | #endif |
Uwe Kleine-König | 0e2adc0 | 2011-05-26 10:41:17 +0200 | [diff] [blame] | 20 | #include <linux/kernel.h> |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 21 | #include <linux/serial_reg.h> |
Andrew Morton | 023bc8e | 2011-05-24 17:13:44 -0700 | [diff] [blame] | 22 | #include <linux/slab.h> |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 23 | #include <linux/module.h> |
| 24 | #include <linux/pci.h> |
Liang Li | 1f9db09 | 2013-01-19 17:52:11 +0800 | [diff] [blame] | 25 | #include <linux/console.h> |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 26 | #include <linux/serial_core.h> |
Jiri Slaby | ee160a3 | 2011-09-01 16:20:57 +0200 | [diff] [blame] | 27 | #include <linux/tty.h> |
| 28 | #include <linux/tty_flip.h> |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 29 | #include <linux/interrupt.h> |
| 30 | #include <linux/io.h> |
Denis Turischev | 6ae705b | 2011-03-10 15:14:00 +0200 | [diff] [blame] | 31 | #include <linux/dmi.h> |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 32 | #include <linux/nmi.h> |
| 33 | #include <linux/delay.h> |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 34 | |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 35 | #include <linux/debugfs.h> |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 36 | #include <linux/dmaengine.h> |
| 37 | #include <linux/pch_dma.h> |
| 38 | |
| 39 | enum { |
| 40 | PCH_UART_HANDLED_RX_INT_SHIFT, |
| 41 | PCH_UART_HANDLED_TX_INT_SHIFT, |
| 42 | PCH_UART_HANDLED_RX_ERR_INT_SHIFT, |
| 43 | PCH_UART_HANDLED_RX_TRG_INT_SHIFT, |
| 44 | PCH_UART_HANDLED_MS_INT_SHIFT, |
Tomoya MORINAGA | 04e2c2e | 2012-03-26 14:43:05 +0900 | [diff] [blame] | 45 | PCH_UART_HANDLED_LS_INT_SHIFT, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 46 | }; |
| 47 | |
| 48 | enum { |
| 49 | PCH_UART_8LINE, |
| 50 | PCH_UART_2LINE, |
| 51 | }; |
| 52 | |
| 53 | #define PCH_UART_DRIVER_DEVICE "ttyPCH" |
| 54 | |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 55 | /* Set the max number of UART port |
| 56 | * Intel EG20T PCH: 4 port |
Tomoya MORINAGA | eca9dfa | 2011-10-28 09:38:50 +0900 | [diff] [blame] | 57 | * LAPIS Semiconductor ML7213 IOH: 3 port |
| 58 | * LAPIS Semiconductor ML7223 IOH: 2 port |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 59 | */ |
| 60 | #define PCH_UART_NR 4 |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 61 | |
| 62 | #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) |
| 63 | #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) |
| 64 | #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ |
| 65 | PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) |
| 66 | #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ |
| 67 | PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) |
| 68 | #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) |
| 69 | |
Tomoya MORINAGA | 04e2c2e | 2012-03-26 14:43:05 +0900 | [diff] [blame] | 70 | #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1)) |
| 71 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 72 | #define PCH_UART_RBR 0x00 |
| 73 | #define PCH_UART_THR 0x00 |
| 74 | |
| 75 | #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ |
| 76 | PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) |
| 77 | #define PCH_UART_IER_ERBFI 0x00000001 |
| 78 | #define PCH_UART_IER_ETBEI 0x00000002 |
| 79 | #define PCH_UART_IER_ELSI 0x00000004 |
| 80 | #define PCH_UART_IER_EDSSI 0x00000008 |
| 81 | |
| 82 | #define PCH_UART_IIR_IP 0x00000001 |
| 83 | #define PCH_UART_IIR_IID 0x00000006 |
| 84 | #define PCH_UART_IIR_MSI 0x00000000 |
| 85 | #define PCH_UART_IIR_TRI 0x00000002 |
| 86 | #define PCH_UART_IIR_RRI 0x00000004 |
| 87 | #define PCH_UART_IIR_REI 0x00000006 |
| 88 | #define PCH_UART_IIR_TOI 0x00000008 |
| 89 | #define PCH_UART_IIR_FIFO256 0x00000020 |
| 90 | #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 |
| 91 | #define PCH_UART_IIR_FE 0x000000C0 |
| 92 | |
| 93 | #define PCH_UART_FCR_FIFOE 0x00000001 |
| 94 | #define PCH_UART_FCR_RFR 0x00000002 |
| 95 | #define PCH_UART_FCR_TFR 0x00000004 |
| 96 | #define PCH_UART_FCR_DMS 0x00000008 |
| 97 | #define PCH_UART_FCR_FIFO256 0x00000020 |
| 98 | #define PCH_UART_FCR_RFTL 0x000000C0 |
| 99 | |
| 100 | #define PCH_UART_FCR_RFTL1 0x00000000 |
| 101 | #define PCH_UART_FCR_RFTL64 0x00000040 |
| 102 | #define PCH_UART_FCR_RFTL128 0x00000080 |
| 103 | #define PCH_UART_FCR_RFTL224 0x000000C0 |
| 104 | #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 |
| 105 | #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 |
| 106 | #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 |
| 107 | #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 |
| 108 | #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 |
| 109 | #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 |
| 110 | #define PCH_UART_FCR_RFTL_SHIFT 6 |
| 111 | |
| 112 | #define PCH_UART_LCR_WLS 0x00000003 |
| 113 | #define PCH_UART_LCR_STB 0x00000004 |
| 114 | #define PCH_UART_LCR_PEN 0x00000008 |
| 115 | #define PCH_UART_LCR_EPS 0x00000010 |
| 116 | #define PCH_UART_LCR_SP 0x00000020 |
| 117 | #define PCH_UART_LCR_SB 0x00000040 |
| 118 | #define PCH_UART_LCR_DLAB 0x00000080 |
| 119 | #define PCH_UART_LCR_NP 0x00000000 |
| 120 | #define PCH_UART_LCR_OP PCH_UART_LCR_PEN |
| 121 | #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) |
| 122 | #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) |
| 123 | #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ |
| 124 | PCH_UART_LCR_SP) |
| 125 | |
| 126 | #define PCH_UART_LCR_5BIT 0x00000000 |
| 127 | #define PCH_UART_LCR_6BIT 0x00000001 |
| 128 | #define PCH_UART_LCR_7BIT 0x00000002 |
| 129 | #define PCH_UART_LCR_8BIT 0x00000003 |
| 130 | |
| 131 | #define PCH_UART_MCR_DTR 0x00000001 |
| 132 | #define PCH_UART_MCR_RTS 0x00000002 |
| 133 | #define PCH_UART_MCR_OUT 0x0000000C |
| 134 | #define PCH_UART_MCR_LOOP 0x00000010 |
| 135 | #define PCH_UART_MCR_AFE 0x00000020 |
| 136 | |
| 137 | #define PCH_UART_LSR_DR 0x00000001 |
| 138 | #define PCH_UART_LSR_ERR (1<<7) |
| 139 | |
| 140 | #define PCH_UART_MSR_DCTS 0x00000001 |
| 141 | #define PCH_UART_MSR_DDSR 0x00000002 |
| 142 | #define PCH_UART_MSR_TERI 0x00000004 |
| 143 | #define PCH_UART_MSR_DDCD 0x00000008 |
| 144 | #define PCH_UART_MSR_CTS 0x00000010 |
| 145 | #define PCH_UART_MSR_DSR 0x00000020 |
| 146 | #define PCH_UART_MSR_RI 0x00000040 |
| 147 | #define PCH_UART_MSR_DCD 0x00000080 |
| 148 | #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ |
| 149 | PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) |
| 150 | |
| 151 | #define PCH_UART_DLL 0x00 |
| 152 | #define PCH_UART_DLM 0x01 |
| 153 | |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 154 | #define PCH_UART_BRCSR 0x0E |
| 155 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 156 | #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) |
| 157 | #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) |
| 158 | #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) |
| 159 | #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) |
| 160 | #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) |
| 161 | |
| 162 | #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) |
| 163 | #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) |
| 164 | #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) |
| 165 | #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) |
| 166 | #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) |
| 167 | #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) |
| 168 | #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) |
| 169 | #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) |
| 170 | #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) |
| 171 | #define PCH_UART_HAL_STB1 0 |
| 172 | #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) |
| 173 | |
| 174 | #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) |
| 175 | #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) |
| 176 | #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ |
| 177 | PCH_UART_HAL_CLR_RX_FIFO) |
| 178 | |
| 179 | #define PCH_UART_HAL_DMA_MODE0 0 |
| 180 | #define PCH_UART_HAL_FIFO_DIS 0 |
| 181 | #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) |
| 182 | #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ |
| 183 | PCH_UART_FCR_FIFO256) |
| 184 | #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) |
| 185 | #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) |
| 186 | #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) |
| 187 | #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) |
| 188 | #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) |
| 189 | #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) |
| 190 | #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) |
| 191 | #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) |
| 192 | #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) |
| 193 | #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) |
| 194 | #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) |
| 195 | #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) |
| 196 | #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) |
| 197 | #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) |
| 198 | |
| 199 | #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) |
| 200 | #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) |
| 201 | #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) |
| 202 | #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) |
| 203 | #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) |
| 204 | |
| 205 | #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) |
| 206 | #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) |
| 207 | #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) |
| 208 | #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) |
| 209 | #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) |
| 210 | |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 211 | #define PCI_VENDOR_ID_ROHM 0x10DB |
| 212 | |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 213 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
| 214 | |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 215 | #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */ |
| 216 | #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */ |
| 217 | #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */ |
| 218 | #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */ |
Michael Brunner | 11bbd5b | 2012-03-23 11:06:37 +0100 | [diff] [blame] | 219 | #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */ |
Darren Hart | 29692d0 | 2013-06-25 18:53:22 -0700 | [diff] [blame] | 220 | #define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */ |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 221 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 222 | struct pch_uart_buffer { |
| 223 | unsigned char *buf; |
| 224 | int size; |
| 225 | }; |
| 226 | |
| 227 | struct eg20t_port { |
| 228 | struct uart_port port; |
| 229 | int port_type; |
| 230 | void __iomem *membase; |
| 231 | resource_size_t mapbase; |
| 232 | unsigned int iobase; |
| 233 | struct pci_dev *pdev; |
| 234 | int fifo_size; |
Darren Hart | a8a3ec9 | 2012-03-09 09:51:48 -0800 | [diff] [blame] | 235 | int uartclk; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 236 | int start_tx; |
| 237 | int start_rx; |
| 238 | int tx_empty; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 239 | int trigger; |
| 240 | int trigger_level; |
| 241 | struct pch_uart_buffer rxbuf; |
| 242 | unsigned int dmsr; |
| 243 | unsigned int fcr; |
Tomoya MORINAGA | 9af7155 | 2011-02-23 10:03:17 +0900 | [diff] [blame] | 244 | unsigned int mcr; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 245 | unsigned int use_dma; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 246 | struct dma_async_tx_descriptor *desc_tx; |
| 247 | struct dma_async_tx_descriptor *desc_rx; |
| 248 | struct pch_dma_slave param_tx; |
| 249 | struct pch_dma_slave param_rx; |
| 250 | struct dma_chan *chan_tx; |
| 251 | struct dma_chan *chan_rx; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 252 | struct scatterlist *sg_tx_p; |
| 253 | int nent; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 254 | struct scatterlist sg_rx; |
| 255 | int tx_dma_use; |
| 256 | void *rx_buf_virt; |
| 257 | dma_addr_t rx_buf_dma; |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 258 | |
| 259 | struct dentry *debugfs; |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 260 | |
| 261 | /* protect the eg20t_port private structure and io access to membase */ |
| 262 | spinlock_t lock; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 263 | }; |
| 264 | |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 265 | /** |
| 266 | * struct pch_uart_driver_data - private data structure for UART-DMA |
| 267 | * @port_type: The number of DMA channel |
| 268 | * @line_no: UART port line number (0, 1, 2...) |
| 269 | */ |
| 270 | struct pch_uart_driver_data { |
| 271 | int port_type; |
| 272 | int line_no; |
| 273 | }; |
| 274 | |
| 275 | enum pch_uart_num_t { |
| 276 | pch_et20t_uart0 = 0, |
| 277 | pch_et20t_uart1, |
| 278 | pch_et20t_uart2, |
| 279 | pch_et20t_uart3, |
| 280 | pch_ml7213_uart0, |
| 281 | pch_ml7213_uart1, |
| 282 | pch_ml7213_uart2, |
Tomoya MORINAGA | 177c2cb | 2011-05-09 17:25:20 +0900 | [diff] [blame] | 283 | pch_ml7223_uart0, |
| 284 | pch_ml7223_uart1, |
Tomoya MORINAGA | 8249f74 | 2011-10-28 09:38:49 +0900 | [diff] [blame] | 285 | pch_ml7831_uart0, |
| 286 | pch_ml7831_uart1, |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 287 | }; |
| 288 | |
| 289 | static struct pch_uart_driver_data drv_dat[] = { |
| 290 | [pch_et20t_uart0] = {PCH_UART_8LINE, 0}, |
| 291 | [pch_et20t_uart1] = {PCH_UART_2LINE, 1}, |
| 292 | [pch_et20t_uart2] = {PCH_UART_2LINE, 2}, |
| 293 | [pch_et20t_uart3] = {PCH_UART_2LINE, 3}, |
| 294 | [pch_ml7213_uart0] = {PCH_UART_8LINE, 0}, |
| 295 | [pch_ml7213_uart1] = {PCH_UART_2LINE, 1}, |
| 296 | [pch_ml7213_uart2] = {PCH_UART_2LINE, 2}, |
Tomoya MORINAGA | 177c2cb | 2011-05-09 17:25:20 +0900 | [diff] [blame] | 297 | [pch_ml7223_uart0] = {PCH_UART_8LINE, 0}, |
| 298 | [pch_ml7223_uart1] = {PCH_UART_2LINE, 1}, |
Tomoya MORINAGA | 8249f74 | 2011-10-28 09:38:49 +0900 | [diff] [blame] | 299 | [pch_ml7831_uart0] = {PCH_UART_8LINE, 0}, |
| 300 | [pch_ml7831_uart1] = {PCH_UART_2LINE, 1}, |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 301 | }; |
| 302 | |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 303 | #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE |
| 304 | static struct eg20t_port *pch_uart_ports[PCH_UART_NR]; |
| 305 | #endif |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 306 | static unsigned int default_baud = 9600; |
Darren Hart | 2a44feb | 2012-03-09 09:51:50 -0800 | [diff] [blame] | 307 | static unsigned int user_uartclk = 0; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 308 | static const int trigger_level_256[4] = { 1, 64, 128, 224 }; |
| 309 | static const int trigger_level_64[4] = { 1, 16, 32, 56 }; |
| 310 | static const int trigger_level_16[4] = { 1, 4, 8, 14 }; |
| 311 | static const int trigger_level_1[4] = { 1, 1, 1, 1 }; |
| 312 | |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 313 | #ifdef CONFIG_DEBUG_FS |
| 314 | |
| 315 | #define PCH_REGS_BUFSIZE 1024 |
Stephen Boyd | 234e340 | 2012-04-05 14:25:11 -0700 | [diff] [blame] | 316 | |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 317 | |
| 318 | static ssize_t port_show_regs(struct file *file, char __user *user_buf, |
| 319 | size_t count, loff_t *ppos) |
| 320 | { |
| 321 | struct eg20t_port *priv = file->private_data; |
| 322 | char *buf; |
| 323 | u32 len = 0; |
| 324 | ssize_t ret; |
| 325 | unsigned char lcr; |
| 326 | |
| 327 | buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL); |
| 328 | if (!buf) |
| 329 | return 0; |
| 330 | |
| 331 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 332 | "PCH EG20T port[%d] regs:\n", priv->port.line); |
| 333 | |
| 334 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 335 | "=================================\n"); |
| 336 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 337 | "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); |
| 338 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 339 | "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); |
| 340 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 341 | "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); |
| 342 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 343 | "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); |
| 344 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 345 | "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); |
| 346 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 347 | "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); |
| 348 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 349 | "BRCSR: \t0x%02x\n", |
| 350 | ioread8(priv->membase + PCH_UART_BRCSR)); |
| 351 | |
| 352 | lcr = ioread8(priv->membase + UART_LCR); |
| 353 | iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); |
| 354 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 355 | "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); |
| 356 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 357 | "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); |
| 358 | iowrite8(lcr, priv->membase + UART_LCR); |
| 359 | |
| 360 | if (len > PCH_REGS_BUFSIZE) |
| 361 | len = PCH_REGS_BUFSIZE; |
| 362 | |
| 363 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); |
| 364 | kfree(buf); |
| 365 | return ret; |
| 366 | } |
| 367 | |
| 368 | static const struct file_operations port_regs_ops = { |
| 369 | .owner = THIS_MODULE, |
Stephen Boyd | 234e340 | 2012-04-05 14:25:11 -0700 | [diff] [blame] | 370 | .open = simple_open, |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 371 | .read = port_show_regs, |
| 372 | .llseek = default_llseek, |
| 373 | }; |
| 374 | #endif /* CONFIG_DEBUG_FS */ |
| 375 | |
Darren Hart | 4e32348 | 2013-07-12 17:58:05 -0700 | [diff] [blame] | 376 | static struct dmi_system_id __initdata pch_uart_dmi_table[] = { |
| 377 | { |
| 378 | .ident = "CM-iTC", |
| 379 | { |
| 380 | DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"), |
| 381 | }, |
| 382 | (void *)CMITC_UARTCLK, |
| 383 | }, |
| 384 | { |
| 385 | .ident = "FRI2", |
| 386 | { |
| 387 | DMI_MATCH(DMI_BIOS_VERSION, "FRI2"), |
| 388 | }, |
| 389 | (void *)FRI2_64_UARTCLK, |
| 390 | }, |
| 391 | { |
| 392 | .ident = "Fish River Island II", |
| 393 | { |
| 394 | DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"), |
| 395 | }, |
| 396 | (void *)FRI2_48_UARTCLK, |
| 397 | }, |
| 398 | { |
| 399 | .ident = "COMe-mTT", |
| 400 | { |
| 401 | DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"), |
| 402 | }, |
| 403 | (void *)NTC1_UARTCLK, |
| 404 | }, |
| 405 | { |
| 406 | .ident = "nanoETXexpress-TT", |
| 407 | { |
| 408 | DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"), |
| 409 | }, |
| 410 | (void *)NTC1_UARTCLK, |
| 411 | }, |
| 412 | { |
| 413 | .ident = "MinnowBoard", |
| 414 | { |
| 415 | DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"), |
| 416 | }, |
| 417 | (void *)MINNOW_UARTCLK, |
| 418 | }, |
| 419 | }; |
| 420 | |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 421 | /* Return UART clock, checking for board specific clocks. */ |
| 422 | static int pch_uart_get_uartclk(void) |
| 423 | { |
Darren Hart | 4e32348 | 2013-07-12 17:58:05 -0700 | [diff] [blame] | 424 | const struct dmi_system_id *d; |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 425 | |
Darren Hart | 2a44feb | 2012-03-09 09:51:50 -0800 | [diff] [blame] | 426 | if (user_uartclk) |
| 427 | return user_uartclk; |
| 428 | |
Darren Hart | 4e32348 | 2013-07-12 17:58:05 -0700 | [diff] [blame] | 429 | d = dmi_first_match(pch_uart_dmi_table); |
| 430 | if (d) |
| 431 | return (int)d->driver_data; |
Darren Hart | 29692d0 | 2013-06-25 18:53:22 -0700 | [diff] [blame] | 432 | |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 433 | return DEFAULT_UARTCLK; |
| 434 | } |
| 435 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 436 | static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, |
| 437 | unsigned int flag) |
| 438 | { |
| 439 | u8 ier = ioread8(priv->membase + UART_IER); |
| 440 | ier |= flag & PCH_UART_IER_MASK; |
| 441 | iowrite8(ier, priv->membase + UART_IER); |
| 442 | } |
| 443 | |
| 444 | static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, |
| 445 | unsigned int flag) |
| 446 | { |
| 447 | u8 ier = ioread8(priv->membase + UART_IER); |
| 448 | ier &= ~(flag & PCH_UART_IER_MASK); |
| 449 | iowrite8(ier, priv->membase + UART_IER); |
| 450 | } |
| 451 | |
| 452 | static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud, |
| 453 | unsigned int parity, unsigned int bits, |
| 454 | unsigned int stb) |
| 455 | { |
| 456 | unsigned int dll, dlm, lcr; |
| 457 | int div; |
| 458 | |
Darren Hart | a8a3ec9 | 2012-03-09 09:51:48 -0800 | [diff] [blame] | 459 | div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 460 | if (div < 0 || USHRT_MAX <= div) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 461 | dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 462 | return -EINVAL; |
| 463 | } |
| 464 | |
| 465 | dll = (unsigned int)div & 0x00FFU; |
| 466 | dlm = ((unsigned int)div >> 8) & 0x00FFU; |
| 467 | |
| 468 | if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 469 | dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 470 | return -EINVAL; |
| 471 | } |
| 472 | |
| 473 | if (bits & ~PCH_UART_LCR_WLS) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 474 | dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 475 | return -EINVAL; |
| 476 | } |
| 477 | |
| 478 | if (stb & ~PCH_UART_LCR_STB) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 479 | dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 480 | return -EINVAL; |
| 481 | } |
| 482 | |
| 483 | lcr = parity; |
| 484 | lcr |= bits; |
| 485 | lcr |= stb; |
| 486 | |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 487 | dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n", |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 488 | __func__, baud, div, lcr, jiffies); |
| 489 | iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); |
| 490 | iowrite8(dll, priv->membase + PCH_UART_DLL); |
| 491 | iowrite8(dlm, priv->membase + PCH_UART_DLM); |
| 492 | iowrite8(lcr, priv->membase + UART_LCR); |
| 493 | |
| 494 | return 0; |
| 495 | } |
| 496 | |
| 497 | static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, |
| 498 | unsigned int flag) |
| 499 | { |
| 500 | if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 501 | dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", |
| 502 | __func__, flag); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 503 | return -EINVAL; |
| 504 | } |
| 505 | |
| 506 | iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); |
| 507 | iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, |
| 508 | priv->membase + UART_FCR); |
| 509 | iowrite8(priv->fcr, priv->membase + UART_FCR); |
| 510 | |
| 511 | return 0; |
| 512 | } |
| 513 | |
| 514 | static int pch_uart_hal_set_fifo(struct eg20t_port *priv, |
| 515 | unsigned int dmamode, |
| 516 | unsigned int fifo_size, unsigned int trigger) |
| 517 | { |
| 518 | u8 fcr; |
| 519 | |
| 520 | if (dmamode & ~PCH_UART_FCR_DMS) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 521 | dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", |
| 522 | __func__, dmamode); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 523 | return -EINVAL; |
| 524 | } |
| 525 | |
| 526 | if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 527 | dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", |
| 528 | __func__, fifo_size); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 529 | return -EINVAL; |
| 530 | } |
| 531 | |
| 532 | if (trigger & ~PCH_UART_FCR_RFTL) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 533 | dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", |
| 534 | __func__, trigger); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 535 | return -EINVAL; |
| 536 | } |
| 537 | |
| 538 | switch (priv->fifo_size) { |
| 539 | case 256: |
| 540 | priv->trigger_level = |
| 541 | trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; |
| 542 | break; |
| 543 | case 64: |
| 544 | priv->trigger_level = |
| 545 | trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; |
| 546 | break; |
| 547 | case 16: |
| 548 | priv->trigger_level = |
| 549 | trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; |
| 550 | break; |
| 551 | default: |
| 552 | priv->trigger_level = |
| 553 | trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; |
| 554 | break; |
| 555 | } |
| 556 | fcr = |
| 557 | dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; |
| 558 | iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); |
| 559 | iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, |
| 560 | priv->membase + UART_FCR); |
| 561 | iowrite8(fcr, priv->membase + UART_FCR); |
| 562 | priv->fcr = fcr; |
| 563 | |
| 564 | return 0; |
| 565 | } |
| 566 | |
| 567 | static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) |
| 568 | { |
Feng Tang | 30c6c6b | 2012-02-06 17:24:44 +0800 | [diff] [blame] | 569 | unsigned int msr = ioread8(priv->membase + UART_MSR); |
| 570 | priv->dmsr = msr & PCH_UART_MSR_DELTA; |
| 571 | return (u8)msr; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 572 | } |
| 573 | |
Tomoya MORINAGA | 1822076 | 2011-02-23 10:03:14 +0900 | [diff] [blame] | 574 | static void pch_uart_hal_write(struct eg20t_port *priv, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 575 | const unsigned char *buf, int tx_size) |
| 576 | { |
| 577 | int i; |
| 578 | unsigned int thr; |
| 579 | |
| 580 | for (i = 0; i < tx_size;) { |
| 581 | thr = buf[i++]; |
| 582 | iowrite8(thr, priv->membase + PCH_UART_THR); |
| 583 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 584 | } |
| 585 | |
| 586 | static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, |
| 587 | int rx_size) |
| 588 | { |
| 589 | int i; |
| 590 | u8 rbr, lsr; |
Liang Li | 1f9db09 | 2013-01-19 17:52:11 +0800 | [diff] [blame] | 591 | struct uart_port *port = &priv->port; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 592 | |
| 593 | lsr = ioread8(priv->membase + UART_LSR); |
| 594 | for (i = 0, lsr = ioread8(priv->membase + UART_LSR); |
Liang Li | 1f9db09 | 2013-01-19 17:52:11 +0800 | [diff] [blame] | 595 | i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 596 | lsr = ioread8(priv->membase + UART_LSR)) { |
| 597 | rbr = ioread8(priv->membase + PCH_UART_RBR); |
Liang Li | 1f9db09 | 2013-01-19 17:52:11 +0800 | [diff] [blame] | 598 | |
| 599 | if (lsr & UART_LSR_BI) { |
| 600 | port->icount.brk++; |
| 601 | if (uart_handle_break(port)) |
| 602 | continue; |
| 603 | } |
Liang Li | e8c5b56 | 2013-01-24 12:31:27 +0800 | [diff] [blame] | 604 | #ifdef SUPPORT_SYSRQ |
Liang Li | 1f9db09 | 2013-01-19 17:52:11 +0800 | [diff] [blame] | 605 | if (port->sysrq) { |
| 606 | if (uart_handle_sysrq_char(port, rbr)) |
| 607 | continue; |
| 608 | } |
Liang Li | e8c5b56 | 2013-01-24 12:31:27 +0800 | [diff] [blame] | 609 | #endif |
Liang Li | 1f9db09 | 2013-01-19 17:52:11 +0800 | [diff] [blame] | 610 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 611 | buf[i++] = rbr; |
| 612 | } |
| 613 | return i; |
| 614 | } |
| 615 | |
Tomoya MORINAGA | 2a58364 | 2012-03-26 14:43:01 +0900 | [diff] [blame] | 616 | static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv) |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 617 | { |
Tomoya MORINAGA | 2a58364 | 2012-03-26 14:43:01 +0900 | [diff] [blame] | 618 | return ioread8(priv->membase + UART_IIR) &\ |
| 619 | (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 620 | } |
| 621 | |
| 622 | static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) |
| 623 | { |
| 624 | return ioread8(priv->membase + UART_LSR); |
| 625 | } |
| 626 | |
| 627 | static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) |
| 628 | { |
| 629 | unsigned int lcr; |
| 630 | |
| 631 | lcr = ioread8(priv->membase + UART_LCR); |
| 632 | if (on) |
| 633 | lcr |= PCH_UART_LCR_SB; |
| 634 | else |
| 635 | lcr &= ~PCH_UART_LCR_SB; |
| 636 | |
| 637 | iowrite8(lcr, priv->membase + UART_LCR); |
| 638 | } |
| 639 | |
| 640 | static int push_rx(struct eg20t_port *priv, const unsigned char *buf, |
| 641 | int size) |
| 642 | { |
Jiri Slaby | 05c7cd3 | 2013-01-03 15:53:04 +0100 | [diff] [blame] | 643 | struct uart_port *port = &priv->port; |
| 644 | struct tty_port *tport = &port->state->port; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 645 | |
Jiri Slaby | 05c7cd3 | 2013-01-03 15:53:04 +0100 | [diff] [blame] | 646 | tty_insert_flip_string(tport, buf, size); |
Jiri Slaby | 2e124b4 | 2013-01-03 15:53:06 +0100 | [diff] [blame] | 647 | tty_flip_buffer_push(tport); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 648 | |
| 649 | return 0; |
| 650 | } |
| 651 | |
| 652 | static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf) |
| 653 | { |
Feng Tang | 30c6c6b | 2012-02-06 17:24:44 +0800 | [diff] [blame] | 654 | int ret = 0; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 655 | struct uart_port *port = &priv->port; |
| 656 | |
| 657 | if (port->x_char) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 658 | dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n", |
| 659 | __func__, port->x_char, jiffies); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 660 | buf[0] = port->x_char; |
| 661 | port->x_char = 0; |
| 662 | ret = 1; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 663 | } |
| 664 | |
| 665 | return ret; |
| 666 | } |
| 667 | |
| 668 | static int dma_push_rx(struct eg20t_port *priv, int size) |
| 669 | { |
| 670 | struct tty_struct *tty; |
| 671 | int room; |
| 672 | struct uart_port *port = &priv->port; |
Jiri Slaby | 227434f | 2013-01-03 15:53:01 +0100 | [diff] [blame] | 673 | struct tty_port *tport = &port->state->port; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 674 | |
| 675 | port = &priv->port; |
Jiri Slaby | 227434f | 2013-01-03 15:53:01 +0100 | [diff] [blame] | 676 | tty = tty_port_tty_get(tport); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 677 | if (!tty) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 678 | dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 679 | return 0; |
| 680 | } |
| 681 | |
Jiri Slaby | 227434f | 2013-01-03 15:53:01 +0100 | [diff] [blame] | 682 | room = tty_buffer_request_room(tport, size); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 683 | |
| 684 | if (room < size) |
| 685 | dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", |
| 686 | size - room); |
| 687 | if (!room) |
| 688 | return room; |
| 689 | |
Jiri Slaby | 05c7cd3 | 2013-01-03 15:53:04 +0100 | [diff] [blame] | 690 | tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 691 | |
| 692 | port->icount.rx += room; |
| 693 | tty_kref_put(tty); |
| 694 | |
| 695 | return room; |
| 696 | } |
| 697 | |
| 698 | static void pch_free_dma(struct uart_port *port) |
| 699 | { |
| 700 | struct eg20t_port *priv; |
| 701 | priv = container_of(port, struct eg20t_port, port); |
| 702 | |
| 703 | if (priv->chan_tx) { |
| 704 | dma_release_channel(priv->chan_tx); |
| 705 | priv->chan_tx = NULL; |
| 706 | } |
| 707 | if (priv->chan_rx) { |
| 708 | dma_release_channel(priv->chan_rx); |
| 709 | priv->chan_rx = NULL; |
| 710 | } |
Tomoya MORINAGA | ef4f9d4 | 2012-03-26 14:43:06 +0900 | [diff] [blame] | 711 | |
| 712 | if (priv->rx_buf_dma) { |
| 713 | dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt, |
| 714 | priv->rx_buf_dma); |
| 715 | priv->rx_buf_virt = NULL; |
| 716 | priv->rx_buf_dma = 0; |
| 717 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 718 | |
| 719 | return; |
| 720 | } |
| 721 | |
| 722 | static bool filter(struct dma_chan *chan, void *slave) |
| 723 | { |
| 724 | struct pch_dma_slave *param = slave; |
| 725 | |
| 726 | if ((chan->chan_id == param->chan_id) && (param->dma_dev == |
| 727 | chan->device->dev)) { |
| 728 | chan->private = param; |
| 729 | return true; |
| 730 | } else { |
| 731 | return false; |
| 732 | } |
| 733 | } |
| 734 | |
| 735 | static void pch_request_dma(struct uart_port *port) |
| 736 | { |
| 737 | dma_cap_mask_t mask; |
| 738 | struct dma_chan *chan; |
| 739 | struct pci_dev *dma_dev; |
| 740 | struct pch_dma_slave *param; |
| 741 | struct eg20t_port *priv = |
| 742 | container_of(port, struct eg20t_port, port); |
| 743 | dma_cap_zero(mask); |
| 744 | dma_cap_set(DMA_SLAVE, mask); |
| 745 | |
Tomoya MORINAGA | 6c4b47d | 2011-07-20 20:17:49 +0900 | [diff] [blame] | 746 | dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number, |
| 747 | PCI_DEVFN(0xa, 0)); /* Get DMA's dev |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 748 | information */ |
| 749 | /* Set Tx DMA */ |
| 750 | param = &priv->param_tx; |
| 751 | param->dma_dev = &dma_dev->dev; |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 752 | param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ |
| 753 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 754 | param->tx_reg = port->mapbase + UART_TX; |
| 755 | chan = dma_request_channel(mask, filter, param); |
| 756 | if (!chan) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 757 | dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", |
| 758 | __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 759 | return; |
| 760 | } |
| 761 | priv->chan_tx = chan; |
| 762 | |
| 763 | /* Set Rx DMA */ |
| 764 | param = &priv->param_rx; |
| 765 | param->dma_dev = &dma_dev->dev; |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 766 | param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ |
| 767 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 768 | param->rx_reg = port->mapbase + UART_RX; |
| 769 | chan = dma_request_channel(mask, filter, param); |
| 770 | if (!chan) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 771 | dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", |
| 772 | __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 773 | dma_release_channel(priv->chan_tx); |
Tomoya MORINAGA | 90f04c2 | 2011-11-11 10:55:27 +0900 | [diff] [blame] | 774 | priv->chan_tx = NULL; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 775 | return; |
| 776 | } |
| 777 | |
| 778 | /* Get Consistent memory for DMA */ |
| 779 | priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, |
| 780 | &priv->rx_buf_dma, GFP_KERNEL); |
| 781 | priv->chan_rx = chan; |
| 782 | } |
| 783 | |
| 784 | static void pch_dma_rx_complete(void *arg) |
| 785 | { |
| 786 | struct eg20t_port *priv = arg; |
| 787 | struct uart_port *port = &priv->port; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 788 | int count; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 789 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 790 | dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); |
| 791 | count = dma_push_rx(priv, priv->trigger_level); |
| 792 | if (count) |
Jiri Slaby | 2e124b4 | 2013-01-03 15:53:06 +0100 | [diff] [blame] | 793 | tty_flip_buffer_push(&port->state->port); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 794 | async_tx_ack(priv->desc_rx); |
Tomoya MORINAGA | ae213f3 | 2012-07-06 17:19:42 +0900 | [diff] [blame] | 795 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | |
| 796 | PCH_UART_HAL_RX_ERR_INT); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 797 | } |
| 798 | |
| 799 | static void pch_dma_tx_complete(void *arg) |
| 800 | { |
| 801 | struct eg20t_port *priv = arg; |
| 802 | struct uart_port *port = &priv->port; |
| 803 | struct circ_buf *xmit = &port->state->xmit; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 804 | struct scatterlist *sg = priv->sg_tx_p; |
| 805 | int i; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 806 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 807 | for (i = 0; i < priv->nent; i++, sg++) { |
| 808 | xmit->tail += sg_dma_len(sg); |
| 809 | port->icount.tx += sg_dma_len(sg); |
| 810 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 811 | xmit->tail &= UART_XMIT_SIZE - 1; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 812 | async_tx_ack(priv->desc_tx); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 813 | dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 814 | priv->tx_dma_use = 0; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 815 | priv->nent = 0; |
| 816 | kfree(priv->sg_tx_p); |
Tomoya MORINAGA | 60d1031 | 2011-02-23 10:03:18 +0900 | [diff] [blame] | 817 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 818 | } |
| 819 | |
Tomoya MORINAGA | 1822076 | 2011-02-23 10:03:14 +0900 | [diff] [blame] | 820 | static int pop_tx(struct eg20t_port *priv, int size) |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 821 | { |
| 822 | int count = 0; |
| 823 | struct uart_port *port = &priv->port; |
| 824 | struct circ_buf *xmit = &port->state->xmit; |
| 825 | |
| 826 | if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size) |
| 827 | goto pop_tx_end; |
| 828 | |
| 829 | do { |
| 830 | int cnt_to_end = |
| 831 | CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); |
| 832 | int sz = min(size - count, cnt_to_end); |
Tomoya MORINAGA | 1822076 | 2011-02-23 10:03:14 +0900 | [diff] [blame] | 833 | pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 834 | xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1); |
| 835 | count += sz; |
| 836 | } while (!uart_circ_empty(xmit) && count < size); |
| 837 | |
| 838 | pop_tx_end: |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 839 | dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n", |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 840 | count, size - count, jiffies); |
| 841 | |
| 842 | return count; |
| 843 | } |
| 844 | |
| 845 | static int handle_rx_to(struct eg20t_port *priv) |
| 846 | { |
| 847 | struct pch_uart_buffer *buf; |
| 848 | int rx_size; |
| 849 | int ret; |
| 850 | if (!priv->start_rx) { |
Tomoya MORINAGA | ae213f3 | 2012-07-06 17:19:42 +0900 | [diff] [blame] | 851 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | |
| 852 | PCH_UART_HAL_RX_ERR_INT); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 853 | return 0; |
| 854 | } |
| 855 | buf = &priv->rxbuf; |
| 856 | do { |
| 857 | rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); |
| 858 | ret = push_rx(priv, buf->buf, rx_size); |
| 859 | if (ret) |
| 860 | return 0; |
| 861 | } while (rx_size == buf->size); |
| 862 | |
| 863 | return PCH_UART_HANDLED_RX_INT; |
| 864 | } |
| 865 | |
| 866 | static int handle_rx(struct eg20t_port *priv) |
| 867 | { |
| 868 | return handle_rx_to(priv); |
| 869 | } |
| 870 | |
| 871 | static int dma_handle_rx(struct eg20t_port *priv) |
| 872 | { |
| 873 | struct uart_port *port = &priv->port; |
| 874 | struct dma_async_tx_descriptor *desc; |
| 875 | struct scatterlist *sg; |
| 876 | |
| 877 | priv = container_of(port, struct eg20t_port, port); |
| 878 | sg = &priv->sg_rx; |
| 879 | |
| 880 | sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ |
| 881 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 882 | sg_dma_len(sg) = priv->trigger_level; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 883 | |
| 884 | sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 885 | sg_dma_len(sg), (unsigned long)priv->rx_buf_virt & |
| 886 | ~PAGE_MASK); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 887 | |
| 888 | sg_dma_address(sg) = priv->rx_buf_dma; |
| 889 | |
Alexandre Bounine | 1605282 | 2012-03-08 16:11:18 -0500 | [diff] [blame] | 890 | desc = dmaengine_prep_slave_sg(priv->chan_rx, |
Vinod Koul | a485df4 | 2011-10-14 10:47:38 +0530 | [diff] [blame] | 891 | sg, 1, DMA_DEV_TO_MEM, |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 892 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 893 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 894 | if (!desc) |
| 895 | return 0; |
| 896 | |
| 897 | priv->desc_rx = desc; |
| 898 | desc->callback = pch_dma_rx_complete; |
| 899 | desc->callback_param = priv; |
| 900 | desc->tx_submit(desc); |
| 901 | dma_async_issue_pending(priv->chan_rx); |
| 902 | |
| 903 | return PCH_UART_HANDLED_RX_INT; |
| 904 | } |
| 905 | |
| 906 | static unsigned int handle_tx(struct eg20t_port *priv) |
| 907 | { |
| 908 | struct uart_port *port = &priv->port; |
| 909 | struct circ_buf *xmit = &port->state->xmit; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 910 | int fifo_size; |
| 911 | int tx_size; |
| 912 | int size; |
| 913 | int tx_empty; |
| 914 | |
| 915 | if (!priv->start_tx) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 916 | dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", |
| 917 | __func__, jiffies); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 918 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
| 919 | priv->tx_empty = 1; |
| 920 | return 0; |
| 921 | } |
| 922 | |
| 923 | fifo_size = max(priv->fifo_size, 1); |
| 924 | tx_empty = 1; |
| 925 | if (pop_tx_x(priv, xmit->buf)) { |
| 926 | pch_uart_hal_write(priv, xmit->buf, 1); |
| 927 | port->icount.tx++; |
| 928 | tx_empty = 0; |
| 929 | fifo_size--; |
| 930 | } |
| 931 | size = min(xmit->head - xmit->tail, fifo_size); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 932 | if (size < 0) |
| 933 | size = fifo_size; |
| 934 | |
Tomoya MORINAGA | 1822076 | 2011-02-23 10:03:14 +0900 | [diff] [blame] | 935 | tx_size = pop_tx(priv, size); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 936 | if (tx_size > 0) { |
Tomoya MORINAGA | 1822076 | 2011-02-23 10:03:14 +0900 | [diff] [blame] | 937 | port->icount.tx += tx_size; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 938 | tx_empty = 0; |
| 939 | } |
| 940 | |
| 941 | priv->tx_empty = tx_empty; |
| 942 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 943 | if (tx_empty) { |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 944 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 945 | uart_write_wakeup(port); |
| 946 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 947 | |
| 948 | return PCH_UART_HANDLED_TX_INT; |
| 949 | } |
| 950 | |
| 951 | static unsigned int dma_handle_tx(struct eg20t_port *priv) |
| 952 | { |
| 953 | struct uart_port *port = &priv->port; |
| 954 | struct circ_buf *xmit = &port->state->xmit; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 955 | struct scatterlist *sg; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 956 | int nent; |
| 957 | int fifo_size; |
| 958 | int tx_empty; |
| 959 | struct dma_async_tx_descriptor *desc; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 960 | int num; |
| 961 | int i; |
| 962 | int bytes; |
| 963 | int size; |
| 964 | int rem; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 965 | |
| 966 | if (!priv->start_tx) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 967 | dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", |
| 968 | __func__, jiffies); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 969 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
| 970 | priv->tx_empty = 1; |
| 971 | return 0; |
| 972 | } |
| 973 | |
Tomoya MORINAGA | 60d1031 | 2011-02-23 10:03:18 +0900 | [diff] [blame] | 974 | if (priv->tx_dma_use) { |
| 975 | dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", |
| 976 | __func__, jiffies); |
| 977 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
| 978 | priv->tx_empty = 1; |
| 979 | return 0; |
| 980 | } |
| 981 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 982 | fifo_size = max(priv->fifo_size, 1); |
| 983 | tx_empty = 1; |
| 984 | if (pop_tx_x(priv, xmit->buf)) { |
| 985 | pch_uart_hal_write(priv, xmit->buf, 1); |
| 986 | port->icount.tx++; |
| 987 | tx_empty = 0; |
| 988 | fifo_size--; |
| 989 | } |
| 990 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 991 | bytes = min((int)CIRC_CNT(xmit->head, xmit->tail, |
| 992 | UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head, |
| 993 | xmit->tail, UART_XMIT_SIZE)); |
| 994 | if (!bytes) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 995 | dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 996 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
| 997 | uart_write_wakeup(port); |
| 998 | return 0; |
| 999 | } |
| 1000 | |
| 1001 | if (bytes > fifo_size) { |
| 1002 | num = bytes / fifo_size + 1; |
| 1003 | size = fifo_size; |
| 1004 | rem = bytes % fifo_size; |
| 1005 | } else { |
| 1006 | num = 1; |
| 1007 | size = bytes; |
| 1008 | rem = bytes; |
| 1009 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1010 | |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1011 | dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", |
| 1012 | __func__, num, size, rem); |
| 1013 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1014 | priv->tx_dma_use = 1; |
| 1015 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1016 | priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); |
Fengguang Wu | a92098a | 2012-07-28 20:43:57 +0800 | [diff] [blame] | 1017 | if (!priv->sg_tx_p) { |
| 1018 | dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__); |
| 1019 | return 0; |
| 1020 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1021 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1022 | sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ |
| 1023 | sg = priv->sg_tx_p; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1024 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1025 | for (i = 0; i < num; i++, sg++) { |
| 1026 | if (i == (num - 1)) |
| 1027 | sg_set_page(sg, virt_to_page(xmit->buf), |
| 1028 | rem, fifo_size * i); |
| 1029 | else |
| 1030 | sg_set_page(sg, virt_to_page(xmit->buf), |
| 1031 | size, fifo_size * i); |
| 1032 | } |
| 1033 | |
| 1034 | sg = priv->sg_tx_p; |
| 1035 | nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1036 | if (!nent) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1037 | dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1038 | return 0; |
| 1039 | } |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1040 | priv->nent = nent; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1041 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1042 | for (i = 0; i < nent; i++, sg++) { |
| 1043 | sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) + |
| 1044 | fifo_size * i; |
| 1045 | sg_dma_address(sg) = (sg_dma_address(sg) & |
| 1046 | ~(UART_XMIT_SIZE - 1)) + sg->offset; |
| 1047 | if (i == (nent - 1)) |
| 1048 | sg_dma_len(sg) = rem; |
| 1049 | else |
| 1050 | sg_dma_len(sg) = size; |
| 1051 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1052 | |
Alexandre Bounine | 1605282 | 2012-03-08 16:11:18 -0500 | [diff] [blame] | 1053 | desc = dmaengine_prep_slave_sg(priv->chan_tx, |
Vinod Koul | a485df4 | 2011-10-14 10:47:38 +0530 | [diff] [blame] | 1054 | priv->sg_tx_p, nent, DMA_MEM_TO_DEV, |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1055 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1056 | if (!desc) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1057 | dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n", |
| 1058 | __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1059 | return 0; |
| 1060 | } |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1061 | dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1062 | priv->desc_tx = desc; |
| 1063 | desc->callback = pch_dma_tx_complete; |
| 1064 | desc->callback_param = priv; |
| 1065 | |
| 1066 | desc->tx_submit(desc); |
| 1067 | |
| 1068 | dma_async_issue_pending(priv->chan_tx); |
| 1069 | |
| 1070 | return PCH_UART_HANDLED_TX_INT; |
| 1071 | } |
| 1072 | |
| 1073 | static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) |
| 1074 | { |
Liang Li | 384e301 | 2013-01-19 17:52:10 +0800 | [diff] [blame] | 1075 | struct uart_port *port = &priv->port; |
| 1076 | struct tty_struct *tty = tty_port_tty_get(&port->state->port); |
| 1077 | char *error_msg[5] = {}; |
| 1078 | int i = 0; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1079 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1080 | if (lsr & PCH_UART_LSR_ERR) |
Liang Li | 384e301 | 2013-01-19 17:52:10 +0800 | [diff] [blame] | 1081 | error_msg[i++] = "Error data in FIFO\n"; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1082 | |
Liang Li | 384e301 | 2013-01-19 17:52:10 +0800 | [diff] [blame] | 1083 | if (lsr & UART_LSR_FE) { |
| 1084 | port->icount.frame++; |
| 1085 | error_msg[i++] = " Framing Error\n"; |
| 1086 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1087 | |
Liang Li | 384e301 | 2013-01-19 17:52:10 +0800 | [diff] [blame] | 1088 | if (lsr & UART_LSR_PE) { |
| 1089 | port->icount.parity++; |
| 1090 | error_msg[i++] = " Parity Error\n"; |
| 1091 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1092 | |
Liang Li | 384e301 | 2013-01-19 17:52:10 +0800 | [diff] [blame] | 1093 | if (lsr & UART_LSR_OE) { |
| 1094 | port->icount.overrun++; |
| 1095 | error_msg[i++] = " Overrun Error\n"; |
| 1096 | } |
| 1097 | |
| 1098 | if (tty == NULL) { |
| 1099 | for (i = 0; error_msg[i] != NULL; i++) |
| 1100 | dev_err(&priv->pdev->dev, error_msg[i]); |
| 1101 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1102 | } |
| 1103 | |
| 1104 | static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) |
| 1105 | { |
| 1106 | struct eg20t_port *priv = dev_id; |
| 1107 | unsigned int handled; |
| 1108 | u8 lsr; |
| 1109 | int ret = 0; |
Tomoya MORINAGA | 2a58364 | 2012-03-26 14:43:01 +0900 | [diff] [blame] | 1110 | unsigned char iid; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1111 | unsigned long flags; |
Tomoya MORINAGA | 5181fb3 | 2012-03-26 14:43:03 +0900 | [diff] [blame] | 1112 | int next = 1; |
| 1113 | u8 msr; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1114 | |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1115 | spin_lock_irqsave(&priv->lock, flags); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1116 | handled = 0; |
Tomoya MORINAGA | 5181fb3 | 2012-03-26 14:43:03 +0900 | [diff] [blame] | 1117 | while (next) { |
| 1118 | iid = pch_uart_hal_get_iid(priv); |
| 1119 | if (iid & PCH_UART_IIR_IP) /* No Interrupt */ |
| 1120 | break; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1121 | switch (iid) { |
| 1122 | case PCH_UART_IID_RLS: /* Receiver Line Status */ |
| 1123 | lsr = pch_uart_hal_get_line_status(priv); |
| 1124 | if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | |
| 1125 | UART_LSR_PE | UART_LSR_OE)) { |
| 1126 | pch_uart_err_ir(priv, lsr); |
| 1127 | ret = PCH_UART_HANDLED_RX_ERR_INT; |
Tomoya MORINAGA | 04e2c2e | 2012-03-26 14:43:05 +0900 | [diff] [blame] | 1128 | } else { |
| 1129 | ret = PCH_UART_HANDLED_LS_INT; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1130 | } |
| 1131 | break; |
| 1132 | case PCH_UART_IID_RDR: /* Received Data Ready */ |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1133 | if (priv->use_dma) { |
| 1134 | pch_uart_hal_disable_interrupt(priv, |
Tomoya MORINAGA | ae213f3 | 2012-07-06 17:19:42 +0900 | [diff] [blame] | 1135 | PCH_UART_HAL_RX_INT | |
| 1136 | PCH_UART_HAL_RX_ERR_INT); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1137 | ret = dma_handle_rx(priv); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1138 | if (!ret) |
| 1139 | pch_uart_hal_enable_interrupt(priv, |
Tomoya MORINAGA | ae213f3 | 2012-07-06 17:19:42 +0900 | [diff] [blame] | 1140 | PCH_UART_HAL_RX_INT | |
| 1141 | PCH_UART_HAL_RX_ERR_INT); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1142 | } else { |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1143 | ret = handle_rx(priv); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1144 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1145 | break; |
| 1146 | case PCH_UART_IID_RDR_TO: /* Received Data Ready |
| 1147 | (FIFO Timeout) */ |
| 1148 | ret = handle_rx_to(priv); |
| 1149 | break; |
| 1150 | case PCH_UART_IID_THRE: /* Transmitter Holding Register |
| 1151 | Empty */ |
| 1152 | if (priv->use_dma) |
| 1153 | ret = dma_handle_tx(priv); |
| 1154 | else |
| 1155 | ret = handle_tx(priv); |
| 1156 | break; |
| 1157 | case PCH_UART_IID_MS: /* Modem Status */ |
Tomoya MORINAGA | 5181fb3 | 2012-03-26 14:43:03 +0900 | [diff] [blame] | 1158 | msr = pch_uart_hal_get_modem(priv); |
| 1159 | next = 0; /* MS ir prioirty is the lowest. So, MS ir |
| 1160 | means final interrupt */ |
| 1161 | if ((msr & UART_MSR_ANY_DELTA) == 0) |
| 1162 | break; |
| 1163 | ret |= PCH_UART_HANDLED_MS_INT; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1164 | break; |
| 1165 | default: /* Never junp to this label */ |
Tomoya MORINAGA | b23954a3 | 2012-03-26 14:43:02 +0900 | [diff] [blame] | 1166 | dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__, |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1167 | iid, jiffies); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1168 | ret = -1; |
Tomoya MORINAGA | 5181fb3 | 2012-03-26 14:43:03 +0900 | [diff] [blame] | 1169 | next = 0; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1170 | break; |
| 1171 | } |
| 1172 | handled |= (unsigned int)ret; |
| 1173 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1174 | |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1175 | spin_unlock_irqrestore(&priv->lock, flags); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1176 | return IRQ_RETVAL(handled); |
| 1177 | } |
| 1178 | |
| 1179 | /* This function tests whether the transmitter fifo and shifter for the port |
| 1180 | described by 'port' is empty. */ |
| 1181 | static unsigned int pch_uart_tx_empty(struct uart_port *port) |
| 1182 | { |
| 1183 | struct eg20t_port *priv; |
Feng Tang | 30c6c6b | 2012-02-06 17:24:44 +0800 | [diff] [blame] | 1184 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1185 | priv = container_of(port, struct eg20t_port, port); |
| 1186 | if (priv->tx_empty) |
Feng Tang | 30c6c6b | 2012-02-06 17:24:44 +0800 | [diff] [blame] | 1187 | return TIOCSER_TEMT; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1188 | else |
Feng Tang | 30c6c6b | 2012-02-06 17:24:44 +0800 | [diff] [blame] | 1189 | return 0; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1190 | } |
| 1191 | |
| 1192 | /* Returns the current state of modem control inputs. */ |
| 1193 | static unsigned int pch_uart_get_mctrl(struct uart_port *port) |
| 1194 | { |
| 1195 | struct eg20t_port *priv; |
| 1196 | u8 modem; |
| 1197 | unsigned int ret = 0; |
| 1198 | |
| 1199 | priv = container_of(port, struct eg20t_port, port); |
| 1200 | modem = pch_uart_hal_get_modem(priv); |
| 1201 | |
| 1202 | if (modem & UART_MSR_DCD) |
| 1203 | ret |= TIOCM_CAR; |
| 1204 | |
| 1205 | if (modem & UART_MSR_RI) |
| 1206 | ret |= TIOCM_RNG; |
| 1207 | |
| 1208 | if (modem & UART_MSR_DSR) |
| 1209 | ret |= TIOCM_DSR; |
| 1210 | |
| 1211 | if (modem & UART_MSR_CTS) |
| 1212 | ret |= TIOCM_CTS; |
| 1213 | |
| 1214 | return ret; |
| 1215 | } |
| 1216 | |
| 1217 | static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
| 1218 | { |
| 1219 | u32 mcr = 0; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1220 | struct eg20t_port *priv = container_of(port, struct eg20t_port, port); |
| 1221 | |
| 1222 | if (mctrl & TIOCM_DTR) |
| 1223 | mcr |= UART_MCR_DTR; |
| 1224 | if (mctrl & TIOCM_RTS) |
| 1225 | mcr |= UART_MCR_RTS; |
| 1226 | if (mctrl & TIOCM_LOOP) |
| 1227 | mcr |= UART_MCR_LOOP; |
| 1228 | |
Tomoya MORINAGA | 9af7155 | 2011-02-23 10:03:17 +0900 | [diff] [blame] | 1229 | if (priv->mcr & UART_MCR_AFE) |
| 1230 | mcr |= UART_MCR_AFE; |
| 1231 | |
| 1232 | if (mctrl) |
| 1233 | iowrite8(mcr, priv->membase + UART_MCR); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1234 | } |
| 1235 | |
| 1236 | static void pch_uart_stop_tx(struct uart_port *port) |
| 1237 | { |
| 1238 | struct eg20t_port *priv; |
| 1239 | priv = container_of(port, struct eg20t_port, port); |
| 1240 | priv->start_tx = 0; |
| 1241 | priv->tx_dma_use = 0; |
| 1242 | } |
| 1243 | |
| 1244 | static void pch_uart_start_tx(struct uart_port *port) |
| 1245 | { |
| 1246 | struct eg20t_port *priv; |
| 1247 | |
| 1248 | priv = container_of(port, struct eg20t_port, port); |
| 1249 | |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1250 | if (priv->use_dma) { |
| 1251 | if (priv->tx_dma_use) { |
| 1252 | dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", |
| 1253 | __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1254 | return; |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1255 | } |
| 1256 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1257 | |
| 1258 | priv->start_tx = 1; |
| 1259 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); |
| 1260 | } |
| 1261 | |
| 1262 | static void pch_uart_stop_rx(struct uart_port *port) |
| 1263 | { |
| 1264 | struct eg20t_port *priv; |
| 1265 | priv = container_of(port, struct eg20t_port, port); |
| 1266 | priv->start_rx = 0; |
Tomoya MORINAGA | ae213f3 | 2012-07-06 17:19:42 +0900 | [diff] [blame] | 1267 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | |
| 1268 | PCH_UART_HAL_RX_ERR_INT); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1269 | } |
| 1270 | |
| 1271 | /* Enable the modem status interrupts. */ |
| 1272 | static void pch_uart_enable_ms(struct uart_port *port) |
| 1273 | { |
| 1274 | struct eg20t_port *priv; |
| 1275 | priv = container_of(port, struct eg20t_port, port); |
| 1276 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); |
| 1277 | } |
| 1278 | |
| 1279 | /* Control the transmission of a break signal. */ |
| 1280 | static void pch_uart_break_ctl(struct uart_port *port, int ctl) |
| 1281 | { |
| 1282 | struct eg20t_port *priv; |
| 1283 | unsigned long flags; |
| 1284 | |
| 1285 | priv = container_of(port, struct eg20t_port, port); |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1286 | spin_lock_irqsave(&priv->lock, flags); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1287 | pch_uart_hal_set_break(priv, ctl); |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1288 | spin_unlock_irqrestore(&priv->lock, flags); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1289 | } |
| 1290 | |
| 1291 | /* Grab any interrupt resources and initialise any low level driver state. */ |
| 1292 | static int pch_uart_startup(struct uart_port *port) |
| 1293 | { |
| 1294 | struct eg20t_port *priv; |
| 1295 | int ret; |
| 1296 | int fifo_size; |
| 1297 | int trigger_level; |
| 1298 | |
| 1299 | priv = container_of(port, struct eg20t_port, port); |
| 1300 | priv->tx_empty = 1; |
Tomoya MORINAGA | aac6c0b | 2011-02-23 10:03:16 +0900 | [diff] [blame] | 1301 | |
| 1302 | if (port->uartclk) |
Darren Hart | a8a3ec9 | 2012-03-09 09:51:48 -0800 | [diff] [blame] | 1303 | priv->uartclk = port->uartclk; |
Tomoya MORINAGA | aac6c0b | 2011-02-23 10:03:16 +0900 | [diff] [blame] | 1304 | else |
Darren Hart | a8a3ec9 | 2012-03-09 09:51:48 -0800 | [diff] [blame] | 1305 | port->uartclk = priv->uartclk; |
Tomoya MORINAGA | aac6c0b | 2011-02-23 10:03:16 +0900 | [diff] [blame] | 1306 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1307 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); |
| 1308 | ret = pch_uart_hal_set_line(priv, default_baud, |
| 1309 | PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, |
| 1310 | PCH_UART_HAL_STB1); |
| 1311 | if (ret) |
| 1312 | return ret; |
| 1313 | |
| 1314 | switch (priv->fifo_size) { |
| 1315 | case 256: |
| 1316 | fifo_size = PCH_UART_HAL_FIFO256; |
| 1317 | break; |
| 1318 | case 64: |
| 1319 | fifo_size = PCH_UART_HAL_FIFO64; |
| 1320 | break; |
| 1321 | case 16: |
| 1322 | fifo_size = PCH_UART_HAL_FIFO16; |
Alan Cox | 669bd45 | 2012-07-02 18:51:38 +0100 | [diff] [blame] | 1323 | break; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1324 | case 1: |
| 1325 | default: |
| 1326 | fifo_size = PCH_UART_HAL_FIFO_DIS; |
| 1327 | break; |
| 1328 | } |
| 1329 | |
| 1330 | switch (priv->trigger) { |
| 1331 | case PCH_UART_HAL_TRIGGER1: |
| 1332 | trigger_level = 1; |
| 1333 | break; |
| 1334 | case PCH_UART_HAL_TRIGGER_L: |
| 1335 | trigger_level = priv->fifo_size / 4; |
| 1336 | break; |
| 1337 | case PCH_UART_HAL_TRIGGER_M: |
| 1338 | trigger_level = priv->fifo_size / 2; |
| 1339 | break; |
| 1340 | case PCH_UART_HAL_TRIGGER_H: |
| 1341 | default: |
| 1342 | trigger_level = priv->fifo_size - (priv->fifo_size / 8); |
| 1343 | break; |
| 1344 | } |
| 1345 | |
| 1346 | priv->trigger_level = trigger_level; |
| 1347 | ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, |
| 1348 | fifo_size, priv->trigger); |
| 1349 | if (ret < 0) |
| 1350 | return ret; |
| 1351 | |
| 1352 | ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, |
| 1353 | KBUILD_MODNAME, priv); |
| 1354 | if (ret < 0) |
| 1355 | return ret; |
| 1356 | |
| 1357 | if (priv->use_dma) |
| 1358 | pch_request_dma(port); |
| 1359 | |
| 1360 | priv->start_rx = 1; |
Tomoya MORINAGA | ae213f3 | 2012-07-06 17:19:42 +0900 | [diff] [blame] | 1361 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | |
| 1362 | PCH_UART_HAL_RX_ERR_INT); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1363 | uart_update_timeout(port, CS8, default_baud); |
| 1364 | |
| 1365 | return 0; |
| 1366 | } |
| 1367 | |
| 1368 | static void pch_uart_shutdown(struct uart_port *port) |
| 1369 | { |
| 1370 | struct eg20t_port *priv; |
| 1371 | int ret; |
| 1372 | |
| 1373 | priv = container_of(port, struct eg20t_port, port); |
| 1374 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); |
| 1375 | pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); |
| 1376 | ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, |
| 1377 | PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); |
| 1378 | if (ret) |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1379 | dev_err(priv->port.dev, |
| 1380 | "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1381 | |
Tomoya MORINAGA | 90f04c2 | 2011-11-11 10:55:27 +0900 | [diff] [blame] | 1382 | pch_free_dma(port); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1383 | |
| 1384 | free_irq(priv->port.irq, priv); |
| 1385 | } |
| 1386 | |
| 1387 | /* Change the port parameters, including word length, parity, stop |
| 1388 | *bits. Update read_status_mask and ignore_status_mask to indicate |
| 1389 | *the types of events we are interested in receiving. */ |
| 1390 | static void pch_uart_set_termios(struct uart_port *port, |
| 1391 | struct ktermios *termios, struct ktermios *old) |
| 1392 | { |
| 1393 | int baud; |
| 1394 | int rtn; |
| 1395 | unsigned int parity, bits, stb; |
| 1396 | struct eg20t_port *priv; |
| 1397 | unsigned long flags; |
| 1398 | |
| 1399 | priv = container_of(port, struct eg20t_port, port); |
| 1400 | switch (termios->c_cflag & CSIZE) { |
| 1401 | case CS5: |
| 1402 | bits = PCH_UART_HAL_5BIT; |
| 1403 | break; |
| 1404 | case CS6: |
| 1405 | bits = PCH_UART_HAL_6BIT; |
| 1406 | break; |
| 1407 | case CS7: |
| 1408 | bits = PCH_UART_HAL_7BIT; |
| 1409 | break; |
| 1410 | default: /* CS8 */ |
| 1411 | bits = PCH_UART_HAL_8BIT; |
| 1412 | break; |
| 1413 | } |
| 1414 | if (termios->c_cflag & CSTOPB) |
| 1415 | stb = PCH_UART_HAL_STB2; |
| 1416 | else |
| 1417 | stb = PCH_UART_HAL_STB1; |
| 1418 | |
| 1419 | if (termios->c_cflag & PARENB) { |
Tomoya MORINAGA | 2fc39ae | 2012-07-06 17:19:43 +0900 | [diff] [blame] | 1420 | if (termios->c_cflag & PARODD) |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1421 | parity = PCH_UART_HAL_PARITY_ODD; |
| 1422 | else |
| 1423 | parity = PCH_UART_HAL_PARITY_EVEN; |
| 1424 | |
Feng Tang | 30c6c6b | 2012-02-06 17:24:44 +0800 | [diff] [blame] | 1425 | } else |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1426 | parity = PCH_UART_HAL_PARITY_NONE; |
Tomoya MORINAGA | 9af7155 | 2011-02-23 10:03:17 +0900 | [diff] [blame] | 1427 | |
| 1428 | /* Only UART0 has auto hardware flow function */ |
| 1429 | if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) |
| 1430 | priv->mcr |= UART_MCR_AFE; |
| 1431 | else |
| 1432 | priv->mcr &= ~UART_MCR_AFE; |
| 1433 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1434 | termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ |
| 1435 | |
| 1436 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); |
| 1437 | |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1438 | spin_lock_irqsave(&priv->lock, flags); |
| 1439 | spin_lock(&port->lock); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1440 | |
| 1441 | uart_update_timeout(port, termios->c_cflag, baud); |
| 1442 | rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); |
| 1443 | if (rtn) |
| 1444 | goto out; |
| 1445 | |
Tomoya MORINAGA | a1d7cfe | 2011-10-27 15:45:18 +0900 | [diff] [blame] | 1446 | pch_uart_set_mctrl(&priv->port, priv->port.mctrl); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1447 | /* Don't rewrite B0 */ |
| 1448 | if (tty_termios_baud_rate(termios)) |
| 1449 | tty_termios_encode_baud_rate(termios, baud, baud); |
| 1450 | |
| 1451 | out: |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1452 | spin_unlock(&port->lock); |
| 1453 | spin_unlock_irqrestore(&priv->lock, flags); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1454 | } |
| 1455 | |
| 1456 | static const char *pch_uart_type(struct uart_port *port) |
| 1457 | { |
| 1458 | return KBUILD_MODNAME; |
| 1459 | } |
| 1460 | |
| 1461 | static void pch_uart_release_port(struct uart_port *port) |
| 1462 | { |
| 1463 | struct eg20t_port *priv; |
| 1464 | |
| 1465 | priv = container_of(port, struct eg20t_port, port); |
| 1466 | pci_iounmap(priv->pdev, priv->membase); |
| 1467 | pci_release_regions(priv->pdev); |
| 1468 | } |
| 1469 | |
| 1470 | static int pch_uart_request_port(struct uart_port *port) |
| 1471 | { |
| 1472 | struct eg20t_port *priv; |
| 1473 | int ret; |
| 1474 | void __iomem *membase; |
| 1475 | |
| 1476 | priv = container_of(port, struct eg20t_port, port); |
| 1477 | ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); |
| 1478 | if (ret < 0) |
| 1479 | return -EBUSY; |
| 1480 | |
| 1481 | membase = pci_iomap(priv->pdev, 1, 0); |
| 1482 | if (!membase) { |
| 1483 | pci_release_regions(priv->pdev); |
| 1484 | return -EBUSY; |
| 1485 | } |
| 1486 | priv->membase = port->membase = membase; |
| 1487 | |
| 1488 | return 0; |
| 1489 | } |
| 1490 | |
| 1491 | static void pch_uart_config_port(struct uart_port *port, int type) |
| 1492 | { |
| 1493 | struct eg20t_port *priv; |
| 1494 | |
| 1495 | priv = container_of(port, struct eg20t_port, port); |
| 1496 | if (type & UART_CONFIG_TYPE) { |
| 1497 | port->type = priv->port_type; |
| 1498 | pch_uart_request_port(port); |
| 1499 | } |
| 1500 | } |
| 1501 | |
| 1502 | static int pch_uart_verify_port(struct uart_port *port, |
| 1503 | struct serial_struct *serinfo) |
| 1504 | { |
| 1505 | struct eg20t_port *priv; |
| 1506 | |
| 1507 | priv = container_of(port, struct eg20t_port, port); |
| 1508 | if (serinfo->flags & UPF_LOW_LATENCY) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1509 | dev_info(priv->port.dev, |
| 1510 | "PCH UART : Use PIO Mode (without DMA)\n"); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1511 | priv->use_dma = 0; |
| 1512 | serinfo->flags &= ~UPF_LOW_LATENCY; |
| 1513 | } else { |
| 1514 | #ifndef CONFIG_PCH_DMA |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1515 | dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", |
| 1516 | __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1517 | return -EOPNOTSUPP; |
| 1518 | #endif |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1519 | dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n"); |
Tomoya MORINAGA | af6d17c | 2012-04-12 10:47:50 +0900 | [diff] [blame] | 1520 | if (!priv->use_dma) |
| 1521 | pch_request_dma(port); |
| 1522 | priv->use_dma = 1; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1523 | } |
| 1524 | |
| 1525 | return 0; |
| 1526 | } |
| 1527 | |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1528 | /* |
| 1529 | * Wait for transmitter & holding register to empty |
| 1530 | */ |
| 1531 | static void wait_for_xmitr(struct eg20t_port *up, int bits) |
| 1532 | { |
| 1533 | unsigned int status, tmout = 10000; |
| 1534 | |
| 1535 | /* Wait up to 10ms for the character(s) to be sent. */ |
| 1536 | for (;;) { |
| 1537 | status = ioread8(up->membase + UART_LSR); |
| 1538 | |
| 1539 | if ((status & bits) == bits) |
| 1540 | break; |
| 1541 | if (--tmout == 0) |
| 1542 | break; |
| 1543 | udelay(1); |
| 1544 | } |
| 1545 | |
| 1546 | /* Wait up to 1s for flow control if necessary */ |
| 1547 | if (up->port.flags & UPF_CONS_FLOW) { |
| 1548 | unsigned int tmout; |
| 1549 | for (tmout = 1000000; tmout; tmout--) { |
| 1550 | unsigned int msr = ioread8(up->membase + UART_MSR); |
| 1551 | if (msr & UART_MSR_CTS) |
| 1552 | break; |
| 1553 | udelay(1); |
| 1554 | touch_nmi_watchdog(); |
| 1555 | } |
| 1556 | } |
| 1557 | } |
| 1558 | |
Liang Li | ef44d28 | 2013-03-05 22:30:38 +0800 | [diff] [blame] | 1559 | #ifdef CONFIG_CONSOLE_POLL |
| 1560 | /* |
| 1561 | * Console polling routines for communicate via uart while |
| 1562 | * in an interrupt or debug context. |
| 1563 | */ |
| 1564 | static int pch_uart_get_poll_char(struct uart_port *port) |
| 1565 | { |
| 1566 | struct eg20t_port *priv = |
| 1567 | container_of(port, struct eg20t_port, port); |
| 1568 | u8 lsr = ioread8(priv->membase + UART_LSR); |
| 1569 | |
| 1570 | if (!(lsr & UART_LSR_DR)) |
| 1571 | return NO_POLL_CHAR; |
| 1572 | |
| 1573 | return ioread8(priv->membase + PCH_UART_RBR); |
| 1574 | } |
| 1575 | |
| 1576 | |
| 1577 | static void pch_uart_put_poll_char(struct uart_port *port, |
| 1578 | unsigned char c) |
| 1579 | { |
| 1580 | unsigned int ier; |
| 1581 | struct eg20t_port *priv = |
| 1582 | container_of(port, struct eg20t_port, port); |
| 1583 | |
| 1584 | /* |
| 1585 | * First save the IER then disable the interrupts |
| 1586 | */ |
| 1587 | ier = ioread8(priv->membase + UART_IER); |
| 1588 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); |
| 1589 | |
| 1590 | wait_for_xmitr(priv, UART_LSR_THRE); |
| 1591 | /* |
| 1592 | * Send the character out. |
| 1593 | * If a LF, also do CR... |
| 1594 | */ |
| 1595 | iowrite8(c, priv->membase + PCH_UART_THR); |
| 1596 | if (c == 10) { |
| 1597 | wait_for_xmitr(priv, UART_LSR_THRE); |
| 1598 | iowrite8(13, priv->membase + PCH_UART_THR); |
| 1599 | } |
| 1600 | |
| 1601 | /* |
| 1602 | * Finally, wait for transmitter to become empty |
| 1603 | * and restore the IER |
| 1604 | */ |
| 1605 | wait_for_xmitr(priv, BOTH_EMPTY); |
| 1606 | iowrite8(ier, priv->membase + UART_IER); |
| 1607 | } |
| 1608 | #endif /* CONFIG_CONSOLE_POLL */ |
| 1609 | |
| 1610 | static struct uart_ops pch_uart_ops = { |
| 1611 | .tx_empty = pch_uart_tx_empty, |
| 1612 | .set_mctrl = pch_uart_set_mctrl, |
| 1613 | .get_mctrl = pch_uart_get_mctrl, |
| 1614 | .stop_tx = pch_uart_stop_tx, |
| 1615 | .start_tx = pch_uart_start_tx, |
| 1616 | .stop_rx = pch_uart_stop_rx, |
| 1617 | .enable_ms = pch_uart_enable_ms, |
| 1618 | .break_ctl = pch_uart_break_ctl, |
| 1619 | .startup = pch_uart_startup, |
| 1620 | .shutdown = pch_uart_shutdown, |
| 1621 | .set_termios = pch_uart_set_termios, |
| 1622 | /* .pm = pch_uart_pm, Not supported yet */ |
| 1623 | /* .set_wake = pch_uart_set_wake, Not supported yet */ |
| 1624 | .type = pch_uart_type, |
| 1625 | .release_port = pch_uart_release_port, |
| 1626 | .request_port = pch_uart_request_port, |
| 1627 | .config_port = pch_uart_config_port, |
| 1628 | .verify_port = pch_uart_verify_port, |
| 1629 | #ifdef CONFIG_CONSOLE_POLL |
| 1630 | .poll_get_char = pch_uart_get_poll_char, |
| 1631 | .poll_put_char = pch_uart_put_poll_char, |
| 1632 | #endif |
| 1633 | }; |
| 1634 | |
| 1635 | #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE |
| 1636 | |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1637 | static void pch_console_putchar(struct uart_port *port, int ch) |
| 1638 | { |
| 1639 | struct eg20t_port *priv = |
| 1640 | container_of(port, struct eg20t_port, port); |
| 1641 | |
| 1642 | wait_for_xmitr(priv, UART_LSR_THRE); |
| 1643 | iowrite8(ch, priv->membase + PCH_UART_THR); |
| 1644 | } |
| 1645 | |
| 1646 | /* |
| 1647 | * Print a string to the serial port trying not to disturb |
| 1648 | * any possible real use of the port... |
| 1649 | * |
| 1650 | * The console_lock must be held when we get here. |
| 1651 | */ |
| 1652 | static void |
| 1653 | pch_console_write(struct console *co, const char *s, unsigned int count) |
| 1654 | { |
| 1655 | struct eg20t_port *priv; |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1656 | unsigned long flags; |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1657 | int priv_locked = 1; |
| 1658 | int port_locked = 1; |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1659 | u8 ier; |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1660 | |
| 1661 | priv = pch_uart_ports[co->index]; |
| 1662 | |
| 1663 | touch_nmi_watchdog(); |
| 1664 | |
| 1665 | local_irq_save(flags); |
| 1666 | if (priv->port.sysrq) { |
Liang Li | 1f9db09 | 2013-01-19 17:52:11 +0800 | [diff] [blame] | 1667 | /* call to uart_handle_sysrq_char already took the priv lock */ |
| 1668 | priv_locked = 0; |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1669 | /* serial8250_handle_port() already took the port lock */ |
| 1670 | port_locked = 0; |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1671 | } else if (oops_in_progress) { |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1672 | priv_locked = spin_trylock(&priv->lock); |
| 1673 | port_locked = spin_trylock(&priv->port.lock); |
| 1674 | } else { |
| 1675 | spin_lock(&priv->lock); |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1676 | spin_lock(&priv->port.lock); |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1677 | } |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1678 | |
| 1679 | /* |
| 1680 | * First save the IER then disable the interrupts |
| 1681 | */ |
| 1682 | ier = ioread8(priv->membase + UART_IER); |
| 1683 | |
| 1684 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); |
| 1685 | |
| 1686 | uart_console_write(&priv->port, s, count, pch_console_putchar); |
| 1687 | |
| 1688 | /* |
| 1689 | * Finally, wait for transmitter to become empty |
| 1690 | * and restore the IER |
| 1691 | */ |
| 1692 | wait_for_xmitr(priv, BOTH_EMPTY); |
| 1693 | iowrite8(ier, priv->membase + UART_IER); |
| 1694 | |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1695 | if (port_locked) |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1696 | spin_unlock(&priv->port.lock); |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1697 | if (priv_locked) |
| 1698 | spin_unlock(&priv->lock); |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1699 | local_irq_restore(flags); |
| 1700 | } |
| 1701 | |
| 1702 | static int __init pch_console_setup(struct console *co, char *options) |
| 1703 | { |
| 1704 | struct uart_port *port; |
Darren Hart | 7ce9251 | 2012-03-09 09:51:51 -0800 | [diff] [blame] | 1705 | int baud = default_baud; |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1706 | int bits = 8; |
| 1707 | int parity = 'n'; |
| 1708 | int flow = 'n'; |
| 1709 | |
| 1710 | /* |
| 1711 | * Check whether an invalid uart number has been specified, and |
| 1712 | * if so, search for the first available port that does have |
| 1713 | * console support. |
| 1714 | */ |
| 1715 | if (co->index >= PCH_UART_NR) |
| 1716 | co->index = 0; |
| 1717 | port = &pch_uart_ports[co->index]->port; |
| 1718 | |
| 1719 | if (!port || (!port->iobase && !port->membase)) |
| 1720 | return -ENODEV; |
| 1721 | |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 1722 | port->uartclk = pch_uart_get_uartclk(); |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1723 | |
| 1724 | if (options) |
| 1725 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
| 1726 | |
| 1727 | return uart_set_options(port, co, baud, parity, bits, flow); |
| 1728 | } |
| 1729 | |
| 1730 | static struct uart_driver pch_uart_driver; |
| 1731 | |
| 1732 | static struct console pch_console = { |
| 1733 | .name = PCH_UART_DRIVER_DEVICE, |
| 1734 | .write = pch_console_write, |
| 1735 | .device = uart_console_device, |
| 1736 | .setup = pch_console_setup, |
| 1737 | .flags = CON_PRINTBUFFER | CON_ANYTIME, |
| 1738 | .index = -1, |
| 1739 | .data = &pch_uart_driver, |
| 1740 | }; |
| 1741 | |
| 1742 | #define PCH_CONSOLE (&pch_console) |
| 1743 | #else |
| 1744 | #define PCH_CONSOLE NULL |
Liang Li | ef44d28 | 2013-03-05 22:30:38 +0800 | [diff] [blame] | 1745 | #endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */ |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1746 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1747 | static struct uart_driver pch_uart_driver = { |
| 1748 | .owner = THIS_MODULE, |
| 1749 | .driver_name = KBUILD_MODNAME, |
| 1750 | .dev_name = PCH_UART_DRIVER_DEVICE, |
| 1751 | .major = 0, |
| 1752 | .minor = 0, |
| 1753 | .nr = PCH_UART_NR, |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1754 | .cons = PCH_CONSOLE, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1755 | }; |
| 1756 | |
| 1757 | static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1758 | const struct pci_device_id *id) |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1759 | { |
| 1760 | struct eg20t_port *priv; |
| 1761 | int ret; |
| 1762 | unsigned int iobase; |
| 1763 | unsigned int mapbase; |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 1764 | unsigned char *rxbuf; |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 1765 | int fifosize; |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1766 | int port_type; |
| 1767 | struct pch_uart_driver_data *board; |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 1768 | char name[32]; /* for debugfs file name */ |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1769 | |
| 1770 | board = &drv_dat[id->driver_data]; |
| 1771 | port_type = board->port_type; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1772 | |
| 1773 | priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL); |
| 1774 | if (priv == NULL) |
| 1775 | goto init_port_alloc_err; |
| 1776 | |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 1777 | rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1778 | if (!rxbuf) |
| 1779 | goto init_port_free_txbuf; |
| 1780 | |
| 1781 | switch (port_type) { |
| 1782 | case PORT_UNKNOWN: |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1783 | fifosize = 256; /* EG20T/ML7213: UART0 */ |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1784 | break; |
| 1785 | case PORT_8250: |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1786 | fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1787 | break; |
| 1788 | default: |
| 1789 | dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); |
| 1790 | goto init_port_hal_free; |
| 1791 | } |
| 1792 | |
Alexander Stein | e463595 | 2011-07-04 08:58:31 +0200 | [diff] [blame] | 1793 | pci_enable_msi(pdev); |
Tomoya MORINAGA | 867c902 | 2012-04-02 14:36:22 +0900 | [diff] [blame] | 1794 | pci_set_master(pdev); |
Alexander Stein | e463595 | 2011-07-04 08:58:31 +0200 | [diff] [blame] | 1795 | |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1796 | spin_lock_init(&priv->lock); |
| 1797 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1798 | iobase = pci_resource_start(pdev, 0); |
| 1799 | mapbase = pci_resource_start(pdev, 1); |
| 1800 | priv->mapbase = mapbase; |
| 1801 | priv->iobase = iobase; |
| 1802 | priv->pdev = pdev; |
| 1803 | priv->tx_empty = 1; |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 1804 | priv->rxbuf.buf = rxbuf; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1805 | priv->rxbuf.size = PAGE_SIZE; |
| 1806 | |
| 1807 | priv->fifo_size = fifosize; |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 1808 | priv->uartclk = pch_uart_get_uartclk(); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1809 | priv->port_type = PORT_MAX_8250 + port_type + 1; |
| 1810 | priv->port.dev = &pdev->dev; |
| 1811 | priv->port.iobase = iobase; |
| 1812 | priv->port.membase = NULL; |
| 1813 | priv->port.mapbase = mapbase; |
| 1814 | priv->port.irq = pdev->irq; |
| 1815 | priv->port.iotype = UPIO_PORT; |
| 1816 | priv->port.ops = &pch_uart_ops; |
| 1817 | priv->port.flags = UPF_BOOT_AUTOCONF; |
| 1818 | priv->port.fifosize = fifosize; |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1819 | priv->port.line = board->line_no; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1820 | priv->trigger = PCH_UART_HAL_TRIGGER_M; |
| 1821 | |
Tomoya MORINAGA | 7e46132 | 2011-02-23 10:03:13 +0900 | [diff] [blame] | 1822 | spin_lock_init(&priv->port.lock); |
| 1823 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1824 | pci_set_drvdata(pdev, priv); |
Feng Tang | 6f56d0f | 2012-02-06 17:24:45 +0800 | [diff] [blame] | 1825 | priv->trigger_level = 1; |
| 1826 | priv->fcr = 0; |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1827 | |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1828 | #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE |
| 1829 | pch_uart_ports[board->line_no] = priv; |
| 1830 | #endif |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1831 | ret = uart_add_one_port(&pch_uart_driver, &priv->port); |
| 1832 | if (ret < 0) |
| 1833 | goto init_port_hal_free; |
| 1834 | |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 1835 | #ifdef CONFIG_DEBUG_FS |
| 1836 | snprintf(name, sizeof(name), "uart%d_regs", board->line_no); |
| 1837 | priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO, |
| 1838 | NULL, priv, &port_regs_ops); |
| 1839 | #endif |
| 1840 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1841 | return priv; |
| 1842 | |
| 1843 | init_port_hal_free: |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1844 | #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE |
| 1845 | pch_uart_ports[board->line_no] = NULL; |
| 1846 | #endif |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 1847 | free_page((unsigned long)rxbuf); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1848 | init_port_free_txbuf: |
| 1849 | kfree(priv); |
| 1850 | init_port_alloc_err: |
| 1851 | |
| 1852 | return NULL; |
| 1853 | } |
| 1854 | |
| 1855 | static void pch_uart_exit_port(struct eg20t_port *priv) |
| 1856 | { |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 1857 | |
| 1858 | #ifdef CONFIG_DEBUG_FS |
| 1859 | if (priv->debugfs) |
| 1860 | debugfs_remove(priv->debugfs); |
| 1861 | #endif |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1862 | uart_remove_one_port(&pch_uart_driver, &priv->port); |
| 1863 | pci_set_drvdata(priv->pdev, NULL); |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 1864 | free_page((unsigned long)priv->rxbuf.buf); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1865 | } |
| 1866 | |
| 1867 | static void pch_uart_pci_remove(struct pci_dev *pdev) |
| 1868 | { |
Feng Tang | 6f56d0f | 2012-02-06 17:24:45 +0800 | [diff] [blame] | 1869 | struct eg20t_port *priv = pci_get_drvdata(pdev); |
Alexander Stein | e463595 | 2011-07-04 08:58:31 +0200 | [diff] [blame] | 1870 | |
| 1871 | pci_disable_msi(pdev); |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1872 | |
| 1873 | #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE |
| 1874 | pch_uart_ports[priv->port.line] = NULL; |
| 1875 | #endif |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1876 | pch_uart_exit_port(priv); |
| 1877 | pci_disable_device(pdev); |
| 1878 | kfree(priv); |
| 1879 | return; |
| 1880 | } |
| 1881 | #ifdef CONFIG_PM |
| 1882 | static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
| 1883 | { |
| 1884 | struct eg20t_port *priv = pci_get_drvdata(pdev); |
| 1885 | |
| 1886 | uart_suspend_port(&pch_uart_driver, &priv->port); |
| 1887 | |
| 1888 | pci_save_state(pdev); |
| 1889 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
| 1890 | return 0; |
| 1891 | } |
| 1892 | |
| 1893 | static int pch_uart_pci_resume(struct pci_dev *pdev) |
| 1894 | { |
| 1895 | struct eg20t_port *priv = pci_get_drvdata(pdev); |
| 1896 | int ret; |
| 1897 | |
| 1898 | pci_set_power_state(pdev, PCI_D0); |
| 1899 | pci_restore_state(pdev); |
| 1900 | |
| 1901 | ret = pci_enable_device(pdev); |
| 1902 | if (ret) { |
| 1903 | dev_err(&pdev->dev, |
| 1904 | "%s-pci_enable_device failed(ret=%d) ", __func__, ret); |
| 1905 | return ret; |
| 1906 | } |
| 1907 | |
| 1908 | uart_resume_port(&pch_uart_driver, &priv->port); |
| 1909 | |
| 1910 | return 0; |
| 1911 | } |
| 1912 | #else |
| 1913 | #define pch_uart_pci_suspend NULL |
| 1914 | #define pch_uart_pci_resume NULL |
| 1915 | #endif |
| 1916 | |
| 1917 | static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = { |
| 1918 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1919 | .driver_data = pch_et20t_uart0}, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1920 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1921 | .driver_data = pch_et20t_uart1}, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1922 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1923 | .driver_data = pch_et20t_uart2}, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1924 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1925 | .driver_data = pch_et20t_uart3}, |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1926 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027), |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1927 | .driver_data = pch_ml7213_uart0}, |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1928 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028), |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1929 | .driver_data = pch_ml7213_uart1}, |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1930 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029), |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1931 | .driver_data = pch_ml7213_uart2}, |
Tomoya MORINAGA | 177c2cb | 2011-05-09 17:25:20 +0900 | [diff] [blame] | 1932 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C), |
| 1933 | .driver_data = pch_ml7223_uart0}, |
| 1934 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D), |
| 1935 | .driver_data = pch_ml7223_uart1}, |
Tomoya MORINAGA | 8249f74 | 2011-10-28 09:38:49 +0900 | [diff] [blame] | 1936 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811), |
| 1937 | .driver_data = pch_ml7831_uart0}, |
| 1938 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812), |
| 1939 | .driver_data = pch_ml7831_uart1}, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1940 | {0,}, |
| 1941 | }; |
| 1942 | |
Bill Pemberton | 9671f09 | 2012-11-19 13:21:50 -0500 | [diff] [blame] | 1943 | static int pch_uart_pci_probe(struct pci_dev *pdev, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1944 | const struct pci_device_id *id) |
| 1945 | { |
| 1946 | int ret; |
| 1947 | struct eg20t_port *priv; |
| 1948 | |
| 1949 | ret = pci_enable_device(pdev); |
| 1950 | if (ret < 0) |
| 1951 | goto probe_error; |
| 1952 | |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1953 | priv = pch_uart_init_port(pdev, id); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1954 | if (!priv) { |
| 1955 | ret = -EBUSY; |
| 1956 | goto probe_disable_device; |
| 1957 | } |
| 1958 | pci_set_drvdata(pdev, priv); |
| 1959 | |
| 1960 | return ret; |
| 1961 | |
| 1962 | probe_disable_device: |
Alexander Stein | e463595 | 2011-07-04 08:58:31 +0200 | [diff] [blame] | 1963 | pci_disable_msi(pdev); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1964 | pci_disable_device(pdev); |
| 1965 | probe_error: |
| 1966 | return ret; |
| 1967 | } |
| 1968 | |
| 1969 | static struct pci_driver pch_uart_pci_driver = { |
| 1970 | .name = "pch_uart", |
| 1971 | .id_table = pch_uart_pci_id, |
| 1972 | .probe = pch_uart_pci_probe, |
Bill Pemberton | 2d47b71 | 2012-11-19 13:21:34 -0500 | [diff] [blame] | 1973 | .remove = pch_uart_pci_remove, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1974 | .suspend = pch_uart_pci_suspend, |
| 1975 | .resume = pch_uart_pci_resume, |
| 1976 | }; |
| 1977 | |
| 1978 | static int __init pch_uart_module_init(void) |
| 1979 | { |
| 1980 | int ret; |
| 1981 | |
| 1982 | /* register as UART driver */ |
| 1983 | ret = uart_register_driver(&pch_uart_driver); |
| 1984 | if (ret < 0) |
| 1985 | return ret; |
| 1986 | |
| 1987 | /* register as PCI driver */ |
| 1988 | ret = pci_register_driver(&pch_uart_pci_driver); |
| 1989 | if (ret < 0) |
| 1990 | uart_unregister_driver(&pch_uart_driver); |
| 1991 | |
| 1992 | return ret; |
| 1993 | } |
| 1994 | module_init(pch_uart_module_init); |
| 1995 | |
| 1996 | static void __exit pch_uart_module_exit(void) |
| 1997 | { |
| 1998 | pci_unregister_driver(&pch_uart_pci_driver); |
| 1999 | uart_unregister_driver(&pch_uart_driver); |
| 2000 | } |
| 2001 | module_exit(pch_uart_module_exit); |
| 2002 | |
| 2003 | MODULE_LICENSE("GPL v2"); |
| 2004 | MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); |
| 2005 | module_param(default_baud, uint, S_IRUGO); |
Darren Hart | a46f553 | 2012-03-09 09:51:52 -0800 | [diff] [blame] | 2006 | MODULE_PARM_DESC(default_baud, |
| 2007 | "Default BAUD for initial driver state and console (default 9600)"); |
Darren Hart | 2a44feb | 2012-03-09 09:51:50 -0800 | [diff] [blame] | 2008 | module_param(user_uartclk, uint, S_IRUGO); |
Darren Hart | a46f553 | 2012-03-09 09:51:52 -0800 | [diff] [blame] | 2009 | MODULE_PARM_DESC(user_uartclk, |
| 2010 | "Override UART default or board specific UART clock"); |