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Boojin Kimb7d861d2011-12-26 18:49:52 +09001/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
Jassi Brarb3040e42010-05-23 20:28:19 -07004 *
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
Boojin Kimb7d861d2011-12-26 18:49:52 +090014#include <linux/kernel.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070015#include <linux/io.h>
16#include <linux/init.h>
17#include <linux/slab.h>
18#include <linux/module.h>
Boojin Kimb7d861d2011-12-26 18:49:52 +090019#include <linux/string.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/dma-mapping.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070023#include <linux/dmaengine.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070024#include <linux/amba/bus.h>
25#include <linux/amba/pl330.h>
Boojin Kim1b9bb712011-09-02 09:44:30 +090026#include <linux/scatterlist.h>
Thomas Abraham93ed5542011-10-24 11:43:31 +020027#include <linux/of.h>
Padmavathi Vennaa80258f2013-02-14 09:10:06 +053028#include <linux/of_dma.h>
Sachin Kamatbcc7fa92013-03-04 14:36:27 +053029#include <linux/err.h>
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +010030#include <linux/pm_runtime.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070031
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000032#include "dmaengine.h"
Boojin Kimb7d861d2011-12-26 18:49:52 +090033#define PL330_MAX_CHAN 8
34#define PL330_MAX_IRQS 32
35#define PL330_MAX_PERI 32
Shawn Lin86a8ce72016-01-22 19:06:51 +080036#define PL330_MAX_BURST 16
Boojin Kimb7d861d2011-12-26 18:49:52 +090037
Addy Ke271e1b862016-01-22 19:06:46 +080038#define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
39
Lars-Peter Clausenf0564c72014-07-06 20:32:19 +020040enum pl330_cachectrl {
41 CCTRL0, /* Noncacheable and nonbufferable */
42 CCTRL1, /* Bufferable only */
43 CCTRL2, /* Cacheable, but do not allocate */
44 CCTRL3, /* Cacheable and bufferable, but do not allocate */
45 INVALID1, /* AWCACHE = 0x1000 */
46 INVALID2,
47 CCTRL6, /* Cacheable write-through, allocate on writes only */
48 CCTRL7, /* Cacheable write-back, allocate on writes only */
Boojin Kimb7d861d2011-12-26 18:49:52 +090049};
50
51enum pl330_byteswap {
52 SWAP_NO,
53 SWAP_2,
54 SWAP_4,
55 SWAP_8,
56 SWAP_16,
57};
58
Boojin Kimb7d861d2011-12-26 18:49:52 +090059/* Register and Bit field Definitions */
60#define DS 0x0
61#define DS_ST_STOP 0x0
62#define DS_ST_EXEC 0x1
63#define DS_ST_CMISS 0x2
64#define DS_ST_UPDTPC 0x3
65#define DS_ST_WFE 0x4
66#define DS_ST_ATBRR 0x5
67#define DS_ST_QBUSY 0x6
68#define DS_ST_WFP 0x7
69#define DS_ST_KILL 0x8
70#define DS_ST_CMPLT 0x9
71#define DS_ST_FLTCMP 0xe
72#define DS_ST_FAULT 0xf
73
74#define DPC 0x4
75#define INTEN 0x20
76#define ES 0x24
77#define INTSTATUS 0x28
78#define INTCLR 0x2c
79#define FSM 0x30
80#define FSC 0x34
81#define FTM 0x38
82
83#define _FTC 0x40
84#define FTC(n) (_FTC + (n)*0x4)
85
86#define _CS 0x100
87#define CS(n) (_CS + (n)*0x8)
88#define CS_CNS (1 << 21)
89
90#define _CPC 0x104
91#define CPC(n) (_CPC + (n)*0x8)
92
93#define _SA 0x400
94#define SA(n) (_SA + (n)*0x20)
95
96#define _DA 0x404
97#define DA(n) (_DA + (n)*0x20)
98
99#define _CC 0x408
100#define CC(n) (_CC + (n)*0x20)
101
102#define CC_SRCINC (1 << 0)
103#define CC_DSTINC (1 << 14)
104#define CC_SRCPRI (1 << 8)
105#define CC_DSTPRI (1 << 22)
106#define CC_SRCNS (1 << 9)
107#define CC_DSTNS (1 << 23)
108#define CC_SRCIA (1 << 10)
109#define CC_DSTIA (1 << 24)
110#define CC_SRCBRSTLEN_SHFT 4
111#define CC_DSTBRSTLEN_SHFT 18
112#define CC_SRCBRSTSIZE_SHFT 1
113#define CC_DSTBRSTSIZE_SHFT 15
114#define CC_SRCCCTRL_SHFT 11
115#define CC_SRCCCTRL_MASK 0x7
116#define CC_DSTCCTRL_SHFT 25
117#define CC_DRCCCTRL_MASK 0x7
118#define CC_SWAP_SHFT 28
119
120#define _LC0 0x40c
121#define LC0(n) (_LC0 + (n)*0x20)
122
123#define _LC1 0x410
124#define LC1(n) (_LC1 + (n)*0x20)
125
126#define DBGSTATUS 0xd00
127#define DBG_BUSY (1 << 0)
128
129#define DBGCMD 0xd04
130#define DBGINST0 0xd08
131#define DBGINST1 0xd0c
132
133#define CR0 0xe00
134#define CR1 0xe04
135#define CR2 0xe08
136#define CR3 0xe0c
137#define CR4 0xe10
138#define CRD 0xe14
139
140#define PERIPH_ID 0xfe0
Boojin Kim3ecf51a2011-12-26 18:55:47 +0900141#define PERIPH_REV_SHIFT 20
142#define PERIPH_REV_MASK 0xf
143#define PERIPH_REV_R0P0 0
144#define PERIPH_REV_R1P0 1
145#define PERIPH_REV_R1P1 2
Boojin Kimb7d861d2011-12-26 18:49:52 +0900146
147#define CR0_PERIPH_REQ_SET (1 << 0)
148#define CR0_BOOT_EN_SET (1 << 1)
149#define CR0_BOOT_MAN_NS (1 << 2)
150#define CR0_NUM_CHANS_SHIFT 4
151#define CR0_NUM_CHANS_MASK 0x7
152#define CR0_NUM_PERIPH_SHIFT 12
153#define CR0_NUM_PERIPH_MASK 0x1f
154#define CR0_NUM_EVENTS_SHIFT 17
155#define CR0_NUM_EVENTS_MASK 0x1f
156
157#define CR1_ICACHE_LEN_SHIFT 0
158#define CR1_ICACHE_LEN_MASK 0x7
159#define CR1_NUM_ICACHELINES_SHIFT 4
160#define CR1_NUM_ICACHELINES_MASK 0xf
161
162#define CRD_DATA_WIDTH_SHIFT 0
163#define CRD_DATA_WIDTH_MASK 0x7
164#define CRD_WR_CAP_SHIFT 4
165#define CRD_WR_CAP_MASK 0x7
166#define CRD_WR_Q_DEP_SHIFT 8
167#define CRD_WR_Q_DEP_MASK 0xf
168#define CRD_RD_CAP_SHIFT 12
169#define CRD_RD_CAP_MASK 0x7
170#define CRD_RD_Q_DEP_SHIFT 16
171#define CRD_RD_Q_DEP_MASK 0xf
172#define CRD_DATA_BUFF_SHIFT 20
173#define CRD_DATA_BUFF_MASK 0x3ff
174
175#define PART 0x330
176#define DESIGNER 0x41
177#define REVISION 0x0
178#define INTEG_CFG 0x0
179#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
180
Boojin Kimb7d861d2011-12-26 18:49:52 +0900181#define PL330_STATE_STOPPED (1 << 0)
182#define PL330_STATE_EXECUTING (1 << 1)
183#define PL330_STATE_WFE (1 << 2)
184#define PL330_STATE_FAULTING (1 << 3)
185#define PL330_STATE_COMPLETING (1 << 4)
186#define PL330_STATE_WFP (1 << 5)
187#define PL330_STATE_KILLING (1 << 6)
188#define PL330_STATE_FAULT_COMPLETING (1 << 7)
189#define PL330_STATE_CACHEMISS (1 << 8)
190#define PL330_STATE_UPDTPC (1 << 9)
191#define PL330_STATE_ATBARRIER (1 << 10)
192#define PL330_STATE_QUEUEBUSY (1 << 11)
193#define PL330_STATE_INVALID (1 << 15)
194
195#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
196 | PL330_STATE_WFE | PL330_STATE_FAULTING)
197
198#define CMD_DMAADDH 0x54
199#define CMD_DMAEND 0x00
200#define CMD_DMAFLUSHP 0x35
201#define CMD_DMAGO 0xa0
202#define CMD_DMALD 0x04
203#define CMD_DMALDP 0x25
204#define CMD_DMALP 0x20
205#define CMD_DMALPEND 0x28
206#define CMD_DMAKILL 0x01
207#define CMD_DMAMOV 0xbc
208#define CMD_DMANOP 0x18
209#define CMD_DMARMB 0x12
210#define CMD_DMASEV 0x34
211#define CMD_DMAST 0x08
212#define CMD_DMASTP 0x29
213#define CMD_DMASTZ 0x0c
214#define CMD_DMAWFE 0x36
215#define CMD_DMAWFP 0x30
216#define CMD_DMAWMB 0x13
217
218#define SZ_DMAADDH 3
219#define SZ_DMAEND 1
220#define SZ_DMAFLUSHP 2
221#define SZ_DMALD 1
222#define SZ_DMALDP 2
223#define SZ_DMALP 2
224#define SZ_DMALPEND 2
225#define SZ_DMAKILL 1
226#define SZ_DMAMOV 6
227#define SZ_DMANOP 1
228#define SZ_DMARMB 1
229#define SZ_DMASEV 2
230#define SZ_DMAST 1
231#define SZ_DMASTP 2
232#define SZ_DMASTZ 1
233#define SZ_DMAWFE 2
234#define SZ_DMAWFP 2
235#define SZ_DMAWMB 1
236#define SZ_DMAGO 6
237
238#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
239#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
240
241#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
242#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
243
244/*
245 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
246 * at 1byte/burst for P<->M and M<->M respectively.
247 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
248 * should be enough for P<->M and M<->M respectively.
249 */
250#define MCODE_BUFF_PER_REQ 256
251
Boojin Kimb7d861d2011-12-26 18:49:52 +0900252/* Use this _only_ to wait on transient states */
253#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
254
255#ifdef PL330_DEBUG_MCGEN
256static unsigned cmd_line;
257#define PL330_DBGCMD_DUMP(off, x...) do { \
258 printk("%x:", cmd_line); \
259 printk(x); \
260 cmd_line += off; \
261 } while (0)
262#define PL330_DBGMC_START(addr) (cmd_line = addr)
263#else
264#define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
265#define PL330_DBGMC_START(addr) do {} while (0)
266#endif
267
268/* The number of default descriptors */
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +0000269
Jassi Brarb3040e42010-05-23 20:28:19 -0700270#define NR_DEFAULT_DESC 16
271
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +0100272/* Delay for runtime PM autosuspend, ms */
273#define PL330_AUTOSUSPEND_DELAY 20
274
Boojin Kimb7d861d2011-12-26 18:49:52 +0900275/* Populated by the PL330 core driver for DMA API driver's info */
276struct pl330_config {
277 u32 periph_id;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900278#define DMAC_MODE_NS (1 << 0)
279 unsigned int mode;
280 unsigned int data_bus_width:10; /* In number of bits */
Liviu Dudau1f0a5cb2014-11-06 17:20:12 +0000281 unsigned int data_buf_dep:11;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900282 unsigned int num_chan:4;
283 unsigned int num_peri:6;
284 u32 peri_ns;
285 unsigned int num_events:6;
286 u32 irq_ns;
287};
288
Boojin Kimb7d861d2011-12-26 18:49:52 +0900289/**
290 * Request Configuration.
291 * The PL330 core does not modify this and uses the last
292 * working configuration if the request doesn't provide any.
293 *
294 * The Client may want to provide this info only for the
295 * first request and a request with new settings.
296 */
297struct pl330_reqcfg {
298 /* Address Incrementing */
299 unsigned dst_inc:1;
300 unsigned src_inc:1;
301
302 /*
303 * For now, the SRC & DST protection levels
304 * and burst size/length are assumed same.
305 */
306 bool nonsecure;
307 bool privileged;
308 bool insnaccess;
309 unsigned brst_len:5;
310 unsigned brst_size:3; /* in power of 2 */
311
Lars-Peter Clausenf0564c72014-07-06 20:32:19 +0200312 enum pl330_cachectrl dcctl;
313 enum pl330_cachectrl scctl;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900314 enum pl330_byteswap swap;
Boojin Kim3ecf51a2011-12-26 18:55:47 +0900315 struct pl330_config *pcfg;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900316};
317
318/*
319 * One cycle of DMAC operation.
320 * There may be more than one xfer in a request.
321 */
322struct pl330_xfer {
323 u32 src_addr;
324 u32 dst_addr;
325 /* Size to xfer */
326 u32 bytes;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900327};
328
329/* The xfer callbacks are made with one of these arguments. */
330enum pl330_op_err {
331 /* The all xfers in the request were success. */
332 PL330_ERR_NONE,
333 /* If req aborted due to global error. */
334 PL330_ERR_ABORT,
335 /* If req failed due to problem with Channel. */
336 PL330_ERR_FAIL,
337};
338
Boojin Kimb7d861d2011-12-26 18:49:52 +0900339enum dmamov_dst {
340 SAR = 0,
341 CCR,
342 DAR,
343};
344
345enum pl330_dst {
346 SRC = 0,
347 DST,
348};
349
350enum pl330_cond {
351 SINGLE,
352 BURST,
353 ALWAYS,
354};
355
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +0200356struct dma_pl330_desc;
357
Boojin Kimb7d861d2011-12-26 18:49:52 +0900358struct _pl330_req {
359 u32 mc_bus;
360 void *mc_cpu;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +0200361 struct dma_pl330_desc *desc;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900362};
363
364/* ToBeDone for tasklet */
365struct _pl330_tbd {
366 bool reset_dmac;
367 bool reset_mngr;
368 u8 reset_chan;
369};
370
371/* A DMAC Thread */
372struct pl330_thread {
373 u8 id;
374 int ev;
375 /* If the channel is not yet acquired by any client */
376 bool free;
377 /* Parent DMAC */
378 struct pl330_dmac *dmac;
379 /* Only two at a time */
380 struct _pl330_req req[2];
381 /* Index of the last enqueued request */
382 unsigned lstenq;
383 /* Index of the last submitted request or -1 if the DMA is stopped */
384 int req_running;
385};
386
387enum pl330_dmac_state {
388 UNINIT,
389 INIT,
390 DYING,
391};
392
Jassi Brarb3040e42010-05-23 20:28:19 -0700393enum desc_status {
394 /* In the DMAC pool */
395 FREE,
396 /*
Masanari Iidad73111c2012-08-04 23:37:53 +0900397 * Allocated to some channel during prep_xxx
Jassi Brarb3040e42010-05-23 20:28:19 -0700398 * Also may be sitting on the work_list.
399 */
400 PREP,
401 /*
402 * Sitting on the work_list and already submitted
403 * to the PL330 core. Not more than two descriptors
404 * of a channel can be BUSY at any time.
405 */
406 BUSY,
407 /*
408 * Sitting on the channel work_list but xfer done
409 * by PL330 core
410 */
411 DONE,
412};
413
414struct dma_pl330_chan {
415 /* Schedule desc completion */
416 struct tasklet_struct task;
417
418 /* DMA-Engine Channel */
419 struct dma_chan chan;
420
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +0100421 /* List of submitted descriptors */
422 struct list_head submitted_list;
423 /* List of issued descriptors */
Jassi Brarb3040e42010-05-23 20:28:19 -0700424 struct list_head work_list;
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +0200425 /* List of completed descriptors */
426 struct list_head completed_list;
Jassi Brarb3040e42010-05-23 20:28:19 -0700427
428 /* Pointer to the DMAC that manages this channel,
429 * NULL if the channel is available to be acquired.
430 * As the parent, this DMAC also provides descriptors
431 * to the channel.
432 */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200433 struct pl330_dmac *dmac;
Jassi Brarb3040e42010-05-23 20:28:19 -0700434
435 /* To protect channel manipulation */
436 spinlock_t lock;
437
Lars-Peter Clausen65ad6062014-07-06 20:32:26 +0200438 /*
439 * Hardware channel thread of PL330 DMAC. NULL if the channel is
440 * available.
Jassi Brarb3040e42010-05-23 20:28:19 -0700441 */
Lars-Peter Clausen65ad6062014-07-06 20:32:26 +0200442 struct pl330_thread *thread;
Boojin Kim1b9bb712011-09-02 09:44:30 +0900443
444 /* For D-to-M and M-to-D channels */
445 int burst_sz; /* the peripheral fifo width */
Boojin Kim1d0c1d62011-09-02 09:44:31 +0900446 int burst_len; /* the number of burst */
Boojin Kim1b9bb712011-09-02 09:44:30 +0900447 dma_addr_t fifo_addr;
Boojin Kim42bc9cf2011-09-02 09:44:33 +0900448
449 /* for cyclic capability */
450 bool cyclic;
Jassi Brarb3040e42010-05-23 20:28:19 -0700451};
452
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200453struct pl330_dmac {
Jassi Brarb3040e42010-05-23 20:28:19 -0700454 /* DMA-Engine Device */
455 struct dma_device ddma;
456
Lars-Peter Clausenb714b842013-11-25 16:07:46 +0100457 /* Holds info about sg limitations */
458 struct device_dma_parameters dma_parms;
459
Jassi Brarb3040e42010-05-23 20:28:19 -0700460 /* Pool of descriptors available for the DMAC's channels */
461 struct list_head desc_pool;
462 /* To protect desc_pool manipulation */
463 spinlock_t pool_lock;
464
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200465 /* Size of MicroCode buffers for each channel. */
466 unsigned mcbufsz;
467 /* ioremap'ed address of PL330 registers. */
468 void __iomem *base;
469 /* Populated by the PL330 core driver during pl330_add */
470 struct pl330_config pcfg;
471
472 spinlock_t lock;
473 /* Maximum possible events/irqs */
474 int events[32];
475 /* BUS address of MicroCode buffer */
476 dma_addr_t mcode_bus;
477 /* CPU address of MicroCode buffer */
478 void *mcode_cpu;
479 /* List of all Channel threads */
480 struct pl330_thread *channels;
481 /* Pointer to the MANAGER thread */
482 struct pl330_thread *manager;
483 /* To handle bad news in interrupt */
484 struct tasklet_struct tasks;
485 struct _pl330_tbd dmac_tbd;
486 /* State of DMAC operation */
487 enum pl330_dmac_state state;
488 /* Holds list of reqs with due callbacks */
489 struct list_head req_done;
490
Jassi Brarb3040e42010-05-23 20:28:19 -0700491 /* Peripheral channels connected to this DMAC */
Lars-Peter Clausen70cbb162014-01-11 20:08:39 +0100492 unsigned int num_peripherals;
Rob Herring4e0e6102011-07-25 16:05:04 -0500493 struct dma_pl330_chan *peripherals; /* keep at end */
Addy Ke271e1b862016-01-22 19:06:46 +0800494 int quirks;
495};
496
497static struct pl330_of_quirks {
498 char *quirk;
499 int id;
500} of_quirks[] = {
501 {
502 .quirk = "arm,pl330-broken-no-flushp",
503 .id = PL330_QUIRK_BROKEN_NO_FLUSHP,
504 }
Jassi Brarb3040e42010-05-23 20:28:19 -0700505};
506
507struct dma_pl330_desc {
508 /* To attach to a queue as child */
509 struct list_head node;
510
511 /* Descriptor for the DMA Engine API */
512 struct dma_async_tx_descriptor txd;
513
514 /* Xfer for PL330 core */
515 struct pl330_xfer px;
516
517 struct pl330_reqcfg rqcfg;
Jassi Brarb3040e42010-05-23 20:28:19 -0700518
519 enum desc_status status;
520
Robert Baldygaaee4d1f2015-02-11 13:23:17 +0100521 int bytes_requested;
522 bool last;
523
Jassi Brarb3040e42010-05-23 20:28:19 -0700524 /* The channel which currently holds this desc */
525 struct dma_pl330_chan *pchan;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +0200526
527 enum dma_transfer_direction rqtype;
528 /* Index of peripheral for the xfer. */
529 unsigned peri:5;
530 /* Hook to attach to DMAC's list of reqs with due callback */
531 struct list_head rqd;
532};
533
534struct _xfer_spec {
535 u32 ccr;
536 struct dma_pl330_desc *desc;
Jassi Brarb3040e42010-05-23 20:28:19 -0700537};
538
Boojin Kimb7d861d2011-12-26 18:49:52 +0900539static inline bool _queue_empty(struct pl330_thread *thrd)
540{
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +0200541 return thrd->req[0].desc == NULL && thrd->req[1].desc == NULL;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900542}
543
544static inline bool _queue_full(struct pl330_thread *thrd)
545{
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +0200546 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900547}
548
549static inline bool is_manager(struct pl330_thread *thrd)
550{
Lars-Peter Clausenfbbcd9b2014-07-06 20:32:28 +0200551 return thrd->dmac->manager == thrd;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900552}
553
554/* If manager of the thread is in Non-Secure mode */
555static inline bool _manager_ns(struct pl330_thread *thrd)
556{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200557 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900558}
559
Boojin Kim3ecf51a2011-12-26 18:55:47 +0900560static inline u32 get_revision(u32 periph_id)
561{
562 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
563}
564
Boojin Kimb7d861d2011-12-26 18:49:52 +0900565static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
566 enum pl330_dst da, u16 val)
567{
568 if (dry_run)
569 return SZ_DMAADDH;
570
571 buf[0] = CMD_DMAADDH;
572 buf[0] |= (da << 1);
Ben Dooks3a2307f2015-03-16 11:52:43 +0000573 *((__le16 *)&buf[1]) = cpu_to_le16(val);
Boojin Kimb7d861d2011-12-26 18:49:52 +0900574
575 PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
576 da == 1 ? "DA" : "SA", val);
577
578 return SZ_DMAADDH;
579}
580
581static inline u32 _emit_END(unsigned dry_run, u8 buf[])
582{
583 if (dry_run)
584 return SZ_DMAEND;
585
586 buf[0] = CMD_DMAEND;
587
588 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
589
590 return SZ_DMAEND;
591}
592
593static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
594{
595 if (dry_run)
596 return SZ_DMAFLUSHP;
597
598 buf[0] = CMD_DMAFLUSHP;
599
600 peri &= 0x1f;
601 peri <<= 3;
602 buf[1] = peri;
603
604 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
605
606 return SZ_DMAFLUSHP;
607}
608
609static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
610{
611 if (dry_run)
612 return SZ_DMALD;
613
614 buf[0] = CMD_DMALD;
615
616 if (cond == SINGLE)
617 buf[0] |= (0 << 1) | (1 << 0);
618 else if (cond == BURST)
619 buf[0] |= (1 << 1) | (1 << 0);
620
621 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
622 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
623
624 return SZ_DMALD;
625}
626
627static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
628 enum pl330_cond cond, u8 peri)
629{
630 if (dry_run)
631 return SZ_DMALDP;
632
633 buf[0] = CMD_DMALDP;
634
635 if (cond == BURST)
636 buf[0] |= (1 << 1);
637
638 peri &= 0x1f;
639 peri <<= 3;
640 buf[1] = peri;
641
642 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
643 cond == SINGLE ? 'S' : 'B', peri >> 3);
644
645 return SZ_DMALDP;
646}
647
648static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
649 unsigned loop, u8 cnt)
650{
651 if (dry_run)
652 return SZ_DMALP;
653
654 buf[0] = CMD_DMALP;
655
656 if (loop)
657 buf[0] |= (1 << 1);
658
659 cnt--; /* DMAC increments by 1 internally */
660 buf[1] = cnt;
661
662 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
663
664 return SZ_DMALP;
665}
666
667struct _arg_LPEND {
668 enum pl330_cond cond;
669 bool forever;
670 unsigned loop;
671 u8 bjump;
672};
673
674static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
675 const struct _arg_LPEND *arg)
676{
677 enum pl330_cond cond = arg->cond;
678 bool forever = arg->forever;
679 unsigned loop = arg->loop;
680 u8 bjump = arg->bjump;
681
682 if (dry_run)
683 return SZ_DMALPEND;
684
685 buf[0] = CMD_DMALPEND;
686
687 if (loop)
688 buf[0] |= (1 << 2);
689
690 if (!forever)
691 buf[0] |= (1 << 4);
692
693 if (cond == SINGLE)
694 buf[0] |= (0 << 1) | (1 << 0);
695 else if (cond == BURST)
696 buf[0] |= (1 << 1) | (1 << 0);
697
698 buf[1] = bjump;
699
700 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
701 forever ? "FE" : "END",
702 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
703 loop ? '1' : '0',
704 bjump);
705
706 return SZ_DMALPEND;
707}
708
709static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
710{
711 if (dry_run)
712 return SZ_DMAKILL;
713
714 buf[0] = CMD_DMAKILL;
715
716 return SZ_DMAKILL;
717}
718
719static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
720 enum dmamov_dst dst, u32 val)
721{
722 if (dry_run)
723 return SZ_DMAMOV;
724
725 buf[0] = CMD_DMAMOV;
726 buf[1] = dst;
Ben Dooks3a2307f2015-03-16 11:52:43 +0000727 *((__le32 *)&buf[2]) = cpu_to_le32(val);
Boojin Kimb7d861d2011-12-26 18:49:52 +0900728
729 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
730 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
731
732 return SZ_DMAMOV;
733}
734
735static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
736{
737 if (dry_run)
738 return SZ_DMANOP;
739
740 buf[0] = CMD_DMANOP;
741
742 PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
743
744 return SZ_DMANOP;
745}
746
747static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
748{
749 if (dry_run)
750 return SZ_DMARMB;
751
752 buf[0] = CMD_DMARMB;
753
754 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
755
756 return SZ_DMARMB;
757}
758
759static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
760{
761 if (dry_run)
762 return SZ_DMASEV;
763
764 buf[0] = CMD_DMASEV;
765
766 ev &= 0x1f;
767 ev <<= 3;
768 buf[1] = ev;
769
770 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
771
772 return SZ_DMASEV;
773}
774
775static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
776{
777 if (dry_run)
778 return SZ_DMAST;
779
780 buf[0] = CMD_DMAST;
781
782 if (cond == SINGLE)
783 buf[0] |= (0 << 1) | (1 << 0);
784 else if (cond == BURST)
785 buf[0] |= (1 << 1) | (1 << 0);
786
787 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
788 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
789
790 return SZ_DMAST;
791}
792
793static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
794 enum pl330_cond cond, u8 peri)
795{
796 if (dry_run)
797 return SZ_DMASTP;
798
799 buf[0] = CMD_DMASTP;
800
801 if (cond == BURST)
802 buf[0] |= (1 << 1);
803
804 peri &= 0x1f;
805 peri <<= 3;
806 buf[1] = peri;
807
808 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
809 cond == SINGLE ? 'S' : 'B', peri >> 3);
810
811 return SZ_DMASTP;
812}
813
814static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
815{
816 if (dry_run)
817 return SZ_DMASTZ;
818
819 buf[0] = CMD_DMASTZ;
820
821 PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
822
823 return SZ_DMASTZ;
824}
825
826static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
827 unsigned invalidate)
828{
829 if (dry_run)
830 return SZ_DMAWFE;
831
832 buf[0] = CMD_DMAWFE;
833
834 ev &= 0x1f;
835 ev <<= 3;
836 buf[1] = ev;
837
838 if (invalidate)
839 buf[1] |= (1 << 1);
840
841 PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
842 ev >> 3, invalidate ? ", I" : "");
843
844 return SZ_DMAWFE;
845}
846
847static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
848 enum pl330_cond cond, u8 peri)
849{
850 if (dry_run)
851 return SZ_DMAWFP;
852
853 buf[0] = CMD_DMAWFP;
854
855 if (cond == SINGLE)
856 buf[0] |= (0 << 1) | (0 << 0);
857 else if (cond == BURST)
858 buf[0] |= (1 << 1) | (0 << 0);
859 else
860 buf[0] |= (0 << 1) | (1 << 0);
861
862 peri &= 0x1f;
863 peri <<= 3;
864 buf[1] = peri;
865
866 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
867 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
868
869 return SZ_DMAWFP;
870}
871
872static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
873{
874 if (dry_run)
875 return SZ_DMAWMB;
876
877 buf[0] = CMD_DMAWMB;
878
879 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
880
881 return SZ_DMAWMB;
882}
883
884struct _arg_GO {
885 u8 chan;
886 u32 addr;
887 unsigned ns;
888};
889
890static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
891 const struct _arg_GO *arg)
892{
893 u8 chan = arg->chan;
894 u32 addr = arg->addr;
895 unsigned ns = arg->ns;
896
897 if (dry_run)
898 return SZ_DMAGO;
899
900 buf[0] = CMD_DMAGO;
901 buf[0] |= (ns << 1);
902
903 buf[1] = chan & 0x7;
904
Ben Dooks3a2307f2015-03-16 11:52:43 +0000905 *((__le32 *)&buf[2]) = cpu_to_le32(addr);
Boojin Kimb7d861d2011-12-26 18:49:52 +0900906
907 return SZ_DMAGO;
908}
909
910#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
911
912/* Returns Time-Out */
913static bool _until_dmac_idle(struct pl330_thread *thrd)
914{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200915 void __iomem *regs = thrd->dmac->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900916 unsigned long loops = msecs_to_loops(5);
917
918 do {
919 /* Until Manager is Idle */
920 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
921 break;
922
923 cpu_relax();
924 } while (--loops);
925
926 if (!loops)
927 return true;
928
929 return false;
930}
931
932static inline void _execute_DBGINSN(struct pl330_thread *thrd,
933 u8 insn[], bool as_manager)
934{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200935 void __iomem *regs = thrd->dmac->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900936 u32 val;
937
938 val = (insn[0] << 16) | (insn[1] << 24);
939 if (!as_manager) {
940 val |= (1 << 0);
941 val |= (thrd->id << 8); /* Channel Number */
942 }
943 writel(val, regs + DBGINST0);
944
Ben Dooks3a2307f2015-03-16 11:52:43 +0000945 val = le32_to_cpu(*((__le32 *)&insn[2]));
Boojin Kimb7d861d2011-12-26 18:49:52 +0900946 writel(val, regs + DBGINST1);
947
948 /* If timed out due to halted state-machine */
949 if (_until_dmac_idle(thrd)) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200950 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
Boojin Kimb7d861d2011-12-26 18:49:52 +0900951 return;
952 }
953
954 /* Get going */
955 writel(0, regs + DBGCMD);
956}
957
Boojin Kimb7d861d2011-12-26 18:49:52 +0900958static inline u32 _state(struct pl330_thread *thrd)
959{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200960 void __iomem *regs = thrd->dmac->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900961 u32 val;
962
963 if (is_manager(thrd))
964 val = readl(regs + DS) & 0xf;
965 else
966 val = readl(regs + CS(thrd->id)) & 0xf;
967
968 switch (val) {
969 case DS_ST_STOP:
970 return PL330_STATE_STOPPED;
971 case DS_ST_EXEC:
972 return PL330_STATE_EXECUTING;
973 case DS_ST_CMISS:
974 return PL330_STATE_CACHEMISS;
975 case DS_ST_UPDTPC:
976 return PL330_STATE_UPDTPC;
977 case DS_ST_WFE:
978 return PL330_STATE_WFE;
979 case DS_ST_FAULT:
980 return PL330_STATE_FAULTING;
981 case DS_ST_ATBRR:
982 if (is_manager(thrd))
983 return PL330_STATE_INVALID;
984 else
985 return PL330_STATE_ATBARRIER;
986 case DS_ST_QBUSY:
987 if (is_manager(thrd))
988 return PL330_STATE_INVALID;
989 else
990 return PL330_STATE_QUEUEBUSY;
991 case DS_ST_WFP:
992 if (is_manager(thrd))
993 return PL330_STATE_INVALID;
994 else
995 return PL330_STATE_WFP;
996 case DS_ST_KILL:
997 if (is_manager(thrd))
998 return PL330_STATE_INVALID;
999 else
1000 return PL330_STATE_KILLING;
1001 case DS_ST_CMPLT:
1002 if (is_manager(thrd))
1003 return PL330_STATE_INVALID;
1004 else
1005 return PL330_STATE_COMPLETING;
1006 case DS_ST_FLTCMP:
1007 if (is_manager(thrd))
1008 return PL330_STATE_INVALID;
1009 else
1010 return PL330_STATE_FAULT_COMPLETING;
1011 default:
1012 return PL330_STATE_INVALID;
1013 }
1014}
1015
1016static void _stop(struct pl330_thread *thrd)
1017{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001018 void __iomem *regs = thrd->dmac->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001019 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1020
1021 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
1022 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1023
1024 /* Return if nothing needs to be done */
1025 if (_state(thrd) == PL330_STATE_COMPLETING
1026 || _state(thrd) == PL330_STATE_KILLING
1027 || _state(thrd) == PL330_STATE_STOPPED)
1028 return;
1029
1030 _emit_KILL(0, insn);
1031
1032 /* Stop generating interrupts for SEV */
1033 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
1034
1035 _execute_DBGINSN(thrd, insn, is_manager(thrd));
1036}
1037
1038/* Start doing req 'idx' of thread 'thrd' */
1039static bool _trigger(struct pl330_thread *thrd)
1040{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001041 void __iomem *regs = thrd->dmac->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001042 struct _pl330_req *req;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001043 struct dma_pl330_desc *desc;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001044 struct _arg_GO go;
1045 unsigned ns;
1046 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1047 int idx;
1048
1049 /* Return if already ACTIVE */
1050 if (_state(thrd) != PL330_STATE_STOPPED)
1051 return true;
1052
1053 idx = 1 - thrd->lstenq;
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001054 if (thrd->req[idx].desc != NULL) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001055 req = &thrd->req[idx];
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001056 } else {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001057 idx = thrd->lstenq;
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001058 if (thrd->req[idx].desc != NULL)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001059 req = &thrd->req[idx];
1060 else
1061 req = NULL;
1062 }
1063
1064 /* Return if no request */
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001065 if (!req)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001066 return true;
1067
Addy Ke0091b9d2014-12-08 19:28:20 +08001068 /* Return if req is running */
1069 if (idx == thrd->req_running)
1070 return true;
1071
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001072 desc = req->desc;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001073
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001074 ns = desc->rqcfg.nonsecure ? 1 : 0;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001075
1076 /* See 'Abort Sources' point-4 at Page 2-25 */
1077 if (_manager_ns(thrd) && !ns)
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001078 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
Boojin Kimb7d861d2011-12-26 18:49:52 +09001079 __func__, __LINE__);
1080
1081 go.chan = thrd->id;
1082 go.addr = req->mc_bus;
1083 go.ns = ns;
1084 _emit_GO(0, insn, &go);
1085
1086 /* Set to generate interrupts for SEV */
1087 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1088
1089 /* Only manager can execute GO */
1090 _execute_DBGINSN(thrd, insn, true);
1091
1092 thrd->req_running = idx;
1093
1094 return true;
1095}
1096
1097static bool _start(struct pl330_thread *thrd)
1098{
1099 switch (_state(thrd)) {
1100 case PL330_STATE_FAULT_COMPLETING:
1101 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1102
1103 if (_state(thrd) == PL330_STATE_KILLING)
1104 UNTIL(thrd, PL330_STATE_STOPPED)
1105
1106 case PL330_STATE_FAULTING:
1107 _stop(thrd);
1108
1109 case PL330_STATE_KILLING:
1110 case PL330_STATE_COMPLETING:
1111 UNTIL(thrd, PL330_STATE_STOPPED)
1112
1113 case PL330_STATE_STOPPED:
1114 return _trigger(thrd);
1115
1116 case PL330_STATE_WFP:
1117 case PL330_STATE_QUEUEBUSY:
1118 case PL330_STATE_ATBARRIER:
1119 case PL330_STATE_UPDTPC:
1120 case PL330_STATE_CACHEMISS:
1121 case PL330_STATE_EXECUTING:
1122 return true;
1123
1124 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1125 default:
1126 return false;
1127 }
1128}
1129
1130static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1131 const struct _xfer_spec *pxs, int cyc)
1132{
1133 int off = 0;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001134 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001135
Boojin Kim3ecf51a2011-12-26 18:55:47 +09001136 /* check lock-up free version */
1137 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1138 while (cyc--) {
1139 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1140 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1141 }
1142 } else {
1143 while (cyc--) {
1144 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1145 off += _emit_RMB(dry_run, &buf[off]);
1146 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1147 off += _emit_WMB(dry_run, &buf[off]);
1148 }
Boojin Kimb7d861d2011-12-26 18:49:52 +09001149 }
1150
1151 return off;
1152}
1153
Addy Ke271e1b862016-01-22 19:06:46 +08001154static inline int _ldst_devtomem(struct pl330_dmac *pl330, unsigned dry_run,
1155 u8 buf[], const struct _xfer_spec *pxs,
1156 int cyc)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001157{
1158 int off = 0;
Boojin Kim848e9772016-01-22 19:06:44 +08001159 enum pl330_cond cond;
1160
Addy Ke271e1b862016-01-22 19:06:46 +08001161 if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
1162 cond = BURST;
1163 else
1164 cond = (pxs->desc->rqcfg.brst_len == 1) ? SINGLE : BURST;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001165
1166 while (cyc--) {
Boojin Kim848e9772016-01-22 19:06:44 +08001167 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1168 off += _emit_LDP(dry_run, &buf[off], cond, pxs->desc->peri);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001169 off += _emit_ST(dry_run, &buf[off], ALWAYS);
Addy Ke271e1b862016-01-22 19:06:46 +08001170
1171 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1172 off += _emit_FLUSHP(dry_run, &buf[off],
1173 pxs->desc->peri);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001174 }
1175
1176 return off;
1177}
1178
Addy Ke271e1b862016-01-22 19:06:46 +08001179static inline int _ldst_memtodev(struct pl330_dmac *pl330,
1180 unsigned dry_run, u8 buf[],
1181 const struct _xfer_spec *pxs, int cyc)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001182{
1183 int off = 0;
Boojin Kim848e9772016-01-22 19:06:44 +08001184 enum pl330_cond cond;
1185
Addy Ke271e1b862016-01-22 19:06:46 +08001186 if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
1187 cond = BURST;
1188 else
1189 cond = (pxs->desc->rqcfg.brst_len == 1) ? SINGLE : BURST;
1190
Boojin Kimb7d861d2011-12-26 18:49:52 +09001191
1192 while (cyc--) {
Boojin Kim848e9772016-01-22 19:06:44 +08001193 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001194 off += _emit_LD(dry_run, &buf[off], ALWAYS);
Boojin Kim848e9772016-01-22 19:06:44 +08001195 off += _emit_STP(dry_run, &buf[off], cond, pxs->desc->peri);
Addy Ke271e1b862016-01-22 19:06:46 +08001196
1197 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1198 off += _emit_FLUSHP(dry_run, &buf[off],
1199 pxs->desc->peri);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001200 }
1201
1202 return off;
1203}
1204
Addy Ke271e1b862016-01-22 19:06:46 +08001205static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
Boojin Kimb7d861d2011-12-26 18:49:52 +09001206 const struct _xfer_spec *pxs, int cyc)
1207{
1208 int off = 0;
1209
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001210 switch (pxs->desc->rqtype) {
Lars-Peter Clausen585a9d02014-07-06 20:32:18 +02001211 case DMA_MEM_TO_DEV:
Addy Ke271e1b862016-01-22 19:06:46 +08001212 off += _ldst_memtodev(pl330, dry_run, &buf[off], pxs, cyc);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001213 break;
Lars-Peter Clausen585a9d02014-07-06 20:32:18 +02001214 case DMA_DEV_TO_MEM:
Addy Ke271e1b862016-01-22 19:06:46 +08001215 off += _ldst_devtomem(pl330, dry_run, &buf[off], pxs, cyc);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001216 break;
Lars-Peter Clausen585a9d02014-07-06 20:32:18 +02001217 case DMA_MEM_TO_MEM:
Boojin Kimb7d861d2011-12-26 18:49:52 +09001218 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1219 break;
1220 default:
1221 off += 0x40000000; /* Scare off the Client */
1222 break;
1223 }
1224
1225 return off;
1226}
1227
1228/* Returns bytes consumed and updates bursts */
Addy Ke271e1b862016-01-22 19:06:46 +08001229static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
Boojin Kimb7d861d2011-12-26 18:49:52 +09001230 unsigned long *bursts, const struct _xfer_spec *pxs)
1231{
1232 int cyc, cycmax, szlp, szlpend, szbrst, off;
1233 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1234 struct _arg_LPEND lpend;
1235
Michal Suchanek31495d62015-07-23 18:04:49 +02001236 if (*bursts == 1)
Boojin Kim848e9772016-01-22 19:06:44 +08001237 return _bursts(pl330, dry_run, buf, pxs, 1);
Michal Suchanek31495d62015-07-23 18:04:49 +02001238
Boojin Kimb7d861d2011-12-26 18:49:52 +09001239 /* Max iterations possible in DMALP is 256 */
1240 if (*bursts >= 256*256) {
1241 lcnt1 = 256;
1242 lcnt0 = 256;
1243 cyc = *bursts / lcnt1 / lcnt0;
1244 } else if (*bursts > 256) {
1245 lcnt1 = 256;
1246 lcnt0 = *bursts / lcnt1;
1247 cyc = 1;
1248 } else {
1249 lcnt1 = *bursts;
1250 lcnt0 = 0;
1251 cyc = 1;
1252 }
1253
1254 szlp = _emit_LP(1, buf, 0, 0);
Addy Ke271e1b862016-01-22 19:06:46 +08001255 szbrst = _bursts(pl330, 1, buf, pxs, 1);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001256
1257 lpend.cond = ALWAYS;
1258 lpend.forever = false;
1259 lpend.loop = 0;
1260 lpend.bjump = 0;
1261 szlpend = _emit_LPEND(1, buf, &lpend);
1262
1263 if (lcnt0) {
1264 szlp *= 2;
1265 szlpend *= 2;
1266 }
1267
1268 /*
1269 * Max bursts that we can unroll due to limit on the
1270 * size of backward jump that can be encoded in DMALPEND
1271 * which is 8-bits and hence 255
1272 */
1273 cycmax = (255 - (szlp + szlpend)) / szbrst;
1274
1275 cyc = (cycmax < cyc) ? cycmax : cyc;
1276
1277 off = 0;
1278
1279 if (lcnt0) {
1280 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1281 ljmp0 = off;
1282 }
1283
1284 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1285 ljmp1 = off;
1286
Addy Ke271e1b862016-01-22 19:06:46 +08001287 off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001288
1289 lpend.cond = ALWAYS;
1290 lpend.forever = false;
1291 lpend.loop = 1;
1292 lpend.bjump = off - ljmp1;
1293 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1294
1295 if (lcnt0) {
1296 lpend.cond = ALWAYS;
1297 lpend.forever = false;
1298 lpend.loop = 0;
1299 lpend.bjump = off - ljmp0;
1300 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1301 }
1302
1303 *bursts = lcnt1 * cyc;
1304 if (lcnt0)
1305 *bursts *= lcnt0;
1306
1307 return off;
1308}
1309
Addy Ke271e1b862016-01-22 19:06:46 +08001310static inline int _setup_loops(struct pl330_dmac *pl330,
1311 unsigned dry_run, u8 buf[],
1312 const struct _xfer_spec *pxs)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001313{
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001314 struct pl330_xfer *x = &pxs->desc->px;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001315 u32 ccr = pxs->ccr;
1316 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1317 int off = 0;
1318
1319 while (bursts) {
1320 c = bursts;
Addy Ke271e1b862016-01-22 19:06:46 +08001321 off += _loop(pl330, dry_run, &buf[off], &c, pxs);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001322 bursts -= c;
1323 }
1324
1325 return off;
1326}
1327
Addy Ke271e1b862016-01-22 19:06:46 +08001328static inline int _setup_xfer(struct pl330_dmac *pl330,
1329 unsigned dry_run, u8 buf[],
1330 const struct _xfer_spec *pxs)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001331{
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001332 struct pl330_xfer *x = &pxs->desc->px;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001333 int off = 0;
1334
1335 /* DMAMOV SAR, x->src_addr */
1336 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1337 /* DMAMOV DAR, x->dst_addr */
1338 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1339
1340 /* Setup Loop(s) */
Addy Ke271e1b862016-01-22 19:06:46 +08001341 off += _setup_loops(pl330, dry_run, &buf[off], pxs);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001342
1343 return off;
1344}
1345
1346/*
1347 * A req is a sequence of one or more xfer units.
1348 * Returns the number of bytes taken to setup the MC for the req.
1349 */
Addy Ke271e1b862016-01-22 19:06:46 +08001350static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
1351 struct pl330_thread *thrd, unsigned index,
1352 struct _xfer_spec *pxs)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001353{
1354 struct _pl330_req *req = &thrd->req[index];
1355 struct pl330_xfer *x;
1356 u8 *buf = req->mc_cpu;
1357 int off = 0;
1358
1359 PL330_DBGMC_START(req->mc_bus);
1360
1361 /* DMAMOV CCR, ccr */
1362 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1363
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001364 x = &pxs->desc->px;
Lars-Peter Clausend5cef122014-07-06 20:32:23 +02001365 /* Error if xfer length is not aligned at burst size */
1366 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1367 return -EINVAL;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001368
Addy Ke271e1b862016-01-22 19:06:46 +08001369 off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001370
1371 /* DMASEV peripheral/event */
1372 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1373 /* DMAEND */
1374 off += _emit_END(dry_run, &buf[off]);
1375
1376 return off;
1377}
1378
1379static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1380{
1381 u32 ccr = 0;
1382
1383 if (rqc->src_inc)
1384 ccr |= CC_SRCINC;
1385
1386 if (rqc->dst_inc)
1387 ccr |= CC_DSTINC;
1388
1389 /* We set same protection levels for Src and DST for now */
1390 if (rqc->privileged)
1391 ccr |= CC_SRCPRI | CC_DSTPRI;
1392 if (rqc->nonsecure)
1393 ccr |= CC_SRCNS | CC_DSTNS;
1394 if (rqc->insnaccess)
1395 ccr |= CC_SRCIA | CC_DSTIA;
1396
1397 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1398 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1399
1400 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1401 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1402
1403 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1404 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1405
1406 ccr |= (rqc->swap << CC_SWAP_SHFT);
1407
1408 return ccr;
1409}
1410
Boojin Kimb7d861d2011-12-26 18:49:52 +09001411/*
1412 * Submit a list of xfers after which the client wants notification.
1413 * Client is not notified after each xfer unit, just once after all
1414 * xfer units are done or some error occurs.
1415 */
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001416static int pl330_submit_req(struct pl330_thread *thrd,
1417 struct dma_pl330_desc *desc)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001418{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001419 struct pl330_dmac *pl330 = thrd->dmac;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001420 struct _xfer_spec xs;
1421 unsigned long flags;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001422 unsigned idx;
1423 u32 ccr;
1424 int ret = 0;
1425
Boojin Kimb7d861d2011-12-26 18:49:52 +09001426 if (pl330->state == DYING
1427 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001428 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
Boojin Kimb7d861d2011-12-26 18:49:52 +09001429 __func__, __LINE__);
1430 return -EAGAIN;
1431 }
1432
1433 /* If request for non-existing peripheral */
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001434 if (desc->rqtype != DMA_MEM_TO_MEM &&
1435 desc->peri >= pl330->pcfg.num_peri) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001436 dev_info(thrd->dmac->ddma.dev,
Boojin Kimb7d861d2011-12-26 18:49:52 +09001437 "%s:%d Invalid peripheral(%u)!\n",
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001438 __func__, __LINE__, desc->peri);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001439 return -EINVAL;
1440 }
1441
1442 spin_lock_irqsave(&pl330->lock, flags);
1443
1444 if (_queue_full(thrd)) {
1445 ret = -EAGAIN;
1446 goto xfer_exit;
1447 }
1448
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001449 /* Prefer Secure Channel */
1450 if (!_manager_ns(thrd))
1451 desc->rqcfg.nonsecure = 0;
1452 else
1453 desc->rqcfg.nonsecure = 1;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001454
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001455 ccr = _prepare_ccr(&desc->rqcfg);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001456
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001457 idx = thrd->req[0].desc == NULL ? 0 : 1;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001458
1459 xs.ccr = ccr;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001460 xs.desc = desc;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001461
1462 /* First dry run to check if req is acceptable */
Addy Ke271e1b862016-01-22 19:06:46 +08001463 ret = _setup_req(pl330, 1, thrd, idx, &xs);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001464 if (ret < 0)
1465 goto xfer_exit;
1466
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001467 if (ret > pl330->mcbufsz / 2) {
Michal Suchaneke5489d52015-06-03 21:26:41 +00001468 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1469 __func__, __LINE__, ret, pl330->mcbufsz / 2);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001470 ret = -ENOMEM;
1471 goto xfer_exit;
1472 }
1473
1474 /* Hook the request */
1475 thrd->lstenq = idx;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001476 thrd->req[idx].desc = desc;
Addy Ke271e1b862016-01-22 19:06:46 +08001477 _setup_req(pl330, 0, thrd, idx, &xs);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001478
1479 ret = 0;
1480
1481xfer_exit:
1482 spin_unlock_irqrestore(&pl330->lock, flags);
1483
1484 return ret;
1485}
1486
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001487static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
Lars-Peter Clausen6079d382014-07-06 20:32:25 +02001488{
Javier Martinez Canillasb1e51d72014-07-19 03:21:47 +02001489 struct dma_pl330_chan *pch;
Lars-Peter Clausen6079d382014-07-06 20:32:25 +02001490 unsigned long flags;
1491
Javier Martinez Canillasb1e51d72014-07-19 03:21:47 +02001492 if (!desc)
1493 return;
1494
1495 pch = desc->pchan;
1496
Lars-Peter Clausen6079d382014-07-06 20:32:25 +02001497 /* If desc aborted */
1498 if (!pch)
1499 return;
1500
1501 spin_lock_irqsave(&pch->lock, flags);
1502
1503 desc->status = DONE;
1504
1505 spin_unlock_irqrestore(&pch->lock, flags);
1506
1507 tasklet_schedule(&pch->task);
1508}
1509
Boojin Kimb7d861d2011-12-26 18:49:52 +09001510static void pl330_dotask(unsigned long data)
1511{
1512 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001513 unsigned long flags;
1514 int i;
1515
1516 spin_lock_irqsave(&pl330->lock, flags);
1517
1518 /* The DMAC itself gone nuts */
1519 if (pl330->dmac_tbd.reset_dmac) {
1520 pl330->state = DYING;
1521 /* Reset the manager too */
1522 pl330->dmac_tbd.reset_mngr = true;
1523 /* Clear the reset flag */
1524 pl330->dmac_tbd.reset_dmac = false;
1525 }
1526
1527 if (pl330->dmac_tbd.reset_mngr) {
1528 _stop(pl330->manager);
1529 /* Reset all channels */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001530 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001531 /* Clear the reset flag */
1532 pl330->dmac_tbd.reset_mngr = false;
1533 }
1534
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001535 for (i = 0; i < pl330->pcfg.num_chan; i++) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001536
1537 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1538 struct pl330_thread *thrd = &pl330->channels[i];
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001539 void __iomem *regs = pl330->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001540 enum pl330_op_err err;
1541
1542 _stop(thrd);
1543
1544 if (readl(regs + FSC) & (1 << thrd->id))
1545 err = PL330_ERR_FAIL;
1546 else
1547 err = PL330_ERR_ABORT;
1548
1549 spin_unlock_irqrestore(&pl330->lock, flags);
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001550 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1551 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001552 spin_lock_irqsave(&pl330->lock, flags);
1553
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001554 thrd->req[0].desc = NULL;
1555 thrd->req[1].desc = NULL;
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001556 thrd->req_running = -1;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001557
1558 /* Clear the reset flag */
1559 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1560 }
1561 }
1562
1563 spin_unlock_irqrestore(&pl330->lock, flags);
1564
1565 return;
1566}
1567
1568/* Returns 1 if state was updated, 0 otherwise */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001569static int pl330_update(struct pl330_dmac *pl330)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001570{
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001571 struct dma_pl330_desc *descdone, *tmp;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001572 unsigned long flags;
1573 void __iomem *regs;
1574 u32 val;
1575 int id, ev, ret = 0;
1576
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001577 regs = pl330->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001578
1579 spin_lock_irqsave(&pl330->lock, flags);
1580
1581 val = readl(regs + FSM) & 0x1;
1582 if (val)
1583 pl330->dmac_tbd.reset_mngr = true;
1584 else
1585 pl330->dmac_tbd.reset_mngr = false;
1586
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001587 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001588 pl330->dmac_tbd.reset_chan |= val;
1589 if (val) {
1590 int i = 0;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001591 while (i < pl330->pcfg.num_chan) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001592 if (val & (1 << i)) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001593 dev_info(pl330->ddma.dev,
Boojin Kimb7d861d2011-12-26 18:49:52 +09001594 "Reset Channel-%d\t CS-%x FTC-%x\n",
1595 i, readl(regs + CS(i)),
1596 readl(regs + FTC(i)));
1597 _stop(&pl330->channels[i]);
1598 }
1599 i++;
1600 }
1601 }
1602
1603 /* Check which event happened i.e, thread notified */
1604 val = readl(regs + ES);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001605 if (pl330->pcfg.num_events < 32
1606 && val & ~((1 << pl330->pcfg.num_events) - 1)) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001607 pl330->dmac_tbd.reset_dmac = true;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001608 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1609 __LINE__);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001610 ret = 1;
1611 goto updt_exit;
1612 }
1613
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001614 for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001615 if (val & (1 << ev)) { /* Event occurred */
1616 struct pl330_thread *thrd;
1617 u32 inten = readl(regs + INTEN);
1618 int active;
1619
1620 /* Clear the event */
1621 if (inten & (1 << ev))
1622 writel(1 << ev, regs + INTCLR);
1623
1624 ret = 1;
1625
1626 id = pl330->events[ev];
1627
1628 thrd = &pl330->channels[id];
1629
1630 active = thrd->req_running;
1631 if (active == -1) /* Aborted */
1632 continue;
1633
Javi Merinofdec53d2012-06-13 15:07:00 +01001634 /* Detach the req */
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001635 descdone = thrd->req[active].desc;
1636 thrd->req[active].desc = NULL;
Javi Merinofdec53d2012-06-13 15:07:00 +01001637
Addy Ke0091b9d2014-12-08 19:28:20 +08001638 thrd->req_running = -1;
1639
Boojin Kimb7d861d2011-12-26 18:49:52 +09001640 /* Get going again ASAP */
1641 _start(thrd);
1642
1643 /* For now, just make a list of callbacks to be done */
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001644 list_add_tail(&descdone->rqd, &pl330->req_done);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001645 }
1646 }
1647
1648 /* Now that we are in no hurry, do the callbacks */
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001649 list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) {
1650 list_del(&descdone->rqd);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001651 spin_unlock_irqrestore(&pl330->lock, flags);
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001652 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001653 spin_lock_irqsave(&pl330->lock, flags);
1654 }
1655
1656updt_exit:
1657 spin_unlock_irqrestore(&pl330->lock, flags);
1658
1659 if (pl330->dmac_tbd.reset_dmac
1660 || pl330->dmac_tbd.reset_mngr
1661 || pl330->dmac_tbd.reset_chan) {
1662 ret = 1;
1663 tasklet_schedule(&pl330->tasks);
1664 }
1665
1666 return ret;
1667}
1668
Boojin Kimb7d861d2011-12-26 18:49:52 +09001669/* Reserve an event */
1670static inline int _alloc_event(struct pl330_thread *thrd)
1671{
1672 struct pl330_dmac *pl330 = thrd->dmac;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001673 int ev;
1674
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001675 for (ev = 0; ev < pl330->pcfg.num_events; ev++)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001676 if (pl330->events[ev] == -1) {
1677 pl330->events[ev] = thrd->id;
1678 return ev;
1679 }
1680
1681 return -1;
1682}
1683
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001684static bool _chan_ns(const struct pl330_dmac *pl330, int i)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001685{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001686 return pl330->pcfg.irq_ns & (1 << i);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001687}
1688
1689/* Upon success, returns IdentityToken for the
1690 * allocated channel, NULL otherwise.
1691 */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001692static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001693{
1694 struct pl330_thread *thrd = NULL;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001695 unsigned long flags;
1696 int chans, i;
1697
Boojin Kimb7d861d2011-12-26 18:49:52 +09001698 if (pl330->state == DYING)
1699 return NULL;
1700
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001701 chans = pl330->pcfg.num_chan;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001702
1703 spin_lock_irqsave(&pl330->lock, flags);
1704
1705 for (i = 0; i < chans; i++) {
1706 thrd = &pl330->channels[i];
1707 if ((thrd->free) && (!_manager_ns(thrd) ||
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001708 _chan_ns(pl330, i))) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001709 thrd->ev = _alloc_event(thrd);
1710 if (thrd->ev >= 0) {
1711 thrd->free = false;
1712 thrd->lstenq = 1;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001713 thrd->req[0].desc = NULL;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001714 thrd->req[1].desc = NULL;
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001715 thrd->req_running = -1;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001716 break;
1717 }
1718 }
1719 thrd = NULL;
1720 }
1721
1722 spin_unlock_irqrestore(&pl330->lock, flags);
1723
1724 return thrd;
1725}
1726
1727/* Release an event */
1728static inline void _free_event(struct pl330_thread *thrd, int ev)
1729{
1730 struct pl330_dmac *pl330 = thrd->dmac;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001731
1732 /* If the event is valid and was held by the thread */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001733 if (ev >= 0 && ev < pl330->pcfg.num_events
Boojin Kimb7d861d2011-12-26 18:49:52 +09001734 && pl330->events[ev] == thrd->id)
1735 pl330->events[ev] = -1;
1736}
1737
Lars-Peter Clausen65ad6062014-07-06 20:32:26 +02001738static void pl330_release_channel(struct pl330_thread *thrd)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001739{
Boojin Kimb7d861d2011-12-26 18:49:52 +09001740 struct pl330_dmac *pl330;
1741 unsigned long flags;
1742
1743 if (!thrd || thrd->free)
1744 return;
1745
1746 _stop(thrd);
1747
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001748 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1749 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001750
1751 pl330 = thrd->dmac;
1752
1753 spin_lock_irqsave(&pl330->lock, flags);
1754 _free_event(thrd, thrd->ev);
1755 thrd->free = true;
1756 spin_unlock_irqrestore(&pl330->lock, flags);
1757}
1758
1759/* Initialize the structure for PL330 configuration, that can be used
1760 * by the client driver the make best use of the DMAC
1761 */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001762static void read_dmac_config(struct pl330_dmac *pl330)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001763{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001764 void __iomem *regs = pl330->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001765 u32 val;
1766
1767 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1768 val &= CRD_DATA_WIDTH_MASK;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001769 pl330->pcfg.data_bus_width = 8 * (1 << val);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001770
1771 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1772 val &= CRD_DATA_BUFF_MASK;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001773 pl330->pcfg.data_buf_dep = val + 1;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001774
1775 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1776 val &= CR0_NUM_CHANS_MASK;
1777 val += 1;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001778 pl330->pcfg.num_chan = val;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001779
1780 val = readl(regs + CR0);
1781 if (val & CR0_PERIPH_REQ_SET) {
1782 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1783 val += 1;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001784 pl330->pcfg.num_peri = val;
1785 pl330->pcfg.peri_ns = readl(regs + CR4);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001786 } else {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001787 pl330->pcfg.num_peri = 0;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001788 }
1789
1790 val = readl(regs + CR0);
1791 if (val & CR0_BOOT_MAN_NS)
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001792 pl330->pcfg.mode |= DMAC_MODE_NS;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001793 else
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001794 pl330->pcfg.mode &= ~DMAC_MODE_NS;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001795
1796 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1797 val &= CR0_NUM_EVENTS_MASK;
1798 val += 1;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001799 pl330->pcfg.num_events = val;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001800
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001801 pl330->pcfg.irq_ns = readl(regs + CR3);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001802}
1803
1804static inline void _reset_thread(struct pl330_thread *thrd)
1805{
1806 struct pl330_dmac *pl330 = thrd->dmac;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001807
1808 thrd->req[0].mc_cpu = pl330->mcode_cpu
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001809 + (thrd->id * pl330->mcbufsz);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001810 thrd->req[0].mc_bus = pl330->mcode_bus
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001811 + (thrd->id * pl330->mcbufsz);
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001812 thrd->req[0].desc = NULL;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001813
1814 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001815 + pl330->mcbufsz / 2;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001816 thrd->req[1].mc_bus = thrd->req[0].mc_bus
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001817 + pl330->mcbufsz / 2;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001818 thrd->req[1].desc = NULL;
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001819
1820 thrd->req_running = -1;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001821}
1822
1823static int dmac_alloc_threads(struct pl330_dmac *pl330)
1824{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001825 int chans = pl330->pcfg.num_chan;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001826 struct pl330_thread *thrd;
1827 int i;
1828
1829 /* Allocate 1 Manager and 'chans' Channel threads */
1830 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
1831 GFP_KERNEL);
1832 if (!pl330->channels)
1833 return -ENOMEM;
1834
1835 /* Init Channel threads */
1836 for (i = 0; i < chans; i++) {
1837 thrd = &pl330->channels[i];
1838 thrd->id = i;
1839 thrd->dmac = pl330;
1840 _reset_thread(thrd);
1841 thrd->free = true;
1842 }
1843
1844 /* MANAGER is indexed at the end */
1845 thrd = &pl330->channels[chans];
1846 thrd->id = chans;
1847 thrd->dmac = pl330;
1848 thrd->free = false;
1849 pl330->manager = thrd;
1850
1851 return 0;
1852}
1853
1854static int dmac_alloc_resources(struct pl330_dmac *pl330)
1855{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001856 int chans = pl330->pcfg.num_chan;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001857 int ret;
1858
1859 /*
1860 * Alloc MicroCode buffer for 'chans' Channel threads.
1861 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1862 */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001863 pl330->mcode_cpu = dma_alloc_coherent(pl330->ddma.dev,
1864 chans * pl330->mcbufsz,
Boojin Kimb7d861d2011-12-26 18:49:52 +09001865 &pl330->mcode_bus, GFP_KERNEL);
1866 if (!pl330->mcode_cpu) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001867 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
Boojin Kimb7d861d2011-12-26 18:49:52 +09001868 __func__, __LINE__);
1869 return -ENOMEM;
1870 }
1871
1872 ret = dmac_alloc_threads(pl330);
1873 if (ret) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001874 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
Boojin Kimb7d861d2011-12-26 18:49:52 +09001875 __func__, __LINE__);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001876 dma_free_coherent(pl330->ddma.dev,
1877 chans * pl330->mcbufsz,
Boojin Kimb7d861d2011-12-26 18:49:52 +09001878 pl330->mcode_cpu, pl330->mcode_bus);
1879 return ret;
1880 }
1881
1882 return 0;
1883}
1884
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001885static int pl330_add(struct pl330_dmac *pl330)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001886{
Boojin Kimb7d861d2011-12-26 18:49:52 +09001887 void __iomem *regs;
1888 int i, ret;
1889
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001890 regs = pl330->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001891
1892 /* Check if we can handle this DMAC */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001893 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1894 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1895 pl330->pcfg.periph_id);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001896 return -EINVAL;
1897 }
1898
1899 /* Read the configuration of the DMAC */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001900 read_dmac_config(pl330);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001901
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001902 if (pl330->pcfg.num_events == 0) {
1903 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
Boojin Kimb7d861d2011-12-26 18:49:52 +09001904 __func__, __LINE__);
1905 return -EINVAL;
1906 }
1907
Boojin Kimb7d861d2011-12-26 18:49:52 +09001908 spin_lock_init(&pl330->lock);
1909
1910 INIT_LIST_HEAD(&pl330->req_done);
1911
1912 /* Use default MC buffer size if not provided */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001913 if (!pl330->mcbufsz)
1914 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001915
1916 /* Mark all events as free */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001917 for (i = 0; i < pl330->pcfg.num_events; i++)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001918 pl330->events[i] = -1;
1919
1920 /* Allocate resources needed by the DMAC */
1921 ret = dmac_alloc_resources(pl330);
1922 if (ret) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001923 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
Boojin Kimb7d861d2011-12-26 18:49:52 +09001924 return ret;
1925 }
1926
1927 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
1928
1929 pl330->state = INIT;
1930
1931 return 0;
1932}
1933
1934static int dmac_free_threads(struct pl330_dmac *pl330)
1935{
Boojin Kimb7d861d2011-12-26 18:49:52 +09001936 struct pl330_thread *thrd;
1937 int i;
1938
1939 /* Release Channel threads */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001940 for (i = 0; i < pl330->pcfg.num_chan; i++) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001941 thrd = &pl330->channels[i];
Lars-Peter Clausen65ad6062014-07-06 20:32:26 +02001942 pl330_release_channel(thrd);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001943 }
1944
1945 /* Free memory */
1946 kfree(pl330->channels);
1947
1948 return 0;
1949}
1950
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001951static void pl330_del(struct pl330_dmac *pl330)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001952{
Boojin Kimb7d861d2011-12-26 18:49:52 +09001953 pl330->state = UNINIT;
1954
1955 tasklet_kill(&pl330->tasks);
1956
1957 /* Free DMAC resources */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001958 dmac_free_threads(pl330);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001959
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001960 dma_free_coherent(pl330->ddma.dev,
1961 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
1962 pl330->mcode_bus);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001963}
1964
Thomas Abraham3e2ec132011-10-24 11:43:02 +02001965/* forward declaration */
1966static struct amba_driver pl330_driver;
1967
Jassi Brarb3040e42010-05-23 20:28:19 -07001968static inline struct dma_pl330_chan *
1969to_pchan(struct dma_chan *ch)
1970{
1971 if (!ch)
1972 return NULL;
1973
1974 return container_of(ch, struct dma_pl330_chan, chan);
1975}
1976
1977static inline struct dma_pl330_desc *
1978to_desc(struct dma_async_tx_descriptor *tx)
1979{
1980 return container_of(tx, struct dma_pl330_desc, txd);
1981}
1982
Jassi Brarb3040e42010-05-23 20:28:19 -07001983static inline void fill_queue(struct dma_pl330_chan *pch)
1984{
1985 struct dma_pl330_desc *desc;
1986 int ret;
1987
1988 list_for_each_entry(desc, &pch->work_list, node) {
1989
1990 /* If already submitted */
1991 if (desc->status == BUSY)
Jassi Brar30fb9802013-02-13 16:13:14 +05301992 continue;
Jassi Brarb3040e42010-05-23 20:28:19 -07001993
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001994 ret = pl330_submit_req(pch->thread, desc);
Jassi Brarb3040e42010-05-23 20:28:19 -07001995 if (!ret) {
1996 desc->status = BUSY;
Jassi Brarb3040e42010-05-23 20:28:19 -07001997 } else if (ret == -EAGAIN) {
1998 /* QFull or DMAC Dying */
1999 break;
2000 } else {
2001 /* Unacceptable request */
2002 desc->status = DONE;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002003 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
Jassi Brarb3040e42010-05-23 20:28:19 -07002004 __func__, __LINE__, desc->txd.cookie);
2005 tasklet_schedule(&pch->task);
2006 }
2007 }
2008}
2009
2010static void pl330_tasklet(unsigned long data)
2011{
2012 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
2013 struct dma_pl330_desc *desc, *_dt;
2014 unsigned long flags;
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002015 bool power_down = false;
Jassi Brarb3040e42010-05-23 20:28:19 -07002016
2017 spin_lock_irqsave(&pch->lock, flags);
2018
2019 /* Pick up ripe tomatoes */
2020 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2021 if (desc->status == DONE) {
Tushar Behera30c1dc02012-05-23 16:47:31 +05302022 if (!pch->cyclic)
Vinod Kouleab21582012-05-11 11:24:41 +05302023 dma_cookie_complete(&desc->txd);
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002024 list_move_tail(&desc->node, &pch->completed_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002025 }
2026
2027 /* Try to submit a req imm. next to the last completed cookie */
2028 fill_queue(pch);
2029
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002030 if (list_empty(&pch->work_list)) {
2031 spin_lock(&pch->thread->dmac->lock);
2032 _stop(pch->thread);
2033 spin_unlock(&pch->thread->dmac->lock);
2034 power_down = true;
2035 } else {
2036 /* Make sure the PL330 Channel thread is active */
2037 spin_lock(&pch->thread->dmac->lock);
2038 _start(pch->thread);
2039 spin_unlock(&pch->thread->dmac->lock);
2040 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002041
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002042 while (!list_empty(&pch->completed_list)) {
2043 dma_async_tx_callback callback;
2044 void *callback_param;
Jassi Brarb3040e42010-05-23 20:28:19 -07002045
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002046 desc = list_first_entry(&pch->completed_list,
2047 struct dma_pl330_desc, node);
2048
2049 callback = desc->txd.callback;
2050 callback_param = desc->txd.callback_param;
2051
2052 if (pch->cyclic) {
2053 desc->status = PREP;
2054 list_move_tail(&desc->node, &pch->work_list);
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002055 if (power_down) {
2056 spin_lock(&pch->thread->dmac->lock);
2057 _start(pch->thread);
2058 spin_unlock(&pch->thread->dmac->lock);
2059 power_down = false;
2060 }
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002061 } else {
2062 desc->status = FREE;
2063 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2064 }
2065
Dan Williamsd38a8c62013-10-18 19:35:23 +02002066 dma_descriptor_unmap(&desc->txd);
2067
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002068 if (callback) {
2069 spin_unlock_irqrestore(&pch->lock, flags);
2070 callback(callback_param);
2071 spin_lock_irqsave(&pch->lock, flags);
2072 }
2073 }
2074 spin_unlock_irqrestore(&pch->lock, flags);
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002075
2076 /* If work list empty, power down */
2077 if (power_down) {
2078 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2079 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2080 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002081}
2082
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002083bool pl330_filter(struct dma_chan *chan, void *param)
2084{
Thomas Abrahamcd072512011-10-24 11:43:11 +02002085 u8 *peri_id;
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002086
2087 if (chan->device->dev->driver != &pl330_driver.drv)
2088 return false;
2089
Thomas Abrahamcd072512011-10-24 11:43:11 +02002090 peri_id = chan->private;
Dan Carpenter2f986ec2013-11-08 12:51:16 +03002091 return *peri_id == (unsigned long)param;
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002092}
2093EXPORT_SYMBOL(pl330_filter);
2094
Padmavathi Vennaa80258f2013-02-14 09:10:06 +05302095static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2096 struct of_dma *ofdma)
2097{
2098 int count = dma_spec->args_count;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002099 struct pl330_dmac *pl330 = ofdma->of_dma_data;
Lars-Peter Clausen70cbb162014-01-11 20:08:39 +01002100 unsigned int chan_id;
Padmavathi Vennaa80258f2013-02-14 09:10:06 +05302101
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002102 if (!pl330)
2103 return NULL;
2104
Padmavathi Vennaa80258f2013-02-14 09:10:06 +05302105 if (count != 1)
2106 return NULL;
2107
Lars-Peter Clausen70cbb162014-01-11 20:08:39 +01002108 chan_id = dma_spec->args[0];
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002109 if (chan_id >= pl330->num_peripherals)
Lars-Peter Clausen70cbb162014-01-11 20:08:39 +01002110 return NULL;
Padmavathi Vennaa80258f2013-02-14 09:10:06 +05302111
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002112 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
Padmavathi Vennaa80258f2013-02-14 09:10:06 +05302113}
2114
Jassi Brarb3040e42010-05-23 20:28:19 -07002115static int pl330_alloc_chan_resources(struct dma_chan *chan)
2116{
2117 struct dma_pl330_chan *pch = to_pchan(chan);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002118 struct pl330_dmac *pl330 = pch->dmac;
Jassi Brarb3040e42010-05-23 20:28:19 -07002119 unsigned long flags;
2120
2121 spin_lock_irqsave(&pch->lock, flags);
2122
Russell King - ARM Linuxd3ee98cdc2012-03-06 22:35:47 +00002123 dma_cookie_init(chan);
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002124 pch->cyclic = false;
Jassi Brarb3040e42010-05-23 20:28:19 -07002125
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002126 pch->thread = pl330_request_channel(pl330);
Lars-Peter Clausen65ad6062014-07-06 20:32:26 +02002127 if (!pch->thread) {
Jassi Brarb3040e42010-05-23 20:28:19 -07002128 spin_unlock_irqrestore(&pch->lock, flags);
Inderpal Singh02747882012-09-17 09:57:45 +05302129 return -ENOMEM;
Jassi Brarb3040e42010-05-23 20:28:19 -07002130 }
2131
2132 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2133
2134 spin_unlock_irqrestore(&pch->lock, flags);
2135
2136 return 1;
2137}
2138
Maxime Ripard740aa952014-11-17 14:42:29 +01002139static int pl330_config(struct dma_chan *chan,
2140 struct dma_slave_config *slave_config)
2141{
2142 struct dma_pl330_chan *pch = to_pchan(chan);
2143
2144 if (slave_config->direction == DMA_MEM_TO_DEV) {
2145 if (slave_config->dst_addr)
2146 pch->fifo_addr = slave_config->dst_addr;
2147 if (slave_config->dst_addr_width)
2148 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2149 if (slave_config->dst_maxburst)
2150 pch->burst_len = slave_config->dst_maxburst;
2151 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
2152 if (slave_config->src_addr)
2153 pch->fifo_addr = slave_config->src_addr;
2154 if (slave_config->src_addr_width)
2155 pch->burst_sz = __ffs(slave_config->src_addr_width);
2156 if (slave_config->src_maxburst)
2157 pch->burst_len = slave_config->src_maxburst;
2158 }
2159
2160 return 0;
2161}
2162
2163static int pl330_terminate_all(struct dma_chan *chan)
Jassi Brarb3040e42010-05-23 20:28:19 -07002164{
2165 struct dma_pl330_chan *pch = to_pchan(chan);
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002166 struct dma_pl330_desc *desc;
Jassi Brarb3040e42010-05-23 20:28:19 -07002167 unsigned long flags;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002168 struct pl330_dmac *pl330 = pch->dmac;
Boojin Kimae43b882011-09-02 09:44:32 +09002169 LIST_HEAD(list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002170
Krzysztof Kozlowski81cc6ed2015-05-21 09:34:09 +09002171 pm_runtime_get_sync(pl330->ddma.dev);
Maxime Ripard740aa952014-11-17 14:42:29 +01002172 spin_lock_irqsave(&pch->lock, flags);
2173 spin_lock(&pl330->lock);
2174 _stop(pch->thread);
2175 spin_unlock(&pl330->lock);
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002176
Maxime Ripard740aa952014-11-17 14:42:29 +01002177 pch->thread->req[0].desc = NULL;
2178 pch->thread->req[1].desc = NULL;
2179 pch->thread->req_running = -1;
Lars-Peter Clausenc26939e2014-07-06 20:32:32 +02002180
Maxime Ripard740aa952014-11-17 14:42:29 +01002181 /* Mark all desc done */
2182 list_for_each_entry(desc, &pch->submitted_list, node) {
2183 desc->status = FREE;
2184 dma_cookie_complete(&desc->txd);
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002185 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002186
Maxime Ripard740aa952014-11-17 14:42:29 +01002187 list_for_each_entry(desc, &pch->work_list , node) {
2188 desc->status = FREE;
2189 dma_cookie_complete(&desc->txd);
2190 }
2191
2192 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2193 list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2194 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2195 spin_unlock_irqrestore(&pch->lock, flags);
Krzysztof Kozlowski81cc6ed2015-05-21 09:34:09 +09002196 pm_runtime_mark_last_busy(pl330->ddma.dev);
2197 pm_runtime_put_autosuspend(pl330->ddma.dev);
Maxime Ripard740aa952014-11-17 14:42:29 +01002198
Jassi Brarb3040e42010-05-23 20:28:19 -07002199 return 0;
2200}
2201
Robert Baldyga88987d22015-02-11 13:23:18 +01002202/*
2203 * We don't support DMA_RESUME command because of hardware
2204 * limitations, so after pausing the channel we cannot restore
2205 * it to active state. We have to terminate channel and setup
2206 * DMA transfer again. This pause feature was implemented to
2207 * allow safely read residue before channel termination.
2208 */
Ben Dooks5503aed2015-03-16 11:52:44 +00002209static int pl330_pause(struct dma_chan *chan)
Robert Baldyga88987d22015-02-11 13:23:18 +01002210{
2211 struct dma_pl330_chan *pch = to_pchan(chan);
2212 struct pl330_dmac *pl330 = pch->dmac;
2213 unsigned long flags;
2214
2215 pm_runtime_get_sync(pl330->ddma.dev);
2216 spin_lock_irqsave(&pch->lock, flags);
2217
2218 spin_lock(&pl330->lock);
2219 _stop(pch->thread);
2220 spin_unlock(&pl330->lock);
2221
2222 spin_unlock_irqrestore(&pch->lock, flags);
2223 pm_runtime_mark_last_busy(pl330->ddma.dev);
2224 pm_runtime_put_autosuspend(pl330->ddma.dev);
2225
2226 return 0;
2227}
2228
Jassi Brarb3040e42010-05-23 20:28:19 -07002229static void pl330_free_chan_resources(struct dma_chan *chan)
2230{
2231 struct dma_pl330_chan *pch = to_pchan(chan);
2232 unsigned long flags;
2233
Jassi Brarb3040e42010-05-23 20:28:19 -07002234 tasklet_kill(&pch->task);
2235
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002236 pm_runtime_get_sync(pch->dmac->ddma.dev);
Bartlomiej Zolnierkiewiczda331ba2013-07-03 15:00:43 -07002237 spin_lock_irqsave(&pch->lock, flags);
2238
Lars-Peter Clausen65ad6062014-07-06 20:32:26 +02002239 pl330_release_channel(pch->thread);
2240 pch->thread = NULL;
Jassi Brarb3040e42010-05-23 20:28:19 -07002241
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002242 if (pch->cyclic)
2243 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2244
Jassi Brarb3040e42010-05-23 20:28:19 -07002245 spin_unlock_irqrestore(&pch->lock, flags);
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002246 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2247 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
Jassi Brarb3040e42010-05-23 20:28:19 -07002248}
2249
Ben Dooks5503aed2015-03-16 11:52:44 +00002250static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2251 struct dma_pl330_desc *desc)
Robert Baldygaaee4d1f2015-02-11 13:23:17 +01002252{
2253 struct pl330_thread *thrd = pch->thread;
2254 struct pl330_dmac *pl330 = pch->dmac;
2255 void __iomem *regs = thrd->dmac->base;
2256 u32 val, addr;
2257
2258 pm_runtime_get_sync(pl330->ddma.dev);
2259 val = addr = 0;
2260 if (desc->rqcfg.src_inc) {
2261 val = readl(regs + SA(thrd->id));
2262 addr = desc->px.src_addr;
2263 } else {
2264 val = readl(regs + DA(thrd->id));
2265 addr = desc->px.dst_addr;
2266 }
2267 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2268 pm_runtime_put_autosuspend(pl330->ddma.dev);
2269 return val - addr;
2270}
2271
Jassi Brarb3040e42010-05-23 20:28:19 -07002272static enum dma_status
2273pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2274 struct dma_tx_state *txstate)
2275{
Robert Baldygaaee4d1f2015-02-11 13:23:17 +01002276 enum dma_status ret;
2277 unsigned long flags;
2278 struct dma_pl330_desc *desc, *running = NULL;
2279 struct dma_pl330_chan *pch = to_pchan(chan);
2280 unsigned int transferred, residual = 0;
2281
2282 ret = dma_cookie_status(chan, cookie, txstate);
2283
2284 if (!txstate)
2285 return ret;
2286
2287 if (ret == DMA_COMPLETE)
2288 goto out;
2289
2290 spin_lock_irqsave(&pch->lock, flags);
2291
2292 if (pch->thread->req_running != -1)
2293 running = pch->thread->req[pch->thread->req_running].desc;
2294
2295 /* Check in pending list */
2296 list_for_each_entry(desc, &pch->work_list, node) {
2297 if (desc->status == DONE)
2298 transferred = desc->bytes_requested;
2299 else if (running && desc == running)
2300 transferred =
2301 pl330_get_current_xferred_count(pch, desc);
2302 else
2303 transferred = 0;
2304 residual += desc->bytes_requested - transferred;
2305 if (desc->txd.cookie == cookie) {
Ben Dooks75967b72015-03-16 11:52:45 +00002306 switch (desc->status) {
2307 case DONE:
2308 ret = DMA_COMPLETE;
2309 break;
2310 case PREP:
2311 case BUSY:
2312 ret = DMA_IN_PROGRESS;
2313 break;
2314 default:
2315 WARN_ON(1);
2316 }
Robert Baldygaaee4d1f2015-02-11 13:23:17 +01002317 break;
2318 }
2319 if (desc->last)
2320 residual = 0;
2321 }
2322 spin_unlock_irqrestore(&pch->lock, flags);
2323
2324out:
2325 dma_set_residue(txstate, residual);
2326
2327 return ret;
Jassi Brarb3040e42010-05-23 20:28:19 -07002328}
2329
2330static void pl330_issue_pending(struct dma_chan *chan)
2331{
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002332 struct dma_pl330_chan *pch = to_pchan(chan);
2333 unsigned long flags;
2334
2335 spin_lock_irqsave(&pch->lock, flags);
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002336 if (list_empty(&pch->work_list)) {
2337 /*
2338 * Warn on nothing pending. Empty submitted_list may
2339 * break our pm_runtime usage counter as it is
2340 * updated on work_list emptiness status.
2341 */
2342 WARN_ON(list_empty(&pch->submitted_list));
2343 pm_runtime_get_sync(pch->dmac->ddma.dev);
2344 }
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002345 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2346 spin_unlock_irqrestore(&pch->lock, flags);
2347
2348 pl330_tasklet((unsigned long)pch);
Jassi Brarb3040e42010-05-23 20:28:19 -07002349}
2350
2351/*
2352 * We returned the last one of the circular list of descriptor(s)
2353 * from prep_xxx, so the argument to submit corresponds to the last
2354 * descriptor of the list.
2355 */
2356static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2357{
2358 struct dma_pl330_desc *desc, *last = to_desc(tx);
2359 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2360 dma_cookie_t cookie;
2361 unsigned long flags;
2362
2363 spin_lock_irqsave(&pch->lock, flags);
2364
2365 /* Assign cookies to all nodes */
Jassi Brarb3040e42010-05-23 20:28:19 -07002366 while (!list_empty(&last->node)) {
2367 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002368 if (pch->cyclic) {
2369 desc->txd.callback = last->txd.callback;
2370 desc->txd.callback_param = last->txd.callback_param;
2371 }
Krzysztof Kozlowski5dd90e52015-06-15 23:00:09 +09002372 desc->last = false;
Jassi Brarb3040e42010-05-23 20:28:19 -07002373
Russell King - ARM Linux884485e2012-03-06 22:34:46 +00002374 dma_cookie_assign(&desc->txd);
Jassi Brarb3040e42010-05-23 20:28:19 -07002375
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002376 list_move_tail(&desc->node, &pch->submitted_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002377 }
2378
Robert Baldygaaee4d1f2015-02-11 13:23:17 +01002379 last->last = true;
Russell King - ARM Linux884485e2012-03-06 22:34:46 +00002380 cookie = dma_cookie_assign(&last->txd);
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002381 list_add_tail(&last->node, &pch->submitted_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002382 spin_unlock_irqrestore(&pch->lock, flags);
2383
2384 return cookie;
2385}
2386
2387static inline void _init_desc(struct dma_pl330_desc *desc)
2388{
Jassi Brarb3040e42010-05-23 20:28:19 -07002389 desc->rqcfg.swap = SWAP_NO;
Lars-Peter Clausenf0564c72014-07-06 20:32:19 +02002390 desc->rqcfg.scctl = CCTRL0;
2391 desc->rqcfg.dcctl = CCTRL0;
Jassi Brarb3040e42010-05-23 20:28:19 -07002392 desc->txd.tx_submit = pl330_tx_submit;
2393
2394 INIT_LIST_HEAD(&desc->node);
2395}
2396
2397/* Returns the number of descriptors added to the DMAC pool */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002398static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count)
Jassi Brarb3040e42010-05-23 20:28:19 -07002399{
2400 struct dma_pl330_desc *desc;
2401 unsigned long flags;
2402 int i;
2403
Will Deacon0baf8f62013-12-02 18:01:30 +00002404 desc = kcalloc(count, sizeof(*desc), flg);
Jassi Brarb3040e42010-05-23 20:28:19 -07002405 if (!desc)
2406 return 0;
2407
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002408 spin_lock_irqsave(&pl330->pool_lock, flags);
Jassi Brarb3040e42010-05-23 20:28:19 -07002409
2410 for (i = 0; i < count; i++) {
2411 _init_desc(&desc[i]);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002412 list_add_tail(&desc[i].node, &pl330->desc_pool);
Jassi Brarb3040e42010-05-23 20:28:19 -07002413 }
2414
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002415 spin_unlock_irqrestore(&pl330->pool_lock, flags);
Jassi Brarb3040e42010-05-23 20:28:19 -07002416
2417 return count;
2418}
2419
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002420static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330)
Jassi Brarb3040e42010-05-23 20:28:19 -07002421{
2422 struct dma_pl330_desc *desc = NULL;
2423 unsigned long flags;
2424
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002425 spin_lock_irqsave(&pl330->pool_lock, flags);
Jassi Brarb3040e42010-05-23 20:28:19 -07002426
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002427 if (!list_empty(&pl330->desc_pool)) {
2428 desc = list_entry(pl330->desc_pool.next,
Jassi Brarb3040e42010-05-23 20:28:19 -07002429 struct dma_pl330_desc, node);
2430
2431 list_del_init(&desc->node);
2432
2433 desc->status = PREP;
2434 desc->txd.callback = NULL;
2435 }
2436
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002437 spin_unlock_irqrestore(&pl330->pool_lock, flags);
Jassi Brarb3040e42010-05-23 20:28:19 -07002438
2439 return desc;
2440}
2441
2442static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2443{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002444 struct pl330_dmac *pl330 = pch->dmac;
Thomas Abrahamcd072512011-10-24 11:43:11 +02002445 u8 *peri_id = pch->chan.private;
Jassi Brarb3040e42010-05-23 20:28:19 -07002446 struct dma_pl330_desc *desc;
2447
2448 /* Pluck one desc from the pool of DMAC */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002449 desc = pluck_desc(pl330);
Jassi Brarb3040e42010-05-23 20:28:19 -07002450
2451 /* If the DMAC pool is empty, alloc new */
2452 if (!desc) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002453 if (!add_desc(pl330, GFP_ATOMIC, 1))
Jassi Brarb3040e42010-05-23 20:28:19 -07002454 return NULL;
2455
2456 /* Try again */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002457 desc = pluck_desc(pl330);
Jassi Brarb3040e42010-05-23 20:28:19 -07002458 if (!desc) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002459 dev_err(pch->dmac->ddma.dev,
Jassi Brarb3040e42010-05-23 20:28:19 -07002460 "%s:%d ALERT!\n", __func__, __LINE__);
2461 return NULL;
2462 }
2463 }
2464
2465 /* Initialize the descriptor */
2466 desc->pchan = pch;
2467 desc->txd.cookie = 0;
2468 async_tx_ack(&desc->txd);
2469
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02002470 desc->peri = peri_id ? pch->chan.chan_id : 0;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002471 desc->rqcfg.pcfg = &pch->dmac->pcfg;
Jassi Brarb3040e42010-05-23 20:28:19 -07002472
2473 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2474
2475 return desc;
2476}
2477
2478static inline void fill_px(struct pl330_xfer *px,
2479 dma_addr_t dst, dma_addr_t src, size_t len)
2480{
Jassi Brarb3040e42010-05-23 20:28:19 -07002481 px->bytes = len;
2482 px->dst_addr = dst;
2483 px->src_addr = src;
2484}
2485
2486static struct dma_pl330_desc *
2487__pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2488 dma_addr_t src, size_t len)
2489{
2490 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2491
2492 if (!desc) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002493 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
Jassi Brarb3040e42010-05-23 20:28:19 -07002494 __func__, __LINE__);
2495 return NULL;
2496 }
2497
2498 /*
2499 * Ideally we should lookout for reqs bigger than
2500 * those that can be programmed with 256 bytes of
2501 * MC buffer, but considering a req size is seldom
2502 * going to be word-unaligned and more than 200MB,
2503 * we take it easy.
2504 * Also, should the limit is reached we'd rather
2505 * have the platform increase MC buffer size than
2506 * complicating this API driver.
2507 */
2508 fill_px(&desc->px, dst, src, len);
2509
2510 return desc;
2511}
2512
2513/* Call after fixing burst size */
2514static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2515{
2516 struct dma_pl330_chan *pch = desc->pchan;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002517 struct pl330_dmac *pl330 = pch->dmac;
Jassi Brarb3040e42010-05-23 20:28:19 -07002518 int burst_len;
2519
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002520 burst_len = pl330->pcfg.data_bus_width / 8;
Jon Medhurstc27f9552014-11-07 18:05:18 +00002521 burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
Jassi Brarb3040e42010-05-23 20:28:19 -07002522 burst_len >>= desc->rqcfg.brst_size;
2523
2524 /* src/dst_burst_len can't be more than 16 */
2525 if (burst_len > 16)
2526 burst_len = 16;
2527
2528 while (burst_len > 1) {
2529 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2530 break;
2531 burst_len--;
2532 }
2533
2534 return burst_len;
2535}
2536
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002537static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2538 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -05002539 size_t period_len, enum dma_transfer_direction direction,
Laurent Pinchart31c1e5a2014-08-01 12:20:10 +02002540 unsigned long flags)
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002541{
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002542 struct dma_pl330_desc *desc = NULL, *first = NULL;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002543 struct dma_pl330_chan *pch = to_pchan(chan);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002544 struct pl330_dmac *pl330 = pch->dmac;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002545 unsigned int i;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002546 dma_addr_t dst;
2547 dma_addr_t src;
2548
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002549 if (len % period_len != 0)
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002550 return NULL;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002551
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002552 if (!is_slave_direction(direction)) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002553 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002554 __func__, __LINE__);
2555 return NULL;
2556 }
2557
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002558 for (i = 0; i < len / period_len; i++) {
2559 desc = pl330_get_desc(pch);
2560 if (!desc) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002561 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002562 __func__, __LINE__);
2563
2564 if (!first)
2565 return NULL;
2566
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002567 spin_lock_irqsave(&pl330->pool_lock, flags);
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002568
2569 while (!list_empty(&first->node)) {
2570 desc = list_entry(first->node.next,
2571 struct dma_pl330_desc, node);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002572 list_move_tail(&desc->node, &pl330->desc_pool);
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002573 }
2574
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002575 list_move_tail(&first->node, &pl330->desc_pool);
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002576
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002577 spin_unlock_irqrestore(&pl330->pool_lock, flags);
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002578
2579 return NULL;
2580 }
2581
2582 switch (direction) {
2583 case DMA_MEM_TO_DEV:
2584 desc->rqcfg.src_inc = 1;
2585 desc->rqcfg.dst_inc = 0;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002586 src = dma_addr;
2587 dst = pch->fifo_addr;
2588 break;
2589 case DMA_DEV_TO_MEM:
2590 desc->rqcfg.src_inc = 0;
2591 desc->rqcfg.dst_inc = 1;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002592 src = pch->fifo_addr;
2593 dst = dma_addr;
2594 break;
2595 default:
2596 break;
2597 }
2598
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02002599 desc->rqtype = direction;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002600 desc->rqcfg.brst_size = pch->burst_sz;
Boojin Kim848e9772016-01-22 19:06:44 +08002601 desc->rqcfg.brst_len = pch->burst_len;
Robert Baldygaaee4d1f2015-02-11 13:23:17 +01002602 desc->bytes_requested = period_len;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002603 fill_px(&desc->px, dst, src, period_len);
2604
2605 if (!first)
2606 first = desc;
2607 else
2608 list_add_tail(&desc->node, &first->node);
2609
2610 dma_addr += period_len;
2611 }
2612
2613 if (!desc)
2614 return NULL;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002615
2616 pch->cyclic = true;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002617 desc->txd.flags = flags;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002618
2619 return &desc->txd;
2620}
2621
Jassi Brarb3040e42010-05-23 20:28:19 -07002622static struct dma_async_tx_descriptor *
2623pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2624 dma_addr_t src, size_t len, unsigned long flags)
2625{
2626 struct dma_pl330_desc *desc;
2627 struct dma_pl330_chan *pch = to_pchan(chan);
Maninder Singhf5636852015-05-26 00:40:05 +05302628 struct pl330_dmac *pl330;
Jassi Brarb3040e42010-05-23 20:28:19 -07002629 int burst;
2630
Rob Herring4e0e6102011-07-25 16:05:04 -05002631 if (unlikely(!pch || !len))
Jassi Brarb3040e42010-05-23 20:28:19 -07002632 return NULL;
2633
Maninder Singhf5636852015-05-26 00:40:05 +05302634 pl330 = pch->dmac;
2635
Jassi Brarb3040e42010-05-23 20:28:19 -07002636 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2637 if (!desc)
2638 return NULL;
2639
2640 desc->rqcfg.src_inc = 1;
2641 desc->rqcfg.dst_inc = 1;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02002642 desc->rqtype = DMA_MEM_TO_MEM;
Jassi Brarb3040e42010-05-23 20:28:19 -07002643
2644 /* Select max possible burst size */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002645 burst = pl330->pcfg.data_bus_width / 8;
Jassi Brarb3040e42010-05-23 20:28:19 -07002646
Jon Medhurst137bd112014-11-07 18:05:17 +00002647 /*
2648 * Make sure we use a burst size that aligns with all the memcpy
2649 * parameters because our DMA programming algorithm doesn't cope with
2650 * transfers which straddle an entry in the DMA device's MFIFO.
2651 */
2652 while ((src | dst | len) & (burst - 1))
Jassi Brarb3040e42010-05-23 20:28:19 -07002653 burst /= 2;
Jassi Brarb3040e42010-05-23 20:28:19 -07002654
2655 desc->rqcfg.brst_size = 0;
2656 while (burst != (1 << desc->rqcfg.brst_size))
2657 desc->rqcfg.brst_size++;
2658
Jon Medhurst137bd112014-11-07 18:05:17 +00002659 /*
2660 * If burst size is smaller than bus width then make sure we only
2661 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2662 */
2663 if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
2664 desc->rqcfg.brst_len = 1;
2665
Jassi Brarb3040e42010-05-23 20:28:19 -07002666 desc->rqcfg.brst_len = get_burst_len(desc, len);
Krzysztof Kozlowskiae128292015-06-15 17:25:16 +09002667 desc->bytes_requested = len;
Jassi Brarb3040e42010-05-23 20:28:19 -07002668
2669 desc->txd.flags = flags;
2670
2671 return &desc->txd;
2672}
2673
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002674static void __pl330_giveback_desc(struct pl330_dmac *pl330,
Chanho Park52a9d172013-08-09 20:11:33 +09002675 struct dma_pl330_desc *first)
2676{
2677 unsigned long flags;
2678 struct dma_pl330_desc *desc;
2679
2680 if (!first)
2681 return;
2682
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002683 spin_lock_irqsave(&pl330->pool_lock, flags);
Chanho Park52a9d172013-08-09 20:11:33 +09002684
2685 while (!list_empty(&first->node)) {
2686 desc = list_entry(first->node.next,
2687 struct dma_pl330_desc, node);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002688 list_move_tail(&desc->node, &pl330->desc_pool);
Chanho Park52a9d172013-08-09 20:11:33 +09002689 }
2690
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002691 list_move_tail(&first->node, &pl330->desc_pool);
Chanho Park52a9d172013-08-09 20:11:33 +09002692
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002693 spin_unlock_irqrestore(&pl330->pool_lock, flags);
Chanho Park52a9d172013-08-09 20:11:33 +09002694}
2695
Jassi Brarb3040e42010-05-23 20:28:19 -07002696static struct dma_async_tx_descriptor *
2697pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +05302698 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -05002699 unsigned long flg, void *context)
Jassi Brarb3040e42010-05-23 20:28:19 -07002700{
2701 struct dma_pl330_desc *first, *desc = NULL;
2702 struct dma_pl330_chan *pch = to_pchan(chan);
Jassi Brarb3040e42010-05-23 20:28:19 -07002703 struct scatterlist *sg;
Boojin Kim1b9bb712011-09-02 09:44:30 +09002704 int i;
Jassi Brarb3040e42010-05-23 20:28:19 -07002705 dma_addr_t addr;
2706
Thomas Abrahamcd072512011-10-24 11:43:11 +02002707 if (unlikely(!pch || !sgl || !sg_len))
Jassi Brarb3040e42010-05-23 20:28:19 -07002708 return NULL;
2709
Boojin Kim1b9bb712011-09-02 09:44:30 +09002710 addr = pch->fifo_addr;
Jassi Brarb3040e42010-05-23 20:28:19 -07002711
2712 first = NULL;
2713
2714 for_each_sg(sgl, sg, sg_len, i) {
2715
2716 desc = pl330_get_desc(pch);
2717 if (!desc) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002718 struct pl330_dmac *pl330 = pch->dmac;
Jassi Brarb3040e42010-05-23 20:28:19 -07002719
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002720 dev_err(pch->dmac->ddma.dev,
Jassi Brarb3040e42010-05-23 20:28:19 -07002721 "%s:%d Unable to fetch desc\n",
2722 __func__, __LINE__);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002723 __pl330_giveback_desc(pl330, first);
Jassi Brarb3040e42010-05-23 20:28:19 -07002724
2725 return NULL;
2726 }
2727
2728 if (!first)
2729 first = desc;
2730 else
2731 list_add_tail(&desc->node, &first->node);
2732
Vinod Kouldb8196d2011-10-13 22:34:23 +05302733 if (direction == DMA_MEM_TO_DEV) {
Jassi Brarb3040e42010-05-23 20:28:19 -07002734 desc->rqcfg.src_inc = 1;
2735 desc->rqcfg.dst_inc = 0;
2736 fill_px(&desc->px,
2737 addr, sg_dma_address(sg), sg_dma_len(sg));
2738 } else {
2739 desc->rqcfg.src_inc = 0;
2740 desc->rqcfg.dst_inc = 1;
2741 fill_px(&desc->px,
2742 sg_dma_address(sg), addr, sg_dma_len(sg));
2743 }
2744
Boojin Kim1b9bb712011-09-02 09:44:30 +09002745 desc->rqcfg.brst_size = pch->burst_sz;
Boojin Kim848e9772016-01-22 19:06:44 +08002746 desc->rqcfg.brst_len = pch->burst_len;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02002747 desc->rqtype = direction;
Robert Baldygaaee4d1f2015-02-11 13:23:17 +01002748 desc->bytes_requested = sg_dma_len(sg);
Jassi Brarb3040e42010-05-23 20:28:19 -07002749 }
2750
2751 /* Return the last desc in the chain */
2752 desc->txd.flags = flg;
2753 return &desc->txd;
2754}
2755
2756static irqreturn_t pl330_irq_handler(int irq, void *data)
2757{
2758 if (pl330_update(data))
2759 return IRQ_HANDLED;
2760 else
2761 return IRQ_NONE;
2762}
2763
Lars-Peter Clausenca38ff12013-07-15 17:53:08 +02002764#define PL330_DMA_BUSWIDTHS \
2765 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2766 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2767 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2768 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2769 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2770
Krzysztof Kozlowskib816ccc2014-11-18 12:17:56 +01002771/*
2772 * Runtime PM callbacks are provided by amba/bus.c driver.
2773 *
2774 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2775 * bus driver will only disable/enable the clock in runtime PM callbacks.
2776 */
2777static int __maybe_unused pl330_suspend(struct device *dev)
2778{
2779 struct amba_device *pcdev = to_amba_device(dev);
2780
2781 pm_runtime_disable(dev);
2782
2783 if (!pm_runtime_status_suspended(dev)) {
2784 /* amba did not disable the clock */
2785 amba_pclk_disable(pcdev);
2786 }
2787 amba_pclk_unprepare(pcdev);
2788
2789 return 0;
2790}
2791
2792static int __maybe_unused pl330_resume(struct device *dev)
2793{
2794 struct amba_device *pcdev = to_amba_device(dev);
2795 int ret;
2796
2797 ret = amba_pclk_prepare(pcdev);
2798 if (ret)
2799 return ret;
2800
2801 if (!pm_runtime_status_suspended(dev))
2802 ret = amba_pclk_enable(pcdev);
2803
2804 pm_runtime_enable(dev);
2805
2806 return ret;
2807}
2808
2809static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume);
2810
Bill Pemberton463a1f82012-11-19 13:22:55 -05002811static int
Russell Kingaa25afa2011-02-19 15:55:00 +00002812pl330_probe(struct amba_device *adev, const struct amba_id *id)
Jassi Brarb3040e42010-05-23 20:28:19 -07002813{
2814 struct dma_pl330_platdata *pdat;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002815 struct pl330_config *pcfg;
2816 struct pl330_dmac *pl330;
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302817 struct dma_pl330_chan *pch, *_p;
Jassi Brarb3040e42010-05-23 20:28:19 -07002818 struct dma_device *pd;
2819 struct resource *res;
2820 int i, ret, irq;
Rob Herring4e0e6102011-07-25 16:05:04 -05002821 int num_chan;
Addy Ke271e1b862016-01-22 19:06:46 +08002822 struct device_node *np = adev->dev.of_node;
Jassi Brarb3040e42010-05-23 20:28:19 -07002823
Jingoo Hand4adcc02013-07-30 17:09:11 +09002824 pdat = dev_get_platdata(&adev->dev);
Jassi Brarb3040e42010-05-23 20:28:19 -07002825
Russell King64113012013-06-27 10:29:32 +01002826 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
2827 if (ret)
2828 return ret;
2829
Jassi Brarb3040e42010-05-23 20:28:19 -07002830 /* Allocate a new DMAC and its Channels */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002831 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
2832 if (!pl330) {
Jassi Brarb3040e42010-05-23 20:28:19 -07002833 dev_err(&adev->dev, "unable to allocate mem\n");
2834 return -ENOMEM;
2835 }
2836
Andrew Jacksoncee42392014-11-06 11:39:47 +00002837 pd = &pl330->ddma;
2838 pd->dev = &adev->dev;
2839
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002840 pl330->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
Jassi Brarb3040e42010-05-23 20:28:19 -07002841
Addy Ke271e1b862016-01-22 19:06:46 +08002842 /* get quirk */
2843 for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
2844 if (of_property_read_bool(np, of_quirks[i].quirk))
2845 pl330->quirks |= of_quirks[i].id;
2846
Jassi Brarb3040e42010-05-23 20:28:19 -07002847 res = &adev->res;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002848 pl330->base = devm_ioremap_resource(&adev->dev, res);
2849 if (IS_ERR(pl330->base))
2850 return PTR_ERR(pl330->base);
Jassi Brarb3040e42010-05-23 20:28:19 -07002851
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002852 amba_set_drvdata(adev, pl330);
Boojin Kima2f52032011-09-02 09:44:29 +09002853
Dan Carpenter02808b42013-11-08 12:50:24 +03002854 for (i = 0; i < AMBA_NR_IRQS; i++) {
Michal Simeke98b3ca2013-09-30 08:50:48 +02002855 irq = adev->irq[i];
2856 if (irq) {
2857 ret = devm_request_irq(&adev->dev, irq,
2858 pl330_irq_handler, 0,
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002859 dev_name(&adev->dev), pl330);
Michal Simeke98b3ca2013-09-30 08:50:48 +02002860 if (ret)
2861 return ret;
2862 } else {
2863 break;
2864 }
2865 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002866
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002867 pcfg = &pl330->pcfg;
2868
2869 pcfg->periph_id = adev->periphid;
2870 ret = pl330_add(pl330);
Jassi Brarb3040e42010-05-23 20:28:19 -07002871 if (ret)
Michal Simek173e8382013-09-04 16:40:17 +02002872 return ret;
Jassi Brarb3040e42010-05-23 20:28:19 -07002873
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002874 INIT_LIST_HEAD(&pl330->desc_pool);
2875 spin_lock_init(&pl330->pool_lock);
Jassi Brarb3040e42010-05-23 20:28:19 -07002876
2877 /* Create a descriptor pool of default size */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002878 if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC))
Jassi Brarb3040e42010-05-23 20:28:19 -07002879 dev_warn(&adev->dev, "unable to allocate desc\n");
2880
Jassi Brarb3040e42010-05-23 20:28:19 -07002881 INIT_LIST_HEAD(&pd->channels);
2882
2883 /* Initialize channel parameters */
Olof Johanssonc8473822012-04-08 16:26:19 -07002884 if (pdat)
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002885 num_chan = max_t(int, pdat->nr_valid_peri, pcfg->num_chan);
Olof Johanssonc8473822012-04-08 16:26:19 -07002886 else
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002887 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
Olof Johanssonc8473822012-04-08 16:26:19 -07002888
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002889 pl330->num_peripherals = num_chan;
Lars-Peter Clausen70cbb162014-01-11 20:08:39 +01002890
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002891 pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
2892 if (!pl330->peripherals) {
Sachin Kamat61c6e752012-09-17 15:20:23 +05302893 ret = -ENOMEM;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002894 dev_err(&adev->dev, "unable to allocate pl330->peripherals\n");
Sachin Kamate4d43c12012-11-15 06:27:50 +00002895 goto probe_err2;
Sachin Kamat61c6e752012-09-17 15:20:23 +05302896 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002897
Rob Herring4e0e6102011-07-25 16:05:04 -05002898 for (i = 0; i < num_chan; i++) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002899 pch = &pl330->peripherals[i];
Thomas Abraham93ed5542011-10-24 11:43:31 +02002900 if (!adev->dev.of_node)
2901 pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
2902 else
2903 pch->chan.private = adev->dev.of_node;
Jassi Brarb3040e42010-05-23 20:28:19 -07002904
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002905 INIT_LIST_HEAD(&pch->submitted_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002906 INIT_LIST_HEAD(&pch->work_list);
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002907 INIT_LIST_HEAD(&pch->completed_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002908 spin_lock_init(&pch->lock);
Lars-Peter Clausen65ad6062014-07-06 20:32:26 +02002909 pch->thread = NULL;
Jassi Brarb3040e42010-05-23 20:28:19 -07002910 pch->chan.device = pd;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002911 pch->dmac = pl330;
Jassi Brarb3040e42010-05-23 20:28:19 -07002912
2913 /* Add the channel to the DMAC list */
Jassi Brarb3040e42010-05-23 20:28:19 -07002914 list_add_tail(&pch->chan.device_node, &pd->channels);
2915 }
2916
Thomas Abraham93ed5542011-10-24 11:43:31 +02002917 if (pdat) {
Thomas Abrahamcd072512011-10-24 11:43:11 +02002918 pd->cap_mask = pdat->cap_mask;
Thomas Abraham93ed5542011-10-24 11:43:31 +02002919 } else {
Thomas Abrahamcd072512011-10-24 11:43:11 +02002920 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002921 if (pcfg->num_peri) {
Thomas Abraham93ed5542011-10-24 11:43:31 +02002922 dma_cap_set(DMA_SLAVE, pd->cap_mask);
2923 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
Tushar Behera5557a412012-08-29 10:16:25 +05302924 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
Thomas Abraham93ed5542011-10-24 11:43:31 +02002925 }
2926 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002927
2928 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
2929 pd->device_free_chan_resources = pl330_free_chan_resources;
2930 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002931 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
Jassi Brarb3040e42010-05-23 20:28:19 -07002932 pd->device_tx_status = pl330_tx_status;
2933 pd->device_prep_slave_sg = pl330_prep_slave_sg;
Maxime Ripard740aa952014-11-17 14:42:29 +01002934 pd->device_config = pl330_config;
Robert Baldyga88987d22015-02-11 13:23:18 +01002935 pd->device_pause = pl330_pause;
Maxime Ripard740aa952014-11-17 14:42:29 +01002936 pd->device_terminate_all = pl330_terminate_all;
Jassi Brarb3040e42010-05-23 20:28:19 -07002937 pd->device_issue_pending = pl330_issue_pending;
Maxime Riparddcabe4562014-11-17 14:42:50 +01002938 pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
2939 pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
2940 pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
Robert Baldygaaee4d1f2015-02-11 13:23:17 +01002941 pd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
Shawn Lin86a8ce72016-01-22 19:06:51 +08002942 pd->max_burst = ((pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) ?
2943 1 : PL330_MAX_BURST);
Jassi Brarb3040e42010-05-23 20:28:19 -07002944
2945 ret = dma_async_device_register(pd);
2946 if (ret) {
2947 dev_err(&adev->dev, "unable to register DMAC\n");
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302948 goto probe_err3;
2949 }
2950
2951 if (adev->dev.of_node) {
2952 ret = of_dma_controller_register(adev->dev.of_node,
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002953 of_dma_pl330_xlate, pl330);
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302954 if (ret) {
2955 dev_err(&adev->dev,
2956 "unable to register DMA to the generic DT DMA helpers\n");
2957 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002958 }
Lars-Peter Clausenb714b842013-11-25 16:07:46 +01002959
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002960 adev->dev.dma_parms = &pl330->dma_parms;
Lars-Peter Clausenb714b842013-11-25 16:07:46 +01002961
Vinod Kouldbaf6d82013-09-02 21:54:48 +05302962 /*
2963 * This is the limit for transfers with a buswidth of 1, larger
2964 * buswidths will have larger limits.
2965 */
2966 ret = dma_set_max_seg_size(&adev->dev, 1900800);
2967 if (ret)
2968 dev_err(&adev->dev, "unable to set the seg size\n");
2969
Jassi Brarb3040e42010-05-23 20:28:19 -07002970
Jassi Brarb3040e42010-05-23 20:28:19 -07002971 dev_info(&adev->dev,
Liviu Dudau1f0a5cb2014-11-06 17:20:12 +00002972 "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
Jassi Brarb3040e42010-05-23 20:28:19 -07002973 dev_info(&adev->dev,
2974 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002975 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
2976 pcfg->num_peri, pcfg->num_events);
Jassi Brarb3040e42010-05-23 20:28:19 -07002977
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002978 pm_runtime_irq_safe(&adev->dev);
2979 pm_runtime_use_autosuspend(&adev->dev);
2980 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
2981 pm_runtime_mark_last_busy(&adev->dev);
2982 pm_runtime_put_autosuspend(&adev->dev);
2983
Jassi Brarb3040e42010-05-23 20:28:19 -07002984 return 0;
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302985probe_err3:
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302986 /* Idle the DMAC */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002987 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302988 chan.device_node) {
2989
2990 /* Remove the channel */
2991 list_del(&pch->chan.device_node);
2992
2993 /* Flush the channel */
Krzysztof Kozlowski0f5ebab2014-09-29 14:42:20 +02002994 if (pch->thread) {
Maxime Ripard740aa952014-11-17 14:42:29 +01002995 pl330_terminate_all(&pch->chan);
Krzysztof Kozlowski0f5ebab2014-09-29 14:42:20 +02002996 pl330_free_chan_resources(&pch->chan);
2997 }
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302998 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002999probe_err2:
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02003000 pl330_del(pl330);
Jassi Brarb3040e42010-05-23 20:28:19 -07003001
3002 return ret;
3003}
3004
Greg Kroah-Hartman4bf27b82012-12-21 15:09:59 -08003005static int pl330_remove(struct amba_device *adev)
Jassi Brarb3040e42010-05-23 20:28:19 -07003006{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02003007 struct pl330_dmac *pl330 = amba_get_drvdata(adev);
Jassi Brarb3040e42010-05-23 20:28:19 -07003008 struct dma_pl330_chan *pch, *_p;
Jassi Brarb3040e42010-05-23 20:28:19 -07003009
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01003010 pm_runtime_get_noresume(pl330->ddma.dev);
3011
Padmavathi Venna0b94c572013-03-05 14:55:31 +05303012 if (adev->dev.of_node)
3013 of_dma_controller_free(adev->dev.of_node);
Padmavathi Venna421da892013-02-14 09:10:07 +05303014
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02003015 dma_async_device_unregister(&pl330->ddma);
Jassi Brarb3040e42010-05-23 20:28:19 -07003016
3017 /* Idle the DMAC */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02003018 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
Jassi Brarb3040e42010-05-23 20:28:19 -07003019 chan.device_node) {
3020
3021 /* Remove the channel */
3022 list_del(&pch->chan.device_node);
3023
3024 /* Flush the channel */
Krzysztof Kozlowski6e4a2a82014-09-29 14:42:21 +02003025 if (pch->thread) {
Maxime Ripard740aa952014-11-17 14:42:29 +01003026 pl330_terminate_all(&pch->chan);
Krzysztof Kozlowski6e4a2a82014-09-29 14:42:21 +02003027 pl330_free_chan_resources(&pch->chan);
3028 }
Jassi Brarb3040e42010-05-23 20:28:19 -07003029 }
3030
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02003031 pl330_del(pl330);
Jassi Brarb3040e42010-05-23 20:28:19 -07003032
Jassi Brarb3040e42010-05-23 20:28:19 -07003033 return 0;
3034}
3035
3036static struct amba_id pl330_ids[] = {
3037 {
3038 .id = 0x00041330,
3039 .mask = 0x000fffff,
3040 },
3041 { 0, 0 },
3042};
3043
Dave Martine8fa5162011-10-05 15:15:20 +01003044MODULE_DEVICE_TABLE(amba, pl330_ids);
3045
Jassi Brarb3040e42010-05-23 20:28:19 -07003046static struct amba_driver pl330_driver = {
3047 .drv = {
3048 .owner = THIS_MODULE,
3049 .name = "dma-pl330",
Krzysztof Kozlowskib816ccc2014-11-18 12:17:56 +01003050 .pm = &pl330_pm,
Jassi Brarb3040e42010-05-23 20:28:19 -07003051 },
3052 .id_table = pl330_ids,
3053 .probe = pl330_probe,
3054 .remove = pl330_remove,
3055};
3056
viresh kumar9e5ed092012-03-15 10:40:38 +01003057module_amba_driver(pl330_driver);
Jassi Brarb3040e42010-05-23 20:28:19 -07003058
Jassi Brar046209f2014-12-05 19:07:49 +05303059MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
Jassi Brarb3040e42010-05-23 20:28:19 -07003060MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3061MODULE_LICENSE("GPL");