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Boojin Kimb7d861d2011-12-26 18:49:52 +09001/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
Jassi Brarb3040e42010-05-23 20:28:19 -07004 *
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
Boojin Kimb7d861d2011-12-26 18:49:52 +090014#include <linux/kernel.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070015#include <linux/io.h>
16#include <linux/init.h>
17#include <linux/slab.h>
18#include <linux/module.h>
Boojin Kimb7d861d2011-12-26 18:49:52 +090019#include <linux/string.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/dma-mapping.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070023#include <linux/dmaengine.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070024#include <linux/amba/bus.h>
25#include <linux/amba/pl330.h>
Boojin Kim1b9bb712011-09-02 09:44:30 +090026#include <linux/scatterlist.h>
Thomas Abraham93ed5542011-10-24 11:43:31 +020027#include <linux/of.h>
Padmavathi Vennaa80258f2013-02-14 09:10:06 +053028#include <linux/of_dma.h>
Sachin Kamatbcc7fa92013-03-04 14:36:27 +053029#include <linux/err.h>
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +010030#include <linux/pm_runtime.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070031
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000032#include "dmaengine.h"
Boojin Kimb7d861d2011-12-26 18:49:52 +090033#define PL330_MAX_CHAN 8
34#define PL330_MAX_IRQS 32
35#define PL330_MAX_PERI 32
36
Lars-Peter Clausenf0564c72014-07-06 20:32:19 +020037enum pl330_cachectrl {
38 CCTRL0, /* Noncacheable and nonbufferable */
39 CCTRL1, /* Bufferable only */
40 CCTRL2, /* Cacheable, but do not allocate */
41 CCTRL3, /* Cacheable and bufferable, but do not allocate */
42 INVALID1, /* AWCACHE = 0x1000 */
43 INVALID2,
44 CCTRL6, /* Cacheable write-through, allocate on writes only */
45 CCTRL7, /* Cacheable write-back, allocate on writes only */
Boojin Kimb7d861d2011-12-26 18:49:52 +090046};
47
48enum pl330_byteswap {
49 SWAP_NO,
50 SWAP_2,
51 SWAP_4,
52 SWAP_8,
53 SWAP_16,
54};
55
Boojin Kimb7d861d2011-12-26 18:49:52 +090056/* Register and Bit field Definitions */
57#define DS 0x0
58#define DS_ST_STOP 0x0
59#define DS_ST_EXEC 0x1
60#define DS_ST_CMISS 0x2
61#define DS_ST_UPDTPC 0x3
62#define DS_ST_WFE 0x4
63#define DS_ST_ATBRR 0x5
64#define DS_ST_QBUSY 0x6
65#define DS_ST_WFP 0x7
66#define DS_ST_KILL 0x8
67#define DS_ST_CMPLT 0x9
68#define DS_ST_FLTCMP 0xe
69#define DS_ST_FAULT 0xf
70
71#define DPC 0x4
72#define INTEN 0x20
73#define ES 0x24
74#define INTSTATUS 0x28
75#define INTCLR 0x2c
76#define FSM 0x30
77#define FSC 0x34
78#define FTM 0x38
79
80#define _FTC 0x40
81#define FTC(n) (_FTC + (n)*0x4)
82
83#define _CS 0x100
84#define CS(n) (_CS + (n)*0x8)
85#define CS_CNS (1 << 21)
86
87#define _CPC 0x104
88#define CPC(n) (_CPC + (n)*0x8)
89
90#define _SA 0x400
91#define SA(n) (_SA + (n)*0x20)
92
93#define _DA 0x404
94#define DA(n) (_DA + (n)*0x20)
95
96#define _CC 0x408
97#define CC(n) (_CC + (n)*0x20)
98
99#define CC_SRCINC (1 << 0)
100#define CC_DSTINC (1 << 14)
101#define CC_SRCPRI (1 << 8)
102#define CC_DSTPRI (1 << 22)
103#define CC_SRCNS (1 << 9)
104#define CC_DSTNS (1 << 23)
105#define CC_SRCIA (1 << 10)
106#define CC_DSTIA (1 << 24)
107#define CC_SRCBRSTLEN_SHFT 4
108#define CC_DSTBRSTLEN_SHFT 18
109#define CC_SRCBRSTSIZE_SHFT 1
110#define CC_DSTBRSTSIZE_SHFT 15
111#define CC_SRCCCTRL_SHFT 11
112#define CC_SRCCCTRL_MASK 0x7
113#define CC_DSTCCTRL_SHFT 25
114#define CC_DRCCCTRL_MASK 0x7
115#define CC_SWAP_SHFT 28
116
117#define _LC0 0x40c
118#define LC0(n) (_LC0 + (n)*0x20)
119
120#define _LC1 0x410
121#define LC1(n) (_LC1 + (n)*0x20)
122
123#define DBGSTATUS 0xd00
124#define DBG_BUSY (1 << 0)
125
126#define DBGCMD 0xd04
127#define DBGINST0 0xd08
128#define DBGINST1 0xd0c
129
130#define CR0 0xe00
131#define CR1 0xe04
132#define CR2 0xe08
133#define CR3 0xe0c
134#define CR4 0xe10
135#define CRD 0xe14
136
137#define PERIPH_ID 0xfe0
Boojin Kim3ecf51a2011-12-26 18:55:47 +0900138#define PERIPH_REV_SHIFT 20
139#define PERIPH_REV_MASK 0xf
140#define PERIPH_REV_R0P0 0
141#define PERIPH_REV_R1P0 1
142#define PERIPH_REV_R1P1 2
Boojin Kimb7d861d2011-12-26 18:49:52 +0900143
144#define CR0_PERIPH_REQ_SET (1 << 0)
145#define CR0_BOOT_EN_SET (1 << 1)
146#define CR0_BOOT_MAN_NS (1 << 2)
147#define CR0_NUM_CHANS_SHIFT 4
148#define CR0_NUM_CHANS_MASK 0x7
149#define CR0_NUM_PERIPH_SHIFT 12
150#define CR0_NUM_PERIPH_MASK 0x1f
151#define CR0_NUM_EVENTS_SHIFT 17
152#define CR0_NUM_EVENTS_MASK 0x1f
153
154#define CR1_ICACHE_LEN_SHIFT 0
155#define CR1_ICACHE_LEN_MASK 0x7
156#define CR1_NUM_ICACHELINES_SHIFT 4
157#define CR1_NUM_ICACHELINES_MASK 0xf
158
159#define CRD_DATA_WIDTH_SHIFT 0
160#define CRD_DATA_WIDTH_MASK 0x7
161#define CRD_WR_CAP_SHIFT 4
162#define CRD_WR_CAP_MASK 0x7
163#define CRD_WR_Q_DEP_SHIFT 8
164#define CRD_WR_Q_DEP_MASK 0xf
165#define CRD_RD_CAP_SHIFT 12
166#define CRD_RD_CAP_MASK 0x7
167#define CRD_RD_Q_DEP_SHIFT 16
168#define CRD_RD_Q_DEP_MASK 0xf
169#define CRD_DATA_BUFF_SHIFT 20
170#define CRD_DATA_BUFF_MASK 0x3ff
171
172#define PART 0x330
173#define DESIGNER 0x41
174#define REVISION 0x0
175#define INTEG_CFG 0x0
176#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
177
Boojin Kimb7d861d2011-12-26 18:49:52 +0900178#define PL330_STATE_STOPPED (1 << 0)
179#define PL330_STATE_EXECUTING (1 << 1)
180#define PL330_STATE_WFE (1 << 2)
181#define PL330_STATE_FAULTING (1 << 3)
182#define PL330_STATE_COMPLETING (1 << 4)
183#define PL330_STATE_WFP (1 << 5)
184#define PL330_STATE_KILLING (1 << 6)
185#define PL330_STATE_FAULT_COMPLETING (1 << 7)
186#define PL330_STATE_CACHEMISS (1 << 8)
187#define PL330_STATE_UPDTPC (1 << 9)
188#define PL330_STATE_ATBARRIER (1 << 10)
189#define PL330_STATE_QUEUEBUSY (1 << 11)
190#define PL330_STATE_INVALID (1 << 15)
191
192#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
193 | PL330_STATE_WFE | PL330_STATE_FAULTING)
194
195#define CMD_DMAADDH 0x54
196#define CMD_DMAEND 0x00
197#define CMD_DMAFLUSHP 0x35
198#define CMD_DMAGO 0xa0
199#define CMD_DMALD 0x04
200#define CMD_DMALDP 0x25
201#define CMD_DMALP 0x20
202#define CMD_DMALPEND 0x28
203#define CMD_DMAKILL 0x01
204#define CMD_DMAMOV 0xbc
205#define CMD_DMANOP 0x18
206#define CMD_DMARMB 0x12
207#define CMD_DMASEV 0x34
208#define CMD_DMAST 0x08
209#define CMD_DMASTP 0x29
210#define CMD_DMASTZ 0x0c
211#define CMD_DMAWFE 0x36
212#define CMD_DMAWFP 0x30
213#define CMD_DMAWMB 0x13
214
215#define SZ_DMAADDH 3
216#define SZ_DMAEND 1
217#define SZ_DMAFLUSHP 2
218#define SZ_DMALD 1
219#define SZ_DMALDP 2
220#define SZ_DMALP 2
221#define SZ_DMALPEND 2
222#define SZ_DMAKILL 1
223#define SZ_DMAMOV 6
224#define SZ_DMANOP 1
225#define SZ_DMARMB 1
226#define SZ_DMASEV 2
227#define SZ_DMAST 1
228#define SZ_DMASTP 2
229#define SZ_DMASTZ 1
230#define SZ_DMAWFE 2
231#define SZ_DMAWFP 2
232#define SZ_DMAWMB 1
233#define SZ_DMAGO 6
234
235#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
236#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
237
238#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
239#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
240
241/*
242 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
243 * at 1byte/burst for P<->M and M<->M respectively.
244 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
245 * should be enough for P<->M and M<->M respectively.
246 */
247#define MCODE_BUFF_PER_REQ 256
248
Boojin Kimb7d861d2011-12-26 18:49:52 +0900249/* Use this _only_ to wait on transient states */
250#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
251
252#ifdef PL330_DEBUG_MCGEN
253static unsigned cmd_line;
254#define PL330_DBGCMD_DUMP(off, x...) do { \
255 printk("%x:", cmd_line); \
256 printk(x); \
257 cmd_line += off; \
258 } while (0)
259#define PL330_DBGMC_START(addr) (cmd_line = addr)
260#else
261#define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
262#define PL330_DBGMC_START(addr) do {} while (0)
263#endif
264
265/* The number of default descriptors */
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +0000266
Jassi Brarb3040e42010-05-23 20:28:19 -0700267#define NR_DEFAULT_DESC 16
268
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +0100269/* Delay for runtime PM autosuspend, ms */
270#define PL330_AUTOSUSPEND_DELAY 20
271
Boojin Kimb7d861d2011-12-26 18:49:52 +0900272/* Populated by the PL330 core driver for DMA API driver's info */
273struct pl330_config {
274 u32 periph_id;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900275#define DMAC_MODE_NS (1 << 0)
276 unsigned int mode;
277 unsigned int data_bus_width:10; /* In number of bits */
278 unsigned int data_buf_dep:10;
279 unsigned int num_chan:4;
280 unsigned int num_peri:6;
281 u32 peri_ns;
282 unsigned int num_events:6;
283 u32 irq_ns;
284};
285
Boojin Kimb7d861d2011-12-26 18:49:52 +0900286/**
287 * Request Configuration.
288 * The PL330 core does not modify this and uses the last
289 * working configuration if the request doesn't provide any.
290 *
291 * The Client may want to provide this info only for the
292 * first request and a request with new settings.
293 */
294struct pl330_reqcfg {
295 /* Address Incrementing */
296 unsigned dst_inc:1;
297 unsigned src_inc:1;
298
299 /*
300 * For now, the SRC & DST protection levels
301 * and burst size/length are assumed same.
302 */
303 bool nonsecure;
304 bool privileged;
305 bool insnaccess;
306 unsigned brst_len:5;
307 unsigned brst_size:3; /* in power of 2 */
308
Lars-Peter Clausenf0564c72014-07-06 20:32:19 +0200309 enum pl330_cachectrl dcctl;
310 enum pl330_cachectrl scctl;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900311 enum pl330_byteswap swap;
Boojin Kim3ecf51a2011-12-26 18:55:47 +0900312 struct pl330_config *pcfg;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900313};
314
315/*
316 * One cycle of DMAC operation.
317 * There may be more than one xfer in a request.
318 */
319struct pl330_xfer {
320 u32 src_addr;
321 u32 dst_addr;
322 /* Size to xfer */
323 u32 bytes;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900324};
325
326/* The xfer callbacks are made with one of these arguments. */
327enum pl330_op_err {
328 /* The all xfers in the request were success. */
329 PL330_ERR_NONE,
330 /* If req aborted due to global error. */
331 PL330_ERR_ABORT,
332 /* If req failed due to problem with Channel. */
333 PL330_ERR_FAIL,
334};
335
Boojin Kimb7d861d2011-12-26 18:49:52 +0900336enum dmamov_dst {
337 SAR = 0,
338 CCR,
339 DAR,
340};
341
342enum pl330_dst {
343 SRC = 0,
344 DST,
345};
346
347enum pl330_cond {
348 SINGLE,
349 BURST,
350 ALWAYS,
351};
352
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +0200353struct dma_pl330_desc;
354
Boojin Kimb7d861d2011-12-26 18:49:52 +0900355struct _pl330_req {
356 u32 mc_bus;
357 void *mc_cpu;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +0200358 struct dma_pl330_desc *desc;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900359};
360
361/* ToBeDone for tasklet */
362struct _pl330_tbd {
363 bool reset_dmac;
364 bool reset_mngr;
365 u8 reset_chan;
366};
367
368/* A DMAC Thread */
369struct pl330_thread {
370 u8 id;
371 int ev;
372 /* If the channel is not yet acquired by any client */
373 bool free;
374 /* Parent DMAC */
375 struct pl330_dmac *dmac;
376 /* Only two at a time */
377 struct _pl330_req req[2];
378 /* Index of the last enqueued request */
379 unsigned lstenq;
380 /* Index of the last submitted request or -1 if the DMA is stopped */
381 int req_running;
382};
383
384enum pl330_dmac_state {
385 UNINIT,
386 INIT,
387 DYING,
388};
389
Jassi Brarb3040e42010-05-23 20:28:19 -0700390enum desc_status {
391 /* In the DMAC pool */
392 FREE,
393 /*
Masanari Iidad73111c2012-08-04 23:37:53 +0900394 * Allocated to some channel during prep_xxx
Jassi Brarb3040e42010-05-23 20:28:19 -0700395 * Also may be sitting on the work_list.
396 */
397 PREP,
398 /*
399 * Sitting on the work_list and already submitted
400 * to the PL330 core. Not more than two descriptors
401 * of a channel can be BUSY at any time.
402 */
403 BUSY,
404 /*
405 * Sitting on the channel work_list but xfer done
406 * by PL330 core
407 */
408 DONE,
409};
410
411struct dma_pl330_chan {
412 /* Schedule desc completion */
413 struct tasklet_struct task;
414
415 /* DMA-Engine Channel */
416 struct dma_chan chan;
417
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +0100418 /* List of submitted descriptors */
419 struct list_head submitted_list;
420 /* List of issued descriptors */
Jassi Brarb3040e42010-05-23 20:28:19 -0700421 struct list_head work_list;
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +0200422 /* List of completed descriptors */
423 struct list_head completed_list;
Jassi Brarb3040e42010-05-23 20:28:19 -0700424
425 /* Pointer to the DMAC that manages this channel,
426 * NULL if the channel is available to be acquired.
427 * As the parent, this DMAC also provides descriptors
428 * to the channel.
429 */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200430 struct pl330_dmac *dmac;
Jassi Brarb3040e42010-05-23 20:28:19 -0700431
432 /* To protect channel manipulation */
433 spinlock_t lock;
434
Lars-Peter Clausen65ad6062014-07-06 20:32:26 +0200435 /*
436 * Hardware channel thread of PL330 DMAC. NULL if the channel is
437 * available.
Jassi Brarb3040e42010-05-23 20:28:19 -0700438 */
Lars-Peter Clausen65ad6062014-07-06 20:32:26 +0200439 struct pl330_thread *thread;
Boojin Kim1b9bb712011-09-02 09:44:30 +0900440
441 /* For D-to-M and M-to-D channels */
442 int burst_sz; /* the peripheral fifo width */
Boojin Kim1d0c1d62011-09-02 09:44:31 +0900443 int burst_len; /* the number of burst */
Boojin Kim1b9bb712011-09-02 09:44:30 +0900444 dma_addr_t fifo_addr;
Boojin Kim42bc9cf2011-09-02 09:44:33 +0900445
446 /* for cyclic capability */
447 bool cyclic;
Jassi Brarb3040e42010-05-23 20:28:19 -0700448};
449
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200450struct pl330_dmac {
Jassi Brarb3040e42010-05-23 20:28:19 -0700451 /* DMA-Engine Device */
452 struct dma_device ddma;
453
Lars-Peter Clausenb714b842013-11-25 16:07:46 +0100454 /* Holds info about sg limitations */
455 struct device_dma_parameters dma_parms;
456
Jassi Brarb3040e42010-05-23 20:28:19 -0700457 /* Pool of descriptors available for the DMAC's channels */
458 struct list_head desc_pool;
459 /* To protect desc_pool manipulation */
460 spinlock_t pool_lock;
461
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200462 /* Size of MicroCode buffers for each channel. */
463 unsigned mcbufsz;
464 /* ioremap'ed address of PL330 registers. */
465 void __iomem *base;
466 /* Populated by the PL330 core driver during pl330_add */
467 struct pl330_config pcfg;
468
469 spinlock_t lock;
470 /* Maximum possible events/irqs */
471 int events[32];
472 /* BUS address of MicroCode buffer */
473 dma_addr_t mcode_bus;
474 /* CPU address of MicroCode buffer */
475 void *mcode_cpu;
476 /* List of all Channel threads */
477 struct pl330_thread *channels;
478 /* Pointer to the MANAGER thread */
479 struct pl330_thread *manager;
480 /* To handle bad news in interrupt */
481 struct tasklet_struct tasks;
482 struct _pl330_tbd dmac_tbd;
483 /* State of DMAC operation */
484 enum pl330_dmac_state state;
485 /* Holds list of reqs with due callbacks */
486 struct list_head req_done;
487
Jassi Brarb3040e42010-05-23 20:28:19 -0700488 /* Peripheral channels connected to this DMAC */
Lars-Peter Clausen70cbb162014-01-11 20:08:39 +0100489 unsigned int num_peripherals;
Rob Herring4e0e6102011-07-25 16:05:04 -0500490 struct dma_pl330_chan *peripherals; /* keep at end */
Jassi Brarb3040e42010-05-23 20:28:19 -0700491};
492
493struct dma_pl330_desc {
494 /* To attach to a queue as child */
495 struct list_head node;
496
497 /* Descriptor for the DMA Engine API */
498 struct dma_async_tx_descriptor txd;
499
500 /* Xfer for PL330 core */
501 struct pl330_xfer px;
502
503 struct pl330_reqcfg rqcfg;
Jassi Brarb3040e42010-05-23 20:28:19 -0700504
505 enum desc_status status;
506
507 /* The channel which currently holds this desc */
508 struct dma_pl330_chan *pchan;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +0200509
510 enum dma_transfer_direction rqtype;
511 /* Index of peripheral for the xfer. */
512 unsigned peri:5;
513 /* Hook to attach to DMAC's list of reqs with due callback */
514 struct list_head rqd;
515};
516
517struct _xfer_spec {
518 u32 ccr;
519 struct dma_pl330_desc *desc;
Jassi Brarb3040e42010-05-23 20:28:19 -0700520};
521
Boojin Kimb7d861d2011-12-26 18:49:52 +0900522static inline bool _queue_empty(struct pl330_thread *thrd)
523{
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +0200524 return thrd->req[0].desc == NULL && thrd->req[1].desc == NULL;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900525}
526
527static inline bool _queue_full(struct pl330_thread *thrd)
528{
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +0200529 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900530}
531
532static inline bool is_manager(struct pl330_thread *thrd)
533{
Lars-Peter Clausenfbbcd9b2014-07-06 20:32:28 +0200534 return thrd->dmac->manager == thrd;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900535}
536
537/* If manager of the thread is in Non-Secure mode */
538static inline bool _manager_ns(struct pl330_thread *thrd)
539{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200540 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900541}
542
Boojin Kim3ecf51a2011-12-26 18:55:47 +0900543static inline u32 get_revision(u32 periph_id)
544{
545 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
546}
547
Boojin Kimb7d861d2011-12-26 18:49:52 +0900548static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
549 enum pl330_dst da, u16 val)
550{
551 if (dry_run)
552 return SZ_DMAADDH;
553
554 buf[0] = CMD_DMAADDH;
555 buf[0] |= (da << 1);
556 *((u16 *)&buf[1]) = val;
557
558 PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
559 da == 1 ? "DA" : "SA", val);
560
561 return SZ_DMAADDH;
562}
563
564static inline u32 _emit_END(unsigned dry_run, u8 buf[])
565{
566 if (dry_run)
567 return SZ_DMAEND;
568
569 buf[0] = CMD_DMAEND;
570
571 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
572
573 return SZ_DMAEND;
574}
575
576static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
577{
578 if (dry_run)
579 return SZ_DMAFLUSHP;
580
581 buf[0] = CMD_DMAFLUSHP;
582
583 peri &= 0x1f;
584 peri <<= 3;
585 buf[1] = peri;
586
587 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
588
589 return SZ_DMAFLUSHP;
590}
591
592static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
593{
594 if (dry_run)
595 return SZ_DMALD;
596
597 buf[0] = CMD_DMALD;
598
599 if (cond == SINGLE)
600 buf[0] |= (0 << 1) | (1 << 0);
601 else if (cond == BURST)
602 buf[0] |= (1 << 1) | (1 << 0);
603
604 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
605 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
606
607 return SZ_DMALD;
608}
609
610static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
611 enum pl330_cond cond, u8 peri)
612{
613 if (dry_run)
614 return SZ_DMALDP;
615
616 buf[0] = CMD_DMALDP;
617
618 if (cond == BURST)
619 buf[0] |= (1 << 1);
620
621 peri &= 0x1f;
622 peri <<= 3;
623 buf[1] = peri;
624
625 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
626 cond == SINGLE ? 'S' : 'B', peri >> 3);
627
628 return SZ_DMALDP;
629}
630
631static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
632 unsigned loop, u8 cnt)
633{
634 if (dry_run)
635 return SZ_DMALP;
636
637 buf[0] = CMD_DMALP;
638
639 if (loop)
640 buf[0] |= (1 << 1);
641
642 cnt--; /* DMAC increments by 1 internally */
643 buf[1] = cnt;
644
645 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
646
647 return SZ_DMALP;
648}
649
650struct _arg_LPEND {
651 enum pl330_cond cond;
652 bool forever;
653 unsigned loop;
654 u8 bjump;
655};
656
657static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
658 const struct _arg_LPEND *arg)
659{
660 enum pl330_cond cond = arg->cond;
661 bool forever = arg->forever;
662 unsigned loop = arg->loop;
663 u8 bjump = arg->bjump;
664
665 if (dry_run)
666 return SZ_DMALPEND;
667
668 buf[0] = CMD_DMALPEND;
669
670 if (loop)
671 buf[0] |= (1 << 2);
672
673 if (!forever)
674 buf[0] |= (1 << 4);
675
676 if (cond == SINGLE)
677 buf[0] |= (0 << 1) | (1 << 0);
678 else if (cond == BURST)
679 buf[0] |= (1 << 1) | (1 << 0);
680
681 buf[1] = bjump;
682
683 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
684 forever ? "FE" : "END",
685 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
686 loop ? '1' : '0',
687 bjump);
688
689 return SZ_DMALPEND;
690}
691
692static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
693{
694 if (dry_run)
695 return SZ_DMAKILL;
696
697 buf[0] = CMD_DMAKILL;
698
699 return SZ_DMAKILL;
700}
701
702static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
703 enum dmamov_dst dst, u32 val)
704{
705 if (dry_run)
706 return SZ_DMAMOV;
707
708 buf[0] = CMD_DMAMOV;
709 buf[1] = dst;
710 *((u32 *)&buf[2]) = val;
711
712 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
713 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
714
715 return SZ_DMAMOV;
716}
717
718static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
719{
720 if (dry_run)
721 return SZ_DMANOP;
722
723 buf[0] = CMD_DMANOP;
724
725 PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
726
727 return SZ_DMANOP;
728}
729
730static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
731{
732 if (dry_run)
733 return SZ_DMARMB;
734
735 buf[0] = CMD_DMARMB;
736
737 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
738
739 return SZ_DMARMB;
740}
741
742static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
743{
744 if (dry_run)
745 return SZ_DMASEV;
746
747 buf[0] = CMD_DMASEV;
748
749 ev &= 0x1f;
750 ev <<= 3;
751 buf[1] = ev;
752
753 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
754
755 return SZ_DMASEV;
756}
757
758static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
759{
760 if (dry_run)
761 return SZ_DMAST;
762
763 buf[0] = CMD_DMAST;
764
765 if (cond == SINGLE)
766 buf[0] |= (0 << 1) | (1 << 0);
767 else if (cond == BURST)
768 buf[0] |= (1 << 1) | (1 << 0);
769
770 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
771 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
772
773 return SZ_DMAST;
774}
775
776static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
777 enum pl330_cond cond, u8 peri)
778{
779 if (dry_run)
780 return SZ_DMASTP;
781
782 buf[0] = CMD_DMASTP;
783
784 if (cond == BURST)
785 buf[0] |= (1 << 1);
786
787 peri &= 0x1f;
788 peri <<= 3;
789 buf[1] = peri;
790
791 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
792 cond == SINGLE ? 'S' : 'B', peri >> 3);
793
794 return SZ_DMASTP;
795}
796
797static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
798{
799 if (dry_run)
800 return SZ_DMASTZ;
801
802 buf[0] = CMD_DMASTZ;
803
804 PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
805
806 return SZ_DMASTZ;
807}
808
809static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
810 unsigned invalidate)
811{
812 if (dry_run)
813 return SZ_DMAWFE;
814
815 buf[0] = CMD_DMAWFE;
816
817 ev &= 0x1f;
818 ev <<= 3;
819 buf[1] = ev;
820
821 if (invalidate)
822 buf[1] |= (1 << 1);
823
824 PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
825 ev >> 3, invalidate ? ", I" : "");
826
827 return SZ_DMAWFE;
828}
829
830static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
831 enum pl330_cond cond, u8 peri)
832{
833 if (dry_run)
834 return SZ_DMAWFP;
835
836 buf[0] = CMD_DMAWFP;
837
838 if (cond == SINGLE)
839 buf[0] |= (0 << 1) | (0 << 0);
840 else if (cond == BURST)
841 buf[0] |= (1 << 1) | (0 << 0);
842 else
843 buf[0] |= (0 << 1) | (1 << 0);
844
845 peri &= 0x1f;
846 peri <<= 3;
847 buf[1] = peri;
848
849 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
850 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
851
852 return SZ_DMAWFP;
853}
854
855static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
856{
857 if (dry_run)
858 return SZ_DMAWMB;
859
860 buf[0] = CMD_DMAWMB;
861
862 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
863
864 return SZ_DMAWMB;
865}
866
867struct _arg_GO {
868 u8 chan;
869 u32 addr;
870 unsigned ns;
871};
872
873static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
874 const struct _arg_GO *arg)
875{
876 u8 chan = arg->chan;
877 u32 addr = arg->addr;
878 unsigned ns = arg->ns;
879
880 if (dry_run)
881 return SZ_DMAGO;
882
883 buf[0] = CMD_DMAGO;
884 buf[0] |= (ns << 1);
885
886 buf[1] = chan & 0x7;
887
888 *((u32 *)&buf[2]) = addr;
889
890 return SZ_DMAGO;
891}
892
893#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
894
895/* Returns Time-Out */
896static bool _until_dmac_idle(struct pl330_thread *thrd)
897{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200898 void __iomem *regs = thrd->dmac->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900899 unsigned long loops = msecs_to_loops(5);
900
901 do {
902 /* Until Manager is Idle */
903 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
904 break;
905
906 cpu_relax();
907 } while (--loops);
908
909 if (!loops)
910 return true;
911
912 return false;
913}
914
915static inline void _execute_DBGINSN(struct pl330_thread *thrd,
916 u8 insn[], bool as_manager)
917{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200918 void __iomem *regs = thrd->dmac->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900919 u32 val;
920
921 val = (insn[0] << 16) | (insn[1] << 24);
922 if (!as_manager) {
923 val |= (1 << 0);
924 val |= (thrd->id << 8); /* Channel Number */
925 }
926 writel(val, regs + DBGINST0);
927
928 val = *((u32 *)&insn[2]);
929 writel(val, regs + DBGINST1);
930
931 /* If timed out due to halted state-machine */
932 if (_until_dmac_idle(thrd)) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200933 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
Boojin Kimb7d861d2011-12-26 18:49:52 +0900934 return;
935 }
936
937 /* Get going */
938 writel(0, regs + DBGCMD);
939}
940
Boojin Kimb7d861d2011-12-26 18:49:52 +0900941static inline u32 _state(struct pl330_thread *thrd)
942{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +0200943 void __iomem *regs = thrd->dmac->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900944 u32 val;
945
946 if (is_manager(thrd))
947 val = readl(regs + DS) & 0xf;
948 else
949 val = readl(regs + CS(thrd->id)) & 0xf;
950
951 switch (val) {
952 case DS_ST_STOP:
953 return PL330_STATE_STOPPED;
954 case DS_ST_EXEC:
955 return PL330_STATE_EXECUTING;
956 case DS_ST_CMISS:
957 return PL330_STATE_CACHEMISS;
958 case DS_ST_UPDTPC:
959 return PL330_STATE_UPDTPC;
960 case DS_ST_WFE:
961 return PL330_STATE_WFE;
962 case DS_ST_FAULT:
963 return PL330_STATE_FAULTING;
964 case DS_ST_ATBRR:
965 if (is_manager(thrd))
966 return PL330_STATE_INVALID;
967 else
968 return PL330_STATE_ATBARRIER;
969 case DS_ST_QBUSY:
970 if (is_manager(thrd))
971 return PL330_STATE_INVALID;
972 else
973 return PL330_STATE_QUEUEBUSY;
974 case DS_ST_WFP:
975 if (is_manager(thrd))
976 return PL330_STATE_INVALID;
977 else
978 return PL330_STATE_WFP;
979 case DS_ST_KILL:
980 if (is_manager(thrd))
981 return PL330_STATE_INVALID;
982 else
983 return PL330_STATE_KILLING;
984 case DS_ST_CMPLT:
985 if (is_manager(thrd))
986 return PL330_STATE_INVALID;
987 else
988 return PL330_STATE_COMPLETING;
989 case DS_ST_FLTCMP:
990 if (is_manager(thrd))
991 return PL330_STATE_INVALID;
992 else
993 return PL330_STATE_FAULT_COMPLETING;
994 default:
995 return PL330_STATE_INVALID;
996 }
997}
998
999static void _stop(struct pl330_thread *thrd)
1000{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001001 void __iomem *regs = thrd->dmac->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001002 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1003
1004 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
1005 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1006
1007 /* Return if nothing needs to be done */
1008 if (_state(thrd) == PL330_STATE_COMPLETING
1009 || _state(thrd) == PL330_STATE_KILLING
1010 || _state(thrd) == PL330_STATE_STOPPED)
1011 return;
1012
1013 _emit_KILL(0, insn);
1014
1015 /* Stop generating interrupts for SEV */
1016 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
1017
1018 _execute_DBGINSN(thrd, insn, is_manager(thrd));
1019}
1020
1021/* Start doing req 'idx' of thread 'thrd' */
1022static bool _trigger(struct pl330_thread *thrd)
1023{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001024 void __iomem *regs = thrd->dmac->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001025 struct _pl330_req *req;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001026 struct dma_pl330_desc *desc;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001027 struct _arg_GO go;
1028 unsigned ns;
1029 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1030 int idx;
1031
1032 /* Return if already ACTIVE */
1033 if (_state(thrd) != PL330_STATE_STOPPED)
1034 return true;
1035
1036 idx = 1 - thrd->lstenq;
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001037 if (thrd->req[idx].desc != NULL) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001038 req = &thrd->req[idx];
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001039 } else {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001040 idx = thrd->lstenq;
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001041 if (thrd->req[idx].desc != NULL)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001042 req = &thrd->req[idx];
1043 else
1044 req = NULL;
1045 }
1046
1047 /* Return if no request */
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001048 if (!req)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001049 return true;
1050
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001051 desc = req->desc;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001052
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001053 ns = desc->rqcfg.nonsecure ? 1 : 0;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001054
1055 /* See 'Abort Sources' point-4 at Page 2-25 */
1056 if (_manager_ns(thrd) && !ns)
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001057 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
Boojin Kimb7d861d2011-12-26 18:49:52 +09001058 __func__, __LINE__);
1059
1060 go.chan = thrd->id;
1061 go.addr = req->mc_bus;
1062 go.ns = ns;
1063 _emit_GO(0, insn, &go);
1064
1065 /* Set to generate interrupts for SEV */
1066 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1067
1068 /* Only manager can execute GO */
1069 _execute_DBGINSN(thrd, insn, true);
1070
1071 thrd->req_running = idx;
1072
1073 return true;
1074}
1075
1076static bool _start(struct pl330_thread *thrd)
1077{
1078 switch (_state(thrd)) {
1079 case PL330_STATE_FAULT_COMPLETING:
1080 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1081
1082 if (_state(thrd) == PL330_STATE_KILLING)
1083 UNTIL(thrd, PL330_STATE_STOPPED)
1084
1085 case PL330_STATE_FAULTING:
1086 _stop(thrd);
1087
1088 case PL330_STATE_KILLING:
1089 case PL330_STATE_COMPLETING:
1090 UNTIL(thrd, PL330_STATE_STOPPED)
1091
1092 case PL330_STATE_STOPPED:
1093 return _trigger(thrd);
1094
1095 case PL330_STATE_WFP:
1096 case PL330_STATE_QUEUEBUSY:
1097 case PL330_STATE_ATBARRIER:
1098 case PL330_STATE_UPDTPC:
1099 case PL330_STATE_CACHEMISS:
1100 case PL330_STATE_EXECUTING:
1101 return true;
1102
1103 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1104 default:
1105 return false;
1106 }
1107}
1108
1109static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1110 const struct _xfer_spec *pxs, int cyc)
1111{
1112 int off = 0;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001113 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001114
Boojin Kim3ecf51a2011-12-26 18:55:47 +09001115 /* check lock-up free version */
1116 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1117 while (cyc--) {
1118 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1119 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1120 }
1121 } else {
1122 while (cyc--) {
1123 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1124 off += _emit_RMB(dry_run, &buf[off]);
1125 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1126 off += _emit_WMB(dry_run, &buf[off]);
1127 }
Boojin Kimb7d861d2011-12-26 18:49:52 +09001128 }
1129
1130 return off;
1131}
1132
1133static inline int _ldst_devtomem(unsigned dry_run, u8 buf[],
1134 const struct _xfer_spec *pxs, int cyc)
1135{
1136 int off = 0;
1137
1138 while (cyc--) {
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001139 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
1140 off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001141 off += _emit_ST(dry_run, &buf[off], ALWAYS);
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001142 off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001143 }
1144
1145 return off;
1146}
1147
1148static inline int _ldst_memtodev(unsigned dry_run, u8 buf[],
1149 const struct _xfer_spec *pxs, int cyc)
1150{
1151 int off = 0;
1152
1153 while (cyc--) {
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001154 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001155 off += _emit_LD(dry_run, &buf[off], ALWAYS);
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001156 off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
1157 off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001158 }
1159
1160 return off;
1161}
1162
1163static int _bursts(unsigned dry_run, u8 buf[],
1164 const struct _xfer_spec *pxs, int cyc)
1165{
1166 int off = 0;
1167
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001168 switch (pxs->desc->rqtype) {
Lars-Peter Clausen585a9d02014-07-06 20:32:18 +02001169 case DMA_MEM_TO_DEV:
Boojin Kimb7d861d2011-12-26 18:49:52 +09001170 off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc);
1171 break;
Lars-Peter Clausen585a9d02014-07-06 20:32:18 +02001172 case DMA_DEV_TO_MEM:
Boojin Kimb7d861d2011-12-26 18:49:52 +09001173 off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc);
1174 break;
Lars-Peter Clausen585a9d02014-07-06 20:32:18 +02001175 case DMA_MEM_TO_MEM:
Boojin Kimb7d861d2011-12-26 18:49:52 +09001176 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1177 break;
1178 default:
1179 off += 0x40000000; /* Scare off the Client */
1180 break;
1181 }
1182
1183 return off;
1184}
1185
1186/* Returns bytes consumed and updates bursts */
1187static inline int _loop(unsigned dry_run, u8 buf[],
1188 unsigned long *bursts, const struct _xfer_spec *pxs)
1189{
1190 int cyc, cycmax, szlp, szlpend, szbrst, off;
1191 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1192 struct _arg_LPEND lpend;
1193
1194 /* Max iterations possible in DMALP is 256 */
1195 if (*bursts >= 256*256) {
1196 lcnt1 = 256;
1197 lcnt0 = 256;
1198 cyc = *bursts / lcnt1 / lcnt0;
1199 } else if (*bursts > 256) {
1200 lcnt1 = 256;
1201 lcnt0 = *bursts / lcnt1;
1202 cyc = 1;
1203 } else {
1204 lcnt1 = *bursts;
1205 lcnt0 = 0;
1206 cyc = 1;
1207 }
1208
1209 szlp = _emit_LP(1, buf, 0, 0);
1210 szbrst = _bursts(1, buf, pxs, 1);
1211
1212 lpend.cond = ALWAYS;
1213 lpend.forever = false;
1214 lpend.loop = 0;
1215 lpend.bjump = 0;
1216 szlpend = _emit_LPEND(1, buf, &lpend);
1217
1218 if (lcnt0) {
1219 szlp *= 2;
1220 szlpend *= 2;
1221 }
1222
1223 /*
1224 * Max bursts that we can unroll due to limit on the
1225 * size of backward jump that can be encoded in DMALPEND
1226 * which is 8-bits and hence 255
1227 */
1228 cycmax = (255 - (szlp + szlpend)) / szbrst;
1229
1230 cyc = (cycmax < cyc) ? cycmax : cyc;
1231
1232 off = 0;
1233
1234 if (lcnt0) {
1235 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1236 ljmp0 = off;
1237 }
1238
1239 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1240 ljmp1 = off;
1241
1242 off += _bursts(dry_run, &buf[off], pxs, cyc);
1243
1244 lpend.cond = ALWAYS;
1245 lpend.forever = false;
1246 lpend.loop = 1;
1247 lpend.bjump = off - ljmp1;
1248 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1249
1250 if (lcnt0) {
1251 lpend.cond = ALWAYS;
1252 lpend.forever = false;
1253 lpend.loop = 0;
1254 lpend.bjump = off - ljmp0;
1255 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1256 }
1257
1258 *bursts = lcnt1 * cyc;
1259 if (lcnt0)
1260 *bursts *= lcnt0;
1261
1262 return off;
1263}
1264
1265static inline int _setup_loops(unsigned dry_run, u8 buf[],
1266 const struct _xfer_spec *pxs)
1267{
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001268 struct pl330_xfer *x = &pxs->desc->px;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001269 u32 ccr = pxs->ccr;
1270 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1271 int off = 0;
1272
1273 while (bursts) {
1274 c = bursts;
1275 off += _loop(dry_run, &buf[off], &c, pxs);
1276 bursts -= c;
1277 }
1278
1279 return off;
1280}
1281
1282static inline int _setup_xfer(unsigned dry_run, u8 buf[],
1283 const struct _xfer_spec *pxs)
1284{
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001285 struct pl330_xfer *x = &pxs->desc->px;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001286 int off = 0;
1287
1288 /* DMAMOV SAR, x->src_addr */
1289 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1290 /* DMAMOV DAR, x->dst_addr */
1291 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1292
1293 /* Setup Loop(s) */
1294 off += _setup_loops(dry_run, &buf[off], pxs);
1295
1296 return off;
1297}
1298
1299/*
1300 * A req is a sequence of one or more xfer units.
1301 * Returns the number of bytes taken to setup the MC for the req.
1302 */
1303static int _setup_req(unsigned dry_run, struct pl330_thread *thrd,
1304 unsigned index, struct _xfer_spec *pxs)
1305{
1306 struct _pl330_req *req = &thrd->req[index];
1307 struct pl330_xfer *x;
1308 u8 *buf = req->mc_cpu;
1309 int off = 0;
1310
1311 PL330_DBGMC_START(req->mc_bus);
1312
1313 /* DMAMOV CCR, ccr */
1314 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1315
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001316 x = &pxs->desc->px;
Lars-Peter Clausend5cef122014-07-06 20:32:23 +02001317 /* Error if xfer length is not aligned at burst size */
1318 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1319 return -EINVAL;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001320
Lars-Peter Clausend5cef122014-07-06 20:32:23 +02001321 off += _setup_xfer(dry_run, &buf[off], pxs);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001322
1323 /* DMASEV peripheral/event */
1324 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1325 /* DMAEND */
1326 off += _emit_END(dry_run, &buf[off]);
1327
1328 return off;
1329}
1330
1331static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1332{
1333 u32 ccr = 0;
1334
1335 if (rqc->src_inc)
1336 ccr |= CC_SRCINC;
1337
1338 if (rqc->dst_inc)
1339 ccr |= CC_DSTINC;
1340
1341 /* We set same protection levels for Src and DST for now */
1342 if (rqc->privileged)
1343 ccr |= CC_SRCPRI | CC_DSTPRI;
1344 if (rqc->nonsecure)
1345 ccr |= CC_SRCNS | CC_DSTNS;
1346 if (rqc->insnaccess)
1347 ccr |= CC_SRCIA | CC_DSTIA;
1348
1349 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1350 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1351
1352 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1353 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1354
1355 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1356 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1357
1358 ccr |= (rqc->swap << CC_SWAP_SHFT);
1359
1360 return ccr;
1361}
1362
Boojin Kimb7d861d2011-12-26 18:49:52 +09001363/*
1364 * Submit a list of xfers after which the client wants notification.
1365 * Client is not notified after each xfer unit, just once after all
1366 * xfer units are done or some error occurs.
1367 */
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001368static int pl330_submit_req(struct pl330_thread *thrd,
1369 struct dma_pl330_desc *desc)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001370{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001371 struct pl330_dmac *pl330 = thrd->dmac;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001372 struct _xfer_spec xs;
1373 unsigned long flags;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001374 unsigned idx;
1375 u32 ccr;
1376 int ret = 0;
1377
Boojin Kimb7d861d2011-12-26 18:49:52 +09001378 if (pl330->state == DYING
1379 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001380 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
Boojin Kimb7d861d2011-12-26 18:49:52 +09001381 __func__, __LINE__);
1382 return -EAGAIN;
1383 }
1384
1385 /* If request for non-existing peripheral */
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001386 if (desc->rqtype != DMA_MEM_TO_MEM &&
1387 desc->peri >= pl330->pcfg.num_peri) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001388 dev_info(thrd->dmac->ddma.dev,
Boojin Kimb7d861d2011-12-26 18:49:52 +09001389 "%s:%d Invalid peripheral(%u)!\n",
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001390 __func__, __LINE__, desc->peri);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001391 return -EINVAL;
1392 }
1393
1394 spin_lock_irqsave(&pl330->lock, flags);
1395
1396 if (_queue_full(thrd)) {
1397 ret = -EAGAIN;
1398 goto xfer_exit;
1399 }
1400
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001401 /* Prefer Secure Channel */
1402 if (!_manager_ns(thrd))
1403 desc->rqcfg.nonsecure = 0;
1404 else
1405 desc->rqcfg.nonsecure = 1;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001406
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001407 ccr = _prepare_ccr(&desc->rqcfg);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001408
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001409 idx = thrd->req[0].desc == NULL ? 0 : 1;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001410
1411 xs.ccr = ccr;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001412 xs.desc = desc;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001413
1414 /* First dry run to check if req is acceptable */
1415 ret = _setup_req(1, thrd, idx, &xs);
1416 if (ret < 0)
1417 goto xfer_exit;
1418
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001419 if (ret > pl330->mcbufsz / 2) {
1420 dev_info(pl330->ddma.dev, "%s:%d Trying increasing mcbufsz\n",
Boojin Kimb7d861d2011-12-26 18:49:52 +09001421 __func__, __LINE__);
1422 ret = -ENOMEM;
1423 goto xfer_exit;
1424 }
1425
1426 /* Hook the request */
1427 thrd->lstenq = idx;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001428 thrd->req[idx].desc = desc;
Lars-Peter Clausenbe025322014-07-06 20:32:24 +02001429 _setup_req(0, thrd, idx, &xs);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001430
1431 ret = 0;
1432
1433xfer_exit:
1434 spin_unlock_irqrestore(&pl330->lock, flags);
1435
1436 return ret;
1437}
1438
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001439static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
Lars-Peter Clausen6079d382014-07-06 20:32:25 +02001440{
Javier Martinez Canillasb1e51d72014-07-19 03:21:47 +02001441 struct dma_pl330_chan *pch;
Lars-Peter Clausen6079d382014-07-06 20:32:25 +02001442 unsigned long flags;
1443
Javier Martinez Canillasb1e51d72014-07-19 03:21:47 +02001444 if (!desc)
1445 return;
1446
1447 pch = desc->pchan;
1448
Lars-Peter Clausen6079d382014-07-06 20:32:25 +02001449 /* If desc aborted */
1450 if (!pch)
1451 return;
1452
1453 spin_lock_irqsave(&pch->lock, flags);
1454
1455 desc->status = DONE;
1456
1457 spin_unlock_irqrestore(&pch->lock, flags);
1458
1459 tasklet_schedule(&pch->task);
1460}
1461
Boojin Kimb7d861d2011-12-26 18:49:52 +09001462static void pl330_dotask(unsigned long data)
1463{
1464 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001465 unsigned long flags;
1466 int i;
1467
1468 spin_lock_irqsave(&pl330->lock, flags);
1469
1470 /* The DMAC itself gone nuts */
1471 if (pl330->dmac_tbd.reset_dmac) {
1472 pl330->state = DYING;
1473 /* Reset the manager too */
1474 pl330->dmac_tbd.reset_mngr = true;
1475 /* Clear the reset flag */
1476 pl330->dmac_tbd.reset_dmac = false;
1477 }
1478
1479 if (pl330->dmac_tbd.reset_mngr) {
1480 _stop(pl330->manager);
1481 /* Reset all channels */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001482 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001483 /* Clear the reset flag */
1484 pl330->dmac_tbd.reset_mngr = false;
1485 }
1486
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001487 for (i = 0; i < pl330->pcfg.num_chan; i++) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001488
1489 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1490 struct pl330_thread *thrd = &pl330->channels[i];
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001491 void __iomem *regs = pl330->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001492 enum pl330_op_err err;
1493
1494 _stop(thrd);
1495
1496 if (readl(regs + FSC) & (1 << thrd->id))
1497 err = PL330_ERR_FAIL;
1498 else
1499 err = PL330_ERR_ABORT;
1500
1501 spin_unlock_irqrestore(&pl330->lock, flags);
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001502 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1503 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001504 spin_lock_irqsave(&pl330->lock, flags);
1505
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001506 thrd->req[0].desc = NULL;
1507 thrd->req[1].desc = NULL;
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001508 thrd->req_running = -1;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001509
1510 /* Clear the reset flag */
1511 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1512 }
1513 }
1514
1515 spin_unlock_irqrestore(&pl330->lock, flags);
1516
1517 return;
1518}
1519
1520/* Returns 1 if state was updated, 0 otherwise */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001521static int pl330_update(struct pl330_dmac *pl330)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001522{
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001523 struct dma_pl330_desc *descdone, *tmp;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001524 unsigned long flags;
1525 void __iomem *regs;
1526 u32 val;
1527 int id, ev, ret = 0;
1528
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001529 regs = pl330->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001530
1531 spin_lock_irqsave(&pl330->lock, flags);
1532
1533 val = readl(regs + FSM) & 0x1;
1534 if (val)
1535 pl330->dmac_tbd.reset_mngr = true;
1536 else
1537 pl330->dmac_tbd.reset_mngr = false;
1538
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001539 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001540 pl330->dmac_tbd.reset_chan |= val;
1541 if (val) {
1542 int i = 0;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001543 while (i < pl330->pcfg.num_chan) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001544 if (val & (1 << i)) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001545 dev_info(pl330->ddma.dev,
Boojin Kimb7d861d2011-12-26 18:49:52 +09001546 "Reset Channel-%d\t CS-%x FTC-%x\n",
1547 i, readl(regs + CS(i)),
1548 readl(regs + FTC(i)));
1549 _stop(&pl330->channels[i]);
1550 }
1551 i++;
1552 }
1553 }
1554
1555 /* Check which event happened i.e, thread notified */
1556 val = readl(regs + ES);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001557 if (pl330->pcfg.num_events < 32
1558 && val & ~((1 << pl330->pcfg.num_events) - 1)) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001559 pl330->dmac_tbd.reset_dmac = true;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001560 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1561 __LINE__);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001562 ret = 1;
1563 goto updt_exit;
1564 }
1565
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001566 for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001567 if (val & (1 << ev)) { /* Event occurred */
1568 struct pl330_thread *thrd;
1569 u32 inten = readl(regs + INTEN);
1570 int active;
1571
1572 /* Clear the event */
1573 if (inten & (1 << ev))
1574 writel(1 << ev, regs + INTCLR);
1575
1576 ret = 1;
1577
1578 id = pl330->events[ev];
1579
1580 thrd = &pl330->channels[id];
1581
1582 active = thrd->req_running;
1583 if (active == -1) /* Aborted */
1584 continue;
1585
Javi Merinofdec53d2012-06-13 15:07:00 +01001586 /* Detach the req */
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001587 descdone = thrd->req[active].desc;
1588 thrd->req[active].desc = NULL;
Javi Merinofdec53d2012-06-13 15:07:00 +01001589
Boojin Kimb7d861d2011-12-26 18:49:52 +09001590 /* Get going again ASAP */
1591 _start(thrd);
1592
1593 /* For now, just make a list of callbacks to be done */
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001594 list_add_tail(&descdone->rqd, &pl330->req_done);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001595 }
1596 }
1597
1598 /* Now that we are in no hurry, do the callbacks */
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001599 list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) {
1600 list_del(&descdone->rqd);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001601 spin_unlock_irqrestore(&pl330->lock, flags);
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001602 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001603 spin_lock_irqsave(&pl330->lock, flags);
1604 }
1605
1606updt_exit:
1607 spin_unlock_irqrestore(&pl330->lock, flags);
1608
1609 if (pl330->dmac_tbd.reset_dmac
1610 || pl330->dmac_tbd.reset_mngr
1611 || pl330->dmac_tbd.reset_chan) {
1612 ret = 1;
1613 tasklet_schedule(&pl330->tasks);
1614 }
1615
1616 return ret;
1617}
1618
Boojin Kimb7d861d2011-12-26 18:49:52 +09001619/* Reserve an event */
1620static inline int _alloc_event(struct pl330_thread *thrd)
1621{
1622 struct pl330_dmac *pl330 = thrd->dmac;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001623 int ev;
1624
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001625 for (ev = 0; ev < pl330->pcfg.num_events; ev++)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001626 if (pl330->events[ev] == -1) {
1627 pl330->events[ev] = thrd->id;
1628 return ev;
1629 }
1630
1631 return -1;
1632}
1633
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001634static bool _chan_ns(const struct pl330_dmac *pl330, int i)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001635{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001636 return pl330->pcfg.irq_ns & (1 << i);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001637}
1638
1639/* Upon success, returns IdentityToken for the
1640 * allocated channel, NULL otherwise.
1641 */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001642static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001643{
1644 struct pl330_thread *thrd = NULL;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001645 unsigned long flags;
1646 int chans, i;
1647
Boojin Kimb7d861d2011-12-26 18:49:52 +09001648 if (pl330->state == DYING)
1649 return NULL;
1650
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001651 chans = pl330->pcfg.num_chan;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001652
1653 spin_lock_irqsave(&pl330->lock, flags);
1654
1655 for (i = 0; i < chans; i++) {
1656 thrd = &pl330->channels[i];
1657 if ((thrd->free) && (!_manager_ns(thrd) ||
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001658 _chan_ns(pl330, i))) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001659 thrd->ev = _alloc_event(thrd);
1660 if (thrd->ev >= 0) {
1661 thrd->free = false;
1662 thrd->lstenq = 1;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001663 thrd->req[0].desc = NULL;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001664 thrd->req[1].desc = NULL;
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001665 thrd->req_running = -1;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001666 break;
1667 }
1668 }
1669 thrd = NULL;
1670 }
1671
1672 spin_unlock_irqrestore(&pl330->lock, flags);
1673
1674 return thrd;
1675}
1676
1677/* Release an event */
1678static inline void _free_event(struct pl330_thread *thrd, int ev)
1679{
1680 struct pl330_dmac *pl330 = thrd->dmac;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001681
1682 /* If the event is valid and was held by the thread */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001683 if (ev >= 0 && ev < pl330->pcfg.num_events
Boojin Kimb7d861d2011-12-26 18:49:52 +09001684 && pl330->events[ev] == thrd->id)
1685 pl330->events[ev] = -1;
1686}
1687
Lars-Peter Clausen65ad6062014-07-06 20:32:26 +02001688static void pl330_release_channel(struct pl330_thread *thrd)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001689{
Boojin Kimb7d861d2011-12-26 18:49:52 +09001690 struct pl330_dmac *pl330;
1691 unsigned long flags;
1692
1693 if (!thrd || thrd->free)
1694 return;
1695
1696 _stop(thrd);
1697
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001698 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1699 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001700
1701 pl330 = thrd->dmac;
1702
1703 spin_lock_irqsave(&pl330->lock, flags);
1704 _free_event(thrd, thrd->ev);
1705 thrd->free = true;
1706 spin_unlock_irqrestore(&pl330->lock, flags);
1707}
1708
1709/* Initialize the structure for PL330 configuration, that can be used
1710 * by the client driver the make best use of the DMAC
1711 */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001712static void read_dmac_config(struct pl330_dmac *pl330)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001713{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001714 void __iomem *regs = pl330->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001715 u32 val;
1716
1717 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1718 val &= CRD_DATA_WIDTH_MASK;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001719 pl330->pcfg.data_bus_width = 8 * (1 << val);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001720
1721 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1722 val &= CRD_DATA_BUFF_MASK;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001723 pl330->pcfg.data_buf_dep = val + 1;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001724
1725 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1726 val &= CR0_NUM_CHANS_MASK;
1727 val += 1;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001728 pl330->pcfg.num_chan = val;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001729
1730 val = readl(regs + CR0);
1731 if (val & CR0_PERIPH_REQ_SET) {
1732 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1733 val += 1;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001734 pl330->pcfg.num_peri = val;
1735 pl330->pcfg.peri_ns = readl(regs + CR4);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001736 } else {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001737 pl330->pcfg.num_peri = 0;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001738 }
1739
1740 val = readl(regs + CR0);
1741 if (val & CR0_BOOT_MAN_NS)
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001742 pl330->pcfg.mode |= DMAC_MODE_NS;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001743 else
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001744 pl330->pcfg.mode &= ~DMAC_MODE_NS;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001745
1746 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1747 val &= CR0_NUM_EVENTS_MASK;
1748 val += 1;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001749 pl330->pcfg.num_events = val;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001750
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001751 pl330->pcfg.irq_ns = readl(regs + CR3);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001752}
1753
1754static inline void _reset_thread(struct pl330_thread *thrd)
1755{
1756 struct pl330_dmac *pl330 = thrd->dmac;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001757
1758 thrd->req[0].mc_cpu = pl330->mcode_cpu
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001759 + (thrd->id * pl330->mcbufsz);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001760 thrd->req[0].mc_bus = pl330->mcode_bus
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001761 + (thrd->id * pl330->mcbufsz);
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001762 thrd->req[0].desc = NULL;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001763
1764 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001765 + pl330->mcbufsz / 2;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001766 thrd->req[1].mc_bus = thrd->req[0].mc_bus
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001767 + pl330->mcbufsz / 2;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001768 thrd->req[1].desc = NULL;
Lars-Peter Clausen8ed30a12014-07-06 20:32:31 +02001769
1770 thrd->req_running = -1;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001771}
1772
1773static int dmac_alloc_threads(struct pl330_dmac *pl330)
1774{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001775 int chans = pl330->pcfg.num_chan;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001776 struct pl330_thread *thrd;
1777 int i;
1778
1779 /* Allocate 1 Manager and 'chans' Channel threads */
1780 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
1781 GFP_KERNEL);
1782 if (!pl330->channels)
1783 return -ENOMEM;
1784
1785 /* Init Channel threads */
1786 for (i = 0; i < chans; i++) {
1787 thrd = &pl330->channels[i];
1788 thrd->id = i;
1789 thrd->dmac = pl330;
1790 _reset_thread(thrd);
1791 thrd->free = true;
1792 }
1793
1794 /* MANAGER is indexed at the end */
1795 thrd = &pl330->channels[chans];
1796 thrd->id = chans;
1797 thrd->dmac = pl330;
1798 thrd->free = false;
1799 pl330->manager = thrd;
1800
1801 return 0;
1802}
1803
1804static int dmac_alloc_resources(struct pl330_dmac *pl330)
1805{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001806 int chans = pl330->pcfg.num_chan;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001807 int ret;
1808
1809 /*
1810 * Alloc MicroCode buffer for 'chans' Channel threads.
1811 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1812 */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001813 pl330->mcode_cpu = dma_alloc_coherent(pl330->ddma.dev,
1814 chans * pl330->mcbufsz,
Boojin Kimb7d861d2011-12-26 18:49:52 +09001815 &pl330->mcode_bus, GFP_KERNEL);
1816 if (!pl330->mcode_cpu) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001817 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
Boojin Kimb7d861d2011-12-26 18:49:52 +09001818 __func__, __LINE__);
1819 return -ENOMEM;
1820 }
1821
1822 ret = dmac_alloc_threads(pl330);
1823 if (ret) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001824 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
Boojin Kimb7d861d2011-12-26 18:49:52 +09001825 __func__, __LINE__);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001826 dma_free_coherent(pl330->ddma.dev,
1827 chans * pl330->mcbufsz,
Boojin Kimb7d861d2011-12-26 18:49:52 +09001828 pl330->mcode_cpu, pl330->mcode_bus);
1829 return ret;
1830 }
1831
1832 return 0;
1833}
1834
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001835static int pl330_add(struct pl330_dmac *pl330)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001836{
Boojin Kimb7d861d2011-12-26 18:49:52 +09001837 void __iomem *regs;
1838 int i, ret;
1839
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001840 regs = pl330->base;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001841
1842 /* Check if we can handle this DMAC */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001843 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1844 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1845 pl330->pcfg.periph_id);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001846 return -EINVAL;
1847 }
1848
1849 /* Read the configuration of the DMAC */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001850 read_dmac_config(pl330);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001851
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001852 if (pl330->pcfg.num_events == 0) {
1853 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
Boojin Kimb7d861d2011-12-26 18:49:52 +09001854 __func__, __LINE__);
1855 return -EINVAL;
1856 }
1857
Boojin Kimb7d861d2011-12-26 18:49:52 +09001858 spin_lock_init(&pl330->lock);
1859
1860 INIT_LIST_HEAD(&pl330->req_done);
1861
1862 /* Use default MC buffer size if not provided */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001863 if (!pl330->mcbufsz)
1864 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001865
1866 /* Mark all events as free */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001867 for (i = 0; i < pl330->pcfg.num_events; i++)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001868 pl330->events[i] = -1;
1869
1870 /* Allocate resources needed by the DMAC */
1871 ret = dmac_alloc_resources(pl330);
1872 if (ret) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001873 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
Boojin Kimb7d861d2011-12-26 18:49:52 +09001874 return ret;
1875 }
1876
1877 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
1878
1879 pl330->state = INIT;
1880
1881 return 0;
1882}
1883
1884static int dmac_free_threads(struct pl330_dmac *pl330)
1885{
Boojin Kimb7d861d2011-12-26 18:49:52 +09001886 struct pl330_thread *thrd;
1887 int i;
1888
1889 /* Release Channel threads */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001890 for (i = 0; i < pl330->pcfg.num_chan; i++) {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001891 thrd = &pl330->channels[i];
Lars-Peter Clausen65ad6062014-07-06 20:32:26 +02001892 pl330_release_channel(thrd);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001893 }
1894
1895 /* Free memory */
1896 kfree(pl330->channels);
1897
1898 return 0;
1899}
1900
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001901static void pl330_del(struct pl330_dmac *pl330)
Boojin Kimb7d861d2011-12-26 18:49:52 +09001902{
Boojin Kimb7d861d2011-12-26 18:49:52 +09001903 pl330->state = UNINIT;
1904
1905 tasklet_kill(&pl330->tasks);
1906
1907 /* Free DMAC resources */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001908 dmac_free_threads(pl330);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001909
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001910 dma_free_coherent(pl330->ddma.dev,
1911 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
1912 pl330->mcode_bus);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001913}
1914
Thomas Abraham3e2ec132011-10-24 11:43:02 +02001915/* forward declaration */
1916static struct amba_driver pl330_driver;
1917
Jassi Brarb3040e42010-05-23 20:28:19 -07001918static inline struct dma_pl330_chan *
1919to_pchan(struct dma_chan *ch)
1920{
1921 if (!ch)
1922 return NULL;
1923
1924 return container_of(ch, struct dma_pl330_chan, chan);
1925}
1926
1927static inline struct dma_pl330_desc *
1928to_desc(struct dma_async_tx_descriptor *tx)
1929{
1930 return container_of(tx, struct dma_pl330_desc, txd);
1931}
1932
Jassi Brarb3040e42010-05-23 20:28:19 -07001933static inline void fill_queue(struct dma_pl330_chan *pch)
1934{
1935 struct dma_pl330_desc *desc;
1936 int ret;
1937
1938 list_for_each_entry(desc, &pch->work_list, node) {
1939
1940 /* If already submitted */
1941 if (desc->status == BUSY)
Jassi Brar30fb9802013-02-13 16:13:14 +05301942 continue;
Jassi Brarb3040e42010-05-23 20:28:19 -07001943
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02001944 ret = pl330_submit_req(pch->thread, desc);
Jassi Brarb3040e42010-05-23 20:28:19 -07001945 if (!ret) {
1946 desc->status = BUSY;
Jassi Brarb3040e42010-05-23 20:28:19 -07001947 } else if (ret == -EAGAIN) {
1948 /* QFull or DMAC Dying */
1949 break;
1950 } else {
1951 /* Unacceptable request */
1952 desc->status = DONE;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02001953 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
Jassi Brarb3040e42010-05-23 20:28:19 -07001954 __func__, __LINE__, desc->txd.cookie);
1955 tasklet_schedule(&pch->task);
1956 }
1957 }
1958}
1959
1960static void pl330_tasklet(unsigned long data)
1961{
1962 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
1963 struct dma_pl330_desc *desc, *_dt;
1964 unsigned long flags;
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01001965 bool power_down = false;
Jassi Brarb3040e42010-05-23 20:28:19 -07001966
1967 spin_lock_irqsave(&pch->lock, flags);
1968
1969 /* Pick up ripe tomatoes */
1970 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
1971 if (desc->status == DONE) {
Tushar Behera30c1dc02012-05-23 16:47:31 +05301972 if (!pch->cyclic)
Vinod Kouleab21582012-05-11 11:24:41 +05301973 dma_cookie_complete(&desc->txd);
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02001974 list_move_tail(&desc->node, &pch->completed_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07001975 }
1976
1977 /* Try to submit a req imm. next to the last completed cookie */
1978 fill_queue(pch);
1979
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01001980 if (list_empty(&pch->work_list)) {
1981 spin_lock(&pch->thread->dmac->lock);
1982 _stop(pch->thread);
1983 spin_unlock(&pch->thread->dmac->lock);
1984 power_down = true;
1985 } else {
1986 /* Make sure the PL330 Channel thread is active */
1987 spin_lock(&pch->thread->dmac->lock);
1988 _start(pch->thread);
1989 spin_unlock(&pch->thread->dmac->lock);
1990 }
Jassi Brarb3040e42010-05-23 20:28:19 -07001991
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02001992 while (!list_empty(&pch->completed_list)) {
1993 dma_async_tx_callback callback;
1994 void *callback_param;
Jassi Brarb3040e42010-05-23 20:28:19 -07001995
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02001996 desc = list_first_entry(&pch->completed_list,
1997 struct dma_pl330_desc, node);
1998
1999 callback = desc->txd.callback;
2000 callback_param = desc->txd.callback_param;
2001
2002 if (pch->cyclic) {
2003 desc->status = PREP;
2004 list_move_tail(&desc->node, &pch->work_list);
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002005 if (power_down) {
2006 spin_lock(&pch->thread->dmac->lock);
2007 _start(pch->thread);
2008 spin_unlock(&pch->thread->dmac->lock);
2009 power_down = false;
2010 }
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002011 } else {
2012 desc->status = FREE;
2013 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2014 }
2015
Dan Williamsd38a8c62013-10-18 19:35:23 +02002016 dma_descriptor_unmap(&desc->txd);
2017
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002018 if (callback) {
2019 spin_unlock_irqrestore(&pch->lock, flags);
2020 callback(callback_param);
2021 spin_lock_irqsave(&pch->lock, flags);
2022 }
2023 }
2024 spin_unlock_irqrestore(&pch->lock, flags);
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002025
2026 /* If work list empty, power down */
2027 if (power_down) {
2028 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2029 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2030 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002031}
2032
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002033bool pl330_filter(struct dma_chan *chan, void *param)
2034{
Thomas Abrahamcd072512011-10-24 11:43:11 +02002035 u8 *peri_id;
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002036
2037 if (chan->device->dev->driver != &pl330_driver.drv)
2038 return false;
2039
Thomas Abrahamcd072512011-10-24 11:43:11 +02002040 peri_id = chan->private;
Dan Carpenter2f986ec2013-11-08 12:51:16 +03002041 return *peri_id == (unsigned long)param;
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002042}
2043EXPORT_SYMBOL(pl330_filter);
2044
Padmavathi Vennaa80258f2013-02-14 09:10:06 +05302045static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2046 struct of_dma *ofdma)
2047{
2048 int count = dma_spec->args_count;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002049 struct pl330_dmac *pl330 = ofdma->of_dma_data;
Lars-Peter Clausen70cbb162014-01-11 20:08:39 +01002050 unsigned int chan_id;
Padmavathi Vennaa80258f2013-02-14 09:10:06 +05302051
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002052 if (!pl330)
2053 return NULL;
2054
Padmavathi Vennaa80258f2013-02-14 09:10:06 +05302055 if (count != 1)
2056 return NULL;
2057
Lars-Peter Clausen70cbb162014-01-11 20:08:39 +01002058 chan_id = dma_spec->args[0];
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002059 if (chan_id >= pl330->num_peripherals)
Lars-Peter Clausen70cbb162014-01-11 20:08:39 +01002060 return NULL;
Padmavathi Vennaa80258f2013-02-14 09:10:06 +05302061
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002062 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
Padmavathi Vennaa80258f2013-02-14 09:10:06 +05302063}
2064
Jassi Brarb3040e42010-05-23 20:28:19 -07002065static int pl330_alloc_chan_resources(struct dma_chan *chan)
2066{
2067 struct dma_pl330_chan *pch = to_pchan(chan);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002068 struct pl330_dmac *pl330 = pch->dmac;
Jassi Brarb3040e42010-05-23 20:28:19 -07002069 unsigned long flags;
2070
2071 spin_lock_irqsave(&pch->lock, flags);
2072
Russell King - ARM Linuxd3ee98cdc2012-03-06 22:35:47 +00002073 dma_cookie_init(chan);
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002074 pch->cyclic = false;
Jassi Brarb3040e42010-05-23 20:28:19 -07002075
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002076 pch->thread = pl330_request_channel(pl330);
Lars-Peter Clausen65ad6062014-07-06 20:32:26 +02002077 if (!pch->thread) {
Jassi Brarb3040e42010-05-23 20:28:19 -07002078 spin_unlock_irqrestore(&pch->lock, flags);
Inderpal Singh02747882012-09-17 09:57:45 +05302079 return -ENOMEM;
Jassi Brarb3040e42010-05-23 20:28:19 -07002080 }
2081
2082 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2083
2084 spin_unlock_irqrestore(&pch->lock, flags);
2085
2086 return 1;
2087}
2088
2089static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg)
2090{
2091 struct dma_pl330_chan *pch = to_pchan(chan);
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002092 struct dma_pl330_desc *desc;
Jassi Brarb3040e42010-05-23 20:28:19 -07002093 unsigned long flags;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002094 struct pl330_dmac *pl330 = pch->dmac;
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002095 struct dma_slave_config *slave_config;
Boojin Kimae43b882011-09-02 09:44:32 +09002096 LIST_HEAD(list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002097
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002098 switch (cmd) {
2099 case DMA_TERMINATE_ALL:
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002100 pm_runtime_get_sync(pl330->ddma.dev);
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002101 spin_lock_irqsave(&pch->lock, flags);
2102
Lars-Peter Clausenc26939e2014-07-06 20:32:32 +02002103 spin_lock(&pl330->lock);
2104 _stop(pch->thread);
2105 spin_unlock(&pl330->lock);
2106
2107 pch->thread->req[0].desc = NULL;
2108 pch->thread->req[1].desc = NULL;
2109 pch->thread->req_running = -1;
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002110
2111 /* Mark all desc done */
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002112 list_for_each_entry(desc, &pch->submitted_list, node) {
2113 desc->status = FREE;
2114 dma_cookie_complete(&desc->txd);
2115 }
2116
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002117 list_for_each_entry(desc, &pch->work_list , node) {
2118 desc->status = FREE;
2119 dma_cookie_complete(&desc->txd);
Boojin Kimae43b882011-09-02 09:44:32 +09002120 }
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002121
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002122 list_for_each_entry(desc, &pch->completed_list , node) {
2123 desc->status = FREE;
2124 dma_cookie_complete(&desc->txd);
2125 }
2126
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002127 if (!list_empty(&pch->work_list))
2128 pm_runtime_put(pl330->ddma.dev);
2129
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002130 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2131 list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2132 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002133 spin_unlock_irqrestore(&pch->lock, flags);
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002134 pm_runtime_mark_last_busy(pl330->ddma.dev);
2135 pm_runtime_put_autosuspend(pl330->ddma.dev);
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002136 break;
2137 case DMA_SLAVE_CONFIG:
2138 slave_config = (struct dma_slave_config *)arg;
2139
Vinod Kouldb8196d2011-10-13 22:34:23 +05302140 if (slave_config->direction == DMA_MEM_TO_DEV) {
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002141 if (slave_config->dst_addr)
2142 pch->fifo_addr = slave_config->dst_addr;
2143 if (slave_config->dst_addr_width)
2144 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2145 if (slave_config->dst_maxburst)
2146 pch->burst_len = slave_config->dst_maxburst;
Vinod Kouldb8196d2011-10-13 22:34:23 +05302147 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002148 if (slave_config->src_addr)
2149 pch->fifo_addr = slave_config->src_addr;
2150 if (slave_config->src_addr_width)
2151 pch->burst_sz = __ffs(slave_config->src_addr_width);
2152 if (slave_config->src_maxburst)
2153 pch->burst_len = slave_config->src_maxburst;
2154 }
2155 break;
2156 default:
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002157 dev_err(pch->dmac->ddma.dev, "Not supported command.\n");
Jassi Brarb3040e42010-05-23 20:28:19 -07002158 return -ENXIO;
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002159 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002160
2161 return 0;
2162}
2163
2164static void pl330_free_chan_resources(struct dma_chan *chan)
2165{
2166 struct dma_pl330_chan *pch = to_pchan(chan);
2167 unsigned long flags;
2168
Jassi Brarb3040e42010-05-23 20:28:19 -07002169 tasklet_kill(&pch->task);
2170
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002171 pm_runtime_get_sync(pch->dmac->ddma.dev);
Bartlomiej Zolnierkiewiczda331ba2013-07-03 15:00:43 -07002172 spin_lock_irqsave(&pch->lock, flags);
2173
Lars-Peter Clausen65ad6062014-07-06 20:32:26 +02002174 pl330_release_channel(pch->thread);
2175 pch->thread = NULL;
Jassi Brarb3040e42010-05-23 20:28:19 -07002176
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002177 if (pch->cyclic)
2178 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2179
Jassi Brarb3040e42010-05-23 20:28:19 -07002180 spin_unlock_irqrestore(&pch->lock, flags);
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002181 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2182 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
Jassi Brarb3040e42010-05-23 20:28:19 -07002183}
2184
2185static enum dma_status
2186pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2187 struct dma_tx_state *txstate)
2188{
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +00002189 return dma_cookie_status(chan, cookie, txstate);
Jassi Brarb3040e42010-05-23 20:28:19 -07002190}
2191
2192static void pl330_issue_pending(struct dma_chan *chan)
2193{
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002194 struct dma_pl330_chan *pch = to_pchan(chan);
2195 unsigned long flags;
2196
2197 spin_lock_irqsave(&pch->lock, flags);
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002198 if (list_empty(&pch->work_list)) {
2199 /*
2200 * Warn on nothing pending. Empty submitted_list may
2201 * break our pm_runtime usage counter as it is
2202 * updated on work_list emptiness status.
2203 */
2204 WARN_ON(list_empty(&pch->submitted_list));
2205 pm_runtime_get_sync(pch->dmac->ddma.dev);
2206 }
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002207 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2208 spin_unlock_irqrestore(&pch->lock, flags);
2209
2210 pl330_tasklet((unsigned long)pch);
Jassi Brarb3040e42010-05-23 20:28:19 -07002211}
2212
2213/*
2214 * We returned the last one of the circular list of descriptor(s)
2215 * from prep_xxx, so the argument to submit corresponds to the last
2216 * descriptor of the list.
2217 */
2218static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2219{
2220 struct dma_pl330_desc *desc, *last = to_desc(tx);
2221 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2222 dma_cookie_t cookie;
2223 unsigned long flags;
2224
2225 spin_lock_irqsave(&pch->lock, flags);
2226
2227 /* Assign cookies to all nodes */
Jassi Brarb3040e42010-05-23 20:28:19 -07002228 while (!list_empty(&last->node)) {
2229 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002230 if (pch->cyclic) {
2231 desc->txd.callback = last->txd.callback;
2232 desc->txd.callback_param = last->txd.callback_param;
2233 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002234
Russell King - ARM Linux884485e2012-03-06 22:34:46 +00002235 dma_cookie_assign(&desc->txd);
Jassi Brarb3040e42010-05-23 20:28:19 -07002236
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002237 list_move_tail(&desc->node, &pch->submitted_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002238 }
2239
Russell King - ARM Linux884485e2012-03-06 22:34:46 +00002240 cookie = dma_cookie_assign(&last->txd);
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002241 list_add_tail(&last->node, &pch->submitted_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002242 spin_unlock_irqrestore(&pch->lock, flags);
2243
2244 return cookie;
2245}
2246
2247static inline void _init_desc(struct dma_pl330_desc *desc)
2248{
Jassi Brarb3040e42010-05-23 20:28:19 -07002249 desc->rqcfg.swap = SWAP_NO;
Lars-Peter Clausenf0564c72014-07-06 20:32:19 +02002250 desc->rqcfg.scctl = CCTRL0;
2251 desc->rqcfg.dcctl = CCTRL0;
Jassi Brarb3040e42010-05-23 20:28:19 -07002252 desc->txd.tx_submit = pl330_tx_submit;
2253
2254 INIT_LIST_HEAD(&desc->node);
2255}
2256
2257/* Returns the number of descriptors added to the DMAC pool */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002258static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count)
Jassi Brarb3040e42010-05-23 20:28:19 -07002259{
2260 struct dma_pl330_desc *desc;
2261 unsigned long flags;
2262 int i;
2263
Will Deacon0baf8f62013-12-02 18:01:30 +00002264 desc = kcalloc(count, sizeof(*desc), flg);
Jassi Brarb3040e42010-05-23 20:28:19 -07002265 if (!desc)
2266 return 0;
2267
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002268 spin_lock_irqsave(&pl330->pool_lock, flags);
Jassi Brarb3040e42010-05-23 20:28:19 -07002269
2270 for (i = 0; i < count; i++) {
2271 _init_desc(&desc[i]);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002272 list_add_tail(&desc[i].node, &pl330->desc_pool);
Jassi Brarb3040e42010-05-23 20:28:19 -07002273 }
2274
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002275 spin_unlock_irqrestore(&pl330->pool_lock, flags);
Jassi Brarb3040e42010-05-23 20:28:19 -07002276
2277 return count;
2278}
2279
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002280static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330)
Jassi Brarb3040e42010-05-23 20:28:19 -07002281{
2282 struct dma_pl330_desc *desc = NULL;
2283 unsigned long flags;
2284
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002285 spin_lock_irqsave(&pl330->pool_lock, flags);
Jassi Brarb3040e42010-05-23 20:28:19 -07002286
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002287 if (!list_empty(&pl330->desc_pool)) {
2288 desc = list_entry(pl330->desc_pool.next,
Jassi Brarb3040e42010-05-23 20:28:19 -07002289 struct dma_pl330_desc, node);
2290
2291 list_del_init(&desc->node);
2292
2293 desc->status = PREP;
2294 desc->txd.callback = NULL;
2295 }
2296
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002297 spin_unlock_irqrestore(&pl330->pool_lock, flags);
Jassi Brarb3040e42010-05-23 20:28:19 -07002298
2299 return desc;
2300}
2301
2302static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2303{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002304 struct pl330_dmac *pl330 = pch->dmac;
Thomas Abrahamcd072512011-10-24 11:43:11 +02002305 u8 *peri_id = pch->chan.private;
Jassi Brarb3040e42010-05-23 20:28:19 -07002306 struct dma_pl330_desc *desc;
2307
2308 /* Pluck one desc from the pool of DMAC */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002309 desc = pluck_desc(pl330);
Jassi Brarb3040e42010-05-23 20:28:19 -07002310
2311 /* If the DMAC pool is empty, alloc new */
2312 if (!desc) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002313 if (!add_desc(pl330, GFP_ATOMIC, 1))
Jassi Brarb3040e42010-05-23 20:28:19 -07002314 return NULL;
2315
2316 /* Try again */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002317 desc = pluck_desc(pl330);
Jassi Brarb3040e42010-05-23 20:28:19 -07002318 if (!desc) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002319 dev_err(pch->dmac->ddma.dev,
Jassi Brarb3040e42010-05-23 20:28:19 -07002320 "%s:%d ALERT!\n", __func__, __LINE__);
2321 return NULL;
2322 }
2323 }
2324
2325 /* Initialize the descriptor */
2326 desc->pchan = pch;
2327 desc->txd.cookie = 0;
2328 async_tx_ack(&desc->txd);
2329
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02002330 desc->peri = peri_id ? pch->chan.chan_id : 0;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002331 desc->rqcfg.pcfg = &pch->dmac->pcfg;
Jassi Brarb3040e42010-05-23 20:28:19 -07002332
2333 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2334
2335 return desc;
2336}
2337
2338static inline void fill_px(struct pl330_xfer *px,
2339 dma_addr_t dst, dma_addr_t src, size_t len)
2340{
Jassi Brarb3040e42010-05-23 20:28:19 -07002341 px->bytes = len;
2342 px->dst_addr = dst;
2343 px->src_addr = src;
2344}
2345
2346static struct dma_pl330_desc *
2347__pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2348 dma_addr_t src, size_t len)
2349{
2350 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2351
2352 if (!desc) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002353 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
Jassi Brarb3040e42010-05-23 20:28:19 -07002354 __func__, __LINE__);
2355 return NULL;
2356 }
2357
2358 /*
2359 * Ideally we should lookout for reqs bigger than
2360 * those that can be programmed with 256 bytes of
2361 * MC buffer, but considering a req size is seldom
2362 * going to be word-unaligned and more than 200MB,
2363 * we take it easy.
2364 * Also, should the limit is reached we'd rather
2365 * have the platform increase MC buffer size than
2366 * complicating this API driver.
2367 */
2368 fill_px(&desc->px, dst, src, len);
2369
2370 return desc;
2371}
2372
2373/* Call after fixing burst size */
2374static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2375{
2376 struct dma_pl330_chan *pch = desc->pchan;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002377 struct pl330_dmac *pl330 = pch->dmac;
Jassi Brarb3040e42010-05-23 20:28:19 -07002378 int burst_len;
2379
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002380 burst_len = pl330->pcfg.data_bus_width / 8;
2381 burst_len *= pl330->pcfg.data_buf_dep;
Jassi Brarb3040e42010-05-23 20:28:19 -07002382 burst_len >>= desc->rqcfg.brst_size;
2383
2384 /* src/dst_burst_len can't be more than 16 */
2385 if (burst_len > 16)
2386 burst_len = 16;
2387
2388 while (burst_len > 1) {
2389 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2390 break;
2391 burst_len--;
2392 }
2393
2394 return burst_len;
2395}
2396
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002397static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2398 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -05002399 size_t period_len, enum dma_transfer_direction direction,
Laurent Pinchart31c1e5a2014-08-01 12:20:10 +02002400 unsigned long flags)
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002401{
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002402 struct dma_pl330_desc *desc = NULL, *first = NULL;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002403 struct dma_pl330_chan *pch = to_pchan(chan);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002404 struct pl330_dmac *pl330 = pch->dmac;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002405 unsigned int i;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002406 dma_addr_t dst;
2407 dma_addr_t src;
2408
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002409 if (len % period_len != 0)
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002410 return NULL;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002411
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002412 if (!is_slave_direction(direction)) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002413 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002414 __func__, __LINE__);
2415 return NULL;
2416 }
2417
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002418 for (i = 0; i < len / period_len; i++) {
2419 desc = pl330_get_desc(pch);
2420 if (!desc) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002421 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002422 __func__, __LINE__);
2423
2424 if (!first)
2425 return NULL;
2426
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002427 spin_lock_irqsave(&pl330->pool_lock, flags);
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002428
2429 while (!list_empty(&first->node)) {
2430 desc = list_entry(first->node.next,
2431 struct dma_pl330_desc, node);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002432 list_move_tail(&desc->node, &pl330->desc_pool);
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002433 }
2434
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002435 list_move_tail(&first->node, &pl330->desc_pool);
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002436
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002437 spin_unlock_irqrestore(&pl330->pool_lock, flags);
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002438
2439 return NULL;
2440 }
2441
2442 switch (direction) {
2443 case DMA_MEM_TO_DEV:
2444 desc->rqcfg.src_inc = 1;
2445 desc->rqcfg.dst_inc = 0;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002446 src = dma_addr;
2447 dst = pch->fifo_addr;
2448 break;
2449 case DMA_DEV_TO_MEM:
2450 desc->rqcfg.src_inc = 0;
2451 desc->rqcfg.dst_inc = 1;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002452 src = pch->fifo_addr;
2453 dst = dma_addr;
2454 break;
2455 default:
2456 break;
2457 }
2458
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02002459 desc->rqtype = direction;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002460 desc->rqcfg.brst_size = pch->burst_sz;
2461 desc->rqcfg.brst_len = 1;
2462 fill_px(&desc->px, dst, src, period_len);
2463
2464 if (!first)
2465 first = desc;
2466 else
2467 list_add_tail(&desc->node, &first->node);
2468
2469 dma_addr += period_len;
2470 }
2471
2472 if (!desc)
2473 return NULL;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002474
2475 pch->cyclic = true;
Lars-Peter Clausenfc514462013-07-23 10:24:50 +02002476 desc->txd.flags = flags;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002477
2478 return &desc->txd;
2479}
2480
Jassi Brarb3040e42010-05-23 20:28:19 -07002481static struct dma_async_tx_descriptor *
2482pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2483 dma_addr_t src, size_t len, unsigned long flags)
2484{
2485 struct dma_pl330_desc *desc;
2486 struct dma_pl330_chan *pch = to_pchan(chan);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002487 struct pl330_dmac *pl330 = pch->dmac;
Jassi Brarb3040e42010-05-23 20:28:19 -07002488 int burst;
2489
Rob Herring4e0e6102011-07-25 16:05:04 -05002490 if (unlikely(!pch || !len))
Jassi Brarb3040e42010-05-23 20:28:19 -07002491 return NULL;
2492
Jassi Brarb3040e42010-05-23 20:28:19 -07002493 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2494 if (!desc)
2495 return NULL;
2496
2497 desc->rqcfg.src_inc = 1;
2498 desc->rqcfg.dst_inc = 1;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02002499 desc->rqtype = DMA_MEM_TO_MEM;
Jassi Brarb3040e42010-05-23 20:28:19 -07002500
2501 /* Select max possible burst size */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002502 burst = pl330->pcfg.data_bus_width / 8;
Jassi Brarb3040e42010-05-23 20:28:19 -07002503
2504 while (burst > 1) {
2505 if (!(len % burst))
2506 break;
2507 burst /= 2;
2508 }
2509
2510 desc->rqcfg.brst_size = 0;
2511 while (burst != (1 << desc->rqcfg.brst_size))
2512 desc->rqcfg.brst_size++;
2513
2514 desc->rqcfg.brst_len = get_burst_len(desc, len);
2515
2516 desc->txd.flags = flags;
2517
2518 return &desc->txd;
2519}
2520
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002521static void __pl330_giveback_desc(struct pl330_dmac *pl330,
Chanho Park52a9d172013-08-09 20:11:33 +09002522 struct dma_pl330_desc *first)
2523{
2524 unsigned long flags;
2525 struct dma_pl330_desc *desc;
2526
2527 if (!first)
2528 return;
2529
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002530 spin_lock_irqsave(&pl330->pool_lock, flags);
Chanho Park52a9d172013-08-09 20:11:33 +09002531
2532 while (!list_empty(&first->node)) {
2533 desc = list_entry(first->node.next,
2534 struct dma_pl330_desc, node);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002535 list_move_tail(&desc->node, &pl330->desc_pool);
Chanho Park52a9d172013-08-09 20:11:33 +09002536 }
2537
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002538 list_move_tail(&first->node, &pl330->desc_pool);
Chanho Park52a9d172013-08-09 20:11:33 +09002539
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002540 spin_unlock_irqrestore(&pl330->pool_lock, flags);
Chanho Park52a9d172013-08-09 20:11:33 +09002541}
2542
Jassi Brarb3040e42010-05-23 20:28:19 -07002543static struct dma_async_tx_descriptor *
2544pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +05302545 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -05002546 unsigned long flg, void *context)
Jassi Brarb3040e42010-05-23 20:28:19 -07002547{
2548 struct dma_pl330_desc *first, *desc = NULL;
2549 struct dma_pl330_chan *pch = to_pchan(chan);
Jassi Brarb3040e42010-05-23 20:28:19 -07002550 struct scatterlist *sg;
Boojin Kim1b9bb712011-09-02 09:44:30 +09002551 int i;
Jassi Brarb3040e42010-05-23 20:28:19 -07002552 dma_addr_t addr;
2553
Thomas Abrahamcd072512011-10-24 11:43:11 +02002554 if (unlikely(!pch || !sgl || !sg_len))
Jassi Brarb3040e42010-05-23 20:28:19 -07002555 return NULL;
2556
Boojin Kim1b9bb712011-09-02 09:44:30 +09002557 addr = pch->fifo_addr;
Jassi Brarb3040e42010-05-23 20:28:19 -07002558
2559 first = NULL;
2560
2561 for_each_sg(sgl, sg, sg_len, i) {
2562
2563 desc = pl330_get_desc(pch);
2564 if (!desc) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002565 struct pl330_dmac *pl330 = pch->dmac;
Jassi Brarb3040e42010-05-23 20:28:19 -07002566
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002567 dev_err(pch->dmac->ddma.dev,
Jassi Brarb3040e42010-05-23 20:28:19 -07002568 "%s:%d Unable to fetch desc\n",
2569 __func__, __LINE__);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002570 __pl330_giveback_desc(pl330, first);
Jassi Brarb3040e42010-05-23 20:28:19 -07002571
2572 return NULL;
2573 }
2574
2575 if (!first)
2576 first = desc;
2577 else
2578 list_add_tail(&desc->node, &first->node);
2579
Vinod Kouldb8196d2011-10-13 22:34:23 +05302580 if (direction == DMA_MEM_TO_DEV) {
Jassi Brarb3040e42010-05-23 20:28:19 -07002581 desc->rqcfg.src_inc = 1;
2582 desc->rqcfg.dst_inc = 0;
2583 fill_px(&desc->px,
2584 addr, sg_dma_address(sg), sg_dma_len(sg));
2585 } else {
2586 desc->rqcfg.src_inc = 0;
2587 desc->rqcfg.dst_inc = 1;
2588 fill_px(&desc->px,
2589 sg_dma_address(sg), addr, sg_dma_len(sg));
2590 }
2591
Boojin Kim1b9bb712011-09-02 09:44:30 +09002592 desc->rqcfg.brst_size = pch->burst_sz;
Jassi Brarb3040e42010-05-23 20:28:19 -07002593 desc->rqcfg.brst_len = 1;
Lars-Peter Clausen9dc5a312014-07-06 20:32:30 +02002594 desc->rqtype = direction;
Jassi Brarb3040e42010-05-23 20:28:19 -07002595 }
2596
2597 /* Return the last desc in the chain */
2598 desc->txd.flags = flg;
2599 return &desc->txd;
2600}
2601
2602static irqreturn_t pl330_irq_handler(int irq, void *data)
2603{
2604 if (pl330_update(data))
2605 return IRQ_HANDLED;
2606 else
2607 return IRQ_NONE;
2608}
2609
Lars-Peter Clausenca38ff12013-07-15 17:53:08 +02002610#define PL330_DMA_BUSWIDTHS \
2611 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2612 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2613 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2614 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2615 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2616
2617static int pl330_dma_device_slave_caps(struct dma_chan *dchan,
2618 struct dma_slave_caps *caps)
2619{
2620 caps->src_addr_widths = PL330_DMA_BUSWIDTHS;
2621 caps->dstn_addr_widths = PL330_DMA_BUSWIDTHS;
2622 caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2623 caps->cmd_pause = false;
2624 caps->cmd_terminate = true;
Lars-Peter Clausenbfb9bb42014-01-11 14:02:17 +01002625 caps->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
Lars-Peter Clausenca38ff12013-07-15 17:53:08 +02002626
Lars-Peter Clausenca38ff12013-07-15 17:53:08 +02002627 return 0;
2628}
2629
Krzysztof Kozlowskib816ccc2014-11-18 12:17:56 +01002630/*
2631 * Runtime PM callbacks are provided by amba/bus.c driver.
2632 *
2633 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2634 * bus driver will only disable/enable the clock in runtime PM callbacks.
2635 */
2636static int __maybe_unused pl330_suspend(struct device *dev)
2637{
2638 struct amba_device *pcdev = to_amba_device(dev);
2639
2640 pm_runtime_disable(dev);
2641
2642 if (!pm_runtime_status_suspended(dev)) {
2643 /* amba did not disable the clock */
2644 amba_pclk_disable(pcdev);
2645 }
2646 amba_pclk_unprepare(pcdev);
2647
2648 return 0;
2649}
2650
2651static int __maybe_unused pl330_resume(struct device *dev)
2652{
2653 struct amba_device *pcdev = to_amba_device(dev);
2654 int ret;
2655
2656 ret = amba_pclk_prepare(pcdev);
2657 if (ret)
2658 return ret;
2659
2660 if (!pm_runtime_status_suspended(dev))
2661 ret = amba_pclk_enable(pcdev);
2662
2663 pm_runtime_enable(dev);
2664
2665 return ret;
2666}
2667
2668static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume);
2669
Bill Pemberton463a1f82012-11-19 13:22:55 -05002670static int
Russell Kingaa25afa2011-02-19 15:55:00 +00002671pl330_probe(struct amba_device *adev, const struct amba_id *id)
Jassi Brarb3040e42010-05-23 20:28:19 -07002672{
2673 struct dma_pl330_platdata *pdat;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002674 struct pl330_config *pcfg;
2675 struct pl330_dmac *pl330;
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302676 struct dma_pl330_chan *pch, *_p;
Jassi Brarb3040e42010-05-23 20:28:19 -07002677 struct dma_device *pd;
2678 struct resource *res;
2679 int i, ret, irq;
Rob Herring4e0e6102011-07-25 16:05:04 -05002680 int num_chan;
Jassi Brarb3040e42010-05-23 20:28:19 -07002681
Jingoo Hand4adcc02013-07-30 17:09:11 +09002682 pdat = dev_get_platdata(&adev->dev);
Jassi Brarb3040e42010-05-23 20:28:19 -07002683
Russell King64113012013-06-27 10:29:32 +01002684 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
2685 if (ret)
2686 return ret;
2687
Jassi Brarb3040e42010-05-23 20:28:19 -07002688 /* Allocate a new DMAC and its Channels */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002689 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
2690 if (!pl330) {
Jassi Brarb3040e42010-05-23 20:28:19 -07002691 dev_err(&adev->dev, "unable to allocate mem\n");
2692 return -ENOMEM;
2693 }
2694
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002695 pl330->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
Jassi Brarb3040e42010-05-23 20:28:19 -07002696
2697 res = &adev->res;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002698 pl330->base = devm_ioremap_resource(&adev->dev, res);
2699 if (IS_ERR(pl330->base))
2700 return PTR_ERR(pl330->base);
Jassi Brarb3040e42010-05-23 20:28:19 -07002701
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002702 amba_set_drvdata(adev, pl330);
Boojin Kima2f52032011-09-02 09:44:29 +09002703
Dan Carpenter02808b42013-11-08 12:50:24 +03002704 for (i = 0; i < AMBA_NR_IRQS; i++) {
Michal Simeke98b3ca2013-09-30 08:50:48 +02002705 irq = adev->irq[i];
2706 if (irq) {
2707 ret = devm_request_irq(&adev->dev, irq,
2708 pl330_irq_handler, 0,
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002709 dev_name(&adev->dev), pl330);
Michal Simeke98b3ca2013-09-30 08:50:48 +02002710 if (ret)
2711 return ret;
2712 } else {
2713 break;
2714 }
2715 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002716
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002717 pcfg = &pl330->pcfg;
2718
2719 pcfg->periph_id = adev->periphid;
2720 ret = pl330_add(pl330);
Jassi Brarb3040e42010-05-23 20:28:19 -07002721 if (ret)
Michal Simek173e8382013-09-04 16:40:17 +02002722 return ret;
Jassi Brarb3040e42010-05-23 20:28:19 -07002723
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002724 INIT_LIST_HEAD(&pl330->desc_pool);
2725 spin_lock_init(&pl330->pool_lock);
Jassi Brarb3040e42010-05-23 20:28:19 -07002726
2727 /* Create a descriptor pool of default size */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002728 if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC))
Jassi Brarb3040e42010-05-23 20:28:19 -07002729 dev_warn(&adev->dev, "unable to allocate desc\n");
2730
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002731 pd = &pl330->ddma;
Jassi Brarb3040e42010-05-23 20:28:19 -07002732 INIT_LIST_HEAD(&pd->channels);
2733
2734 /* Initialize channel parameters */
Olof Johanssonc8473822012-04-08 16:26:19 -07002735 if (pdat)
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002736 num_chan = max_t(int, pdat->nr_valid_peri, pcfg->num_chan);
Olof Johanssonc8473822012-04-08 16:26:19 -07002737 else
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002738 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
Olof Johanssonc8473822012-04-08 16:26:19 -07002739
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002740 pl330->num_peripherals = num_chan;
Lars-Peter Clausen70cbb162014-01-11 20:08:39 +01002741
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002742 pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
2743 if (!pl330->peripherals) {
Sachin Kamat61c6e752012-09-17 15:20:23 +05302744 ret = -ENOMEM;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002745 dev_err(&adev->dev, "unable to allocate pl330->peripherals\n");
Sachin Kamate4d43c12012-11-15 06:27:50 +00002746 goto probe_err2;
Sachin Kamat61c6e752012-09-17 15:20:23 +05302747 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002748
Rob Herring4e0e6102011-07-25 16:05:04 -05002749 for (i = 0; i < num_chan; i++) {
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002750 pch = &pl330->peripherals[i];
Thomas Abraham93ed5542011-10-24 11:43:31 +02002751 if (!adev->dev.of_node)
2752 pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
2753 else
2754 pch->chan.private = adev->dev.of_node;
Jassi Brarb3040e42010-05-23 20:28:19 -07002755
Lars-Peter Clausen04abf5d2014-01-11 20:08:38 +01002756 INIT_LIST_HEAD(&pch->submitted_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002757 INIT_LIST_HEAD(&pch->work_list);
Lars-Peter Clausen39ff8612013-08-27 20:34:05 +02002758 INIT_LIST_HEAD(&pch->completed_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002759 spin_lock_init(&pch->lock);
Lars-Peter Clausen65ad6062014-07-06 20:32:26 +02002760 pch->thread = NULL;
Jassi Brarb3040e42010-05-23 20:28:19 -07002761 pch->chan.device = pd;
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002762 pch->dmac = pl330;
Jassi Brarb3040e42010-05-23 20:28:19 -07002763
2764 /* Add the channel to the DMAC list */
Jassi Brarb3040e42010-05-23 20:28:19 -07002765 list_add_tail(&pch->chan.device_node, &pd->channels);
2766 }
2767
2768 pd->dev = &adev->dev;
Thomas Abraham93ed5542011-10-24 11:43:31 +02002769 if (pdat) {
Thomas Abrahamcd072512011-10-24 11:43:11 +02002770 pd->cap_mask = pdat->cap_mask;
Thomas Abraham93ed5542011-10-24 11:43:31 +02002771 } else {
Thomas Abrahamcd072512011-10-24 11:43:11 +02002772 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002773 if (pcfg->num_peri) {
Thomas Abraham93ed5542011-10-24 11:43:31 +02002774 dma_cap_set(DMA_SLAVE, pd->cap_mask);
2775 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
Tushar Behera5557a412012-08-29 10:16:25 +05302776 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
Thomas Abraham93ed5542011-10-24 11:43:31 +02002777 }
2778 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002779
2780 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
2781 pd->device_free_chan_resources = pl330_free_chan_resources;
2782 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002783 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
Jassi Brarb3040e42010-05-23 20:28:19 -07002784 pd->device_tx_status = pl330_tx_status;
2785 pd->device_prep_slave_sg = pl330_prep_slave_sg;
2786 pd->device_control = pl330_control;
2787 pd->device_issue_pending = pl330_issue_pending;
Lars-Peter Clausenca38ff12013-07-15 17:53:08 +02002788 pd->device_slave_caps = pl330_dma_device_slave_caps;
Jassi Brarb3040e42010-05-23 20:28:19 -07002789
2790 ret = dma_async_device_register(pd);
2791 if (ret) {
2792 dev_err(&adev->dev, "unable to register DMAC\n");
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302793 goto probe_err3;
2794 }
2795
2796 if (adev->dev.of_node) {
2797 ret = of_dma_controller_register(adev->dev.of_node,
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002798 of_dma_pl330_xlate, pl330);
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302799 if (ret) {
2800 dev_err(&adev->dev,
2801 "unable to register DMA to the generic DT DMA helpers\n");
2802 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002803 }
Lars-Peter Clausenb714b842013-11-25 16:07:46 +01002804
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002805 adev->dev.dma_parms = &pl330->dma_parms;
Lars-Peter Clausenb714b842013-11-25 16:07:46 +01002806
Vinod Kouldbaf6d82013-09-02 21:54:48 +05302807 /*
2808 * This is the limit for transfers with a buswidth of 1, larger
2809 * buswidths will have larger limits.
2810 */
2811 ret = dma_set_max_seg_size(&adev->dev, 1900800);
2812 if (ret)
2813 dev_err(&adev->dev, "unable to set the seg size\n");
2814
Jassi Brarb3040e42010-05-23 20:28:19 -07002815
Jassi Brarb3040e42010-05-23 20:28:19 -07002816 dev_info(&adev->dev,
2817 "Loaded driver for PL330 DMAC-%d\n", adev->periphid);
2818 dev_info(&adev->dev,
2819 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002820 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
2821 pcfg->num_peri, pcfg->num_events);
Jassi Brarb3040e42010-05-23 20:28:19 -07002822
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002823 pm_runtime_irq_safe(&adev->dev);
2824 pm_runtime_use_autosuspend(&adev->dev);
2825 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
2826 pm_runtime_mark_last_busy(&adev->dev);
2827 pm_runtime_put_autosuspend(&adev->dev);
2828
Jassi Brarb3040e42010-05-23 20:28:19 -07002829 return 0;
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302830probe_err3:
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302831 /* Idle the DMAC */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002832 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302833 chan.device_node) {
2834
2835 /* Remove the channel */
2836 list_del(&pch->chan.device_node);
2837
2838 /* Flush the channel */
Krzysztof Kozlowski0f5ebab2014-09-29 14:42:20 +02002839 if (pch->thread) {
2840 pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0);
2841 pl330_free_chan_resources(&pch->chan);
2842 }
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302843 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002844probe_err2:
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002845 pl330_del(pl330);
Jassi Brarb3040e42010-05-23 20:28:19 -07002846
2847 return ret;
2848}
2849
Greg Kroah-Hartman4bf27b82012-12-21 15:09:59 -08002850static int pl330_remove(struct amba_device *adev)
Jassi Brarb3040e42010-05-23 20:28:19 -07002851{
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002852 struct pl330_dmac *pl330 = amba_get_drvdata(adev);
Jassi Brarb3040e42010-05-23 20:28:19 -07002853 struct dma_pl330_chan *pch, *_p;
Jassi Brarb3040e42010-05-23 20:28:19 -07002854
Krzysztof Kozlowskiae43b322014-11-14 09:48:57 +01002855 pm_runtime_get_noresume(pl330->ddma.dev);
2856
Padmavathi Venna0b94c572013-03-05 14:55:31 +05302857 if (adev->dev.of_node)
2858 of_dma_controller_free(adev->dev.of_node);
Padmavathi Venna421da892013-02-14 09:10:07 +05302859
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002860 dma_async_device_unregister(&pl330->ddma);
Jassi Brarb3040e42010-05-23 20:28:19 -07002861
2862 /* Idle the DMAC */
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002863 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
Jassi Brarb3040e42010-05-23 20:28:19 -07002864 chan.device_node) {
2865
2866 /* Remove the channel */
2867 list_del(&pch->chan.device_node);
2868
2869 /* Flush the channel */
Krzysztof Kozlowski6e4a2a82014-09-29 14:42:21 +02002870 if (pch->thread) {
2871 pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0);
2872 pl330_free_chan_resources(&pch->chan);
2873 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002874 }
2875
Lars-Peter Clausenf6f24212014-07-06 20:32:29 +02002876 pl330_del(pl330);
Jassi Brarb3040e42010-05-23 20:28:19 -07002877
Jassi Brarb3040e42010-05-23 20:28:19 -07002878 return 0;
2879}
2880
2881static struct amba_id pl330_ids[] = {
2882 {
2883 .id = 0x00041330,
2884 .mask = 0x000fffff,
2885 },
2886 { 0, 0 },
2887};
2888
Dave Martine8fa5162011-10-05 15:15:20 +01002889MODULE_DEVICE_TABLE(amba, pl330_ids);
2890
Jassi Brarb3040e42010-05-23 20:28:19 -07002891static struct amba_driver pl330_driver = {
2892 .drv = {
2893 .owner = THIS_MODULE,
2894 .name = "dma-pl330",
Krzysztof Kozlowskib816ccc2014-11-18 12:17:56 +01002895 .pm = &pl330_pm,
Jassi Brarb3040e42010-05-23 20:28:19 -07002896 },
2897 .id_table = pl330_ids,
2898 .probe = pl330_probe,
2899 .remove = pl330_remove,
2900};
2901
viresh kumar9e5ed092012-03-15 10:40:38 +01002902module_amba_driver(pl330_driver);
Jassi Brarb3040e42010-05-23 20:28:19 -07002903
2904MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
2905MODULE_DESCRIPTION("API Driver for PL330 DMAC");
2906MODULE_LICENSE("GPL");