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gerrit-public.fairphone.software / kernel / msm-4.9 / 1355ab147fa38e4b3841469c51422e2343a877b2 / . / sound / soc / codecs / wm8962.c
blob: 445d2090661cea83d7b2fc780cc39fcf861e5956 [file] [log] [blame]
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1/*
2 * wm8962.c -- WM8962 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/gcd.h>
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]20#include <linux/gpio.h>
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]21#include <linux/i2c.h>
22#include <linux/input.h>
Mark Brownd23031a2012-02-01 12:48:59 +0000[diff] [blame]23#include <linux/pm_runtime.h>
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]24#include <linux/regmap.h>
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]25#include <linux/regulator/consumer.h>
26#include <linux/slab.h>
27#include <linux/workqueue.h>
28#include <sound/core.h>
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]29#include <sound/jack.h>
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/soc.h>
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]33#include <sound/initval.h>
34#include <sound/tlv.h>
35#include <sound/wm8962.h>
Mark Brown2bbb5d62010-12-05 12:50:12 +0000[diff] [blame]36#include <trace/events/asoc.h>
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]37
38#include "wm8962.h"
39
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]40#define WM8962_NUM_SUPPLIES 8
41static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
42 "DCVDD",
43 "DBVDD",
44 "AVDD",
45 "CPVDD",
46 "MICVDD",
47 "PLLVDD",
48 "SPKVDD1",
49 "SPKVDD2",
50};
51
52/* codec private data */
53struct wm8962_priv {
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]54 struct regmap *regmap;
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]55 struct snd_soc_codec *codec;
56
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]57 int sysclk;
58 int sysclk_rate;
59
60 int bclk; /* Desired BCLK */
61 int lrclk;
62
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]63 struct completion fll_lock;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]64 int fll_src;
65 int fll_fref;
66 int fll_fout;
67
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]68 u16 dsp2_ena;
69
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]70 struct delayed_work mic_work;
71 struct snd_soc_jack *jack;
72
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]73 struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
74 struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
75
76#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
77 struct input_dev *beep;
78 struct work_struct beep_work;
79 int beep_rate;
80#endif
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]81
82#ifdef CONFIG_GPIOLIB
83 struct gpio_chip gpio_chip;
84#endif
Mark Brownc7356da2011-06-07 23:13:53 +0100[diff] [blame]85
86 int irq;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]87};
88
89/* We can't use the same notifier block for more than one supply and
90 * there's no way I can see to get from a callback to the caller
91 * except container_of().
92 */
93#define WM8962_REGULATOR_EVENT(n) \
94static int wm8962_regulator_event_##n(struct notifier_block *nb, \
95 unsigned long event, void *data) \
96{ \
97 struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
98 disable_nb[n]); \
99 if (event & REGULATOR_EVENT_DISABLE) { \
Mark Brown5539a102012-01-25 21:10:21 +0000[diff] [blame]100 regcache_mark_dirty(wm8962->regmap); \
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]101 } \
102 return 0; \
103}
104
105WM8962_REGULATOR_EVENT(0)
106WM8962_REGULATOR_EVENT(1)
107WM8962_REGULATOR_EVENT(2)
108WM8962_REGULATOR_EVENT(3)
109WM8962_REGULATOR_EVENT(4)
110WM8962_REGULATOR_EVENT(5)
111WM8962_REGULATOR_EVENT(6)
112WM8962_REGULATOR_EVENT(7)
113
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]114static struct reg_default wm8962_reg[] = {
115 { 0, 0x009F }, /* R0 - Left Input volume */
116 { 1, 0x049F }, /* R1 - Right Input volume */
117 { 2, 0x0000 }, /* R2 - HPOUTL volume */
118 { 3, 0x0000 }, /* R3 - HPOUTR volume */
119 { 4, 0x0020 }, /* R4 - Clocking1 */
120 { 5, 0x0018 }, /* R5 - ADC & DAC Control 1 */
121 { 6, 0x2008 }, /* R6 - ADC & DAC Control 2 */
122 { 7, 0x000A }, /* R7 - Audio Interface 0 */
123 { 8, 0x01E4 }, /* R8 - Clocking2 */
124 { 9, 0x0300 }, /* R9 - Audio Interface 1 */
125 { 10, 0x00C0 }, /* R10 - Left DAC volume */
126 { 11, 0x00C0 }, /* R11 - Right DAC volume */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]127
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]128 { 14, 0x0040 }, /* R14 - Audio Interface 2 */
129 { 15, 0x6243 }, /* R15 - Software Reset */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]130
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]131 { 17, 0x007B }, /* R17 - ALC1 */
132 { 18, 0x0000 }, /* R18 - ALC2 */
133 { 19, 0x1C32 }, /* R19 - ALC3 */
134 { 20, 0x3200 }, /* R20 - Noise Gate */
135 { 21, 0x00C0 }, /* R21 - Left ADC volume */
136 { 22, 0x00C0 }, /* R22 - Right ADC volume */
137 { 23, 0x0160 }, /* R23 - Additional control(1) */
138 { 24, 0x0000 }, /* R24 - Additional control(2) */
139 { 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */
140 { 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */
141 { 27, 0x0010 }, /* R27 - Additional Control (3) */
142 { 28, 0x0000 }, /* R28 - Anti-pop */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]143
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]144 { 30, 0x005E }, /* R30 - Clocking 3 */
145 { 31, 0x0000 }, /* R31 - Input mixer control (1) */
146 { 32, 0x0145 }, /* R32 - Left input mixer volume */
147 { 33, 0x0145 }, /* R33 - Right input mixer volume */
148 { 34, 0x0009 }, /* R34 - Input mixer control (2) */
149 { 35, 0x0003 }, /* R35 - Input bias control */
150 { 37, 0x0008 }, /* R37 - Left input PGA control */
151 { 38, 0x0008 }, /* R38 - Right input PGA control */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]152
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]153 { 40, 0x0000 }, /* R40 - SPKOUTL volume */
154 { 41, 0x0000 }, /* R41 - SPKOUTR volume */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]155
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]156 { 47, 0x0000 }, /* R47 - Thermal Shutdown Status */
157 { 48, 0x8027 }, /* R48 - Additional Control (4) */
158 { 49, 0x0010 }, /* R49 - Class D Control 1 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]159
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]160 { 51, 0x0003 }, /* R51 - Class D Control 2 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]161
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]162 { 56, 0x0506 }, /* R56 - Clocking 4 */
163 { 57, 0x0000 }, /* R57 - DAC DSP Mixing (1) */
164 { 58, 0x0000 }, /* R58 - DAC DSP Mixing (2) */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]165
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]166 { 60, 0x0300 }, /* R60 - DC Servo 0 */
167 { 61, 0x0300 }, /* R61 - DC Servo 1 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]168
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]169 { 64, 0x0810 }, /* R64 - DC Servo 4 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]170
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]171 { 66, 0x0000 }, /* R66 - DC Servo 6 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]172
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]173 { 68, 0x001B }, /* R68 - Analogue PGA Bias */
174 { 69, 0x0000 }, /* R69 - Analogue HP 0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]175
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]176 { 71, 0x01FB }, /* R71 - Analogue HP 2 */
177 { 72, 0x0000 }, /* R72 - Charge Pump 1 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]178
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]179 { 82, 0x0004 }, /* R82 - Charge Pump B */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]180
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]181 { 87, 0x0000 }, /* R87 - Write Sequencer Control 1 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]182
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]183 { 90, 0x0000 }, /* R90 - Write Sequencer Control 2 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]184
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]185 { 93, 0x0000 }, /* R93 - Write Sequencer Control 3 */
186 { 94, 0x0000 }, /* R94 - Control Interface */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]187
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]188 { 99, 0x0000 }, /* R99 - Mixer Enables */
189 { 100, 0x0000 }, /* R100 - Headphone Mixer (1) */
190 { 101, 0x0000 }, /* R101 - Headphone Mixer (2) */
191 { 102, 0x013F }, /* R102 - Headphone Mixer (3) */
192 { 103, 0x013F }, /* R103 - Headphone Mixer (4) */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]193
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]194 { 105, 0x0000 }, /* R105 - Speaker Mixer (1) */
195 { 106, 0x0000 }, /* R106 - Speaker Mixer (2) */
196 { 107, 0x013F }, /* R107 - Speaker Mixer (3) */
197 { 108, 0x013F }, /* R108 - Speaker Mixer (4) */
198 { 109, 0x0003 }, /* R109 - Speaker Mixer (5) */
199 { 110, 0x0002 }, /* R110 - Beep Generator (1) */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]200
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]201 { 115, 0x0006 }, /* R115 - Oscillator Trim (3) */
202 { 116, 0x0026 }, /* R116 - Oscillator Trim (4) */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]203
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]204 { 119, 0x0000 }, /* R119 - Oscillator Trim (7) */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]205
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]206 { 124, 0x0011 }, /* R124 - Analogue Clocking1 */
207 { 125, 0x004B }, /* R125 - Analogue Clocking2 */
208 { 126, 0x000D }, /* R126 - Analogue Clocking3 */
209 { 127, 0x0000 }, /* R127 - PLL Software Reset */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]210
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]211 { 131, 0x0000 }, /* R131 - PLL 4 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]212
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]213 { 136, 0x0067 }, /* R136 - PLL 9 */
214 { 137, 0x001C }, /* R137 - PLL 10 */
215 { 138, 0x0071 }, /* R138 - PLL 11 */
216 { 139, 0x00C7 }, /* R139 - PLL 12 */
217 { 140, 0x0067 }, /* R140 - PLL 13 */
218 { 141, 0x0048 }, /* R141 - PLL 14 */
219 { 142, 0x0022 }, /* R142 - PLL 15 */
220 { 143, 0x0097 }, /* R143 - PLL 16 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]221
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]222 { 155, 0x000C }, /* R155 - FLL Control (1) */
223 { 156, 0x0039 }, /* R156 - FLL Control (2) */
224 { 157, 0x0180 }, /* R157 - FLL Control (3) */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]225
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]226 { 159, 0x0032 }, /* R159 - FLL Control (5) */
227 { 160, 0x0018 }, /* R160 - FLL Control (6) */
228 { 161, 0x007D }, /* R161 - FLL Control (7) */
229 { 162, 0x0008 }, /* R162 - FLL Control (8) */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]230
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]231 { 252, 0x0005 }, /* R252 - General test 1 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]232
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]233 { 256, 0x0000 }, /* R256 - DF1 */
234 { 257, 0x0000 }, /* R257 - DF2 */
235 { 258, 0x0000 }, /* R258 - DF3 */
236 { 259, 0x0000 }, /* R259 - DF4 */
237 { 260, 0x0000 }, /* R260 - DF5 */
238 { 261, 0x0000 }, /* R261 - DF6 */
239 { 262, 0x0000 }, /* R262 - DF7 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]240
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]241 { 264, 0x0000 }, /* R264 - LHPF1 */
242 { 265, 0x0000 }, /* R265 - LHPF2 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]243
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]244 { 268, 0x0000 }, /* R268 - THREED1 */
245 { 269, 0x0000 }, /* R269 - THREED2 */
246 { 270, 0x0000 }, /* R270 - THREED3 */
247 { 271, 0x0000 }, /* R271 - THREED4 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]248
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]249 { 276, 0x000C }, /* R276 - DRC 1 */
250 { 277, 0x0925 }, /* R277 - DRC 2 */
251 { 278, 0x0000 }, /* R278 - DRC 3 */
252 { 279, 0x0000 }, /* R279 - DRC 4 */
253 { 280, 0x0000 }, /* R280 - DRC 5 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]254
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]255 { 285, 0x0000 }, /* R285 - Tloopback */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]256
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]257 { 335, 0x0004 }, /* R335 - EQ1 */
258 { 336, 0x6318 }, /* R336 - EQ2 */
259 { 337, 0x6300 }, /* R337 - EQ3 */
260 { 338, 0x0FCA }, /* R338 - EQ4 */
261 { 339, 0x0400 }, /* R339 - EQ5 */
262 { 340, 0x00D8 }, /* R340 - EQ6 */
263 { 341, 0x1EB5 }, /* R341 - EQ7 */
264 { 342, 0xF145 }, /* R342 - EQ8 */
265 { 343, 0x0B75 }, /* R343 - EQ9 */
266 { 344, 0x01C5 }, /* R344 - EQ10 */
267 { 345, 0x1C58 }, /* R345 - EQ11 */
268 { 346, 0xF373 }, /* R346 - EQ12 */
269 { 347, 0x0A54 }, /* R347 - EQ13 */
270 { 348, 0x0558 }, /* R348 - EQ14 */
271 { 349, 0x168E }, /* R349 - EQ15 */
272 { 350, 0xF829 }, /* R350 - EQ16 */
273 { 351, 0x07AD }, /* R351 - EQ17 */
274 { 352, 0x1103 }, /* R352 - EQ18 */
275 { 353, 0x0564 }, /* R353 - EQ19 */
276 { 354, 0x0559 }, /* R354 - EQ20 */
277 { 355, 0x4000 }, /* R355 - EQ21 */
278 { 356, 0x6318 }, /* R356 - EQ22 */
279 { 357, 0x6300 }, /* R357 - EQ23 */
280 { 358, 0x0FCA }, /* R358 - EQ24 */
281 { 359, 0x0400 }, /* R359 - EQ25 */
282 { 360, 0x00D8 }, /* R360 - EQ26 */
283 { 361, 0x1EB5 }, /* R361 - EQ27 */
284 { 362, 0xF145 }, /* R362 - EQ28 */
285 { 363, 0x0B75 }, /* R363 - EQ29 */
286 { 364, 0x01C5 }, /* R364 - EQ30 */
287 { 365, 0x1C58 }, /* R365 - EQ31 */
288 { 366, 0xF373 }, /* R366 - EQ32 */
289 { 367, 0x0A54 }, /* R367 - EQ33 */
290 { 368, 0x0558 }, /* R368 - EQ34 */
291 { 369, 0x168E }, /* R369 - EQ35 */
292 { 370, 0xF829 }, /* R370 - EQ36 */
293 { 371, 0x07AD }, /* R371 - EQ37 */
294 { 372, 0x1103 }, /* R372 - EQ38 */
295 { 373, 0x0564 }, /* R373 - EQ39 */
296 { 374, 0x0559 }, /* R374 - EQ40 */
297 { 375, 0x4000 }, /* R375 - EQ41 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]298
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]299 { 513, 0x0000 }, /* R513 - GPIO 2 */
300 { 514, 0x0000 }, /* R514 - GPIO 3 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]301
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]302 { 516, 0x8100 }, /* R516 - GPIO 5 */
303 { 517, 0x8100 }, /* R517 - GPIO 6 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]304
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]305 { 560, 0x0000 }, /* R560 - Interrupt Status 1 */
306 { 561, 0x0000 }, /* R561 - Interrupt Status 2 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]307
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]308 { 568, 0x0030 }, /* R568 - Interrupt Status 1 Mask */
309 { 569, 0xFFED }, /* R569 - Interrupt Status 2 Mask */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]310
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]311 { 576, 0x0000 }, /* R576 - Interrupt Control */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]312
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]313 { 584, 0x002D }, /* R584 - IRQ Debounce */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]314
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]315 { 586, 0x0000 }, /* R586 - MICINT Source Pol */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]316
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]317 { 768, 0x1C00 }, /* R768 - DSP2 Power Management */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]318
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]319 { 1037, 0x0000 }, /* R1037 - DSP2_ExecControl */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]320
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]321 { 8192, 0x0000 }, /* R8192 - DSP2 Instruction RAM 0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]322
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]323 { 9216, 0x0030 }, /* R9216 - DSP2 Address RAM 2 */
324 { 9217, 0x0000 }, /* R9217 - DSP2 Address RAM 1 */
325 { 9218, 0x0000 }, /* R9218 - DSP2 Address RAM 0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]326
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]327 { 12288, 0x0000 }, /* R12288 - DSP2 Data1 RAM 1 */
328 { 12289, 0x0000 }, /* R12289 - DSP2 Data1 RAM 0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]329
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]330 { 13312, 0x0000 }, /* R13312 - DSP2 Data2 RAM 1 */
331 { 13313, 0x0000 }, /* R13313 - DSP2 Data2 RAM 0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]332
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]333 { 14336, 0x0000 }, /* R14336 - DSP2 Data3 RAM 1 */
334 { 14337, 0x0000 }, /* R14337 - DSP2 Data3 RAM 0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]335
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]336 { 15360, 0x000A }, /* R15360 - DSP2 Coeff RAM 0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]337
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]338 { 16384, 0x0000 }, /* R16384 - RETUNEADC_SHARED_COEFF_1 */
339 { 16385, 0x0000 }, /* R16385 - RETUNEADC_SHARED_COEFF_0 */
340 { 16386, 0x0000 }, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */
341 { 16387, 0x0000 }, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */
342 { 16388, 0x0000 }, /* R16388 - SOUNDSTAGE_ENABLES_1 */
343 { 16389, 0x0000 }, /* R16389 - SOUNDSTAGE_ENABLES_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]344
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]345 { 16896, 0x0002 }, /* R16896 - HDBASS_AI_1 */
346 { 16897, 0xBD12 }, /* R16897 - HDBASS_AI_0 */
347 { 16898, 0x007C }, /* R16898 - HDBASS_AR_1 */
348 { 16899, 0x586C }, /* R16899 - HDBASS_AR_0 */
349 { 16900, 0x0053 }, /* R16900 - HDBASS_B_1 */
350 { 16901, 0x8121 }, /* R16901 - HDBASS_B_0 */
351 { 16902, 0x003F }, /* R16902 - HDBASS_K_1 */
352 { 16903, 0x8BD8 }, /* R16903 - HDBASS_K_0 */
353 { 16904, 0x0032 }, /* R16904 - HDBASS_N1_1 */
354 { 16905, 0xF52D }, /* R16905 - HDBASS_N1_0 */
355 { 16906, 0x0065 }, /* R16906 - HDBASS_N2_1 */
356 { 16907, 0xAC8C }, /* R16907 - HDBASS_N2_0 */
357 { 16908, 0x006B }, /* R16908 - HDBASS_N3_1 */
358 { 16909, 0xE087 }, /* R16909 - HDBASS_N3_0 */
359 { 16910, 0x0072 }, /* R16910 - HDBASS_N4_1 */
360 { 16911, 0x1483 }, /* R16911 - HDBASS_N4_0 */
361 { 16912, 0x0072 }, /* R16912 - HDBASS_N5_1 */
362 { 16913, 0x1483 }, /* R16913 - HDBASS_N5_0 */
363 { 16914, 0x0043 }, /* R16914 - HDBASS_X1_1 */
364 { 16915, 0x3525 }, /* R16915 - HDBASS_X1_0 */
365 { 16916, 0x0006 }, /* R16916 - HDBASS_X2_1 */
366 { 16917, 0x6A4A }, /* R16917 - HDBASS_X2_0 */
367 { 16918, 0x0043 }, /* R16918 - HDBASS_X3_1 */
368 { 16919, 0x6079 }, /* R16919 - HDBASS_X3_0 */
369 { 16920, 0x0008 }, /* R16920 - HDBASS_ATK_1 */
370 { 16921, 0x0000 }, /* R16921 - HDBASS_ATK_0 */
371 { 16922, 0x0001 }, /* R16922 - HDBASS_DCY_1 */
372 { 16923, 0x0000 }, /* R16923 - HDBASS_DCY_0 */
373 { 16924, 0x0059 }, /* R16924 - HDBASS_PG_1 */
374 { 16925, 0x999A }, /* R16925 - HDBASS_PG_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]375
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]376 { 17048, 0x0083 }, /* R17408 - HPF_C_1 */
377 { 17049, 0x98AD }, /* R17409 - HPF_C_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]378
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]379 { 17920, 0x007F }, /* R17920 - ADCL_RETUNE_C1_1 */
380 { 17921, 0xFFFF }, /* R17921 - ADCL_RETUNE_C1_0 */
381 { 17922, 0x0000 }, /* R17922 - ADCL_RETUNE_C2_1 */
382 { 17923, 0x0000 }, /* R17923 - ADCL_RETUNE_C2_0 */
383 { 17924, 0x0000 }, /* R17924 - ADCL_RETUNE_C3_1 */
384 { 17925, 0x0000 }, /* R17925 - ADCL_RETUNE_C3_0 */
385 { 17926, 0x0000 }, /* R17926 - ADCL_RETUNE_C4_1 */
386 { 17927, 0x0000 }, /* R17927 - ADCL_RETUNE_C4_0 */
387 { 17928, 0x0000 }, /* R17928 - ADCL_RETUNE_C5_1 */
388 { 17929, 0x0000 }, /* R17929 - ADCL_RETUNE_C5_0 */
389 { 17930, 0x0000 }, /* R17930 - ADCL_RETUNE_C6_1 */
390 { 17931, 0x0000 }, /* R17931 - ADCL_RETUNE_C6_0 */
391 { 17932, 0x0000 }, /* R17932 - ADCL_RETUNE_C7_1 */
392 { 17933, 0x0000 }, /* R17933 - ADCL_RETUNE_C7_0 */
393 { 17934, 0x0000 }, /* R17934 - ADCL_RETUNE_C8_1 */
394 { 17935, 0x0000 }, /* R17935 - ADCL_RETUNE_C8_0 */
395 { 17936, 0x0000 }, /* R17936 - ADCL_RETUNE_C9_1 */
396 { 17937, 0x0000 }, /* R17937 - ADCL_RETUNE_C9_0 */
397 { 17938, 0x0000 }, /* R17938 - ADCL_RETUNE_C10_1 */
398 { 17939, 0x0000 }, /* R17939 - ADCL_RETUNE_C10_0 */
399 { 17940, 0x0000 }, /* R17940 - ADCL_RETUNE_C11_1 */
400 { 17941, 0x0000 }, /* R17941 - ADCL_RETUNE_C11_0 */
401 { 17942, 0x0000 }, /* R17942 - ADCL_RETUNE_C12_1 */
402 { 17943, 0x0000 }, /* R17943 - ADCL_RETUNE_C12_0 */
403 { 17944, 0x0000 }, /* R17944 - ADCL_RETUNE_C13_1 */
404 { 17945, 0x0000 }, /* R17945 - ADCL_RETUNE_C13_0 */
405 { 17946, 0x0000 }, /* R17946 - ADCL_RETUNE_C14_1 */
406 { 17947, 0x0000 }, /* R17947 - ADCL_RETUNE_C14_0 */
407 { 17948, 0x0000 }, /* R17948 - ADCL_RETUNE_C15_1 */
408 { 17949, 0x0000 }, /* R17949 - ADCL_RETUNE_C15_0 */
409 { 17950, 0x0000 }, /* R17950 - ADCL_RETUNE_C16_1 */
410 { 17951, 0x0000 }, /* R17951 - ADCL_RETUNE_C16_0 */
411 { 17952, 0x0000 }, /* R17952 - ADCL_RETUNE_C17_1 */
412 { 17953, 0x0000 }, /* R17953 - ADCL_RETUNE_C17_0 */
413 { 17954, 0x0000 }, /* R17954 - ADCL_RETUNE_C18_1 */
414 { 17955, 0x0000 }, /* R17955 - ADCL_RETUNE_C18_0 */
415 { 17956, 0x0000 }, /* R17956 - ADCL_RETUNE_C19_1 */
416 { 17957, 0x0000 }, /* R17957 - ADCL_RETUNE_C19_0 */
417 { 17958, 0x0000 }, /* R17958 - ADCL_RETUNE_C20_1 */
418 { 17959, 0x0000 }, /* R17959 - ADCL_RETUNE_C20_0 */
419 { 17960, 0x0000 }, /* R17960 - ADCL_RETUNE_C21_1 */
420 { 17961, 0x0000 }, /* R17961 - ADCL_RETUNE_C21_0 */
421 { 17962, 0x0000 }, /* R17962 - ADCL_RETUNE_C22_1 */
422 { 17963, 0x0000 }, /* R17963 - ADCL_RETUNE_C22_0 */
423 { 17964, 0x0000 }, /* R17964 - ADCL_RETUNE_C23_1 */
424 { 17965, 0x0000 }, /* R17965 - ADCL_RETUNE_C23_0 */
425 { 17966, 0x0000 }, /* R17966 - ADCL_RETUNE_C24_1 */
426 { 17967, 0x0000 }, /* R17967 - ADCL_RETUNE_C24_0 */
427 { 17968, 0x0000 }, /* R17968 - ADCL_RETUNE_C25_1 */
428 { 17969, 0x0000 }, /* R17969 - ADCL_RETUNE_C25_0 */
429 { 17970, 0x0000 }, /* R17970 - ADCL_RETUNE_C26_1 */
430 { 17971, 0x0000 }, /* R17971 - ADCL_RETUNE_C26_0 */
431 { 17972, 0x0000 }, /* R17972 - ADCL_RETUNE_C27_1 */
432 { 17973, 0x0000 }, /* R17973 - ADCL_RETUNE_C27_0 */
433 { 17974, 0x0000 }, /* R17974 - ADCL_RETUNE_C28_1 */
434 { 17975, 0x0000 }, /* R17975 - ADCL_RETUNE_C28_0 */
435 { 17976, 0x0000 }, /* R17976 - ADCL_RETUNE_C29_1 */
436 { 17977, 0x0000 }, /* R17977 - ADCL_RETUNE_C29_0 */
437 { 17978, 0x0000 }, /* R17978 - ADCL_RETUNE_C30_1 */
438 { 17979, 0x0000 }, /* R17979 - ADCL_RETUNE_C30_0 */
439 { 17980, 0x0000 }, /* R17980 - ADCL_RETUNE_C31_1 */
440 { 17981, 0x0000 }, /* R17981 - ADCL_RETUNE_C31_0 */
441 { 17982, 0x0000 }, /* R17982 - ADCL_RETUNE_C32_1 */
442 { 17983, 0x0000 }, /* R17983 - ADCL_RETUNE_C32_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]443
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]444 { 18432, 0x0020 }, /* R18432 - RETUNEADC_PG2_1 */
445 { 18433, 0x0000 }, /* R18433 - RETUNEADC_PG2_0 */
446 { 18434, 0x0040 }, /* R18434 - RETUNEADC_PG_1 */
447 { 18435, 0x0000 }, /* R18435 - RETUNEADC_PG_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]448
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]449 { 18944, 0x007F }, /* R18944 - ADCR_RETUNE_C1_1 */
450 { 18945, 0xFFFF }, /* R18945 - ADCR_RETUNE_C1_0 */
451 { 18946, 0x0000 }, /* R18946 - ADCR_RETUNE_C2_1 */
452 { 18947, 0x0000 }, /* R18947 - ADCR_RETUNE_C2_0 */
453 { 18948, 0x0000 }, /* R18948 - ADCR_RETUNE_C3_1 */
454 { 18949, 0x0000 }, /* R18949 - ADCR_RETUNE_C3_0 */
455 { 18950, 0x0000 }, /* R18950 - ADCR_RETUNE_C4_1 */
456 { 18951, 0x0000 }, /* R18951 - ADCR_RETUNE_C4_0 */
457 { 18952, 0x0000 }, /* R18952 - ADCR_RETUNE_C5_1 */
458 { 18953, 0x0000 }, /* R18953 - ADCR_RETUNE_C5_0 */
459 { 18954, 0x0000 }, /* R18954 - ADCR_RETUNE_C6_1 */
460 { 18955, 0x0000 }, /* R18955 - ADCR_RETUNE_C6_0 */
461 { 18956, 0x0000 }, /* R18956 - ADCR_RETUNE_C7_1 */
462 { 18957, 0x0000 }, /* R18957 - ADCR_RETUNE_C7_0 */
463 { 18958, 0x0000 }, /* R18958 - ADCR_RETUNE_C8_1 */
464 { 18959, 0x0000 }, /* R18959 - ADCR_RETUNE_C8_0 */
465 { 18960, 0x0000 }, /* R18960 - ADCR_RETUNE_C9_1 */
466 { 18961, 0x0000 }, /* R18961 - ADCR_RETUNE_C9_0 */
467 { 18962, 0x0000 }, /* R18962 - ADCR_RETUNE_C10_1 */
468 { 18963, 0x0000 }, /* R18963 - ADCR_RETUNE_C10_0 */
469 { 18964, 0x0000 }, /* R18964 - ADCR_RETUNE_C11_1 */
470 { 18965, 0x0000 }, /* R18965 - ADCR_RETUNE_C11_0 */
471 { 18966, 0x0000 }, /* R18966 - ADCR_RETUNE_C12_1 */
472 { 18967, 0x0000 }, /* R18967 - ADCR_RETUNE_C12_0 */
473 { 18968, 0x0000 }, /* R18968 - ADCR_RETUNE_C13_1 */
474 { 18969, 0x0000 }, /* R18969 - ADCR_RETUNE_C13_0 */
475 { 18970, 0x0000 }, /* R18970 - ADCR_RETUNE_C14_1 */
476 { 18971, 0x0000 }, /* R18971 - ADCR_RETUNE_C14_0 */
477 { 18972, 0x0000 }, /* R18972 - ADCR_RETUNE_C15_1 */
478 { 18973, 0x0000 }, /* R18973 - ADCR_RETUNE_C15_0 */
479 { 18974, 0x0000 }, /* R18974 - ADCR_RETUNE_C16_1 */
480 { 18975, 0x0000 }, /* R18975 - ADCR_RETUNE_C16_0 */
481 { 18976, 0x0000 }, /* R18976 - ADCR_RETUNE_C17_1 */
482 { 18977, 0x0000 }, /* R18977 - ADCR_RETUNE_C17_0 */
483 { 18978, 0x0000 }, /* R18978 - ADCR_RETUNE_C18_1 */
484 { 18979, 0x0000 }, /* R18979 - ADCR_RETUNE_C18_0 */
485 { 18980, 0x0000 }, /* R18980 - ADCR_RETUNE_C19_1 */
486 { 18981, 0x0000 }, /* R18981 - ADCR_RETUNE_C19_0 */
487 { 18982, 0x0000 }, /* R18982 - ADCR_RETUNE_C20_1 */
488 { 18983, 0x0000 }, /* R18983 - ADCR_RETUNE_C20_0 */
489 { 18984, 0x0000 }, /* R18984 - ADCR_RETUNE_C21_1 */
490 { 18985, 0x0000 }, /* R18985 - ADCR_RETUNE_C21_0 */
491 { 18986, 0x0000 }, /* R18986 - ADCR_RETUNE_C22_1 */
492 { 18987, 0x0000 }, /* R18987 - ADCR_RETUNE_C22_0 */
493 { 18988, 0x0000 }, /* R18988 - ADCR_RETUNE_C23_1 */
494 { 18989, 0x0000 }, /* R18989 - ADCR_RETUNE_C23_0 */
495 { 18990, 0x0000 }, /* R18990 - ADCR_RETUNE_C24_1 */
496 { 18991, 0x0000 }, /* R18991 - ADCR_RETUNE_C24_0 */
497 { 18992, 0x0000 }, /* R18992 - ADCR_RETUNE_C25_1 */
498 { 18993, 0x0000 }, /* R18993 - ADCR_RETUNE_C25_0 */
499 { 18994, 0x0000 }, /* R18994 - ADCR_RETUNE_C26_1 */
500 { 18995, 0x0000 }, /* R18995 - ADCR_RETUNE_C26_0 */
501 { 18996, 0x0000 }, /* R18996 - ADCR_RETUNE_C27_1 */
502 { 18997, 0x0000 }, /* R18997 - ADCR_RETUNE_C27_0 */
503 { 18998, 0x0000 }, /* R18998 - ADCR_RETUNE_C28_1 */
504 { 18999, 0x0000 }, /* R18999 - ADCR_RETUNE_C28_0 */
505 { 19000, 0x0000 }, /* R19000 - ADCR_RETUNE_C29_1 */
506 { 19001, 0x0000 }, /* R19001 - ADCR_RETUNE_C29_0 */
507 { 19002, 0x0000 }, /* R19002 - ADCR_RETUNE_C30_1 */
508 { 19003, 0x0000 }, /* R19003 - ADCR_RETUNE_C30_0 */
509 { 19004, 0x0000 }, /* R19004 - ADCR_RETUNE_C31_1 */
510 { 19005, 0x0000 }, /* R19005 - ADCR_RETUNE_C31_0 */
511 { 19006, 0x0000 }, /* R19006 - ADCR_RETUNE_C32_1 */
512 { 19007, 0x0000 }, /* R19007 - ADCR_RETUNE_C32_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]513
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]514 { 19456, 0x007F }, /* R19456 - DACL_RETUNE_C1_1 */
515 { 19457, 0xFFFF }, /* R19457 - DACL_RETUNE_C1_0 */
516 { 19458, 0x0000 }, /* R19458 - DACL_RETUNE_C2_1 */
517 { 19459, 0x0000 }, /* R19459 - DACL_RETUNE_C2_0 */
518 { 19460, 0x0000 }, /* R19460 - DACL_RETUNE_C3_1 */
519 { 19461, 0x0000 }, /* R19461 - DACL_RETUNE_C3_0 */
520 { 19462, 0x0000 }, /* R19462 - DACL_RETUNE_C4_1 */
521 { 19463, 0x0000 }, /* R19463 - DACL_RETUNE_C4_0 */
522 { 19464, 0x0000 }, /* R19464 - DACL_RETUNE_C5_1 */
523 { 19465, 0x0000 }, /* R19465 - DACL_RETUNE_C5_0 */
524 { 19466, 0x0000 }, /* R19466 - DACL_RETUNE_C6_1 */
525 { 19467, 0x0000 }, /* R19467 - DACL_RETUNE_C6_0 */
526 { 19468, 0x0000 }, /* R19468 - DACL_RETUNE_C7_1 */
527 { 19469, 0x0000 }, /* R19469 - DACL_RETUNE_C7_0 */
528 { 19470, 0x0000 }, /* R19470 - DACL_RETUNE_C8_1 */
529 { 19471, 0x0000 }, /* R19471 - DACL_RETUNE_C8_0 */
530 { 19472, 0x0000 }, /* R19472 - DACL_RETUNE_C9_1 */
531 { 19473, 0x0000 }, /* R19473 - DACL_RETUNE_C9_0 */
532 { 19474, 0x0000 }, /* R19474 - DACL_RETUNE_C10_1 */
533 { 19475, 0x0000 }, /* R19475 - DACL_RETUNE_C10_0 */
534 { 19476, 0x0000 }, /* R19476 - DACL_RETUNE_C11_1 */
535 { 19477, 0x0000 }, /* R19477 - DACL_RETUNE_C11_0 */
536 { 19478, 0x0000 }, /* R19478 - DACL_RETUNE_C12_1 */
537 { 19479, 0x0000 }, /* R19479 - DACL_RETUNE_C12_0 */
538 { 19480, 0x0000 }, /* R19480 - DACL_RETUNE_C13_1 */
539 { 19481, 0x0000 }, /* R19481 - DACL_RETUNE_C13_0 */
540 { 19482, 0x0000 }, /* R19482 - DACL_RETUNE_C14_1 */
541 { 19483, 0x0000 }, /* R19483 - DACL_RETUNE_C14_0 */
542 { 19484, 0x0000 }, /* R19484 - DACL_RETUNE_C15_1 */
543 { 19485, 0x0000 }, /* R19485 - DACL_RETUNE_C15_0 */
544 { 19486, 0x0000 }, /* R19486 - DACL_RETUNE_C16_1 */
545 { 19487, 0x0000 }, /* R19487 - DACL_RETUNE_C16_0 */
546 { 19488, 0x0000 }, /* R19488 - DACL_RETUNE_C17_1 */
547 { 19489, 0x0000 }, /* R19489 - DACL_RETUNE_C17_0 */
548 { 19490, 0x0000 }, /* R19490 - DACL_RETUNE_C18_1 */
549 { 19491, 0x0000 }, /* R19491 - DACL_RETUNE_C18_0 */
550 { 19492, 0x0000 }, /* R19492 - DACL_RETUNE_C19_1 */
551 { 19493, 0x0000 }, /* R19493 - DACL_RETUNE_C19_0 */
552 { 19494, 0x0000 }, /* R19494 - DACL_RETUNE_C20_1 */
553 { 19495, 0x0000 }, /* R19495 - DACL_RETUNE_C20_0 */
554 { 19496, 0x0000 }, /* R19496 - DACL_RETUNE_C21_1 */
555 { 19497, 0x0000 }, /* R19497 - DACL_RETUNE_C21_0 */
556 { 19498, 0x0000 }, /* R19498 - DACL_RETUNE_C22_1 */
557 { 19499, 0x0000 }, /* R19499 - DACL_RETUNE_C22_0 */
558 { 19500, 0x0000 }, /* R19500 - DACL_RETUNE_C23_1 */
559 { 19501, 0x0000 }, /* R19501 - DACL_RETUNE_C23_0 */
560 { 19502, 0x0000 }, /* R19502 - DACL_RETUNE_C24_1 */
561 { 19503, 0x0000 }, /* R19503 - DACL_RETUNE_C24_0 */
562 { 19504, 0x0000 }, /* R19504 - DACL_RETUNE_C25_1 */
563 { 19505, 0x0000 }, /* R19505 - DACL_RETUNE_C25_0 */
564 { 19506, 0x0000 }, /* R19506 - DACL_RETUNE_C26_1 */
565 { 19507, 0x0000 }, /* R19507 - DACL_RETUNE_C26_0 */
566 { 19508, 0x0000 }, /* R19508 - DACL_RETUNE_C27_1 */
567 { 19509, 0x0000 }, /* R19509 - DACL_RETUNE_C27_0 */
568 { 19510, 0x0000 }, /* R19510 - DACL_RETUNE_C28_1 */
569 { 19511, 0x0000 }, /* R19511 - DACL_RETUNE_C28_0 */
570 { 19512, 0x0000 }, /* R19512 - DACL_RETUNE_C29_1 */
571 { 19513, 0x0000 }, /* R19513 - DACL_RETUNE_C29_0 */
572 { 19514, 0x0000 }, /* R19514 - DACL_RETUNE_C30_1 */
573 { 19515, 0x0000 }, /* R19515 - DACL_RETUNE_C30_0 */
574 { 19516, 0x0000 }, /* R19516 - DACL_RETUNE_C31_1 */
575 { 19517, 0x0000 }, /* R19517 - DACL_RETUNE_C31_0 */
576 { 19518, 0x0000 }, /* R19518 - DACL_RETUNE_C32_1 */
577 { 19519, 0x0000 }, /* R19519 - DACL_RETUNE_C32_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]578
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]579 { 19968, 0x0020 }, /* R19968 - RETUNEDAC_PG2_1 */
580 { 19969, 0x0000 }, /* R19969 - RETUNEDAC_PG2_0 */
581 { 19970, 0x0040 }, /* R19970 - RETUNEDAC_PG_1 */
582 { 19971, 0x0000 }, /* R19971 - RETUNEDAC_PG_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]583
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]584 { 20480, 0x007F }, /* R20480 - DACR_RETUNE_C1_1 */
585 { 20481, 0xFFFF }, /* R20481 - DACR_RETUNE_C1_0 */
586 { 20482, 0x0000 }, /* R20482 - DACR_RETUNE_C2_1 */
587 { 20483, 0x0000 }, /* R20483 - DACR_RETUNE_C2_0 */
588 { 20484, 0x0000 }, /* R20484 - DACR_RETUNE_C3_1 */
589 { 20485, 0x0000 }, /* R20485 - DACR_RETUNE_C3_0 */
590 { 20486, 0x0000 }, /* R20486 - DACR_RETUNE_C4_1 */
591 { 20487, 0x0000 }, /* R20487 - DACR_RETUNE_C4_0 */
592 { 20488, 0x0000 }, /* R20488 - DACR_RETUNE_C5_1 */
593 { 20489, 0x0000 }, /* R20489 - DACR_RETUNE_C5_0 */
594 { 20490, 0x0000 }, /* R20490 - DACR_RETUNE_C6_1 */
595 { 20491, 0x0000 }, /* R20491 - DACR_RETUNE_C6_0 */
596 { 20492, 0x0000 }, /* R20492 - DACR_RETUNE_C7_1 */
597 { 20493, 0x0000 }, /* R20493 - DACR_RETUNE_C7_0 */
598 { 20494, 0x0000 }, /* R20494 - DACR_RETUNE_C8_1 */
599 { 20495, 0x0000 }, /* R20495 - DACR_RETUNE_C8_0 */
600 { 20496, 0x0000 }, /* R20496 - DACR_RETUNE_C9_1 */
601 { 20497, 0x0000 }, /* R20497 - DACR_RETUNE_C9_0 */
602 { 20498, 0x0000 }, /* R20498 - DACR_RETUNE_C10_1 */
603 { 20499, 0x0000 }, /* R20499 - DACR_RETUNE_C10_0 */
604 { 20500, 0x0000 }, /* R20500 - DACR_RETUNE_C11_1 */
605 { 20501, 0x0000 }, /* R20501 - DACR_RETUNE_C11_0 */
606 { 20502, 0x0000 }, /* R20502 - DACR_RETUNE_C12_1 */
607 { 20503, 0x0000 }, /* R20503 - DACR_RETUNE_C12_0 */
608 { 20504, 0x0000 }, /* R20504 - DACR_RETUNE_C13_1 */
609 { 20505, 0x0000 }, /* R20505 - DACR_RETUNE_C13_0 */
610 { 20506, 0x0000 }, /* R20506 - DACR_RETUNE_C14_1 */
611 { 20507, 0x0000 }, /* R20507 - DACR_RETUNE_C14_0 */
612 { 20508, 0x0000 }, /* R20508 - DACR_RETUNE_C15_1 */
613 { 20509, 0x0000 }, /* R20509 - DACR_RETUNE_C15_0 */
614 { 20510, 0x0000 }, /* R20510 - DACR_RETUNE_C16_1 */
615 { 20511, 0x0000 }, /* R20511 - DACR_RETUNE_C16_0 */
616 { 20512, 0x0000 }, /* R20512 - DACR_RETUNE_C17_1 */
617 { 20513, 0x0000 }, /* R20513 - DACR_RETUNE_C17_0 */
618 { 20514, 0x0000 }, /* R20514 - DACR_RETUNE_C18_1 */
619 { 20515, 0x0000 }, /* R20515 - DACR_RETUNE_C18_0 */
620 { 20516, 0x0000 }, /* R20516 - DACR_RETUNE_C19_1 */
621 { 20517, 0x0000 }, /* R20517 - DACR_RETUNE_C19_0 */
622 { 20518, 0x0000 }, /* R20518 - DACR_RETUNE_C20_1 */
623 { 20519, 0x0000 }, /* R20519 - DACR_RETUNE_C20_0 */
624 { 20520, 0x0000 }, /* R20520 - DACR_RETUNE_C21_1 */
625 { 20521, 0x0000 }, /* R20521 - DACR_RETUNE_C21_0 */
626 { 20522, 0x0000 }, /* R20522 - DACR_RETUNE_C22_1 */
627 { 20523, 0x0000 }, /* R20523 - DACR_RETUNE_C22_0 */
628 { 20524, 0x0000 }, /* R20524 - DACR_RETUNE_C23_1 */
629 { 20525, 0x0000 }, /* R20525 - DACR_RETUNE_C23_0 */
630 { 20526, 0x0000 }, /* R20526 - DACR_RETUNE_C24_1 */
631 { 20527, 0x0000 }, /* R20527 - DACR_RETUNE_C24_0 */
632 { 20528, 0x0000 }, /* R20528 - DACR_RETUNE_C25_1 */
633 { 20529, 0x0000 }, /* R20529 - DACR_RETUNE_C25_0 */
634 { 20530, 0x0000 }, /* R20530 - DACR_RETUNE_C26_1 */
635 { 20531, 0x0000 }, /* R20531 - DACR_RETUNE_C26_0 */
636 { 20532, 0x0000 }, /* R20532 - DACR_RETUNE_C27_1 */
637 { 20533, 0x0000 }, /* R20533 - DACR_RETUNE_C27_0 */
638 { 20534, 0x0000 }, /* R20534 - DACR_RETUNE_C28_1 */
639 { 20535, 0x0000 }, /* R20535 - DACR_RETUNE_C28_0 */
640 { 20536, 0x0000 }, /* R20536 - DACR_RETUNE_C29_1 */
641 { 20537, 0x0000 }, /* R20537 - DACR_RETUNE_C29_0 */
642 { 20538, 0x0000 }, /* R20538 - DACR_RETUNE_C30_1 */
643 { 20539, 0x0000 }, /* R20539 - DACR_RETUNE_C30_0 */
644 { 20540, 0x0000 }, /* R20540 - DACR_RETUNE_C31_1 */
645 { 20541, 0x0000 }, /* R20541 - DACR_RETUNE_C31_0 */
646 { 20542, 0x0000 }, /* R20542 - DACR_RETUNE_C32_1 */
647 { 20543, 0x0000 }, /* R20543 - DACR_RETUNE_C32_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]648
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]649 { 20992, 0x008C }, /* R20992 - VSS_XHD2_1 */
650 { 20993, 0x0200 }, /* R20993 - VSS_XHD2_0 */
651 { 20994, 0x0035 }, /* R20994 - VSS_XHD3_1 */
652 { 20995, 0x0700 }, /* R20995 - VSS_XHD3_0 */
653 { 20996, 0x003A }, /* R20996 - VSS_XHN1_1 */
654 { 20997, 0x4100 }, /* R20997 - VSS_XHN1_0 */
655 { 20998, 0x008B }, /* R20998 - VSS_XHN2_1 */
656 { 20999, 0x7D00 }, /* R20999 - VSS_XHN2_0 */
657 { 21000, 0x003A }, /* R21000 - VSS_XHN3_1 */
658 { 21001, 0x4100 }, /* R21001 - VSS_XHN3_0 */
659 { 21002, 0x008C }, /* R21002 - VSS_XLA_1 */
660 { 21003, 0xFEE8 }, /* R21003 - VSS_XLA_0 */
661 { 21004, 0x0078 }, /* R21004 - VSS_XLB_1 */
662 { 21005, 0x0000 }, /* R21005 - VSS_XLB_0 */
663 { 21006, 0x003F }, /* R21006 - VSS_XLG_1 */
664 { 21007, 0xB260 }, /* R21007 - VSS_XLG_0 */
665 { 21008, 0x002D }, /* R21008 - VSS_PG2_1 */
666 { 21009, 0x1818 }, /* R21009 - VSS_PG2_0 */
667 { 21010, 0x0020 }, /* R21010 - VSS_PG_1 */
668 { 21011, 0x0000 }, /* R21011 - VSS_PG_0 */
669 { 21012, 0x00F1 }, /* R21012 - VSS_XTD1_1 */
670 { 21013, 0x8340 }, /* R21013 - VSS_XTD1_0 */
671 { 21014, 0x00FB }, /* R21014 - VSS_XTD2_1 */
672 { 21015, 0x8300 }, /* R21015 - VSS_XTD2_0 */
673 { 21016, 0x00EE }, /* R21016 - VSS_XTD3_1 */
674 { 21017, 0xAEC0 }, /* R21017 - VSS_XTD3_0 */
675 { 21018, 0x00FB }, /* R21018 - VSS_XTD4_1 */
676 { 21019, 0xAC40 }, /* R21019 - VSS_XTD4_0 */
677 { 21020, 0x00F1 }, /* R21020 - VSS_XTD5_1 */
678 { 21021, 0x7F80 }, /* R21021 - VSS_XTD5_0 */
679 { 21022, 0x00F4 }, /* R21022 - VSS_XTD6_1 */
680 { 21023, 0x3B40 }, /* R21023 - VSS_XTD6_0 */
681 { 21024, 0x00F5 }, /* R21024 - VSS_XTD7_1 */
682 { 21025, 0xFB00 }, /* R21025 - VSS_XTD7_0 */
683 { 21026, 0x00EA }, /* R21026 - VSS_XTD8_1 */
684 { 21027, 0x10C0 }, /* R21027 - VSS_XTD8_0 */
685 { 21028, 0x00FC }, /* R21028 - VSS_XTD9_1 */
686 { 21029, 0xC580 }, /* R21029 - VSS_XTD9_0 */
687 { 21030, 0x00E2 }, /* R21030 - VSS_XTD10_1 */
688 { 21031, 0x75C0 }, /* R21031 - VSS_XTD10_0 */
689 { 21032, 0x0004 }, /* R21032 - VSS_XTD11_1 */
690 { 21033, 0xB480 }, /* R21033 - VSS_XTD11_0 */
691 { 21034, 0x00D4 }, /* R21034 - VSS_XTD12_1 */
692 { 21035, 0xF980 }, /* R21035 - VSS_XTD12_0 */
693 { 21036, 0x0004 }, /* R21036 - VSS_XTD13_1 */
694 { 21037, 0x9140 }, /* R21037 - VSS_XTD13_0 */
695 { 21038, 0x00D8 }, /* R21038 - VSS_XTD14_1 */
696 { 21039, 0xA480 }, /* R21039 - VSS_XTD14_0 */
697 { 21040, 0x0002 }, /* R21040 - VSS_XTD15_1 */
698 { 21041, 0x3DC0 }, /* R21041 - VSS_XTD15_0 */
699 { 21042, 0x00CF }, /* R21042 - VSS_XTD16_1 */
700 { 21043, 0x7A80 }, /* R21043 - VSS_XTD16_0 */
701 { 21044, 0x00DC }, /* R21044 - VSS_XTD17_1 */
702 { 21045, 0x0600 }, /* R21045 - VSS_XTD17_0 */
703 { 21046, 0x00F2 }, /* R21046 - VSS_XTD18_1 */
704 { 21047, 0xDAC0 }, /* R21047 - VSS_XTD18_0 */
705 { 21048, 0x00BA }, /* R21048 - VSS_XTD19_1 */
706 { 21049, 0xF340 }, /* R21049 - VSS_XTD19_0 */
707 { 21050, 0x000A }, /* R21050 - VSS_XTD20_1 */
708 { 21051, 0x7940 }, /* R21051 - VSS_XTD20_0 */
709 { 21052, 0x001C }, /* R21052 - VSS_XTD21_1 */
710 { 21053, 0x0680 }, /* R21053 - VSS_XTD21_0 */
711 { 21054, 0x00FD }, /* R21054 - VSS_XTD22_1 */
712 { 21055, 0x2D00 }, /* R21055 - VSS_XTD22_0 */
713 { 21056, 0x001C }, /* R21056 - VSS_XTD23_1 */
714 { 21057, 0xE840 }, /* R21057 - VSS_XTD23_0 */
715 { 21058, 0x000D }, /* R21058 - VSS_XTD24_1 */
716 { 21059, 0xDC40 }, /* R21059 - VSS_XTD24_0 */
717 { 21060, 0x00FC }, /* R21060 - VSS_XTD25_1 */
718 { 21061, 0x9D00 }, /* R21061 - VSS_XTD25_0 */
719 { 21062, 0x0009 }, /* R21062 - VSS_XTD26_1 */
720 { 21063, 0x5580 }, /* R21063 - VSS_XTD26_0 */
721 { 21064, 0x00FE }, /* R21064 - VSS_XTD27_1 */
722 { 21065, 0x7E80 }, /* R21065 - VSS_XTD27_0 */
723 { 21066, 0x000E }, /* R21066 - VSS_XTD28_1 */
724 { 21067, 0xAB40 }, /* R21067 - VSS_XTD28_0 */
725 { 21068, 0x00F9 }, /* R21068 - VSS_XTD29_1 */
726 { 21069, 0x9880 }, /* R21069 - VSS_XTD29_0 */
727 { 21070, 0x0009 }, /* R21070 - VSS_XTD30_1 */
728 { 21071, 0x87C0 }, /* R21071 - VSS_XTD30_0 */
729 { 21072, 0x00FD }, /* R21072 - VSS_XTD31_1 */
730 { 21073, 0x2C40 }, /* R21073 - VSS_XTD31_0 */
731 { 21074, 0x0009 }, /* R21074 - VSS_XTD32_1 */
732 { 21075, 0x4800 }, /* R21075 - VSS_XTD32_0 */
733 { 21076, 0x0003 }, /* R21076 - VSS_XTS1_1 */
734 { 21077, 0x5F40 }, /* R21077 - VSS_XTS1_0 */
735 { 21078, 0x0000 }, /* R21078 - VSS_XTS2_1 */
736 { 21079, 0x8700 }, /* R21079 - VSS_XTS2_0 */
737 { 21080, 0x00FA }, /* R21080 - VSS_XTS3_1 */
738 { 21081, 0xE4C0 }, /* R21081 - VSS_XTS3_0 */
739 { 21082, 0x0000 }, /* R21082 - VSS_XTS4_1 */
740 { 21083, 0x0B40 }, /* R21083 - VSS_XTS4_0 */
741 { 21084, 0x0004 }, /* R21084 - VSS_XTS5_1 */
742 { 21085, 0xE180 }, /* R21085 - VSS_XTS5_0 */
743 { 21086, 0x0001 }, /* R21086 - VSS_XTS6_1 */
744 { 21087, 0x1F40 }, /* R21087 - VSS_XTS6_0 */
745 { 21088, 0x00F8 }, /* R21088 - VSS_XTS7_1 */
746 { 21089, 0xB000 }, /* R21089 - VSS_XTS7_0 */
747 { 21090, 0x00FB }, /* R21090 - VSS_XTS8_1 */
748 { 21091, 0xCBC0 }, /* R21091 - VSS_XTS8_0 */
749 { 21092, 0x0004 }, /* R21092 - VSS_XTS9_1 */
750 { 21093, 0xF380 }, /* R21093 - VSS_XTS9_0 */
751 { 21094, 0x0007 }, /* R21094 - VSS_XTS10_1 */
752 { 21095, 0xDF40 }, /* R21095 - VSS_XTS10_0 */
753 { 21096, 0x00FF }, /* R21096 - VSS_XTS11_1 */
754 { 21097, 0x0700 }, /* R21097 - VSS_XTS11_0 */
755 { 21098, 0x00EF }, /* R21098 - VSS_XTS12_1 */
756 { 21099, 0xD700 }, /* R21099 - VSS_XTS12_0 */
757 { 21100, 0x00FB }, /* R21100 - VSS_XTS13_1 */
758 { 21101, 0xAF40 }, /* R21101 - VSS_XTS13_0 */
759 { 21102, 0x0010 }, /* R21102 - VSS_XTS14_1 */
760 { 21103, 0x8A80 }, /* R21103 - VSS_XTS14_0 */
761 { 21104, 0x0011 }, /* R21104 - VSS_XTS15_1 */
762 { 21105, 0x07C0 }, /* R21105 - VSS_XTS15_0 */
763 { 21106, 0x00E0 }, /* R21106 - VSS_XTS16_1 */
764 { 21107, 0x0800 }, /* R21107 - VSS_XTS16_0 */
765 { 21108, 0x00D2 }, /* R21108 - VSS_XTS17_1 */
766 { 21109, 0x7600 }, /* R21109 - VSS_XTS17_0 */
767 { 21110, 0x0020 }, /* R21110 - VSS_XTS18_1 */
768 { 21111, 0xCF40 }, /* R21111 - VSS_XTS18_0 */
769 { 21112, 0x0030 }, /* R21112 - VSS_XTS19_1 */
770 { 21113, 0x2340 }, /* R21113 - VSS_XTS19_0 */
771 { 21114, 0x00FD }, /* R21114 - VSS_XTS20_1 */
772 { 21115, 0x69C0 }, /* R21115 - VSS_XTS20_0 */
773 { 21116, 0x0028 }, /* R21116 - VSS_XTS21_1 */
774 { 21117, 0x3500 }, /* R21117 - VSS_XTS21_0 */
775 { 21118, 0x0006 }, /* R21118 - VSS_XTS22_1 */
776 { 21119, 0x3300 }, /* R21119 - VSS_XTS22_0 */
777 { 21120, 0x00D9 }, /* R21120 - VSS_XTS23_1 */
778 { 21121, 0xF6C0 }, /* R21121 - VSS_XTS23_0 */
779 { 21122, 0x00F3 }, /* R21122 - VSS_XTS24_1 */
780 { 21123, 0x3340 }, /* R21123 - VSS_XTS24_0 */
781 { 21124, 0x000F }, /* R21124 - VSS_XTS25_1 */
782 { 21125, 0x4200 }, /* R21125 - VSS_XTS25_0 */
783 { 21126, 0x0004 }, /* R21126 - VSS_XTS26_1 */
784 { 21127, 0x0C80 }, /* R21127 - VSS_XTS26_0 */
785 { 21128, 0x00FB }, /* R21128 - VSS_XTS27_1 */
786 { 21129, 0x3F80 }, /* R21129 - VSS_XTS27_0 */
787 { 21130, 0x00F7 }, /* R21130 - VSS_XTS28_1 */
788 { 21131, 0x57C0 }, /* R21131 - VSS_XTS28_0 */
789 { 21132, 0x0003 }, /* R21132 - VSS_XTS29_1 */
790 { 21133, 0x5400 }, /* R21133 - VSS_XTS29_0 */
791 { 21134, 0x0000 }, /* R21134 - VSS_XTS30_1 */
792 { 21135, 0xC6C0 }, /* R21135 - VSS_XTS30_0 */
793 { 21136, 0x0003 }, /* R21136 - VSS_XTS31_1 */
794 { 21137, 0x12C0 }, /* R21137 - VSS_XTS31_0 */
795 { 21138, 0x00FD }, /* R21138 - VSS_XTS32_1 */
796 { 21139, 0x8580 }, /* R21139 - VSS_XTS32_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]797};
798
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]799static bool wm8962_volatile_register(struct device *dev, unsigned int reg)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]800{
Mark Browncef6d1d2012-01-11 20:13:19 -0800[diff] [blame]801 switch (reg) {
802 case WM8962_CLOCKING1:
803 case WM8962_CLOCKING2:
804 case WM8962_SOFTWARE_RESET:
805 case WM8962_ALC2:
806 case WM8962_THERMAL_SHUTDOWN_STATUS:
807 case WM8962_ADDITIONAL_CONTROL_4:
808 case WM8962_CLASS_D_CONTROL_1:
809 case WM8962_DC_SERVO_6:
810 case WM8962_INTERRUPT_STATUS_1:
811 case WM8962_INTERRUPT_STATUS_2:
812 case WM8962_DSP2_EXECCONTROL:
813 return true;
814 default:
815 return false;
816 }
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]817}
818
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]819static bool wm8962_readable_register(struct device *dev, unsigned int reg)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]820{
Mark Browncef6d1d2012-01-11 20:13:19 -0800[diff] [blame]821 switch (reg) {
822 case WM8962_LEFT_INPUT_VOLUME:
823 case WM8962_RIGHT_INPUT_VOLUME:
824 case WM8962_HPOUTL_VOLUME:
825 case WM8962_HPOUTR_VOLUME:
826 case WM8962_CLOCKING1:
827 case WM8962_ADC_DAC_CONTROL_1:
828 case WM8962_ADC_DAC_CONTROL_2:
829 case WM8962_AUDIO_INTERFACE_0:
830 case WM8962_CLOCKING2:
831 case WM8962_AUDIO_INTERFACE_1:
832 case WM8962_LEFT_DAC_VOLUME:
833 case WM8962_RIGHT_DAC_VOLUME:
834 case WM8962_AUDIO_INTERFACE_2:
835 case WM8962_SOFTWARE_RESET:
836 case WM8962_ALC1:
837 case WM8962_ALC2:
838 case WM8962_ALC3:
839 case WM8962_NOISE_GATE:
840 case WM8962_LEFT_ADC_VOLUME:
841 case WM8962_RIGHT_ADC_VOLUME:
842 case WM8962_ADDITIONAL_CONTROL_1:
843 case WM8962_ADDITIONAL_CONTROL_2:
844 case WM8962_PWR_MGMT_1:
845 case WM8962_PWR_MGMT_2:
846 case WM8962_ADDITIONAL_CONTROL_3:
847 case WM8962_ANTI_POP:
848 case WM8962_CLOCKING_3:
849 case WM8962_INPUT_MIXER_CONTROL_1:
850 case WM8962_LEFT_INPUT_MIXER_VOLUME:
851 case WM8962_RIGHT_INPUT_MIXER_VOLUME:
852 case WM8962_INPUT_MIXER_CONTROL_2:
853 case WM8962_INPUT_BIAS_CONTROL:
854 case WM8962_LEFT_INPUT_PGA_CONTROL:
855 case WM8962_RIGHT_INPUT_PGA_CONTROL:
856 case WM8962_SPKOUTL_VOLUME:
857 case WM8962_SPKOUTR_VOLUME:
858 case WM8962_THERMAL_SHUTDOWN_STATUS:
859 case WM8962_ADDITIONAL_CONTROL_4:
860 case WM8962_CLASS_D_CONTROL_1:
861 case WM8962_CLASS_D_CONTROL_2:
862 case WM8962_CLOCKING_4:
863 case WM8962_DAC_DSP_MIXING_1:
864 case WM8962_DAC_DSP_MIXING_2:
865 case WM8962_DC_SERVO_0:
866 case WM8962_DC_SERVO_1:
867 case WM8962_DC_SERVO_4:
868 case WM8962_DC_SERVO_6:
869 case WM8962_ANALOGUE_PGA_BIAS:
870 case WM8962_ANALOGUE_HP_0:
871 case WM8962_ANALOGUE_HP_2:
872 case WM8962_CHARGE_PUMP_1:
873 case WM8962_CHARGE_PUMP_B:
874 case WM8962_WRITE_SEQUENCER_CONTROL_1:
875 case WM8962_WRITE_SEQUENCER_CONTROL_2:
876 case WM8962_WRITE_SEQUENCER_CONTROL_3:
877 case WM8962_CONTROL_INTERFACE:
878 case WM8962_MIXER_ENABLES:
879 case WM8962_HEADPHONE_MIXER_1:
880 case WM8962_HEADPHONE_MIXER_2:
881 case WM8962_HEADPHONE_MIXER_3:
882 case WM8962_HEADPHONE_MIXER_4:
883 case WM8962_SPEAKER_MIXER_1:
884 case WM8962_SPEAKER_MIXER_2:
885 case WM8962_SPEAKER_MIXER_3:
886 case WM8962_SPEAKER_MIXER_4:
887 case WM8962_SPEAKER_MIXER_5:
888 case WM8962_BEEP_GENERATOR_1:
889 case WM8962_OSCILLATOR_TRIM_3:
890 case WM8962_OSCILLATOR_TRIM_4:
891 case WM8962_OSCILLATOR_TRIM_7:
892 case WM8962_ANALOGUE_CLOCKING1:
893 case WM8962_ANALOGUE_CLOCKING2:
894 case WM8962_ANALOGUE_CLOCKING3:
895 case WM8962_PLL_SOFTWARE_RESET:
896 case WM8962_PLL2:
897 case WM8962_PLL_4:
898 case WM8962_PLL_9:
899 case WM8962_PLL_10:
900 case WM8962_PLL_11:
901 case WM8962_PLL_12:
902 case WM8962_PLL_13:
903 case WM8962_PLL_14:
904 case WM8962_PLL_15:
905 case WM8962_PLL_16:
906 case WM8962_FLL_CONTROL_1:
907 case WM8962_FLL_CONTROL_2:
908 case WM8962_FLL_CONTROL_3:
909 case WM8962_FLL_CONTROL_5:
910 case WM8962_FLL_CONTROL_6:
911 case WM8962_FLL_CONTROL_7:
912 case WM8962_FLL_CONTROL_8:
913 case WM8962_GENERAL_TEST_1:
914 case WM8962_DF1:
915 case WM8962_DF2:
916 case WM8962_DF3:
917 case WM8962_DF4:
918 case WM8962_DF5:
919 case WM8962_DF6:
920 case WM8962_DF7:
921 case WM8962_LHPF1:
922 case WM8962_LHPF2:
923 case WM8962_THREED1:
924 case WM8962_THREED2:
925 case WM8962_THREED3:
926 case WM8962_THREED4:
927 case WM8962_DRC_1:
928 case WM8962_DRC_2:
929 case WM8962_DRC_3:
930 case WM8962_DRC_4:
931 case WM8962_DRC_5:
932 case WM8962_TLOOPBACK:
933 case WM8962_EQ1:
934 case WM8962_EQ2:
935 case WM8962_EQ3:
936 case WM8962_EQ4:
937 case WM8962_EQ5:
938 case WM8962_EQ6:
939 case WM8962_EQ7:
940 case WM8962_EQ8:
941 case WM8962_EQ9:
942 case WM8962_EQ10:
943 case WM8962_EQ11:
944 case WM8962_EQ12:
945 case WM8962_EQ13:
946 case WM8962_EQ14:
947 case WM8962_EQ15:
948 case WM8962_EQ16:
949 case WM8962_EQ17:
950 case WM8962_EQ18:
951 case WM8962_EQ19:
952 case WM8962_EQ20:
953 case WM8962_EQ21:
954 case WM8962_EQ22:
955 case WM8962_EQ23:
956 case WM8962_EQ24:
957 case WM8962_EQ25:
958 case WM8962_EQ26:
959 case WM8962_EQ27:
960 case WM8962_EQ28:
961 case WM8962_EQ29:
962 case WM8962_EQ30:
963 case WM8962_EQ31:
964 case WM8962_EQ32:
965 case WM8962_EQ33:
966 case WM8962_EQ34:
967 case WM8962_EQ35:
968 case WM8962_EQ36:
969 case WM8962_EQ37:
970 case WM8962_EQ38:
971 case WM8962_EQ39:
972 case WM8962_EQ40:
973 case WM8962_EQ41:
974 case WM8962_GPIO_BASE:
975 case WM8962_GPIO_2:
976 case WM8962_GPIO_3:
977 case WM8962_GPIO_5:
978 case WM8962_GPIO_6:
979 case WM8962_INTERRUPT_STATUS_1:
980 case WM8962_INTERRUPT_STATUS_2:
981 case WM8962_INTERRUPT_STATUS_1_MASK:
982 case WM8962_INTERRUPT_STATUS_2_MASK:
983 case WM8962_INTERRUPT_CONTROL:
984 case WM8962_IRQ_DEBOUNCE:
985 case WM8962_MICINT_SOURCE_POL:
986 case WM8962_DSP2_POWER_MANAGEMENT:
987 case WM8962_DSP2_EXECCONTROL:
988 case WM8962_DSP2_INSTRUCTION_RAM_0:
989 case WM8962_DSP2_ADDRESS_RAM_2:
990 case WM8962_DSP2_ADDRESS_RAM_1:
991 case WM8962_DSP2_ADDRESS_RAM_0:
992 case WM8962_DSP2_DATA1_RAM_1:
993 case WM8962_DSP2_DATA1_RAM_0:
994 case WM8962_DSP2_DATA2_RAM_1:
995 case WM8962_DSP2_DATA2_RAM_0:
996 case WM8962_DSP2_DATA3_RAM_1:
997 case WM8962_DSP2_DATA3_RAM_0:
998 case WM8962_DSP2_COEFF_RAM_0:
999 case WM8962_RETUNEADC_SHARED_COEFF_1:
1000 case WM8962_RETUNEADC_SHARED_COEFF_0:
1001 case WM8962_RETUNEDAC_SHARED_COEFF_1:
1002 case WM8962_RETUNEDAC_SHARED_COEFF_0:
1003 case WM8962_SOUNDSTAGE_ENABLES_1:
1004 case WM8962_SOUNDSTAGE_ENABLES_0:
1005 case WM8962_HDBASS_AI_1:
1006 case WM8962_HDBASS_AI_0:
1007 case WM8962_HDBASS_AR_1:
1008 case WM8962_HDBASS_AR_0:
1009 case WM8962_HDBASS_B_1:
1010 case WM8962_HDBASS_B_0:
1011 case WM8962_HDBASS_K_1:
1012 case WM8962_HDBASS_K_0:
1013 case WM8962_HDBASS_N1_1:
1014 case WM8962_HDBASS_N1_0:
1015 case WM8962_HDBASS_N2_1:
1016 case WM8962_HDBASS_N2_0:
1017 case WM8962_HDBASS_N3_1:
1018 case WM8962_HDBASS_N3_0:
1019 case WM8962_HDBASS_N4_1:
1020 case WM8962_HDBASS_N4_0:
1021 case WM8962_HDBASS_N5_1:
1022 case WM8962_HDBASS_N5_0:
1023 case WM8962_HDBASS_X1_1:
1024 case WM8962_HDBASS_X1_0:
1025 case WM8962_HDBASS_X2_1:
1026 case WM8962_HDBASS_X2_0:
1027 case WM8962_HDBASS_X3_1:
1028 case WM8962_HDBASS_X3_0:
1029 case WM8962_HDBASS_ATK_1:
1030 case WM8962_HDBASS_ATK_0:
1031 case WM8962_HDBASS_DCY_1:
1032 case WM8962_HDBASS_DCY_0:
1033 case WM8962_HDBASS_PG_1:
1034 case WM8962_HDBASS_PG_0:
1035 case WM8962_HPF_C_1:
1036 case WM8962_HPF_C_0:
1037 case WM8962_ADCL_RETUNE_C1_1:
1038 case WM8962_ADCL_RETUNE_C1_0:
1039 case WM8962_ADCL_RETUNE_C2_1:
1040 case WM8962_ADCL_RETUNE_C2_0:
1041 case WM8962_ADCL_RETUNE_C3_1:
1042 case WM8962_ADCL_RETUNE_C3_0:
1043 case WM8962_ADCL_RETUNE_C4_1:
1044 case WM8962_ADCL_RETUNE_C4_0:
1045 case WM8962_ADCL_RETUNE_C5_1:
1046 case WM8962_ADCL_RETUNE_C5_0:
1047 case WM8962_ADCL_RETUNE_C6_1:
1048 case WM8962_ADCL_RETUNE_C6_0:
1049 case WM8962_ADCL_RETUNE_C7_1:
1050 case WM8962_ADCL_RETUNE_C7_0:
1051 case WM8962_ADCL_RETUNE_C8_1:
1052 case WM8962_ADCL_RETUNE_C8_0:
1053 case WM8962_ADCL_RETUNE_C9_1:
1054 case WM8962_ADCL_RETUNE_C9_0:
1055 case WM8962_ADCL_RETUNE_C10_1:
1056 case WM8962_ADCL_RETUNE_C10_0:
1057 case WM8962_ADCL_RETUNE_C11_1:
1058 case WM8962_ADCL_RETUNE_C11_0:
1059 case WM8962_ADCL_RETUNE_C12_1:
1060 case WM8962_ADCL_RETUNE_C12_0:
1061 case WM8962_ADCL_RETUNE_C13_1:
1062 case WM8962_ADCL_RETUNE_C13_0:
1063 case WM8962_ADCL_RETUNE_C14_1:
1064 case WM8962_ADCL_RETUNE_C14_0:
1065 case WM8962_ADCL_RETUNE_C15_1:
1066 case WM8962_ADCL_RETUNE_C15_0:
1067 case WM8962_ADCL_RETUNE_C16_1:
1068 case WM8962_ADCL_RETUNE_C16_0:
1069 case WM8962_ADCL_RETUNE_C17_1:
1070 case WM8962_ADCL_RETUNE_C17_0:
1071 case WM8962_ADCL_RETUNE_C18_1:
1072 case WM8962_ADCL_RETUNE_C18_0:
1073 case WM8962_ADCL_RETUNE_C19_1:
1074 case WM8962_ADCL_RETUNE_C19_0:
1075 case WM8962_ADCL_RETUNE_C20_1:
1076 case WM8962_ADCL_RETUNE_C20_0:
1077 case WM8962_ADCL_RETUNE_C21_1:
1078 case WM8962_ADCL_RETUNE_C21_0:
1079 case WM8962_ADCL_RETUNE_C22_1:
1080 case WM8962_ADCL_RETUNE_C22_0:
1081 case WM8962_ADCL_RETUNE_C23_1:
1082 case WM8962_ADCL_RETUNE_C23_0:
1083 case WM8962_ADCL_RETUNE_C24_1:
1084 case WM8962_ADCL_RETUNE_C24_0:
1085 case WM8962_ADCL_RETUNE_C25_1:
1086 case WM8962_ADCL_RETUNE_C25_0:
1087 case WM8962_ADCL_RETUNE_C26_1:
1088 case WM8962_ADCL_RETUNE_C26_0:
1089 case WM8962_ADCL_RETUNE_C27_1:
1090 case WM8962_ADCL_RETUNE_C27_0:
1091 case WM8962_ADCL_RETUNE_C28_1:
1092 case WM8962_ADCL_RETUNE_C28_0:
1093 case WM8962_ADCL_RETUNE_C29_1:
1094 case WM8962_ADCL_RETUNE_C29_0:
1095 case WM8962_ADCL_RETUNE_C30_1:
1096 case WM8962_ADCL_RETUNE_C30_0:
1097 case WM8962_ADCL_RETUNE_C31_1:
1098 case WM8962_ADCL_RETUNE_C31_0:
1099 case WM8962_ADCL_RETUNE_C32_1:
1100 case WM8962_ADCL_RETUNE_C32_0:
1101 case WM8962_RETUNEADC_PG2_1:
1102 case WM8962_RETUNEADC_PG2_0:
1103 case WM8962_RETUNEADC_PG_1:
1104 case WM8962_RETUNEADC_PG_0:
1105 case WM8962_ADCR_RETUNE_C1_1:
1106 case WM8962_ADCR_RETUNE_C1_0:
1107 case WM8962_ADCR_RETUNE_C2_1:
1108 case WM8962_ADCR_RETUNE_C2_0:
1109 case WM8962_ADCR_RETUNE_C3_1:
1110 case WM8962_ADCR_RETUNE_C3_0:
1111 case WM8962_ADCR_RETUNE_C4_1:
1112 case WM8962_ADCR_RETUNE_C4_0:
1113 case WM8962_ADCR_RETUNE_C5_1:
1114 case WM8962_ADCR_RETUNE_C5_0:
1115 case WM8962_ADCR_RETUNE_C6_1:
1116 case WM8962_ADCR_RETUNE_C6_0:
1117 case WM8962_ADCR_RETUNE_C7_1:
1118 case WM8962_ADCR_RETUNE_C7_0:
1119 case WM8962_ADCR_RETUNE_C8_1:
1120 case WM8962_ADCR_RETUNE_C8_0:
1121 case WM8962_ADCR_RETUNE_C9_1:
1122 case WM8962_ADCR_RETUNE_C9_0:
1123 case WM8962_ADCR_RETUNE_C10_1:
1124 case WM8962_ADCR_RETUNE_C10_0:
1125 case WM8962_ADCR_RETUNE_C11_1:
1126 case WM8962_ADCR_RETUNE_C11_0:
1127 case WM8962_ADCR_RETUNE_C12_1:
1128 case WM8962_ADCR_RETUNE_C12_0:
1129 case WM8962_ADCR_RETUNE_C13_1:
1130 case WM8962_ADCR_RETUNE_C13_0:
1131 case WM8962_ADCR_RETUNE_C14_1:
1132 case WM8962_ADCR_RETUNE_C14_0:
1133 case WM8962_ADCR_RETUNE_C15_1:
1134 case WM8962_ADCR_RETUNE_C15_0:
1135 case WM8962_ADCR_RETUNE_C16_1:
1136 case WM8962_ADCR_RETUNE_C16_0:
1137 case WM8962_ADCR_RETUNE_C17_1:
1138 case WM8962_ADCR_RETUNE_C17_0:
1139 case WM8962_ADCR_RETUNE_C18_1:
1140 case WM8962_ADCR_RETUNE_C18_0:
1141 case WM8962_ADCR_RETUNE_C19_1:
1142 case WM8962_ADCR_RETUNE_C19_0:
1143 case WM8962_ADCR_RETUNE_C20_1:
1144 case WM8962_ADCR_RETUNE_C20_0:
1145 case WM8962_ADCR_RETUNE_C21_1:
1146 case WM8962_ADCR_RETUNE_C21_0:
1147 case WM8962_ADCR_RETUNE_C22_1:
1148 case WM8962_ADCR_RETUNE_C22_0:
1149 case WM8962_ADCR_RETUNE_C23_1:
1150 case WM8962_ADCR_RETUNE_C23_0:
1151 case WM8962_ADCR_RETUNE_C24_1:
1152 case WM8962_ADCR_RETUNE_C24_0:
1153 case WM8962_ADCR_RETUNE_C25_1:
1154 case WM8962_ADCR_RETUNE_C25_0:
1155 case WM8962_ADCR_RETUNE_C26_1:
1156 case WM8962_ADCR_RETUNE_C26_0:
1157 case WM8962_ADCR_RETUNE_C27_1:
1158 case WM8962_ADCR_RETUNE_C27_0:
1159 case WM8962_ADCR_RETUNE_C28_1:
1160 case WM8962_ADCR_RETUNE_C28_0:
1161 case WM8962_ADCR_RETUNE_C29_1:
1162 case WM8962_ADCR_RETUNE_C29_0:
1163 case WM8962_ADCR_RETUNE_C30_1:
1164 case WM8962_ADCR_RETUNE_C30_0:
1165 case WM8962_ADCR_RETUNE_C31_1:
1166 case WM8962_ADCR_RETUNE_C31_0:
1167 case WM8962_ADCR_RETUNE_C32_1:
1168 case WM8962_ADCR_RETUNE_C32_0:
1169 case WM8962_DACL_RETUNE_C1_1:
1170 case WM8962_DACL_RETUNE_C1_0:
1171 case WM8962_DACL_RETUNE_C2_1:
1172 case WM8962_DACL_RETUNE_C2_0:
1173 case WM8962_DACL_RETUNE_C3_1:
1174 case WM8962_DACL_RETUNE_C3_0:
1175 case WM8962_DACL_RETUNE_C4_1:
1176 case WM8962_DACL_RETUNE_C4_0:
1177 case WM8962_DACL_RETUNE_C5_1:
1178 case WM8962_DACL_RETUNE_C5_0:
1179 case WM8962_DACL_RETUNE_C6_1:
1180 case WM8962_DACL_RETUNE_C6_0:
1181 case WM8962_DACL_RETUNE_C7_1:
1182 case WM8962_DACL_RETUNE_C7_0:
1183 case WM8962_DACL_RETUNE_C8_1:
1184 case WM8962_DACL_RETUNE_C8_0:
1185 case WM8962_DACL_RETUNE_C9_1:
1186 case WM8962_DACL_RETUNE_C9_0:
1187 case WM8962_DACL_RETUNE_C10_1:
1188 case WM8962_DACL_RETUNE_C10_0:
1189 case WM8962_DACL_RETUNE_C11_1:
1190 case WM8962_DACL_RETUNE_C11_0:
1191 case WM8962_DACL_RETUNE_C12_1:
1192 case WM8962_DACL_RETUNE_C12_0:
1193 case WM8962_DACL_RETUNE_C13_1:
1194 case WM8962_DACL_RETUNE_C13_0:
1195 case WM8962_DACL_RETUNE_C14_1:
1196 case WM8962_DACL_RETUNE_C14_0:
1197 case WM8962_DACL_RETUNE_C15_1:
1198 case WM8962_DACL_RETUNE_C15_0:
1199 case WM8962_DACL_RETUNE_C16_1:
1200 case WM8962_DACL_RETUNE_C16_0:
1201 case WM8962_DACL_RETUNE_C17_1:
1202 case WM8962_DACL_RETUNE_C17_0:
1203 case WM8962_DACL_RETUNE_C18_1:
1204 case WM8962_DACL_RETUNE_C18_0:
1205 case WM8962_DACL_RETUNE_C19_1:
1206 case WM8962_DACL_RETUNE_C19_0:
1207 case WM8962_DACL_RETUNE_C20_1:
1208 case WM8962_DACL_RETUNE_C20_0:
1209 case WM8962_DACL_RETUNE_C21_1:
1210 case WM8962_DACL_RETUNE_C21_0:
1211 case WM8962_DACL_RETUNE_C22_1:
1212 case WM8962_DACL_RETUNE_C22_0:
1213 case WM8962_DACL_RETUNE_C23_1:
1214 case WM8962_DACL_RETUNE_C23_0:
1215 case WM8962_DACL_RETUNE_C24_1:
1216 case WM8962_DACL_RETUNE_C24_0:
1217 case WM8962_DACL_RETUNE_C25_1:
1218 case WM8962_DACL_RETUNE_C25_0:
1219 case WM8962_DACL_RETUNE_C26_1:
1220 case WM8962_DACL_RETUNE_C26_0:
1221 case WM8962_DACL_RETUNE_C27_1:
1222 case WM8962_DACL_RETUNE_C27_0:
1223 case WM8962_DACL_RETUNE_C28_1:
1224 case WM8962_DACL_RETUNE_C28_0:
1225 case WM8962_DACL_RETUNE_C29_1:
1226 case WM8962_DACL_RETUNE_C29_0:
1227 case WM8962_DACL_RETUNE_C30_1:
1228 case WM8962_DACL_RETUNE_C30_0:
1229 case WM8962_DACL_RETUNE_C31_1:
1230 case WM8962_DACL_RETUNE_C31_0:
1231 case WM8962_DACL_RETUNE_C32_1:
1232 case WM8962_DACL_RETUNE_C32_0:
1233 case WM8962_RETUNEDAC_PG2_1:
1234 case WM8962_RETUNEDAC_PG2_0:
1235 case WM8962_RETUNEDAC_PG_1:
1236 case WM8962_RETUNEDAC_PG_0:
1237 case WM8962_DACR_RETUNE_C1_1:
1238 case WM8962_DACR_RETUNE_C1_0:
1239 case WM8962_DACR_RETUNE_C2_1:
1240 case WM8962_DACR_RETUNE_C2_0:
1241 case WM8962_DACR_RETUNE_C3_1:
1242 case WM8962_DACR_RETUNE_C3_0:
1243 case WM8962_DACR_RETUNE_C4_1:
1244 case WM8962_DACR_RETUNE_C4_0:
1245 case WM8962_DACR_RETUNE_C5_1:
1246 case WM8962_DACR_RETUNE_C5_0:
1247 case WM8962_DACR_RETUNE_C6_1:
1248 case WM8962_DACR_RETUNE_C6_0:
1249 case WM8962_DACR_RETUNE_C7_1:
1250 case WM8962_DACR_RETUNE_C7_0:
1251 case WM8962_DACR_RETUNE_C8_1:
1252 case WM8962_DACR_RETUNE_C8_0:
1253 case WM8962_DACR_RETUNE_C9_1:
1254 case WM8962_DACR_RETUNE_C9_0:
1255 case WM8962_DACR_RETUNE_C10_1:
1256 case WM8962_DACR_RETUNE_C10_0:
1257 case WM8962_DACR_RETUNE_C11_1:
1258 case WM8962_DACR_RETUNE_C11_0:
1259 case WM8962_DACR_RETUNE_C12_1:
1260 case WM8962_DACR_RETUNE_C12_0:
1261 case WM8962_DACR_RETUNE_C13_1:
1262 case WM8962_DACR_RETUNE_C13_0:
1263 case WM8962_DACR_RETUNE_C14_1:
1264 case WM8962_DACR_RETUNE_C14_0:
1265 case WM8962_DACR_RETUNE_C15_1:
1266 case WM8962_DACR_RETUNE_C15_0:
1267 case WM8962_DACR_RETUNE_C16_1:
1268 case WM8962_DACR_RETUNE_C16_0:
1269 case WM8962_DACR_RETUNE_C17_1:
1270 case WM8962_DACR_RETUNE_C17_0:
1271 case WM8962_DACR_RETUNE_C18_1:
1272 case WM8962_DACR_RETUNE_C18_0:
1273 case WM8962_DACR_RETUNE_C19_1:
1274 case WM8962_DACR_RETUNE_C19_0:
1275 case WM8962_DACR_RETUNE_C20_1:
1276 case WM8962_DACR_RETUNE_C20_0:
1277 case WM8962_DACR_RETUNE_C21_1:
1278 case WM8962_DACR_RETUNE_C21_0:
1279 case WM8962_DACR_RETUNE_C22_1:
1280 case WM8962_DACR_RETUNE_C22_0:
1281 case WM8962_DACR_RETUNE_C23_1:
1282 case WM8962_DACR_RETUNE_C23_0:
1283 case WM8962_DACR_RETUNE_C24_1:
1284 case WM8962_DACR_RETUNE_C24_0:
1285 case WM8962_DACR_RETUNE_C25_1:
1286 case WM8962_DACR_RETUNE_C25_0:
1287 case WM8962_DACR_RETUNE_C26_1:
1288 case WM8962_DACR_RETUNE_C26_0:
1289 case WM8962_DACR_RETUNE_C27_1:
1290 case WM8962_DACR_RETUNE_C27_0:
1291 case WM8962_DACR_RETUNE_C28_1:
1292 case WM8962_DACR_RETUNE_C28_0:
1293 case WM8962_DACR_RETUNE_C29_1:
1294 case WM8962_DACR_RETUNE_C29_0:
1295 case WM8962_DACR_RETUNE_C30_1:
1296 case WM8962_DACR_RETUNE_C30_0:
1297 case WM8962_DACR_RETUNE_C31_1:
1298 case WM8962_DACR_RETUNE_C31_0:
1299 case WM8962_DACR_RETUNE_C32_1:
1300 case WM8962_DACR_RETUNE_C32_0:
1301 case WM8962_VSS_XHD2_1:
1302 case WM8962_VSS_XHD2_0:
1303 case WM8962_VSS_XHD3_1:
1304 case WM8962_VSS_XHD3_0:
1305 case WM8962_VSS_XHN1_1:
1306 case WM8962_VSS_XHN1_0:
1307 case WM8962_VSS_XHN2_1:
1308 case WM8962_VSS_XHN2_0:
1309 case WM8962_VSS_XHN3_1:
1310 case WM8962_VSS_XHN3_0:
1311 case WM8962_VSS_XLA_1:
1312 case WM8962_VSS_XLA_0:
1313 case WM8962_VSS_XLB_1:
1314 case WM8962_VSS_XLB_0:
1315 case WM8962_VSS_XLG_1:
1316 case WM8962_VSS_XLG_0:
1317 case WM8962_VSS_PG2_1:
1318 case WM8962_VSS_PG2_0:
1319 case WM8962_VSS_PG_1:
1320 case WM8962_VSS_PG_0:
1321 case WM8962_VSS_XTD1_1:
1322 case WM8962_VSS_XTD1_0:
1323 case WM8962_VSS_XTD2_1:
1324 case WM8962_VSS_XTD2_0:
1325 case WM8962_VSS_XTD3_1:
1326 case WM8962_VSS_XTD3_0:
1327 case WM8962_VSS_XTD4_1:
1328 case WM8962_VSS_XTD4_0:
1329 case WM8962_VSS_XTD5_1:
1330 case WM8962_VSS_XTD5_0:
1331 case WM8962_VSS_XTD6_1:
1332 case WM8962_VSS_XTD6_0:
1333 case WM8962_VSS_XTD7_1:
1334 case WM8962_VSS_XTD7_0:
1335 case WM8962_VSS_XTD8_1:
1336 case WM8962_VSS_XTD8_0:
1337 case WM8962_VSS_XTD9_1:
1338 case WM8962_VSS_XTD9_0:
1339 case WM8962_VSS_XTD10_1:
1340 case WM8962_VSS_XTD10_0:
1341 case WM8962_VSS_XTD11_1:
1342 case WM8962_VSS_XTD11_0:
1343 case WM8962_VSS_XTD12_1:
1344 case WM8962_VSS_XTD12_0:
1345 case WM8962_VSS_XTD13_1:
1346 case WM8962_VSS_XTD13_0:
1347 case WM8962_VSS_XTD14_1:
1348 case WM8962_VSS_XTD14_0:
1349 case WM8962_VSS_XTD15_1:
1350 case WM8962_VSS_XTD15_0:
1351 case WM8962_VSS_XTD16_1:
1352 case WM8962_VSS_XTD16_0:
1353 case WM8962_VSS_XTD17_1:
1354 case WM8962_VSS_XTD17_0:
1355 case WM8962_VSS_XTD18_1:
1356 case WM8962_VSS_XTD18_0:
1357 case WM8962_VSS_XTD19_1:
1358 case WM8962_VSS_XTD19_0:
1359 case WM8962_VSS_XTD20_1:
1360 case WM8962_VSS_XTD20_0:
1361 case WM8962_VSS_XTD21_1:
1362 case WM8962_VSS_XTD21_0:
1363 case WM8962_VSS_XTD22_1:
1364 case WM8962_VSS_XTD22_0:
1365 case WM8962_VSS_XTD23_1:
1366 case WM8962_VSS_XTD23_0:
1367 case WM8962_VSS_XTD24_1:
1368 case WM8962_VSS_XTD24_0:
1369 case WM8962_VSS_XTD25_1:
1370 case WM8962_VSS_XTD25_0:
1371 case WM8962_VSS_XTD26_1:
1372 case WM8962_VSS_XTD26_0:
1373 case WM8962_VSS_XTD27_1:
1374 case WM8962_VSS_XTD27_0:
1375 case WM8962_VSS_XTD28_1:
1376 case WM8962_VSS_XTD28_0:
1377 case WM8962_VSS_XTD29_1:
1378 case WM8962_VSS_XTD29_0:
1379 case WM8962_VSS_XTD30_1:
1380 case WM8962_VSS_XTD30_0:
1381 case WM8962_VSS_XTD31_1:
1382 case WM8962_VSS_XTD31_0:
1383 case WM8962_VSS_XTD32_1:
1384 case WM8962_VSS_XTD32_0:
1385 case WM8962_VSS_XTS1_1:
1386 case WM8962_VSS_XTS1_0:
1387 case WM8962_VSS_XTS2_1:
1388 case WM8962_VSS_XTS2_0:
1389 case WM8962_VSS_XTS3_1:
1390 case WM8962_VSS_XTS3_0:
1391 case WM8962_VSS_XTS4_1:
1392 case WM8962_VSS_XTS4_0:
1393 case WM8962_VSS_XTS5_1:
1394 case WM8962_VSS_XTS5_0:
1395 case WM8962_VSS_XTS6_1:
1396 case WM8962_VSS_XTS6_0:
1397 case WM8962_VSS_XTS7_1:
1398 case WM8962_VSS_XTS7_0:
1399 case WM8962_VSS_XTS8_1:
1400 case WM8962_VSS_XTS8_0:
1401 case WM8962_VSS_XTS9_1:
1402 case WM8962_VSS_XTS9_0:
1403 case WM8962_VSS_XTS10_1:
1404 case WM8962_VSS_XTS10_0:
1405 case WM8962_VSS_XTS11_1:
1406 case WM8962_VSS_XTS11_0:
1407 case WM8962_VSS_XTS12_1:
1408 case WM8962_VSS_XTS12_0:
1409 case WM8962_VSS_XTS13_1:
1410 case WM8962_VSS_XTS13_0:
1411 case WM8962_VSS_XTS14_1:
1412 case WM8962_VSS_XTS14_0:
1413 case WM8962_VSS_XTS15_1:
1414 case WM8962_VSS_XTS15_0:
1415 case WM8962_VSS_XTS16_1:
1416 case WM8962_VSS_XTS16_0:
1417 case WM8962_VSS_XTS17_1:
1418 case WM8962_VSS_XTS17_0:
1419 case WM8962_VSS_XTS18_1:
1420 case WM8962_VSS_XTS18_0:
1421 case WM8962_VSS_XTS19_1:
1422 case WM8962_VSS_XTS19_0:
1423 case WM8962_VSS_XTS20_1:
1424 case WM8962_VSS_XTS20_0:
1425 case WM8962_VSS_XTS21_1:
1426 case WM8962_VSS_XTS21_0:
1427 case WM8962_VSS_XTS22_1:
1428 case WM8962_VSS_XTS22_0:
1429 case WM8962_VSS_XTS23_1:
1430 case WM8962_VSS_XTS23_0:
1431 case WM8962_VSS_XTS24_1:
1432 case WM8962_VSS_XTS24_0:
1433 case WM8962_VSS_XTS25_1:
1434 case WM8962_VSS_XTS25_0:
1435 case WM8962_VSS_XTS26_1:
1436 case WM8962_VSS_XTS26_0:
1437 case WM8962_VSS_XTS27_1:
1438 case WM8962_VSS_XTS27_0:
1439 case WM8962_VSS_XTS28_1:
1440 case WM8962_VSS_XTS28_0:
1441 case WM8962_VSS_XTS29_1:
1442 case WM8962_VSS_XTS29_0:
1443 case WM8962_VSS_XTS30_1:
1444 case WM8962_VSS_XTS30_0:
1445 case WM8962_VSS_XTS31_1:
1446 case WM8962_VSS_XTS31_0:
1447 case WM8962_VSS_XTS32_1:
1448 case WM8962_VSS_XTS32_0:
1449 return true;
1450 default:
1451 return false;
1452 }
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1453}
1454
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]1455static int wm8962_reset(struct wm8962_priv *wm8962)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1456{
Mark Brown4f4488a2011-11-01 13:36:10 +0000[diff] [blame]1457 int ret;
1458
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]1459 ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243);
Mark Brown4f4488a2011-11-01 13:36:10 +0000[diff] [blame]1460 if (ret != 0)
1461 return ret;
1462
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]1463 return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1464}
1465
1466static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
1467static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
1468static const unsigned int mixinpga_tlv[] = {
Clemens Ladisch43e9dc72011-11-20 15:13:27 +0100[diff] [blame]1469 TLV_DB_RANGE_HEAD(5),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1470 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
1471 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
1472 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
1473 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
1474 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0),
1475};
1476static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
1477static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1478static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
1479static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
1480static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
1481static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
1482static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
1483static const unsigned int classd_tlv[] = {
Clemens Ladisch43e9dc72011-11-20 15:13:27 +0100[diff] [blame]1484 TLV_DB_RANGE_HEAD(2),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1485 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
1486 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
1487};
Mark Brown8f63aaa882011-06-07 23:14:37 +0100[diff] [blame]1488static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1489
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]1490static int wm8962_dsp2_write_config(struct snd_soc_codec *codec)
1491{
1492 return 0;
1493}
1494
1495static int wm8962_dsp2_set_enable(struct snd_soc_codec *codec, u16 val)
1496{
1497 u16 adcl = snd_soc_read(codec, WM8962_LEFT_ADC_VOLUME);
1498 u16 adcr = snd_soc_read(codec, WM8962_RIGHT_ADC_VOLUME);
1499 u16 dac = snd_soc_read(codec, WM8962_ADC_DAC_CONTROL_1);
1500
1501 /* Mute the ADCs and DACs */
1502 snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, 0);
1503 snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU);
1504 snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1505 WM8962_DAC_MUTE, WM8962_DAC_MUTE);
1506
1507 snd_soc_write(codec, WM8962_SOUNDSTAGE_ENABLES_0, val);
1508
1509 /* Restore the ADCs and DACs */
1510 snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, adcl);
1511 snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, adcr);
1512 snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1513 WM8962_DAC_MUTE, dac);
1514
1515 return 0;
1516}
1517
1518static int wm8962_dsp2_start(struct snd_soc_codec *codec)
1519{
1520 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1521
1522 wm8962_dsp2_write_config(codec);
1523
1524 snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR);
1525
1526 wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1527
1528 return 0;
1529}
1530
1531static int wm8962_dsp2_stop(struct snd_soc_codec *codec)
1532{
1533 wm8962_dsp2_set_enable(codec, 0);
1534
1535 snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP);
1536
1537 return 0;
1538}
1539
1540#define WM8962_DSP2_ENABLE(xname, xshift) \
1541{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1542 .info = wm8962_dsp2_ena_info, \
1543 .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \
1544 .private_value = xshift }
1545
1546static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol,
1547 struct snd_ctl_elem_info *uinfo)
1548{
1549 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1550
1551 uinfo->count = 1;
1552 uinfo->value.integer.min = 0;
1553 uinfo->value.integer.max = 1;
1554
1555 return 0;
1556}
1557
1558static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol,
1559 struct snd_ctl_elem_value *ucontrol)
1560{
1561 int shift = kcontrol->private_value;
1562 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1563 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1564
1565 ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift);
1566
1567 return 0;
1568}
1569
1570static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol,
1571 struct snd_ctl_elem_value *ucontrol)
1572{
1573 int shift = kcontrol->private_value;
1574 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1575 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1576 int old = wm8962->dsp2_ena;
1577 int ret = 0;
1578 int dsp2_running = snd_soc_read(codec, WM8962_DSP2_POWER_MANAGEMENT) &
1579 WM8962_DSP2_ENA;
1580
1581 mutex_lock(&codec->mutex);
1582
1583 if (ucontrol->value.integer.value[0])
1584 wm8962->dsp2_ena |= 1 << shift;
1585 else
1586 wm8962->dsp2_ena &= ~(1 << shift);
1587
1588 if (wm8962->dsp2_ena == old)
1589 goto out;
1590
1591 ret = 1;
1592
1593 if (dsp2_running) {
1594 if (wm8962->dsp2_ena)
1595 wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1596 else
1597 wm8962_dsp2_stop(codec);
1598 }
1599
1600out:
1601 mutex_unlock(&codec->mutex);
1602
1603 return ret;
1604}
1605
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1606/* The VU bits for the headphones are in a different register to the mute
1607 * bits and only take effect on the PGA if it is actually powered.
1608 */
1609static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
1610 struct snd_ctl_elem_value *ucontrol)
1611{
1612 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
Lars-Peter Clausen7f87e302010-12-28 21:38:01 +0100[diff] [blame]1613 u16 *reg_cache = codec->reg_cache;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1614 int ret;
1615
1616 /* Apply the update (if any) */
1617 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1618 if (ret == 0)
1619 return 0;
1620
1621 /* If the left PGA is enabled hit that VU bit... */
Mark Brown0f82bdf2011-06-07 23:42:04 +0100[diff] [blame]1622 if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTL_PGA_ENA)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1623 return snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
1624 reg_cache[WM8962_HPOUTL_VOLUME]);
1625
1626 /* ...otherwise the right. The VU is stereo. */
Mark Brown0f82bdf2011-06-07 23:42:04 +0100[diff] [blame]1627 if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTR_PGA_ENA)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1628 return snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
1629 reg_cache[WM8962_HPOUTR_VOLUME]);
1630
1631 return 0;
1632}
1633
1634/* The VU bits for the speakers are in a different register to the mute
1635 * bits and only take effect on the PGA if it is actually powered.
1636 */
1637static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
1638 struct snd_ctl_elem_value *ucontrol)
1639{
1640 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1641 int ret;
1642
1643 /* Apply the update (if any) */
1644 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1645 if (ret == 0)
1646 return 0;
1647
1648 /* If the left PGA is enabled hit that VU bit... */
Mark Brown38f3f312011-09-23 21:26:33 +0100[diff] [blame]1649 ret = snd_soc_read(codec, WM8962_PWR_MGMT_2);
1650 if (ret & WM8962_SPKOUTL_PGA_ENA) {
1651 snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
1652 snd_soc_read(codec, WM8962_SPKOUTL_VOLUME));
1653 return 1;
1654 }
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1655
1656 /* ...otherwise the right. The VU is stereo. */
Mark Brown38f3f312011-09-23 21:26:33 +0100[diff] [blame]1657 if (ret & WM8962_SPKOUTR_PGA_ENA)
1658 snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
1659 snd_soc_read(codec, WM8962_SPKOUTR_VOLUME));
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1660
Mark Brown38f3f312011-09-23 21:26:33 +0100[diff] [blame]1661 return 1;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1662}
1663
Mark Brown6be449e2011-04-26 16:04:37 +0100[diff] [blame]1664static const char *cap_hpf_mode_text[] = {
1665 "Hi-fi", "Application"
1666};
1667
1668static const struct soc_enum cap_hpf_mode =
1669 SOC_ENUM_SINGLE(WM8962_ADC_DAC_CONTROL_2, 10, 2, cap_hpf_mode_text);
1670
Mark Brown1ab63da2011-08-21 10:54:38 +0100[diff] [blame]1671
1672static const char *cap_lhpf_mode_text[] = {
1673 "LPF", "HPF"
1674};
1675
1676static const struct soc_enum cap_lhpf_mode =
1677 SOC_ENUM_SINGLE(WM8962_LHPF1, 1, 2, cap_lhpf_mode_text);
1678
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1679static const struct snd_kcontrol_new wm8962_snd_controls[] = {
1680SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
1681
1682SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
1683 mixin_tlv),
1684SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
1685 mixinpga_tlv),
1686SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
1687 mixin_tlv),
1688
1689SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
1690 mixin_tlv),
1691SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
1692 mixinpga_tlv),
1693SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
1694 mixin_tlv),
1695
1696SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
1697 WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
1698SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
1699 WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
1700SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
1701 WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
1702SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
1703 WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
Mark Brown6be449e2011-04-26 16:04:37 +0100[diff] [blame]1704SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1),
1705SOC_ENUM("Capture HPF Mode", cap_hpf_mode),
1706SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0),
Mark Brown1ab63da2011-08-21 10:54:38 +0100[diff] [blame]1707SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0),
1708SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1709
1710SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
1711 WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
1712
1713SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
1714 WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
1715SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
Mark Brown5f52ee42012-01-11 16:31:00 -0800[diff] [blame]1716SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0),
1717SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1718
1719SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
1720 5, 1, 0),
1721
1722SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
1723
1724SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
1725 WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
1726SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
1727 snd_soc_get_volsw, wm8962_put_hp_sw),
1728SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
1729 7, 1, 0),
1730SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
1731 hp_tlv),
1732
1733SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
1734 WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
1735
1736SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
1737 3, 7, 0, bypass_tlv),
1738SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
1739 0, 7, 0, bypass_tlv),
1740SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
1741 7, 1, 1, inmix_tlv),
1742SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
1743 6, 1, 1, inmix_tlv),
1744
1745SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
1746 3, 7, 0, bypass_tlv),
1747SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
1748 0, 7, 0, bypass_tlv),
1749SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
1750 7, 1, 1, inmix_tlv),
1751SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
1752 6, 1, 1, inmix_tlv),
1753
1754SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
1755 classd_tlv),
Mark Brown8f63aaa882011-06-07 23:14:37 +0100[diff] [blame]1756
1757SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0),
1758SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22,
1759 WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv),
1760SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22,
1761 WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv),
1762SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22,
1763 WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv),
1764SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23,
1765 WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv),
1766SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23,
1767 WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv),
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]1768
1769WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT),
1770WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT),
1771WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT),
1772WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1773};
1774
1775static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
1776SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
1777SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
1778 snd_soc_get_volsw, wm8962_put_spk_sw),
1779SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
1780
1781SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
1782SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1783 3, 7, 0, bypass_tlv),
1784SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1785 0, 7, 0, bypass_tlv),
1786SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1787 7, 1, 1, inmix_tlv),
1788SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1789 6, 1, 1, inmix_tlv),
1790SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1791 7, 1, 0, inmix_tlv),
1792SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1793 6, 1, 0, inmix_tlv),
1794};
1795
1796static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
1797SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
1798 WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
1799SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
1800 snd_soc_get_volsw, wm8962_put_spk_sw),
1801SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
1802 7, 1, 0),
1803
1804SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
1805 WM8962_SPEAKER_MIXER_4, 8, 1, 1),
1806
1807SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1808 3, 7, 0, bypass_tlv),
1809SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1810 0, 7, 0, bypass_tlv),
1811SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1812 7, 1, 1, inmix_tlv),
1813SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1814 6, 1, 1, inmix_tlv),
1815SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1816 7, 1, 0, inmix_tlv),
1817SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1818 6, 1, 0, inmix_tlv),
1819
1820SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
1821 3, 7, 0, bypass_tlv),
1822SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
1823 0, 7, 0, bypass_tlv),
1824SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
1825 7, 1, 1, inmix_tlv),
1826SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
1827 6, 1, 1, inmix_tlv),
1828SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1829 5, 1, 0, inmix_tlv),
1830SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1831 4, 1, 0, inmix_tlv),
1832};
1833
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1834static int cp_event(struct snd_soc_dapm_widget *w,
1835 struct snd_kcontrol *kcontrol, int event)
1836{
1837 switch (event) {
1838 case SND_SOC_DAPM_POST_PMU:
1839 msleep(5);
1840 break;
1841
1842 default:
1843 BUG();
1844 return -EINVAL;
1845 }
1846
1847 return 0;
1848}
1849
1850static int hp_event(struct snd_soc_dapm_widget *w,
1851 struct snd_kcontrol *kcontrol, int event)
1852{
1853 struct snd_soc_codec *codec = w->codec;
1854 int timeout;
1855 int reg;
1856 int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
1857 WM8962_DCS_STARTUP_DONE_HP1R);
1858
1859 switch (event) {
1860 case SND_SOC_DAPM_POST_PMU:
1861 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1862 WM8962_HP1L_ENA | WM8962_HP1R_ENA,
1863 WM8962_HP1L_ENA | WM8962_HP1R_ENA);
1864 udelay(20);
1865
1866 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1867 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
1868 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
1869
1870 /* Start the DC servo */
1871 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1872 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1873 WM8962_HP1L_DCS_STARTUP |
1874 WM8962_HP1R_DCS_STARTUP,
1875 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1876 WM8962_HP1L_DCS_STARTUP |
1877 WM8962_HP1R_DCS_STARTUP);
1878
1879 /* Wait for it to complete, should be well under 100ms */
1880 timeout = 0;
1881 do {
1882 msleep(1);
1883 reg = snd_soc_read(codec, WM8962_DC_SERVO_6);
1884 if (reg < 0) {
1885 dev_err(codec->dev,
1886 "Failed to read DCS status: %d\n",
1887 reg);
1888 continue;
1889 }
1890 dev_dbg(codec->dev, "DCS status: %x\n", reg);
1891 } while (++timeout < 200 && (reg & expected) != expected);
1892
1893 if ((reg & expected) != expected)
1894 dev_err(codec->dev, "DC servo timed out\n");
1895 else
1896 dev_dbg(codec->dev, "DC servo complete after %dms\n",
1897 timeout);
1898
1899 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1900 WM8962_HP1L_ENA_OUTP |
1901 WM8962_HP1R_ENA_OUTP,
1902 WM8962_HP1L_ENA_OUTP |
1903 WM8962_HP1R_ENA_OUTP);
1904 udelay(20);
1905
1906 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1907 WM8962_HP1L_RMV_SHORT |
1908 WM8962_HP1R_RMV_SHORT,
1909 WM8962_HP1L_RMV_SHORT |
1910 WM8962_HP1R_RMV_SHORT);
1911 break;
1912
1913 case SND_SOC_DAPM_PRE_PMD:
1914 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1915 WM8962_HP1L_RMV_SHORT |
1916 WM8962_HP1R_RMV_SHORT, 0);
1917
1918 udelay(20);
1919
1920 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1921 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1922 WM8962_HP1L_DCS_STARTUP |
1923 WM8962_HP1R_DCS_STARTUP,
1924 0);
1925
1926 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1927 WM8962_HP1L_ENA | WM8962_HP1R_ENA |
1928 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
1929 WM8962_HP1L_ENA_OUTP |
1930 WM8962_HP1R_ENA_OUTP, 0);
1931
1932 break;
1933
1934 default:
1935 BUG();
1936 return -EINVAL;
1937
1938 }
1939
1940 return 0;
1941}
1942
1943/* VU bits for the output PGAs only take effect while the PGA is powered */
1944static int out_pga_event(struct snd_soc_dapm_widget *w,
1945 struct snd_kcontrol *kcontrol, int event)
1946{
1947 struct snd_soc_codec *codec = w->codec;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1948 int reg;
1949
1950 switch (w->shift) {
1951 case WM8962_HPOUTR_PGA_ENA_SHIFT:
1952 reg = WM8962_HPOUTR_VOLUME;
1953 break;
1954 case WM8962_HPOUTL_PGA_ENA_SHIFT:
1955 reg = WM8962_HPOUTL_VOLUME;
1956 break;
1957 case WM8962_SPKOUTR_PGA_ENA_SHIFT:
1958 reg = WM8962_SPKOUTR_VOLUME;
1959 break;
1960 case WM8962_SPKOUTL_PGA_ENA_SHIFT:
1961 reg = WM8962_SPKOUTL_VOLUME;
1962 break;
1963 default:
1964 BUG();
1965 return -EINVAL;
1966 }
1967
1968 switch (event) {
1969 case SND_SOC_DAPM_POST_PMU:
Mark Brown38f3f312011-09-23 21:26:33 +0100[diff] [blame]1970 return snd_soc_write(codec, reg, snd_soc_read(codec, reg));
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1971 default:
1972 BUG();
1973 return -EINVAL;
1974 }
1975}
1976
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]1977static int dsp2_event(struct snd_soc_dapm_widget *w,
1978 struct snd_kcontrol *kcontrol, int event)
1979{
1980 struct snd_soc_codec *codec = w->codec;
1981 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1982
1983 switch (event) {
1984 case SND_SOC_DAPM_POST_PMU:
1985 if (wm8962->dsp2_ena)
1986 wm8962_dsp2_start(codec);
1987 break;
1988
1989 case SND_SOC_DAPM_PRE_PMD:
1990 if (wm8962->dsp2_ena)
1991 wm8962_dsp2_stop(codec);
1992 break;
1993
1994 default:
1995 BUG();
1996 return -EINVAL;
1997 }
1998
1999 return 0;
2000}
2001
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2002static const char *st_text[] = { "None", "Right", "Left" };
2003
2004static const struct soc_enum str_enum =
2005 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text);
2006
2007static const struct snd_kcontrol_new str_mux =
2008 SOC_DAPM_ENUM("Right Sidetone", str_enum);
2009
2010static const struct soc_enum stl_enum =
2011 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text);
2012
2013static const struct snd_kcontrol_new stl_mux =
2014 SOC_DAPM_ENUM("Left Sidetone", stl_enum);
2015
2016static const char *outmux_text[] = { "DAC", "Mixer" };
2017
2018static const struct soc_enum spkoutr_enum =
2019 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text);
2020
2021static const struct snd_kcontrol_new spkoutr_mux =
2022 SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
2023
2024static const struct soc_enum spkoutl_enum =
2025 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text);
2026
2027static const struct snd_kcontrol_new spkoutl_mux =
2028 SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
2029
2030static const struct soc_enum hpoutr_enum =
2031 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text);
2032
2033static const struct snd_kcontrol_new hpoutr_mux =
2034 SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
2035
2036static const struct soc_enum hpoutl_enum =
2037 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text);
2038
2039static const struct snd_kcontrol_new hpoutl_mux =
2040 SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
2041
2042static const struct snd_kcontrol_new inpgal[] = {
2043SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
2044SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
2045SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
2046SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
2047};
2048
2049static const struct snd_kcontrol_new inpgar[] = {
2050SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
2051SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
2052SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
2053SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
2054};
2055
2056static const struct snd_kcontrol_new mixinl[] = {
2057SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
2058SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
2059SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
2060};
2061
2062static const struct snd_kcontrol_new mixinr[] = {
2063SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
2064SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
2065SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
2066};
2067
2068static const struct snd_kcontrol_new hpmixl[] = {
2069SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
2070SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
2071SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
2072SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
2073SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
2074SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
2075};
2076
2077static const struct snd_kcontrol_new hpmixr[] = {
2078SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
2079SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
2080SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
2081SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
2082SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
2083SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
2084};
2085
2086static const struct snd_kcontrol_new spkmixl[] = {
2087SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
2088SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
2089SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
2090SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
2091SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
2092SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
2093};
2094
2095static const struct snd_kcontrol_new spkmixr[] = {
2096SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
2097SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
2098SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
2099SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
2100SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
2101SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
2102};
2103
2104static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
2105SND_SOC_DAPM_INPUT("IN1L"),
2106SND_SOC_DAPM_INPUT("IN1R"),
2107SND_SOC_DAPM_INPUT("IN2L"),
2108SND_SOC_DAPM_INPUT("IN2R"),
2109SND_SOC_DAPM_INPUT("IN3L"),
2110SND_SOC_DAPM_INPUT("IN3R"),
2111SND_SOC_DAPM_INPUT("IN4L"),
2112SND_SOC_DAPM_INPUT("IN4R"),
Mark Brown36c6b542011-11-27 16:24:18 +0000[diff] [blame]2113SND_SOC_DAPM_SIGGEN("Beep"),
Mark Browne47ac372011-04-25 20:14:21 +0100[diff] [blame]2114SND_SOC_DAPM_INPUT("DMICDAT"),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2115
Mark Brown086d7f82011-09-23 16:22:48 +0100[diff] [blame]2116SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0),
Mark Browna4f28c02010-09-29 13:24:35 -0700[diff] [blame]2117
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2118SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
Mark Browna968d9d2012-01-27 19:54:03 +0000[diff] [blame]2119SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, NULL, 0),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2120SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
2121 SND_SOC_DAPM_POST_PMU),
2122SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2123SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT,
2124 WM8962_DSP2_ENA_SHIFT, 0, dsp2_event,
2125 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
Mark Brown94b88e62011-11-04 17:48:28 +0000[diff] [blame]2126SND_SOC_DAPM_SUPPLY("TEMP_HP", WM8962_ADDITIONAL_CONTROL_4, 2, 0, NULL, 0),
2127SND_SOC_DAPM_SUPPLY("TEMP_SPK", WM8962_ADDITIONAL_CONTROL_4, 1, 0, NULL, 0),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2128
2129SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
2130 inpgal, ARRAY_SIZE(inpgal)),
2131SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
2132 inpgar, ARRAY_SIZE(inpgar)),
2133SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
2134 mixinl, ARRAY_SIZE(mixinl)),
2135SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
2136 mixinr, ARRAY_SIZE(mixinr)),
2137
Mark Brown3f7d55a2011-09-23 16:39:31 +0100[diff] [blame]2138SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0),
Mark Browne47ac372011-04-25 20:14:21 +0100[diff] [blame]2139
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2140SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
2141SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
2142
2143SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
2144SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
2145
2146SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
2147SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
2148
2149SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2150SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2151
2152SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
2153 hpmixl, ARRAY_SIZE(hpmixl)),
2154SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
2155 hpmixr, ARRAY_SIZE(hpmixr)),
2156
2157SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
2158 out_pga_event, SND_SOC_DAPM_POST_PMU),
2159SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
2160 out_pga_event, SND_SOC_DAPM_POST_PMU),
2161
2162SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
2163 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2164
2165SND_SOC_DAPM_OUTPUT("HPOUTL"),
2166SND_SOC_DAPM_OUTPUT("HPOUTR"),
2167};
2168
2169static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
2170SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
2171 spkmixl, ARRAY_SIZE(spkmixl)),
2172SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2173 out_pga_event, SND_SOC_DAPM_POST_PMU),
2174SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2175SND_SOC_DAPM_OUTPUT("SPKOUT"),
2176};
2177
2178static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
2179SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
2180 spkmixl, ARRAY_SIZE(spkmixl)),
2181SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
2182 spkmixr, ARRAY_SIZE(spkmixr)),
2183
2184SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2185 out_pga_event, SND_SOC_DAPM_POST_PMU),
2186SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
2187 out_pga_event, SND_SOC_DAPM_POST_PMU),
2188
2189SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2190SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
2191
2192SND_SOC_DAPM_OUTPUT("SPKOUTL"),
2193SND_SOC_DAPM_OUTPUT("SPKOUTR"),
2194};
2195
2196static const struct snd_soc_dapm_route wm8962_intercon[] = {
2197 { "INPGAL", "IN1L Switch", "IN1L" },
2198 { "INPGAL", "IN2L Switch", "IN2L" },
2199 { "INPGAL", "IN3L Switch", "IN3L" },
2200 { "INPGAL", "IN4L Switch", "IN4L" },
2201
2202 { "INPGAR", "IN1R Switch", "IN1R" },
2203 { "INPGAR", "IN2R Switch", "IN2R" },
2204 { "INPGAR", "IN3R Switch", "IN3R" },
2205 { "INPGAR", "IN4R Switch", "IN4R" },
2206
2207 { "MIXINL", "IN2L Switch", "IN2L" },
2208 { "MIXINL", "IN3L Switch", "IN3L" },
2209 { "MIXINL", "PGA Switch", "INPGAL" },
2210
2211 { "MIXINR", "IN2R Switch", "IN2R" },
2212 { "MIXINR", "IN3R Switch", "IN3R" },
2213 { "MIXINR", "PGA Switch", "INPGAR" },
2214
Mark Brown821f4202010-09-21 17:53:38 +0100[diff] [blame]2215 { "MICBIAS", NULL, "SYSCLK" },
2216
Mark Brown3f7d55a2011-09-23 16:39:31 +0100[diff] [blame]2217 { "DMIC_ENA", NULL, "DMICDAT" },
Mark Browne47ac372011-04-25 20:14:21 +0100[diff] [blame]2218
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2219 { "ADCL", NULL, "SYSCLK" },
2220 { "ADCL", NULL, "TOCLK" },
2221 { "ADCL", NULL, "MIXINL" },
Mark Brown3f7d55a2011-09-23 16:39:31 +0100[diff] [blame]2222 { "ADCL", NULL, "DMIC_ENA" },
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2223 { "ADCL", NULL, "DSP2" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2224
2225 { "ADCR", NULL, "SYSCLK" },
2226 { "ADCR", NULL, "TOCLK" },
2227 { "ADCR", NULL, "MIXINR" },
Mark Brown3f7d55a2011-09-23 16:39:31 +0100[diff] [blame]2228 { "ADCR", NULL, "DMIC_ENA" },
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2229 { "ADCR", NULL, "DSP2" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2230
2231 { "STL", "Left", "ADCL" },
2232 { "STL", "Right", "ADCR" },
Mark Brown1355ab12012-03-01 16:40:51 +0000[diff] [blame^]2233 { "STL", NULL, "Class G" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2234
2235 { "STR", "Left", "ADCL" },
2236 { "STR", "Right", "ADCR" },
Mark Brown1355ab12012-03-01 16:40:51 +0000[diff] [blame^]2237 { "STR", NULL, "Class G" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2238
2239 { "DACL", NULL, "SYSCLK" },
2240 { "DACL", NULL, "TOCLK" },
2241 { "DACL", NULL, "Beep" },
2242 { "DACL", NULL, "STL" },
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2243 { "DACL", NULL, "DSP2" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2244
2245 { "DACR", NULL, "SYSCLK" },
2246 { "DACR", NULL, "TOCLK" },
2247 { "DACR", NULL, "Beep" },
2248 { "DACR", NULL, "STR" },
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2249 { "DACR", NULL, "DSP2" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2250
2251 { "HPMIXL", "IN4L Switch", "IN4L" },
2252 { "HPMIXL", "IN4R Switch", "IN4R" },
2253 { "HPMIXL", "DACL Switch", "DACL" },
2254 { "HPMIXL", "DACR Switch", "DACR" },
2255 { "HPMIXL", "MIXINL Switch", "MIXINL" },
2256 { "HPMIXL", "MIXINR Switch", "MIXINR" },
2257
2258 { "HPMIXR", "IN4L Switch", "IN4L" },
2259 { "HPMIXR", "IN4R Switch", "IN4R" },
2260 { "HPMIXR", "DACL Switch", "DACL" },
2261 { "HPMIXR", "DACR Switch", "DACR" },
2262 { "HPMIXR", "MIXINL Switch", "MIXINL" },
2263 { "HPMIXR", "MIXINR Switch", "MIXINR" },
2264
2265 { "Left Bypass", NULL, "HPMIXL" },
2266 { "Left Bypass", NULL, "Class G" },
2267
2268 { "Right Bypass", NULL, "HPMIXR" },
2269 { "Right Bypass", NULL, "Class G" },
2270
2271 { "HPOUTL PGA", "Mixer", "Left Bypass" },
2272 { "HPOUTL PGA", "DAC", "DACL" },
2273
2274 { "HPOUTR PGA", "Mixer", "Right Bypass" },
2275 { "HPOUTR PGA", "DAC", "DACR" },
2276
2277 { "HPOUT", NULL, "HPOUTL PGA" },
2278 { "HPOUT", NULL, "HPOUTR PGA" },
2279 { "HPOUT", NULL, "Charge Pump" },
2280 { "HPOUT", NULL, "SYSCLK" },
2281 { "HPOUT", NULL, "TOCLK" },
2282
2283 { "HPOUTL", NULL, "HPOUT" },
2284 { "HPOUTR", NULL, "HPOUT" },
Mark Brown94b88e62011-11-04 17:48:28 +0000[diff] [blame]2285
2286 { "HPOUTL", NULL, "TEMP_HP" },
2287 { "HPOUTR", NULL, "TEMP_HP" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2288};
2289
2290static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
2291 { "Speaker Mixer", "IN4L Switch", "IN4L" },
2292 { "Speaker Mixer", "IN4R Switch", "IN4R" },
2293 { "Speaker Mixer", "DACL Switch", "DACL" },
2294 { "Speaker Mixer", "DACR Switch", "DACR" },
2295 { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
2296 { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
2297
2298 { "Speaker PGA", "Mixer", "Speaker Mixer" },
2299 { "Speaker PGA", "DAC", "DACL" },
2300
2301 { "Speaker Output", NULL, "Speaker PGA" },
2302 { "Speaker Output", NULL, "SYSCLK" },
2303 { "Speaker Output", NULL, "TOCLK" },
Mark Brown94b88e62011-11-04 17:48:28 +0000[diff] [blame]2304 { "Speaker Output", NULL, "TEMP_SPK" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2305
2306 { "SPKOUT", NULL, "Speaker Output" },
2307};
2308
2309static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
2310 { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
2311 { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
2312 { "SPKOUTL Mixer", "DACL Switch", "DACL" },
2313 { "SPKOUTL Mixer", "DACR Switch", "DACR" },
2314 { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
2315 { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
2316
2317 { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
2318 { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
2319 { "SPKOUTR Mixer", "DACL Switch", "DACL" },
2320 { "SPKOUTR Mixer", "DACR Switch", "DACR" },
2321 { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
2322 { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
2323
2324 { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
2325 { "SPKOUTL PGA", "DAC", "DACL" },
2326
2327 { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
2328 { "SPKOUTR PGA", "DAC", "DACR" },
2329
2330 { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
2331 { "SPKOUTL Output", NULL, "SYSCLK" },
2332 { "SPKOUTL Output", NULL, "TOCLK" },
Mark Brown94b88e62011-11-04 17:48:28 +0000[diff] [blame]2333 { "SPKOUTL Output", NULL, "TEMP_SPK" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2334
2335 { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
2336 { "SPKOUTR Output", NULL, "SYSCLK" },
2337 { "SPKOUTR Output", NULL, "TOCLK" },
Mark Brown94b88e62011-11-04 17:48:28 +0000[diff] [blame]2338 { "SPKOUTR Output", NULL, "TEMP_SPK" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2339
2340 { "SPKOUTL", NULL, "SPKOUTL Output" },
2341 { "SPKOUTR", NULL, "SPKOUTR Output" },
2342};
2343
2344static int wm8962_add_widgets(struct snd_soc_codec *codec)
2345{
2346 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2347 struct snd_soc_dapm_context *dapm = &codec->dapm;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2348
Liam Girdwood022658b2012-02-03 17:43:09 +0000[diff] [blame]2349 snd_soc_add_codec_controls(codec, wm8962_snd_controls,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2350 ARRAY_SIZE(wm8962_snd_controls));
2351 if (pdata && pdata->spk_mono)
Liam Girdwood022658b2012-02-03 17:43:09 +0000[diff] [blame]2352 snd_soc_add_codec_controls(codec, wm8962_spk_mono_controls,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2353 ARRAY_SIZE(wm8962_spk_mono_controls));
2354 else
Liam Girdwood022658b2012-02-03 17:43:09 +0000[diff] [blame]2355 snd_soc_add_codec_controls(codec, wm8962_spk_stereo_controls,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2356 ARRAY_SIZE(wm8962_spk_stereo_controls));
2357
2358
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2359 snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2360 ARRAY_SIZE(wm8962_dapm_widgets));
2361 if (pdata && pdata->spk_mono)
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2362 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2363 ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
2364 else
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2365 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2366 ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
2367
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2368 snd_soc_dapm_add_routes(dapm, wm8962_intercon,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2369 ARRAY_SIZE(wm8962_intercon));
2370 if (pdata && pdata->spk_mono)
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2371 snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2372 ARRAY_SIZE(wm8962_spk_mono_intercon));
2373 else
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2374 snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2375 ARRAY_SIZE(wm8962_spk_stereo_intercon));
2376
2377
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2378 snd_soc_dapm_disable_pin(dapm, "Beep");
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2379
2380 return 0;
2381}
2382
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2383/* -1 for reserved values */
2384static const int bclk_divs[] = {
2385 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
2386};
2387
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2388static const int sysclk_rates[] = {
Mark Brown07fabd12012-02-16 00:19:47 -0800[diff] [blame]2389 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 3072, 6144
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2390};
2391
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2392static void wm8962_configure_bclk(struct snd_soc_codec *codec)
2393{
2394 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2395 int dspclk, i;
2396 int clocking2 = 0;
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2397 int clocking4 = 0;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2398 int aif2 = 0;
2399
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2400 if (!wm8962->sysclk_rate) {
2401 dev_dbg(codec->dev, "No SYSCLK configured\n");
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2402 return;
2403 }
2404
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2405 if (!wm8962->bclk || !wm8962->lrclk) {
2406 dev_dbg(codec->dev, "No audio clocks configured\n");
2407 return;
2408 }
2409
2410 for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
2411 if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) {
2412 clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
2413 break;
2414 }
2415 }
2416
2417 if (i == ARRAY_SIZE(sysclk_rates)) {
2418 dev_err(codec->dev, "Unsupported sysclk ratio %d\n",
2419 wm8962->sysclk_rate / wm8962->lrclk);
2420 return;
2421 }
2422
Mark Browneeba1f82012-02-16 00:19:30 -0800[diff] [blame]2423 dev_dbg(codec->dev, "Selected sysclk ratio %d\n", sysclk_rates[i]);
2424
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2425 snd_soc_update_bits(codec, WM8962_CLOCKING_4,
2426 WM8962_SYSCLK_RATE_MASK, clocking4);
2427
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2428 dspclk = snd_soc_read(codec, WM8962_CLOCKING1);
2429 if (dspclk < 0) {
2430 dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk);
2431 return;
2432 }
2433
2434 dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
2435 switch (dspclk) {
2436 case 0:
2437 dspclk = wm8962->sysclk_rate;
2438 break;
2439 case 1:
2440 dspclk = wm8962->sysclk_rate / 2;
2441 break;
2442 case 2:
2443 dspclk = wm8962->sysclk_rate / 4;
2444 break;
2445 default:
2446 dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
2447 dspclk = wm8962->sysclk;
2448 }
2449
2450 dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
2451
2452 /* We're expecting an exact match */
2453 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2454 if (bclk_divs[i] < 0)
2455 continue;
2456
2457 if (dspclk / bclk_divs[i] == wm8962->bclk) {
2458 dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n",
2459 bclk_divs[i], wm8962->bclk);
2460 clocking2 |= i;
2461 break;
2462 }
2463 }
2464 if (i == ARRAY_SIZE(bclk_divs)) {
2465 dev_err(codec->dev, "Unsupported BCLK ratio %d\n",
2466 dspclk / wm8962->bclk);
2467 return;
2468 }
2469
2470 aif2 |= wm8962->bclk / wm8962->lrclk;
2471 dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n",
2472 wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
2473
2474 snd_soc_update_bits(codec, WM8962_CLOCKING2,
2475 WM8962_BCLK_DIV_MASK, clocking2);
2476 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2,
2477 WM8962_AIF_RATE_MASK, aif2);
2478}
2479
2480static int wm8962_set_bias_level(struct snd_soc_codec *codec,
2481 enum snd_soc_bias_level level)
2482{
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2483 if (level == codec->dapm.bias_level)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2484 return 0;
2485
2486 switch (level) {
2487 case SND_SOC_BIAS_ON:
2488 break;
2489
2490 case SND_SOC_BIAS_PREPARE:
2491 /* VMID 2*50k */
2492 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2493 WM8962_VMID_SEL_MASK, 0x80);
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2494
2495 wm8962_configure_bclk(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2496 break;
2497
2498 case SND_SOC_BIAS_STANDBY:
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2499 /* VMID 2*250k */
2500 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2501 WM8962_VMID_SEL_MASK, 0x100);
2502 break;
2503
2504 case SND_SOC_BIAS_OFF:
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2505 break;
2506 }
Mark Brownd23031a2012-02-01 12:48:59 +0000[diff] [blame]2507
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2508 codec->dapm.bias_level = level;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2509 return 0;
2510}
2511
2512static const struct {
2513 int rate;
2514 int reg;
2515} sr_vals[] = {
2516 { 48000, 0 },
2517 { 44100, 0 },
2518 { 32000, 1 },
2519 { 22050, 2 },
2520 { 24000, 2 },
2521 { 16000, 3 },
2522 { 11025, 4 },
2523 { 12000, 4 },
2524 { 8000, 5 },
2525 { 88200, 6 },
2526 { 96000, 6 },
2527};
2528
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2529static int wm8962_hw_params(struct snd_pcm_substream *substream,
2530 struct snd_pcm_hw_params *params,
2531 struct snd_soc_dai *dai)
2532{
2533 struct snd_soc_pcm_runtime *rtd = substream->private_data;
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]2534 struct snd_soc_codec *codec = rtd->codec;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2535 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2536 int i;
2537 int aif0 = 0;
2538 int adctl3 = 0;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2539
2540 wm8962->bclk = snd_soc_params_to_bclk(params);
Mark Brown4c6c0b52012-02-08 19:02:24 +0000[diff] [blame]2541 if (params_channels(params) == 1)
2542 wm8962->bclk *= 2;
2543
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2544 wm8962->lrclk = params_rate(params);
2545
2546 for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2547 if (sr_vals[i].rate == wm8962->lrclk) {
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2548 adctl3 |= sr_vals[i].reg;
2549 break;
2550 }
2551 }
2552 if (i == ARRAY_SIZE(sr_vals)) {
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2553 dev_err(codec->dev, "Unsupported rate %dHz\n", wm8962->lrclk);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2554 return -EINVAL;
2555 }
2556
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2557 if (wm8962->lrclk % 8000 == 0)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2558 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
2559
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2560 switch (params_format(params)) {
2561 case SNDRV_PCM_FORMAT_S16_LE:
2562 break;
2563 case SNDRV_PCM_FORMAT_S20_3LE:
Susan Gao2b6712b2012-01-30 13:57:04 -0800[diff] [blame]2564 aif0 |= 0x4;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2565 break;
2566 case SNDRV_PCM_FORMAT_S24_LE:
Susan Gao2b6712b2012-01-30 13:57:04 -0800[diff] [blame]2567 aif0 |= 0x8;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2568 break;
2569 case SNDRV_PCM_FORMAT_S32_LE:
Susan Gao2b6712b2012-01-30 13:57:04 -0800[diff] [blame]2570 aif0 |= 0xc;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2571 break;
2572 default:
2573 return -EINVAL;
2574 }
2575
2576 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2577 WM8962_WL_MASK, aif0);
2578 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3,
2579 WM8962_SAMPLE_RATE_INT_MODE |
2580 WM8962_SAMPLE_RATE_MASK, adctl3);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2581
Mark Brown19935022012-02-16 00:46:44 -0800[diff] [blame]2582 if (codec->dapm.bias_level == SND_SOC_BIAS_ON)
2583 wm8962_configure_bclk(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2584
2585 return 0;
2586}
2587
2588static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2589 unsigned int freq, int dir)
2590{
2591 struct snd_soc_codec *codec = dai->codec;
2592 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2593 int src;
2594
2595 switch (clk_id) {
2596 case WM8962_SYSCLK_MCLK:
2597 wm8962->sysclk = WM8962_SYSCLK_MCLK;
2598 src = 0;
2599 break;
2600 case WM8962_SYSCLK_FLL:
2601 wm8962->sysclk = WM8962_SYSCLK_FLL;
2602 src = 1 << WM8962_SYSCLK_SRC_SHIFT;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2603 break;
2604 default:
2605 return -EINVAL;
2606 }
2607
2608 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
2609 src);
2610
2611 wm8962->sysclk_rate = freq;
2612
Mark Brown71de4d22012-02-16 22:26:23 -0800[diff] [blame]2613 wm8962_configure_bclk(codec);
2614
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2615 return 0;
2616}
2617
2618static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2619{
2620 struct snd_soc_codec *codec = dai->codec;
2621 int aif0 = 0;
2622
2623 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2624 case SND_SOC_DAIFMT_DSP_B:
Susan Gaofbc7c622011-09-29 11:08:18 +0100[diff] [blame]2625 aif0 |= WM8962_LRCLK_INV | 3;
2626 case SND_SOC_DAIFMT_DSP_A:
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2627 aif0 |= 3;
2628
2629 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2630 case SND_SOC_DAIFMT_NB_NF:
2631 case SND_SOC_DAIFMT_IB_NF:
2632 break;
2633 default:
2634 return -EINVAL;
2635 }
2636 break;
2637
2638 case SND_SOC_DAIFMT_RIGHT_J:
2639 break;
2640 case SND_SOC_DAIFMT_LEFT_J:
2641 aif0 |= 1;
2642 break;
2643 case SND_SOC_DAIFMT_I2S:
2644 aif0 |= 2;
2645 break;
2646 default:
2647 return -EINVAL;
2648 }
2649
2650 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2651 case SND_SOC_DAIFMT_NB_NF:
2652 break;
2653 case SND_SOC_DAIFMT_IB_NF:
2654 aif0 |= WM8962_BCLK_INV;
2655 break;
2656 case SND_SOC_DAIFMT_NB_IF:
2657 aif0 |= WM8962_LRCLK_INV;
2658 break;
2659 case SND_SOC_DAIFMT_IB_IF:
2660 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
2661 break;
2662 default:
2663 return -EINVAL;
2664 }
2665
2666 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2667 case SND_SOC_DAIFMT_CBM_CFM:
2668 aif0 |= WM8962_MSTR;
2669 break;
2670 case SND_SOC_DAIFMT_CBS_CFS:
2671 break;
2672 default:
2673 return -EINVAL;
2674 }
2675
2676 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2677 WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
2678 WM8962_LRCLK_INV, aif0);
2679
2680 return 0;
2681}
2682
2683struct _fll_div {
2684 u16 fll_fratio;
2685 u16 fll_outdiv;
2686 u16 fll_refclk_div;
2687 u16 n;
2688 u16 theta;
2689 u16 lambda;
2690};
2691
2692/* The size in bits of the FLL divide multiplied by 10
2693 * to allow rounding later */
2694#define FIXED_FLL_SIZE ((1 << 16) * 10)
2695
2696static struct {
2697 unsigned int min;
2698 unsigned int max;
2699 u16 fll_fratio;
2700 int ratio;
2701} fll_fratios[] = {
2702 { 0, 64000, 4, 16 },
2703 { 64000, 128000, 3, 8 },
2704 { 128000, 256000, 2, 4 },
2705 { 256000, 1000000, 1, 2 },
2706 { 1000000, 13500000, 0, 1 },
2707};
2708
2709static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
2710 unsigned int Fout)
2711{
2712 unsigned int target;
2713 unsigned int div;
2714 unsigned int fratio, gcd_fll;
2715 int i;
2716
2717 /* Fref must be <=13.5MHz */
2718 div = 1;
2719 fll_div->fll_refclk_div = 0;
2720 while ((Fref / div) > 13500000) {
2721 div *= 2;
2722 fll_div->fll_refclk_div++;
2723
2724 if (div > 4) {
2725 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2726 Fref);
2727 return -EINVAL;
2728 }
2729 }
2730
2731 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2732
2733 /* Apply the division for our remaining calculations */
2734 Fref /= div;
2735
2736 /* Fvco should be 90-100MHz; don't check the upper bound */
2737 div = 2;
2738 while (Fout * div < 90000000) {
2739 div++;
2740 if (div > 64) {
2741 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2742 Fout);
2743 return -EINVAL;
2744 }
2745 }
2746 target = Fout * div;
2747 fll_div->fll_outdiv = div - 1;
2748
2749 pr_debug("FLL Fvco=%dHz\n", target);
2750
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]2751 /* Find an appropriate FLL_FRATIO and factor it out of the target */
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2752 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2753 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2754 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2755 fratio = fll_fratios[i].ratio;
2756 break;
2757 }
2758 }
2759 if (i == ARRAY_SIZE(fll_fratios)) {
2760 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2761 return -EINVAL;
2762 }
2763
2764 fll_div->n = target / (fratio * Fref);
2765
2766 if (target % Fref == 0) {
2767 fll_div->theta = 0;
2768 fll_div->lambda = 0;
2769 } else {
2770 gcd_fll = gcd(target, fratio * Fref);
2771
2772 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2773 / gcd_fll;
2774 fll_div->lambda = (fratio * Fref) / gcd_fll;
2775 }
2776
2777 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2778 fll_div->n, fll_div->theta, fll_div->lambda);
2779 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2780 fll_div->fll_fratio, fll_div->fll_outdiv,
2781 fll_div->fll_refclk_div);
2782
2783 return 0;
2784}
2785
Mark Brown92a43522011-04-25 18:44:01 +0100[diff] [blame]2786static int wm8962_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2787 unsigned int Fref, unsigned int Fout)
2788{
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2789 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2790 struct _fll_div fll_div;
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]2791 unsigned long timeout;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2792 int ret;
Mark Browna968d9d2012-01-27 19:54:03 +0000[diff] [blame]2793 int fll1 = 0;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2794
2795 /* Any change? */
2796 if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
2797 Fout == wm8962->fll_fout)
2798 return 0;
2799
2800 if (Fout == 0) {
2801 dev_dbg(codec->dev, "FLL disabled\n");
2802
2803 wm8962->fll_fref = 0;
2804 wm8962->fll_fout = 0;
2805
2806 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2807 WM8962_FLL_ENA, 0);
2808
Mark Brownd23031a2012-02-01 12:48:59 +0000[diff] [blame]2809 pm_runtime_put(codec->dev);
2810
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2811 return 0;
2812 }
2813
2814 ret = fll_factors(&fll_div, Fref, Fout);
2815 if (ret != 0)
2816 return ret;
2817
Mark Browna968d9d2012-01-27 19:54:03 +0000[diff] [blame]2818 /* Parameters good, disable so we can reprogram */
2819 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2820
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2821 switch (fll_id) {
2822 case WM8962_FLL_MCLK:
2823 case WM8962_FLL_BCLK:
2824 case WM8962_FLL_OSC:
2825 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
2826 break;
2827 case WM8962_FLL_INT:
2828 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2829 WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
2830 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5,
2831 WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
2832 break;
2833 default:
2834 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2835 return -EINVAL;
2836 }
2837
2838 if (fll_div.theta || fll_div.lambda)
2839 fll1 |= WM8962_FLL_FRAC;
2840
2841 /* Stop the FLL while we reconfigure */
2842 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2843
2844 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2,
2845 WM8962_FLL_OUTDIV_MASK |
2846 WM8962_FLL_REFCLK_DIV_MASK,
2847 (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
2848 (fll_div.fll_refclk_div));
2849
2850 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3,
2851 WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
2852
2853 snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta);
2854 snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda);
2855 snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n);
2856
Mark Brown4df0cb22011-08-21 17:18:52 +0100[diff] [blame]2857 try_wait_for_completion(&wm8962->fll_lock);
2858
Mark Brownd23031a2012-02-01 12:48:59 +0000[diff] [blame]2859 pm_runtime_get_sync(codec->dev);
Mark Brown2a761cd2011-11-01 15:19:23 +0000[diff] [blame]2860
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2861 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2862 WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
Mark Browna968d9d2012-01-27 19:54:03 +0000[diff] [blame]2863 WM8962_FLL_ENA, fll1 | WM8962_FLL_ENA);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2864
2865 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2866
Mark Brown649a1a02011-06-07 23:16:29 +0100[diff] [blame]2867 ret = 0;
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]2868
Mark Brown649a1a02011-06-07 23:16:29 +0100[diff] [blame]2869 if (fll1 & WM8962_FLL_ENA) {
2870 /* This should be a massive overestimate but go even
2871 * higher if we'll error out
2872 */
2873 if (wm8962->irq)
2874 timeout = msecs_to_jiffies(5);
2875 else
2876 timeout = msecs_to_jiffies(1);
2877
2878 timeout = wait_for_completion_timeout(&wm8962->fll_lock,
2879 timeout);
2880
2881 if (timeout == 0 && wm8962->irq) {
2882 dev_err(codec->dev, "FLL lock timed out");
2883 ret = -ETIMEDOUT;
2884 }
2885 }
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]2886
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2887 wm8962->fll_fref = Fref;
2888 wm8962->fll_fout = Fout;
2889 wm8962->fll_src = source;
2890
Mark Brown649a1a02011-06-07 23:16:29 +0100[diff] [blame]2891 return ret;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2892}
2893
2894static int wm8962_mute(struct snd_soc_dai *dai, int mute)
2895{
2896 struct snd_soc_codec *codec = dai->codec;
2897 int val;
2898
2899 if (mute)
2900 val = WM8962_DAC_MUTE;
2901 else
2902 val = 0;
2903
2904 return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
2905 WM8962_DAC_MUTE, val);
2906}
2907
2908#define WM8962_RATES SNDRV_PCM_RATE_8000_96000
2909
2910#define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2911 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2912
Lars-Peter Clausen85e76522011-11-23 11:40:40 +0100[diff] [blame]2913static const struct snd_soc_dai_ops wm8962_dai_ops = {
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2914 .hw_params = wm8962_hw_params,
2915 .set_sysclk = wm8962_set_dai_sysclk,
2916 .set_fmt = wm8962_set_dai_fmt,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2917 .digital_mute = wm8962_mute,
2918};
2919
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]2920static struct snd_soc_dai_driver wm8962_dai = {
2921 .name = "wm8962",
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2922 .playback = {
2923 .stream_name = "Playback",
Mark Brown4c6c0b52012-02-08 19:02:24 +0000[diff] [blame]2924 .channels_min = 1,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2925 .channels_max = 2,
2926 .rates = WM8962_RATES,
2927 .formats = WM8962_FORMATS,
2928 },
2929 .capture = {
2930 .stream_name = "Capture",
Mark Brown4c6c0b52012-02-08 19:02:24 +0000[diff] [blame]2931 .channels_min = 1,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2932 .channels_max = 2,
2933 .rates = WM8962_RATES,
2934 .formats = WM8962_FORMATS,
2935 },
2936 .ops = &wm8962_dai_ops,
2937 .symmetric_rates = 1,
2938};
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2939
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]2940static void wm8962_mic_work(struct work_struct *work)
2941{
2942 struct wm8962_priv *wm8962 = container_of(work,
2943 struct wm8962_priv,
2944 mic_work.work);
2945 struct snd_soc_codec *codec = wm8962->codec;
2946 int status = 0;
2947 int irq_pol = 0;
2948 int reg;
2949
2950 reg = snd_soc_read(codec, WM8962_ADDITIONAL_CONTROL_4);
2951
2952 if (reg & WM8962_MICDET_STS) {
2953 status |= SND_JACK_MICROPHONE;
2954 irq_pol |= WM8962_MICD_IRQ_POL;
2955 }
2956
2957 if (reg & WM8962_MICSHORT_STS) {
2958 status |= SND_JACK_BTN_0;
2959 irq_pol |= WM8962_MICSCD_IRQ_POL;
2960 }
2961
2962 snd_soc_jack_report(wm8962->jack, status,
2963 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
2964
2965 snd_soc_update_bits(codec, WM8962_MICINT_SOURCE_POL,
2966 WM8962_MICSCD_IRQ_POL |
2967 WM8962_MICD_IRQ_POL, irq_pol);
2968}
2969
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]2970static irqreturn_t wm8962_irq(int irq, void *data)
2971{
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]2972 struct device *dev = data;
2973 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
2974 unsigned int mask;
2975 unsigned int active;
2976 int reg, ret;
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]2977
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]2978 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK,
2979 &mask);
2980 if (ret != 0) {
2981 dev_err(dev, "Failed to read interrupt mask: %d\n",
2982 ret);
2983 return IRQ_NONE;
2984 }
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]2985
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]2986 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, &active);
2987 if (ret != 0) {
2988 dev_err(dev, "Failed to read interrupt: %d\n", ret);
2989 return IRQ_NONE;
2990 }
2991
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]2992 active &= ~mask;
2993
Mark Browne6ef5872011-08-21 11:47:14 +0100[diff] [blame]2994 if (!active)
2995 return IRQ_NONE;
2996
Mark Brown3198b9e2011-07-20 13:50:10 +0100[diff] [blame]2997 /* Acknowledge the interrupts */
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]2998 ret = regmap_write(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, active);
2999 if (ret != 0)
3000 dev_warn(dev, "Failed to ack interrupt: %d\n", ret);
Mark Brown3198b9e2011-07-20 13:50:10 +0100[diff] [blame]3001
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]3002 if (active & WM8962_FLL_LOCK_EINT) {
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3003 dev_dbg(dev, "FLL locked\n");
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]3004 complete(&wm8962->fll_lock);
3005 }
3006
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3007 if (active & WM8962_FIFOS_ERR_EINT)
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3008 dev_err(dev, "FIFO error\n");
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3009
Mark Brownfbf04072011-08-21 18:07:44 +0100[diff] [blame]3010 if (active & WM8962_TEMP_SHUT_EINT) {
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3011 dev_crit(dev, "Thermal shutdown\n");
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3012
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3013 ret = regmap_read(wm8962->regmap,
3014 WM8962_THERMAL_SHUTDOWN_STATUS, &reg);
3015 if (ret != 0) {
3016 dev_warn(dev, "Failed to read thermal status: %d\n",
3017 ret);
3018 reg = 0;
3019 }
Mark Brownfbf04072011-08-21 18:07:44 +0100[diff] [blame]3020
3021 if (reg & WM8962_TEMP_ERR_HP)
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3022 dev_crit(dev, "Headphone thermal error\n");
Mark Brownfbf04072011-08-21 18:07:44 +0100[diff] [blame]3023 if (reg & WM8962_TEMP_WARN_HP)
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3024 dev_crit(dev, "Headphone thermal warning\n");
Mark Brownfbf04072011-08-21 18:07:44 +0100[diff] [blame]3025 if (reg & WM8962_TEMP_ERR_SPK)
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3026 dev_crit(dev, "Speaker thermal error\n");
Mark Brownfbf04072011-08-21 18:07:44 +0100[diff] [blame]3027 if (reg & WM8962_TEMP_WARN_SPK)
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3028 dev_crit(dev, "Speaker thermal warning\n");
Mark Brownfbf04072011-08-21 18:07:44 +0100[diff] [blame]3029 }
3030
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3031 if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3032 dev_dbg(dev, "Microphone event detected\n");
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3033
Mark Brown6dc47e92010-12-28 02:14:25 +0000[diff] [blame]3034#ifndef CONFIG_SND_SOC_WM8962_MODULE
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3035 trace_snd_soc_jack_irq(dev_name(dev));
Mark Brown1435b942010-12-23 01:56:20 +0000[diff] [blame]3036#endif
Mark Brown2bbb5d62010-12-05 12:50:12 +0000[diff] [blame]3037
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3038 pm_wakeup_event(dev, 300);
Mark Brown11e16eb2010-11-03 14:45:07 -0400[diff] [blame]3039
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3040 schedule_delayed_work(&wm8962->mic_work,
3041 msecs_to_jiffies(250));
3042 }
3043
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3044 return IRQ_HANDLED;
3045}
3046
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3047/**
3048 * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ
3049 *
3050 * @codec: WM8962 codec
3051 * @jack: jack to report detection events on
3052 *
3053 * Enable microphone detection via IRQ on the WM8962. If GPIOs are
3054 * being used to bring out signals to the processor then only platform
3055 * data configuration is needed for WM8962 and processor GPIOs should
3056 * be configured using snd_soc_jack_add_gpios() instead.
3057 *
3058 * If no jack is supplied detection will be disabled.
3059 */
3060int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
3061{
3062 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3063 int irq_mask, enable;
3064
3065 wm8962->jack = jack;
3066 if (jack) {
3067 irq_mask = 0;
3068 enable = WM8962_MICDET_ENA;
3069 } else {
3070 irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT;
3071 enable = 0;
3072 }
3073
3074 snd_soc_update_bits(codec, WM8962_INTERRUPT_STATUS_2_MASK,
3075 WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask);
3076 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
3077 WM8962_MICDET_ENA, enable);
3078
3079 /* Send an initial empty report */
3080 snd_soc_jack_report(wm8962->jack, 0,
3081 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3082
Mark Browna5ef9882011-11-01 16:00:15 +0000[diff] [blame]3083 if (jack) {
Mark Browndb0e5542011-11-01 15:59:03 +0000[diff] [blame]3084 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
Mark Browna5ef9882011-11-01 16:00:15 +0000[diff] [blame]3085 snd_soc_dapm_force_enable_pin(&codec->dapm, "MICBIAS");
Mark Brown00ae3b82011-11-01 16:02:01 +0000[diff] [blame]3086 } else {
3087 snd_soc_dapm_disable_pin(&codec->dapm, "SYSCLK");
3088 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS");
Mark Browna5ef9882011-11-01 16:00:15 +0000[diff] [blame]3089 }
Mark Browndb0e5542011-11-01 15:59:03 +0000[diff] [blame]3090
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3091 return 0;
3092}
3093EXPORT_SYMBOL_GPL(wm8962_mic_detect);
3094
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3095#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
3096static int beep_rates[] = {
3097 500, 1000, 2000, 4000,
3098};
3099
3100static void wm8962_beep_work(struct work_struct *work)
3101{
3102 struct wm8962_priv *wm8962 =
3103 container_of(work, struct wm8962_priv, beep_work);
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3104 struct snd_soc_codec *codec = wm8962->codec;
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]3105 struct snd_soc_dapm_context *dapm = &codec->dapm;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3106 int i;
3107 int reg = 0;
3108 int best = 0;
3109
3110 if (wm8962->beep_rate) {
3111 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
3112 if (abs(wm8962->beep_rate - beep_rates[i]) <
3113 abs(wm8962->beep_rate - beep_rates[best]))
3114 best = i;
3115 }
3116
3117 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
3118 beep_rates[best], wm8962->beep_rate);
3119
3120 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
3121
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]3122 snd_soc_dapm_enable_pin(dapm, "Beep");
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3123 } else {
3124 dev_dbg(codec->dev, "Disabling beep\n");
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]3125 snd_soc_dapm_disable_pin(dapm, "Beep");
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3126 }
3127
3128 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1,
3129 WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
3130
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]3131 snd_soc_dapm_sync(dapm);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3132}
3133
3134/* For usability define a way of injecting beep events for the device -
3135 * many systems will not have a keyboard.
3136 */
3137static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
3138 unsigned int code, int hz)
3139{
3140 struct snd_soc_codec *codec = input_get_drvdata(dev);
3141 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3142
3143 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
3144
3145 switch (code) {
3146 case SND_BELL:
3147 if (hz)
3148 hz = 1000;
3149 case SND_TONE:
3150 break;
3151 default:
3152 return -1;
3153 }
3154
3155 /* Kick the beep from a workqueue */
3156 wm8962->beep_rate = hz;
3157 schedule_work(&wm8962->beep_work);
3158 return 0;
3159}
3160
3161static ssize_t wm8962_beep_set(struct device *dev,
3162 struct device_attribute *attr,
3163 const char *buf, size_t count)
3164{
3165 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3166 long int time;
Mark Brown74a557e2010-11-03 09:37:06 -0400[diff] [blame]3167 int ret;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3168
Mark Brown74a557e2010-11-03 09:37:06 -0400[diff] [blame]3169 ret = strict_strtol(buf, 10, &time);
3170 if (ret != 0)
3171 return ret;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3172
3173 input_event(wm8962->beep, EV_SND, SND_TONE, time);
3174
3175 return count;
3176}
3177
3178static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set);
3179
3180static void wm8962_init_beep(struct snd_soc_codec *codec)
3181{
3182 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3183 int ret;
3184
3185 wm8962->beep = input_allocate_device();
3186 if (!wm8962->beep) {
3187 dev_err(codec->dev, "Failed to allocate beep device\n");
3188 return;
3189 }
3190
3191 INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
3192 wm8962->beep_rate = 0;
3193
3194 wm8962->beep->name = "WM8962 Beep Generator";
3195 wm8962->beep->phys = dev_name(codec->dev);
3196 wm8962->beep->id.bustype = BUS_I2C;
3197
3198 wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
3199 wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
3200 wm8962->beep->event = wm8962_beep_event;
3201 wm8962->beep->dev.parent = codec->dev;
3202 input_set_drvdata(wm8962->beep, codec);
3203
3204 ret = input_register_device(wm8962->beep);
3205 if (ret != 0) {
3206 input_free_device(wm8962->beep);
3207 wm8962->beep = NULL;
3208 dev_err(codec->dev, "Failed to register beep device\n");
3209 }
3210
3211 ret = device_create_file(codec->dev, &dev_attr_beep);
3212 if (ret != 0) {
3213 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
3214 ret);
3215 }
3216}
3217
3218static void wm8962_free_beep(struct snd_soc_codec *codec)
3219{
3220 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3221
3222 device_remove_file(codec->dev, &dev_attr_beep);
3223 input_unregister_device(wm8962->beep);
3224 cancel_work_sync(&wm8962->beep_work);
3225 wm8962->beep = NULL;
3226
3227 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
3228}
3229#else
3230static void wm8962_init_beep(struct snd_soc_codec *codec)
3231{
3232}
3233
3234static void wm8962_free_beep(struct snd_soc_codec *codec)
3235{
3236}
3237#endif
3238
Mark Brown8ca2aa92010-10-01 17:46:37 -0700[diff] [blame]3239static void wm8962_set_gpio_mode(struct snd_soc_codec *codec, int gpio)
3240{
3241 int mask = 0;
3242 int val = 0;
3243
3244 /* Some of the GPIOs are behind MFP configuration and need to
3245 * be put into GPIO mode. */
3246 switch (gpio) {
3247 case 2:
3248 mask = WM8962_CLKOUT2_SEL_MASK;
3249 val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
3250 break;
3251 case 3:
3252 mask = WM8962_CLKOUT3_SEL_MASK;
3253 val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
3254 break;
3255 default:
3256 break;
3257 }
3258
3259 if (mask)
3260 snd_soc_update_bits(codec, WM8962_ANALOGUE_CLOCKING1,
3261 mask, val);
3262}
3263
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3264#ifdef CONFIG_GPIOLIB
3265static inline struct wm8962_priv *gpio_to_wm8962(struct gpio_chip *chip)
3266{
3267 return container_of(chip, struct wm8962_priv, gpio_chip);
3268}
3269
3270static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
3271{
3272 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3273 struct snd_soc_codec *codec = wm8962->codec;
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3274
3275 /* The WM8962 GPIOs aren't linearly numbered. For simplicity
3276 * we export linear numbers and error out if the unsupported
3277 * ones are requsted.
3278 */
3279 switch (offset + 1) {
3280 case 2:
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3281 case 3:
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3282 case 5:
3283 case 6:
3284 break;
3285 default:
3286 return -EINVAL;
3287 }
3288
Mark Brown8ca2aa92010-10-01 17:46:37 -0700[diff] [blame]3289 wm8962_set_gpio_mode(codec, offset + 1);
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3290
3291 return 0;
3292}
3293
3294static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3295{
3296 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3297 struct snd_soc_codec *codec = wm8962->codec;
3298
3299 snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
Mark Brownd71bb812011-01-31 13:41:03 +0000[diff] [blame]3300 WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT);
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3301}
3302
3303static int wm8962_gpio_direction_out(struct gpio_chip *chip,
3304 unsigned offset, int value)
3305{
3306 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3307 struct snd_soc_codec *codec = wm8962->codec;
Axel Linfe75fe02011-12-30 23:38:03 +0800[diff] [blame]3308 int ret, val;
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3309
3310 /* Force function 1 (logic output) */
3311 val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
3312
Axel Linfe75fe02011-12-30 23:38:03 +0800[diff] [blame]3313 ret = snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
3314 WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
3315 if (ret < 0)
3316 return ret;
3317
3318 return 0;
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3319}
3320
3321static struct gpio_chip wm8962_template_chip = {
3322 .label = "wm8962",
3323 .owner = THIS_MODULE,
3324 .request = wm8962_gpio_request,
3325 .direction_output = wm8962_gpio_direction_out,
3326 .set = wm8962_gpio_set,
3327 .can_sleep = 1,
3328};
3329
3330static void wm8962_init_gpio(struct snd_soc_codec *codec)
3331{
3332 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3333 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
3334 int ret;
3335
3336 wm8962->gpio_chip = wm8962_template_chip;
3337 wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
3338 wm8962->gpio_chip.dev = codec->dev;
3339
3340 if (pdata && pdata->gpio_base)
3341 wm8962->gpio_chip.base = pdata->gpio_base;
3342 else
3343 wm8962->gpio_chip.base = -1;
3344
3345 ret = gpiochip_add(&wm8962->gpio_chip);
3346 if (ret != 0)
3347 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
3348}
3349
3350static void wm8962_free_gpio(struct snd_soc_codec *codec)
3351{
3352 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3353 int ret;
3354
3355 ret = gpiochip_remove(&wm8962->gpio_chip);
3356 if (ret != 0)
3357 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
3358}
3359#else
3360static void wm8962_init_gpio(struct snd_soc_codec *codec)
3361{
3362}
3363
3364static void wm8962_free_gpio(struct snd_soc_codec *codec)
3365{
3366}
3367#endif
3368
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3369static int wm8962_probe(struct snd_soc_codec *codec)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3370{
3371 int ret;
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3372 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3373 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
Lars-Peter Clausen7f87e302010-12-28 21:38:01 +0100[diff] [blame]3374 u16 *reg_cache = codec->reg_cache;
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3375 int i, trigger, irq_pol;
Mark Browne47ac372011-04-25 20:14:21 +0100[diff] [blame]3376 bool dmicclk, dmicdat;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3377
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3378 wm8962->codec = codec;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3379 codec->control_data = wm8962->regmap;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3380
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3381 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3382 if (ret != 0) {
3383 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3384 return ret;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3385 }
3386
3387 wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
3388 wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
3389 wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
3390 wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
3391 wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
3392 wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
3393 wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
3394 wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
3395
3396 /* This should really be moved into the regulator core */
3397 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
3398 ret = regulator_register_notifier(wm8962->supplies[i].consumer,
3399 &wm8962->disable_nb[i]);
3400 if (ret != 0) {
3401 dev_err(codec->dev,
3402 "Failed to register regulator notifier: %d\n",
3403 ret);
3404 }
3405 }
3406
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3407 /* SYSCLK defaults to on; make sure it is off so we can safely
3408 * write to registers if the device is declocked.
3409 */
3410 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0);
3411
Mark Browna115c722011-08-04 13:23:38 +0900[diff] [blame]3412 /* Ensure we have soft control over all registers */
3413 snd_soc_update_bits(codec, WM8962_CLOCKING2,
3414 WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3415
Mark Brown2af8de82011-11-01 13:53:37 +0000[diff] [blame]3416 /* Ensure that the oscillator and PLLs are disabled */
3417 snd_soc_update_bits(codec, WM8962_PLL2,
3418 WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3419 0);
3420
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3421 if (pdata) {
3422 /* Apply static configuration for GPIOs */
3423 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++)
Mark Brown8ca2aa92010-10-01 17:46:37 -0700[diff] [blame]3424 if (pdata->gpio_init[i]) {
3425 wm8962_set_gpio_mode(codec, i + 1);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3426 snd_soc_write(codec, 0x200 + i,
3427 pdata->gpio_init[i] & 0xffff);
Mark Brown8ca2aa92010-10-01 17:46:37 -0700[diff] [blame]3428 }
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3429
3430 /* Put the speakers into mono mode? */
3431 if (pdata->spk_mono)
Lars-Peter Clausen7f87e302010-12-28 21:38:01 +0100[diff] [blame]3432 reg_cache[WM8962_CLASS_D_CONTROL_2]
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3433 |= WM8962_SPK_MONO;
Mark Browna4f28c02010-09-29 13:24:35 -0700[diff] [blame]3434
3435 /* Micbias setup, detection enable and detection
3436 * threasholds. */
3437 if (pdata->mic_cfg)
3438 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
3439 WM8962_MICDET_ENA |
3440 WM8962_MICDET_THR_MASK |
3441 WM8962_MICSHORT_THR_MASK |
3442 WM8962_MICBIAS_LVL,
3443 pdata->mic_cfg);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3444 }
3445
3446 /* Latch volume update bits */
Mark Browna1b3b5e2010-12-24 16:59:30 +0000[diff] [blame]3447 snd_soc_update_bits(codec, WM8962_LEFT_INPUT_VOLUME,
3448 WM8962_IN_VU, WM8962_IN_VU);
3449 snd_soc_update_bits(codec, WM8962_RIGHT_INPUT_VOLUME,
3450 WM8962_IN_VU, WM8962_IN_VU);
3451 snd_soc_update_bits(codec, WM8962_LEFT_ADC_VOLUME,
3452 WM8962_ADC_VU, WM8962_ADC_VU);
3453 snd_soc_update_bits(codec, WM8962_RIGHT_ADC_VOLUME,
3454 WM8962_ADC_VU, WM8962_ADC_VU);
3455 snd_soc_update_bits(codec, WM8962_LEFT_DAC_VOLUME,
3456 WM8962_DAC_VU, WM8962_DAC_VU);
3457 snd_soc_update_bits(codec, WM8962_RIGHT_DAC_VOLUME,
3458 WM8962_DAC_VU, WM8962_DAC_VU);
3459 snd_soc_update_bits(codec, WM8962_SPKOUTL_VOLUME,
3460 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3461 snd_soc_update_bits(codec, WM8962_SPKOUTR_VOLUME,
3462 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3463 snd_soc_update_bits(codec, WM8962_HPOUTL_VOLUME,
3464 WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3465 snd_soc_update_bits(codec, WM8962_HPOUTR_VOLUME,
3466 WM8962_HPOUT_VU, WM8962_HPOUT_VU);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3467
Mark Brown8f63aaa882011-06-07 23:14:37 +0100[diff] [blame]3468 /* Stereo control for EQ */
3469 snd_soc_update_bits(codec, WM8962_EQ1, WM8962_EQ_SHARED_COEFF, 0);
3470
Mark Brown0469e7b2011-11-08 15:22:09 +0000[diff] [blame]3471 /* Don't debouce interrupts so we don't need SYSCLK */
3472 snd_soc_update_bits(codec, WM8962_IRQ_DEBOUNCE,
3473 WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB |
3474 WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB,
3475 0);
3476
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3477 wm8962_add_widgets(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3478
Mark Browne47ac372011-04-25 20:14:21 +0100[diff] [blame]3479 /* Save boards having to disable DMIC when not in use */
3480 dmicclk = false;
3481 dmicdat = false;
3482 for (i = 0; i < WM8962_MAX_GPIO; i++) {
3483 switch (snd_soc_read(codec, WM8962_GPIO_BASE + i)
3484 & WM8962_GP2_FN_MASK) {
3485 case WM8962_GPIO_FN_DMICCLK:
3486 dmicclk = true;
3487 break;
3488 case WM8962_GPIO_FN_DMICDAT:
3489 dmicdat = true;
3490 break;
3491 default:
3492 break;
3493 }
3494 }
3495 if (!dmicclk || !dmicdat) {
3496 dev_dbg(codec->dev, "DMIC not in use, disabling\n");
3497 snd_soc_dapm_nc_pin(&codec->dapm, "DMICDAT");
3498 }
3499 if (dmicclk != dmicdat)
3500 dev_warn(codec->dev, "DMIC GPIOs partially configured\n");
3501
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3502 wm8962_init_beep(codec);
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3503 wm8962_init_gpio(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3504
Mark Brownc7356da2011-06-07 23:13:53 +0100[diff] [blame]3505 if (wm8962->irq) {
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3506 if (pdata && pdata->irq_active_low) {
3507 trigger = IRQF_TRIGGER_LOW;
3508 irq_pol = WM8962_IRQ_POL;
3509 } else {
3510 trigger = IRQF_TRIGGER_HIGH;
3511 irq_pol = 0;
3512 }
3513
3514 snd_soc_update_bits(codec, WM8962_INTERRUPT_CONTROL,
3515 WM8962_IRQ_POL, irq_pol);
3516
Mark Brownc7356da2011-06-07 23:13:53 +0100[diff] [blame]3517 ret = request_threaded_irq(wm8962->irq, NULL, wm8962_irq,
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3518 trigger | IRQF_ONESHOT,
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3519 "wm8962", codec->dev);
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3520 if (ret != 0) {
3521 dev_err(codec->dev, "Failed to request IRQ %d: %d\n",
Mark Brownc7356da2011-06-07 23:13:53 +0100[diff] [blame]3522 wm8962->irq, ret);
3523 wm8962->irq = 0;
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3524 /* Non-fatal */
3525 } else {
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]3526 /* Enable some IRQs by default */
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3527 snd_soc_update_bits(codec,
3528 WM8962_INTERRUPT_STATUS_2_MASK,
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]3529 WM8962_FLL_LOCK_EINT |
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3530 WM8962_TEMP_SHUT_EINT |
3531 WM8962_FIFOS_ERR_EINT, 0);
3532 }
3533 }
3534
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3535 return 0;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3536}
3537
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3538static int wm8962_remove(struct snd_soc_codec *codec)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3539{
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3540 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3541 int i;
3542
Mark Brownc7356da2011-06-07 23:13:53 +0100[diff] [blame]3543 if (wm8962->irq)
3544 free_irq(wm8962->irq, codec);
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3545
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3546 cancel_delayed_work_sync(&wm8962->mic_work);
3547
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3548 wm8962_free_gpio(codec);
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3549 wm8962_free_beep(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3550 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3551 regulator_unregister_notifier(wm8962->supplies[i].consumer,
3552 &wm8962->disable_nb[i]);
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3553
3554 return 0;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3555}
3556
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3557static struct snd_soc_codec_driver soc_codec_dev_wm8962 = {
3558 .probe = wm8962_probe,
3559 .remove = wm8962_remove,
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3560 .set_bias_level = wm8962_set_bias_level,
Mark Brown92a43522011-04-25 18:44:01 +0100[diff] [blame]3561 .set_pll = wm8962_set_fll,
Mark Brown2693efd2012-01-27 19:36:45 +0000[diff] [blame]3562 .idle_bias_off = true,
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3563};
3564
Mark Brown182c51c2012-01-24 21:07:55 +0000[diff] [blame]3565/* Improve power consumption for IN4 DC measurement mode */
3566static const struct reg_default wm8962_dc_measure[] = {
3567 { 0xfd, 0x1 },
3568 { 0xcc, 0x40 },
3569 { 0xfd, 0 },
3570};
3571
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3572static const struct regmap_config wm8962_regmap = {
3573 .reg_bits = 16,
3574 .val_bits = 16,
3575
3576 .max_register = WM8962_MAX_REGISTER,
3577 .reg_defaults = wm8962_reg,
3578 .num_reg_defaults = ARRAY_SIZE(wm8962_reg),
3579 .volatile_reg = wm8962_volatile_register,
3580 .readable_reg = wm8962_readable_register,
3581 .cache_type = REGCACHE_RBTREE,
3582};
3583
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3584static __devinit int wm8962_i2c_probe(struct i2c_client *i2c,
3585 const struct i2c_device_id *id)
3586{
Mark Brown182c51c2012-01-24 21:07:55 +0000[diff] [blame]3587 struct wm8962_pdata *pdata = dev_get_platdata(&i2c->dev);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3588 struct wm8962_priv *wm8962;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3589 unsigned int reg;
3590 int ret, i;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3591
Mark Brownbe086aa2011-11-27 19:56:52 +0000[diff] [blame]3592 wm8962 = devm_kzalloc(&i2c->dev, sizeof(struct wm8962_priv),
3593 GFP_KERNEL);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3594 if (wm8962 == NULL)
3595 return -ENOMEM;
3596
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3597 i2c_set_clientdata(i2c, wm8962);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3598
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3599 INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
3600 init_completion(&wm8962->fll_lock);
Mark Brownc7356da2011-06-07 23:13:53 +0100[diff] [blame]3601 wm8962->irq = i2c->irq;
3602
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3603 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3604 wm8962->supplies[i].supply = wm8962_supply_names[i];
3605
3606 ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies),
3607 wm8962->supplies);
3608 if (ret != 0) {
3609 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
Mark Brownbe086aa2011-11-27 19:56:52 +0000[diff] [blame]3610 goto err;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3611 }
3612
3613 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3614 wm8962->supplies);
3615 if (ret != 0) {
3616 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3617 goto err_get;
3618 }
3619
3620 wm8962->regmap = regmap_init_i2c(i2c, &wm8962_regmap);
3621 if (IS_ERR(wm8962->regmap)) {
3622 ret = PTR_ERR(wm8962->regmap);
3623 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
3624 goto err_enable;
3625 }
3626
3627 /*
3628 * We haven't marked the chip revision as volatile due to
3629 * sharing a register with the right input volume; explicitly
3630 * bypass the cache to read it.
3631 */
3632 regcache_cache_bypass(wm8962->regmap, true);
3633
3634 ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, &reg);
3635 if (ret < 0) {
3636 dev_err(&i2c->dev, "Failed to read ID register\n");
3637 goto err_regmap;
3638 }
3639 if (reg != 0x6243) {
3640 dev_err(&i2c->dev,
Axel Lin905b4192012-02-16 10:33:45 +0800[diff] [blame]3641 "Device is not a WM8962, ID %x != 0x6243\n", reg);
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3642 ret = -EINVAL;
3643 goto err_regmap;
3644 }
3645
3646 ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, &reg);
3647 if (ret < 0) {
3648 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
3649 ret);
3650 goto err_regmap;
3651 }
3652
3653 dev_info(&i2c->dev, "customer id %x revision %c\n",
3654 (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
3655 ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
3656 + 'A');
3657
3658 regcache_cache_bypass(wm8962->regmap, false);
3659
3660 ret = wm8962_reset(wm8962);
3661 if (ret < 0) {
3662 dev_err(&i2c->dev, "Failed to issue reset\n");
3663 goto err_regmap;
3664 }
3665
Mark Brown182c51c2012-01-24 21:07:55 +0000[diff] [blame]3666 if (pdata && pdata->in4_dc_measure) {
3667 ret = regmap_register_patch(wm8962->regmap,
3668 wm8962_dc_measure,
3669 ARRAY_SIZE(wm8962_dc_measure));
3670 if (ret != 0)
3671 dev_err(&i2c->dev,
3672 "Failed to configure for DC mesurement: %d\n",
3673 ret);
3674 }
3675
Mark Brownd23031a2012-02-01 12:48:59 +0000[diff] [blame]3676 pm_runtime_set_active(&i2c->dev);
3677 pm_runtime_enable(&i2c->dev);
3678 pm_request_idle(&i2c->dev);
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3679
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3680 ret = snd_soc_register_codec(&i2c->dev,
3681 &soc_codec_dev_wm8962, &wm8962_dai, 1);
3682 if (ret < 0)
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3683 goto err_regmap;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3684
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3685 /* The drivers should power up as needed */
3686 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3687
3688 return 0;
3689
3690err_regmap:
3691 regmap_exit(wm8962->regmap);
3692err_enable:
3693 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3694err_get:
3695 regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
Mark Brownbe086aa2011-11-27 19:56:52 +0000[diff] [blame]3696err:
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3697 return ret;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3698}
3699
3700static __devexit int wm8962_i2c_remove(struct i2c_client *client)
3701{
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3702 struct wm8962_priv *wm8962 = dev_get_drvdata(&client->dev);
3703
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3704 snd_soc_unregister_codec(&client->dev);
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3705 regmap_exit(wm8962->regmap);
3706 regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3707 return 0;
3708}
3709
Mark Brownd23031a2012-02-01 12:48:59 +0000[diff] [blame]3710#ifdef CONFIG_PM_RUNTIME
3711static int wm8962_runtime_resume(struct device *dev)
3712{
3713 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3714 int ret;
3715
3716 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3717 wm8962->supplies);
3718 if (ret != 0) {
3719 dev_err(dev,
3720 "Failed to enable supplies: %d\n", ret);
3721 return ret;
3722 }
3723
3724 regcache_cache_only(wm8962->regmap, false);
3725 regcache_sync(wm8962->regmap);
3726
3727 regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3728 WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA,
3729 WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA);
3730
3731 /* Bias enable at 2*50k for ramp */
3732 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3733 WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA,
3734 WM8962_BIAS_ENA | 0x180);
3735
3736 msleep(5);
3737
3738 /* VMID back to 2x250k for standby */
3739 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3740 WM8962_VMID_SEL_MASK, 0x100);
3741
Mark Brownd23031a2012-02-01 12:48:59 +0000[diff] [blame]3742 return 0;
3743}
3744
3745static int wm8962_runtime_suspend(struct device *dev)
3746{
3747 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3748
Mark Brownd23031a2012-02-01 12:48:59 +0000[diff] [blame]3749 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3750 WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
3751
3752 regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3753 WM8962_STARTUP_BIAS_ENA |
3754 WM8962_VMID_BUF_ENA, 0);
3755
3756 regcache_cache_only(wm8962->regmap, true);
3757
3758 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
3759 wm8962->supplies);
3760
3761 return 0;
3762}
3763#endif
3764
3765static struct dev_pm_ops wm8962_pm = {
3766 SET_RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL)
3767};
3768
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3769static const struct i2c_device_id wm8962_i2c_id[] = {
3770 { "wm8962", 0 },
3771 { }
3772};
3773MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
3774
3775static struct i2c_driver wm8962_i2c_driver = {
3776 .driver = {
Mark Brownea738ba2010-09-20 20:36:19 +0100[diff] [blame]3777 .name = "wm8962",
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3778 .owner = THIS_MODULE,
Mark Brownd23031a2012-02-01 12:48:59 +0000[diff] [blame]3779 .pm = &wm8962_pm,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3780 },
3781 .probe = wm8962_i2c_probe,
3782 .remove = __devexit_p(wm8962_i2c_remove),
3783 .id_table = wm8962_i2c_id,
3784};
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3785
Mark Brown9d50a762012-02-16 22:43:39 -0800[diff] [blame]3786module_i2c_driver(wm8962_i2c_driver);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3787
3788MODULE_DESCRIPTION("ASoC WM8962 driver");
3789MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3790MODULE_LICENSE("GPL");