blob: 5aaef8d46b4f3cd4087da54f88ed48477b60d141 [file] [log] [blame]
Raghavendra Rao Ananta2f75ed72017-10-18 10:14:05 -07001/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
Kyle Yan679cbee2016-07-27 16:55:20 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13&soc {
Channagoud Kadabieb7f0112017-04-03 20:39:27 -070014 tlmm: pinctrl@03400000 {
Kyle Yan6a20fae2017-02-14 13:34:41 -080015 compatible = "qcom,sdm845-pinctrl";
Channagoud Kadabieb7f0112017-04-03 20:39:27 -070016 reg = <0x03400000 0xc00000>;
Kyle Yan679cbee2016-07-27 16:55:20 -070017 interrupts = <0 208 0>;
18 gpio-controller;
19 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
Archana Sathyakumar00a36ab2017-03-03 14:38:26 -070022 interrupt-parent = <&pdc>;
Banajit Goswamib016de92017-02-15 21:02:30 -080023
Subhash Jadavaniafe2a792017-03-31 21:08:29 -070024 ufs_dev_reset_assert: ufs_dev_reset_assert {
25 config {
26 pins = "ufs_reset";
27 bias-pull-down; /* default: pull down */
28 /*
29 * UFS_RESET driver strengths are having
30 * different values/steps compared to typical
31 * GPIO drive strengths.
32 *
33 * Following table clarifies:
34 *
35 * HDRV value | UFS_RESET | Typical GPIO
36 * (dec) | (mA) | (mA)
37 * 0 | 0.8 | 2
38 * 1 | 1.55 | 4
39 * 2 | 2.35 | 6
40 * 3 | 3.1 | 8
41 * 4 | 3.9 | 10
42 * 5 | 4.65 | 12
43 * 6 | 5.4 | 14
44 * 7 | 6.15 | 16
45 *
46 * POR value for UFS_RESET HDRV is 3 which means
47 * 3.1mA and we want to use that. Hence just
48 * specify 8mA to "drive-strength" binding and
49 * that should result into writing 3 to HDRV
50 * field.
51 */
52 drive-strength = <8>; /* default: 3.1 mA */
53 output-low; /* active low reset */
54 };
55 };
56
57 ufs_dev_reset_deassert: ufs_dev_reset_deassert {
58 config {
59 pins = "ufs_reset";
60 bias-pull-down; /* default: pull down */
61 /*
62 * default: 3.1 mA
63 * check comments under ufs_dev_reset_assert
64 */
65 drive-strength = <8>;
66 output-high; /* active low reset */
67 };
68 };
69
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070070 flash_led3_front {
71 flash_led3_front_en: flash_led3_front_en {
72 mux {
73 pins = "gpio21";
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070074 function = "gpio";
75 };
76
77 config {
78 pins = "gpio21";
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070079 drive_strength = <2>;
80 output-high;
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070081 bias-disable;
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070082 };
83 };
84
85 flash_led3_front_dis: flash_led3_front_dis {
86 mux {
87 pins = "gpio21";
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070088 function = "gpio";
89 };
90
91 config {
92 pins = "gpio21";
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070093 drive_strength = <2>;
94 output-low;
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070095 bias-disable;
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070096 };
97 };
98 };
Subhash Jadavaniafe2a792017-03-31 21:08:29 -070099
Jilai Wangf4d78a22017-11-10 17:05:47 -0500100 flash_led3_iris {
101 flash_led3_iris_en: flash_led3_iris_en {
102 mux {
103 pins = "gpio23";
104 function = "gpio";
105 };
106
107 config {
108 pins = "gpio23";
109 drive_strength = <2>;
110 output-high;
111 bias-disable;
112 };
113 };
114
115 flash_led3_iris_dis: flash_led3_iris_dis {
116 mux {
117 pins = "gpio23";
118 function = "gpio";
119 };
120
121 config {
122 pins = "gpio23";
123 drive_strength = <2>;
124 output-low;
125 bias-disable;
126 };
127 };
128 };
129
130
Banajit Goswamib016de92017-02-15 21:02:30 -0800131 wcd9xxx_intr {
132 wcd_intr_default: wcd_intr_default{
133 mux {
134 pins = "gpio54";
135 function = "gpio";
136 };
137
138 config {
139 pins = "gpio54";
140 drive-strength = <2>; /* 2 mA */
141 bias-pull-down; /* pull down */
142 input-enable;
143 };
144 };
145 };
146
Subhash Jadavanidd416c42017-05-15 11:54:10 -0700147 storage_cd: storage_cd {
148 mux {
149 pins = "gpio126";
150 function = "gpio";
151 };
152
153 config {
154 pins = "gpio126";
155 bias-pull-up; /* pull up */
156 drive-strength = <2>; /* 2 MA */
157 };
158 };
159
Xiaonian Wang898e0902017-04-08 06:46:29 +0800160 sdc2_clk_on: sdc2_clk_on {
161 config {
162 pins = "sdc2_clk";
163 bias-disable; /* NO pull */
164 drive-strength = <16>; /* 16 MA */
165 };
166 };
167
168 sdc2_clk_off: sdc2_clk_off {
169 config {
170 pins = "sdc2_clk";
171 bias-disable; /* NO pull */
172 drive-strength = <2>; /* 2 MA */
173 };
174 };
175
Can Guo45ebef02017-10-17 13:21:37 +0800176 sdc2_clk_ds_400KHz: sdc2_clk_ds_400KHz {
177 config {
178 pins = "sdc2_clk";
179 bias-disable; /* NO pull */
180 drive-strength = <16>; /* 16 MA */
181 };
182 };
183
184 sdc2_clk_ds_50MHz: sdc2_clk_ds_50MHz {
185 config {
186 pins = "sdc2_clk";
187 bias-disable; /* NO pull */
188 drive-strength = <16>; /* 16 MA */
189 };
190 };
191
192 sdc2_clk_ds_100MHz: sdc2_clk_ds_100MHz {
193 config {
194 pins = "sdc2_clk";
195 bias-disable; /* NO pull */
196 drive-strength = <16>; /* 16 MA */
197 };
198 };
199
200 sdc2_clk_ds_200MHz: sdc2_clk_ds_200MHz {
201 config {
202 pins = "sdc2_clk";
203 bias-disable; /* NO pull */
204 drive-strength = <16>; /* 16 MA */
205 };
206 };
207
Xiaonian Wang898e0902017-04-08 06:46:29 +0800208 sdc2_cmd_on: sdc2_cmd_on {
209 config {
210 pins = "sdc2_cmd";
211 bias-pull-up; /* pull up */
212 drive-strength = <10>; /* 10 MA */
213 };
214 };
215
216 sdc2_cmd_off: sdc2_cmd_off {
217 config {
218 pins = "sdc2_cmd";
219 bias-pull-up; /* pull up */
220 drive-strength = <2>; /* 2 MA */
221 };
222 };
223
Can Guo45ebef02017-10-17 13:21:37 +0800224 sdc2_cmd_ds_400KHz: sdc2_cmd_ds_400KHz {
225 config {
226 pins = "sdc2_cmd";
227 bias-pull-up; /* pull up */
228 drive-strength = <10>; /* 10 MA */
229 };
230 };
231
232 sdc2_cmd_ds_50MHz: sdc2_cmd_ds_50MHz {
233 config {
234 pins = "sdc2_cmd";
235 bias-pull-up; /* pull up */
236 drive-strength = <10>; /* 10 MA */
237 };
238 };
239
240 sdc2_cmd_ds_100MHz: sdc2_cmd_ds_100MHz {
241 config {
242 pins = "sdc2_cmd";
243 bias-pull-up; /* pull up */
244 drive-strength = <10>; /* 10 MA */
245 };
246 };
247
248 sdc2_cmd_ds_200MHz: sdc2_cmd_ds_200MHz {
249 config {
250 pins = "sdc2_cmd";
251 bias-pull-up; /* pull up */
252 drive-strength = <10>; /* 10 MA */
253 };
254 };
255
Xiaonian Wang898e0902017-04-08 06:46:29 +0800256 sdc2_data_on: sdc2_data_on {
257 config {
258 pins = "sdc2_data";
259 bias-pull-up; /* pull up */
260 drive-strength = <10>; /* 10 MA */
261 };
262 };
263
264 sdc2_data_off: sdc2_data_off {
265 config {
266 pins = "sdc2_data";
267 bias-pull-up; /* pull up */
268 drive-strength = <2>; /* 2 MA */
269 };
270 };
271
Can Guo45ebef02017-10-17 13:21:37 +0800272 sdc2_data_ds_400KHz: sdc2_data_ds_400KHz {
273 config {
274 pins = "sdc2_data";
275 bias-pull-up; /* pull up */
276 drive-strength = <10>; /* 10 MA */
277 };
278 };
279
280 sdc2_data_ds_50MHz: sdc2_data_ds_50MHz {
281 config {
282 pins = "sdc2_data";
283 bias-pull-up; /* pull up */
284 drive-strength = <10>; /* 10 MA */
285 };
286 };
287
288 sdc2_data_ds_100MHz: sdc2_data_ds_100MHz {
289 config {
290 pins = "sdc2_data";
291 bias-pull-up; /* pull up */
292 drive-strength = <10>; /* 10 MA */
293 };
294 };
295
296 sdc2_data_ds_200MHz: sdc2_data_ds_200MHz {
297 config {
298 pins = "sdc2_data";
299 bias-pull-up; /* pull up */
300 drive-strength = <10>; /* 10 MA */
301 };
302 };
303
Tony Truongc0e0a5f02017-03-15 11:57:40 -0700304 pcie0 {
305 pcie0_clkreq_default: pcie0_clkreq_default {
306 mux {
307 pins = "gpio36";
308 function = "pci_e0";
309 };
310
311 config {
312 pins = "gpio36";
313 drive-strength = <2>;
314 bias-pull-up;
315 };
316 };
317
318 pcie0_perst_default: pcie0_perst_default {
319 mux {
320 pins = "gpio35";
321 function = "gpio";
322 };
323
324 config {
325 pins = "gpio35";
326 drive-strength = <2>;
327 bias-pull-down;
328 };
329 };
330
331 pcie0_wake_default: pcie0_wake_default {
332 mux {
333 pins = "gpio37";
334 function = "gpio";
335 };
336
337 config {
338 pins = "gpio37";
339 drive-strength = <2>;
Tony Truong299dda12017-09-12 14:32:44 -0700340 bias-pull-up;
Tony Truongc0e0a5f02017-03-15 11:57:40 -0700341 };
342 };
343 };
344
Tony Truong16938352017-05-04 13:39:24 -0700345 pcie1 {
346 pcie1_clkreq_default: pcie1_clkreq_default {
347 mux {
348 pins = "gpio103";
349 function = "pci_e1";
350 };
351
352 config {
353 pins = "gpio103";
354 drive-strength = <2>;
355 bias-pull-up;
356 };
357 };
358
359 pcie1_perst_default: pcie1_perst_default {
360 mux {
361 pins = "gpio102";
362 function = "gpio";
363 };
364
365 config {
366 pins = "gpio102";
367 drive-strength = <2>;
368 bias-pull-down;
369 };
370 };
371
372 pcie1_wake_default: pcie1_wake_default {
373 mux {
374 pins = "gpio104";
375 function = "gpio";
376 };
377
378 config {
379 pins = "gpio104";
380 drive-strength = <2>;
381 bias-pull-down;
382 };
383 };
384 };
385
Banajit Goswamib016de92017-02-15 21:02:30 -0800386 cdc_reset_ctrl {
387 cdc_reset_sleep: cdc_reset_sleep {
388 mux {
389 pins = "gpio64";
390 function = "gpio";
391 };
392 config {
393 pins = "gpio64";
394 drive-strength = <2>;
395 bias-disable;
396 output-low;
397 };
398 };
399
400 cdc_reset_active:cdc_reset_active {
401 mux {
402 pins = "gpio64";
403 function = "gpio";
404 };
405 config {
406 pins = "gpio64";
407 drive-strength = <8>;
408 bias-pull-down;
409 output-high;
410 };
411 };
412 };
413
414 spkr_i2s_clk_pin {
415 spkr_i2s_clk_sleep: spkr_i2s_clk_sleep {
416 mux {
417 pins = "gpio69";
418 function = "spkr_i2s";
419 };
420
421 config {
422 pins = "gpio69";
423 drive-strength = <2>; /* 2 mA */
424 bias-pull-down; /* PULL DOWN */
425 };
426 };
427
428 spkr_i2s_clk_active: spkr_i2s_clk_active {
429 mux {
430 pins = "gpio69";
431 function = "spkr_i2s";
432 };
433
434 config {
435 pins = "gpio69";
436 drive-strength = <8>; /* 8 mA */
437 bias-disable; /* NO PULL */
438 };
439 };
440 };
441
442 wcd_gnd_mic_swap {
443 wcd_gnd_mic_swap_idle: wcd_gnd_mic_swap_idle {
444 mux {
445 pins = "gpio51";
446 function = "gpio";
447 };
448 config {
449 pins = "gpio51";
450 drive-strength = <2>;
451 bias-pull-down;
452 output-low;
453 };
454 };
455
456 wcd_gnd_mic_swap_active: wcd_gnd_mic_swap_active {
457 mux {
458 pins = "gpio51";
459 function = "gpio";
460 };
461 config {
462 pins = "gpio51";
463 drive-strength = <2>;
464 bias-disable;
465 output-high;
466 };
467 };
468 };
469
Karthikeyan Mani5bce47c2017-05-26 15:19:04 -0700470 /* USB C analog configuration */
471 wcd_usbc_analog_en1 {
472 wcd_usbc_analog_en1_idle: wcd_usbc_ana_en1_idle {
473 mux {
474 pins = "gpio49";
475 function = "gpio";
476 };
477 config {
478 pins = "gpio49";
479 drive-strength = <2>;
480 bias-pull-down;
481 output-low;
482 };
483 };
484
485 wcd_usbc_analog_en1_active: wcd_usbc_ana_en1_active {
486 mux {
487 pins = "gpio49";
488 function = "gpio";
489 };
490 config {
491 pins = "gpio49";
492 drive-strength = <2>;
493 bias-disable;
494 output-high;
495 };
496 };
497 };
498
499 wcd_usbc_analog_en2 {
500 wcd_usbc_analog_en2_idle: wcd_usbc_ana_en2_idle {
501 mux {
502 pins = "gpio51";
503 function = "gpio";
504 };
505 config {
506 pins = "gpio51";
507 drive-strength = <2>;
508 bias-pull-down;
509 output-low;
510 };
511 };
512
513 wcd_usbc_analog_en2_active: wcd_usbc_ana_en2_active {
514 mux {
515 pins = "gpio51";
516 function = "gpio";
517 };
518 config {
519 pins = "gpio51";
520 drive-strength = <2>;
521 bias-disable;
522 output-high;
523 };
524 };
525 };
526
Banajit Goswamib016de92017-02-15 21:02:30 -0800527 pri_aux_pcm_clk {
528 pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep {
529 mux {
530 pins = "gpio65";
531 function = "gpio";
532 };
533
534 config {
535 pins = "gpio65";
536 drive-strength = <2>; /* 2 mA */
537 bias-pull-down; /* PULL DOWN */
538 input-enable;
539 };
540 };
541
542 pri_aux_pcm_clk_active: pri_aux_pcm_clk_active {
543 mux {
544 pins = "gpio65";
545 function = "pri_mi2s";
546 };
547
548 config {
549 pins = "gpio65";
550 drive-strength = <8>; /* 8 mA */
551 bias-disable; /* NO PULL */
552 output-high;
553 };
554 };
555 };
556
557 pri_aux_pcm_sync {
558 pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep {
559 mux {
560 pins = "gpio66";
561 function = "gpio";
562 };
563
564 config {
565 pins = "gpio66";
566 drive-strength = <2>; /* 2 mA */
567 bias-pull-down; /* PULL DOWN */
568 input-enable;
569 };
570 };
571
572 pri_aux_pcm_sync_active: pri_aux_pcm_sync_active {
573 mux {
574 pins = "gpio66";
575 function = "pri_mi2s_ws";
576 };
577
578 config {
579 pins = "gpio66";
580 drive-strength = <8>; /* 8 mA */
581 bias-disable; /* NO PULL */
582 output-high;
583 };
584 };
585 };
586
587 pri_aux_pcm_din {
588 pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep {
589 mux {
590 pins = "gpio67";
591 function = "gpio";
592 };
593
594 config {
595 pins = "gpio67";
596 drive-strength = <2>; /* 2 mA */
597 bias-pull-down; /* PULL DOWN */
598 input-enable;
599 };
600 };
601
602 pri_aux_pcm_din_active: pri_aux_pcm_din_active {
603 mux {
604 pins = "gpio67";
605 function = "pri_mi2s";
606 };
607
608 config {
609 pins = "gpio67";
610 drive-strength = <8>; /* 8 mA */
611 bias-disable; /* NO PULL */
612 };
613 };
614 };
615
616 pri_aux_pcm_dout {
617 pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep {
618 mux {
619 pins = "gpio68";
620 function = "gpio";
621 };
622
623 config {
624 pins = "gpio68";
625 drive-strength = <2>; /* 2 mA */
626 bias-pull-down; /* PULL DOWN */
627 input-enable;
628 };
629 };
630
631 pri_aux_pcm_dout_active: pri_aux_pcm_dout_active {
632 mux {
633 pins = "gpio68";
634 function = "pri_mi2s";
635 };
636
637 config {
638 pins = "gpio68";
639 drive-strength = <8>; /* 8 mA */
640 bias-disable; /* NO PULL */
641 };
642 };
643 };
644
Shashank Babu Chinta Venkata2f40bc72017-03-21 15:31:38 -0700645 pmx_sde: pmx_sde {
646 sde_dsi_active: sde_dsi_active {
647 mux {
648 pins = "gpio6", "gpio52";
649 function = "gpio";
650 };
651
652 config {
653 pins = "gpio6", "gpio52";
654 drive-strength = <8>; /* 8 mA */
655 bias-disable = <0>; /* no pull */
656 };
657 };
658 sde_dsi_suspend: sde_dsi_suspend {
659 mux {
660 pins = "gpio6", "gpio52";
661 function = "gpio";
662 };
663
664 config {
665 pins = "gpio6", "gpio52";
666 drive-strength = <2>; /* 2 mA */
667 bias-pull-down; /* PULL DOWN */
668 };
669 };
670 };
671
672 pmx_sde_te {
673 sde_te_active: sde_te_active {
674 mux {
675 pins = "gpio10";
676 function = "mdp_vsync";
677 };
678
679 config {
680 pins = "gpio10";
681 drive-strength = <2>; /* 2 mA */
682 bias-pull-down; /* PULL DOWN */
683 };
684 };
685
686 sde_te_suspend: sde_te_suspend {
687 mux {
688 pins = "gpio10";
689 function = "mdp_vsync";
690 };
691
692 config {
693 pins = "gpio10";
694 drive-strength = <2>; /* 2 mA */
695 bias-pull-down; /* PULL DOWN */
696 };
697 };
698 };
699
Padmanabhan Komanduru887085e2017-05-02 14:57:12 -0700700 sde_dp_aux_active: sde_dp_aux_active {
701 mux {
702 pins = "gpio43", "gpio51";
703 function = "gpio";
704 };
705
706 config {
707 pins = "gpio43", "gpio51";
708 bias-disable = <0>; /* no pull */
709 drive-strength = <8>;
710 };
711 };
712
713 sde_dp_aux_suspend: sde_dp_aux_suspend {
714 mux {
715 pins = "gpio43", "gpio51";
716 function = "gpio";
717 };
718
719 config {
720 pins = "gpio43", "gpio51";
721 bias-pull-down;
722 drive-strength = <2>;
723 };
724 };
725
726 sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active {
727 mux {
728 pins = "gpio38";
729 function = "gpio";
730 };
731
732 config {
733 pins = "gpio38";
734 bias-disable;
735 drive-strength = <16>;
736 };
737 };
738
739 sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend {
740 mux {
741 pins = "gpio38";
742 function = "gpio";
743 };
744
745 config {
746 pins = "gpio38";
747 bias-pull-down;
748 drive-strength = <2>;
749 };
750 };
751
Jin Fu9e861b92018-01-17 17:37:32 +0800752 /* add pingrp for touchscreen */
753 pmx_ts_int_active {
754 ts_int_active: ts_int_active {
755 mux {
756 pins = "gpio122";
757 function = "gpio";
758 };
759
760 config {
761 pins = "gpio122";
762 drive-strength = <8>;
763 bias-pull-up;
764 };
765 };
766 };
767
768 pmx_ts_int_suspend {
769 ts_int_suspend1: ts_int_suspend1 {
770 mux {
771 pins = "gpio122";
772 function = "gpio";
773 };
774
775 config {
776 pins = "gpio122";
777 drive-strength = <2>;
778 bias-pull-down;
779 };
780 };
781 };
782
783 pmx_ts_reset_active {
784 ts_reset_active: ts_reset_active {
785 mux {
786 pins = "gpio99";
787 function = "gpio";
788 };
789
790 config {
791 pins = "gpio99";
792 drive-strength = <8>;
793 bias-pull-up;
794 };
795 };
796 };
797
798 pmx_ts_reset_suspend {
799 ts_reset_suspend1: ts_reset_suspend1 {
800 mux {
801 pins = "gpio99";
802 function = "gpio";
803 };
804
805 config {
806 pins = "gpio99";
807 drive-strength = <2>;
808 bias-pull-down;
809 };
810 };
811 };
812
813 pmx_ts_release {
814 ts_release: ts_release {
815 mux {
816 pins = "gpio122", "gpio99";
817 function = "gpio";
818 };
819
820 config {
821 pins = "gpio122", "gpio99";
822 drive-strength = <2>;
823 bias-pull-down;
824 };
825 };
826 };
827
828 ts_mux {
829 ts_active: ts_active {
830 mux {
831 pins = "gpio99", "gpio122";
832 function = "gpio";
833 };
834
835 config {
836 pins = "gpio99", "gpio122";
837 drive-strength = <16>;
838 bias-pull-up;
839 };
840 };
841
842 ts_reset_suspend: ts_reset_suspend {
843 mux {
844 pins = "gpio99";
845 function = "gpio";
846 };
847
848 config {
849 pins = "gpio99";
850 drive-strength = <2>;
851 bias-pull-down;
852 };
853 };
854
855 ts_int_suspend: ts_int_suspend {
856 mux {
857 pins = "gpio122";
858 function = "gpio";
859 };
860
861 config {
862 pins = "gpio122";
863 drive-strength = <2>;
864 bias-disable;
865 };
866 };
867 };
868
Banajit Goswamib016de92017-02-15 21:02:30 -0800869 sec_aux_pcm {
870 sec_aux_pcm_sleep: sec_aux_pcm_sleep {
871 mux {
872 pins = "gpio80", "gpio81";
873 function = "gpio";
874 };
875
876 config {
877 pins = "gpio80", "gpio81";
878 drive-strength = <2>; /* 2 mA */
879 bias-pull-down; /* PULL DOWN */
880 input-enable;
881 };
882 };
883
884 sec_aux_pcm_active: sec_aux_pcm_active {
885 mux {
886 pins = "gpio80", "gpio81";
887 function = "sec_mi2s";
888 };
889
890 config {
891 pins = "gpio80", "gpio81";
892 drive-strength = <8>; /* 8 mA */
893 bias-disable; /* NO PULL */
894 };
895 };
896 };
897
898 sec_aux_pcm_din {
899 sec_aux_pcm_din_sleep: sec_aux_pcm_din_sleep {
900 mux {
901 pins = "gpio82";
902 function = "gpio";
903 };
904
905 config {
906 pins = "gpio82";
907 drive-strength = <2>; /* 2 mA */
908 bias-pull-down; /* PULL DOWN */
909 input-enable;
910 };
911 };
912
913 sec_aux_pcm_din_active: sec_aux_pcm_din_active {
914 mux {
915 pins = "gpio82";
916 function = "sec_mi2s";
917 };
918
919 config {
920 pins = "gpio82";
921 drive-strength = <8>; /* 8 mA */
922 bias-disable; /* NO PULL */
923 };
924 };
925 };
926
927 sec_aux_pcm_dout {
928 sec_aux_pcm_dout_sleep: sec_aux_pcm_dout_sleep {
929 mux {
930 pins = "gpio83";
931 function = "gpio";
932 };
933
934 config {
935 pins = "gpio83";
936 drive-strength = <2>; /* 2 mA */
937 bias-pull-down; /* PULL DOWN */
938 input-enable;
939 };
940 };
941
942 sec_aux_pcm_dout_active: sec_aux_pcm_dout_active {
943 mux {
944 pins = "gpio83";
945 function = "sec_mi2s";
946 };
947
948 config {
949 pins = "gpio83";
950 drive-strength = <8>; /* 8 mA */
951 bias-disable; /* NO PULL */
952 };
953 };
954 };
955
956 tert_aux_pcm {
957 tert_aux_pcm_sleep: tert_aux_pcm_sleep {
958 mux {
959 pins = "gpio75", "gpio76";
960 function = "gpio";
961 };
962
963 config {
964 pins = "gpio75", "gpio76";
965 drive-strength = <2>; /* 2 mA */
966 bias-pull-down; /* PULL DOWN */
967 input-enable;
968 };
969 };
970
971 tert_aux_pcm_active: tert_aux_pcm_active {
972 mux {
973 pins = "gpio75", "gpio76";
974 function = "ter_mi2s";
975 };
976
977 config {
978 pins = "gpio75", "gpio76";
979 drive-strength = <8>; /* 8 mA */
980 bias-disable; /* NO PULL */
981 output-high;
982 };
983 };
984 };
985
986 tert_aux_pcm_din {
987 tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep {
988 mux {
989 pins = "gpio77";
990 function = "gpio";
991 };
992
993 config {
994 pins = "gpio77";
995 drive-strength = <2>; /* 2 mA */
996 bias-pull-down; /* PULL DOWN */
997 input-enable;
998 };
999 };
1000
1001 tert_aux_pcm_din_active: tert_aux_pcm_din_active {
1002 mux {
1003 pins = "gpio77";
1004 function = "ter_mi2s";
1005 };
1006
1007 config {
1008 pins = "gpio77";
1009 drive-strength = <8>; /* 8 mA */
1010 bias-disable; /* NO PULL */
1011 };
1012 };
1013 };
1014
1015 tert_aux_pcm_dout {
1016 tert_aux_pcm_dout_sleep: tert_aux_pcm_dout_sleep {
1017 mux {
1018 pins = "gpio78";
1019 function = "gpio";
1020 };
1021
1022 config {
1023 pins = "gpio78";
1024 drive-strength = <2>; /* 2 mA */
1025 bias-pull-down; /* PULL DOWN */
1026 input-enable;
1027 };
1028 };
1029
1030 tert_aux_pcm_dout_active: tert_aux_pcm_dout_active {
1031 mux {
1032 pins = "gpio78";
1033 function = "ter_mi2s";
1034 };
1035
1036 config {
1037 pins = "gpio78";
1038 drive-strength = <8>; /* 8 mA */
1039 bias-disable; /* NO PULL */
1040 };
1041 };
1042 };
1043
1044 quat_aux_pcm {
1045 quat_aux_pcm_sleep: quat_aux_pcm_sleep {
1046 mux {
1047 pins = "gpio58", "gpio59";
1048 function = "gpio";
1049 };
1050
1051 config {
1052 pins = "gpio58", "gpio59";
1053 drive-strength = <2>; /* 2 mA */
1054 bias-pull-down; /* PULL DOWN */
1055 input-enable;
1056 };
1057 };
1058
1059 quat_aux_pcm_active: quat_aux_pcm_active {
1060 mux {
1061 pins = "gpio58", "gpio59";
1062 function = "qua_mi2s";
1063 };
1064
1065 config {
1066 pins = "gpio58", "gpio59";
1067 drive-strength = <8>; /* 8 mA */
1068 bias-disable; /* NO PULL */
1069 output-high;
1070 };
1071 };
1072 };
1073
1074 quat_aux_pcm_din {
1075 quat_aux_pcm_din_sleep: quat_aux_pcm_din_sleep {
1076 mux {
1077 pins = "gpio60";
1078 function = "gpio";
1079 };
1080
1081 config {
1082 pins = "gpio60";
1083 drive-strength = <2>; /* 2 mA */
1084 bias-pull-down; /* PULL DOWN */
1085 input-enable;
1086 };
1087 };
1088
1089 quat_aux_pcm_din_active: quat_aux_pcm_din_active {
1090 mux {
1091 pins = "gpio60";
1092 function = "qua_mi2s";
1093 };
1094
1095 config {
1096 pins = "gpio60";
1097 drive-strength = <8>; /* 8 mA */
1098 bias-disable; /* NO PULL */
1099 };
1100 };
1101 };
1102
1103 quat_aux_pcm_dout {
1104 quat_aux_pcm_dout_sleep: quat_aux_pcm_dout_sleep {
1105 mux {
1106 pins = "gpio61";
1107 function = "gpio";
1108 };
1109
1110 config {
1111 pins = "gpio61";
1112 drive-strength = <2>; /* 2 mA */
1113 bias-pull-down; /* PULL DOWN */
1114 input-enable;
1115 };
1116 };
1117
1118 quat_aux_pcm_dout_active: quat_aux_pcm_dout_active {
1119 mux {
1120 pins = "gpio61";
1121 function = "qua_mi2s";
1122 };
1123
1124 config {
1125 pins = "gpio61";
1126 drive-strength = <8>; /* 8 mA */
1127 bias-disable; /* NO PULL */
1128 };
1129 };
1130 };
1131
1132 pri_mi2s_mclk {
1133 pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep {
1134 mux {
1135 pins = "gpio64";
1136 function = "gpio";
1137 };
1138
1139 config {
1140 pins = "gpio64";
1141 drive-strength = <2>; /* 2 mA */
1142 bias-pull-down; /* PULL DOWN */
1143 input-enable;
1144 };
1145 };
1146
1147 pri_mi2s_mclk_active: pri_mi2s_mclk_active {
1148 mux {
1149 pins = "gpio64";
1150 function = "pri_mi2s";
1151 };
1152
1153 config {
1154 pins = "gpio64";
1155 drive-strength = <8>; /* 8 mA */
1156 bias-disable; /* NO PULL */
1157 output-high;
1158 };
1159 };
1160 };
1161
1162 pri_mi2s_sck {
1163 pri_mi2s_sck_sleep: pri_mi2s_sck_sleep {
1164 mux {
1165 pins = "gpio65";
1166 function = "gpio";
1167 };
1168
1169 config {
1170 pins = "gpio65";
1171 drive-strength = <2>; /* 2 mA */
1172 bias-pull-down; /* PULL DOWN */
1173 input-enable;
1174 };
1175 };
1176
1177 pri_mi2s_sck_active: pri_mi2s_sck_active {
1178 mux {
1179 pins = "gpio65";
1180 function = "pri_mi2s";
1181 };
1182
1183 config {
1184 pins = "gpio65";
1185 drive-strength = <8>; /* 8 mA */
1186 bias-disable; /* NO PULL */
1187 output-high;
1188 };
1189 };
1190 };
1191
1192 pri_mi2s_ws {
1193 pri_mi2s_ws_sleep: pri_mi2s_ws_sleep {
1194 mux {
1195 pins = "gpio66";
1196 function = "gpio";
1197 };
1198
1199 config {
1200 pins = "gpio66";
1201 drive-strength = <2>; /* 2 mA */
1202 bias-pull-down; /* PULL DOWN */
1203 input-enable;
1204 };
1205 };
1206
1207 pri_mi2s_ws_active: pri_mi2s_ws_active {
1208 mux {
1209 pins = "gpio66";
1210 function = "pri_mi2s_ws";
1211 };
1212
1213 config {
1214 pins = "gpio66";
1215 drive-strength = <8>; /* 8 mA */
1216 bias-disable; /* NO PULL */
1217 output-high;
1218 };
1219 };
1220 };
1221
1222 pri_mi2s_sd0 {
1223 pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep {
1224 mux {
1225 pins = "gpio67";
1226 function = "gpio";
1227 };
1228
1229 config {
1230 pins = "gpio67";
1231 drive-strength = <2>; /* 2 mA */
1232 bias-pull-down; /* PULL DOWN */
1233 input-enable;
1234 };
1235 };
1236
1237 pri_mi2s_sd0_active: pri_mi2s_sd0_active {
1238 mux {
1239 pins = "gpio67";
1240 function = "pri_mi2s";
1241 };
1242
1243 config {
1244 pins = "gpio67";
1245 drive-strength = <8>; /* 8 mA */
1246 bias-disable; /* NO PULL */
1247 };
1248 };
1249 };
1250
1251 pri_mi2s_sd1 {
1252 pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep {
1253 mux {
1254 pins = "gpio68";
1255 function = "gpio";
1256 };
1257
1258 config {
1259 pins = "gpio68";
1260 drive-strength = <2>; /* 2 mA */
1261 bias-pull-down; /* PULL DOWN */
1262 input-enable;
1263 };
1264 };
1265
1266 pri_mi2s_sd1_active: pri_mi2s_sd1_active {
1267 mux {
1268 pins = "gpio68";
1269 function = "pri_mi2s";
1270 };
1271
1272 config {
1273 pins = "gpio68";
1274 drive-strength = <8>; /* 8 mA */
1275 bias-disable; /* NO PULL */
1276 };
1277 };
1278 };
1279
1280 sec_mi2s_mclk {
1281 sec_mi2s_mclk_sleep: sec_mi2s_mclk_sleep {
1282 mux {
1283 pins = "gpio79";
1284 function = "gpio";
1285 };
1286
1287 config {
1288 pins = "gpio79";
1289 drive-strength = <2>; /* 2 mA */
1290 bias-pull-down; /* PULL DOWN */
1291 input-enable;
1292 };
1293 };
1294
1295 sec_mi2s_mclk_active: sec_mi2s_mclk_active {
1296 mux {
1297 pins = "gpio79";
1298 function = "sec_mi2s";
1299 };
1300
1301 config {
1302 pins = "gpio79";
1303 drive-strength = <8>; /* 8 mA */
1304 bias-disable; /* NO PULL */
1305 };
1306 };
1307 };
1308
1309 sec_mi2s {
1310 sec_mi2s_sleep: sec_mi2s_sleep {
1311 mux {
1312 pins = "gpio80", "gpio81";
1313 function = "gpio";
1314 };
1315
1316 config {
1317 pins = "gpio80", "gpio81";
1318 drive-strength = <2>; /* 2 mA */
1319 bias-disable; /* NO PULL */
1320 input-enable;
1321 };
1322 };
1323
1324 sec_mi2s_active: sec_mi2s_active {
1325 mux {
1326 pins = "gpio80", "gpio81";
1327 function = "sec_mi2s";
1328 };
1329
1330 config {
1331 pins = "gpio80", "gpio81";
1332 drive-strength = <8>; /* 8 mA */
1333 bias-disable; /* NO PULL */
1334 };
1335 };
1336 };
1337
1338 sec_mi2s_sd0 {
1339 sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep {
1340 mux {
1341 pins = "gpio82";
1342 function = "gpio";
1343 };
1344
1345 config {
1346 pins = "gpio82";
1347 drive-strength = <2>; /* 2 mA */
1348 bias-pull-down; /* PULL DOWN */
1349 input-enable;
1350 };
1351 };
1352
1353 sec_mi2s_sd0_active: sec_mi2s_sd0_active {
1354 mux {
1355 pins = "gpio82";
1356 function = "sec_mi2s";
1357 };
1358
1359 config {
1360 pins = "gpio82";
1361 drive-strength = <8>; /* 8 mA */
1362 bias-disable; /* NO PULL */
1363 };
1364 };
1365 };
1366
1367 sec_mi2s_sd1 {
1368 sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep {
1369 mux {
1370 pins = "gpio83";
1371 function = "gpio";
1372 };
1373
1374 config {
1375 pins = "gpio83";
1376 drive-strength = <2>; /* 2 mA */
1377 bias-pull-down; /* PULL DOWN */
1378 input-enable;
1379 };
1380 };
1381
1382 sec_mi2s_sd1_active: sec_mi2s_sd1_active {
1383 mux {
1384 pins = "gpio83";
1385 function = "sec_mi2s";
1386 };
1387
1388 config {
1389 pins = "gpio83";
1390 drive-strength = <8>; /* 8 mA */
1391 bias-disable; /* NO PULL */
1392 };
1393 };
1394 };
1395
1396 tert_mi2s_mclk {
1397 tert_mi2s_mclk_sleep: tert_mi2s_mclk_sleep {
1398 mux {
1399 pins = "gpio74";
1400 function = "gpio";
1401 };
1402
1403 config {
1404 pins = "gpio74";
1405 drive-strength = <2>; /* 2 mA */
1406 bias-pull-down; /* PULL DOWN */
1407 input-enable;
1408 };
1409 };
1410
1411 tert_mi2s_mclk_active: tert_mi2s_mclk_active {
1412 mux {
1413 pins = "gpio74";
1414 function = "ter_mi2s";
1415 };
1416
1417 config {
1418 pins = "gpio74";
1419 drive-strength = <8>; /* 8 mA */
1420 bias-disable; /* NO PULL */
1421 };
1422 };
1423 };
1424
1425 tert_mi2s {
1426 tert_mi2s_sleep: tert_mi2s_sleep {
1427 mux {
1428 pins = "gpio75", "gpio76";
1429 function = "gpio";
1430 };
1431
1432 config {
1433 pins = "gpio75", "gpio76";
1434 drive-strength = <2>; /* 2 mA */
1435 bias-pull-down; /* PULL DOWN */
1436 input-enable;
1437 };
1438 };
1439
1440 tert_mi2s_active: tert_mi2s_active {
1441 mux {
1442 pins = "gpio75", "gpio76";
1443 function = "ter_mi2s";
1444 };
1445
1446 config {
1447 pins = "gpio75", "gpio76";
1448 drive-strength = <8>; /* 8 mA */
1449 bias-disable; /* NO PULL */
1450 output-high;
1451 };
1452 };
1453 };
1454
1455 tert_mi2s_sd0 {
1456 tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep {
1457 mux {
1458 pins = "gpio77";
1459 function = "gpio";
1460 };
1461
1462 config {
1463 pins = "gpio77";
1464 drive-strength = <2>; /* 2 mA */
1465 bias-pull-down; /* PULL DOWN */
1466 input-enable;
1467 };
1468 };
1469
1470 tert_mi2s_sd0_active: tert_mi2s_sd0_active {
1471 mux {
1472 pins = "gpio77";
1473 function = "ter_mi2s";
1474 };
1475
1476 config {
1477 pins = "gpio77";
1478 drive-strength = <8>; /* 8 mA */
1479 bias-disable; /* NO PULL */
1480 };
1481 };
1482 };
1483
1484 tert_mi2s_sd1 {
1485 tert_mi2s_sd1_sleep: tert_mi2s_sd1_sleep {
1486 mux {
1487 pins = "gpio78";
1488 function = "gpio";
1489 };
1490
1491 config {
1492 pins = "gpio78";
1493 drive-strength = <2>; /* 2 mA */
1494 bias-pull-down; /* PULL DOWN */
1495 input-enable;
1496 };
1497 };
1498
1499 tert_mi2s_sd1_active: tert_mi2s_sd1_active {
1500 mux {
1501 pins = "gpio78";
1502 function = "ter_mi2s";
1503 };
1504
1505 config {
1506 pins = "gpio78";
1507 drive-strength = <8>; /* 8 mA */
1508 bias-disable; /* NO PULL */
1509 };
1510 };
1511 };
1512
1513 quat_mi2s_mclk {
1514 quat_mi2s_mclk_sleep: quat_mi2s_mclk_sleep {
1515 mux {
1516 pins = "gpio57";
1517 function = "gpio";
1518 };
1519
1520 config {
1521 pins = "gpio57";
1522 drive-strength = <2>; /* 2 mA */
1523 bias-pull-down; /* PULL DOWN */
1524 input-enable;
1525 };
1526 };
1527
1528 quat_mi2s_mclk_active: quat_mi2s_mclk_active {
1529 mux {
1530 pins = "gpio57";
1531 function = "qua_mi2s";
1532 };
1533
1534 config {
1535 pins = "gpio57";
1536 drive-strength = <8>; /* 8 mA */
1537 bias-disable; /* NO PULL */
1538 };
1539 };
1540 };
1541
1542 quat_mi2s {
1543 quat_mi2s_sleep: quat_mi2s_sleep {
1544 mux {
1545 pins = "gpio58", "gpio59";
1546 function = "gpio";
1547 };
1548
1549 config {
1550 pins = "gpio58", "gpio59";
1551 drive-strength = <2>; /* 2 mA */
1552 bias-pull-down; /* PULL DOWN */
1553 input-enable;
1554 };
1555 };
1556
1557 quat_mi2s_active: quat_mi2s_active {
1558 mux {
1559 pins = "gpio58", "gpio59";
1560 function = "qua_mi2s";
1561 };
1562
1563 config {
1564 pins = "gpio58", "gpio59";
1565 drive-strength = <8>; /* 8 mA */
1566 bias-disable; /* NO PULL */
1567 output-high;
1568 };
1569 };
1570 };
1571
1572 quat_mi2s_sd0 {
1573 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
1574 mux {
1575 pins = "gpio60";
1576 function = "gpio";
1577 };
1578
1579 config {
1580 pins = "gpio60";
1581 drive-strength = <2>; /* 2 mA */
1582 bias-pull-down; /* PULL DOWN */
1583 input-enable;
1584 };
1585 };
1586
1587 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
1588 mux {
1589 pins = "gpio60";
1590 function = "qua_mi2s";
1591 };
1592
1593 config {
1594 pins = "gpio60";
1595 drive-strength = <8>; /* 8 mA */
1596 bias-disable; /* NO PULL */
1597 };
1598 };
1599 };
1600
1601 quat_mi2s_sd1 {
1602 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
1603 mux {
1604 pins = "gpio61";
1605 function = "gpio";
1606 };
1607
1608 config {
1609 pins = "gpio61";
1610 drive-strength = <2>; /* 2 mA */
1611 bias-pull-down; /* PULL DOWN */
1612 input-enable;
1613 };
1614 };
1615
1616 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
1617 mux {
1618 pins = "gpio61";
1619 function = "qua_mi2s";
1620 };
1621
1622 config {
1623 pins = "gpio61";
1624 drive-strength = <8>; /* 8 mA */
1625 bias-disable; /* NO PULL */
1626 };
1627 };
1628 };
1629
1630 quat_mi2s_sd2 {
1631 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
1632 mux {
1633 pins = "gpio62";
1634 function = "gpio";
1635 };
1636
1637 config {
1638 pins = "gpio62";
1639 drive-strength = <2>; /* 2 mA */
1640 bias-pull-down; /* PULL DOWN */
1641 input-enable;
1642 };
1643 };
1644
1645 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
1646 mux {
1647 pins = "gpio62";
1648 function = "qua_mi2s";
1649 };
1650
1651 config {
1652 pins = "gpio62";
1653 drive-strength = <8>; /* 8 mA */
1654 bias-disable; /* NO PULL */
1655 };
1656 };
1657 };
1658
1659 quat_mi2s_sd3 {
1660 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
1661 mux {
1662 pins = "gpio63";
1663 function = "gpio";
1664 };
1665
1666 config {
1667 pins = "gpio63";
1668 drive-strength = <2>; /* 2 mA */
1669 bias-pull-down; /* PULL DOWN */
1670 input-enable;
1671 };
1672 };
1673
1674 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
1675 mux {
1676 pins = "gpio63";
1677 function = "qua_mi2s";
1678 };
1679
1680 config {
1681 pins = "gpio63";
1682 drive-strength = <8>; /* 8 mA */
1683 bias-disable; /* NO PULL */
1684 };
1685 };
1686 };
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06001687
Xiaoyu Yee1bd1c62017-07-31 16:36:25 -07001688 quat_tdm {
1689 quat_tdm_sleep: quat_tdm_sleep {
1690 mux {
1691 pins = "gpio58", "gpio59";
1692 function = "qua_mi2s";
1693 };
1694
1695 config {
1696 pins = "gpio58", "gpio59";
1697 drive-strength = <2>; /* 2 mA */
1698 bias-pull-down; /* PULL DOWN */
1699 };
1700 };
1701
1702 quat_tdm_active: quat_tdm_active {
1703 mux {
1704 pins = "gpio58", "gpio59";
1705 function = "qua_mi2s";
1706 };
1707
1708 config {
1709 pins = "gpio58", "gpio59";
1710 drive-strength = <8>; /* 8 mA */
1711 bias-disable; /* NO PULL */
1712 };
1713 };
1714 };
1715
1716 quat_tdm_dout {
1717 quat_tdm_dout_sleep: quat_tdm_dout_sleep {
1718 mux {
1719 pins = "gpio61";
1720 function = "qua_mi2s";
1721 };
1722
1723 config {
1724 pins = "gpio61";
1725 drive-strength = <2>; /* 2 mA */
1726 bias-pull-down; /* PULL DOWN */
1727 };
1728 };
1729
1730 quat_tdm_dout_active: quat_tdm_dout_active {
1731 mux {
1732 pins = "gpio61";
1733 function = "qua_mi2s";
1734 };
1735
1736 config {
1737 pins = "gpio61";
1738 drive-strength = <2>; /* 2 mA */
1739 bias-disable; /* NO PULL */
1740 };
1741 };
1742 };
1743
1744 quat_tdm_din {
1745 quat_tdm_din_sleep: quat_tdm_din_sleep {
1746 mux {
1747 pins = "gpio60";
1748 function = "qua_mi2s";
1749 };
1750
1751 config {
1752 pins = "gpio60";
1753 drive-strength = <2>; /* 2 mA */
1754 bias-pull-down; /* PULL DOWN */
1755 };
1756 };
1757
1758 quat_tdm_din_active: quat_tdm_din_active {
1759 mux {
1760 pins = "gpio60";
1761 function = "qua_mi2s";
1762 };
1763
1764 config {
1765 pins = "gpio60";
1766 drive-strength = <2>; /* 2 mA */
1767 bias-disable; /* NO PULL */
1768 };
1769 };
1770 };
1771
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06001772 /* QUPv3 South SE mappings */
1773 /* SE 0 pin mappings */
1774 qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
1775 qupv3_se0_i2c_active: qupv3_se0_i2c_active {
1776 mux {
1777 pins = "gpio0", "gpio1";
1778 function = "qup0";
1779 };
1780
1781 config {
1782 pins = "gpio0", "gpio1";
1783 drive-strength = <2>;
1784 bias-disable;
1785 };
1786 };
1787
1788 qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
1789 mux {
1790 pins = "gpio0", "gpio1";
1791 function = "gpio";
1792 };
1793
1794 config {
1795 pins = "gpio0", "gpio1";
1796 drive-strength = <2>;
1797 bias-pull-up;
1798 };
1799 };
1800 };
1801
1802 qupv3_se0_spi_pins: qupv3_se0_spi_pins {
1803 qupv3_se0_spi_active: qupv3_se0_spi_active {
1804 mux {
1805 pins = "gpio0", "gpio1", "gpio2",
1806 "gpio3";
1807 function = "qup0";
1808 };
1809
1810 config {
1811 pins = "gpio0", "gpio1", "gpio2",
1812 "gpio3";
1813 drive-strength = <6>;
1814 bias-disable;
1815 };
1816 };
1817
1818 qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
1819 mux {
1820 pins = "gpio0", "gpio1", "gpio2",
1821 "gpio3";
1822 function = "gpio";
1823 };
1824
1825 config {
1826 pins = "gpio0", "gpio1", "gpio2",
1827 "gpio3";
1828 drive-strength = <6>;
1829 bias-disable;
1830 };
1831 };
1832 };
1833
1834 /* SE 1 pin mappings */
1835 qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
1836 qupv3_se1_i2c_active: qupv3_se1_i2c_active {
1837 mux {
1838 pins = "gpio17", "gpio18";
1839 function = "qup1";
1840 };
1841
1842 config {
1843 pins = "gpio17", "gpio18";
1844 drive-strength = <2>;
1845 bias-disable;
1846 };
1847 };
1848
1849 qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
1850 mux {
1851 pins = "gpio17", "gpio18";
1852 function = "gpio";
1853 };
1854
1855 config {
1856 pins = "gpio17", "gpio18";
1857 drive-strength = <2>;
1858 bias-pull-up;
1859 };
1860 };
1861 };
1862
1863 qupv3_se1_spi_pins: qupv3_se1_spi_pins {
1864 qupv3_se1_spi_active: qupv3_se1_spi_active {
1865 mux {
1866 pins = "gpio17", "gpio18", "gpio19",
1867 "gpio20";
1868 function = "qup1";
1869 };
1870
1871 config {
1872 pins = "gpio17", "gpio18", "gpio19",
1873 "gpio20";
1874 drive-strength = <6>;
1875 bias-disable;
1876 };
1877 };
1878
1879 qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
1880 mux {
1881 pins = "gpio17", "gpio18", "gpio19",
1882 "gpio20";
1883 function = "gpio";
1884 };
1885
1886 config {
1887 pins = "gpio17", "gpio18", "gpio19",
1888 "gpio20";
1889 drive-strength = <6>;
1890 bias-disable;
1891 };
1892 };
1893 };
1894
1895 /* SE 2 pin mappings */
1896 qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
1897 qupv3_se2_i2c_active: qupv3_se2_i2c_active {
1898 mux {
1899 pins = "gpio27", "gpio28";
1900 function = "qup2";
1901 };
1902
1903 config {
1904 pins = "gpio27", "gpio28";
1905 drive-strength = <2>;
1906 bias-disable;
1907 };
1908 };
1909
1910 qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
1911 mux {
1912 pins = "gpio27", "gpio28";
1913 function = "gpio";
1914 };
1915
1916 config {
1917 pins = "gpio27", "gpio28";
1918 drive-strength = <2>;
1919 bias-pull-up;
1920 };
1921 };
1922 };
1923
1924 qupv3_se2_spi_pins: qupv3_se2_spi_pins {
1925 qupv3_se2_spi_active: qupv3_se2_spi_active {
1926 mux {
1927 pins = "gpio27", "gpio28", "gpio29",
1928 "gpio30";
1929 function = "qup2";
1930 };
1931
1932 config {
1933 pins = "gpio27", "gpio28", "gpio29",
1934 "gpio30";
1935 drive-strength = <6>;
1936 bias-disable;
1937 };
1938 };
1939
1940 qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
1941 mux {
1942 pins = "gpio27", "gpio28", "gpio29",
1943 "gpio30";
1944 function = "gpio";
1945 };
1946
1947 config {
1948 pins = "gpio27", "gpio28", "gpio29",
1949 "gpio30";
1950 drive-strength = <6>;
1951 bias-disable;
1952 };
1953 };
1954 };
1955
1956 /* SE 3 pin mappings */
1957 qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
1958 qupv3_se3_i2c_active: qupv3_se3_i2c_active {
1959 mux {
1960 pins = "gpio41", "gpio42";
1961 function = "qup3";
1962 };
1963
1964 config {
1965 pins = "gpio41", "gpio42";
1966 drive-strength = <2>;
1967 bias-disable;
1968 };
1969 };
1970
1971 qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
1972 mux {
1973 pins = "gpio41", "gpio42";
1974 function = "gpio";
1975 };
1976
1977 config {
1978 pins = "gpio41", "gpio42";
1979 drive-strength = <2>;
1980 bias-pull-up;
1981 };
1982 };
1983 };
1984
Gaurav Singhalf6d253d2017-05-11 08:24:40 +05301985 nfc {
1986 nfc_int_active: nfc_int_active {
1987 /* active state */
1988 mux {
1989 /* GPIO 63 NFC Read Interrupt */
1990 pins = "gpio63";
1991 function = "gpio";
1992 };
1993
1994 config {
1995 pins = "gpio63";
1996 drive-strength = <2>; /* 2 MA */
1997 bias-pull-up;
1998 };
1999 };
2000
2001 nfc_int_suspend: nfc_int_suspend {
2002 /* sleep state */
2003 mux {
2004 /* GPIO 63 NFC Read Interrupt */
2005 pins = "gpio63";
2006 function = "gpio";
2007 };
2008
2009 config {
2010 pins = "gpio63";
2011 drive-strength = <2>; /* 2 MA */
2012 bias-pull-up;
2013 };
2014 };
2015
2016 nfc_enable_active: nfc_enable_active {
2017 /* active state */
2018 mux {
2019 /* 12: NFC ENABLE 116:ESE Enable */
2020 pins = "gpio12", "gpio62", "gpio116";
2021 function = "gpio";
2022 };
2023
2024 config {
2025 pins = "gpio12", "gpio62", "gpio116";
2026 drive-strength = <2>; /* 2 MA */
2027 bias-pull-up;
2028 };
2029 };
2030
2031 nfc_enable_suspend: nfc_enable_suspend {
2032 /* sleep state */
2033 mux {
2034 /* 12: NFC ENABLE 116:ESE Enable */
2035 pins = "gpio12", "gpio62", "gpio116";
2036 function = "gpio";
2037 };
2038
2039 config {
2040 pins = "gpio12", "gpio62", "gpio116";
2041 drive-strength = <2>; /* 2 MA */
2042 bias-disable;
2043 };
2044 };
2045 };
2046
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06002047 qupv3_se3_spi_pins: qupv3_se3_spi_pins {
2048 qupv3_se3_spi_active: qupv3_se3_spi_active {
2049 mux {
2050 pins = "gpio41", "gpio42", "gpio43",
2051 "gpio44";
2052 function = "qup3";
2053 };
2054
2055 config {
2056 pins = "gpio41", "gpio42", "gpio43",
2057 "gpio44";
2058 drive-strength = <6>;
2059 bias-disable;
2060 };
2061 };
2062
2063 qupv3_se3_spi_sleep: qupv3_se3_spi_sleep {
2064 mux {
2065 pins = "gpio41", "gpio42", "gpio43",
2066 "gpio44";
2067 function = "gpio";
2068 };
2069
2070 config {
2071 pins = "gpio41", "gpio42", "gpio43",
2072 "gpio44";
2073 drive-strength = <6>;
2074 bias-disable;
2075 };
2076 };
2077 };
2078
2079 /* SE 4 pin mappings */
2080 qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
2081 qupv3_se4_i2c_active: qupv3_se4_i2c_active {
2082 mux {
2083 pins = "gpio89", "gpio90";
2084 function = "qup4";
2085 };
2086
2087 config {
2088 pins = "gpio89", "gpio90";
2089 drive-strength = <2>;
2090 bias-disable;
2091 };
2092 };
2093
2094 qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
2095 mux {
2096 pins = "gpio89", "gpio90";
2097 function = "gpio";
2098 };
2099
2100 config {
2101 pins = "gpio89", "gpio90";
2102 drive-strength = <2>;
2103 bias-pull-up;
2104 };
2105 };
2106 };
2107
2108 qupv3_se4_spi_pins: qupv3_se4_spi_pins {
2109 qupv3_se4_spi_active: qupv3_se4_spi_active {
2110 mux {
2111 pins = "gpio89", "gpio90", "gpio91",
2112 "gpio92";
2113 function = "qup4";
2114 };
2115
2116 config {
2117 pins = "gpio89", "gpio90", "gpio91",
2118 "gpio92";
2119 drive-strength = <6>;
2120 bias-disable;
2121 };
2122 };
2123
2124 qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
2125 mux {
2126 pins = "gpio89", "gpio90", "gpio91",
2127 "gpio92";
2128 function = "gpio";
2129 };
2130
2131 config {
2132 pins = "gpio89", "gpio90", "gpio91",
2133 "gpio92";
2134 drive-strength = <6>;
2135 bias-disable;
2136 };
2137 };
2138 };
2139
2140 /* SE 5 pin mappings */
2141 qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
2142 qupv3_se5_i2c_active: qupv3_se5_i2c_active {
2143 mux {
2144 pins = "gpio85", "gpio86";
2145 function = "qup5";
2146 };
2147
2148 config {
2149 pins = "gpio85", "gpio86";
2150 drive-strength = <2>;
2151 bias-disable;
2152 };
2153 };
2154
2155 qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
2156 mux {
2157 pins = "gpio85", "gpio86";
2158 function = "gpio";
2159 };
2160
2161 config {
2162 pins = "gpio85", "gpio86";
2163 drive-strength = <2>;
2164 bias-pull-up;
2165 };
2166 };
2167 };
2168
2169 qupv3_se5_spi_pins: qupv3_se5_spi_pins {
2170 qupv3_se5_spi_active: qupv3_se5_spi_active {
2171 mux {
2172 pins = "gpio85", "gpio86", "gpio87",
2173 "gpio88";
2174 function = "qup5";
2175 };
2176
2177 config {
2178 pins = "gpio85", "gpio86", "gpio87",
2179 "gpio88";
2180 drive-strength = <6>;
2181 bias-disable;
2182 };
2183 };
2184
2185 qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
2186 mux {
2187 pins = "gpio85", "gpio86", "gpio87",
2188 "gpio88";
2189 function = "gpio";
2190 };
2191
2192 config {
2193 pins = "gpio85", "gpio86", "gpio87",
2194 "gpio88";
2195 drive-strength = <6>;
2196 bias-disable;
2197 };
2198 };
2199 };
2200
2201 /* SE 6 pin mappings */
2202 qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
2203 qupv3_se6_i2c_active: qupv3_se6_i2c_active {
2204 mux {
2205 pins = "gpio45", "gpio46";
2206 function = "qup6";
2207 };
2208
2209 config {
2210 pins = "gpio45", "gpio46";
2211 drive-strength = <2>;
2212 bias-disable;
2213 };
2214 };
2215
2216 qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
2217 mux {
2218 pins = "gpio45", "gpio46";
2219 function = "gpio";
2220 };
2221
2222 config {
2223 pins = "gpio45", "gpio46";
2224 drive-strength = <2>;
2225 bias-pull-up;
2226 };
2227 };
2228 };
2229
2230 qupv3_se6_4uart_pins: qupv3_se6_4uart_pins {
Girish Mahadevan5d2ed912017-10-27 14:04:22 -06002231 qupv3_se6_ctsrx: qupv3_se6_ctsrx {
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06002232 mux {
Girish Mahadevan5d2ed912017-10-27 14:04:22 -06002233 pins = "gpio45", "gpio48";
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06002234 function = "qup6";
2235 };
2236
2237 config {
Girish Mahadevan5d2ed912017-10-27 14:04:22 -06002238 pins = "gpio45", "gpio48";
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06002239 drive-strength = <2>;
Girish Mahadevan5d2ed912017-10-27 14:04:22 -06002240 bias-no-pull;
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06002241 };
2242 };
2243
Girish Mahadevan5d2ed912017-10-27 14:04:22 -06002244 qupv3_se6_rts: qupv3_se6_rts {
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06002245 mux {
Girish Mahadevan5d2ed912017-10-27 14:04:22 -06002246 pins = "gpio46";
2247 function = "qup6";
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06002248 };
2249
2250 config {
Girish Mahadevan5d2ed912017-10-27 14:04:22 -06002251 pins = "gpio46";
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06002252 drive-strength = <2>;
Girish Mahadevan5d2ed912017-10-27 14:04:22 -06002253 bias-pull-down;
2254 };
2255 };
2256 qupv3_se6_tx: qupv3_se6_tx {
2257 mux {
2258 pins = "gpio47";
2259 function = "qup6";
2260 };
2261
2262 config {
2263 pins = "gpio47";
2264 drive-strength = <2>;
2265 bias-pull-up;
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06002266 };
2267 };
2268 };
2269
2270 qupv3_se6_spi_pins: qupv3_se6_spi_pins {
2271 qupv3_se6_spi_active: qupv3_se6_spi_active {
2272 mux {
2273 pins = "gpio45", "gpio46", "gpio47",
2274 "gpio48";
2275 function = "qup6";
2276 };
2277
2278 config {
2279 pins = "gpio45", "gpio46", "gpio47",
2280 "gpio48";
2281 drive-strength = <6>;
2282 bias-disable;
2283 };
2284 };
2285
2286 qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
2287 mux {
2288 pins = "gpio45", "gpio46", "gpio47",
2289 "gpio48";
2290 function = "gpio";
2291 };
2292
2293 config {
2294 pins = "gpio45", "gpio46", "gpio47",
2295 "gpio48";
2296 drive-strength = <6>;
2297 bias-disable;
2298 };
2299 };
2300 };
2301
2302 /* SE 7 pin mappings */
2303 qupv3_se7_i2c_pins: qupv3_se7_i2c_pins {
2304 qupv3_se7_i2c_active: qupv3_se7_i2c_active {
2305 mux {
2306 pins = "gpio93", "gpio94";
2307 function = "qup7";
2308 };
2309
2310 config {
2311 pins = "gpio93", "gpio94";
2312 drive-strength = <2>;
2313 bias-disable;
2314 };
2315 };
2316
2317 qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep {
2318 mux {
2319 pins = "gpio93", "gpio94";
2320 function = "gpio";
2321 };
2322
2323 config {
2324 pins = "gpio93", "gpio94";
2325 drive-strength = <2>;
2326 bias-pull-up;
2327 };
2328 };
2329 };
2330
2331 qupv3_se7_4uart_pins: qupv3_se7_4uart_pins {
2332 qupv3_se7_4uart_active: qupv3_se7_4uart_active {
2333 mux {
2334 pins = "gpio93", "gpio94", "gpio95",
2335 "gpio96";
2336 function = "qup7";
2337 };
2338
2339 config {
2340 pins = "gpio93", "gpio94", "gpio95",
2341 "gpio96";
2342 drive-strength = <2>;
2343 bias-disable;
2344 };
2345 };
2346
2347 qupv3_se7_4uart_sleep: qupv3_se7_4uart_sleep {
2348 mux {
2349 pins = "gpio93", "gpio94", "gpio95",
2350 "gpio96";
2351 function = "gpio";
2352 };
2353
2354 config {
2355 pins = "gpio93", "gpio94", "gpio95",
2356 "gpio96";
2357 drive-strength = <2>;
2358 bias-disable;
2359 };
2360 };
2361 };
2362
2363 qupv3_se7_spi_pins: qupv3_se7_spi_pins {
2364 qupv3_se7_spi_active: qupv3_se7_spi_active {
2365 mux {
2366 pins = "gpio93", "gpio94", "gpio95",
2367 "gpio96";
2368 function = "qup7";
2369 };
2370
2371 config {
2372 pins = "gpio93", "gpio94", "gpio95",
2373 "gpio96";
2374 drive-strength = <6>;
2375 bias-disable;
2376 };
2377 };
2378
2379 qupv3_se7_spi_sleep: qupv3_se7_spi_sleep {
2380 mux {
2381 pins = "gpio93", "gpio94", "gpio95",
2382 "gpio96";
2383 function = "gpio";
2384 };
2385
2386 config {
2387 pins = "gpio93", "gpio94", "gpio95",
2388 "gpio96";
2389 drive-strength = <6>;
2390 bias-disable;
2391 };
2392 };
2393 };
2394
2395 /* QUPv3 North instances */
2396 /* SE 8 pin mappings */
2397 qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
2398 qupv3_se8_i2c_active: qupv3_se8_i2c_active {
2399 mux {
2400 pins = "gpio65", "gpio66";
2401 function = "qup8";
2402 };
2403
2404 config {
2405 pins = "gpio65", "gpio66";
2406 drive-strength = <2>;
2407 bias-disable;
2408 };
2409 };
2410
2411 qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
2412 mux {
2413 pins = "gpio65", "gpio66";
2414 function = "gpio";
2415 };
2416
2417 config {
2418 pins = "gpio65", "gpio66";
2419 drive-strength = <2>;
2420 bias-pull-up;
2421 };
2422 };
2423 };
2424
2425 qupv3_se8_spi_pins: qupv3_se8_spi_pins {
2426 qupv3_se8_spi_active: qupv3_se8_spi_active {
2427 mux {
2428 pins = "gpio65", "gpio66", "gpio67",
2429 "gpio68";
2430 function = "qup8";
2431 };
2432
2433 config {
2434 pins = "gpio65", "gpio66", "gpio67",
2435 "gpio68";
2436 drive-strength = <6>;
2437 bias-disable;
2438 };
2439 };
2440
2441 qupv3_se8_spi_sleep: qupv3_se8_spi_sleep {
2442 mux {
2443 pins = "gpio65", "gpio66", "gpio67",
2444 "gpio68";
2445 function = "gpio";
2446 };
2447
2448 config {
2449 pins = "gpio65", "gpio66", "gpio67",
2450 "gpio68";
2451 drive-strength = <6>;
2452 bias-disable;
2453 };
2454 };
2455 };
2456
2457 /* SE 9 pin mappings */
2458 qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
2459 qupv3_se9_i2c_active: qupv3_se9_i2c_active {
2460 mux {
2461 pins = "gpio6", "gpio7";
2462 function = "qup9";
2463 };
2464
2465 config {
2466 pins = "gpio6", "gpio7";
2467 drive-strength = <2>;
2468 bias-disable;
2469 };
2470 };
2471
2472 qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
2473 mux {
2474 pins = "gpio6", "gpio7";
2475 function = "gpio";
2476 };
2477
2478 config {
2479 pins = "gpio6", "gpio7";
2480 drive-strength = <2>;
2481 bias-pull-up;
2482 };
2483 };
2484 };
2485
2486 qupv3_se9_2uart_pins: qupv3_se9_2uart_pins {
2487 qupv3_se9_2uart_active: qupv3_se9_2uart_active {
2488 mux {
2489 pins = "gpio4", "gpio5";
2490 function = "qup9";
2491 };
2492
2493 config {
2494 pins = "gpio4", "gpio5";
2495 drive-strength = <2>;
2496 bias-disable;
2497 };
2498 };
2499
2500 qupv3_se9_2uart_sleep: qupv3_se9_2uart_sleep {
2501 mux {
2502 pins = "gpio4", "gpio5";
2503 function = "gpio";
2504 };
2505
2506 config {
2507 pins = "gpio4", "gpio5";
2508 drive-strength = <2>;
2509 bias-disable;
2510 };
2511 };
2512 };
2513
2514 qupv3_se9_spi_pins: qupv3_se9_spi_pins {
2515 qupv3_se9_spi_active: qupv3_se9_spi_active {
2516 mux {
2517 pins = "gpio4", "gpio5", "gpio6",
2518 "gpio7";
2519 function = "qup9";
2520 };
2521
2522 config {
2523 pins = "gpio4", "gpio5", "gpio6",
2524 "gpio7";
2525 drive-strength = <6>;
2526 bias-disable;
2527 };
2528 };
2529
2530 qupv3_se9_spi_sleep: qupv3_se9_spi_sleep {
2531 mux {
2532 pins = "gpio4", "gpio5", "gpio6",
2533 "gpio7";
2534 function = "gpio";
2535 };
2536
2537 config {
2538 pins = "gpio4", "gpio5", "gpio6",
2539 "gpio7";
2540 drive-strength = <6>;
2541 bias-disable;
2542 };
2543 };
2544 };
2545
2546 /* SE 10 pin mappings */
2547 qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
2548 qupv3_se10_i2c_active: qupv3_se10_i2c_active {
2549 mux {
2550 pins = "gpio55", "gpio56";
2551 function = "qup10";
2552 };
2553
2554 config {
2555 pins = "gpio55", "gpio56";
2556 drive-strength = <2>;
2557 bias-disable;
2558 };
2559 };
2560
2561 qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
2562 mux {
2563 pins = "gpio55", "gpio56";
2564 function = "gpio";
2565 };
2566
2567 config {
2568 pins = "gpio55", "gpio56";
2569 drive-strength = <2>;
2570 bias-pull-up;
2571 };
2572 };
2573 };
2574
2575 qupv3_se10_2uart_pins: qupv3_se10_2uart_pins {
2576 qupv3_se10_2uart_active: qupv3_se10_2uart_active {
2577 mux {
2578 pins = "gpio53", "gpio54";
2579 function = "qup10";
2580 };
2581
2582 config {
2583 pins = "gpio53", "gpio54";
2584 drive-strength = <2>;
2585 bias-disable;
2586 };
2587 };
2588
2589 qupv3_se10_2uart_sleep: qupv3_se10_2uart_sleep {
2590 mux {
2591 pins = "gpio53", "gpio54";
2592 function = "gpio";
2593 };
2594
2595 config {
2596 pins = "gpio53", "gpio54";
2597 drive-strength = <2>;
2598 bias-disable;
2599 };
2600 };
2601 };
2602
2603 qupv3_se10_spi_pins: qupv3_se10_spi_pins {
2604 qupv3_se10_spi_active: qupv3_se10_spi_active {
2605 mux {
2606 pins = "gpio53", "gpio54", "gpio55",
2607 "gpio56";
2608 function = "qup10";
2609 };
2610
2611 config {
2612 pins = "gpio53", "gpio54", "gpio55",
2613 "gpio56";
2614 drive-strength = <6>;
2615 bias-disable;
2616 };
2617 };
2618
2619 qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {
2620 mux {
2621 pins = "gpio53", "gpio54", "gpio55",
2622 "gpio56";
2623 function = "gpio";
2624 };
2625
2626 config {
2627 pins = "gpio53", "gpio54", "gpio55",
2628 "gpio56";
2629 drive-strength = <6>;
2630 bias-disable;
2631 };
2632 };
2633 };
2634
2635 /* SE 11 pin mappings */
2636 qupv3_se11_i2c_pins: qupv3_se11_i2c_pins {
2637 qupv3_se11_i2c_active: qupv3_se11_i2c_active {
2638 mux {
2639 pins = "gpio31", "gpio32";
2640 function = "qup11";
2641 };
2642
2643 config {
2644 pins = "gpio31", "gpio32";
2645 drive-strength = <2>;
2646 bias-disable;
2647 };
2648 };
2649
2650 qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
2651 mux {
2652 pins = "gpio31", "gpio32";
2653 function = "gpio";
2654 };
2655
2656 config {
2657 pins = "gpio31", "gpio32";
2658 drive-strength = <2>;
2659 bias-pull-up;
2660 };
2661 };
2662 };
2663
2664 qupv3_se11_spi_pins: qupv3_se11_spi_pins {
2665 qupv3_se11_spi_active: qupv3_se11_spi_active {
2666 mux {
2667 pins = "gpio31", "gpio32", "gpio33",
2668 "gpio34";
2669 function = "qup11";
2670 };
2671
2672 config {
2673 pins = "gpio31", "gpio32", "gpio33",
2674 "gpio34";
2675 drive-strength = <6>;
2676 bias-disable;
2677 };
2678 };
2679
2680 qupv3_se11_spi_sleep: qupv3_se11_spi_sleep {
2681 mux {
2682 pins = "gpio31", "gpio32", "gpio33",
2683 "gpio34";
2684 function = "gpio";
2685 };
2686
2687 config {
2688 pins = "gpio31", "gpio32", "gpio33",
2689 "gpio34";
2690 drive-strength = <6>;
2691 bias-disable;
2692 };
2693 };
2694 };
2695
2696 /* SE 12 pin mappings */
2697 qupv3_se12_i2c_pins: qupv3_se12_i2c_pins {
2698 qupv3_se12_i2c_active: qupv3_se12_i2c_active {
2699 mux {
2700 pins = "gpio49", "gpio50";
2701 function = "qup12";
2702 };
2703
2704 config {
2705 pins = "gpio49", "gpio50";
2706 drive-strength = <2>;
2707 bias-disable;
2708 };
2709 };
2710
2711 qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep {
2712 mux {
2713 pins = "gpio49", "gpio50";
2714 function = "gpio";
2715 };
2716
2717 config {
2718 pins = "gpio49", "gpio50";
2719 drive-strength = <2>;
2720 bias-pull-up;
2721 };
2722 };
2723 };
2724
2725 qupv3_se12_spi_pins: qupv3_se12_spi_pins {
2726 qupv3_se12_spi_active: qupv3_se12_spi_active {
2727 mux {
2728 pins = "gpio49", "gpio50", "gpio51",
2729 "gpio52";
2730 function = "qup12";
2731 };
2732
2733 config {
2734 pins = "gpio49", "gpio50", "gpio51",
2735 "gpio52";
2736 drive-strength = <6>;
2737 bias-disable;
2738 };
2739 };
2740
2741 qupv3_se12_spi_sleep: qupv3_se12_spi_sleep {
2742 mux {
2743 pins = "gpio49", "gpio50", "gpio51",
2744 "gpio52";
2745 function = "gpio";
2746 };
2747
2748 config {
2749 pins = "gpio49", "gpio50", "gpio51",
2750 "gpio52";
2751 drive-strength = <6>;
2752 bias-disable;
2753 };
2754 };
2755 };
2756
2757 /* SE 13 pin mappings */
2758 qupv3_se13_i2c_pins: qupv3_se13_i2c_pins {
2759 qupv3_se13_i2c_active: qupv3_se13_i2c_active {
2760 mux {
2761 pins = "gpio105", "gpio106";
2762 function = "qup13";
2763 };
2764
2765 config {
2766 pins = "gpio105", "gpio106";
2767 drive-strength = <2>;
2768 bias-disable;
2769 };
2770 };
2771
2772 qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep {
2773 mux {
2774 pins = "gpio105", "gpio106";
2775 function = "gpio";
2776 };
2777
2778 config {
2779 pins = "gpio105", "gpio106";
2780 drive-strength = <2>;
2781 bias-pull-up;
2782 };
2783 };
2784 };
2785
2786 qupv3_se13_spi_pins: qupv3_se13_spi_pins {
2787 qupv3_se13_spi_active: qupv3_se13_spi_active {
2788 mux {
2789 pins = "gpio105", "gpio106", "gpio107",
2790 "gpio108";
2791 function = "qup13";
2792 };
2793
2794 config {
2795 pins = "gpio105", "gpio106", "gpio107",
2796 "gpio108";
2797 drive-strength = <6>;
2798 bias-disable;
2799 };
2800 };
2801
2802 qupv3_se13_spi_sleep: qupv3_se13_spi_sleep {
2803 mux {
2804 pins = "gpio105", "gpio106", "gpio107",
2805 "gpio108";
2806 function = "gpio";
2807 };
2808
2809 config {
2810 pins = "gpio105", "gpio106", "gpio107",
2811 "gpio108";
2812 drive-strength = <6>;
2813 bias-disable;
2814 };
2815 };
2816 };
2817
2818 /* SE 14 pin mappings */
2819 qupv3_se14_i2c_pins: qupv3_se14_i2c_pins {
2820 qupv3_se14_i2c_active: qupv3_se14_i2c_active {
2821 mux {
2822 pins = "gpio33", "gpio34";
2823 function = "qup14";
2824 };
2825
2826 config {
2827 pins = "gpio33", "gpio34";
2828 drive-strength = <2>;
2829 bias-disable;
2830 };
2831 };
2832
2833 qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep {
2834 mux {
2835 pins = "gpio33", "gpio34";
2836 function = "gpio";
2837 };
2838
2839 config {
2840 pins = "gpio33", "gpio34";
2841 drive-strength = <2>;
2842 bias-pull-up;
2843 };
2844 };
2845 };
2846
2847 qupv3_se14_spi_pins: qupv3_se14_spi_pins {
2848 qupv3_se14_spi_active: qupv3_se14_spi_active {
2849 mux {
2850 pins = "gpio31", "gpio32", "gpio33",
2851 "gpio34";
2852 function = "qup14";
2853 };
2854
2855 config {
2856 pins = "gpio31", "gpio32", "gpio33",
2857 "gpio34";
2858 drive-strength = <6>;
2859 bias-disable;
2860 };
2861 };
2862
2863 qupv3_se14_spi_sleep: qupv3_se14_spi_sleep {
2864 mux {
2865 pins = "gpio31", "gpio32", "gpio33",
2866 "gpio34";
2867 function = "gpio";
2868 };
2869
2870 config {
2871 pins = "gpio31", "gpio32", "gpio33",
2872 "gpio34";
2873 drive-strength = <6>;
2874 bias-disable;
2875 };
2876 };
2877 };
2878
2879 /* SE 15 pin mappings */
2880 qupv3_se15_i2c_pins: qupv3_se15_i2c_pins {
2881 qupv3_se15_i2c_active: qupv3_se15_i2c_active {
2882 mux {
2883 pins = "gpio81", "gpio82";
2884 function = "qup15";
2885 };
2886
2887 config {
2888 pins = "gpio81", "gpio82";
2889 drive-strength = <2>;
2890 bias-disable;
2891 };
2892 };
2893
2894 qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep {
2895 mux {
2896 pins = "gpio81", "gpio82";
2897 function = "gpio";
2898 };
2899
2900 config {
2901 pins = "gpio81", "gpio82";
2902 drive-strength = <2>;
2903 bias-pull-up;
2904 };
2905 };
2906 };
2907
2908 qupv3_se15_spi_pins: qupv3_se15_spi_pins {
2909 qupv3_se15_spi_active: qupv3_se15_spi_active {
2910 mux {
2911 pins = "gpio81", "gpio82", "gpio83",
2912 "gpio84";
2913 function = "qup15";
2914 };
2915
2916 config {
2917 pins = "gpio81", "gpio82", "gpio83",
2918 "gpio84";
2919 drive-strength = <6>;
2920 bias-disable;
2921 };
2922 };
2923
2924 qupv3_se15_spi_sleep: qupv3_se15_spi_sleep {
2925 mux {
2926 pins = "gpio81", "gpio82", "gpio83",
2927 "gpio84";
2928 function = "gpio";
2929 };
2930
2931 config {
2932 pins = "gpio81", "gpio82", "gpio83",
2933 "gpio84";
2934 drive-strength = <6>;
2935 bias-disable;
2936 };
2937 };
2938 };
Jigarkumar Zala861231152017-02-28 14:05:11 -08002939
2940 cci0_active: cci0_active {
2941 mux {
2942 /* CLK, DATA */
2943 pins = "gpio17","gpio18"; // Only 2
2944 function = "cci_i2c";
2945 };
2946
2947 config {
2948 pins = "gpio17","gpio18";
2949 bias-pull-up; /* PULL UP*/
2950 drive-strength = <2>; /* 2 MA */
2951 };
2952 };
2953
2954 cci0_suspend: cci0_suspend {
2955 mux {
2956 /* CLK, DATA */
2957 pins = "gpio17","gpio18";
2958 function = "cci_i2c";
2959 };
2960
2961 config {
2962 pins = "gpio17","gpio18";
2963 bias-pull-down; /* PULL DOWN */
2964 drive-strength = <2>; /* 2 MA */
2965 };
2966 };
2967
2968 cci1_active: cci1_active {
2969 mux {
2970 /* CLK, DATA */
2971 pins = "gpio19","gpio20";
2972 function = "cci_i2c";
2973 };
2974
2975 config {
2976 pins = "gpio19","gpio20";
2977 bias-pull-up; /* PULL UP*/
2978 drive-strength = <2>; /* 2 MA */
2979 };
2980 };
2981
2982 cci1_suspend: cci1_suspend {
2983 mux {
2984 /* CLK, DATA */
2985 pins = "gpio19","gpio20";
2986 function = "cci_i2c";
2987 };
2988
2989 config {
2990 pins = "gpio19","gpio20";
2991 bias-pull-down; /* PULL DOWN */
2992 drive-strength = <2>; /* 2 MA */
2993 };
2994 };
2995
2996 cam_sensor_mclk0_active: cam_sensor_mclk0_active {
2997 /* MCLK0 */
2998 mux {
2999 pins = "gpio13";
3000 function = "cam_mclk";
3001 };
3002
3003 config {
3004 pins = "gpio13";
3005 bias-disable; /* No PULL */
3006 drive-strength = <2>; /* 2 MA */
3007 };
3008 };
3009
3010 cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend {
3011 /* MCLK0 */
3012 mux {
3013 pins = "gpio13";
3014 function = "cam_mclk";
3015 };
3016
3017 config {
3018 pins = "gpio13";
3019 bias-pull-down; /* PULL DOWN */
3020 drive-strength = <2>; /* 2 MA */
3021 };
3022 };
3023
3024 cam_sensor_rear_active: cam_sensor_rear_active {
3025 /* RESET, AVDD LDO */
3026 mux {
3027 pins = "gpio80","gpio79";
3028 function = "gpio";
3029 };
3030
3031 config {
3032 pins = "gpio80","gpio79";
3033 bias-disable; /* No PULL */
3034 drive-strength = <2>; /* 2 MA */
3035 };
3036 };
3037
3038 cam_sensor_rear_suspend: cam_sensor_rear_suspend {
3039 /* RESET, AVDD LDO */
3040 mux {
3041 pins = "gpio80","gpio79";
3042 function = "gpio";
3043 };
3044
3045 config {
3046 pins = "gpio80","gpio79";
Jeyaprakash Soundrapandian902116a2017-07-20 18:17:59 -07003047 bias-pull-down; /* PULL DOWN */
Jigarkumar Zala861231152017-02-28 14:05:11 -08003048 drive-strength = <2>; /* 2 MA */
Karthik Anantha Rame87f1ee2017-08-24 14:05:36 -07003049 output-low;
Jigarkumar Zala861231152017-02-28 14:05:11 -08003050 };
3051 };
3052
3053 cam_sensor_mclk1_active: cam_sensor_mclk1_active {
3054 /* MCLK1 */
3055 mux {
3056 pins = "gpio14";
3057 function = "cam_mclk";
3058 };
3059
3060 config {
3061 pins = "gpio14";
3062 bias-disable; /* No PULL */
3063 drive-strength = <2>; /* 2 MA */
3064 };
3065 };
3066
3067 cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend {
3068 /* MCLK1 */
3069 mux {
3070 pins = "gpio14";
3071 function = "cam_mclk";
3072 };
3073
3074 config {
3075 pins = "gpio14";
3076 bias-pull-down; /* PULL DOWN */
3077 drive-strength = <2>; /* 2 MA */
3078 };
3079 };
3080
Jigarkumar Zala9e214912017-09-14 16:40:03 -07003081 cam_sensor_mclk3_active: cam_sensor_mclk3_active {
3082 /* MCLK3 */
3083 mux {
3084 pins = "gpio16";
3085 function = "cam_mclk";
3086 };
3087
3088 config {
3089 pins = "gpio16";
3090 bias-disable; /* No PULL */
3091 drive-strength = <2>; /* 2 MA */
3092 };
3093 };
3094
3095 cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend {
3096 /* MCLK3 */
3097 mux {
3098 pins = "gpio16";
3099 function = "cam_mclk";
3100 };
3101
3102 config {
3103 pins = "gpio16";
3104 bias-pull-down; /* PULL DOWN */
3105 drive-strength = <2>; /* 2 MA */
3106 };
3107 };
3108
3109
Jigarkumar Zala861231152017-02-28 14:05:11 -08003110 cam_sensor_front_active: cam_sensor_front_active {
3111 /* RESET AVDD_LDO*/
3112 mux {
Jilai Wange0297632017-11-15 18:15:10 -05003113 pins = "gpio28";
Jigarkumar Zala861231152017-02-28 14:05:11 -08003114 function = "gpio";
3115 };
3116
3117 config {
Jilai Wange0297632017-11-15 18:15:10 -05003118 pins = "gpio28";
Jigarkumar Zala861231152017-02-28 14:05:11 -08003119 bias-disable; /* No PULL */
3120 drive-strength = <2>; /* 2 MA */
3121 };
3122 };
3123
3124 cam_sensor_front_suspend: cam_sensor_front_suspend {
3125 /* RESET */
3126 mux {
3127 pins = "gpio28";
3128 function = "gpio";
3129 };
3130
3131 config {
3132 pins = "gpio28";
Jeyaprakash Soundrapandian902116a2017-07-20 18:17:59 -07003133 bias-pull-down; /* PULL DOWN */
Jigarkumar Zala861231152017-02-28 14:05:11 -08003134 drive-strength = <2>; /* 2 MA */
Karthik Anantha Rame87f1ee2017-08-24 14:05:36 -07003135 output-low;
Jigarkumar Zala861231152017-02-28 14:05:11 -08003136 };
3137 };
3138
Jigarkumar Zala9e214912017-09-14 16:40:03 -07003139 cam_sensor_iris_active: cam_sensor_iris_active {
3140 /* RESET AVDD_LDO*/
3141 mux {
Jilai Wange0297632017-11-15 18:15:10 -05003142 pins = "gpio9";
Jigarkumar Zala9e214912017-09-14 16:40:03 -07003143 function = "gpio";
3144 };
3145
3146 config {
Jilai Wange0297632017-11-15 18:15:10 -05003147 pins = "gpio9";
Jigarkumar Zala9e214912017-09-14 16:40:03 -07003148 bias-disable; /* No PULL */
3149 drive-strength = <2>; /* 2 MA */
3150 };
3151 };
3152
3153 cam_sensor_iris_suspend: cam_sensor_iris_suspend {
3154 /* RESET */
3155 mux {
3156 pins = "gpio9";
3157 function = "gpio";
3158 };
3159
3160 config {
3161 pins = "gpio9";
3162 bias-disable; /* No PULL */
3163 drive-strength = <2>; /* 2 MA */
3164 output-low;
3165 };
3166 };
3167
3168
Jigarkumar Zala861231152017-02-28 14:05:11 -08003169 cam_sensor_mclk2_active: cam_sensor_mclk2_active {
3170 /* MCLK1 */
3171 mux {
3172 /* CLK, DATA */
3173 pins = "gpio15";
3174 function = "cam_mclk";
3175 };
3176
3177 config {
3178 pins = "gpio15";
3179 bias-disable; /* No PULL */
3180 drive-strength = <2>; /* 2 MA */
3181 };
3182 };
3183
3184 cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend {
3185 /* MCLK1 */
3186 mux {
3187 /* CLK, DATA */
3188 pins = "gpio15";
3189 function = "cam_mclk";
3190 };
3191
3192 config {
3193 pins = "gpio15";
3194 bias-pull-down; /* PULL DOWN */
3195 drive-strength = <2>; /* 2 MA */
3196 };
3197 };
3198
3199 cam_sensor_rear2_active: cam_sensor_rear2_active {
3200 /* RESET, STANDBY */
3201 mux {
Jilai Wange0297632017-11-15 18:15:10 -05003202 pins = "gpio9";
Jigarkumar Zala861231152017-02-28 14:05:11 -08003203 function = "gpio";
3204 };
3205
3206 config {
Jilai Wange0297632017-11-15 18:15:10 -05003207 pins = "gpio9";
Jigarkumar Zala861231152017-02-28 14:05:11 -08003208 bias-disable; /* No PULL */
3209 drive-strength = <2>; /* 2 MA */
3210 };
3211 };
3212
3213 cam_sensor_rear2_suspend: cam_sensor_rear2_suspend {
3214 /* RESET, STANDBY */
3215 mux {
Jilai Wange0297632017-11-15 18:15:10 -05003216 pins = "gpio9";
Jigarkumar Zala861231152017-02-28 14:05:11 -08003217 function = "gpio";
3218 };
3219 config {
Jilai Wange0297632017-11-15 18:15:10 -05003220 pins = "gpio9";
Jeyaprakash Soundrapandian902116a2017-07-20 18:17:59 -07003221 bias-pull-down; /* PULL DOWN */
Jigarkumar Zala861231152017-02-28 14:05:11 -08003222 drive-strength = <2>; /* 2 MA */
Karthik Anantha Rame87f1ee2017-08-24 14:05:36 -07003223 output-low;
Jigarkumar Zala861231152017-02-28 14:05:11 -08003224 };
3225 };
Satyajit Desaie4508132017-04-05 17:15:22 -07003226
Vivek Veenam38718002017-12-21 17:34:57 +05303227 cam_sensor_rear_vana: cam_sensor_rear_vana {
3228 /* AVDD LDO */
3229 mux {
3230 pins = "gpio8";
3231 function = "gpio";
3232 };
3233
3234 config {
3235 pins = "gpio8";
3236 bias-disable; /* No PULL */
3237 drive-strength = <2>; /* 2 MA */
3238 };
3239 };
3240
Jilai Wange0297632017-11-15 18:15:10 -05003241 cam_res_mgr_active: cam_res_mgr_active {
3242 /* AVDD_LDO*/
3243 mux {
3244 pins = "gpio8";
3245 function = "gpio";
3246 };
3247
3248 config {
3249 pins = "gpio8";
3250 bias-disable; /* No PULL */
3251 drive-strength = <2>; /* 2 MA */
3252 };
3253 };
3254
3255 cam_res_mgr_suspend: cam_res_mgr_suspend {
3256 /* AVDD_LDO */
3257 mux {
3258 pins = "gpio8";
3259 function = "gpio";
3260 };
3261
3262 config {
3263 pins = "gpio8";
3264 bias-disable; /* No PULL */
3265 drive-strength = <2>; /* 2 MA */
3266 output-low;
3267 };
3268 };
3269
3270
Satyajit Desaie4508132017-04-05 17:15:22 -07003271 trigout_a: trigout_a {
3272 mux {
Satyajit Desai602a6712017-05-09 14:45:16 -07003273 pins = "gpio90";
Satyajit Desaie4508132017-04-05 17:15:22 -07003274 function = "qdss_cti";
3275 };
3276 config {
Satyajit Desai602a6712017-05-09 14:45:16 -07003277 pins = "gpio90";
Satyajit Desaie4508132017-04-05 17:15:22 -07003278 drive-strength = <2>;
3279 bias-disable;
3280 };
3281 };
Udaya Bhaskara Reddy Mallavarapu55ef0cb2017-06-12 14:45:28 +05303282
3283 tsif0_signals_active: tsif0_signals_active {
3284 tsif1_clk {
3285 pins = "gpio89"; /* TSIF0 CLK */
3286 function = "tsif1_clk";
3287 };
3288 tsif1_en {
3289 pins = "gpio90"; /* TSIF0 Enable */
3290 function = "tsif1_en";
3291 };
3292 tsif1_data {
3293 pins = "gpio91"; /* TSIF0 DATA */
3294 function = "tsif1_data";
3295 };
3296 signals_cfg {
3297 pins = "gpio89", "gpio90", "gpio91";
3298 drive_strength = <2>; /* 2 mA */
3299 bias-pull-down; /* pull down */
3300 };
3301 };
3302
3303 /* sync signal is only used if configured to mode-2 */
3304 tsif0_sync_active: tsif0_sync_active {
3305 tsif1_sync {
3306 pins = "gpio12"; /* TSIF0 SYNC */
3307 function = "tsif1_sync";
3308 drive_strength = <2>; /* 2 mA */
3309 bias-pull-down; /* pull down */
3310 };
3311 };
3312
3313 tsif1_signals_active: tsif1_signals_active {
3314 tsif2_clk {
3315 pins = "gpio93"; /* TSIF1 CLK */
3316 function = "tsif2_clk";
3317 };
3318 tsif2_en {
3319 pins = "gpio94"; /* TSIF1 Enable */
3320 function = "tsif2_en";
3321 };
3322 tsif2_data {
3323 pins = "gpio95"; /* TSIF1 DATA */
3324 function = "tsif2_data";
3325 };
3326 signals_cfg {
3327 pins = "gpio93", "gpio94", "gpio95";
3328 drive_strength = <2>; /* 2 mA */
3329 bias-pull-down; /* pull down */
3330 };
3331 };
3332
3333 /* sync signal is only used if configured to mode-2 */
3334 tsif1_sync_active: tsif1_sync_active {
3335 tsif2_sync {
3336 pins = "gpio96"; /* TSIF1 SYNC */
3337 function = "tsif2_sync";
3338 drive_strength = <2>; /* 2 mA */
3339 bias-pull-down; /* pull down */
3340 };
3341 };
Raghavendra Rao Ananta2f75ed72017-10-18 10:14:05 -07003342
3343 ap2mdm {
3344 ap2mdm_active: ap2mdm_active {
3345 mux {
3346 /* ap2mdm-status
3347 * ap2mdm-errfatal
3348 * ap2mdm-vddmin
3349 */
3350 pins = "gpio21", "gpio23";
3351 function = "gpio";
3352 };
3353
3354 config {
3355 pins = "gpio21", "gpio23";
3356 drive-strength = <16>;
3357 bias-disable;
3358 };
3359 };
3360 ap2mdm_sleep: ap2mdm_sleep {
3361 mux {
3362 /* ap2mdm-status
3363 * ap2mdm-errfatal
3364 * ap2mdm-vddmin
3365 */
3366 pins = "gpio21", "gpio23";
3367 function = "gpio";
3368 };
3369
3370 config {
3371 pins = "gpio21", "gpio23";
3372 drive-strength = <8>;
3373 bias-disable;
3374 };
3375
3376 };
3377 };
3378
3379 mdm2ap {
3380 mdm2ap_active: mdm2ap_active {
3381 mux {
3382 /* mdm2ap-status
3383 * mdm2ap-errfatal
3384 * mdm2ap-vddmin
3385 */
3386 pins = "gpio22", "gpio20";
3387 function = "gpio";
3388 };
3389
3390 config {
3391 pins = "gpio22", "gpio20";
3392 drive-strength = <8>;
3393 bias-disable;
3394 };
3395 };
3396 mdm2ap_sleep: mdm2ap_sleep {
3397 mux {
3398 /* mdm2ap-status
3399 * mdm2ap-errfatal
3400 * mdm2ap-vddmin
3401 */
3402 pins = "gpio22", "gpio20";
3403 function = "gpio";
3404 };
3405
3406 config {
3407 pins = "gpio22", "gpio20";
3408 drive-strength = <8>;
3409 bias-disable;
3410 };
3411 };
3412 };
Kyle Yan679cbee2016-07-27 16:55:20 -07003413 };
3414};
David Collinsc6686252017-03-31 14:23:09 -07003415
3416&pm8998_gpios {
3417 key_home {
3418 key_home_default: key_home_default {
3419 pins = "gpio5";
3420 function = "normal";
3421 input-enable;
3422 bias-pull-up;
3423 power-source = <0>;
3424 };
3425 };
3426
3427 key_vol_up {
3428 key_vol_up_default: key_vol_up_default {
3429 pins = "gpio6";
3430 function = "normal";
3431 input-enable;
3432 bias-pull-up;
3433 power-source = <0>;
3434 };
3435 };
3436
3437 key_cam_snapshot {
3438 key_cam_snapshot_default: key_cam_snapshot_default {
3439 pins = "gpio7";
3440 function = "normal";
3441 input-enable;
3442 bias-pull-up;
3443 power-source = <0>;
3444 };
3445 };
3446
3447 key_cam_focus {
3448 key_cam_focus_default: key_cam_focus_default {
3449 pins = "gpio8";
3450 function = "normal";
3451 input-enable;
3452 bias-pull-up;
3453 power-source = <0>;
3454 };
3455 };
Jigarkumar Zala861231152017-02-28 14:05:11 -08003456
3457 camera_dvdd_en {
3458 camera_dvdd_en_default: camera_dvdd_en_default {
3459 pins = "gpio9";
3460 function = "normal";
3461 power-source = <0>;
3462 output-low;
3463 };
3464 };
3465
3466 camera_rear_dvdd_en {
3467 camera_rear_dvdd_en_default: camera_rear_dvdd_en_default {
3468 pins = "gpio12";
3469 function = "normal";
3470 power-source = <0>;
3471 output-low;
3472 };
3473 };
Gaurav Singhal243b94b2017-06-20 14:16:59 +05303474
3475 nfc_clk {
3476 nfc_clk_default: nfc_clk_default {
3477 pins = "gpio21";
3478 function = "normal";
3479 input-enable;
3480 power-source = <1>;
3481 };
3482 };
David Collinsc6686252017-03-31 14:23:09 -07003483};