Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
| 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 5 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 8 | * copy of this software and associated documentation files (the |
| 9 | * "Software"), to deal in the Software without restriction, including |
| 10 | * without limitation the rights to use, copy, modify, merge, publish, |
| 11 | * distribute, sub license, and/or sell copies of the Software, and to |
| 12 | * permit persons to whom the Software is furnished to do so, subject to |
| 13 | * the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the |
| 16 | * next paragraph) shall be included in all copies or substantial portions |
| 17 | * of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 26 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 27 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 30 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 31 | #include <drm/drmP.h> |
| 32 | #include <drm/drm_crtc_helper.h> |
| 33 | #include <drm/drm_fb_helper.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 34 | #include "intel_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 35 | #include <drm/i915_drm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 37 | #include "i915_trace.h" |
Jordan Crouse | dcdb167 | 2010-05-27 13:40:25 -0600 | [diff] [blame] | 38 | #include <linux/pci.h> |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 39 | #include <linux/vgaarb.h> |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 40 | #include <linux/acpi.h> |
| 41 | #include <linux/pnp.h> |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 42 | #include <linux/vga_switcheroo.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 43 | #include <linux/slab.h> |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 44 | #include <acpi/video.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | |
Daniel Vetter | 09422b2 | 2012-04-26 23:28:10 +0200 | [diff] [blame] | 46 | #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
| 47 | |
| 48 | #define BEGIN_LP_RING(n) \ |
| 49 | intel_ring_begin(LP_RING(dev_priv), (n)) |
| 50 | |
| 51 | #define OUT_RING(x) \ |
| 52 | intel_ring_emit(LP_RING(dev_priv), x) |
| 53 | |
| 54 | #define ADVANCE_LP_RING() \ |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 55 | __intel_ring_advance(LP_RING(dev_priv)) |
Daniel Vetter | 09422b2 | 2012-04-26 23:28:10 +0200 | [diff] [blame] | 56 | |
| 57 | /** |
| 58 | * Lock test for when it's just for synchronization of ring access. |
| 59 | * |
| 60 | * In that case, we don't need to do it when GEM is initialized as nobody else |
| 61 | * has access to the ring. |
| 62 | */ |
| 63 | #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ |
| 64 | if (LP_RING(dev->dev_private)->obj == NULL) \ |
| 65 | LOCK_TEST_WITH_RETURN(dev, file); \ |
| 66 | } while (0) |
| 67 | |
Daniel Vetter | 316d388 | 2012-04-26 23:28:15 +0200 | [diff] [blame] | 68 | static inline u32 |
| 69 | intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg) |
| 70 | { |
| 71 | if (I915_NEED_GFX_HWS(dev_priv->dev)) |
| 72 | return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg); |
| 73 | else |
| 74 | return intel_read_status_page(LP_RING(dev_priv), reg); |
| 75 | } |
| 76 | |
| 77 | #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg) |
Daniel Vetter | 09422b2 | 2012-04-26 23:28:10 +0200 | [diff] [blame] | 78 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) |
| 79 | #define I915_BREADCRUMB_INDEX 0x21 |
| 80 | |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 81 | void i915_update_dri1_breadcrumb(struct drm_device *dev) |
| 82 | { |
| 83 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 84 | struct drm_i915_master_private *master_priv; |
| 85 | |
Daniel Vetter | 6c719fa | 2013-12-10 13:20:59 +0100 | [diff] [blame] | 86 | /* |
| 87 | * The dri breadcrumb update races against the drm master disappearing. |
| 88 | * Instead of trying to fix this (this is by far not the only ums issue) |
| 89 | * just don't do the update in kms mode. |
| 90 | */ |
| 91 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 92 | return; |
| 93 | |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 94 | if (dev->primary->master) { |
| 95 | master_priv = dev->primary->master->driver_priv; |
| 96 | if (master_priv->sarea_priv) |
| 97 | master_priv->sarea_priv->last_dispatch = |
| 98 | READ_BREADCRUMB(dev_priv); |
| 99 | } |
| 100 | } |
| 101 | |
Chris Wilson | 4cbf74c | 2011-02-25 22:26:23 +0000 | [diff] [blame] | 102 | static void i915_write_hws_pga(struct drm_device *dev) |
| 103 | { |
| 104 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 105 | u32 addr; |
| 106 | |
| 107 | addr = dev_priv->status_page_dmah->busaddr; |
| 108 | if (INTEL_INFO(dev)->gen >= 4) |
| 109 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
| 110 | I915_WRITE(HWS_PGA, addr); |
| 111 | } |
| 112 | |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 113 | /** |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 114 | * Frees the hardware status page, whether it's a physical address or a virtual |
| 115 | * address set up by the X Server. |
| 116 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 117 | static void i915_free_hws(struct drm_device *dev) |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 118 | { |
| 119 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 120 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
| 121 | |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 122 | if (dev_priv->status_page_dmah) { |
| 123 | drm_pci_free(dev, dev_priv->status_page_dmah); |
| 124 | dev_priv->status_page_dmah = NULL; |
| 125 | } |
| 126 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 127 | if (ring->status_page.gfx_addr) { |
| 128 | ring->status_page.gfx_addr = 0; |
Daniel Vetter | 316d388 | 2012-04-26 23:28:15 +0200 | [diff] [blame] | 129 | iounmap(dev_priv->dri1.gfx_hws_cpu_addr); |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 130 | } |
| 131 | |
| 132 | /* Need to rewrite hardware status page */ |
| 133 | I915_WRITE(HWS_PGA, 0x1ffff000); |
| 134 | } |
| 135 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 136 | void i915_kernel_lost_context(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 137 | { |
| 138 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 139 | struct drm_i915_master_private *master_priv; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 140 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 141 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 142 | /* |
| 143 | * We should never lose context on the ring with modesetting |
| 144 | * as we don't expose it to userspace |
| 145 | */ |
| 146 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 147 | return; |
| 148 | |
Chris Wilson | 8168bd4 | 2010-11-11 17:54:52 +0000 | [diff] [blame] | 149 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
| 150 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
Ville Syrjälä | 633cf8f | 2012-12-03 18:43:32 +0200 | [diff] [blame] | 151 | ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 152 | if (ring->space < 0) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 153 | ring->space += ring->size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 154 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 155 | if (!dev->primary->master) |
| 156 | return; |
| 157 | |
| 158 | master_priv = dev->primary->master->driver_priv; |
| 159 | if (ring->head == ring->tail && master_priv->sarea_priv) |
| 160 | master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 161 | } |
| 162 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 163 | static int i915_dma_cleanup(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | { |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 165 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 166 | int i; |
| 167 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 168 | /* Make sure interrupts are disabled here because the uninstall ioctl |
| 169 | * may not have been called from userspace and after dev_private |
| 170 | * is freed, it's too late. |
| 171 | */ |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 172 | if (dev->irq_enabled) |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 173 | drm_irq_uninstall(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 174 | |
Dan Carpenter | ee0c6bf | 2010-06-23 13:19:55 +0200 | [diff] [blame] | 175 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 176 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 177 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); |
Dan Carpenter | ee0c6bf | 2010-06-23 13:19:55 +0200 | [diff] [blame] | 178 | mutex_unlock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 179 | |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 180 | /* Clear the HWS virtual address at teardown */ |
| 181 | if (I915_NEED_GFX_HWS(dev)) |
| 182 | i915_free_hws(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 183 | |
| 184 | return 0; |
| 185 | } |
| 186 | |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 187 | static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 188 | { |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 189 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 190 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 191 | int ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 192 | |
Dave Airlie | 3a03ac1 | 2009-01-11 09:03:49 +1000 | [diff] [blame] | 193 | master_priv->sarea = drm_getsarea(dev); |
| 194 | if (master_priv->sarea) { |
| 195 | master_priv->sarea_priv = (drm_i915_sarea_t *) |
| 196 | ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); |
| 197 | } else { |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 198 | DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); |
Dave Airlie | 3a03ac1 | 2009-01-11 09:03:49 +1000 | [diff] [blame] | 199 | } |
| 200 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 201 | if (init->ring_size != 0) { |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 202 | if (LP_RING(dev_priv)->obj != NULL) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 203 | i915_dma_cleanup(dev); |
| 204 | DRM_ERROR("Client tried to initialize ringbuffer in " |
| 205 | "GEM mode\n"); |
| 206 | return -EINVAL; |
| 207 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 208 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 209 | ret = intel_render_ring_init_dri(dev, |
| 210 | init->ring_start, |
| 211 | init->ring_size); |
| 212 | if (ret) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 213 | i915_dma_cleanup(dev); |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 214 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 215 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 216 | } |
| 217 | |
Daniel Vetter | 5d985ac | 2012-08-12 19:27:13 +0200 | [diff] [blame] | 218 | dev_priv->dri1.cpp = init->cpp; |
| 219 | dev_priv->dri1.back_offset = init->back_offset; |
| 220 | dev_priv->dri1.front_offset = init->front_offset; |
| 221 | dev_priv->dri1.current_page = 0; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 222 | if (master_priv->sarea_priv) |
| 223 | master_priv->sarea_priv->pf_current_page = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 224 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 225 | /* Allow hardware batchbuffers unless told otherwise. |
| 226 | */ |
Daniel Vetter | 8781342 | 2012-05-02 11:49:32 +0200 | [diff] [blame] | 227 | dev_priv->dri1.allow_batchbuffer = 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 228 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 229 | return 0; |
| 230 | } |
| 231 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 232 | static int i915_dma_resume(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 233 | { |
| 234 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 235 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 236 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 237 | DRM_DEBUG_DRIVER("%s\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 238 | |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 239 | if (ring->virtual_start == NULL) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 240 | DRM_ERROR("can not ioremap virtual address for" |
| 241 | " ring buffer\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 242 | return -ENOMEM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 243 | } |
| 244 | |
| 245 | /* Program Hardware Status Page */ |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 246 | if (!ring->status_page.page_addr) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 247 | DRM_ERROR("Can not find hardware status page\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 248 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 249 | } |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 250 | DRM_DEBUG_DRIVER("hw status page @ %p\n", |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 251 | ring->status_page.page_addr); |
| 252 | if (ring->status_page.gfx_addr != 0) |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 253 | intel_ring_setup_status_page(ring); |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 254 | else |
Chris Wilson | 4cbf74c | 2011-02-25 22:26:23 +0000 | [diff] [blame] | 255 | i915_write_hws_pga(dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 256 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 257 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 258 | |
| 259 | return 0; |
| 260 | } |
| 261 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 262 | static int i915_dma_init(struct drm_device *dev, void *data, |
| 263 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 264 | { |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 265 | drm_i915_init_t *init = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 266 | int retcode = 0; |
| 267 | |
Daniel Vetter | cd9d4e9 | 2012-04-24 08:29:42 +0200 | [diff] [blame] | 268 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 269 | return -ENODEV; |
| 270 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 271 | switch (init->func) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 272 | case I915_INIT_DMA: |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 273 | retcode = i915_initialize(dev, init); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 274 | break; |
| 275 | case I915_CLEANUP_DMA: |
| 276 | retcode = i915_dma_cleanup(dev); |
| 277 | break; |
| 278 | case I915_RESUME_DMA: |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 279 | retcode = i915_dma_resume(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 280 | break; |
| 281 | default: |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 282 | retcode = -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 283 | break; |
| 284 | } |
| 285 | |
| 286 | return retcode; |
| 287 | } |
| 288 | |
| 289 | /* Implement basically the same security restrictions as hardware does |
| 290 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. |
| 291 | * |
| 292 | * Most of the calculations below involve calculating the size of a |
| 293 | * particular instruction. It's important to get the size right as |
| 294 | * that tells us where the next instruction to check is. Any illegal |
| 295 | * instruction detected will be given a size of zero, which is a |
| 296 | * signal to abort the rest of the buffer. |
| 297 | */ |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 298 | static int validate_cmd(int cmd) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 299 | { |
| 300 | switch (((cmd >> 29) & 0x7)) { |
| 301 | case 0x0: |
| 302 | switch ((cmd >> 23) & 0x3f) { |
| 303 | case 0x0: |
| 304 | return 1; /* MI_NOOP */ |
| 305 | case 0x4: |
| 306 | return 1; /* MI_FLUSH */ |
| 307 | default: |
| 308 | return 0; /* disallow everything else */ |
| 309 | } |
| 310 | break; |
| 311 | case 0x1: |
| 312 | return 0; /* reserved */ |
| 313 | case 0x2: |
| 314 | return (cmd & 0xff) + 2; /* 2d commands */ |
| 315 | case 0x3: |
| 316 | if (((cmd >> 24) & 0x1f) <= 0x18) |
| 317 | return 1; |
| 318 | |
| 319 | switch ((cmd >> 24) & 0x1f) { |
| 320 | case 0x1c: |
| 321 | return 1; |
| 322 | case 0x1d: |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 323 | switch ((cmd >> 16) & 0xff) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 324 | case 0x3: |
| 325 | return (cmd & 0x1f) + 2; |
| 326 | case 0x4: |
| 327 | return (cmd & 0xf) + 2; |
| 328 | default: |
| 329 | return (cmd & 0xffff) + 2; |
| 330 | } |
| 331 | case 0x1e: |
| 332 | if (cmd & (1 << 23)) |
| 333 | return (cmd & 0xffff) + 1; |
| 334 | else |
| 335 | return 1; |
| 336 | case 0x1f: |
| 337 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ |
| 338 | return (cmd & 0x1ffff) + 2; |
| 339 | else if (cmd & (1 << 17)) /* indirect random */ |
| 340 | if ((cmd & 0xffff) == 0) |
| 341 | return 0; /* unknown length, too hard */ |
| 342 | else |
| 343 | return (((cmd & 0xffff) + 1) / 2) + 1; |
| 344 | else |
| 345 | return 2; /* indirect sequential */ |
| 346 | default: |
| 347 | return 0; |
| 348 | } |
| 349 | default: |
| 350 | return 0; |
| 351 | } |
| 352 | |
| 353 | return 0; |
| 354 | } |
| 355 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 356 | static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 357 | { |
| 358 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 359 | int i, ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 360 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 361 | if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8) |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 362 | return -EINVAL; |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 363 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 364 | for (i = 0; i < dwords;) { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 365 | int sz = validate_cmd(buffer[i]); |
| 366 | if (sz == 0 || i + sz > dwords) |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 367 | return -EINVAL; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 368 | i += sz; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 369 | } |
| 370 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 371 | ret = BEGIN_LP_RING((dwords+1)&~1); |
| 372 | if (ret) |
| 373 | return ret; |
| 374 | |
| 375 | for (i = 0; i < dwords; i++) |
| 376 | OUT_RING(buffer[i]); |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 377 | if (dwords & 1) |
| 378 | OUT_RING(0); |
| 379 | |
| 380 | ADVANCE_LP_RING(); |
| 381 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 382 | return 0; |
| 383 | } |
| 384 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 385 | int |
| 386 | i915_emit_box(struct drm_device *dev, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 387 | struct drm_clip_rect *box, |
| 388 | int DR1, int DR4) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 389 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 390 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 391 | int ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 392 | |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 393 | if (box->y2 <= box->y1 || box->x2 <= box->x1 || |
| 394 | box->y2 <= 0 || box->x2 <= 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 395 | DRM_ERROR("Bad box %d,%d..%d,%d\n", |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 396 | box->x1, box->y1, box->x2, box->y2); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 397 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 398 | } |
| 399 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 400 | if (INTEL_INFO(dev)->gen >= 4) { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 401 | ret = BEGIN_LP_RING(4); |
| 402 | if (ret) |
| 403 | return ret; |
| 404 | |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 405 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 406 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
| 407 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 408 | OUT_RING(DR4); |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 409 | } else { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 410 | ret = BEGIN_LP_RING(6); |
| 411 | if (ret) |
| 412 | return ret; |
| 413 | |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 414 | OUT_RING(GFX_OP_DRAWRECT_INFO); |
| 415 | OUT_RING(DR1); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 416 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
| 417 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 418 | OUT_RING(DR4); |
| 419 | OUT_RING(0); |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 420 | } |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 421 | ADVANCE_LP_RING(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 422 | |
| 423 | return 0; |
| 424 | } |
| 425 | |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 426 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
| 427 | * emit. For now, do it in both places: |
| 428 | */ |
| 429 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 430 | static void i915_emit_breadcrumb(struct drm_device *dev) |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 431 | { |
| 432 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 433 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 434 | |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 435 | dev_priv->dri1.counter++; |
| 436 | if (dev_priv->dri1.counter > 0x7FFFFFFFUL) |
| 437 | dev_priv->dri1.counter = 0; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 438 | if (master_priv->sarea_priv) |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 439 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter; |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 440 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 441 | if (BEGIN_LP_RING(4) == 0) { |
| 442 | OUT_RING(MI_STORE_DWORD_INDEX); |
| 443 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 444 | OUT_RING(dev_priv->dri1.counter); |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 445 | OUT_RING(0); |
| 446 | ADVANCE_LP_RING(); |
| 447 | } |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 448 | } |
| 449 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 450 | static int i915_dispatch_cmdbuffer(struct drm_device * dev, |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 451 | drm_i915_cmdbuffer_t *cmd, |
| 452 | struct drm_clip_rect *cliprects, |
| 453 | void *cmdbuf) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 454 | { |
| 455 | int nbox = cmd->num_cliprects; |
| 456 | int i = 0, count, ret; |
| 457 | |
| 458 | if (cmd->sz & 0x3) { |
| 459 | DRM_ERROR("alignment"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 460 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 461 | } |
| 462 | |
| 463 | i915_kernel_lost_context(dev); |
| 464 | |
| 465 | count = nbox ? nbox : 1; |
| 466 | |
| 467 | for (i = 0; i < count; i++) { |
| 468 | if (i < nbox) { |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 469 | ret = i915_emit_box(dev, &cliprects[i], |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 470 | cmd->DR1, cmd->DR4); |
| 471 | if (ret) |
| 472 | return ret; |
| 473 | } |
| 474 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 475 | ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 476 | if (ret) |
| 477 | return ret; |
| 478 | } |
| 479 | |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 480 | i915_emit_breadcrumb(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 481 | return 0; |
| 482 | } |
| 483 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 484 | static int i915_dispatch_batchbuffer(struct drm_device * dev, |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 485 | drm_i915_batchbuffer_t * batch, |
| 486 | struct drm_clip_rect *cliprects) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 487 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 488 | struct drm_i915_private *dev_priv = dev->dev_private; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 489 | int nbox = batch->num_cliprects; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 490 | int i, count, ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 491 | |
| 492 | if ((batch->start | batch->used) & 0x7) { |
| 493 | DRM_ERROR("alignment"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 494 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 495 | } |
| 496 | |
| 497 | i915_kernel_lost_context(dev); |
| 498 | |
| 499 | count = nbox ? nbox : 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 500 | for (i = 0; i < count; i++) { |
| 501 | if (i < nbox) { |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 502 | ret = i915_emit_box(dev, &cliprects[i], |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 503 | batch->DR1, batch->DR4); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 504 | if (ret) |
| 505 | return ret; |
| 506 | } |
| 507 | |
Keith Packard | 0790d5e | 2008-07-30 12:28:47 -0700 | [diff] [blame] | 508 | if (!IS_I830(dev) && !IS_845G(dev)) { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 509 | ret = BEGIN_LP_RING(2); |
| 510 | if (ret) |
| 511 | return ret; |
| 512 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 513 | if (INTEL_INFO(dev)->gen >= 4) { |
Dave Airlie | 21f1628 | 2007-08-07 09:09:51 +1000 | [diff] [blame] | 514 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); |
| 515 | OUT_RING(batch->start); |
| 516 | } else { |
| 517 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); |
| 518 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); |
| 519 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 520 | } else { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 521 | ret = BEGIN_LP_RING(4); |
| 522 | if (ret) |
| 523 | return ret; |
| 524 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 525 | OUT_RING(MI_BATCH_BUFFER); |
| 526 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); |
| 527 | OUT_RING(batch->start + batch->used - 4); |
| 528 | OUT_RING(0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 529 | } |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 530 | ADVANCE_LP_RING(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 531 | } |
| 532 | |
Zou Nan hai | 1cafd34 | 2010-06-25 13:40:24 +0800 | [diff] [blame] | 533 | |
Chris Wilson | f00a3dd | 2010-10-21 14:57:17 +0100 | [diff] [blame] | 534 | if (IS_G4X(dev) || IS_GEN5(dev)) { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 535 | if (BEGIN_LP_RING(2) == 0) { |
| 536 | OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP); |
| 537 | OUT_RING(MI_NOOP); |
| 538 | ADVANCE_LP_RING(); |
| 539 | } |
Zou Nan hai | 1cafd34 | 2010-06-25 13:40:24 +0800 | [diff] [blame] | 540 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 541 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 542 | i915_emit_breadcrumb(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 543 | return 0; |
| 544 | } |
| 545 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 546 | static int i915_dispatch_flip(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 547 | { |
| 548 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 549 | struct drm_i915_master_private *master_priv = |
| 550 | dev->primary->master->driver_priv; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 551 | int ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 552 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 553 | if (!master_priv->sarea_priv) |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 554 | return -EINVAL; |
| 555 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 556 | DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", |
yakui_zhao | be25ed9 | 2009-06-02 14:13:55 +0800 | [diff] [blame] | 557 | __func__, |
Daniel Vetter | 5d985ac | 2012-08-12 19:27:13 +0200 | [diff] [blame] | 558 | dev_priv->dri1.current_page, |
yakui_zhao | be25ed9 | 2009-06-02 14:13:55 +0800 | [diff] [blame] | 559 | master_priv->sarea_priv->pf_current_page); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 560 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 561 | i915_kernel_lost_context(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 562 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 563 | ret = BEGIN_LP_RING(10); |
| 564 | if (ret) |
| 565 | return ret; |
| 566 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 567 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 568 | OUT_RING(0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 569 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 570 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); |
| 571 | OUT_RING(0); |
Daniel Vetter | 5d985ac | 2012-08-12 19:27:13 +0200 | [diff] [blame] | 572 | if (dev_priv->dri1.current_page == 0) { |
| 573 | OUT_RING(dev_priv->dri1.back_offset); |
| 574 | dev_priv->dri1.current_page = 1; |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 575 | } else { |
Daniel Vetter | 5d985ac | 2012-08-12 19:27:13 +0200 | [diff] [blame] | 576 | OUT_RING(dev_priv->dri1.front_offset); |
| 577 | dev_priv->dri1.current_page = 0; |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 578 | } |
| 579 | OUT_RING(0); |
Jesse Barnes | ac741ab | 2008-04-22 16:03:07 +1000 | [diff] [blame] | 580 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 581 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); |
| 582 | OUT_RING(0); |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 583 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 584 | ADVANCE_LP_RING(); |
Jesse Barnes | ac741ab | 2008-04-22 16:03:07 +1000 | [diff] [blame] | 585 | |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 586 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++; |
Jesse Barnes | ac741ab | 2008-04-22 16:03:07 +1000 | [diff] [blame] | 587 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 588 | if (BEGIN_LP_RING(4) == 0) { |
| 589 | OUT_RING(MI_STORE_DWORD_INDEX); |
| 590 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 591 | OUT_RING(dev_priv->dri1.counter); |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 592 | OUT_RING(0); |
| 593 | ADVANCE_LP_RING(); |
| 594 | } |
Jesse Barnes | ac741ab | 2008-04-22 16:03:07 +1000 | [diff] [blame] | 595 | |
Daniel Vetter | 5d985ac | 2012-08-12 19:27:13 +0200 | [diff] [blame] | 596 | master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page; |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 597 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 598 | } |
| 599 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 600 | static int i915_quiescent(struct drm_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 601 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 602 | i915_kernel_lost_context(dev); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 603 | return intel_ring_idle(LP_RING(dev->dev_private)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 604 | } |
| 605 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 606 | static int i915_flush_ioctl(struct drm_device *dev, void *data, |
| 607 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 608 | { |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 609 | int ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 610 | |
Daniel Vetter | cd9d4e9 | 2012-04-24 08:29:42 +0200 | [diff] [blame] | 611 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 612 | return -ENODEV; |
| 613 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 614 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
| 615 | |
| 616 | mutex_lock(&dev->struct_mutex); |
| 617 | ret = i915_quiescent(dev); |
| 618 | mutex_unlock(&dev->struct_mutex); |
| 619 | |
| 620 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 621 | } |
| 622 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 623 | static int i915_batchbuffer(struct drm_device *dev, void *data, |
| 624 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 625 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 626 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 627 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 628 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 629 | master_priv->sarea_priv; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 630 | drm_i915_batchbuffer_t *batch = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 631 | int ret; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 632 | struct drm_clip_rect *cliprects = NULL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 633 | |
Daniel Vetter | cd9d4e9 | 2012-04-24 08:29:42 +0200 | [diff] [blame] | 634 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 635 | return -ENODEV; |
| 636 | |
Daniel Vetter | 8781342 | 2012-05-02 11:49:32 +0200 | [diff] [blame] | 637 | if (!dev_priv->dri1.allow_batchbuffer) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 638 | DRM_ERROR("Batchbuffer ioctl disabled\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 639 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 640 | } |
| 641 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 642 | DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", |
yakui_zhao | be25ed9 | 2009-06-02 14:13:55 +0800 | [diff] [blame] | 643 | batch->start, batch->used, batch->num_cliprects); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 644 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 645 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 646 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 647 | if (batch->num_cliprects < 0) |
| 648 | return -EINVAL; |
| 649 | |
| 650 | if (batch->num_cliprects) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 651 | cliprects = kcalloc(batch->num_cliprects, |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 652 | sizeof(*cliprects), |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 653 | GFP_KERNEL); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 654 | if (cliprects == NULL) |
| 655 | return -ENOMEM; |
| 656 | |
| 657 | ret = copy_from_user(cliprects, batch->cliprects, |
| 658 | batch->num_cliprects * |
| 659 | sizeof(struct drm_clip_rect)); |
Dan Carpenter | 9927a40 | 2010-06-19 15:12:51 +0200 | [diff] [blame] | 660 | if (ret != 0) { |
| 661 | ret = -EFAULT; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 662 | goto fail_free; |
Dan Carpenter | 9927a40 | 2010-06-19 15:12:51 +0200 | [diff] [blame] | 663 | } |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 664 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 665 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 666 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 667 | ret = i915_dispatch_batchbuffer(dev, batch, cliprects); |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 668 | mutex_unlock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 669 | |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 670 | if (sarea_priv) |
Keith Packard | 0baf823 | 2008-11-08 11:44:14 +1000 | [diff] [blame] | 671 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 672 | |
| 673 | fail_free: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 674 | kfree(cliprects); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 675 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 676 | return ret; |
| 677 | } |
| 678 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 679 | static int i915_cmdbuffer(struct drm_device *dev, void *data, |
| 680 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 681 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 682 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 683 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 684 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 685 | master_priv->sarea_priv; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 686 | drm_i915_cmdbuffer_t *cmdbuf = data; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 687 | struct drm_clip_rect *cliprects = NULL; |
| 688 | void *batch_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 689 | int ret; |
| 690 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 691 | DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", |
yakui_zhao | be25ed9 | 2009-06-02 14:13:55 +0800 | [diff] [blame] | 692 | cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 693 | |
Daniel Vetter | cd9d4e9 | 2012-04-24 08:29:42 +0200 | [diff] [blame] | 694 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 695 | return -ENODEV; |
| 696 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 697 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 698 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 699 | if (cmdbuf->num_cliprects < 0) |
| 700 | return -EINVAL; |
| 701 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 702 | batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 703 | if (batch_data == NULL) |
| 704 | return -ENOMEM; |
| 705 | |
| 706 | ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz); |
Dan Carpenter | 9927a40 | 2010-06-19 15:12:51 +0200 | [diff] [blame] | 707 | if (ret != 0) { |
| 708 | ret = -EFAULT; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 709 | goto fail_batch_free; |
Dan Carpenter | 9927a40 | 2010-06-19 15:12:51 +0200 | [diff] [blame] | 710 | } |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 711 | |
| 712 | if (cmdbuf->num_cliprects) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 713 | cliprects = kcalloc(cmdbuf->num_cliprects, |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 714 | sizeof(*cliprects), GFP_KERNEL); |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 715 | if (cliprects == NULL) { |
| 716 | ret = -ENOMEM; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 717 | goto fail_batch_free; |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 718 | } |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 719 | |
| 720 | ret = copy_from_user(cliprects, cmdbuf->cliprects, |
| 721 | cmdbuf->num_cliprects * |
| 722 | sizeof(struct drm_clip_rect)); |
Dan Carpenter | 9927a40 | 2010-06-19 15:12:51 +0200 | [diff] [blame] | 723 | if (ret != 0) { |
| 724 | ret = -EFAULT; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 725 | goto fail_clip_free; |
Dan Carpenter | 9927a40 | 2010-06-19 15:12:51 +0200 | [diff] [blame] | 726 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 727 | } |
| 728 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 729 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 730 | ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data); |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 731 | mutex_unlock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 732 | if (ret) { |
| 733 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); |
Chris Wright | 355d7f3 | 2009-04-17 01:18:55 +0000 | [diff] [blame] | 734 | goto fail_clip_free; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 735 | } |
| 736 | |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 737 | if (sarea_priv) |
Keith Packard | 0baf823 | 2008-11-08 11:44:14 +1000 | [diff] [blame] | 738 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 739 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 740 | fail_clip_free: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 741 | kfree(cliprects); |
Chris Wright | 355d7f3 | 2009-04-17 01:18:55 +0000 | [diff] [blame] | 742 | fail_batch_free: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 743 | kfree(batch_data); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 744 | |
| 745 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 746 | } |
| 747 | |
Daniel Vetter | 9488867 | 2012-04-26 23:28:08 +0200 | [diff] [blame] | 748 | static int i915_emit_irq(struct drm_device * dev) |
| 749 | { |
| 750 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 751 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
| 752 | |
| 753 | i915_kernel_lost_context(dev); |
| 754 | |
| 755 | DRM_DEBUG_DRIVER("\n"); |
| 756 | |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 757 | dev_priv->dri1.counter++; |
| 758 | if (dev_priv->dri1.counter > 0x7FFFFFFFUL) |
| 759 | dev_priv->dri1.counter = 1; |
Daniel Vetter | 9488867 | 2012-04-26 23:28:08 +0200 | [diff] [blame] | 760 | if (master_priv->sarea_priv) |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 761 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter; |
Daniel Vetter | 9488867 | 2012-04-26 23:28:08 +0200 | [diff] [blame] | 762 | |
| 763 | if (BEGIN_LP_RING(4) == 0) { |
| 764 | OUT_RING(MI_STORE_DWORD_INDEX); |
| 765 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 766 | OUT_RING(dev_priv->dri1.counter); |
Daniel Vetter | 9488867 | 2012-04-26 23:28:08 +0200 | [diff] [blame] | 767 | OUT_RING(MI_USER_INTERRUPT); |
| 768 | ADVANCE_LP_RING(); |
| 769 | } |
| 770 | |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 771 | return dev_priv->dri1.counter; |
Daniel Vetter | 9488867 | 2012-04-26 23:28:08 +0200 | [diff] [blame] | 772 | } |
| 773 | |
| 774 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
| 775 | { |
| 776 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 777 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
| 778 | int ret = 0; |
| 779 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
| 780 | |
| 781 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
| 782 | READ_BREADCRUMB(dev_priv)); |
| 783 | |
| 784 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
| 785 | if (master_priv->sarea_priv) |
| 786 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
| 787 | return 0; |
| 788 | } |
| 789 | |
| 790 | if (master_priv->sarea_priv) |
| 791 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
| 792 | |
| 793 | if (ring->irq_get(ring)) { |
| 794 | DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ, |
| 795 | READ_BREADCRUMB(dev_priv) >= irq_nr); |
| 796 | ring->irq_put(ring); |
| 797 | } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) |
| 798 | ret = -EBUSY; |
| 799 | |
| 800 | if (ret == -EBUSY) { |
| 801 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 802 | READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter); |
Daniel Vetter | 9488867 | 2012-04-26 23:28:08 +0200 | [diff] [blame] | 803 | } |
| 804 | |
| 805 | return ret; |
| 806 | } |
| 807 | |
| 808 | /* Needs the lock as it touches the ring. |
| 809 | */ |
| 810 | static int i915_irq_emit(struct drm_device *dev, void *data, |
| 811 | struct drm_file *file_priv) |
| 812 | { |
| 813 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 814 | drm_i915_irq_emit_t *emit = data; |
| 815 | int result; |
| 816 | |
| 817 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 818 | return -ENODEV; |
| 819 | |
| 820 | if (!dev_priv || !LP_RING(dev_priv)->virtual_start) { |
| 821 | DRM_ERROR("called with no initialization\n"); |
| 822 | return -EINVAL; |
| 823 | } |
| 824 | |
| 825 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
| 826 | |
| 827 | mutex_lock(&dev->struct_mutex); |
| 828 | result = i915_emit_irq(dev); |
| 829 | mutex_unlock(&dev->struct_mutex); |
| 830 | |
| 831 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
| 832 | DRM_ERROR("copy_to_user\n"); |
| 833 | return -EFAULT; |
| 834 | } |
| 835 | |
| 836 | return 0; |
| 837 | } |
| 838 | |
| 839 | /* Doesn't need the hardware lock. |
| 840 | */ |
| 841 | static int i915_irq_wait(struct drm_device *dev, void *data, |
| 842 | struct drm_file *file_priv) |
| 843 | { |
| 844 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 845 | drm_i915_irq_wait_t *irqwait = data; |
| 846 | |
| 847 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 848 | return -ENODEV; |
| 849 | |
| 850 | if (!dev_priv) { |
| 851 | DRM_ERROR("called with no initialization\n"); |
| 852 | return -EINVAL; |
| 853 | } |
| 854 | |
| 855 | return i915_wait_irq(dev, irqwait->irq_seq); |
| 856 | } |
| 857 | |
Daniel Vetter | d1c1edb | 2012-04-26 23:28:01 +0200 | [diff] [blame] | 858 | static int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
| 859 | struct drm_file *file_priv) |
| 860 | { |
| 861 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 862 | drm_i915_vblank_pipe_t *pipe = data; |
| 863 | |
| 864 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 865 | return -ENODEV; |
| 866 | |
| 867 | if (!dev_priv) { |
| 868 | DRM_ERROR("called with no initialization\n"); |
| 869 | return -EINVAL; |
| 870 | } |
| 871 | |
| 872 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
| 873 | |
| 874 | return 0; |
| 875 | } |
| 876 | |
| 877 | /** |
| 878 | * Schedule buffer swap at given vertical blank. |
| 879 | */ |
| 880 | static int i915_vblank_swap(struct drm_device *dev, void *data, |
| 881 | struct drm_file *file_priv) |
| 882 | { |
| 883 | /* The delayed swap mechanism was fundamentally racy, and has been |
| 884 | * removed. The model was that the client requested a delayed flip/swap |
| 885 | * from the kernel, then waited for vblank before continuing to perform |
| 886 | * rendering. The problem was that the kernel might wake the client |
| 887 | * up before it dispatched the vblank swap (since the lock has to be |
| 888 | * held while touching the ringbuffer), in which case the client would |
| 889 | * clear and start the next frame before the swap occurred, and |
| 890 | * flicker would occur in addition to likely missing the vblank. |
| 891 | * |
| 892 | * In the absence of this ioctl, userland falls back to a correct path |
| 893 | * of waiting for a vblank, then dispatching the swap on its own. |
| 894 | * Context switching to userland and back is plenty fast enough for |
| 895 | * meeting the requirements of vblank swapping. |
| 896 | */ |
| 897 | return -EINVAL; |
| 898 | } |
| 899 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 900 | static int i915_flip_bufs(struct drm_device *dev, void *data, |
| 901 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 902 | { |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 903 | int ret; |
| 904 | |
Daniel Vetter | cd9d4e9 | 2012-04-24 08:29:42 +0200 | [diff] [blame] | 905 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 906 | return -ENODEV; |
| 907 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 908 | DRM_DEBUG_DRIVER("%s\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 909 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 910 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 911 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 912 | mutex_lock(&dev->struct_mutex); |
| 913 | ret = i915_dispatch_flip(dev); |
| 914 | mutex_unlock(&dev->struct_mutex); |
| 915 | |
| 916 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 917 | } |
| 918 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 919 | static int i915_getparam(struct drm_device *dev, void *data, |
| 920 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 921 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 922 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 923 | drm_i915_getparam_t *param = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 924 | int value; |
| 925 | |
| 926 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 927 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 928 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 929 | } |
| 930 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 931 | switch (param->param) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 932 | case I915_PARAM_IRQ_ACTIVE: |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 933 | value = dev->pdev->irq ? 1 : 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 934 | break; |
| 935 | case I915_PARAM_ALLOW_BATCHBUFFER: |
Daniel Vetter | 8781342 | 2012-05-02 11:49:32 +0200 | [diff] [blame] | 936 | value = dev_priv->dri1.allow_batchbuffer ? 1 : 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 937 | break; |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 938 | case I915_PARAM_LAST_DISPATCH: |
| 939 | value = READ_BREADCRUMB(dev_priv); |
| 940 | break; |
Kristian Høgsberg | ed4c9c4 | 2008-08-20 11:08:52 -0400 | [diff] [blame] | 941 | case I915_PARAM_CHIPSET_ID: |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 942 | value = dev->pdev->device; |
Kristian Høgsberg | ed4c9c4 | 2008-08-20 11:08:52 -0400 | [diff] [blame] | 943 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 944 | case I915_PARAM_HAS_GEM: |
Daniel Vetter | 2e895b1 | 2012-04-23 16:50:51 +0200 | [diff] [blame] | 945 | value = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 946 | break; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 947 | case I915_PARAM_NUM_FENCES_AVAIL: |
| 948 | value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; |
| 949 | break; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 950 | case I915_PARAM_HAS_OVERLAY: |
| 951 | value = dev_priv->overlay ? 1 : 0; |
| 952 | break; |
Jesse Barnes | e9560f7 | 2009-11-19 10:49:07 -0800 | [diff] [blame] | 953 | case I915_PARAM_HAS_PAGEFLIPPING: |
| 954 | value = 1; |
| 955 | break; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 956 | case I915_PARAM_HAS_EXECBUF2: |
| 957 | /* depends on GEM */ |
Daniel Vetter | 2e895b1 | 2012-04-23 16:50:51 +0200 | [diff] [blame] | 958 | value = 1; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 959 | break; |
Zou Nan hai | e3a815f | 2010-05-31 13:58:47 +0800 | [diff] [blame] | 960 | case I915_PARAM_HAS_BSD: |
Chris Wilson | edc912f | 2012-05-11 14:29:32 +0100 | [diff] [blame] | 961 | value = intel_ring_initialized(&dev_priv->ring[VCS]); |
Zou Nan hai | e3a815f | 2010-05-31 13:58:47 +0800 | [diff] [blame] | 962 | break; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 963 | case I915_PARAM_HAS_BLT: |
Chris Wilson | edc912f | 2012-05-11 14:29:32 +0100 | [diff] [blame] | 964 | value = intel_ring_initialized(&dev_priv->ring[BCS]); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 965 | break; |
Xiang, Haihao | a1f2cc7 | 2013-05-28 19:22:34 -0700 | [diff] [blame] | 966 | case I915_PARAM_HAS_VEBOX: |
| 967 | value = intel_ring_initialized(&dev_priv->ring[VECS]); |
| 968 | break; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 969 | case I915_PARAM_HAS_RELAXED_FENCING: |
| 970 | value = 1; |
| 971 | break; |
Daniel Vetter | bbf0c6b | 2010-12-05 11:30:40 +0100 | [diff] [blame] | 972 | case I915_PARAM_HAS_COHERENT_RINGS: |
| 973 | value = 1; |
| 974 | break; |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 975 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
| 976 | value = INTEL_INFO(dev)->gen >= 4; |
| 977 | break; |
Chris Wilson | 271d81b | 2011-03-01 15:24:41 +0000 | [diff] [blame] | 978 | case I915_PARAM_HAS_RELAXED_DELTA: |
| 979 | value = 1; |
| 980 | break; |
Eric Anholt | ae662d3 | 2012-01-03 09:23:29 -0800 | [diff] [blame] | 981 | case I915_PARAM_HAS_GEN7_SOL_RESET: |
| 982 | value = 1; |
| 983 | break; |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 984 | case I915_PARAM_HAS_LLC: |
| 985 | value = HAS_LLC(dev); |
| 986 | break; |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 987 | case I915_PARAM_HAS_WT: |
| 988 | value = HAS_WT(dev); |
| 989 | break; |
Daniel Vetter | 777ee96 | 2012-02-15 23:50:25 +0100 | [diff] [blame] | 990 | case I915_PARAM_HAS_ALIASING_PPGTT: |
| 991 | value = dev_priv->mm.aliasing_ppgtt ? 1 : 0; |
| 992 | break; |
Ben Widawsky | 172cf15 | 2012-06-05 15:24:25 -0700 | [diff] [blame] | 993 | case I915_PARAM_HAS_WAIT_TIMEOUT: |
| 994 | value = 1; |
| 995 | break; |
Chris Wilson | 2fedbff | 2012-08-08 10:23:22 +0100 | [diff] [blame] | 996 | case I915_PARAM_HAS_SEMAPHORES: |
| 997 | value = i915_semaphore_is_enabled(dev); |
| 998 | break; |
Dave Airlie | ec6f1bb | 2012-08-16 10:15:34 +1000 | [diff] [blame] | 999 | case I915_PARAM_HAS_PRIME_VMAP_FLUSH: |
| 1000 | value = 1; |
| 1001 | break; |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1002 | case I915_PARAM_HAS_SECURE_BATCHES: |
| 1003 | value = capable(CAP_SYS_ADMIN); |
| 1004 | break; |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1005 | case I915_PARAM_HAS_PINNED_BATCHES: |
| 1006 | value = 1; |
| 1007 | break; |
Daniel Vetter | ed5982e | 2013-01-17 22:23:36 +0100 | [diff] [blame] | 1008 | case I915_PARAM_HAS_EXEC_NO_RELOC: |
| 1009 | value = 1; |
| 1010 | break; |
Chris Wilson | eef90cc | 2013-01-08 10:53:17 +0000 | [diff] [blame] | 1011 | case I915_PARAM_HAS_EXEC_HANDLE_LUT: |
| 1012 | value = 1; |
| 1013 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1014 | default: |
Ben Widawsky | e29c32d | 2013-05-31 11:28:45 -0700 | [diff] [blame] | 1015 | DRM_DEBUG("Unknown parameter %d\n", param->param); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1016 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1017 | } |
| 1018 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1019 | if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1020 | DRM_ERROR("DRM_COPY_TO_USER failed\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1021 | return -EFAULT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1022 | } |
| 1023 | |
| 1024 | return 0; |
| 1025 | } |
| 1026 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1027 | static int i915_setparam(struct drm_device *dev, void *data, |
| 1028 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1029 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1030 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1031 | drm_i915_setparam_t *param = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1032 | |
| 1033 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1034 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1035 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1036 | } |
| 1037 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1038 | switch (param->param) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1039 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1040 | break; |
| 1041 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1042 | break; |
| 1043 | case I915_SETPARAM_ALLOW_BATCHBUFFER: |
Daniel Vetter | 8781342 | 2012-05-02 11:49:32 +0200 | [diff] [blame] | 1044 | dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1045 | break; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1046 | case I915_SETPARAM_NUM_USED_FENCES: |
| 1047 | if (param->value > dev_priv->num_fence_regs || |
| 1048 | param->value < 0) |
| 1049 | return -EINVAL; |
| 1050 | /* Userspace can use first N regs */ |
| 1051 | dev_priv->fence_reg_start = param->value; |
| 1052 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1053 | default: |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 1054 | DRM_DEBUG_DRIVER("unknown parameter %d\n", |
yakui_zhao | be25ed9 | 2009-06-02 14:13:55 +0800 | [diff] [blame] | 1055 | param->param); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1056 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1057 | } |
| 1058 | |
| 1059 | return 0; |
| 1060 | } |
| 1061 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1062 | static int i915_set_status_page(struct drm_device *dev, void *data, |
| 1063 | struct drm_file *file_priv) |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1064 | { |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1065 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1066 | drm_i915_hws_addr_t *hws = data; |
Mika Kuoppala | 4f1ba0f | 2012-11-12 14:20:19 +0200 | [diff] [blame] | 1067 | struct intel_ring_buffer *ring; |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1068 | |
Daniel Vetter | cd9d4e9 | 2012-04-24 08:29:42 +0200 | [diff] [blame] | 1069 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 1070 | return -ENODEV; |
| 1071 | |
Zhenyu Wang | b39d50e | 2008-02-19 20:59:09 +1000 | [diff] [blame] | 1072 | if (!I915_NEED_GFX_HWS(dev)) |
| 1073 | return -EINVAL; |
| 1074 | |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1075 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1076 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1077 | return -EINVAL; |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1078 | } |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1079 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1080 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 1081 | WARN(1, "tried to set status page when mode setting active\n"); |
| 1082 | return 0; |
| 1083 | } |
| 1084 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 1085 | DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1086 | |
Mika Kuoppala | 4f1ba0f | 2012-11-12 14:20:19 +0200 | [diff] [blame] | 1087 | ring = LP_RING(dev_priv); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1088 | ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12); |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1089 | |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1090 | dev_priv->dri1.gfx_hws_cpu_addr = |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 1091 | ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096); |
Daniel Vetter | 316d388 | 2012-04-26 23:28:15 +0200 | [diff] [blame] | 1092 | if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) { |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1093 | i915_dma_cleanup(dev); |
Eric Anholt | e20f9c6 | 2010-05-26 14:51:06 -0700 | [diff] [blame] | 1094 | ring->status_page.gfx_addr = 0; |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1095 | DRM_ERROR("can not ioremap virtual address for" |
| 1096 | " G33 hw status page\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1097 | return -ENOMEM; |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1098 | } |
Daniel Vetter | 316d388 | 2012-04-26 23:28:15 +0200 | [diff] [blame] | 1099 | |
| 1100 | memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1101 | I915_WRITE(HWS_PGA, ring->status_page.gfx_addr); |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1102 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 1103 | DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", |
Eric Anholt | e20f9c6 | 2010-05-26 14:51:06 -0700 | [diff] [blame] | 1104 | ring->status_page.gfx_addr); |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 1105 | DRM_DEBUG_DRIVER("load hws at %p\n", |
Eric Anholt | e20f9c6 | 2010-05-26 14:51:06 -0700 | [diff] [blame] | 1106 | ring->status_page.page_addr); |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1107 | return 0; |
| 1108 | } |
| 1109 | |
Dave Airlie | ec2a4c3 | 2009-08-04 11:43:41 +1000 | [diff] [blame] | 1110 | static int i915_get_bridge_dev(struct drm_device *dev) |
| 1111 | { |
| 1112 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1113 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1114 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
Dave Airlie | ec2a4c3 | 2009-08-04 11:43:41 +1000 | [diff] [blame] | 1115 | if (!dev_priv->bridge_dev) { |
| 1116 | DRM_ERROR("bridge device not found\n"); |
| 1117 | return -1; |
| 1118 | } |
| 1119 | return 0; |
| 1120 | } |
| 1121 | |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1122 | #define MCHBAR_I915 0x44 |
| 1123 | #define MCHBAR_I965 0x48 |
| 1124 | #define MCHBAR_SIZE (4*4096) |
| 1125 | |
| 1126 | #define DEVEN_REG 0x54 |
| 1127 | #define DEVEN_MCHBAR_EN (1 << 28) |
| 1128 | |
| 1129 | /* Allocate space for the MCH regs if needed, return nonzero on error */ |
| 1130 | static int |
| 1131 | intel_alloc_mchbar_resource(struct drm_device *dev) |
| 1132 | { |
| 1133 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1134 | int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1135 | u32 temp_lo, temp_hi = 0; |
| 1136 | u64 mchbar_addr; |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 1137 | int ret; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1138 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1139 | if (INTEL_INFO(dev)->gen >= 4) |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1140 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
| 1141 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); |
| 1142 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; |
| 1143 | |
| 1144 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ |
| 1145 | #ifdef CONFIG_PNP |
| 1146 | if (mchbar_addr && |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 1147 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) |
| 1148 | return 0; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1149 | #endif |
| 1150 | |
| 1151 | /* Get some space for it */ |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 1152 | dev_priv->mch_res.name = "i915 MCHBAR"; |
| 1153 | dev_priv->mch_res.flags = IORESOURCE_MEM; |
| 1154 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, |
| 1155 | &dev_priv->mch_res, |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1156 | MCHBAR_SIZE, MCHBAR_SIZE, |
| 1157 | PCIBIOS_MIN_MEM, |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 1158 | 0, pcibios_align_resource, |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1159 | dev_priv->bridge_dev); |
| 1160 | if (ret) { |
| 1161 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); |
| 1162 | dev_priv->mch_res.start = 0; |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 1163 | return ret; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1164 | } |
| 1165 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1166 | if (INTEL_INFO(dev)->gen >= 4) |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1167 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
| 1168 | upper_32_bits(dev_priv->mch_res.start)); |
| 1169 | |
| 1170 | pci_write_config_dword(dev_priv->bridge_dev, reg, |
| 1171 | lower_32_bits(dev_priv->mch_res.start)); |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 1172 | return 0; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1173 | } |
| 1174 | |
| 1175 | /* Setup MCHBAR if possible, return true if we should disable it again */ |
| 1176 | static void |
| 1177 | intel_setup_mchbar(struct drm_device *dev) |
| 1178 | { |
| 1179 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1180 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1181 | u32 temp; |
| 1182 | bool enabled; |
| 1183 | |
| 1184 | dev_priv->mchbar_need_disable = false; |
| 1185 | |
| 1186 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
| 1187 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); |
| 1188 | enabled = !!(temp & DEVEN_MCHBAR_EN); |
| 1189 | } else { |
| 1190 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); |
| 1191 | enabled = temp & 1; |
| 1192 | } |
| 1193 | |
| 1194 | /* If it's already enabled, don't have to do anything */ |
| 1195 | if (enabled) |
| 1196 | return; |
| 1197 | |
| 1198 | if (intel_alloc_mchbar_resource(dev)) |
| 1199 | return; |
| 1200 | |
| 1201 | dev_priv->mchbar_need_disable = true; |
| 1202 | |
| 1203 | /* Space is allocated or reserved, so enable it. */ |
| 1204 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
| 1205 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, |
| 1206 | temp | DEVEN_MCHBAR_EN); |
| 1207 | } else { |
| 1208 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); |
| 1209 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); |
| 1210 | } |
| 1211 | } |
| 1212 | |
| 1213 | static void |
| 1214 | intel_teardown_mchbar(struct drm_device *dev) |
| 1215 | { |
| 1216 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1217 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1218 | u32 temp; |
| 1219 | |
| 1220 | if (dev_priv->mchbar_need_disable) { |
| 1221 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
| 1222 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); |
| 1223 | temp &= ~DEVEN_MCHBAR_EN; |
| 1224 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); |
| 1225 | } else { |
| 1226 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); |
| 1227 | temp &= ~1; |
| 1228 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); |
| 1229 | } |
| 1230 | } |
| 1231 | |
| 1232 | if (dev_priv->mch_res.start) |
| 1233 | release_resource(&dev_priv->mch_res); |
| 1234 | } |
| 1235 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1236 | /* true = enable decode, false = disable decoder */ |
| 1237 | static unsigned int i915_vga_set_decode(void *cookie, bool state) |
| 1238 | { |
| 1239 | struct drm_device *dev = cookie; |
| 1240 | |
| 1241 | intel_modeset_vga_set_state(dev, state); |
| 1242 | if (state) |
| 1243 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | |
| 1244 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
| 1245 | else |
| 1246 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
| 1247 | } |
| 1248 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1249 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
| 1250 | { |
| 1251 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 1252 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; |
| 1253 | if (state == VGA_SWITCHEROO_ON) { |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1254 | pr_info("switched on\n"); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 1255 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1256 | /* i915 resume handler doesn't set to D0 */ |
| 1257 | pci_set_power_state(dev->pdev, PCI_D0); |
| 1258 | i915_resume(dev); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 1259 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1260 | } else { |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1261 | pr_err("switched off\n"); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 1262 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1263 | i915_suspend(dev, pmm); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 1264 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1265 | } |
| 1266 | } |
| 1267 | |
| 1268 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) |
| 1269 | { |
| 1270 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 1271 | bool can_switch; |
| 1272 | |
| 1273 | spin_lock(&dev->count_lock); |
| 1274 | can_switch = (dev->open_count == 0); |
| 1275 | spin_unlock(&dev->count_lock); |
| 1276 | return can_switch; |
| 1277 | } |
| 1278 | |
Takashi Iwai | 26ec685 | 2012-05-11 07:51:17 +0200 | [diff] [blame] | 1279 | static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { |
| 1280 | .set_gpu_state = i915_switcheroo_set_state, |
| 1281 | .reprobe = NULL, |
| 1282 | .can_switch = i915_switcheroo_can_switch, |
| 1283 | }; |
| 1284 | |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 1285 | static int i915_load_modeset_init(struct drm_device *dev) |
| 1286 | { |
| 1287 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1288 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1289 | |
Bryan Freed | 6d139a8 | 2010-10-14 09:14:51 +0100 | [diff] [blame] | 1290 | ret = intel_parse_bios(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1291 | if (ret) |
| 1292 | DRM_INFO("failed to find VBIOS tables\n"); |
| 1293 | |
Chris Wilson | 934f992 | 2011-01-20 13:09:12 +0000 | [diff] [blame] | 1294 | /* If we have > 1 VGA cards, then we need to arbitrate access |
| 1295 | * to the common VGA resources. |
| 1296 | * |
| 1297 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), |
| 1298 | * then we do not take part in VGA arbitration and the |
| 1299 | * vga_client_register() fails with -ENODEV. |
| 1300 | */ |
Dave Airlie | ebff5fa9 | 2013-10-11 15:12:04 +1000 | [diff] [blame] | 1301 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); |
| 1302 | if (ret && ret != -ENODEV) |
| 1303 | goto out; |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1304 | |
Jesse Barnes | 723bfd7 | 2010-10-07 16:01:13 -0700 | [diff] [blame] | 1305 | intel_register_dsm_handler(); |
| 1306 | |
Dave Airlie | 0d69704 | 2012-09-10 12:28:36 +1000 | [diff] [blame] | 1307 | ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1308 | if (ret) |
Chris Wilson | 5a79395 | 2010-06-06 10:50:03 +0100 | [diff] [blame] | 1309 | goto cleanup_vga_client; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1310 | |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 1311 | /* Initialise stolen first so that we may reserve preallocated |
| 1312 | * objects for the BIOS to KMS transition. |
| 1313 | */ |
| 1314 | ret = i915_gem_init_stolen(dev); |
| 1315 | if (ret) |
| 1316 | goto cleanup_vga_switcheroo; |
| 1317 | |
Daniel Vetter | 52d7ece | 2012-12-01 21:03:22 +0100 | [diff] [blame] | 1318 | ret = drm_irq_install(dev); |
| 1319 | if (ret) |
| 1320 | goto cleanup_gem_stolen; |
| 1321 | |
Imre Deak | ddb642f | 2013-10-28 17:20:35 +0200 | [diff] [blame] | 1322 | intel_power_domains_init_hw(dev); |
Ville Syrjälä | a148532 | 2013-09-16 17:38:34 +0300 | [diff] [blame] | 1323 | |
Daniel Vetter | 52d7ece | 2012-12-01 21:03:22 +0100 | [diff] [blame] | 1324 | /* Important: The output setup functions called by modeset_init need |
| 1325 | * working irqs for e.g. gmbus and dp aux transfers. */ |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 1326 | intel_modeset_init(dev); |
| 1327 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 1328 | ret = i915_gem_init(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1329 | if (ret) |
Ville Syrjälä | a148532 | 2013-09-16 17:38:34 +0300 | [diff] [blame] | 1330 | goto cleanup_power; |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 1331 | |
Jesse Barnes | 073f34d | 2012-11-02 11:13:59 -0700 | [diff] [blame] | 1332 | INIT_WORK(&dev_priv->console_resume_work, intel_console_resume); |
| 1333 | |
Daniel Vetter | 52d7ece | 2012-12-01 21:03:22 +0100 | [diff] [blame] | 1334 | intel_modeset_gem_init(dev); |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 1335 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1336 | /* Always safe in the mode setting case. */ |
| 1337 | /* FIXME: do pre/post-mode set stuff in core KMS code */ |
Ville Syrjälä | ba0bf12 | 2013-10-04 14:53:33 +0300 | [diff] [blame] | 1338 | dev->vblank_disable_allowed = true; |
Ville Syrjälä | ce35255 | 2013-09-20 10:14:23 +0300 | [diff] [blame] | 1339 | if (INTEL_INFO(dev)->num_pipes == 0) { |
| 1340 | intel_display_power_put(dev, POWER_DOMAIN_VGA); |
Ben Widawsky | e3c7475 | 2013-04-05 13:12:39 -0700 | [diff] [blame] | 1341 | return 0; |
Ville Syrjälä | ce35255 | 2013-09-20 10:14:23 +0300 | [diff] [blame] | 1342 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1343 | |
Chris Wilson | 5a79395 | 2010-06-06 10:50:03 +0100 | [diff] [blame] | 1344 | ret = intel_fbdev_init(dev); |
| 1345 | if (ret) |
Daniel Vetter | 52d7ece | 2012-12-01 21:03:22 +0100 | [diff] [blame] | 1346 | goto cleanup_gem; |
| 1347 | |
| 1348 | /* Only enable hotplug handling once the fbdev is fully set up. */ |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 1349 | intel_hpd_init(dev); |
| 1350 | |
| 1351 | /* |
| 1352 | * Some ports require correctly set-up hpd registers for detection to |
| 1353 | * work properly (leading to ghost connected connector status), e.g. VGA |
| 1354 | * on gm45. Hence we can only set up the initial fbdev config after hpd |
| 1355 | * irqs are fully enabled. Now we should scan for the initial config |
| 1356 | * only once hotplug handling is enabled, but due to screwed-up locking |
| 1357 | * around kms/fbdev init we can't protect the fdbev initial config |
| 1358 | * scanning against hotplug events. Hence do this first and ignore the |
| 1359 | * tiny window where we will loose hotplug notifactions. |
| 1360 | */ |
| 1361 | intel_fbdev_initial_config(dev); |
| 1362 | |
| 1363 | /* Only enable hotplug handling once the fbdev is fully set up. */ |
Daniel Vetter | 52d7ece | 2012-12-01 21:03:22 +0100 | [diff] [blame] | 1364 | dev_priv->enable_hotplug_processing = true; |
Chris Wilson | 5a79395 | 2010-06-06 10:50:03 +0100 | [diff] [blame] | 1365 | |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 1366 | drm_kms_helper_poll_init(dev); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 1367 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1368 | return 0; |
| 1369 | |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 1370 | cleanup_gem: |
| 1371 | mutex_lock(&dev->struct_mutex); |
| 1372 | i915_gem_cleanup_ringbuffer(dev); |
Ben Widawsky | 55d2328 | 2013-05-25 12:26:39 -0700 | [diff] [blame] | 1373 | i915_gem_context_fini(dev); |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 1374 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1375 | i915_gem_cleanup_aliasing_ppgtt(dev); |
Ben Widawsky | 93bd864 | 2013-07-16 16:50:06 -0700 | [diff] [blame] | 1376 | drm_mm_takedown(&dev_priv->gtt.base.mm); |
Ville Syrjälä | a148532 | 2013-09-16 17:38:34 +0300 | [diff] [blame] | 1377 | cleanup_power: |
| 1378 | intel_display_power_put(dev, POWER_DOMAIN_VGA); |
Daniel Vetter | 52d7ece | 2012-12-01 21:03:22 +0100 | [diff] [blame] | 1379 | drm_irq_uninstall(dev); |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 1380 | cleanup_gem_stolen: |
| 1381 | i915_gem_cleanup_stolen(dev); |
Chris Wilson | 5a79395 | 2010-06-06 10:50:03 +0100 | [diff] [blame] | 1382 | cleanup_vga_switcheroo: |
| 1383 | vga_switcheroo_unregister_client(dev->pdev); |
| 1384 | cleanup_vga_client: |
| 1385 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1386 | out: |
| 1387 | return ret; |
| 1388 | } |
| 1389 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1390 | int i915_master_create(struct drm_device *dev, struct drm_master *master) |
| 1391 | { |
| 1392 | struct drm_i915_master_private *master_priv; |
| 1393 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1394 | master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1395 | if (!master_priv) |
| 1396 | return -ENOMEM; |
| 1397 | |
| 1398 | master->driver_priv = master_priv; |
| 1399 | return 0; |
| 1400 | } |
| 1401 | |
| 1402 | void i915_master_destroy(struct drm_device *dev, struct drm_master *master) |
| 1403 | { |
| 1404 | struct drm_i915_master_private *master_priv = master->driver_priv; |
| 1405 | |
| 1406 | if (!master_priv) |
| 1407 | return; |
| 1408 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1409 | kfree(master_priv); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1410 | |
| 1411 | master->driver_priv = NULL; |
| 1412 | } |
| 1413 | |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1414 | #ifdef CONFIG_DRM_I915_FBDEV |
Daniel Vetter | e188719 | 2012-06-12 11:28:17 +0200 | [diff] [blame] | 1415 | static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
| 1416 | { |
| 1417 | struct apertures_struct *ap; |
| 1418 | struct pci_dev *pdev = dev_priv->dev->pdev; |
| 1419 | bool primary; |
| 1420 | |
| 1421 | ap = alloc_apertures(1); |
| 1422 | if (!ap) |
| 1423 | return; |
| 1424 | |
Ben Widawsky | dabb7a9 | 2013-01-17 12:45:16 -0800 | [diff] [blame] | 1425 | ap->ranges[0].base = dev_priv->gtt.mappable_base; |
Ben Widawsky | f64e292 | 2013-05-25 12:26:36 -0700 | [diff] [blame] | 1426 | ap->ranges[0].size = dev_priv->gtt.mappable_end; |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 1427 | |
Daniel Vetter | e188719 | 2012-06-12 11:28:17 +0200 | [diff] [blame] | 1428 | primary = |
| 1429 | pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; |
| 1430 | |
| 1431 | remove_conflicting_framebuffers(ap, "inteldrmfb", primary); |
| 1432 | |
| 1433 | kfree(ap); |
| 1434 | } |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1435 | #else |
| 1436 | static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
| 1437 | { |
| 1438 | } |
| 1439 | #endif |
Daniel Vetter | e188719 | 2012-06-12 11:28:17 +0200 | [diff] [blame] | 1440 | |
Daniel Vetter | c96ea64 | 2012-08-08 22:01:51 +0200 | [diff] [blame] | 1441 | static void i915_dump_device_info(struct drm_i915_private *dev_priv) |
| 1442 | { |
| 1443 | const struct intel_device_info *info = dev_priv->info; |
| 1444 | |
Damien Lespiau | e2a5800 | 2013-04-23 16:38:34 +0100 | [diff] [blame] | 1445 | #define PRINT_S(name) "%s" |
| 1446 | #define SEP_EMPTY |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 1447 | #define PRINT_FLAG(name) info->name ? #name "," : "" |
| 1448 | #define SEP_COMMA , |
Daniel Vetter | c96ea64 | 2012-08-08 22:01:51 +0200 | [diff] [blame] | 1449 | DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags=" |
Damien Lespiau | e2a5800 | 2013-04-23 16:38:34 +0100 | [diff] [blame] | 1450 | DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY), |
Daniel Vetter | c96ea64 | 2012-08-08 22:01:51 +0200 | [diff] [blame] | 1451 | info->gen, |
| 1452 | dev_priv->dev->pdev->device, |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 1453 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA)); |
Damien Lespiau | e2a5800 | 2013-04-23 16:38:34 +0100 | [diff] [blame] | 1454 | #undef PRINT_S |
| 1455 | #undef SEP_EMPTY |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 1456 | #undef PRINT_FLAG |
| 1457 | #undef SEP_COMMA |
Daniel Vetter | c96ea64 | 2012-08-08 22:01:51 +0200 | [diff] [blame] | 1458 | } |
| 1459 | |
Eric Anholt | 63ee41d | 2010-12-20 18:40:06 -0800 | [diff] [blame] | 1460 | /** |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1461 | * i915_driver_load - setup chip and create an initial config |
| 1462 | * @dev: DRM device |
| 1463 | * @flags: startup flags |
| 1464 | * |
| 1465 | * The driver load routine has to do several things: |
| 1466 | * - drive output discovery via intel_modeset_init() |
| 1467 | * - initialize the memory manager |
| 1468 | * - allocate initial config memory |
| 1469 | * - setup the DRM framebuffer with the allocated memory |
| 1470 | */ |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1471 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 1472 | { |
Luca Tettamanti | ea059a1 | 2010-04-08 21:41:59 +0200 | [diff] [blame] | 1473 | struct drm_i915_private *dev_priv; |
Daniel Vetter | 26394d9 | 2012-03-26 21:33:18 +0200 | [diff] [blame] | 1474 | struct intel_device_info *info; |
Chris Wilson | 934d608 | 2012-09-14 11:57:46 +0100 | [diff] [blame] | 1475 | int ret = 0, mmio_bar, mmio_size; |
Daniel Vetter | 9021f28 | 2012-03-26 09:45:41 +0200 | [diff] [blame] | 1476 | uint32_t aperture_size; |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1477 | |
Daniel Vetter | 26394d9 | 2012-03-26 21:33:18 +0200 | [diff] [blame] | 1478 | info = (struct intel_device_info *) flags; |
| 1479 | |
| 1480 | /* Refuse to load on gen6+ without kms enabled. */ |
Jani Nikula | e147acc | 2013-10-10 15:25:37 +0300 | [diff] [blame] | 1481 | if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 1482 | DRM_INFO("Your hardware requires kernel modesetting (KMS)\n"); |
| 1483 | DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n"); |
Daniel Vetter | 26394d9 | 2012-03-26 21:33:18 +0200 | [diff] [blame] | 1484 | return -ENODEV; |
Jani Nikula | e147acc | 2013-10-10 15:25:37 +0300 | [diff] [blame] | 1485 | } |
Daniel Vetter | 26394d9 | 2012-03-26 21:33:18 +0200 | [diff] [blame] | 1486 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 1487 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1488 | if (dev_priv == NULL) |
| 1489 | return -ENOMEM; |
| 1490 | |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1491 | dev->dev_private = (void *)dev_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1492 | dev_priv->dev = dev; |
Daniel Vetter | 26394d9 | 2012-03-26 21:33:18 +0200 | [diff] [blame] | 1493 | dev_priv->info = info; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1494 | |
Konstantin Khlebnikov | 7dcd267 | 2013-07-17 10:22:58 +0400 | [diff] [blame] | 1495 | spin_lock_init(&dev_priv->irq_lock); |
| 1496 | spin_lock_init(&dev_priv->gpu_error.lock); |
Konstantin Khlebnikov | 7dcd267 | 2013-07-17 10:22:58 +0400 | [diff] [blame] | 1497 | spin_lock_init(&dev_priv->backlight.lock); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1498 | spin_lock_init(&dev_priv->uncore.lock); |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 1499 | spin_lock_init(&dev_priv->mm.object_stat_lock); |
Konstantin Khlebnikov | 7dcd267 | 2013-07-17 10:22:58 +0400 | [diff] [blame] | 1500 | mutex_init(&dev_priv->dpio_lock); |
Konstantin Khlebnikov | 7dcd267 | 2013-07-17 10:22:58 +0400 | [diff] [blame] | 1501 | mutex_init(&dev_priv->modeset_restore_lock); |
| 1502 | |
Daniel Vetter | f742a55 | 2013-12-06 10:17:53 +0100 | [diff] [blame] | 1503 | intel_pm_setup(dev); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1504 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 1505 | intel_display_crc_init(dev); |
| 1506 | |
Daniel Vetter | c96ea64 | 2012-08-08 22:01:51 +0200 | [diff] [blame] | 1507 | i915_dump_device_info(dev_priv); |
| 1508 | |
Paulo Zanoni | ed1c9e2 | 2013-08-12 14:34:08 -0300 | [diff] [blame] | 1509 | /* Not all pre-production machines fall into this category, only the |
| 1510 | * very first ones. Almost everything should work, except for maybe |
| 1511 | * suspend/resume. And we don't implement workarounds that affect only |
| 1512 | * pre-production machines. */ |
| 1513 | if (IS_HSW_EARLY_SDV(dev)) |
| 1514 | DRM_INFO("This is an early pre-production Haswell machine. " |
| 1515 | "It may not be fully functional.\n"); |
| 1516 | |
Dave Airlie | ec2a4c3 | 2009-08-04 11:43:41 +1000 | [diff] [blame] | 1517 | if (i915_get_bridge_dev(dev)) { |
| 1518 | ret = -EIO; |
| 1519 | goto free_priv; |
| 1520 | } |
| 1521 | |
Ben Widawsky | 1e1bd0f | 2013-04-08 18:43:49 -0700 | [diff] [blame] | 1522 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
| 1523 | /* Before gen4, the registers and the GTT are behind different BARs. |
| 1524 | * However, from gen4 onwards, the registers and the GTT are shared |
| 1525 | * in the same BAR, so we want to restrict this ioremap from |
| 1526 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, |
| 1527 | * the register BAR remains the same size for all the earlier |
| 1528 | * generations up to Ironlake. |
| 1529 | */ |
| 1530 | if (info->gen < 5) |
| 1531 | mmio_size = 512*1024; |
| 1532 | else |
| 1533 | mmio_size = 2*1024*1024; |
| 1534 | |
| 1535 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size); |
| 1536 | if (!dev_priv->regs) { |
| 1537 | DRM_ERROR("failed to map registers\n"); |
| 1538 | ret = -EIO; |
| 1539 | goto put_bridge; |
| 1540 | } |
| 1541 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1542 | intel_uncore_early_sanitize(dev); |
Ben Widawsky | 1e1bd0f | 2013-04-08 18:43:49 -0700 | [diff] [blame] | 1543 | |
Ben Widawsky | c3d685a | 2013-10-08 16:31:03 -0700 | [diff] [blame] | 1544 | /* This must be called before any calls to HAS_PCH_* */ |
| 1545 | intel_detect_pch(dev); |
| 1546 | |
| 1547 | intel_uncore_init(dev); |
| 1548 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1549 | ret = i915_gem_gtt_init(dev); |
| 1550 | if (ret) |
Chris Wilson | cbb47d1 | 2013-09-23 17:33:20 -0300 | [diff] [blame] | 1551 | goto out_regs; |
Daniel Vetter | e188719 | 2012-06-12 11:28:17 +0200 | [diff] [blame] | 1552 | |
Chris Wilson | 1623392 | 2012-10-26 12:06:41 +0100 | [diff] [blame] | 1553 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 1554 | i915_kick_out_firmware_fb(dev_priv); |
Daniel Vetter | e188719 | 2012-06-12 11:28:17 +0200 | [diff] [blame] | 1555 | |
Dave Airlie | 466e69b | 2011-12-19 11:15:29 +0000 | [diff] [blame] | 1556 | pci_set_master(dev->pdev); |
| 1557 | |
Daniel Vetter | 9f82d23 | 2010-08-30 21:25:23 +0200 | [diff] [blame] | 1558 | /* overlay on gen2 is broken and can't address above 1G */ |
| 1559 | if (IS_GEN2(dev)) |
| 1560 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); |
| 1561 | |
Jan Niehusmann | 6927faf | 2011-03-01 23:24:16 +0100 | [diff] [blame] | 1562 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
| 1563 | * using 32bit addressing, overwriting memory if HWS is located |
| 1564 | * above 4GB. |
| 1565 | * |
| 1566 | * The documentation also mentions an issue with undefined |
| 1567 | * behaviour if any general state is accessed within a page above 4GB, |
| 1568 | * which also needs to be handled carefully. |
| 1569 | */ |
| 1570 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
| 1571 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); |
| 1572 | |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 1573 | aperture_size = dev_priv->gtt.mappable_end; |
Chris Wilson | 71e9339 | 2010-10-27 18:46:52 +0100 | [diff] [blame] | 1574 | |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 1575 | dev_priv->gtt.mappable = |
| 1576 | io_mapping_create_wc(dev_priv->gtt.mappable_base, |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1577 | aperture_size); |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 1578 | if (dev_priv->gtt.mappable == NULL) { |
Venkatesh Pallipadi | 6644107 | 2009-02-24 17:35:11 -0800 | [diff] [blame] | 1579 | ret = -EIO; |
Chris Wilson | cbb47d1 | 2013-09-23 17:33:20 -0300 | [diff] [blame] | 1580 | goto out_gtt; |
Venkatesh Pallipadi | 6644107 | 2009-02-24 17:35:11 -0800 | [diff] [blame] | 1581 | } |
| 1582 | |
Ben Widawsky | 911bdf0 | 2013-06-27 16:30:23 -0700 | [diff] [blame] | 1583 | dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base, |
| 1584 | aperture_size); |
Eric Anholt | ab657db1 | 2009-01-23 12:57:47 -0800 | [diff] [blame] | 1585 | |
Chris Wilson | e642abb | 2010-09-09 12:46:34 +0100 | [diff] [blame] | 1586 | /* The i915 workqueue is primarily used for batched retirement of |
| 1587 | * requests (and thus managing bo) once the task has been completed |
| 1588 | * by the GPU. i915_gem_retire_requests() is called directly when we |
| 1589 | * need high-priority retirement, such as waiting for an explicit |
| 1590 | * bo. |
| 1591 | * |
| 1592 | * It is also used for periodic low-priority events, such as |
Eric Anholt | df9c204 | 2010-11-18 09:31:12 +0800 | [diff] [blame] | 1593 | * idle-timers and recording error state. |
Chris Wilson | e642abb | 2010-09-09 12:46:34 +0100 | [diff] [blame] | 1594 | * |
| 1595 | * All tasks on the workqueue are expected to acquire the dev mutex |
| 1596 | * so there is no point in running more than one instance of the |
Tejun Heo | 5362186 | 2012-08-22 16:40:57 -0700 | [diff] [blame] | 1597 | * workqueue at any time. Use an ordered one. |
Chris Wilson | e642abb | 2010-09-09 12:46:34 +0100 | [diff] [blame] | 1598 | */ |
Tejun Heo | 5362186 | 2012-08-22 16:40:57 -0700 | [diff] [blame] | 1599 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1600 | if (dev_priv->wq == NULL) { |
| 1601 | DRM_ERROR("Failed to create our workqueue.\n"); |
| 1602 | ret = -ENOMEM; |
Keith Packard | a7b85d2 | 2011-07-10 13:12:17 -0700 | [diff] [blame] | 1603 | goto out_mtrrfree; |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1604 | } |
| 1605 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1606 | intel_irq_init(dev); |
Ben Widawsky | 78511f2 | 2013-10-04 21:22:49 -0700 | [diff] [blame] | 1607 | intel_uncore_sanitize(dev); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 1608 | |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1609 | /* Try to make sure MCHBAR is enabled before poking at it */ |
| 1610 | intel_setup_mchbar(dev); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1611 | intel_setup_gmbus(dev); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1612 | intel_opregion_setup(dev); |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1613 | |
Bryan Freed | 6d139a8 | 2010-10-14 09:14:51 +0100 | [diff] [blame] | 1614 | intel_setup_bios(dev); |
| 1615 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1616 | i915_gem_load(dev); |
| 1617 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1618 | /* On the 945G/GM, the chipset reports the MSI capability on the |
| 1619 | * integrated graphics even though the support isn't actually there |
| 1620 | * according to the published specs. It doesn't appear to function |
| 1621 | * correctly in testing on 945G. |
| 1622 | * This may be a side effect of MSI having been made available for PEG |
| 1623 | * and the registers being closely associated. |
Keith Packard | d1ed629 | 2008-10-17 00:44:42 -0700 | [diff] [blame] | 1624 | * |
| 1625 | * According to chipset errata, on the 965GM, MSI interrupts may |
Keith Packard | b60678a | 2008-12-08 11:12:28 -0800 | [diff] [blame] | 1626 | * be lost or delayed, but we use them anyways to avoid |
| 1627 | * stuck interrupts on some machines. |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1628 | */ |
Keith Packard | b60678a | 2008-12-08 11:12:28 -0800 | [diff] [blame] | 1629 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
Eric Anholt | d3e74d0 | 2008-11-03 14:46:17 -0800 | [diff] [blame] | 1630 | pci_enable_msi(dev->pdev); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1631 | |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 1632 | dev_priv->num_plane = 1; |
| 1633 | if (IS_VALLEYVIEW(dev)) |
| 1634 | dev_priv->num_plane = 2; |
| 1635 | |
Ben Widawsky | e3c7475 | 2013-04-05 13:12:39 -0700 | [diff] [blame] | 1636 | if (INTEL_INFO(dev)->num_pipes) { |
| 1637 | ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes); |
| 1638 | if (ret) |
| 1639 | goto out_gem_unload; |
| 1640 | } |
Keith Packard | 5244021 | 2008-11-18 09:30:25 -0800 | [diff] [blame] | 1641 | |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 1642 | if (HAS_POWER_WELL(dev)) |
Imre Deak | ddb642f | 2013-10-28 17:20:35 +0200 | [diff] [blame] | 1643 | intel_power_domains_init(dev); |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 1644 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1645 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
Daniel Vetter | 5398463 | 2010-09-22 23:44:24 +0200 | [diff] [blame] | 1646 | ret = i915_load_modeset_init(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1647 | if (ret < 0) { |
| 1648 | DRM_ERROR("failed to init modeset\n"); |
Chris Wilson | cbb47d1 | 2013-09-23 17:33:20 -0300 | [diff] [blame] | 1649 | goto out_power_well; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1650 | } |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 1651 | } else { |
| 1652 | /* Start out suspended in ums mode. */ |
| 1653 | dev_priv->ums.mm_suspended = 1; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1654 | } |
| 1655 | |
Ben Widawsky | 0136db58 | 2012-04-10 21:17:01 -0700 | [diff] [blame] | 1656 | i915_setup_sysfs(dev); |
| 1657 | |
Ben Widawsky | e3c7475 | 2013-04-05 13:12:39 -0700 | [diff] [blame] | 1658 | if (INTEL_INFO(dev)->num_pipes) { |
| 1659 | /* Must be done after probing outputs */ |
| 1660 | intel_opregion_init(dev); |
Rafael J. Wysocki | 8e5c2b7 | 2013-07-25 21:43:39 +0200 | [diff] [blame] | 1661 | acpi_video_register(); |
Ben Widawsky | e3c7475 | 2013-04-05 13:12:39 -0700 | [diff] [blame] | 1662 | } |
Matthew Garrett | 74a365b | 2009-03-19 21:35:39 +0000 | [diff] [blame] | 1663 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 1664 | if (IS_GEN5(dev)) |
| 1665 | intel_gpu_ips_init(dev_priv); |
Eric Anholt | 63ee41d | 2010-12-20 18:40:06 -0800 | [diff] [blame] | 1666 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1667 | return 0; |
| 1668 | |
Chris Wilson | cbb47d1 | 2013-09-23 17:33:20 -0300 | [diff] [blame] | 1669 | out_power_well: |
| 1670 | if (HAS_POWER_WELL(dev)) |
Imre Deak | ddb642f | 2013-10-28 17:20:35 +0200 | [diff] [blame] | 1671 | intel_power_domains_remove(dev); |
Chris Wilson | cbb47d1 | 2013-09-23 17:33:20 -0300 | [diff] [blame] | 1672 | drm_vblank_cleanup(dev); |
Chris Wilson | 56e2ea3 | 2010-11-08 17:10:29 +0000 | [diff] [blame] | 1673 | out_gem_unload: |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 1674 | if (dev_priv->mm.inactive_shrinker.scan_objects) |
Keith Packard | a7b85d2 | 2011-07-10 13:12:17 -0700 | [diff] [blame] | 1675 | unregister_shrinker(&dev_priv->mm.inactive_shrinker); |
| 1676 | |
Chris Wilson | 56e2ea3 | 2010-11-08 17:10:29 +0000 | [diff] [blame] | 1677 | if (dev->pdev->msi_enabled) |
| 1678 | pci_disable_msi(dev->pdev); |
| 1679 | |
| 1680 | intel_teardown_gmbus(dev); |
| 1681 | intel_teardown_mchbar(dev); |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1682 | destroy_workqueue(dev_priv->wq); |
Keith Packard | a7b85d2 | 2011-07-10 13:12:17 -0700 | [diff] [blame] | 1683 | out_mtrrfree: |
Ben Widawsky | 911bdf0 | 2013-06-27 16:30:23 -0700 | [diff] [blame] | 1684 | arch_phys_wc_del(dev_priv->gtt.mtrr); |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 1685 | io_mapping_free(dev_priv->gtt.mappable); |
Chris Wilson | cbb47d1 | 2013-09-23 17:33:20 -0300 | [diff] [blame] | 1686 | out_gtt: |
| 1687 | list_del(&dev_priv->gtt.base.global_link); |
| 1688 | drm_mm_takedown(&dev_priv->gtt.base.mm); |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1689 | dev_priv->gtt.base.cleanup(&dev_priv->gtt.base); |
Chris Wilson | cbb47d1 | 2013-09-23 17:33:20 -0300 | [diff] [blame] | 1690 | out_regs: |
Ben Widawsky | c3d685a | 2013-10-08 16:31:03 -0700 | [diff] [blame] | 1691 | intel_uncore_fini(dev); |
Chris Wilson | 6dda569 | 2010-10-29 21:02:18 +0100 | [diff] [blame] | 1692 | pci_iounmap(dev->pdev, dev_priv->regs); |
Dave Airlie | ec2a4c3 | 2009-08-04 11:43:41 +1000 | [diff] [blame] | 1693 | put_bridge: |
| 1694 | pci_dev_put(dev_priv->bridge_dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1695 | free_priv: |
Chris Wilson | cbb47d1 | 2013-09-23 17:33:20 -0300 | [diff] [blame] | 1696 | if (dev_priv->slab) |
| 1697 | kmem_cache_destroy(dev_priv->slab); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1698 | kfree(dev_priv); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1699 | return ret; |
| 1700 | } |
| 1701 | |
| 1702 | int i915_driver_unload(struct drm_device *dev) |
| 1703 | { |
| 1704 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c911fc1 | 2010-08-20 21:23:20 +0200 | [diff] [blame] | 1705 | int ret; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1706 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 1707 | intel_gpu_ips_teardown(); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1708 | |
Paulo Zanoni | 79f8dea | 2013-08-14 14:40:37 -0300 | [diff] [blame] | 1709 | if (HAS_POWER_WELL(dev)) { |
| 1710 | /* The i915.ko module is still not prepared to be loaded when |
| 1711 | * the power well is not enabled, so just enable it in case |
| 1712 | * we're going to unload/reload. */ |
Imre Deak | baa7070 | 2013-10-25 17:36:48 +0300 | [diff] [blame] | 1713 | intel_display_set_init_power(dev, true); |
Imre Deak | ddb642f | 2013-10-28 17:20:35 +0200 | [diff] [blame] | 1714 | intel_power_domains_remove(dev); |
Paulo Zanoni | 79f8dea | 2013-08-14 14:40:37 -0300 | [diff] [blame] | 1715 | } |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 1716 | |
Ben Widawsky | 0136db58 | 2012-04-10 21:17:01 -0700 | [diff] [blame] | 1717 | i915_teardown_sysfs(dev); |
| 1718 | |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 1719 | if (dev_priv->mm.inactive_shrinker.scan_objects) |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 1720 | unregister_shrinker(&dev_priv->mm.inactive_shrinker); |
| 1721 | |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 1722 | ret = i915_gem_suspend(dev); |
Daniel Vetter | c911fc1 | 2010-08-20 21:23:20 +0200 | [diff] [blame] | 1723 | if (ret) |
| 1724 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 1725 | |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 1726 | io_mapping_free(dev_priv->gtt.mappable); |
Ben Widawsky | 911bdf0 | 2013-06-27 16:30:23 -0700 | [diff] [blame] | 1727 | arch_phys_wc_del(dev_priv->gtt.mtrr); |
Eric Anholt | ab657db1 | 2009-01-23 12:57:47 -0800 | [diff] [blame] | 1728 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1729 | acpi_video_unregister(); |
| 1730 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1731 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
Chris Wilson | 7b4f399 | 2010-10-04 15:33:04 +0100 | [diff] [blame] | 1732 | intel_fbdev_fini(dev); |
Jesse Barnes | 3d8620c | 2010-03-26 11:07:21 -0700 | [diff] [blame] | 1733 | intel_modeset_cleanup(dev); |
Jesse Barnes | 073f34d | 2012-11-02 11:13:59 -0700 | [diff] [blame] | 1734 | cancel_work_sync(&dev_priv->console_resume_work); |
Jesse Barnes | 3d8620c | 2010-03-26 11:07:21 -0700 | [diff] [blame] | 1735 | |
Zhao Yakui | 6363ee6 | 2009-11-24 09:48:44 +0800 | [diff] [blame] | 1736 | /* |
| 1737 | * free the memory space allocated for the child device |
| 1738 | * config parsed from VBT |
| 1739 | */ |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1740 | if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) { |
| 1741 | kfree(dev_priv->vbt.child_dev); |
| 1742 | dev_priv->vbt.child_dev = NULL; |
| 1743 | dev_priv->vbt.child_dev_num = 0; |
Zhao Yakui | 6363ee6 | 2009-11-24 09:48:44 +0800 | [diff] [blame] | 1744 | } |
Daniel Vetter | 6c0d9350 | 2010-08-20 18:26:46 +0200 | [diff] [blame] | 1745 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1746 | vga_switcheroo_unregister_client(dev->pdev); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1747 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1748 | } |
| 1749 | |
Daniel Vetter | a8b4899 | 2010-08-20 21:25:11 +0200 | [diff] [blame] | 1750 | /* Free error state after interrupts are fully disabled. */ |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1751 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
| 1752 | cancel_work_sync(&dev_priv->gpu_error.work); |
Daniel Vetter | a8b4899 | 2010-08-20 21:25:11 +0200 | [diff] [blame] | 1753 | i915_destroy_error_state(dev); |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 1754 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1755 | cancel_delayed_work_sync(&dev_priv->pc8.enable_work); |
| 1756 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1757 | if (dev->pdev->msi_enabled) |
| 1758 | pci_disable_msi(dev->pdev); |
| 1759 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1760 | intel_opregion_fini(dev); |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 1761 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1762 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 1763 | /* Flush any outstanding unpin_work. */ |
| 1764 | flush_workqueue(dev_priv->wq); |
| 1765 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1766 | mutex_lock(&dev->struct_mutex); |
Hugh Dickins | ecbec53 | 2011-06-27 16:18:20 -0700 | [diff] [blame] | 1767 | i915_gem_free_all_phys_object(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1768 | i915_gem_cleanup_ringbuffer(dev); |
Daniel Vetter | 55a6662 | 2012-06-19 21:55:32 +0200 | [diff] [blame] | 1769 | i915_gem_context_fini(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1770 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1771 | i915_gem_cleanup_aliasing_ppgtt(dev); |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 1772 | i915_gem_cleanup_stolen(dev); |
Keith Packard | c2873e9 | 2010-10-07 09:20:12 +0100 | [diff] [blame] | 1773 | |
| 1774 | if (!I915_NEED_GFX_HWS(dev)) |
| 1775 | i915_free_hws(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1776 | } |
| 1777 | |
Ben Widawsky | a7bbbd6 | 2013-07-16 16:50:07 -0700 | [diff] [blame] | 1778 | list_del(&dev_priv->gtt.base.global_link); |
| 1779 | WARN_ON(!list_empty(&dev_priv->vm_list)); |
Ben Widawsky | 93bd864 | 2013-07-16 16:50:06 -0700 | [diff] [blame] | 1780 | drm_mm_takedown(&dev_priv->gtt.base.mm); |
Daniel Vetter | 701394c | 2010-10-10 18:54:08 +0100 | [diff] [blame] | 1781 | |
Chris Wilson | cbb47d1 | 2013-09-23 17:33:20 -0300 | [diff] [blame] | 1782 | drm_vblank_cleanup(dev); |
| 1783 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1784 | intel_teardown_gmbus(dev); |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1785 | intel_teardown_mchbar(dev); |
| 1786 | |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 1787 | destroy_workqueue(dev_priv->wq); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 1788 | pm_qos_remove_request(&dev_priv->pm_qos); |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 1789 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1790 | dev_priv->gtt.base.cleanup(&dev_priv->gtt.base); |
Imre Deak | 6640aab | 2013-05-22 17:47:13 +0300 | [diff] [blame] | 1791 | |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 1792 | intel_uncore_fini(dev); |
| 1793 | if (dev_priv->regs != NULL) |
| 1794 | pci_iounmap(dev->pdev, dev_priv->regs); |
| 1795 | |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 1796 | if (dev_priv->slab) |
| 1797 | kmem_cache_destroy(dev_priv->slab); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1798 | |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1799 | pci_dev_put(dev_priv->bridge_dev); |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 1800 | kfree(dev->dev_private); |
| 1801 | |
| 1802 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1803 | } |
| 1804 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1805 | int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1806 | { |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1807 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1808 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1809 | ret = i915_gem_open(dev, file); |
| 1810 | if (ret) |
| 1811 | return ret; |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 1812 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1813 | return 0; |
| 1814 | } |
| 1815 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1816 | /** |
| 1817 | * i915_driver_lastclose - clean up after all DRM clients have exited |
| 1818 | * @dev: DRM device |
| 1819 | * |
| 1820 | * Take care of cleaning up after all DRM clients have exited. In the |
| 1821 | * mode setting case, we want to restore the kernel's initial mode (just |
| 1822 | * in case the last client left us in a bad state). |
| 1823 | * |
Daniel Vetter | 9021f28 | 2012-03-26 09:45:41 +0200 | [diff] [blame] | 1824 | * Additionally, in the non-mode setting case, we'll tear down the GTT |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1825 | * and DMA structures, since the kernel won't be using them, and clea |
| 1826 | * up any GEM state. |
| 1827 | */ |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1828 | void i915_driver_lastclose(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1829 | { |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1830 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1831 | |
Daniel Vetter | e8aeaee | 2012-07-21 16:47:09 +0200 | [diff] [blame] | 1832 | /* On gen6+ we refuse to init without kms enabled, but then the drm core |
| 1833 | * goes right around and calls lastclose. Check for this and don't clean |
| 1834 | * up anything. */ |
| 1835 | if (!dev_priv) |
| 1836 | return; |
| 1837 | |
| 1838 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
Daniel Vetter | 0632fef | 2013-10-08 17:44:49 +0200 | [diff] [blame] | 1839 | intel_fbdev_restore_mode(dev); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1840 | vga_switcheroo_process_delayed_switch(); |
Dave Airlie | 144a75f | 2008-03-30 07:53:58 +1000 | [diff] [blame] | 1841 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1842 | } |
Dave Airlie | 144a75f | 2008-03-30 07:53:58 +1000 | [diff] [blame] | 1843 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1844 | i915_gem_lastclose(dev); |
| 1845 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1846 | i915_dma_cleanup(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1847 | } |
| 1848 | |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 1849 | void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1850 | { |
Chris Wilson | 0d1430a | 2013-12-04 14:52:06 +0000 | [diff] [blame] | 1851 | mutex_lock(&dev->struct_mutex); |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 1852 | i915_gem_context_close(dev, file_priv); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1853 | i915_gem_release(dev, file_priv); |
Chris Wilson | 0d1430a | 2013-12-04 14:52:06 +0000 | [diff] [blame] | 1854 | mutex_unlock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1855 | } |
| 1856 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1857 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1858 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1859 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1860 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1861 | kfree(file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1862 | } |
| 1863 | |
Rob Clark | baa7094 | 2013-08-02 13:27:49 -0400 | [diff] [blame] | 1864 | const struct drm_ioctl_desc i915_ioctls[] = { |
Dave Airlie | 1b2f148 | 2010-08-14 20:20:34 +1000 | [diff] [blame] | 1865 | DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 1866 | DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH), |
| 1867 | DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH), |
| 1868 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), |
| 1869 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), |
| 1870 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), |
Kristian Høgsberg | 10ba501 | 2013-08-25 18:29:01 +0200 | [diff] [blame] | 1871 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW), |
Dave Airlie | 1b2f148 | 2010-08-14 20:20:34 +1000 | [diff] [blame] | 1872 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
Daniel Vetter | b2c606f | 2012-01-17 12:50:12 +0100 | [diff] [blame] | 1873 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), |
| 1874 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), |
| 1875 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
Dave Airlie | 1b2f148 | 2010-08-14 20:20:34 +1000 | [diff] [blame] | 1876 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), |
Daniel Vetter | b2c606f | 2012-01-17 12:50:12 +0100 | [diff] [blame] | 1877 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
Daniel Vetter | d1c1edb | 2012-04-26 23:28:01 +0200 | [diff] [blame] | 1878 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
Dave Airlie | 1b2f148 | 2010-08-14 20:20:34 +1000 | [diff] [blame] | 1879 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH), |
| 1880 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), |
| 1881 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 1882 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
| 1883 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), |
Kristian Høgsberg | 10ba501 | 2013-08-25 18:29:01 +0200 | [diff] [blame] | 1884 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
Dave Airlie | 1b2f148 | 2010-08-14 20:20:34 +1000 | [diff] [blame] | 1885 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), |
| 1886 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), |
Kristian Høgsberg | 10ba501 | 2013-08-25 18:29:01 +0200 | [diff] [blame] | 1887 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1888 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1889 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1890 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
Dave Airlie | 1b2f148 | 2010-08-14 20:20:34 +1000 | [diff] [blame] | 1891 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
| 1892 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
Kristian Høgsberg | 10ba501 | 2013-08-25 18:29:01 +0200 | [diff] [blame] | 1893 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1894 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1895 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1896 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1897 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1898 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1899 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1900 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1901 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1902 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
Dave Airlie | 1b2f148 | 2010-08-14 20:20:34 +1000 | [diff] [blame] | 1903 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), |
Kristian Høgsberg | 10ba501 | 2013-08-25 18:29:01 +0200 | [diff] [blame] | 1904 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
Dave Airlie | 1b2f148 | 2010-08-14 20:20:34 +1000 | [diff] [blame] | 1905 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
| 1906 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
Jesse Barnes | 8ea3086 | 2012-01-03 08:05:39 -0800 | [diff] [blame] | 1907 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
| 1908 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
Kristian Høgsberg | 10ba501 | 2013-08-25 18:29:01 +0200 | [diff] [blame] | 1909 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1910 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1911 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1912 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
Dave Airlie | c94f702 | 2005-07-07 21:03:38 +1000 | [diff] [blame] | 1913 | }; |
| 1914 | |
| 1915 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); |
Dave Airlie | cda1738 | 2005-07-10 17:31:26 +1000 | [diff] [blame] | 1916 | |
Daniel Vetter | 9021f28 | 2012-03-26 09:45:41 +0200 | [diff] [blame] | 1917 | /* |
| 1918 | * This is really ugly: Because old userspace abused the linux agp interface to |
| 1919 | * manage the gtt, we need to claim that all intel devices are agp. For |
| 1920 | * otherwise the drm core refuses to initialize the agp support code. |
Dave Airlie | cda1738 | 2005-07-10 17:31:26 +1000 | [diff] [blame] | 1921 | */ |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1922 | int i915_driver_device_is_agp(struct drm_device * dev) |
Dave Airlie | cda1738 | 2005-07-10 17:31:26 +1000 | [diff] [blame] | 1923 | { |
| 1924 | return 1; |
| 1925 | } |