Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
| 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 5 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 8 | * copy of this software and associated documentation files (the |
| 9 | * "Software"), to deal in the Software without restriction, including |
| 10 | * without limitation the rights to use, copy, modify, merge, publish, |
| 11 | * distribute, sub license, and/or sell copies of the Software, and to |
| 12 | * permit persons to whom the Software is furnished to do so, subject to |
| 13 | * the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the |
| 16 | * next paragraph) shall be included in all copies or substantial portions |
| 17 | * of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 26 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 27 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 30 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 31 | #include <drm/drmP.h> |
| 32 | #include <drm/drm_crtc_helper.h> |
| 33 | #include <drm/drm_fb_helper.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 34 | #include "intel_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 35 | #include <drm/i915_drm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 37 | #include "i915_trace.h" |
Jordan Crouse | dcdb167 | 2010-05-27 13:40:25 -0600 | [diff] [blame] | 38 | #include <linux/pci.h> |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 39 | #include <linux/vgaarb.h> |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 40 | #include <linux/acpi.h> |
| 41 | #include <linux/pnp.h> |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 42 | #include <linux/vga_switcheroo.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 43 | #include <linux/slab.h> |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 44 | #include <acpi/video.h> |
Adam Jackson | 9e984bc1 | 2012-03-14 11:22:11 -0400 | [diff] [blame] | 45 | #include <asm/pat.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | |
Daniel Vetter | 09422b2 | 2012-04-26 23:28:10 +0200 | [diff] [blame] | 47 | #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
| 48 | |
| 49 | #define BEGIN_LP_RING(n) \ |
| 50 | intel_ring_begin(LP_RING(dev_priv), (n)) |
| 51 | |
| 52 | #define OUT_RING(x) \ |
| 53 | intel_ring_emit(LP_RING(dev_priv), x) |
| 54 | |
| 55 | #define ADVANCE_LP_RING() \ |
| 56 | intel_ring_advance(LP_RING(dev_priv)) |
| 57 | |
| 58 | /** |
| 59 | * Lock test for when it's just for synchronization of ring access. |
| 60 | * |
| 61 | * In that case, we don't need to do it when GEM is initialized as nobody else |
| 62 | * has access to the ring. |
| 63 | */ |
| 64 | #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ |
| 65 | if (LP_RING(dev->dev_private)->obj == NULL) \ |
| 66 | LOCK_TEST_WITH_RETURN(dev, file); \ |
| 67 | } while (0) |
| 68 | |
Daniel Vetter | 316d388 | 2012-04-26 23:28:15 +0200 | [diff] [blame] | 69 | static inline u32 |
| 70 | intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg) |
| 71 | { |
| 72 | if (I915_NEED_GFX_HWS(dev_priv->dev)) |
| 73 | return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg); |
| 74 | else |
| 75 | return intel_read_status_page(LP_RING(dev_priv), reg); |
| 76 | } |
| 77 | |
| 78 | #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg) |
Daniel Vetter | 09422b2 | 2012-04-26 23:28:10 +0200 | [diff] [blame] | 79 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) |
| 80 | #define I915_BREADCRUMB_INDEX 0x21 |
| 81 | |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 82 | void i915_update_dri1_breadcrumb(struct drm_device *dev) |
| 83 | { |
| 84 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 85 | struct drm_i915_master_private *master_priv; |
| 86 | |
| 87 | if (dev->primary->master) { |
| 88 | master_priv = dev->primary->master->driver_priv; |
| 89 | if (master_priv->sarea_priv) |
| 90 | master_priv->sarea_priv->last_dispatch = |
| 91 | READ_BREADCRUMB(dev_priv); |
| 92 | } |
| 93 | } |
| 94 | |
Chris Wilson | 4cbf74c | 2011-02-25 22:26:23 +0000 | [diff] [blame] | 95 | static void i915_write_hws_pga(struct drm_device *dev) |
| 96 | { |
| 97 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 98 | u32 addr; |
| 99 | |
| 100 | addr = dev_priv->status_page_dmah->busaddr; |
| 101 | if (INTEL_INFO(dev)->gen >= 4) |
| 102 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
| 103 | I915_WRITE(HWS_PGA, addr); |
| 104 | } |
| 105 | |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 106 | /** |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 107 | * Frees the hardware status page, whether it's a physical address or a virtual |
| 108 | * address set up by the X Server. |
| 109 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 110 | static void i915_free_hws(struct drm_device *dev) |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 111 | { |
| 112 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 113 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
| 114 | |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 115 | if (dev_priv->status_page_dmah) { |
| 116 | drm_pci_free(dev, dev_priv->status_page_dmah); |
| 117 | dev_priv->status_page_dmah = NULL; |
| 118 | } |
| 119 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 120 | if (ring->status_page.gfx_addr) { |
| 121 | ring->status_page.gfx_addr = 0; |
Daniel Vetter | 316d388 | 2012-04-26 23:28:15 +0200 | [diff] [blame] | 122 | iounmap(dev_priv->dri1.gfx_hws_cpu_addr); |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 123 | } |
| 124 | |
| 125 | /* Need to rewrite hardware status page */ |
| 126 | I915_WRITE(HWS_PGA, 0x1ffff000); |
| 127 | } |
| 128 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 129 | void i915_kernel_lost_context(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 130 | { |
| 131 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 132 | struct drm_i915_master_private *master_priv; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 133 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 134 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 135 | /* |
| 136 | * We should never lose context on the ring with modesetting |
| 137 | * as we don't expose it to userspace |
| 138 | */ |
| 139 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 140 | return; |
| 141 | |
Chris Wilson | 8168bd4 | 2010-11-11 17:54:52 +0000 | [diff] [blame] | 142 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
| 143 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
Ville Syrjälä | 633cf8f | 2012-12-03 18:43:32 +0200 | [diff] [blame] | 144 | ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 145 | if (ring->space < 0) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 146 | ring->space += ring->size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 147 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 148 | if (!dev->primary->master) |
| 149 | return; |
| 150 | |
| 151 | master_priv = dev->primary->master->driver_priv; |
| 152 | if (ring->head == ring->tail && master_priv->sarea_priv) |
| 153 | master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 154 | } |
| 155 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 156 | static int i915_dma_cleanup(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 157 | { |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 158 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 159 | int i; |
| 160 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 161 | /* Make sure interrupts are disabled here because the uninstall ioctl |
| 162 | * may not have been called from userspace and after dev_private |
| 163 | * is freed, it's too late. |
| 164 | */ |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 165 | if (dev->irq_enabled) |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 166 | drm_irq_uninstall(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 167 | |
Dan Carpenter | ee0c6bf | 2010-06-23 13:19:55 +0200 | [diff] [blame] | 168 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 169 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 170 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); |
Dan Carpenter | ee0c6bf | 2010-06-23 13:19:55 +0200 | [diff] [blame] | 171 | mutex_unlock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 172 | |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 173 | /* Clear the HWS virtual address at teardown */ |
| 174 | if (I915_NEED_GFX_HWS(dev)) |
| 175 | i915_free_hws(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 176 | |
| 177 | return 0; |
| 178 | } |
| 179 | |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 180 | static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 181 | { |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 182 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 183 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 184 | int ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 185 | |
Dave Airlie | 3a03ac1 | 2009-01-11 09:03:49 +1000 | [diff] [blame] | 186 | master_priv->sarea = drm_getsarea(dev); |
| 187 | if (master_priv->sarea) { |
| 188 | master_priv->sarea_priv = (drm_i915_sarea_t *) |
| 189 | ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); |
| 190 | } else { |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 191 | DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); |
Dave Airlie | 3a03ac1 | 2009-01-11 09:03:49 +1000 | [diff] [blame] | 192 | } |
| 193 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 194 | if (init->ring_size != 0) { |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 195 | if (LP_RING(dev_priv)->obj != NULL) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 196 | i915_dma_cleanup(dev); |
| 197 | DRM_ERROR("Client tried to initialize ringbuffer in " |
| 198 | "GEM mode\n"); |
| 199 | return -EINVAL; |
| 200 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 201 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 202 | ret = intel_render_ring_init_dri(dev, |
| 203 | init->ring_start, |
| 204 | init->ring_size); |
| 205 | if (ret) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 206 | i915_dma_cleanup(dev); |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 207 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 208 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 209 | } |
| 210 | |
Daniel Vetter | 5d985ac | 2012-08-12 19:27:13 +0200 | [diff] [blame] | 211 | dev_priv->dri1.cpp = init->cpp; |
| 212 | dev_priv->dri1.back_offset = init->back_offset; |
| 213 | dev_priv->dri1.front_offset = init->front_offset; |
| 214 | dev_priv->dri1.current_page = 0; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 215 | if (master_priv->sarea_priv) |
| 216 | master_priv->sarea_priv->pf_current_page = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 217 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 218 | /* Allow hardware batchbuffers unless told otherwise. |
| 219 | */ |
Daniel Vetter | 8781342 | 2012-05-02 11:49:32 +0200 | [diff] [blame] | 220 | dev_priv->dri1.allow_batchbuffer = 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 221 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 222 | return 0; |
| 223 | } |
| 224 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 225 | static int i915_dma_resume(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 226 | { |
| 227 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 228 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 229 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 230 | DRM_DEBUG_DRIVER("%s\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 231 | |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 232 | if (ring->virtual_start == NULL) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 233 | DRM_ERROR("can not ioremap virtual address for" |
| 234 | " ring buffer\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 235 | return -ENOMEM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 236 | } |
| 237 | |
| 238 | /* Program Hardware Status Page */ |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 239 | if (!ring->status_page.page_addr) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 240 | DRM_ERROR("Can not find hardware status page\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 241 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 242 | } |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 243 | DRM_DEBUG_DRIVER("hw status page @ %p\n", |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 244 | ring->status_page.page_addr); |
| 245 | if (ring->status_page.gfx_addr != 0) |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 246 | intel_ring_setup_status_page(ring); |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 247 | else |
Chris Wilson | 4cbf74c | 2011-02-25 22:26:23 +0000 | [diff] [blame] | 248 | i915_write_hws_pga(dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 249 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 250 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 251 | |
| 252 | return 0; |
| 253 | } |
| 254 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 255 | static int i915_dma_init(struct drm_device *dev, void *data, |
| 256 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 257 | { |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 258 | drm_i915_init_t *init = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 259 | int retcode = 0; |
| 260 | |
Daniel Vetter | cd9d4e9 | 2012-04-24 08:29:42 +0200 | [diff] [blame] | 261 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 262 | return -ENODEV; |
| 263 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 264 | switch (init->func) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 265 | case I915_INIT_DMA: |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 266 | retcode = i915_initialize(dev, init); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 267 | break; |
| 268 | case I915_CLEANUP_DMA: |
| 269 | retcode = i915_dma_cleanup(dev); |
| 270 | break; |
| 271 | case I915_RESUME_DMA: |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 272 | retcode = i915_dma_resume(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 273 | break; |
| 274 | default: |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 275 | retcode = -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 276 | break; |
| 277 | } |
| 278 | |
| 279 | return retcode; |
| 280 | } |
| 281 | |
| 282 | /* Implement basically the same security restrictions as hardware does |
| 283 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. |
| 284 | * |
| 285 | * Most of the calculations below involve calculating the size of a |
| 286 | * particular instruction. It's important to get the size right as |
| 287 | * that tells us where the next instruction to check is. Any illegal |
| 288 | * instruction detected will be given a size of zero, which is a |
| 289 | * signal to abort the rest of the buffer. |
| 290 | */ |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 291 | static int validate_cmd(int cmd) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 292 | { |
| 293 | switch (((cmd >> 29) & 0x7)) { |
| 294 | case 0x0: |
| 295 | switch ((cmd >> 23) & 0x3f) { |
| 296 | case 0x0: |
| 297 | return 1; /* MI_NOOP */ |
| 298 | case 0x4: |
| 299 | return 1; /* MI_FLUSH */ |
| 300 | default: |
| 301 | return 0; /* disallow everything else */ |
| 302 | } |
| 303 | break; |
| 304 | case 0x1: |
| 305 | return 0; /* reserved */ |
| 306 | case 0x2: |
| 307 | return (cmd & 0xff) + 2; /* 2d commands */ |
| 308 | case 0x3: |
| 309 | if (((cmd >> 24) & 0x1f) <= 0x18) |
| 310 | return 1; |
| 311 | |
| 312 | switch ((cmd >> 24) & 0x1f) { |
| 313 | case 0x1c: |
| 314 | return 1; |
| 315 | case 0x1d: |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 316 | switch ((cmd >> 16) & 0xff) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 317 | case 0x3: |
| 318 | return (cmd & 0x1f) + 2; |
| 319 | case 0x4: |
| 320 | return (cmd & 0xf) + 2; |
| 321 | default: |
| 322 | return (cmd & 0xffff) + 2; |
| 323 | } |
| 324 | case 0x1e: |
| 325 | if (cmd & (1 << 23)) |
| 326 | return (cmd & 0xffff) + 1; |
| 327 | else |
| 328 | return 1; |
| 329 | case 0x1f: |
| 330 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ |
| 331 | return (cmd & 0x1ffff) + 2; |
| 332 | else if (cmd & (1 << 17)) /* indirect random */ |
| 333 | if ((cmd & 0xffff) == 0) |
| 334 | return 0; /* unknown length, too hard */ |
| 335 | else |
| 336 | return (((cmd & 0xffff) + 1) / 2) + 1; |
| 337 | else |
| 338 | return 2; /* indirect sequential */ |
| 339 | default: |
| 340 | return 0; |
| 341 | } |
| 342 | default: |
| 343 | return 0; |
| 344 | } |
| 345 | |
| 346 | return 0; |
| 347 | } |
| 348 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 349 | static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 350 | { |
| 351 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 352 | int i, ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 353 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 354 | if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8) |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 355 | return -EINVAL; |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 356 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 357 | for (i = 0; i < dwords;) { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 358 | int sz = validate_cmd(buffer[i]); |
| 359 | if (sz == 0 || i + sz > dwords) |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 360 | return -EINVAL; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 361 | i += sz; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 362 | } |
| 363 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 364 | ret = BEGIN_LP_RING((dwords+1)&~1); |
| 365 | if (ret) |
| 366 | return ret; |
| 367 | |
| 368 | for (i = 0; i < dwords; i++) |
| 369 | OUT_RING(buffer[i]); |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 370 | if (dwords & 1) |
| 371 | OUT_RING(0); |
| 372 | |
| 373 | ADVANCE_LP_RING(); |
| 374 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 375 | return 0; |
| 376 | } |
| 377 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 378 | int |
| 379 | i915_emit_box(struct drm_device *dev, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 380 | struct drm_clip_rect *box, |
| 381 | int DR1, int DR4) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 382 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 383 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 384 | int ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 385 | |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 386 | if (box->y2 <= box->y1 || box->x2 <= box->x1 || |
| 387 | box->y2 <= 0 || box->x2 <= 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 388 | DRM_ERROR("Bad box %d,%d..%d,%d\n", |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 389 | box->x1, box->y1, box->x2, box->y2); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 390 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 391 | } |
| 392 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 393 | if (INTEL_INFO(dev)->gen >= 4) { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 394 | ret = BEGIN_LP_RING(4); |
| 395 | if (ret) |
| 396 | return ret; |
| 397 | |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 398 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 399 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
| 400 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 401 | OUT_RING(DR4); |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 402 | } else { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 403 | ret = BEGIN_LP_RING(6); |
| 404 | if (ret) |
| 405 | return ret; |
| 406 | |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 407 | OUT_RING(GFX_OP_DRAWRECT_INFO); |
| 408 | OUT_RING(DR1); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 409 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
| 410 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 411 | OUT_RING(DR4); |
| 412 | OUT_RING(0); |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 413 | } |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 414 | ADVANCE_LP_RING(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 415 | |
| 416 | return 0; |
| 417 | } |
| 418 | |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 419 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
| 420 | * emit. For now, do it in both places: |
| 421 | */ |
| 422 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 423 | static void i915_emit_breadcrumb(struct drm_device *dev) |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 424 | { |
| 425 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 426 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 427 | |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 428 | dev_priv->dri1.counter++; |
| 429 | if (dev_priv->dri1.counter > 0x7FFFFFFFUL) |
| 430 | dev_priv->dri1.counter = 0; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 431 | if (master_priv->sarea_priv) |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 432 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter; |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 433 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 434 | if (BEGIN_LP_RING(4) == 0) { |
| 435 | OUT_RING(MI_STORE_DWORD_INDEX); |
| 436 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 437 | OUT_RING(dev_priv->dri1.counter); |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 438 | OUT_RING(0); |
| 439 | ADVANCE_LP_RING(); |
| 440 | } |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 441 | } |
| 442 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 443 | static int i915_dispatch_cmdbuffer(struct drm_device * dev, |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 444 | drm_i915_cmdbuffer_t *cmd, |
| 445 | struct drm_clip_rect *cliprects, |
| 446 | void *cmdbuf) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 447 | { |
| 448 | int nbox = cmd->num_cliprects; |
| 449 | int i = 0, count, ret; |
| 450 | |
| 451 | if (cmd->sz & 0x3) { |
| 452 | DRM_ERROR("alignment"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 453 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 454 | } |
| 455 | |
| 456 | i915_kernel_lost_context(dev); |
| 457 | |
| 458 | count = nbox ? nbox : 1; |
| 459 | |
| 460 | for (i = 0; i < count; i++) { |
| 461 | if (i < nbox) { |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 462 | ret = i915_emit_box(dev, &cliprects[i], |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 463 | cmd->DR1, cmd->DR4); |
| 464 | if (ret) |
| 465 | return ret; |
| 466 | } |
| 467 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 468 | ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 469 | if (ret) |
| 470 | return ret; |
| 471 | } |
| 472 | |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 473 | i915_emit_breadcrumb(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 474 | return 0; |
| 475 | } |
| 476 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 477 | static int i915_dispatch_batchbuffer(struct drm_device * dev, |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 478 | drm_i915_batchbuffer_t * batch, |
| 479 | struct drm_clip_rect *cliprects) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 480 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 481 | struct drm_i915_private *dev_priv = dev->dev_private; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 482 | int nbox = batch->num_cliprects; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 483 | int i, count, ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 484 | |
| 485 | if ((batch->start | batch->used) & 0x7) { |
| 486 | DRM_ERROR("alignment"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 487 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 488 | } |
| 489 | |
| 490 | i915_kernel_lost_context(dev); |
| 491 | |
| 492 | count = nbox ? nbox : 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 493 | for (i = 0; i < count; i++) { |
| 494 | if (i < nbox) { |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 495 | ret = i915_emit_box(dev, &cliprects[i], |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 496 | batch->DR1, batch->DR4); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 497 | if (ret) |
| 498 | return ret; |
| 499 | } |
| 500 | |
Keith Packard | 0790d5e | 2008-07-30 12:28:47 -0700 | [diff] [blame] | 501 | if (!IS_I830(dev) && !IS_845G(dev)) { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 502 | ret = BEGIN_LP_RING(2); |
| 503 | if (ret) |
| 504 | return ret; |
| 505 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 506 | if (INTEL_INFO(dev)->gen >= 4) { |
Dave Airlie | 21f1628 | 2007-08-07 09:09:51 +1000 | [diff] [blame] | 507 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); |
| 508 | OUT_RING(batch->start); |
| 509 | } else { |
| 510 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); |
| 511 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); |
| 512 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 513 | } else { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 514 | ret = BEGIN_LP_RING(4); |
| 515 | if (ret) |
| 516 | return ret; |
| 517 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 518 | OUT_RING(MI_BATCH_BUFFER); |
| 519 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); |
| 520 | OUT_RING(batch->start + batch->used - 4); |
| 521 | OUT_RING(0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 522 | } |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 523 | ADVANCE_LP_RING(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 524 | } |
| 525 | |
Zou Nan hai | 1cafd34 | 2010-06-25 13:40:24 +0800 | [diff] [blame] | 526 | |
Chris Wilson | f00a3dd | 2010-10-21 14:57:17 +0100 | [diff] [blame] | 527 | if (IS_G4X(dev) || IS_GEN5(dev)) { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 528 | if (BEGIN_LP_RING(2) == 0) { |
| 529 | OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP); |
| 530 | OUT_RING(MI_NOOP); |
| 531 | ADVANCE_LP_RING(); |
| 532 | } |
Zou Nan hai | 1cafd34 | 2010-06-25 13:40:24 +0800 | [diff] [blame] | 533 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 534 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 535 | i915_emit_breadcrumb(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 536 | return 0; |
| 537 | } |
| 538 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 539 | static int i915_dispatch_flip(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 540 | { |
| 541 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 542 | struct drm_i915_master_private *master_priv = |
| 543 | dev->primary->master->driver_priv; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 544 | int ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 545 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 546 | if (!master_priv->sarea_priv) |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 547 | return -EINVAL; |
| 548 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 549 | DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", |
yakui_zhao | be25ed9 | 2009-06-02 14:13:55 +0800 | [diff] [blame] | 550 | __func__, |
Daniel Vetter | 5d985ac | 2012-08-12 19:27:13 +0200 | [diff] [blame] | 551 | dev_priv->dri1.current_page, |
yakui_zhao | be25ed9 | 2009-06-02 14:13:55 +0800 | [diff] [blame] | 552 | master_priv->sarea_priv->pf_current_page); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 553 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 554 | i915_kernel_lost_context(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 555 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 556 | ret = BEGIN_LP_RING(10); |
| 557 | if (ret) |
| 558 | return ret; |
| 559 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 560 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 561 | OUT_RING(0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 562 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 563 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); |
| 564 | OUT_RING(0); |
Daniel Vetter | 5d985ac | 2012-08-12 19:27:13 +0200 | [diff] [blame] | 565 | if (dev_priv->dri1.current_page == 0) { |
| 566 | OUT_RING(dev_priv->dri1.back_offset); |
| 567 | dev_priv->dri1.current_page = 1; |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 568 | } else { |
Daniel Vetter | 5d985ac | 2012-08-12 19:27:13 +0200 | [diff] [blame] | 569 | OUT_RING(dev_priv->dri1.front_offset); |
| 570 | dev_priv->dri1.current_page = 0; |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 571 | } |
| 572 | OUT_RING(0); |
Jesse Barnes | ac741ab | 2008-04-22 16:03:07 +1000 | [diff] [blame] | 573 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 574 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); |
| 575 | OUT_RING(0); |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 576 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 577 | ADVANCE_LP_RING(); |
Jesse Barnes | ac741ab | 2008-04-22 16:03:07 +1000 | [diff] [blame] | 578 | |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 579 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++; |
Jesse Barnes | ac741ab | 2008-04-22 16:03:07 +1000 | [diff] [blame] | 580 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 581 | if (BEGIN_LP_RING(4) == 0) { |
| 582 | OUT_RING(MI_STORE_DWORD_INDEX); |
| 583 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 584 | OUT_RING(dev_priv->dri1.counter); |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 585 | OUT_RING(0); |
| 586 | ADVANCE_LP_RING(); |
| 587 | } |
Jesse Barnes | ac741ab | 2008-04-22 16:03:07 +1000 | [diff] [blame] | 588 | |
Daniel Vetter | 5d985ac | 2012-08-12 19:27:13 +0200 | [diff] [blame] | 589 | master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page; |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 590 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 591 | } |
| 592 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 593 | static int i915_quiescent(struct drm_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 594 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 595 | i915_kernel_lost_context(dev); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 596 | return intel_ring_idle(LP_RING(dev->dev_private)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 597 | } |
| 598 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 599 | static int i915_flush_ioctl(struct drm_device *dev, void *data, |
| 600 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 601 | { |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 602 | int ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 603 | |
Daniel Vetter | cd9d4e9 | 2012-04-24 08:29:42 +0200 | [diff] [blame] | 604 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 605 | return -ENODEV; |
| 606 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 607 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
| 608 | |
| 609 | mutex_lock(&dev->struct_mutex); |
| 610 | ret = i915_quiescent(dev); |
| 611 | mutex_unlock(&dev->struct_mutex); |
| 612 | |
| 613 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 614 | } |
| 615 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 616 | static int i915_batchbuffer(struct drm_device *dev, void *data, |
| 617 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 618 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 619 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 620 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 621 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 622 | master_priv->sarea_priv; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 623 | drm_i915_batchbuffer_t *batch = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 624 | int ret; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 625 | struct drm_clip_rect *cliprects = NULL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 626 | |
Daniel Vetter | cd9d4e9 | 2012-04-24 08:29:42 +0200 | [diff] [blame] | 627 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 628 | return -ENODEV; |
| 629 | |
Daniel Vetter | 8781342 | 2012-05-02 11:49:32 +0200 | [diff] [blame] | 630 | if (!dev_priv->dri1.allow_batchbuffer) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 631 | DRM_ERROR("Batchbuffer ioctl disabled\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 632 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 633 | } |
| 634 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 635 | DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", |
yakui_zhao | be25ed9 | 2009-06-02 14:13:55 +0800 | [diff] [blame] | 636 | batch->start, batch->used, batch->num_cliprects); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 637 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 638 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 639 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 640 | if (batch->num_cliprects < 0) |
| 641 | return -EINVAL; |
| 642 | |
| 643 | if (batch->num_cliprects) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 644 | cliprects = kcalloc(batch->num_cliprects, |
| 645 | sizeof(struct drm_clip_rect), |
| 646 | GFP_KERNEL); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 647 | if (cliprects == NULL) |
| 648 | return -ENOMEM; |
| 649 | |
| 650 | ret = copy_from_user(cliprects, batch->cliprects, |
| 651 | batch->num_cliprects * |
| 652 | sizeof(struct drm_clip_rect)); |
Dan Carpenter | 9927a40 | 2010-06-19 15:12:51 +0200 | [diff] [blame] | 653 | if (ret != 0) { |
| 654 | ret = -EFAULT; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 655 | goto fail_free; |
Dan Carpenter | 9927a40 | 2010-06-19 15:12:51 +0200 | [diff] [blame] | 656 | } |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 657 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 658 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 659 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 660 | ret = i915_dispatch_batchbuffer(dev, batch, cliprects); |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 661 | mutex_unlock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 662 | |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 663 | if (sarea_priv) |
Keith Packard | 0baf823 | 2008-11-08 11:44:14 +1000 | [diff] [blame] | 664 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 665 | |
| 666 | fail_free: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 667 | kfree(cliprects); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 668 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 669 | return ret; |
| 670 | } |
| 671 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 672 | static int i915_cmdbuffer(struct drm_device *dev, void *data, |
| 673 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 674 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 675 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 676 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 677 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 678 | master_priv->sarea_priv; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 679 | drm_i915_cmdbuffer_t *cmdbuf = data; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 680 | struct drm_clip_rect *cliprects = NULL; |
| 681 | void *batch_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 682 | int ret; |
| 683 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 684 | DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", |
yakui_zhao | be25ed9 | 2009-06-02 14:13:55 +0800 | [diff] [blame] | 685 | cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 686 | |
Daniel Vetter | cd9d4e9 | 2012-04-24 08:29:42 +0200 | [diff] [blame] | 687 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 688 | return -ENODEV; |
| 689 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 690 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 691 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 692 | if (cmdbuf->num_cliprects < 0) |
| 693 | return -EINVAL; |
| 694 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 695 | batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 696 | if (batch_data == NULL) |
| 697 | return -ENOMEM; |
| 698 | |
| 699 | ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz); |
Dan Carpenter | 9927a40 | 2010-06-19 15:12:51 +0200 | [diff] [blame] | 700 | if (ret != 0) { |
| 701 | ret = -EFAULT; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 702 | goto fail_batch_free; |
Dan Carpenter | 9927a40 | 2010-06-19 15:12:51 +0200 | [diff] [blame] | 703 | } |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 704 | |
| 705 | if (cmdbuf->num_cliprects) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 706 | cliprects = kcalloc(cmdbuf->num_cliprects, |
| 707 | sizeof(struct drm_clip_rect), GFP_KERNEL); |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 708 | if (cliprects == NULL) { |
| 709 | ret = -ENOMEM; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 710 | goto fail_batch_free; |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 711 | } |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 712 | |
| 713 | ret = copy_from_user(cliprects, cmdbuf->cliprects, |
| 714 | cmdbuf->num_cliprects * |
| 715 | sizeof(struct drm_clip_rect)); |
Dan Carpenter | 9927a40 | 2010-06-19 15:12:51 +0200 | [diff] [blame] | 716 | if (ret != 0) { |
| 717 | ret = -EFAULT; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 718 | goto fail_clip_free; |
Dan Carpenter | 9927a40 | 2010-06-19 15:12:51 +0200 | [diff] [blame] | 719 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 720 | } |
| 721 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 722 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 723 | ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data); |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 724 | mutex_unlock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 725 | if (ret) { |
| 726 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); |
Chris Wright | 355d7f3 | 2009-04-17 01:18:55 +0000 | [diff] [blame] | 727 | goto fail_clip_free; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 728 | } |
| 729 | |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 730 | if (sarea_priv) |
Keith Packard | 0baf823 | 2008-11-08 11:44:14 +1000 | [diff] [blame] | 731 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 732 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 733 | fail_clip_free: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 734 | kfree(cliprects); |
Chris Wright | 355d7f3 | 2009-04-17 01:18:55 +0000 | [diff] [blame] | 735 | fail_batch_free: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 736 | kfree(batch_data); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 737 | |
| 738 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 739 | } |
| 740 | |
Daniel Vetter | 9488867 | 2012-04-26 23:28:08 +0200 | [diff] [blame] | 741 | static int i915_emit_irq(struct drm_device * dev) |
| 742 | { |
| 743 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 744 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
| 745 | |
| 746 | i915_kernel_lost_context(dev); |
| 747 | |
| 748 | DRM_DEBUG_DRIVER("\n"); |
| 749 | |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 750 | dev_priv->dri1.counter++; |
| 751 | if (dev_priv->dri1.counter > 0x7FFFFFFFUL) |
| 752 | dev_priv->dri1.counter = 1; |
Daniel Vetter | 9488867 | 2012-04-26 23:28:08 +0200 | [diff] [blame] | 753 | if (master_priv->sarea_priv) |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 754 | master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter; |
Daniel Vetter | 9488867 | 2012-04-26 23:28:08 +0200 | [diff] [blame] | 755 | |
| 756 | if (BEGIN_LP_RING(4) == 0) { |
| 757 | OUT_RING(MI_STORE_DWORD_INDEX); |
| 758 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 759 | OUT_RING(dev_priv->dri1.counter); |
Daniel Vetter | 9488867 | 2012-04-26 23:28:08 +0200 | [diff] [blame] | 760 | OUT_RING(MI_USER_INTERRUPT); |
| 761 | ADVANCE_LP_RING(); |
| 762 | } |
| 763 | |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 764 | return dev_priv->dri1.counter; |
Daniel Vetter | 9488867 | 2012-04-26 23:28:08 +0200 | [diff] [blame] | 765 | } |
| 766 | |
| 767 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
| 768 | { |
| 769 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 770 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
| 771 | int ret = 0; |
| 772 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
| 773 | |
| 774 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
| 775 | READ_BREADCRUMB(dev_priv)); |
| 776 | |
| 777 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
| 778 | if (master_priv->sarea_priv) |
| 779 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
| 780 | return 0; |
| 781 | } |
| 782 | |
| 783 | if (master_priv->sarea_priv) |
| 784 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
| 785 | |
| 786 | if (ring->irq_get(ring)) { |
| 787 | DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ, |
| 788 | READ_BREADCRUMB(dev_priv) >= irq_nr); |
| 789 | ring->irq_put(ring); |
| 790 | } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) |
| 791 | ret = -EBUSY; |
| 792 | |
| 793 | if (ret == -EBUSY) { |
| 794 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 795 | READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter); |
Daniel Vetter | 9488867 | 2012-04-26 23:28:08 +0200 | [diff] [blame] | 796 | } |
| 797 | |
| 798 | return ret; |
| 799 | } |
| 800 | |
| 801 | /* Needs the lock as it touches the ring. |
| 802 | */ |
| 803 | static int i915_irq_emit(struct drm_device *dev, void *data, |
| 804 | struct drm_file *file_priv) |
| 805 | { |
| 806 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 807 | drm_i915_irq_emit_t *emit = data; |
| 808 | int result; |
| 809 | |
| 810 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 811 | return -ENODEV; |
| 812 | |
| 813 | if (!dev_priv || !LP_RING(dev_priv)->virtual_start) { |
| 814 | DRM_ERROR("called with no initialization\n"); |
| 815 | return -EINVAL; |
| 816 | } |
| 817 | |
| 818 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
| 819 | |
| 820 | mutex_lock(&dev->struct_mutex); |
| 821 | result = i915_emit_irq(dev); |
| 822 | mutex_unlock(&dev->struct_mutex); |
| 823 | |
| 824 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
| 825 | DRM_ERROR("copy_to_user\n"); |
| 826 | return -EFAULT; |
| 827 | } |
| 828 | |
| 829 | return 0; |
| 830 | } |
| 831 | |
| 832 | /* Doesn't need the hardware lock. |
| 833 | */ |
| 834 | static int i915_irq_wait(struct drm_device *dev, void *data, |
| 835 | struct drm_file *file_priv) |
| 836 | { |
| 837 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 838 | drm_i915_irq_wait_t *irqwait = data; |
| 839 | |
| 840 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 841 | return -ENODEV; |
| 842 | |
| 843 | if (!dev_priv) { |
| 844 | DRM_ERROR("called with no initialization\n"); |
| 845 | return -EINVAL; |
| 846 | } |
| 847 | |
| 848 | return i915_wait_irq(dev, irqwait->irq_seq); |
| 849 | } |
| 850 | |
Daniel Vetter | d1c1edb | 2012-04-26 23:28:01 +0200 | [diff] [blame] | 851 | static int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
| 852 | struct drm_file *file_priv) |
| 853 | { |
| 854 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 855 | drm_i915_vblank_pipe_t *pipe = data; |
| 856 | |
| 857 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 858 | return -ENODEV; |
| 859 | |
| 860 | if (!dev_priv) { |
| 861 | DRM_ERROR("called with no initialization\n"); |
| 862 | return -EINVAL; |
| 863 | } |
| 864 | |
| 865 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
| 866 | |
| 867 | return 0; |
| 868 | } |
| 869 | |
| 870 | /** |
| 871 | * Schedule buffer swap at given vertical blank. |
| 872 | */ |
| 873 | static int i915_vblank_swap(struct drm_device *dev, void *data, |
| 874 | struct drm_file *file_priv) |
| 875 | { |
| 876 | /* The delayed swap mechanism was fundamentally racy, and has been |
| 877 | * removed. The model was that the client requested a delayed flip/swap |
| 878 | * from the kernel, then waited for vblank before continuing to perform |
| 879 | * rendering. The problem was that the kernel might wake the client |
| 880 | * up before it dispatched the vblank swap (since the lock has to be |
| 881 | * held while touching the ringbuffer), in which case the client would |
| 882 | * clear and start the next frame before the swap occurred, and |
| 883 | * flicker would occur in addition to likely missing the vblank. |
| 884 | * |
| 885 | * In the absence of this ioctl, userland falls back to a correct path |
| 886 | * of waiting for a vblank, then dispatching the swap on its own. |
| 887 | * Context switching to userland and back is plenty fast enough for |
| 888 | * meeting the requirements of vblank swapping. |
| 889 | */ |
| 890 | return -EINVAL; |
| 891 | } |
| 892 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 893 | static int i915_flip_bufs(struct drm_device *dev, void *data, |
| 894 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 895 | { |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 896 | int ret; |
| 897 | |
Daniel Vetter | cd9d4e9 | 2012-04-24 08:29:42 +0200 | [diff] [blame] | 898 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 899 | return -ENODEV; |
| 900 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 901 | DRM_DEBUG_DRIVER("%s\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 902 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 903 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 904 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 905 | mutex_lock(&dev->struct_mutex); |
| 906 | ret = i915_dispatch_flip(dev); |
| 907 | mutex_unlock(&dev->struct_mutex); |
| 908 | |
| 909 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 910 | } |
| 911 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 912 | static int i915_getparam(struct drm_device *dev, void *data, |
| 913 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 914 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 915 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 916 | drm_i915_getparam_t *param = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 917 | int value; |
| 918 | |
| 919 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 920 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 921 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 922 | } |
| 923 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 924 | switch (param->param) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 925 | case I915_PARAM_IRQ_ACTIVE: |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 926 | value = dev->pdev->irq ? 1 : 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 927 | break; |
| 928 | case I915_PARAM_ALLOW_BATCHBUFFER: |
Daniel Vetter | 8781342 | 2012-05-02 11:49:32 +0200 | [diff] [blame] | 929 | value = dev_priv->dri1.allow_batchbuffer ? 1 : 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 930 | break; |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 931 | case I915_PARAM_LAST_DISPATCH: |
| 932 | value = READ_BREADCRUMB(dev_priv); |
| 933 | break; |
Kristian Høgsberg | ed4c9c4 | 2008-08-20 11:08:52 -0400 | [diff] [blame] | 934 | case I915_PARAM_CHIPSET_ID: |
| 935 | value = dev->pci_device; |
| 936 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 937 | case I915_PARAM_HAS_GEM: |
Daniel Vetter | 2e895b1 | 2012-04-23 16:50:51 +0200 | [diff] [blame] | 938 | value = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 939 | break; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 940 | case I915_PARAM_NUM_FENCES_AVAIL: |
| 941 | value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; |
| 942 | break; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 943 | case I915_PARAM_HAS_OVERLAY: |
| 944 | value = dev_priv->overlay ? 1 : 0; |
| 945 | break; |
Jesse Barnes | e9560f7 | 2009-11-19 10:49:07 -0800 | [diff] [blame] | 946 | case I915_PARAM_HAS_PAGEFLIPPING: |
| 947 | value = 1; |
| 948 | break; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 949 | case I915_PARAM_HAS_EXECBUF2: |
| 950 | /* depends on GEM */ |
Daniel Vetter | 2e895b1 | 2012-04-23 16:50:51 +0200 | [diff] [blame] | 951 | value = 1; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 952 | break; |
Zou Nan hai | e3a815f | 2010-05-31 13:58:47 +0800 | [diff] [blame] | 953 | case I915_PARAM_HAS_BSD: |
Chris Wilson | edc912f | 2012-05-11 14:29:32 +0100 | [diff] [blame] | 954 | value = intel_ring_initialized(&dev_priv->ring[VCS]); |
Zou Nan hai | e3a815f | 2010-05-31 13:58:47 +0800 | [diff] [blame] | 955 | break; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 956 | case I915_PARAM_HAS_BLT: |
Chris Wilson | edc912f | 2012-05-11 14:29:32 +0100 | [diff] [blame] | 957 | value = intel_ring_initialized(&dev_priv->ring[BCS]); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 958 | break; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 959 | case I915_PARAM_HAS_RELAXED_FENCING: |
| 960 | value = 1; |
| 961 | break; |
Daniel Vetter | bbf0c6b | 2010-12-05 11:30:40 +0100 | [diff] [blame] | 962 | case I915_PARAM_HAS_COHERENT_RINGS: |
| 963 | value = 1; |
| 964 | break; |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 965 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
| 966 | value = INTEL_INFO(dev)->gen >= 4; |
| 967 | break; |
Chris Wilson | 271d81b | 2011-03-01 15:24:41 +0000 | [diff] [blame] | 968 | case I915_PARAM_HAS_RELAXED_DELTA: |
| 969 | value = 1; |
| 970 | break; |
Eric Anholt | ae662d3 | 2012-01-03 09:23:29 -0800 | [diff] [blame] | 971 | case I915_PARAM_HAS_GEN7_SOL_RESET: |
| 972 | value = 1; |
| 973 | break; |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 974 | case I915_PARAM_HAS_LLC: |
| 975 | value = HAS_LLC(dev); |
| 976 | break; |
Daniel Vetter | 777ee96 | 2012-02-15 23:50:25 +0100 | [diff] [blame] | 977 | case I915_PARAM_HAS_ALIASING_PPGTT: |
| 978 | value = dev_priv->mm.aliasing_ppgtt ? 1 : 0; |
| 979 | break; |
Ben Widawsky | 172cf15 | 2012-06-05 15:24:25 -0700 | [diff] [blame] | 980 | case I915_PARAM_HAS_WAIT_TIMEOUT: |
| 981 | value = 1; |
| 982 | break; |
Chris Wilson | 2fedbff | 2012-08-08 10:23:22 +0100 | [diff] [blame] | 983 | case I915_PARAM_HAS_SEMAPHORES: |
| 984 | value = i915_semaphore_is_enabled(dev); |
| 985 | break; |
Dave Airlie | ec6f1bb | 2012-08-16 10:15:34 +1000 | [diff] [blame] | 986 | case I915_PARAM_HAS_PRIME_VMAP_FLUSH: |
| 987 | value = 1; |
| 988 | break; |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 989 | case I915_PARAM_HAS_SECURE_BATCHES: |
| 990 | value = capable(CAP_SYS_ADMIN); |
| 991 | break; |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame^] | 992 | case I915_PARAM_HAS_PINNED_BATCHES: |
| 993 | value = 1; |
| 994 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 995 | default: |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 996 | DRM_DEBUG_DRIVER("Unknown parameter %d\n", |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 997 | param->param); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 998 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 999 | } |
| 1000 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1001 | if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1002 | DRM_ERROR("DRM_COPY_TO_USER failed\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1003 | return -EFAULT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1004 | } |
| 1005 | |
| 1006 | return 0; |
| 1007 | } |
| 1008 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1009 | static int i915_setparam(struct drm_device *dev, void *data, |
| 1010 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1011 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1012 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1013 | drm_i915_setparam_t *param = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1014 | |
| 1015 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1016 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1017 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1018 | } |
| 1019 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1020 | switch (param->param) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1021 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1022 | break; |
| 1023 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1024 | break; |
| 1025 | case I915_SETPARAM_ALLOW_BATCHBUFFER: |
Daniel Vetter | 8781342 | 2012-05-02 11:49:32 +0200 | [diff] [blame] | 1026 | dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1027 | break; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1028 | case I915_SETPARAM_NUM_USED_FENCES: |
| 1029 | if (param->value > dev_priv->num_fence_regs || |
| 1030 | param->value < 0) |
| 1031 | return -EINVAL; |
| 1032 | /* Userspace can use first N regs */ |
| 1033 | dev_priv->fence_reg_start = param->value; |
| 1034 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1035 | default: |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 1036 | DRM_DEBUG_DRIVER("unknown parameter %d\n", |
yakui_zhao | be25ed9 | 2009-06-02 14:13:55 +0800 | [diff] [blame] | 1037 | param->param); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1038 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1039 | } |
| 1040 | |
| 1041 | return 0; |
| 1042 | } |
| 1043 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1044 | static int i915_set_status_page(struct drm_device *dev, void *data, |
| 1045 | struct drm_file *file_priv) |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1046 | { |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1047 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1048 | drm_i915_hws_addr_t *hws = data; |
Mika Kuoppala | 4f1ba0f | 2012-11-12 14:20:19 +0200 | [diff] [blame] | 1049 | struct intel_ring_buffer *ring; |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1050 | |
Daniel Vetter | cd9d4e9 | 2012-04-24 08:29:42 +0200 | [diff] [blame] | 1051 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 1052 | return -ENODEV; |
| 1053 | |
Zhenyu Wang | b39d50e | 2008-02-19 20:59:09 +1000 | [diff] [blame] | 1054 | if (!I915_NEED_GFX_HWS(dev)) |
| 1055 | return -EINVAL; |
| 1056 | |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1057 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 1058 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1059 | return -EINVAL; |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1060 | } |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1061 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1062 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 1063 | WARN(1, "tried to set status page when mode setting active\n"); |
| 1064 | return 0; |
| 1065 | } |
| 1066 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 1067 | DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1068 | |
Mika Kuoppala | 4f1ba0f | 2012-11-12 14:20:19 +0200 | [diff] [blame] | 1069 | ring = LP_RING(dev_priv); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1070 | ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12); |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1071 | |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1072 | dev_priv->dri1.gfx_hws_cpu_addr = |
| 1073 | ioremap_wc(dev_priv->mm.gtt_base_addr + hws->addr, 4096); |
Daniel Vetter | 316d388 | 2012-04-26 23:28:15 +0200 | [diff] [blame] | 1074 | if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) { |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1075 | i915_dma_cleanup(dev); |
Eric Anholt | e20f9c6 | 2010-05-26 14:51:06 -0700 | [diff] [blame] | 1076 | ring->status_page.gfx_addr = 0; |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1077 | DRM_ERROR("can not ioremap virtual address for" |
| 1078 | " G33 hw status page\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 1079 | return -ENOMEM; |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1080 | } |
Daniel Vetter | 316d388 | 2012-04-26 23:28:15 +0200 | [diff] [blame] | 1081 | |
| 1082 | memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1083 | I915_WRITE(HWS_PGA, ring->status_page.gfx_addr); |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1084 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 1085 | DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", |
Eric Anholt | e20f9c6 | 2010-05-26 14:51:06 -0700 | [diff] [blame] | 1086 | ring->status_page.gfx_addr); |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 1087 | DRM_DEBUG_DRIVER("load hws at %p\n", |
Eric Anholt | e20f9c6 | 2010-05-26 14:51:06 -0700 | [diff] [blame] | 1088 | ring->status_page.page_addr); |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 1089 | return 0; |
| 1090 | } |
| 1091 | |
Dave Airlie | ec2a4c3 | 2009-08-04 11:43:41 +1000 | [diff] [blame] | 1092 | static int i915_get_bridge_dev(struct drm_device *dev) |
| 1093 | { |
| 1094 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1095 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1096 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
Dave Airlie | ec2a4c3 | 2009-08-04 11:43:41 +1000 | [diff] [blame] | 1097 | if (!dev_priv->bridge_dev) { |
| 1098 | DRM_ERROR("bridge device not found\n"); |
| 1099 | return -1; |
| 1100 | } |
| 1101 | return 0; |
| 1102 | } |
| 1103 | |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1104 | #define MCHBAR_I915 0x44 |
| 1105 | #define MCHBAR_I965 0x48 |
| 1106 | #define MCHBAR_SIZE (4*4096) |
| 1107 | |
| 1108 | #define DEVEN_REG 0x54 |
| 1109 | #define DEVEN_MCHBAR_EN (1 << 28) |
| 1110 | |
| 1111 | /* Allocate space for the MCH regs if needed, return nonzero on error */ |
| 1112 | static int |
| 1113 | intel_alloc_mchbar_resource(struct drm_device *dev) |
| 1114 | { |
| 1115 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1116 | int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1117 | u32 temp_lo, temp_hi = 0; |
| 1118 | u64 mchbar_addr; |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 1119 | int ret; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1120 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1121 | if (INTEL_INFO(dev)->gen >= 4) |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1122 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
| 1123 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); |
| 1124 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; |
| 1125 | |
| 1126 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ |
| 1127 | #ifdef CONFIG_PNP |
| 1128 | if (mchbar_addr && |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 1129 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) |
| 1130 | return 0; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1131 | #endif |
| 1132 | |
| 1133 | /* Get some space for it */ |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 1134 | dev_priv->mch_res.name = "i915 MCHBAR"; |
| 1135 | dev_priv->mch_res.flags = IORESOURCE_MEM; |
| 1136 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, |
| 1137 | &dev_priv->mch_res, |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1138 | MCHBAR_SIZE, MCHBAR_SIZE, |
| 1139 | PCIBIOS_MIN_MEM, |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 1140 | 0, pcibios_align_resource, |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1141 | dev_priv->bridge_dev); |
| 1142 | if (ret) { |
| 1143 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); |
| 1144 | dev_priv->mch_res.start = 0; |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 1145 | return ret; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1146 | } |
| 1147 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1148 | if (INTEL_INFO(dev)->gen >= 4) |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1149 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
| 1150 | upper_32_bits(dev_priv->mch_res.start)); |
| 1151 | |
| 1152 | pci_write_config_dword(dev_priv->bridge_dev, reg, |
| 1153 | lower_32_bits(dev_priv->mch_res.start)); |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 1154 | return 0; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1155 | } |
| 1156 | |
| 1157 | /* Setup MCHBAR if possible, return true if we should disable it again */ |
| 1158 | static void |
| 1159 | intel_setup_mchbar(struct drm_device *dev) |
| 1160 | { |
| 1161 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1162 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1163 | u32 temp; |
| 1164 | bool enabled; |
| 1165 | |
| 1166 | dev_priv->mchbar_need_disable = false; |
| 1167 | |
| 1168 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
| 1169 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); |
| 1170 | enabled = !!(temp & DEVEN_MCHBAR_EN); |
| 1171 | } else { |
| 1172 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); |
| 1173 | enabled = temp & 1; |
| 1174 | } |
| 1175 | |
| 1176 | /* If it's already enabled, don't have to do anything */ |
| 1177 | if (enabled) |
| 1178 | return; |
| 1179 | |
| 1180 | if (intel_alloc_mchbar_resource(dev)) |
| 1181 | return; |
| 1182 | |
| 1183 | dev_priv->mchbar_need_disable = true; |
| 1184 | |
| 1185 | /* Space is allocated or reserved, so enable it. */ |
| 1186 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
| 1187 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, |
| 1188 | temp | DEVEN_MCHBAR_EN); |
| 1189 | } else { |
| 1190 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); |
| 1191 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); |
| 1192 | } |
| 1193 | } |
| 1194 | |
| 1195 | static void |
| 1196 | intel_teardown_mchbar(struct drm_device *dev) |
| 1197 | { |
| 1198 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1199 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1200 | u32 temp; |
| 1201 | |
| 1202 | if (dev_priv->mchbar_need_disable) { |
| 1203 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
| 1204 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); |
| 1205 | temp &= ~DEVEN_MCHBAR_EN; |
| 1206 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); |
| 1207 | } else { |
| 1208 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); |
| 1209 | temp &= ~1; |
| 1210 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); |
| 1211 | } |
| 1212 | } |
| 1213 | |
| 1214 | if (dev_priv->mch_res.start) |
| 1215 | release_resource(&dev_priv->mch_res); |
| 1216 | } |
| 1217 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1218 | /* true = enable decode, false = disable decoder */ |
| 1219 | static unsigned int i915_vga_set_decode(void *cookie, bool state) |
| 1220 | { |
| 1221 | struct drm_device *dev = cookie; |
| 1222 | |
| 1223 | intel_modeset_vga_set_state(dev, state); |
| 1224 | if (state) |
| 1225 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | |
| 1226 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
| 1227 | else |
| 1228 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
| 1229 | } |
| 1230 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1231 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
| 1232 | { |
| 1233 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 1234 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; |
| 1235 | if (state == VGA_SWITCHEROO_ON) { |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1236 | pr_info("switched on\n"); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 1237 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1238 | /* i915 resume handler doesn't set to D0 */ |
| 1239 | pci_set_power_state(dev->pdev, PCI_D0); |
| 1240 | i915_resume(dev); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 1241 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1242 | } else { |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1243 | pr_err("switched off\n"); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 1244 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1245 | i915_suspend(dev, pmm); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 1246 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1247 | } |
| 1248 | } |
| 1249 | |
| 1250 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) |
| 1251 | { |
| 1252 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 1253 | bool can_switch; |
| 1254 | |
| 1255 | spin_lock(&dev->count_lock); |
| 1256 | can_switch = (dev->open_count == 0); |
| 1257 | spin_unlock(&dev->count_lock); |
| 1258 | return can_switch; |
| 1259 | } |
| 1260 | |
Takashi Iwai | 26ec685 | 2012-05-11 07:51:17 +0200 | [diff] [blame] | 1261 | static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { |
| 1262 | .set_gpu_state = i915_switcheroo_set_state, |
| 1263 | .reprobe = NULL, |
| 1264 | .can_switch = i915_switcheroo_can_switch, |
| 1265 | }; |
| 1266 | |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 1267 | static int i915_load_modeset_init(struct drm_device *dev) |
| 1268 | { |
| 1269 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1270 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1271 | |
Bryan Freed | 6d139a8 | 2010-10-14 09:14:51 +0100 | [diff] [blame] | 1272 | ret = intel_parse_bios(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1273 | if (ret) |
| 1274 | DRM_INFO("failed to find VBIOS tables\n"); |
| 1275 | |
Chris Wilson | 934f992 | 2011-01-20 13:09:12 +0000 | [diff] [blame] | 1276 | /* If we have > 1 VGA cards, then we need to arbitrate access |
| 1277 | * to the common VGA resources. |
| 1278 | * |
| 1279 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), |
| 1280 | * then we do not take part in VGA arbitration and the |
| 1281 | * vga_client_register() fails with -ENODEV. |
| 1282 | */ |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1283 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); |
Chris Wilson | 934f992 | 2011-01-20 13:09:12 +0000 | [diff] [blame] | 1284 | if (ret && ret != -ENODEV) |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 1285 | goto out; |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1286 | |
Jesse Barnes | 723bfd7 | 2010-10-07 16:01:13 -0700 | [diff] [blame] | 1287 | intel_register_dsm_handler(); |
| 1288 | |
Takashi Iwai | 26ec685 | 2012-05-11 07:51:17 +0200 | [diff] [blame] | 1289 | ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1290 | if (ret) |
Chris Wilson | 5a79395 | 2010-06-06 10:50:03 +0100 | [diff] [blame] | 1291 | goto cleanup_vga_client; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1292 | |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 1293 | /* Initialise stolen first so that we may reserve preallocated |
| 1294 | * objects for the BIOS to KMS transition. |
| 1295 | */ |
| 1296 | ret = i915_gem_init_stolen(dev); |
| 1297 | if (ret) |
| 1298 | goto cleanup_vga_switcheroo; |
| 1299 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 1300 | intel_modeset_init(dev); |
| 1301 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 1302 | ret = i915_gem_init(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1303 | if (ret) |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 1304 | goto cleanup_gem_stolen; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1305 | |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 1306 | intel_modeset_gem_init(dev); |
| 1307 | |
Jesse Barnes | 073f34d | 2012-11-02 11:13:59 -0700 | [diff] [blame] | 1308 | INIT_WORK(&dev_priv->console_resume_work, intel_console_resume); |
| 1309 | |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 1310 | ret = drm_irq_install(dev); |
| 1311 | if (ret) |
| 1312 | goto cleanup_gem; |
| 1313 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1314 | /* Always safe in the mode setting case. */ |
| 1315 | /* FIXME: do pre/post-mode set stuff in core KMS code */ |
| 1316 | dev->vblank_disable_allowed = 1; |
| 1317 | |
Chris Wilson | 5a79395 | 2010-06-06 10:50:03 +0100 | [diff] [blame] | 1318 | ret = intel_fbdev_init(dev); |
| 1319 | if (ret) |
| 1320 | goto cleanup_irq; |
| 1321 | |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 1322 | drm_kms_helper_poll_init(dev); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 1323 | |
| 1324 | /* We're off and running w/KMS */ |
| 1325 | dev_priv->mm.suspended = 0; |
| 1326 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1327 | return 0; |
| 1328 | |
Chris Wilson | 5a79395 | 2010-06-06 10:50:03 +0100 | [diff] [blame] | 1329 | cleanup_irq: |
| 1330 | drm_irq_uninstall(dev); |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 1331 | cleanup_gem: |
| 1332 | mutex_lock(&dev->struct_mutex); |
| 1333 | i915_gem_cleanup_ringbuffer(dev); |
| 1334 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1335 | i915_gem_cleanup_aliasing_ppgtt(dev); |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 1336 | cleanup_gem_stolen: |
| 1337 | i915_gem_cleanup_stolen(dev); |
Chris Wilson | 5a79395 | 2010-06-06 10:50:03 +0100 | [diff] [blame] | 1338 | cleanup_vga_switcheroo: |
| 1339 | vga_switcheroo_unregister_client(dev->pdev); |
| 1340 | cleanup_vga_client: |
| 1341 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1342 | out: |
| 1343 | return ret; |
| 1344 | } |
| 1345 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1346 | int i915_master_create(struct drm_device *dev, struct drm_master *master) |
| 1347 | { |
| 1348 | struct drm_i915_master_private *master_priv; |
| 1349 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1350 | master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1351 | if (!master_priv) |
| 1352 | return -ENOMEM; |
| 1353 | |
| 1354 | master->driver_priv = master_priv; |
| 1355 | return 0; |
| 1356 | } |
| 1357 | |
| 1358 | void i915_master_destroy(struct drm_device *dev, struct drm_master *master) |
| 1359 | { |
| 1360 | struct drm_i915_master_private *master_priv = master->driver_priv; |
| 1361 | |
| 1362 | if (!master_priv) |
| 1363 | return; |
| 1364 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1365 | kfree(master_priv); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1366 | |
| 1367 | master->driver_priv = NULL; |
| 1368 | } |
| 1369 | |
Adam Jackson | e2b665c | 2012-03-14 11:22:10 -0400 | [diff] [blame] | 1370 | static void |
| 1371 | i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base, |
| 1372 | unsigned long size) |
| 1373 | { |
Chris Wilson | 23f54be | 2012-03-23 17:38:49 +0000 | [diff] [blame] | 1374 | dev_priv->mm.gtt_mtrr = -1; |
| 1375 | |
Adam Jackson | 9e984bc1 | 2012-03-14 11:22:11 -0400 | [diff] [blame] | 1376 | #if defined(CONFIG_X86_PAT) |
| 1377 | if (cpu_has_pat) |
| 1378 | return; |
| 1379 | #endif |
| 1380 | |
Adam Jackson | e2b665c | 2012-03-14 11:22:10 -0400 | [diff] [blame] | 1381 | /* Set up a WC MTRR for non-PAT systems. This is more common than |
| 1382 | * one would think, because the kernel disables PAT on first |
| 1383 | * generation Core chips because WC PAT gets overridden by a UC |
| 1384 | * MTRR if present. Even if a UC MTRR isn't present. |
| 1385 | */ |
| 1386 | dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1); |
| 1387 | if (dev_priv->mm.gtt_mtrr < 0) { |
| 1388 | DRM_INFO("MTRR allocation failed. Graphics " |
| 1389 | "performance may suffer.\n"); |
| 1390 | } |
| 1391 | } |
| 1392 | |
Daniel Vetter | e188719 | 2012-06-12 11:28:17 +0200 | [diff] [blame] | 1393 | static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
| 1394 | { |
| 1395 | struct apertures_struct *ap; |
| 1396 | struct pci_dev *pdev = dev_priv->dev->pdev; |
| 1397 | bool primary; |
| 1398 | |
| 1399 | ap = alloc_apertures(1); |
| 1400 | if (!ap) |
| 1401 | return; |
| 1402 | |
Daniel Vetter | 87207ca | 2012-06-24 20:51:36 +0200 | [diff] [blame] | 1403 | ap->ranges[0].base = dev_priv->mm.gtt->gma_bus_addr; |
Daniel Vetter | e188719 | 2012-06-12 11:28:17 +0200 | [diff] [blame] | 1404 | ap->ranges[0].size = |
| 1405 | dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; |
| 1406 | primary = |
| 1407 | pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; |
| 1408 | |
| 1409 | remove_conflicting_framebuffers(ap, "inteldrmfb", primary); |
| 1410 | |
| 1411 | kfree(ap); |
| 1412 | } |
| 1413 | |
Daniel Vetter | c96ea64 | 2012-08-08 22:01:51 +0200 | [diff] [blame] | 1414 | static void i915_dump_device_info(struct drm_i915_private *dev_priv) |
| 1415 | { |
| 1416 | const struct intel_device_info *info = dev_priv->info; |
| 1417 | |
| 1418 | #define DEV_INFO_FLAG(name) info->name ? #name "," : "" |
| 1419 | #define DEV_INFO_SEP , |
| 1420 | DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags=" |
| 1421 | "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
| 1422 | info->gen, |
| 1423 | dev_priv->dev->pdev->device, |
| 1424 | DEV_INFO_FLAGS); |
| 1425 | #undef DEV_INFO_FLAG |
| 1426 | #undef DEV_INFO_SEP |
| 1427 | } |
| 1428 | |
Eric Anholt | 63ee41d | 2010-12-20 18:40:06 -0800 | [diff] [blame] | 1429 | /** |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1430 | * i915_driver_load - setup chip and create an initial config |
| 1431 | * @dev: DRM device |
| 1432 | * @flags: startup flags |
| 1433 | * |
| 1434 | * The driver load routine has to do several things: |
| 1435 | * - drive output discovery via intel_modeset_init() |
| 1436 | * - initialize the memory manager |
| 1437 | * - allocate initial config memory |
| 1438 | * - setup the DRM framebuffer with the allocated memory |
| 1439 | */ |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1440 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 1441 | { |
Luca Tettamanti | ea059a1 | 2010-04-08 21:41:59 +0200 | [diff] [blame] | 1442 | struct drm_i915_private *dev_priv; |
Daniel Vetter | 26394d9 | 2012-03-26 21:33:18 +0200 | [diff] [blame] | 1443 | struct intel_device_info *info; |
Chris Wilson | 934d608 | 2012-09-14 11:57:46 +0100 | [diff] [blame] | 1444 | int ret = 0, mmio_bar, mmio_size; |
Daniel Vetter | 9021f28 | 2012-03-26 09:45:41 +0200 | [diff] [blame] | 1445 | uint32_t aperture_size; |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1446 | |
Daniel Vetter | 26394d9 | 2012-03-26 21:33:18 +0200 | [diff] [blame] | 1447 | info = (struct intel_device_info *) flags; |
| 1448 | |
| 1449 | /* Refuse to load on gen6+ without kms enabled. */ |
| 1450 | if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) |
| 1451 | return -ENODEV; |
| 1452 | |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 1453 | /* i915 has 4 more counters */ |
| 1454 | dev->counters += 4; |
| 1455 | dev->types[6] = _DRM_STAT_IRQ; |
| 1456 | dev->types[7] = _DRM_STAT_PRIMARY; |
| 1457 | dev->types[8] = _DRM_STAT_SECONDARY; |
| 1458 | dev->types[9] = _DRM_STAT_DMA; |
| 1459 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1460 | dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1461 | if (dev_priv == NULL) |
| 1462 | return -ENOMEM; |
| 1463 | |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1464 | dev->dev_private = (void *)dev_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1465 | dev_priv->dev = dev; |
Daniel Vetter | 26394d9 | 2012-03-26 21:33:18 +0200 | [diff] [blame] | 1466 | dev_priv->info = info; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1467 | |
Daniel Vetter | c96ea64 | 2012-08-08 22:01:51 +0200 | [diff] [blame] | 1468 | i915_dump_device_info(dev_priv); |
| 1469 | |
Dave Airlie | ec2a4c3 | 2009-08-04 11:43:41 +1000 | [diff] [blame] | 1470 | if (i915_get_bridge_dev(dev)) { |
| 1471 | ret = -EIO; |
| 1472 | goto free_priv; |
| 1473 | } |
| 1474 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1475 | ret = i915_gem_gtt_init(dev); |
| 1476 | if (ret) |
Daniel Vetter | e188719 | 2012-06-12 11:28:17 +0200 | [diff] [blame] | 1477 | goto put_bridge; |
Daniel Vetter | e188719 | 2012-06-12 11:28:17 +0200 | [diff] [blame] | 1478 | |
Chris Wilson | 1623392 | 2012-10-26 12:06:41 +0100 | [diff] [blame] | 1479 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 1480 | i915_kick_out_firmware_fb(dev_priv); |
Daniel Vetter | e188719 | 2012-06-12 11:28:17 +0200 | [diff] [blame] | 1481 | |
Dave Airlie | 466e69b | 2011-12-19 11:15:29 +0000 | [diff] [blame] | 1482 | pci_set_master(dev->pdev); |
| 1483 | |
Daniel Vetter | 9f82d23 | 2010-08-30 21:25:23 +0200 | [diff] [blame] | 1484 | /* overlay on gen2 is broken and can't address above 1G */ |
| 1485 | if (IS_GEN2(dev)) |
| 1486 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); |
| 1487 | |
Jan Niehusmann | 6927faf | 2011-03-01 23:24:16 +0100 | [diff] [blame] | 1488 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
| 1489 | * using 32bit addressing, overwriting memory if HWS is located |
| 1490 | * above 4GB. |
| 1491 | * |
| 1492 | * The documentation also mentions an issue with undefined |
| 1493 | * behaviour if any general state is accessed within a page above 4GB, |
| 1494 | * which also needs to be handled carefully. |
| 1495 | */ |
| 1496 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
| 1497 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); |
| 1498 | |
Chris Wilson | b4ce0f8 | 2010-10-28 11:26:06 +0100 | [diff] [blame] | 1499 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
Chris Wilson | 934d608 | 2012-09-14 11:57:46 +0100 | [diff] [blame] | 1500 | /* Before gen4, the registers and the GTT are behind different BARs. |
| 1501 | * However, from gen4 onwards, the registers and the GTT are shared |
| 1502 | * in the same BAR, so we want to restrict this ioremap from |
| 1503 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, |
| 1504 | * the register BAR remains the same size for all the earlier |
| 1505 | * generations up to Ironlake. |
| 1506 | */ |
| 1507 | if (info->gen < 5) |
| 1508 | mmio_size = 512*1024; |
| 1509 | else |
| 1510 | mmio_size = 2*1024*1024; |
| 1511 | |
| 1512 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size); |
Chris Wilson | b4ce0f8 | 2010-10-28 11:26:06 +0100 | [diff] [blame] | 1513 | if (!dev_priv->regs) { |
| 1514 | DRM_ERROR("failed to map registers\n"); |
| 1515 | ret = -EIO; |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1516 | goto put_gmch; |
Chris Wilson | 71e9339 | 2010-10-27 18:46:52 +0100 | [diff] [blame] | 1517 | } |
| 1518 | |
Daniel Vetter | 9021f28 | 2012-03-26 09:45:41 +0200 | [diff] [blame] | 1519 | aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1520 | dev_priv->mm.gtt_base_addr = dev_priv->mm.gtt->gma_bus_addr; |
Chris Wilson | 71e9339 | 2010-10-27 18:46:52 +0100 | [diff] [blame] | 1521 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1522 | dev_priv->mm.gtt_mapping = |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1523 | io_mapping_create_wc(dev_priv->mm.gtt_base_addr, |
| 1524 | aperture_size); |
Venkatesh Pallipadi | 6644107 | 2009-02-24 17:35:11 -0800 | [diff] [blame] | 1525 | if (dev_priv->mm.gtt_mapping == NULL) { |
| 1526 | ret = -EIO; |
Daniel Vetter | e188719 | 2012-06-12 11:28:17 +0200 | [diff] [blame] | 1527 | goto out_rmmap; |
Venkatesh Pallipadi | 6644107 | 2009-02-24 17:35:11 -0800 | [diff] [blame] | 1528 | } |
| 1529 | |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1530 | i915_mtrr_setup(dev_priv, dev_priv->mm.gtt_base_addr, |
| 1531 | aperture_size); |
Eric Anholt | ab657db1 | 2009-01-23 12:57:47 -0800 | [diff] [blame] | 1532 | |
Chris Wilson | e642abb | 2010-09-09 12:46:34 +0100 | [diff] [blame] | 1533 | /* The i915 workqueue is primarily used for batched retirement of |
| 1534 | * requests (and thus managing bo) once the task has been completed |
| 1535 | * by the GPU. i915_gem_retire_requests() is called directly when we |
| 1536 | * need high-priority retirement, such as waiting for an explicit |
| 1537 | * bo. |
| 1538 | * |
| 1539 | * It is also used for periodic low-priority events, such as |
Eric Anholt | df9c204 | 2010-11-18 09:31:12 +0800 | [diff] [blame] | 1540 | * idle-timers and recording error state. |
Chris Wilson | e642abb | 2010-09-09 12:46:34 +0100 | [diff] [blame] | 1541 | * |
| 1542 | * All tasks on the workqueue are expected to acquire the dev mutex |
| 1543 | * so there is no point in running more than one instance of the |
Tejun Heo | 5362186 | 2012-08-22 16:40:57 -0700 | [diff] [blame] | 1544 | * workqueue at any time. Use an ordered one. |
Chris Wilson | e642abb | 2010-09-09 12:46:34 +0100 | [diff] [blame] | 1545 | */ |
Tejun Heo | 5362186 | 2012-08-22 16:40:57 -0700 | [diff] [blame] | 1546 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1547 | if (dev_priv->wq == NULL) { |
| 1548 | DRM_ERROR("Failed to create our workqueue.\n"); |
| 1549 | ret = -ENOMEM; |
Keith Packard | a7b85d2 | 2011-07-10 13:12:17 -0700 | [diff] [blame] | 1550 | goto out_mtrrfree; |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1551 | } |
| 1552 | |
Paulo Zanoni | 45e6e3a | 2012-07-03 15:57:32 -0300 | [diff] [blame] | 1553 | /* This must be called before any calls to HAS_PCH_* */ |
| 1554 | intel_detect_pch(dev); |
| 1555 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1556 | intel_irq_init(dev); |
Chris Wilson | 990bbda | 2012-07-02 11:51:02 -0300 | [diff] [blame] | 1557 | intel_gt_init(dev); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 1558 | |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1559 | /* Try to make sure MCHBAR is enabled before poking at it */ |
| 1560 | intel_setup_mchbar(dev); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1561 | intel_setup_gmbus(dev); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1562 | intel_opregion_setup(dev); |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1563 | |
Bryan Freed | 6d139a8 | 2010-10-14 09:14:51 +0100 | [diff] [blame] | 1564 | intel_setup_bios(dev); |
| 1565 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1566 | i915_gem_load(dev); |
| 1567 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1568 | /* On the 945G/GM, the chipset reports the MSI capability on the |
| 1569 | * integrated graphics even though the support isn't actually there |
| 1570 | * according to the published specs. It doesn't appear to function |
| 1571 | * correctly in testing on 945G. |
| 1572 | * This may be a side effect of MSI having been made available for PEG |
| 1573 | * and the registers being closely associated. |
Keith Packard | d1ed629 | 2008-10-17 00:44:42 -0700 | [diff] [blame] | 1574 | * |
| 1575 | * According to chipset errata, on the 965GM, MSI interrupts may |
Keith Packard | b60678a | 2008-12-08 11:12:28 -0800 | [diff] [blame] | 1576 | * be lost or delayed, but we use them anyways to avoid |
| 1577 | * stuck interrupts on some machines. |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1578 | */ |
Keith Packard | b60678a | 2008-12-08 11:12:28 -0800 | [diff] [blame] | 1579 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
Eric Anholt | d3e74d0 | 2008-11-03 14:46:17 -0800 | [diff] [blame] | 1580 | pci_enable_msi(dev->pdev); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1581 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1582 | spin_lock_init(&dev_priv->irq_lock); |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 1583 | spin_lock_init(&dev_priv->error_lock); |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 1584 | spin_lock_init(&dev_priv->rps.lock); |
Alexander Shishkin | 99d0b1d | 2012-08-31 15:50:55 +0300 | [diff] [blame] | 1585 | spin_lock_init(&dev_priv->dpio_lock); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1586 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1587 | mutex_init(&dev_priv->rps.hw_lock); |
| 1588 | |
Eugeni Dodonov | c51ed78 | 2012-04-13 17:08:45 -0300 | [diff] [blame] | 1589 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
Jesse Barnes | 27f8227 | 2011-09-02 12:54:37 -0700 | [diff] [blame] | 1590 | dev_priv->num_pipe = 3; |
| 1591 | else if (IS_MOBILE(dev) || !IS_GEN2(dev)) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1592 | dev_priv->num_pipe = 2; |
| 1593 | else |
| 1594 | dev_priv->num_pipe = 1; |
| 1595 | |
| 1596 | ret = drm_vblank_init(dev, dev_priv->num_pipe); |
Chris Wilson | 56e2ea3 | 2010-11-08 17:10:29 +0000 | [diff] [blame] | 1597 | if (ret) |
| 1598 | goto out_gem_unload; |
Keith Packard | 5244021 | 2008-11-18 09:30:25 -0800 | [diff] [blame] | 1599 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 1600 | /* Start out suspended */ |
| 1601 | dev_priv->mm.suspended = 1; |
| 1602 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1603 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
Daniel Vetter | 5398463 | 2010-09-22 23:44:24 +0200 | [diff] [blame] | 1604 | ret = i915_load_modeset_init(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1605 | if (ret < 0) { |
| 1606 | DRM_ERROR("failed to init modeset\n"); |
Chris Wilson | 56e2ea3 | 2010-11-08 17:10:29 +0000 | [diff] [blame] | 1607 | goto out_gem_unload; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1608 | } |
| 1609 | } |
| 1610 | |
Ben Widawsky | 0136db58 | 2012-04-10 21:17:01 -0700 | [diff] [blame] | 1611 | i915_setup_sysfs(dev); |
| 1612 | |
Matthew Garrett | 74a365b | 2009-03-19 21:35:39 +0000 | [diff] [blame] | 1613 | /* Must be done after probing outputs */ |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1614 | intel_opregion_init(dev); |
| 1615 | acpi_video_register(); |
Matthew Garrett | 74a365b | 2009-03-19 21:35:39 +0000 | [diff] [blame] | 1616 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1617 | setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, |
| 1618 | (unsigned long) dev); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1619 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 1620 | if (IS_GEN5(dev)) |
| 1621 | intel_gpu_ips_init(dev_priv); |
Eric Anholt | 63ee41d | 2010-12-20 18:40:06 -0800 | [diff] [blame] | 1622 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1623 | return 0; |
| 1624 | |
Chris Wilson | 56e2ea3 | 2010-11-08 17:10:29 +0000 | [diff] [blame] | 1625 | out_gem_unload: |
Keith Packard | a7b85d2 | 2011-07-10 13:12:17 -0700 | [diff] [blame] | 1626 | if (dev_priv->mm.inactive_shrinker.shrink) |
| 1627 | unregister_shrinker(&dev_priv->mm.inactive_shrinker); |
| 1628 | |
Chris Wilson | 56e2ea3 | 2010-11-08 17:10:29 +0000 | [diff] [blame] | 1629 | if (dev->pdev->msi_enabled) |
| 1630 | pci_disable_msi(dev->pdev); |
| 1631 | |
| 1632 | intel_teardown_gmbus(dev); |
| 1633 | intel_teardown_mchbar(dev); |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1634 | destroy_workqueue(dev_priv->wq); |
Keith Packard | a7b85d2 | 2011-07-10 13:12:17 -0700 | [diff] [blame] | 1635 | out_mtrrfree: |
| 1636 | if (dev_priv->mm.gtt_mtrr >= 0) { |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1637 | mtrr_del(dev_priv->mm.gtt_mtrr, |
| 1638 | dev_priv->mm.gtt_base_addr, |
| 1639 | aperture_size); |
Keith Packard | a7b85d2 | 2011-07-10 13:12:17 -0700 | [diff] [blame] | 1640 | dev_priv->mm.gtt_mtrr = -1; |
| 1641 | } |
Venkatesh Pallipadi | 6644107 | 2009-02-24 17:35:11 -0800 | [diff] [blame] | 1642 | io_mapping_free(dev_priv->mm.gtt_mapping); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1643 | out_rmmap: |
Chris Wilson | 6dda569 | 2010-10-29 21:02:18 +0100 | [diff] [blame] | 1644 | pci_iounmap(dev->pdev, dev_priv->regs); |
Daniel Vetter | e188719 | 2012-06-12 11:28:17 +0200 | [diff] [blame] | 1645 | put_gmch: |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1646 | i915_gem_gtt_fini(dev); |
Dave Airlie | ec2a4c3 | 2009-08-04 11:43:41 +1000 | [diff] [blame] | 1647 | put_bridge: |
| 1648 | pci_dev_put(dev_priv->bridge_dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1649 | free_priv: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1650 | kfree(dev_priv); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1651 | return ret; |
| 1652 | } |
| 1653 | |
| 1654 | int i915_driver_unload(struct drm_device *dev) |
| 1655 | { |
| 1656 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c911fc1 | 2010-08-20 21:23:20 +0200 | [diff] [blame] | 1657 | int ret; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1658 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 1659 | intel_gpu_ips_teardown(); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1660 | |
Ben Widawsky | 0136db58 | 2012-04-10 21:17:01 -0700 | [diff] [blame] | 1661 | i915_teardown_sysfs(dev); |
| 1662 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 1663 | if (dev_priv->mm.inactive_shrinker.shrink) |
| 1664 | unregister_shrinker(&dev_priv->mm.inactive_shrinker); |
| 1665 | |
Daniel Vetter | c911fc1 | 2010-08-20 21:23:20 +0200 | [diff] [blame] | 1666 | mutex_lock(&dev->struct_mutex); |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 1667 | ret = i915_gpu_idle(dev); |
Daniel Vetter | c911fc1 | 2010-08-20 21:23:20 +0200 | [diff] [blame] | 1668 | if (ret) |
| 1669 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 1670 | i915_gem_retire_requests(dev); |
Daniel Vetter | c911fc1 | 2010-08-20 21:23:20 +0200 | [diff] [blame] | 1671 | mutex_unlock(&dev->struct_mutex); |
| 1672 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 1673 | /* Cancel the retire work handler, which should be idle now. */ |
| 1674 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 1675 | |
Eric Anholt | ab657db1 | 2009-01-23 12:57:47 -0800 | [diff] [blame] | 1676 | io_mapping_free(dev_priv->mm.gtt_mapping); |
| 1677 | if (dev_priv->mm.gtt_mtrr >= 0) { |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1678 | mtrr_del(dev_priv->mm.gtt_mtrr, |
| 1679 | dev_priv->mm.gtt_base_addr, |
| 1680 | dev_priv->mm.gtt->gtt_mappable_entries * PAGE_SIZE); |
Eric Anholt | ab657db1 | 2009-01-23 12:57:47 -0800 | [diff] [blame] | 1681 | dev_priv->mm.gtt_mtrr = -1; |
| 1682 | } |
| 1683 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1684 | acpi_video_unregister(); |
| 1685 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1686 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
Chris Wilson | 7b4f399 | 2010-10-04 15:33:04 +0100 | [diff] [blame] | 1687 | intel_fbdev_fini(dev); |
Jesse Barnes | 3d8620c | 2010-03-26 11:07:21 -0700 | [diff] [blame] | 1688 | intel_modeset_cleanup(dev); |
Jesse Barnes | 073f34d | 2012-11-02 11:13:59 -0700 | [diff] [blame] | 1689 | cancel_work_sync(&dev_priv->console_resume_work); |
Jesse Barnes | 3d8620c | 2010-03-26 11:07:21 -0700 | [diff] [blame] | 1690 | |
Zhao Yakui | 6363ee6 | 2009-11-24 09:48:44 +0800 | [diff] [blame] | 1691 | /* |
| 1692 | * free the memory space allocated for the child device |
| 1693 | * config parsed from VBT |
| 1694 | */ |
| 1695 | if (dev_priv->child_dev && dev_priv->child_dev_num) { |
| 1696 | kfree(dev_priv->child_dev); |
| 1697 | dev_priv->child_dev = NULL; |
| 1698 | dev_priv->child_dev_num = 0; |
| 1699 | } |
Daniel Vetter | 6c0d9350 | 2010-08-20 18:26:46 +0200 | [diff] [blame] | 1700 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1701 | vga_switcheroo_unregister_client(dev->pdev); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1702 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1703 | } |
| 1704 | |
Daniel Vetter | a8b4899 | 2010-08-20 21:25:11 +0200 | [diff] [blame] | 1705 | /* Free error state after interrupts are fully disabled. */ |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 1706 | del_timer_sync(&dev_priv->hangcheck_timer); |
| 1707 | cancel_work_sync(&dev_priv->error_work); |
Daniel Vetter | a8b4899 | 2010-08-20 21:25:11 +0200 | [diff] [blame] | 1708 | i915_destroy_error_state(dev); |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 1709 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1710 | if (dev->pdev->msi_enabled) |
| 1711 | pci_disable_msi(dev->pdev); |
| 1712 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1713 | intel_opregion_fini(dev); |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 1714 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1715 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 1716 | /* Flush any outstanding unpin_work. */ |
| 1717 | flush_workqueue(dev_priv->wq); |
| 1718 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1719 | mutex_lock(&dev->struct_mutex); |
Hugh Dickins | ecbec53 | 2011-06-27 16:18:20 -0700 | [diff] [blame] | 1720 | i915_gem_free_all_phys_object(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1721 | i915_gem_cleanup_ringbuffer(dev); |
Daniel Vetter | 55a6662 | 2012-06-19 21:55:32 +0200 | [diff] [blame] | 1722 | i915_gem_context_fini(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1723 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1724 | i915_gem_cleanup_aliasing_ppgtt(dev); |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 1725 | i915_gem_cleanup_stolen(dev); |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1726 | drm_mm_takedown(&dev_priv->mm.stolen); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1727 | |
| 1728 | intel_cleanup_overlay(dev); |
Keith Packard | c2873e9 | 2010-10-07 09:20:12 +0100 | [diff] [blame] | 1729 | |
| 1730 | if (!I915_NEED_GFX_HWS(dev)) |
| 1731 | i915_free_hws(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1732 | } |
| 1733 | |
Daniel Vetter | 701394c | 2010-10-10 18:54:08 +0100 | [diff] [blame] | 1734 | if (dev_priv->regs != NULL) |
Chris Wilson | 6dda569 | 2010-10-29 21:02:18 +0100 | [diff] [blame] | 1735 | pci_iounmap(dev->pdev, dev_priv->regs); |
Daniel Vetter | 701394c | 2010-10-10 18:54:08 +0100 | [diff] [blame] | 1736 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1737 | intel_teardown_gmbus(dev); |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1738 | intel_teardown_mchbar(dev); |
| 1739 | |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 1740 | destroy_workqueue(dev_priv->wq); |
| 1741 | |
Dave Airlie | ec2a4c3 | 2009-08-04 11:43:41 +1000 | [diff] [blame] | 1742 | pci_dev_put(dev_priv->bridge_dev); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1743 | kfree(dev->dev_private); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1744 | |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 1745 | return 0; |
| 1746 | } |
| 1747 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1748 | int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1749 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1750 | struct drm_i915_file_private *file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1751 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 1752 | DRM_DEBUG_DRIVER("\n"); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1753 | file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL); |
| 1754 | if (!file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1755 | return -ENOMEM; |
| 1756 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1757 | file->driver_priv = file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1758 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1759 | spin_lock_init(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1760 | INIT_LIST_HEAD(&file_priv->mm.request_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1761 | |
Daniel Vetter | df12c6d | 2012-06-19 16:52:30 +0200 | [diff] [blame] | 1762 | idr_init(&file_priv->context_idr); |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 1763 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1764 | return 0; |
| 1765 | } |
| 1766 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1767 | /** |
| 1768 | * i915_driver_lastclose - clean up after all DRM clients have exited |
| 1769 | * @dev: DRM device |
| 1770 | * |
| 1771 | * Take care of cleaning up after all DRM clients have exited. In the |
| 1772 | * mode setting case, we want to restore the kernel's initial mode (just |
| 1773 | * in case the last client left us in a bad state). |
| 1774 | * |
Daniel Vetter | 9021f28 | 2012-03-26 09:45:41 +0200 | [diff] [blame] | 1775 | * Additionally, in the non-mode setting case, we'll tear down the GTT |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1776 | * and DMA structures, since the kernel won't be using them, and clea |
| 1777 | * up any GEM state. |
| 1778 | */ |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1779 | void i915_driver_lastclose(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1780 | { |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1781 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1782 | |
Daniel Vetter | e8aeaee | 2012-07-21 16:47:09 +0200 | [diff] [blame] | 1783 | /* On gen6+ we refuse to init without kms enabled, but then the drm core |
| 1784 | * goes right around and calls lastclose. Check for this and don't clean |
| 1785 | * up anything. */ |
| 1786 | if (!dev_priv) |
| 1787 | return; |
| 1788 | |
| 1789 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
Dave Airlie | e8e7a2b | 2011-04-21 22:18:32 +0100 | [diff] [blame] | 1790 | intel_fb_restore_mode(dev); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1791 | vga_switcheroo_process_delayed_switch(); |
Dave Airlie | 144a75f | 2008-03-30 07:53:58 +1000 | [diff] [blame] | 1792 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1793 | } |
Dave Airlie | 144a75f | 2008-03-30 07:53:58 +1000 | [diff] [blame] | 1794 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1795 | i915_gem_lastclose(dev); |
| 1796 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 1797 | i915_dma_cleanup(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1798 | } |
| 1799 | |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 1800 | void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1801 | { |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 1802 | i915_gem_context_close(dev, file_priv); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1803 | i915_gem_release(dev, file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1804 | } |
| 1805 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1806 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1807 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1808 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1809 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1810 | kfree(file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1811 | } |
| 1812 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 1813 | struct drm_ioctl_desc i915_ioctls[] = { |
Dave Airlie | 1b2f148 | 2010-08-14 20:20:34 +1000 | [diff] [blame] | 1814 | DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 1815 | DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH), |
| 1816 | DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH), |
| 1817 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), |
| 1818 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), |
| 1819 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), |
| 1820 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH), |
| 1821 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
Daniel Vetter | b2c606f | 2012-01-17 12:50:12 +0100 | [diff] [blame] | 1822 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), |
| 1823 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), |
| 1824 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
Dave Airlie | 1b2f148 | 2010-08-14 20:20:34 +1000 | [diff] [blame] | 1825 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), |
Daniel Vetter | b2c606f | 2012-01-17 12:50:12 +0100 | [diff] [blame] | 1826 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
Daniel Vetter | d1c1edb | 2012-04-26 23:28:01 +0200 | [diff] [blame] | 1827 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
Dave Airlie | 1b2f148 | 2010-08-14 20:20:34 +1000 | [diff] [blame] | 1828 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH), |
| 1829 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), |
| 1830 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 1831 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
| 1832 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), |
| 1833 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED), |
| 1834 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), |
| 1835 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), |
| 1836 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 1837 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED), |
| 1838 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED), |
Dave Airlie | 1b2f148 | 2010-08-14 20:20:34 +1000 | [diff] [blame] | 1839 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED), |
| 1840 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
| 1841 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
| 1842 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED), |
| 1843 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED), |
| 1844 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED), |
| 1845 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED), |
| 1846 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED), |
| 1847 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED), |
| 1848 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED), |
| 1849 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED), |
| 1850 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED), |
| 1851 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED), |
| 1852 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), |
| 1853 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED), |
| 1854 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
| 1855 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
Jesse Barnes | 8ea3086 | 2012-01-03 08:05:39 -0800 | [diff] [blame] | 1856 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
| 1857 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 1858 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED), |
Ben Widawsky | 8462481 | 2012-06-04 14:42:54 -0700 | [diff] [blame] | 1859 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED), |
| 1860 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED), |
Ben Widawsky | c0c7bab | 2012-07-12 11:01:05 -0700 | [diff] [blame] | 1861 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED), |
Dave Airlie | c94f702 | 2005-07-07 21:03:38 +1000 | [diff] [blame] | 1862 | }; |
| 1863 | |
| 1864 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); |
Dave Airlie | cda1738 | 2005-07-10 17:31:26 +1000 | [diff] [blame] | 1865 | |
Daniel Vetter | 9021f28 | 2012-03-26 09:45:41 +0200 | [diff] [blame] | 1866 | /* |
| 1867 | * This is really ugly: Because old userspace abused the linux agp interface to |
| 1868 | * manage the gtt, we need to claim that all intel devices are agp. For |
| 1869 | * otherwise the drm core refuses to initialize the agp support code. |
Dave Airlie | cda1738 | 2005-07-10 17:31:26 +1000 | [diff] [blame] | 1870 | */ |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1871 | int i915_driver_device_is_agp(struct drm_device * dev) |
Dave Airlie | cda1738 | 2005-07-10 17:31:26 +1000 | [diff] [blame] | 1872 | { |
| 1873 | return 1; |
| 1874 | } |