Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * tg3.c: Broadcom Tigon3 ethernet driver. |
| 3 | * |
| 4 | * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) |
| 5 | * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) |
| 6 | * Copyright (C) 2004 Sun Microsystems Inc. |
Matt Carlson | b86fb2c | 2011-01-25 15:58:57 +0000 | [diff] [blame] | 7 | * Copyright (C) 2005-2011 Broadcom Corporation. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | * |
| 9 | * Firmware is: |
Michael Chan | 49cabf4 | 2005-06-06 15:15:17 -0700 | [diff] [blame] | 10 | * Derived from proprietary unpublished source code, |
| 11 | * Copyright (C) 2000-2003 Broadcom Corporation. |
| 12 | * |
| 13 | * Permission is hereby granted for the distribution of this firmware |
| 14 | * data in hexadecimal or equivalent format, provided this copyright |
| 15 | * notice is accompanying it. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | */ |
| 17 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | |
| 19 | #include <linux/module.h> |
| 20 | #include <linux/moduleparam.h> |
Matt Carlson | 6867c84 | 2010-07-11 09:31:44 +0000 | [diff] [blame] | 21 | #include <linux/stringify.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | #include <linux/kernel.h> |
| 23 | #include <linux/types.h> |
| 24 | #include <linux/compiler.h> |
| 25 | #include <linux/slab.h> |
| 26 | #include <linux/delay.h> |
Arnaldo Carvalho de Melo | 14c8502 | 2005-12-27 02:43:12 -0200 | [diff] [blame] | 27 | #include <linux/in.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | #include <linux/init.h> |
Alexey Dobriyan | a6b7a40 | 2011-06-06 10:43:46 +0000 | [diff] [blame] | 29 | #include <linux/interrupt.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | #include <linux/ioport.h> |
| 31 | #include <linux/pci.h> |
| 32 | #include <linux/netdevice.h> |
| 33 | #include <linux/etherdevice.h> |
| 34 | #include <linux/skbuff.h> |
| 35 | #include <linux/ethtool.h> |
Matt Carlson | 3110f5f5 | 2010-12-06 08:28:50 +0000 | [diff] [blame] | 36 | #include <linux/mdio.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | #include <linux/mii.h> |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 38 | #include <linux/phy.h> |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 39 | #include <linux/brcmphy.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | #include <linux/if_vlan.h> |
| 41 | #include <linux/ip.h> |
| 42 | #include <linux/tcp.h> |
| 43 | #include <linux/workqueue.h> |
Michael Chan | 6148748 | 2005-09-05 17:53:19 -0700 | [diff] [blame] | 44 | #include <linux/prefetch.h> |
Tobias Klauser | f9a5f7d | 2005-10-29 15:09:26 +0200 | [diff] [blame] | 45 | #include <linux/dma-mapping.h> |
Jaswinder Singh Rajput | 077f849 | 2009-01-04 16:11:25 -0800 | [diff] [blame] | 46 | #include <linux/firmware.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | |
| 48 | #include <net/checksum.h> |
Arnaldo Carvalho de Melo | c9bdd4b | 2007-03-12 20:09:15 -0300 | [diff] [blame] | 49 | #include <net/ip.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | |
| 51 | #include <asm/system.h> |
Javier Martinez Canillas | 27fd9de | 2011-03-26 16:42:31 +0000 | [diff] [blame] | 52 | #include <linux/io.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 53 | #include <asm/byteorder.h> |
Javier Martinez Canillas | 27fd9de | 2011-03-26 16:42:31 +0000 | [diff] [blame] | 54 | #include <linux/uaccess.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | |
David S. Miller | 49b6e95f | 2007-03-29 01:38:42 -0700 | [diff] [blame] | 56 | #ifdef CONFIG_SPARC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 57 | #include <asm/idprom.h> |
David S. Miller | 49b6e95f | 2007-03-29 01:38:42 -0700 | [diff] [blame] | 58 | #include <asm/prom.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | #endif |
| 60 | |
Matt Carlson | 6353239 | 2008-11-03 16:49:57 -0800 | [diff] [blame] | 61 | #define BAR_0 0 |
| 62 | #define BAR_2 2 |
| 63 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 64 | #include "tg3.h" |
| 65 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 66 | /* Functions & macros to verify TG3_FLAGS types */ |
| 67 | |
| 68 | static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits) |
| 69 | { |
| 70 | return test_bit(flag, bits); |
| 71 | } |
| 72 | |
| 73 | static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits) |
| 74 | { |
| 75 | set_bit(flag, bits); |
| 76 | } |
| 77 | |
| 78 | static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits) |
| 79 | { |
| 80 | clear_bit(flag, bits); |
| 81 | } |
| 82 | |
| 83 | #define tg3_flag(tp, flag) \ |
| 84 | _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags) |
| 85 | #define tg3_flag_set(tp, flag) \ |
| 86 | _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags) |
| 87 | #define tg3_flag_clear(tp, flag) \ |
| 88 | _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags) |
| 89 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 90 | #define DRV_MODULE_NAME "tg3" |
Matt Carlson | 6867c84 | 2010-07-11 09:31:44 +0000 | [diff] [blame] | 91 | #define TG3_MAJ_NUM 3 |
Matt Carlson | efab79c | 2011-12-08 14:40:18 +0000 | [diff] [blame] | 92 | #define TG3_MIN_NUM 122 |
Matt Carlson | 6867c84 | 2010-07-11 09:31:44 +0000 | [diff] [blame] | 93 | #define DRV_MODULE_VERSION \ |
| 94 | __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM) |
Matt Carlson | efab79c | 2011-12-08 14:40:18 +0000 | [diff] [blame] | 95 | #define DRV_MODULE_RELDATE "December 7, 2011" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 96 | |
Matt Carlson | fd6d3f0 | 2011-08-31 11:44:52 +0000 | [diff] [blame] | 97 | #define RESET_KIND_SHUTDOWN 0 |
| 98 | #define RESET_KIND_INIT 1 |
| 99 | #define RESET_KIND_SUSPEND 2 |
| 100 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 101 | #define TG3_DEF_RX_MODE 0 |
| 102 | #define TG3_DEF_TX_MODE 0 |
| 103 | #define TG3_DEF_MSG_ENABLE \ |
| 104 | (NETIF_MSG_DRV | \ |
| 105 | NETIF_MSG_PROBE | \ |
| 106 | NETIF_MSG_LINK | \ |
| 107 | NETIF_MSG_TIMER | \ |
| 108 | NETIF_MSG_IFDOWN | \ |
| 109 | NETIF_MSG_IFUP | \ |
| 110 | NETIF_MSG_RX_ERR | \ |
| 111 | NETIF_MSG_TX_ERR) |
| 112 | |
Matt Carlson | 520b275 | 2011-06-13 13:39:02 +0000 | [diff] [blame] | 113 | #define TG3_GRC_LCLCTL_PWRSW_DELAY 100 |
| 114 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 115 | /* length of time before we decide the hardware is borked, |
| 116 | * and dev->tx_timeout() should be called to fix the problem |
| 117 | */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 118 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 119 | #define TG3_TX_TIMEOUT (5 * HZ) |
| 120 | |
| 121 | /* hardware minimum and maximum for a single frame's data payload */ |
| 122 | #define TG3_MIN_MTU 60 |
| 123 | #define TG3_MAX_MTU(tp) \ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 124 | (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 125 | |
| 126 | /* These numbers seem to be hard coded in the NIC firmware somehow. |
| 127 | * You can't change the ring sizes, but you can change where you place |
| 128 | * them in the NIC onboard memory. |
| 129 | */ |
Matt Carlson | 7cb32cf | 2010-09-30 10:34:36 +0000 | [diff] [blame] | 130 | #define TG3_RX_STD_RING_SIZE(tp) \ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 131 | (tg3_flag(tp, LRG_PROD_RING_CAP) ? \ |
Matt Carlson | de9f523 | 2011-04-05 14:22:43 +0000 | [diff] [blame] | 132 | TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 133 | #define TG3_DEF_RX_RING_PENDING 200 |
Matt Carlson | 7cb32cf | 2010-09-30 10:34:36 +0000 | [diff] [blame] | 134 | #define TG3_RX_JMB_RING_SIZE(tp) \ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 135 | (tg3_flag(tp, LRG_PROD_RING_CAP) ? \ |
Matt Carlson | de9f523 | 2011-04-05 14:22:43 +0000 | [diff] [blame] | 136 | TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 137 | #define TG3_DEF_RX_JUMBO_RING_PENDING 100 |
| 138 | |
| 139 | /* Do not place this n-ring entries value into the tp struct itself, |
| 140 | * we really want to expose these constants to GCC so that modulo et |
| 141 | * al. operations are done with shifts and masks instead of with |
| 142 | * hw multiply/modulo instructions. Another solution would be to |
| 143 | * replace things like '% foo' with '& (foo - 1)'. |
| 144 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 145 | |
| 146 | #define TG3_TX_RING_SIZE 512 |
| 147 | #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) |
| 148 | |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 149 | #define TG3_RX_STD_RING_BYTES(tp) \ |
| 150 | (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp)) |
| 151 | #define TG3_RX_JMB_RING_BYTES(tp) \ |
| 152 | (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp)) |
| 153 | #define TG3_RX_RCB_RING_BYTES(tp) \ |
Matt Carlson | 7cb32cf | 2010-09-30 10:34:36 +0000 | [diff] [blame] | 154 | (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 155 | #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \ |
| 156 | TG3_TX_RING_SIZE) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 157 | #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) |
| 158 | |
Matt Carlson | 287be12 | 2009-08-28 13:58:46 +0000 | [diff] [blame] | 159 | #define TG3_DMA_BYTE_ENAB 64 |
| 160 | |
| 161 | #define TG3_RX_STD_DMA_SZ 1536 |
| 162 | #define TG3_RX_JMB_DMA_SZ 9046 |
| 163 | |
| 164 | #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB) |
| 165 | |
| 166 | #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ) |
| 167 | #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 168 | |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 169 | #define TG3_RX_STD_BUFF_RING_SIZE(tp) \ |
| 170 | (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp)) |
Matt Carlson | 2b2cdb6 | 2009-11-13 13:03:48 +0000 | [diff] [blame] | 171 | |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 172 | #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \ |
| 173 | (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp)) |
Matt Carlson | 2b2cdb6 | 2009-11-13 13:03:48 +0000 | [diff] [blame] | 174 | |
Matt Carlson | d2757fc | 2010-04-12 06:58:27 +0000 | [diff] [blame] | 175 | /* Due to a hardware bug, the 5701 can only DMA to memory addresses |
| 176 | * that are at least dword aligned when used in PCIX mode. The driver |
| 177 | * works around this bug by double copying the packet. This workaround |
| 178 | * is built into the normal double copy length check for efficiency. |
| 179 | * |
| 180 | * However, the double copy is only necessary on those architectures |
| 181 | * where unaligned memory accesses are inefficient. For those architectures |
| 182 | * where unaligned memory accesses incur little penalty, we can reintegrate |
| 183 | * the 5701 in the normal rx path. Doing so saves a device structure |
| 184 | * dereference by hardcoding the double copy threshold in place. |
| 185 | */ |
| 186 | #define TG3_RX_COPY_THRESHOLD 256 |
| 187 | #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) |
| 188 | #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD |
| 189 | #else |
| 190 | #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) |
| 191 | #endif |
| 192 | |
Matt Carlson | 81389f5 | 2011-08-31 11:44:49 +0000 | [diff] [blame] | 193 | #if (NET_IP_ALIGN != 0) |
| 194 | #define TG3_RX_OFFSET(tp) ((tp)->rx_offset) |
| 195 | #else |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 196 | #define TG3_RX_OFFSET(tp) (NET_SKB_PAD) |
Matt Carlson | 81389f5 | 2011-08-31 11:44:49 +0000 | [diff] [blame] | 197 | #endif |
| 198 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 199 | /* minimum number of free TX descriptors required to wake up TX process */ |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 200 | #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) |
Matt Carlson | 55086ad | 2011-12-14 11:09:59 +0000 | [diff] [blame] | 201 | #define TG3_TX_BD_DMA_MAX_2K 2048 |
Matt Carlson | a4cb428 | 2011-12-14 11:09:58 +0000 | [diff] [blame] | 202 | #define TG3_TX_BD_DMA_MAX_4K 4096 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 203 | |
Matt Carlson | ad82926 | 2008-11-21 17:16:16 -0800 | [diff] [blame] | 204 | #define TG3_RAW_IP_ALIGN 2 |
| 205 | |
Matt Carlson | c6cdf43 | 2010-04-05 10:19:26 +0000 | [diff] [blame] | 206 | #define TG3_FW_UPDATE_TIMEOUT_SEC 5 |
| 207 | |
Jaswinder Singh Rajput | 077f849 | 2009-01-04 16:11:25 -0800 | [diff] [blame] | 208 | #define FIRMWARE_TG3 "tigon/tg3.bin" |
| 209 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" |
| 210 | #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" |
| 211 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 212 | static char version[] __devinitdata = |
Joe Perches | 05dbe00 | 2010-02-17 19:44:19 +0000 | [diff] [blame] | 213 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 214 | |
| 215 | MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)"); |
| 216 | MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); |
| 217 | MODULE_LICENSE("GPL"); |
| 218 | MODULE_VERSION(DRV_MODULE_VERSION); |
Jaswinder Singh Rajput | 077f849 | 2009-01-04 16:11:25 -0800 | [diff] [blame] | 219 | MODULE_FIRMWARE(FIRMWARE_TG3); |
| 220 | MODULE_FIRMWARE(FIRMWARE_TG3TSO); |
| 221 | MODULE_FIRMWARE(FIRMWARE_TG3TSO5); |
| 222 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 223 | static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */ |
| 224 | module_param(tg3_debug, int, 0); |
| 225 | MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value"); |
| 226 | |
Alexey Dobriyan | a3aa188 | 2010-01-07 11:58:11 +0000 | [diff] [blame] | 227 | static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = { |
Henrik Kretzschmar | 1318521 | 2006-08-22 00:28:33 -0700 | [diff] [blame] | 228 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)}, |
| 229 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)}, |
| 230 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)}, |
| 231 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)}, |
| 232 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)}, |
| 233 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)}, |
| 234 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)}, |
| 235 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)}, |
| 236 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)}, |
| 237 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)}, |
| 238 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)}, |
| 239 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)}, |
| 240 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)}, |
| 241 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)}, |
| 242 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)}, |
| 243 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)}, |
| 244 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)}, |
| 245 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)}, |
| 246 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)}, |
| 247 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)}, |
| 248 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)}, |
| 249 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)}, |
Henrik Kretzschmar | 1318521 | 2006-08-22 00:28:33 -0700 | [diff] [blame] | 250 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)}, |
Michael Chan | 126a336 | 2006-09-27 16:03:07 -0700 | [diff] [blame] | 251 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)}, |
Henrik Kretzschmar | 1318521 | 2006-08-22 00:28:33 -0700 | [diff] [blame] | 252 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)}, |
Henrik Kretzschmar | 1318521 | 2006-08-22 00:28:33 -0700 | [diff] [blame] | 253 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)}, |
| 254 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)}, |
| 255 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)}, |
| 256 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)}, |
| 257 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)}, |
| 258 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)}, |
| 259 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)}, |
| 260 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)}, |
| 261 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)}, |
| 262 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)}, |
| 263 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)}, |
Michael Chan | 126a336 | 2006-09-27 16:03:07 -0700 | [diff] [blame] | 264 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)}, |
Henrik Kretzschmar | 1318521 | 2006-08-22 00:28:33 -0700 | [diff] [blame] | 265 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)}, |
| 266 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)}, |
| 267 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)}, |
Michael Chan | 676917d | 2006-12-07 00:20:22 -0800 | [diff] [blame] | 268 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)}, |
Henrik Kretzschmar | 1318521 | 2006-08-22 00:28:33 -0700 | [diff] [blame] | 269 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)}, |
| 270 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)}, |
| 271 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)}, |
| 272 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)}, |
| 273 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)}, |
| 274 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)}, |
| 275 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)}, |
Michael Chan | b5d3772 | 2006-09-27 16:06:21 -0700 | [diff] [blame] | 276 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)}, |
| 277 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)}, |
Matt Carlson | d30cdd2 | 2007-10-07 23:28:35 -0700 | [diff] [blame] | 278 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)}, |
| 279 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)}, |
Matt Carlson | 6c7af27 | 2007-10-21 16:12:02 -0700 | [diff] [blame] | 280 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, |
Matt Carlson | 9936bcf | 2007-10-10 18:03:07 -0700 | [diff] [blame] | 281 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, |
| 282 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, |
Matt Carlson | c88e668 | 2008-11-03 16:49:18 -0800 | [diff] [blame] | 283 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)}, |
| 284 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)}, |
Matt Carlson | 2befdce | 2009-08-28 12:28:45 +0000 | [diff] [blame] | 285 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)}, |
| 286 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)}, |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 287 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)}, |
| 288 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)}, |
| 289 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)}, |
Matt Carlson | 5e7ccf2 | 2009-08-25 10:08:42 +0000 | [diff] [blame] | 290 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)}, |
Matt Carlson | 5001e2f | 2009-11-13 13:03:51 +0000 | [diff] [blame] | 291 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)}, |
| 292 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)}, |
Matt Carlson | b0f7522 | 2010-01-20 16:58:11 +0000 | [diff] [blame] | 293 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)}, |
| 294 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)}, |
| 295 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)}, |
| 296 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)}, |
| 297 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)}, |
| 298 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)}, |
Matt Carlson | 302b500 | 2010-06-05 17:24:38 +0000 | [diff] [blame] | 299 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)}, |
Matt Carlson | ba1f3c7 | 2011-04-05 14:22:50 +0000 | [diff] [blame] | 300 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)}, |
Henrik Kretzschmar | 1318521 | 2006-08-22 00:28:33 -0700 | [diff] [blame] | 301 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, |
| 302 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, |
| 303 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, |
| 304 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)}, |
| 305 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)}, |
| 306 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)}, |
| 307 | {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)}, |
Meelis Roos | 1dcb14d | 2011-05-25 05:43:47 +0000 | [diff] [blame] | 308 | {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */ |
Henrik Kretzschmar | 1318521 | 2006-08-22 00:28:33 -0700 | [diff] [blame] | 309 | {} |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 310 | }; |
| 311 | |
| 312 | MODULE_DEVICE_TABLE(pci, tg3_pci_tbl); |
| 313 | |
Andreas Mohr | 50da859 | 2006-08-14 23:54:30 -0700 | [diff] [blame] | 314 | static const struct { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 315 | const char string[ETH_GSTRING_LEN]; |
Matt Carlson | 48fa55a | 2011-04-13 11:05:06 +0000 | [diff] [blame] | 316 | } ethtool_stats_keys[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 317 | { "rx_octets" }, |
| 318 | { "rx_fragments" }, |
| 319 | { "rx_ucast_packets" }, |
| 320 | { "rx_mcast_packets" }, |
| 321 | { "rx_bcast_packets" }, |
| 322 | { "rx_fcs_errors" }, |
| 323 | { "rx_align_errors" }, |
| 324 | { "rx_xon_pause_rcvd" }, |
| 325 | { "rx_xoff_pause_rcvd" }, |
| 326 | { "rx_mac_ctrl_rcvd" }, |
| 327 | { "rx_xoff_entered" }, |
| 328 | { "rx_frame_too_long_errors" }, |
| 329 | { "rx_jabbers" }, |
| 330 | { "rx_undersize_packets" }, |
| 331 | { "rx_in_length_errors" }, |
| 332 | { "rx_out_length_errors" }, |
| 333 | { "rx_64_or_less_octet_packets" }, |
| 334 | { "rx_65_to_127_octet_packets" }, |
| 335 | { "rx_128_to_255_octet_packets" }, |
| 336 | { "rx_256_to_511_octet_packets" }, |
| 337 | { "rx_512_to_1023_octet_packets" }, |
| 338 | { "rx_1024_to_1522_octet_packets" }, |
| 339 | { "rx_1523_to_2047_octet_packets" }, |
| 340 | { "rx_2048_to_4095_octet_packets" }, |
| 341 | { "rx_4096_to_8191_octet_packets" }, |
| 342 | { "rx_8192_to_9022_octet_packets" }, |
| 343 | |
| 344 | { "tx_octets" }, |
| 345 | { "tx_collisions" }, |
| 346 | |
| 347 | { "tx_xon_sent" }, |
| 348 | { "tx_xoff_sent" }, |
| 349 | { "tx_flow_control" }, |
| 350 | { "tx_mac_errors" }, |
| 351 | { "tx_single_collisions" }, |
| 352 | { "tx_mult_collisions" }, |
| 353 | { "tx_deferred" }, |
| 354 | { "tx_excessive_collisions" }, |
| 355 | { "tx_late_collisions" }, |
| 356 | { "tx_collide_2times" }, |
| 357 | { "tx_collide_3times" }, |
| 358 | { "tx_collide_4times" }, |
| 359 | { "tx_collide_5times" }, |
| 360 | { "tx_collide_6times" }, |
| 361 | { "tx_collide_7times" }, |
| 362 | { "tx_collide_8times" }, |
| 363 | { "tx_collide_9times" }, |
| 364 | { "tx_collide_10times" }, |
| 365 | { "tx_collide_11times" }, |
| 366 | { "tx_collide_12times" }, |
| 367 | { "tx_collide_13times" }, |
| 368 | { "tx_collide_14times" }, |
| 369 | { "tx_collide_15times" }, |
| 370 | { "tx_ucast_packets" }, |
| 371 | { "tx_mcast_packets" }, |
| 372 | { "tx_bcast_packets" }, |
| 373 | { "tx_carrier_sense_errors" }, |
| 374 | { "tx_discards" }, |
| 375 | { "tx_errors" }, |
| 376 | |
| 377 | { "dma_writeq_full" }, |
| 378 | { "dma_write_prioq_full" }, |
| 379 | { "rxbds_empty" }, |
| 380 | { "rx_discards" }, |
| 381 | { "rx_errors" }, |
| 382 | { "rx_threshold_hit" }, |
| 383 | |
| 384 | { "dma_readq_full" }, |
| 385 | { "dma_read_prioq_full" }, |
| 386 | { "tx_comp_queue_full" }, |
| 387 | |
| 388 | { "ring_set_send_prod_index" }, |
| 389 | { "ring_status_update" }, |
| 390 | { "nic_irqs" }, |
| 391 | { "nic_avoided_irqs" }, |
Matt Carlson | 4452d09 | 2011-05-19 12:12:51 +0000 | [diff] [blame] | 392 | { "nic_tx_threshold_hit" }, |
| 393 | |
| 394 | { "mbuf_lwm_thresh_hit" }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 395 | }; |
| 396 | |
Matt Carlson | 48fa55a | 2011-04-13 11:05:06 +0000 | [diff] [blame] | 397 | #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys) |
| 398 | |
| 399 | |
Andreas Mohr | 50da859 | 2006-08-14 23:54:30 -0700 | [diff] [blame] | 400 | static const struct { |
Michael Chan | 4cafd3f | 2005-05-29 14:56:34 -0700 | [diff] [blame] | 401 | const char string[ETH_GSTRING_LEN]; |
Matt Carlson | 48fa55a | 2011-04-13 11:05:06 +0000 | [diff] [blame] | 402 | } ethtool_test_keys[] = { |
Matt Carlson | 28a4595 | 2011-08-19 13:58:22 +0000 | [diff] [blame] | 403 | { "nvram test (online) " }, |
| 404 | { "link test (online) " }, |
| 405 | { "register test (offline)" }, |
| 406 | { "memory test (offline)" }, |
| 407 | { "mac loopback test (offline)" }, |
| 408 | { "phy loopback test (offline)" }, |
Matt Carlson | 941ec90 | 2011-08-19 13:58:23 +0000 | [diff] [blame] | 409 | { "ext loopback test (offline)" }, |
Matt Carlson | 28a4595 | 2011-08-19 13:58:22 +0000 | [diff] [blame] | 410 | { "interrupt test (offline)" }, |
Michael Chan | 4cafd3f | 2005-05-29 14:56:34 -0700 | [diff] [blame] | 411 | }; |
| 412 | |
Matt Carlson | 48fa55a | 2011-04-13 11:05:06 +0000 | [diff] [blame] | 413 | #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys) |
| 414 | |
| 415 | |
Michael Chan | b401e9e | 2005-12-19 16:27:04 -0800 | [diff] [blame] | 416 | static void tg3_write32(struct tg3 *tp, u32 off, u32 val) |
| 417 | { |
| 418 | writel(val, tp->regs + off); |
| 419 | } |
| 420 | |
| 421 | static u32 tg3_read32(struct tg3 *tp, u32 off) |
| 422 | { |
Matt Carlson | de6f31e | 2010-04-12 06:58:30 +0000 | [diff] [blame] | 423 | return readl(tp->regs + off); |
Michael Chan | b401e9e | 2005-12-19 16:27:04 -0800 | [diff] [blame] | 424 | } |
| 425 | |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 426 | static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) |
| 427 | { |
| 428 | writel(val, tp->aperegs + off); |
| 429 | } |
| 430 | |
| 431 | static u32 tg3_ape_read32(struct tg3 *tp, u32 off) |
| 432 | { |
Matt Carlson | de6f31e | 2010-04-12 06:58:30 +0000 | [diff] [blame] | 433 | return readl(tp->aperegs + off); |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 434 | } |
| 435 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 436 | static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) |
| 437 | { |
Michael Chan | 6892914 | 2005-08-09 20:17:14 -0700 | [diff] [blame] | 438 | unsigned long flags; |
| 439 | |
| 440 | spin_lock_irqsave(&tp->indirect_lock, flags); |
Michael Chan | 1ee582d | 2005-08-09 20:16:46 -0700 | [diff] [blame] | 441 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); |
| 442 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); |
Michael Chan | 6892914 | 2005-08-09 20:17:14 -0700 | [diff] [blame] | 443 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
Michael Chan | 1ee582d | 2005-08-09 20:16:46 -0700 | [diff] [blame] | 444 | } |
| 445 | |
| 446 | static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) |
| 447 | { |
| 448 | writel(val, tp->regs + off); |
| 449 | readl(tp->regs + off); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 450 | } |
| 451 | |
Michael Chan | 6892914 | 2005-08-09 20:17:14 -0700 | [diff] [blame] | 452 | static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) |
| 453 | { |
| 454 | unsigned long flags; |
| 455 | u32 val; |
| 456 | |
| 457 | spin_lock_irqsave(&tp->indirect_lock, flags); |
| 458 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); |
| 459 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); |
| 460 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
| 461 | return val; |
| 462 | } |
| 463 | |
| 464 | static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) |
| 465 | { |
| 466 | unsigned long flags; |
| 467 | |
| 468 | if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { |
| 469 | pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + |
| 470 | TG3_64BIT_REG_LOW, val); |
| 471 | return; |
| 472 | } |
Matt Carlson | 66711e6 | 2009-11-13 13:03:49 +0000 | [diff] [blame] | 473 | if (off == TG3_RX_STD_PROD_IDX_REG) { |
Michael Chan | 6892914 | 2005-08-09 20:17:14 -0700 | [diff] [blame] | 474 | pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + |
| 475 | TG3_64BIT_REG_LOW, val); |
| 476 | return; |
| 477 | } |
| 478 | |
| 479 | spin_lock_irqsave(&tp->indirect_lock, flags); |
| 480 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); |
| 481 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); |
| 482 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
| 483 | |
| 484 | /* In indirect mode when disabling interrupts, we also need |
| 485 | * to clear the interrupt bit in the GRC local ctrl register. |
| 486 | */ |
| 487 | if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && |
| 488 | (val == 0x1)) { |
| 489 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, |
| 490 | tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); |
| 491 | } |
| 492 | } |
| 493 | |
| 494 | static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) |
| 495 | { |
| 496 | unsigned long flags; |
| 497 | u32 val; |
| 498 | |
| 499 | spin_lock_irqsave(&tp->indirect_lock, flags); |
| 500 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); |
| 501 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); |
| 502 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
| 503 | return val; |
| 504 | } |
| 505 | |
Michael Chan | b401e9e | 2005-12-19 16:27:04 -0800 | [diff] [blame] | 506 | /* usec_wait specifies the wait time in usec when writing to certain registers |
| 507 | * where it is unsafe to read back the register without some delay. |
| 508 | * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power. |
| 509 | * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed. |
| 510 | */ |
| 511 | static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 512 | { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 513 | if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND)) |
Michael Chan | b401e9e | 2005-12-19 16:27:04 -0800 | [diff] [blame] | 514 | /* Non-posted methods */ |
| 515 | tp->write32(tp, off, val); |
| 516 | else { |
| 517 | /* Posted method */ |
| 518 | tg3_write32(tp, off, val); |
| 519 | if (usec_wait) |
| 520 | udelay(usec_wait); |
| 521 | tp->read32(tp, off); |
| 522 | } |
| 523 | /* Wait again after the read for the posted method to guarantee that |
| 524 | * the wait time is met. |
| 525 | */ |
| 526 | if (usec_wait) |
| 527 | udelay(usec_wait); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 528 | } |
| 529 | |
Michael Chan | 09ee929 | 2005-08-09 20:17:00 -0700 | [diff] [blame] | 530 | static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) |
| 531 | { |
| 532 | tp->write32_mbox(tp, off, val); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 533 | if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND)) |
Michael Chan | 6892914 | 2005-08-09 20:17:14 -0700 | [diff] [blame] | 534 | tp->read32_mbox(tp, off); |
Michael Chan | 09ee929 | 2005-08-09 20:17:00 -0700 | [diff] [blame] | 535 | } |
| 536 | |
Michael Chan | 2009493 | 2005-08-09 20:16:32 -0700 | [diff] [blame] | 537 | static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 538 | { |
| 539 | void __iomem *mbox = tp->regs + off; |
| 540 | writel(val, mbox); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 541 | if (tg3_flag(tp, TXD_MBOX_HWBUG)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 542 | writel(val, mbox); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 543 | if (tg3_flag(tp, MBOX_WRITE_REORDER)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 544 | readl(mbox); |
| 545 | } |
| 546 | |
Michael Chan | b5d3772 | 2006-09-27 16:06:21 -0700 | [diff] [blame] | 547 | static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) |
| 548 | { |
Matt Carlson | de6f31e | 2010-04-12 06:58:30 +0000 | [diff] [blame] | 549 | return readl(tp->regs + off + GRCMBOX_BASE); |
Michael Chan | b5d3772 | 2006-09-27 16:06:21 -0700 | [diff] [blame] | 550 | } |
| 551 | |
| 552 | static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) |
| 553 | { |
| 554 | writel(val, tp->regs + off + GRCMBOX_BASE); |
| 555 | } |
| 556 | |
Matt Carlson | c6cdf43 | 2010-04-05 10:19:26 +0000 | [diff] [blame] | 557 | #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) |
Michael Chan | 09ee929 | 2005-08-09 20:17:00 -0700 | [diff] [blame] | 558 | #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) |
Matt Carlson | c6cdf43 | 2010-04-05 10:19:26 +0000 | [diff] [blame] | 559 | #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) |
| 560 | #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) |
| 561 | #define tr32_mailbox(reg) tp->read32_mbox(tp, reg) |
Michael Chan | 2009493 | 2005-08-09 20:16:32 -0700 | [diff] [blame] | 562 | |
Matt Carlson | c6cdf43 | 2010-04-05 10:19:26 +0000 | [diff] [blame] | 563 | #define tw32(reg, val) tp->write32(tp, reg, val) |
| 564 | #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0) |
| 565 | #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us)) |
| 566 | #define tr32(reg) tp->read32(tp, reg) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 567 | |
| 568 | static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) |
| 569 | { |
Michael Chan | 6892914 | 2005-08-09 20:17:14 -0700 | [diff] [blame] | 570 | unsigned long flags; |
| 571 | |
Matt Carlson | 6ff6f81 | 2011-05-19 12:12:54 +0000 | [diff] [blame] | 572 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && |
Michael Chan | b5d3772 | 2006-09-27 16:06:21 -0700 | [diff] [blame] | 573 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) |
| 574 | return; |
| 575 | |
Michael Chan | 6892914 | 2005-08-09 20:17:14 -0700 | [diff] [blame] | 576 | spin_lock_irqsave(&tp->indirect_lock, flags); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 577 | if (tg3_flag(tp, SRAM_USE_CONFIG)) { |
Michael Chan | bbadf50 | 2006-04-06 21:46:34 -0700 | [diff] [blame] | 578 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); |
| 579 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 580 | |
Michael Chan | bbadf50 | 2006-04-06 21:46:34 -0700 | [diff] [blame] | 581 | /* Always leave this as zero. */ |
| 582 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); |
| 583 | } else { |
| 584 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); |
| 585 | tw32_f(TG3PCI_MEM_WIN_DATA, val); |
| 586 | |
| 587 | /* Always leave this as zero. */ |
| 588 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); |
| 589 | } |
Michael Chan | 6892914 | 2005-08-09 20:17:14 -0700 | [diff] [blame] | 590 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 591 | } |
| 592 | |
| 593 | static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) |
| 594 | { |
Michael Chan | 6892914 | 2005-08-09 20:17:14 -0700 | [diff] [blame] | 595 | unsigned long flags; |
| 596 | |
Matt Carlson | 6ff6f81 | 2011-05-19 12:12:54 +0000 | [diff] [blame] | 597 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && |
Michael Chan | b5d3772 | 2006-09-27 16:06:21 -0700 | [diff] [blame] | 598 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) { |
| 599 | *val = 0; |
| 600 | return; |
| 601 | } |
| 602 | |
Michael Chan | 6892914 | 2005-08-09 20:17:14 -0700 | [diff] [blame] | 603 | spin_lock_irqsave(&tp->indirect_lock, flags); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 604 | if (tg3_flag(tp, SRAM_USE_CONFIG)) { |
Michael Chan | bbadf50 | 2006-04-06 21:46:34 -0700 | [diff] [blame] | 605 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); |
| 606 | pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 607 | |
Michael Chan | bbadf50 | 2006-04-06 21:46:34 -0700 | [diff] [blame] | 608 | /* Always leave this as zero. */ |
| 609 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); |
| 610 | } else { |
| 611 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); |
| 612 | *val = tr32(TG3PCI_MEM_WIN_DATA); |
| 613 | |
| 614 | /* Always leave this as zero. */ |
| 615 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); |
| 616 | } |
Michael Chan | 6892914 | 2005-08-09 20:17:14 -0700 | [diff] [blame] | 617 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 618 | } |
| 619 | |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 620 | static void tg3_ape_lock_init(struct tg3 *tp) |
| 621 | { |
| 622 | int i; |
Matt Carlson | 6f5c8f83 | 2011-07-13 09:27:31 +0000 | [diff] [blame] | 623 | u32 regbase, bit; |
Matt Carlson | f92d9dc1 | 2010-06-05 17:24:30 +0000 | [diff] [blame] | 624 | |
| 625 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
| 626 | regbase = TG3_APE_LOCK_GRANT; |
| 627 | else |
| 628 | regbase = TG3_APE_PER_LOCK_GRANT; |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 629 | |
| 630 | /* Make sure the driver hasn't any stale locks. */ |
Matt Carlson | 78f94dc | 2011-11-04 09:14:58 +0000 | [diff] [blame] | 631 | for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) { |
| 632 | switch (i) { |
| 633 | case TG3_APE_LOCK_PHY0: |
| 634 | case TG3_APE_LOCK_PHY1: |
| 635 | case TG3_APE_LOCK_PHY2: |
| 636 | case TG3_APE_LOCK_PHY3: |
| 637 | bit = APE_LOCK_GRANT_DRIVER; |
| 638 | break; |
| 639 | default: |
| 640 | if (!tp->pci_fn) |
| 641 | bit = APE_LOCK_GRANT_DRIVER; |
| 642 | else |
| 643 | bit = 1 << tp->pci_fn; |
| 644 | } |
| 645 | tg3_ape_write32(tp, regbase + 4 * i, bit); |
Matt Carlson | 6f5c8f83 | 2011-07-13 09:27:31 +0000 | [diff] [blame] | 646 | } |
| 647 | |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 648 | } |
| 649 | |
| 650 | static int tg3_ape_lock(struct tg3 *tp, int locknum) |
| 651 | { |
| 652 | int i, off; |
| 653 | int ret = 0; |
Matt Carlson | 6f5c8f83 | 2011-07-13 09:27:31 +0000 | [diff] [blame] | 654 | u32 status, req, gnt, bit; |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 655 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 656 | if (!tg3_flag(tp, ENABLE_APE)) |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 657 | return 0; |
| 658 | |
| 659 | switch (locknum) { |
Matt Carlson | 6f5c8f83 | 2011-07-13 09:27:31 +0000 | [diff] [blame] | 660 | case TG3_APE_LOCK_GPIO: |
| 661 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
| 662 | return 0; |
Matt Carlson | 33f401a | 2010-04-05 10:19:27 +0000 | [diff] [blame] | 663 | case TG3_APE_LOCK_GRC: |
| 664 | case TG3_APE_LOCK_MEM: |
Matt Carlson | 78f94dc | 2011-11-04 09:14:58 +0000 | [diff] [blame] | 665 | if (!tp->pci_fn) |
| 666 | bit = APE_LOCK_REQ_DRIVER; |
| 667 | else |
| 668 | bit = 1 << tp->pci_fn; |
Matt Carlson | 33f401a | 2010-04-05 10:19:27 +0000 | [diff] [blame] | 669 | break; |
| 670 | default: |
| 671 | return -EINVAL; |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 672 | } |
| 673 | |
Matt Carlson | f92d9dc1 | 2010-06-05 17:24:30 +0000 | [diff] [blame] | 674 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { |
| 675 | req = TG3_APE_LOCK_REQ; |
| 676 | gnt = TG3_APE_LOCK_GRANT; |
| 677 | } else { |
| 678 | req = TG3_APE_PER_LOCK_REQ; |
| 679 | gnt = TG3_APE_PER_LOCK_GRANT; |
| 680 | } |
| 681 | |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 682 | off = 4 * locknum; |
| 683 | |
Matt Carlson | 6f5c8f83 | 2011-07-13 09:27:31 +0000 | [diff] [blame] | 684 | tg3_ape_write32(tp, req + off, bit); |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 685 | |
| 686 | /* Wait for up to 1 millisecond to acquire lock. */ |
| 687 | for (i = 0; i < 100; i++) { |
Matt Carlson | f92d9dc1 | 2010-06-05 17:24:30 +0000 | [diff] [blame] | 688 | status = tg3_ape_read32(tp, gnt + off); |
Matt Carlson | 6f5c8f83 | 2011-07-13 09:27:31 +0000 | [diff] [blame] | 689 | if (status == bit) |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 690 | break; |
| 691 | udelay(10); |
| 692 | } |
| 693 | |
Matt Carlson | 6f5c8f83 | 2011-07-13 09:27:31 +0000 | [diff] [blame] | 694 | if (status != bit) { |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 695 | /* Revoke the lock request. */ |
Matt Carlson | 6f5c8f83 | 2011-07-13 09:27:31 +0000 | [diff] [blame] | 696 | tg3_ape_write32(tp, gnt + off, bit); |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 697 | ret = -EBUSY; |
| 698 | } |
| 699 | |
| 700 | return ret; |
| 701 | } |
| 702 | |
| 703 | static void tg3_ape_unlock(struct tg3 *tp, int locknum) |
| 704 | { |
Matt Carlson | 6f5c8f83 | 2011-07-13 09:27:31 +0000 | [diff] [blame] | 705 | u32 gnt, bit; |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 706 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 707 | if (!tg3_flag(tp, ENABLE_APE)) |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 708 | return; |
| 709 | |
| 710 | switch (locknum) { |
Matt Carlson | 6f5c8f83 | 2011-07-13 09:27:31 +0000 | [diff] [blame] | 711 | case TG3_APE_LOCK_GPIO: |
| 712 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
| 713 | return; |
Matt Carlson | 33f401a | 2010-04-05 10:19:27 +0000 | [diff] [blame] | 714 | case TG3_APE_LOCK_GRC: |
| 715 | case TG3_APE_LOCK_MEM: |
Matt Carlson | 78f94dc | 2011-11-04 09:14:58 +0000 | [diff] [blame] | 716 | if (!tp->pci_fn) |
| 717 | bit = APE_LOCK_GRANT_DRIVER; |
| 718 | else |
| 719 | bit = 1 << tp->pci_fn; |
Matt Carlson | 33f401a | 2010-04-05 10:19:27 +0000 | [diff] [blame] | 720 | break; |
| 721 | default: |
| 722 | return; |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 723 | } |
| 724 | |
Matt Carlson | f92d9dc1 | 2010-06-05 17:24:30 +0000 | [diff] [blame] | 725 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
| 726 | gnt = TG3_APE_LOCK_GRANT; |
| 727 | else |
| 728 | gnt = TG3_APE_PER_LOCK_GRANT; |
| 729 | |
Matt Carlson | 6f5c8f83 | 2011-07-13 09:27:31 +0000 | [diff] [blame] | 730 | tg3_ape_write32(tp, gnt + 4 * locknum, bit); |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 731 | } |
| 732 | |
Matt Carlson | fd6d3f0 | 2011-08-31 11:44:52 +0000 | [diff] [blame] | 733 | static void tg3_ape_send_event(struct tg3 *tp, u32 event) |
| 734 | { |
| 735 | int i; |
| 736 | u32 apedata; |
| 737 | |
| 738 | /* NCSI does not support APE events */ |
| 739 | if (tg3_flag(tp, APE_HAS_NCSI)) |
| 740 | return; |
| 741 | |
| 742 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); |
| 743 | if (apedata != APE_SEG_SIG_MAGIC) |
| 744 | return; |
| 745 | |
| 746 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); |
| 747 | if (!(apedata & APE_FW_STATUS_READY)) |
| 748 | return; |
| 749 | |
| 750 | /* Wait for up to 1 millisecond for APE to service previous event. */ |
| 751 | for (i = 0; i < 10; i++) { |
| 752 | if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) |
| 753 | return; |
| 754 | |
| 755 | apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); |
| 756 | |
| 757 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) |
| 758 | tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, |
| 759 | event | APE_EVENT_STATUS_EVENT_PENDING); |
| 760 | |
| 761 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); |
| 762 | |
| 763 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) |
| 764 | break; |
| 765 | |
| 766 | udelay(100); |
| 767 | } |
| 768 | |
| 769 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) |
| 770 | tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); |
| 771 | } |
| 772 | |
| 773 | static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) |
| 774 | { |
| 775 | u32 event; |
| 776 | u32 apedata; |
| 777 | |
| 778 | if (!tg3_flag(tp, ENABLE_APE)) |
| 779 | return; |
| 780 | |
| 781 | switch (kind) { |
| 782 | case RESET_KIND_INIT: |
| 783 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, |
| 784 | APE_HOST_SEG_SIG_MAGIC); |
| 785 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, |
| 786 | APE_HOST_SEG_LEN_MAGIC); |
| 787 | apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); |
| 788 | tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); |
| 789 | tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, |
| 790 | APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM)); |
| 791 | tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, |
| 792 | APE_HOST_BEHAV_NO_PHYLOCK); |
| 793 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, |
| 794 | TG3_APE_HOST_DRVR_STATE_START); |
| 795 | |
| 796 | event = APE_EVENT_STATUS_STATE_START; |
| 797 | break; |
| 798 | case RESET_KIND_SHUTDOWN: |
| 799 | /* With the interface we are currently using, |
| 800 | * APE does not track driver state. Wiping |
| 801 | * out the HOST SEGMENT SIGNATURE forces |
| 802 | * the APE to assume OS absent status. |
| 803 | */ |
| 804 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); |
| 805 | |
| 806 | if (device_may_wakeup(&tp->pdev->dev) && |
| 807 | tg3_flag(tp, WOL_ENABLE)) { |
| 808 | tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED, |
| 809 | TG3_APE_HOST_WOL_SPEED_AUTO); |
| 810 | apedata = TG3_APE_HOST_DRVR_STATE_WOL; |
| 811 | } else |
| 812 | apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD; |
| 813 | |
| 814 | tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata); |
| 815 | |
| 816 | event = APE_EVENT_STATUS_STATE_UNLOAD; |
| 817 | break; |
| 818 | case RESET_KIND_SUSPEND: |
| 819 | event = APE_EVENT_STATUS_STATE_SUSPEND; |
| 820 | break; |
| 821 | default: |
| 822 | return; |
| 823 | } |
| 824 | |
| 825 | event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; |
| 826 | |
| 827 | tg3_ape_send_event(tp, event); |
| 828 | } |
| 829 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 830 | static void tg3_disable_ints(struct tg3 *tp) |
| 831 | { |
Matt Carlson | 89aeb3b | 2009-09-01 13:08:58 +0000 | [diff] [blame] | 832 | int i; |
| 833 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 834 | tw32(TG3PCI_MISC_HOST_CTRL, |
| 835 | (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); |
Matt Carlson | 89aeb3b | 2009-09-01 13:08:58 +0000 | [diff] [blame] | 836 | for (i = 0; i < tp->irq_max; i++) |
| 837 | tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 838 | } |
| 839 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 840 | static void tg3_enable_ints(struct tg3 *tp) |
| 841 | { |
Matt Carlson | 89aeb3b | 2009-09-01 13:08:58 +0000 | [diff] [blame] | 842 | int i; |
Matt Carlson | 89aeb3b | 2009-09-01 13:08:58 +0000 | [diff] [blame] | 843 | |
Michael Chan | bbe832c | 2005-06-24 20:20:04 -0700 | [diff] [blame] | 844 | tp->irq_sync = 0; |
| 845 | wmb(); |
| 846 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 847 | tw32(TG3PCI_MISC_HOST_CTRL, |
| 848 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); |
Matt Carlson | f19af9c | 2009-09-01 12:47:49 +0000 | [diff] [blame] | 849 | |
Matt Carlson | f89f38b | 2010-02-12 14:47:07 +0000 | [diff] [blame] | 850 | tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; |
Matt Carlson | 89aeb3b | 2009-09-01 13:08:58 +0000 | [diff] [blame] | 851 | for (i = 0; i < tp->irq_cnt; i++) { |
| 852 | struct tg3_napi *tnapi = &tp->napi[i]; |
Matt Carlson | c6cdf43 | 2010-04-05 10:19:26 +0000 | [diff] [blame] | 853 | |
Matt Carlson | 89aeb3b | 2009-09-01 13:08:58 +0000 | [diff] [blame] | 854 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 855 | if (tg3_flag(tp, 1SHOT_MSI)) |
Matt Carlson | 89aeb3b | 2009-09-01 13:08:58 +0000 | [diff] [blame] | 856 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
| 857 | |
Matt Carlson | f89f38b | 2010-02-12 14:47:07 +0000 | [diff] [blame] | 858 | tp->coal_now |= tnapi->coal_now; |
Matt Carlson | 89aeb3b | 2009-09-01 13:08:58 +0000 | [diff] [blame] | 859 | } |
Matt Carlson | f19af9c | 2009-09-01 12:47:49 +0000 | [diff] [blame] | 860 | |
| 861 | /* Force an initial interrupt */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 862 | if (!tg3_flag(tp, TAGGED_STATUS) && |
Matt Carlson | f19af9c | 2009-09-01 12:47:49 +0000 | [diff] [blame] | 863 | (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) |
| 864 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); |
| 865 | else |
Matt Carlson | f89f38b | 2010-02-12 14:47:07 +0000 | [diff] [blame] | 866 | tw32(HOSTCC_MODE, tp->coal_now); |
| 867 | |
| 868 | tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 869 | } |
| 870 | |
Matt Carlson | 17375d2 | 2009-08-28 14:02:18 +0000 | [diff] [blame] | 871 | static inline unsigned int tg3_has_work(struct tg3_napi *tnapi) |
Michael Chan | 04237dd | 2005-04-25 15:17:17 -0700 | [diff] [blame] | 872 | { |
Matt Carlson | 17375d2 | 2009-08-28 14:02:18 +0000 | [diff] [blame] | 873 | struct tg3 *tp = tnapi->tp; |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 874 | struct tg3_hw_status *sblk = tnapi->hw_status; |
Michael Chan | 04237dd | 2005-04-25 15:17:17 -0700 | [diff] [blame] | 875 | unsigned int work_exists = 0; |
| 876 | |
| 877 | /* check for phy events */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 878 | if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { |
Michael Chan | 04237dd | 2005-04-25 15:17:17 -0700 | [diff] [blame] | 879 | if (sblk->status & SD_STATUS_LINK_CHG) |
| 880 | work_exists = 1; |
| 881 | } |
| 882 | /* check for RX/TX work to do */ |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 883 | if (sblk->idx[0].tx_consumer != tnapi->tx_cons || |
Matt Carlson | 8d9d7cf | 2009-09-01 13:19:05 +0000 | [diff] [blame] | 884 | *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
Michael Chan | 04237dd | 2005-04-25 15:17:17 -0700 | [diff] [blame] | 885 | work_exists = 1; |
| 886 | |
| 887 | return work_exists; |
| 888 | } |
| 889 | |
Matt Carlson | 17375d2 | 2009-08-28 14:02:18 +0000 | [diff] [blame] | 890 | /* tg3_int_reenable |
Michael Chan | 04237dd | 2005-04-25 15:17:17 -0700 | [diff] [blame] | 891 | * similar to tg3_enable_ints, but it accurately determines whether there |
| 892 | * is new work pending and can return without flushing the PIO write |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 893 | * which reenables interrupts |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 894 | */ |
Matt Carlson | 17375d2 | 2009-08-28 14:02:18 +0000 | [diff] [blame] | 895 | static void tg3_int_reenable(struct tg3_napi *tnapi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 896 | { |
Matt Carlson | 17375d2 | 2009-08-28 14:02:18 +0000 | [diff] [blame] | 897 | struct tg3 *tp = tnapi->tp; |
| 898 | |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 899 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 900 | mmiowb(); |
| 901 | |
David S. Miller | fac9b83 | 2005-05-18 22:46:34 -0700 | [diff] [blame] | 902 | /* When doing tagged status, this work check is unnecessary. |
| 903 | * The last_tag we write above tells the chip which piece of |
| 904 | * work we've completed. |
| 905 | */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 906 | if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi)) |
Michael Chan | 04237dd | 2005-04-25 15:17:17 -0700 | [diff] [blame] | 907 | tw32(HOSTCC_MODE, tp->coalesce_mode | |
Matt Carlson | fd2ce37 | 2009-09-01 12:51:13 +0000 | [diff] [blame] | 908 | HOSTCC_MODE_ENABLE | tnapi->coal_now); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 909 | } |
| 910 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 911 | static void tg3_switch_clocks(struct tg3 *tp) |
| 912 | { |
Matt Carlson | f6eb9b1 | 2009-09-01 13:19:53 +0000 | [diff] [blame] | 913 | u32 clock_ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 914 | u32 orig_clock_ctrl; |
| 915 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 916 | if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS)) |
Michael Chan | 4cf78e4 | 2005-07-25 12:29:19 -0700 | [diff] [blame] | 917 | return; |
| 918 | |
Matt Carlson | f6eb9b1 | 2009-09-01 13:19:53 +0000 | [diff] [blame] | 919 | clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); |
| 920 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 921 | orig_clock_ctrl = clock_ctrl; |
| 922 | clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | |
| 923 | CLOCK_CTRL_CLKRUN_OENABLE | |
| 924 | 0x1f); |
| 925 | tp->pci_clock_ctrl = clock_ctrl; |
| 926 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 927 | if (tg3_flag(tp, 5705_PLUS)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 928 | if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { |
Michael Chan | b401e9e | 2005-12-19 16:27:04 -0800 | [diff] [blame] | 929 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
| 930 | clock_ctrl | CLOCK_CTRL_625_CORE, 40); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 931 | } |
| 932 | } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { |
Michael Chan | b401e9e | 2005-12-19 16:27:04 -0800 | [diff] [blame] | 933 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
| 934 | clock_ctrl | |
| 935 | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK), |
| 936 | 40); |
| 937 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
| 938 | clock_ctrl | (CLOCK_CTRL_ALTCLK), |
| 939 | 40); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 940 | } |
Michael Chan | b401e9e | 2005-12-19 16:27:04 -0800 | [diff] [blame] | 941 | tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 942 | } |
| 943 | |
| 944 | #define PHY_BUSY_LOOPS 5000 |
| 945 | |
| 946 | static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) |
| 947 | { |
| 948 | u32 frame_val; |
| 949 | unsigned int loops; |
| 950 | int ret; |
| 951 | |
| 952 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
| 953 | tw32_f(MAC_MI_MODE, |
| 954 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); |
| 955 | udelay(80); |
| 956 | } |
| 957 | |
| 958 | *val = 0x0; |
| 959 | |
Matt Carlson | 882e979 | 2009-09-01 13:21:36 +0000 | [diff] [blame] | 960 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 961 | MI_COM_PHY_ADDR_MASK); |
| 962 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & |
| 963 | MI_COM_REG_ADDR_MASK); |
| 964 | frame_val |= (MI_COM_CMD_READ | MI_COM_START); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 965 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 966 | tw32_f(MAC_MI_COM, frame_val); |
| 967 | |
| 968 | loops = PHY_BUSY_LOOPS; |
| 969 | while (loops != 0) { |
| 970 | udelay(10); |
| 971 | frame_val = tr32(MAC_MI_COM); |
| 972 | |
| 973 | if ((frame_val & MI_COM_BUSY) == 0) { |
| 974 | udelay(5); |
| 975 | frame_val = tr32(MAC_MI_COM); |
| 976 | break; |
| 977 | } |
| 978 | loops -= 1; |
| 979 | } |
| 980 | |
| 981 | ret = -EBUSY; |
| 982 | if (loops != 0) { |
| 983 | *val = frame_val & MI_COM_DATA_MASK; |
| 984 | ret = 0; |
| 985 | } |
| 986 | |
| 987 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
| 988 | tw32_f(MAC_MI_MODE, tp->mi_mode); |
| 989 | udelay(80); |
| 990 | } |
| 991 | |
| 992 | return ret; |
| 993 | } |
| 994 | |
| 995 | static int tg3_writephy(struct tg3 *tp, int reg, u32 val) |
| 996 | { |
| 997 | u32 frame_val; |
| 998 | unsigned int loops; |
| 999 | int ret; |
| 1000 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 1001 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && |
Matt Carlson | 221c563 | 2011-06-13 13:39:01 +0000 | [diff] [blame] | 1002 | (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL)) |
Michael Chan | b5d3772 | 2006-09-27 16:06:21 -0700 | [diff] [blame] | 1003 | return 0; |
| 1004 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1005 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
| 1006 | tw32_f(MAC_MI_MODE, |
| 1007 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); |
| 1008 | udelay(80); |
| 1009 | } |
| 1010 | |
Matt Carlson | 882e979 | 2009-09-01 13:21:36 +0000 | [diff] [blame] | 1011 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1012 | MI_COM_PHY_ADDR_MASK); |
| 1013 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & |
| 1014 | MI_COM_REG_ADDR_MASK); |
| 1015 | frame_val |= (val & MI_COM_DATA_MASK); |
| 1016 | frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 1017 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1018 | tw32_f(MAC_MI_COM, frame_val); |
| 1019 | |
| 1020 | loops = PHY_BUSY_LOOPS; |
| 1021 | while (loops != 0) { |
| 1022 | udelay(10); |
| 1023 | frame_val = tr32(MAC_MI_COM); |
| 1024 | if ((frame_val & MI_COM_BUSY) == 0) { |
| 1025 | udelay(5); |
| 1026 | frame_val = tr32(MAC_MI_COM); |
| 1027 | break; |
| 1028 | } |
| 1029 | loops -= 1; |
| 1030 | } |
| 1031 | |
| 1032 | ret = -EBUSY; |
| 1033 | if (loops != 0) |
| 1034 | ret = 0; |
| 1035 | |
| 1036 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
| 1037 | tw32_f(MAC_MI_MODE, tp->mi_mode); |
| 1038 | udelay(80); |
| 1039 | } |
| 1040 | |
| 1041 | return ret; |
| 1042 | } |
| 1043 | |
Matt Carlson | b0988c1 | 2011-04-20 07:57:39 +0000 | [diff] [blame] | 1044 | static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) |
| 1045 | { |
| 1046 | int err; |
| 1047 | |
| 1048 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); |
| 1049 | if (err) |
| 1050 | goto done; |
| 1051 | |
| 1052 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); |
| 1053 | if (err) |
| 1054 | goto done; |
| 1055 | |
| 1056 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, |
| 1057 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); |
| 1058 | if (err) |
| 1059 | goto done; |
| 1060 | |
| 1061 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); |
| 1062 | |
| 1063 | done: |
| 1064 | return err; |
| 1065 | } |
| 1066 | |
| 1067 | static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) |
| 1068 | { |
| 1069 | int err; |
| 1070 | |
| 1071 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); |
| 1072 | if (err) |
| 1073 | goto done; |
| 1074 | |
| 1075 | err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); |
| 1076 | if (err) |
| 1077 | goto done; |
| 1078 | |
| 1079 | err = tg3_writephy(tp, MII_TG3_MMD_CTRL, |
| 1080 | MII_TG3_MMD_CTRL_DATA_NOINC | devad); |
| 1081 | if (err) |
| 1082 | goto done; |
| 1083 | |
| 1084 | err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val); |
| 1085 | |
| 1086 | done: |
| 1087 | return err; |
| 1088 | } |
| 1089 | |
| 1090 | static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) |
| 1091 | { |
| 1092 | int err; |
| 1093 | |
| 1094 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); |
| 1095 | if (!err) |
| 1096 | err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); |
| 1097 | |
| 1098 | return err; |
| 1099 | } |
| 1100 | |
| 1101 | static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) |
| 1102 | { |
| 1103 | int err; |
| 1104 | |
| 1105 | err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); |
| 1106 | if (!err) |
| 1107 | err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); |
| 1108 | |
| 1109 | return err; |
| 1110 | } |
| 1111 | |
Matt Carlson | 15ee95c | 2011-04-20 07:57:40 +0000 | [diff] [blame] | 1112 | static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val) |
| 1113 | { |
| 1114 | int err; |
| 1115 | |
| 1116 | err = tg3_writephy(tp, MII_TG3_AUX_CTRL, |
| 1117 | (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) | |
| 1118 | MII_TG3_AUXCTL_SHDWSEL_MISC); |
| 1119 | if (!err) |
| 1120 | err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val); |
| 1121 | |
| 1122 | return err; |
| 1123 | } |
| 1124 | |
Matt Carlson | b4bd292 | 2011-04-20 07:57:41 +0000 | [diff] [blame] | 1125 | static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) |
| 1126 | { |
| 1127 | if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) |
| 1128 | set |= MII_TG3_AUXCTL_MISC_WREN; |
| 1129 | |
| 1130 | return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); |
| 1131 | } |
| 1132 | |
Matt Carlson | 1d36ba4 | 2011-04-20 07:57:42 +0000 | [diff] [blame] | 1133 | #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \ |
| 1134 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ |
| 1135 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \ |
| 1136 | MII_TG3_AUXCTL_ACTL_TX_6DB) |
| 1137 | |
| 1138 | #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \ |
| 1139 | tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \ |
| 1140 | MII_TG3_AUXCTL_ACTL_TX_6DB); |
| 1141 | |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1142 | static int tg3_bmcr_reset(struct tg3 *tp) |
| 1143 | { |
| 1144 | u32 phy_control; |
| 1145 | int limit, err; |
| 1146 | |
| 1147 | /* OK, reset it, and poll the BMCR_RESET bit until it |
| 1148 | * clears or we time out. |
| 1149 | */ |
| 1150 | phy_control = BMCR_RESET; |
| 1151 | err = tg3_writephy(tp, MII_BMCR, phy_control); |
| 1152 | if (err != 0) |
| 1153 | return -EBUSY; |
| 1154 | |
| 1155 | limit = 5000; |
| 1156 | while (limit--) { |
| 1157 | err = tg3_readphy(tp, MII_BMCR, &phy_control); |
| 1158 | if (err != 0) |
| 1159 | return -EBUSY; |
| 1160 | |
| 1161 | if ((phy_control & BMCR_RESET) == 0) { |
| 1162 | udelay(40); |
| 1163 | break; |
| 1164 | } |
| 1165 | udelay(10); |
| 1166 | } |
Roel Kluin | d4675b5 | 2009-02-12 16:33:27 -0800 | [diff] [blame] | 1167 | if (limit < 0) |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1168 | return -EBUSY; |
| 1169 | |
| 1170 | return 0; |
| 1171 | } |
| 1172 | |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 1173 | static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg) |
| 1174 | { |
Francois Romieu | 3d16543 | 2009-01-19 16:56:50 -0800 | [diff] [blame] | 1175 | struct tg3 *tp = bp->priv; |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 1176 | u32 val; |
| 1177 | |
Matt Carlson | 24bb4fb | 2009-10-05 17:55:29 +0000 | [diff] [blame] | 1178 | spin_lock_bh(&tp->lock); |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 1179 | |
| 1180 | if (tg3_readphy(tp, reg, &val)) |
Matt Carlson | 24bb4fb | 2009-10-05 17:55:29 +0000 | [diff] [blame] | 1181 | val = -EIO; |
| 1182 | |
| 1183 | spin_unlock_bh(&tp->lock); |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 1184 | |
| 1185 | return val; |
| 1186 | } |
| 1187 | |
| 1188 | static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) |
| 1189 | { |
Francois Romieu | 3d16543 | 2009-01-19 16:56:50 -0800 | [diff] [blame] | 1190 | struct tg3 *tp = bp->priv; |
Matt Carlson | 24bb4fb | 2009-10-05 17:55:29 +0000 | [diff] [blame] | 1191 | u32 ret = 0; |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 1192 | |
Matt Carlson | 24bb4fb | 2009-10-05 17:55:29 +0000 | [diff] [blame] | 1193 | spin_lock_bh(&tp->lock); |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 1194 | |
| 1195 | if (tg3_writephy(tp, reg, val)) |
Matt Carlson | 24bb4fb | 2009-10-05 17:55:29 +0000 | [diff] [blame] | 1196 | ret = -EIO; |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 1197 | |
Matt Carlson | 24bb4fb | 2009-10-05 17:55:29 +0000 | [diff] [blame] | 1198 | spin_unlock_bh(&tp->lock); |
| 1199 | |
| 1200 | return ret; |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 1201 | } |
| 1202 | |
| 1203 | static int tg3_mdio_reset(struct mii_bus *bp) |
| 1204 | { |
| 1205 | return 0; |
| 1206 | } |
| 1207 | |
Matt Carlson | 9c61d6b | 2008-11-03 16:54:56 -0800 | [diff] [blame] | 1208 | static void tg3_mdio_config_5785(struct tg3 *tp) |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1209 | { |
| 1210 | u32 val; |
Matt Carlson | fcb389d | 2008-11-03 16:55:44 -0800 | [diff] [blame] | 1211 | struct phy_device *phydev; |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1212 | |
Matt Carlson | 3f0e3ad | 2009-11-02 14:24:36 +0000 | [diff] [blame] | 1213 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
Matt Carlson | fcb389d | 2008-11-03 16:55:44 -0800 | [diff] [blame] | 1214 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { |
Matt Carlson | 6a443a0 | 2010-02-17 15:17:04 +0000 | [diff] [blame] | 1215 | case PHY_ID_BCM50610: |
| 1216 | case PHY_ID_BCM50610M: |
Matt Carlson | fcb389d | 2008-11-03 16:55:44 -0800 | [diff] [blame] | 1217 | val = MAC_PHYCFG2_50610_LED_MODES; |
| 1218 | break; |
Matt Carlson | 6a443a0 | 2010-02-17 15:17:04 +0000 | [diff] [blame] | 1219 | case PHY_ID_BCMAC131: |
Matt Carlson | fcb389d | 2008-11-03 16:55:44 -0800 | [diff] [blame] | 1220 | val = MAC_PHYCFG2_AC131_LED_MODES; |
| 1221 | break; |
Matt Carlson | 6a443a0 | 2010-02-17 15:17:04 +0000 | [diff] [blame] | 1222 | case PHY_ID_RTL8211C: |
Matt Carlson | fcb389d | 2008-11-03 16:55:44 -0800 | [diff] [blame] | 1223 | val = MAC_PHYCFG2_RTL8211C_LED_MODES; |
| 1224 | break; |
Matt Carlson | 6a443a0 | 2010-02-17 15:17:04 +0000 | [diff] [blame] | 1225 | case PHY_ID_RTL8201E: |
Matt Carlson | fcb389d | 2008-11-03 16:55:44 -0800 | [diff] [blame] | 1226 | val = MAC_PHYCFG2_RTL8201E_LED_MODES; |
| 1227 | break; |
| 1228 | default: |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1229 | return; |
Matt Carlson | fcb389d | 2008-11-03 16:55:44 -0800 | [diff] [blame] | 1230 | } |
| 1231 | |
| 1232 | if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { |
| 1233 | tw32(MAC_PHYCFG2, val); |
| 1234 | |
| 1235 | val = tr32(MAC_PHYCFG1); |
Matt Carlson | bb85fbb | 2009-08-25 10:09:07 +0000 | [diff] [blame] | 1236 | val &= ~(MAC_PHYCFG1_RGMII_INT | |
| 1237 | MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK); |
| 1238 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT; |
Matt Carlson | fcb389d | 2008-11-03 16:55:44 -0800 | [diff] [blame] | 1239 | tw32(MAC_PHYCFG1, val); |
| 1240 | |
| 1241 | return; |
| 1242 | } |
| 1243 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 1244 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) |
Matt Carlson | fcb389d | 2008-11-03 16:55:44 -0800 | [diff] [blame] | 1245 | val |= MAC_PHYCFG2_EMODE_MASK_MASK | |
| 1246 | MAC_PHYCFG2_FMODE_MASK_MASK | |
| 1247 | MAC_PHYCFG2_GMODE_MASK_MASK | |
| 1248 | MAC_PHYCFG2_ACT_MASK_MASK | |
| 1249 | MAC_PHYCFG2_QUAL_MASK_MASK | |
| 1250 | MAC_PHYCFG2_INBAND_ENABLE; |
| 1251 | |
| 1252 | tw32(MAC_PHYCFG2, val); |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1253 | |
Matt Carlson | bb85fbb | 2009-08-25 10:09:07 +0000 | [diff] [blame] | 1254 | val = tr32(MAC_PHYCFG1); |
| 1255 | val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK | |
| 1256 | MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 1257 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { |
| 1258 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1259 | val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 1260 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1261 | val |= MAC_PHYCFG1_RGMII_SND_STAT_EN; |
| 1262 | } |
Matt Carlson | bb85fbb | 2009-08-25 10:09:07 +0000 | [diff] [blame] | 1263 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT | |
| 1264 | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV; |
| 1265 | tw32(MAC_PHYCFG1, val); |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1266 | |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1267 | val = tr32(MAC_EXT_RGMII_MODE); |
| 1268 | val &= ~(MAC_RGMII_MODE_RX_INT_B | |
| 1269 | MAC_RGMII_MODE_RX_QUALITY | |
| 1270 | MAC_RGMII_MODE_RX_ACTIVITY | |
| 1271 | MAC_RGMII_MODE_RX_ENG_DET | |
| 1272 | MAC_RGMII_MODE_TX_ENABLE | |
| 1273 | MAC_RGMII_MODE_TX_LOWPWR | |
| 1274 | MAC_RGMII_MODE_TX_RESET); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 1275 | if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { |
| 1276 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1277 | val |= MAC_RGMII_MODE_RX_INT_B | |
| 1278 | MAC_RGMII_MODE_RX_QUALITY | |
| 1279 | MAC_RGMII_MODE_RX_ACTIVITY | |
| 1280 | MAC_RGMII_MODE_RX_ENG_DET; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 1281 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1282 | val |= MAC_RGMII_MODE_TX_ENABLE | |
| 1283 | MAC_RGMII_MODE_TX_LOWPWR | |
| 1284 | MAC_RGMII_MODE_TX_RESET; |
| 1285 | } |
| 1286 | tw32(MAC_EXT_RGMII_MODE, val); |
| 1287 | } |
| 1288 | |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 1289 | static void tg3_mdio_start(struct tg3 *tp) |
| 1290 | { |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 1291 | tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; |
| 1292 | tw32_f(MAC_MI_MODE, tp->mi_mode); |
| 1293 | udelay(80); |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1294 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 1295 | if (tg3_flag(tp, MDIOBUS_INITED) && |
Matt Carlson | 9ea4818 | 2010-02-17 15:17:01 +0000 | [diff] [blame] | 1296 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
| 1297 | tg3_mdio_config_5785(tp); |
| 1298 | } |
| 1299 | |
| 1300 | static int tg3_mdio_init(struct tg3 *tp) |
| 1301 | { |
| 1302 | int i; |
| 1303 | u32 reg; |
| 1304 | struct phy_device *phydev; |
| 1305 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 1306 | if (tg3_flag(tp, 5717_PLUS)) { |
Matt Carlson | 9c7df91 | 2010-06-05 17:24:36 +0000 | [diff] [blame] | 1307 | u32 is_serdes; |
Matt Carlson | 882e979 | 2009-09-01 13:21:36 +0000 | [diff] [blame] | 1308 | |
Matt Carlson | 69f11c9 | 2011-07-13 09:27:30 +0000 | [diff] [blame] | 1309 | tp->phy_addr = tp->pci_fn + 1; |
Matt Carlson | 882e979 | 2009-09-01 13:21:36 +0000 | [diff] [blame] | 1310 | |
Matt Carlson | d1ec96a | 2010-01-12 10:11:38 +0000 | [diff] [blame] | 1311 | if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) |
| 1312 | is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; |
| 1313 | else |
| 1314 | is_serdes = tr32(TG3_CPMU_PHY_STRAP) & |
| 1315 | TG3_CPMU_PHY_STRAP_IS_SERDES; |
Matt Carlson | 882e979 | 2009-09-01 13:21:36 +0000 | [diff] [blame] | 1316 | if (is_serdes) |
| 1317 | tp->phy_addr += 7; |
| 1318 | } else |
Matt Carlson | 3f0e3ad | 2009-11-02 14:24:36 +0000 | [diff] [blame] | 1319 | tp->phy_addr = TG3_PHY_MII_ADDR; |
Matt Carlson | 882e979 | 2009-09-01 13:21:36 +0000 | [diff] [blame] | 1320 | |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 1321 | tg3_mdio_start(tp); |
| 1322 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 1323 | if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED)) |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 1324 | return 0; |
| 1325 | |
Lennert Buytenhek | 298cf9be | 2008-10-08 16:29:57 -0700 | [diff] [blame] | 1326 | tp->mdio_bus = mdiobus_alloc(); |
| 1327 | if (tp->mdio_bus == NULL) |
| 1328 | return -ENOMEM; |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 1329 | |
Lennert Buytenhek | 298cf9be | 2008-10-08 16:29:57 -0700 | [diff] [blame] | 1330 | tp->mdio_bus->name = "tg3 mdio bus"; |
| 1331 | snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 1332 | (tp->pdev->bus->number << 8) | tp->pdev->devfn); |
Lennert Buytenhek | 298cf9be | 2008-10-08 16:29:57 -0700 | [diff] [blame] | 1333 | tp->mdio_bus->priv = tp; |
| 1334 | tp->mdio_bus->parent = &tp->pdev->dev; |
| 1335 | tp->mdio_bus->read = &tg3_mdio_read; |
| 1336 | tp->mdio_bus->write = &tg3_mdio_write; |
| 1337 | tp->mdio_bus->reset = &tg3_mdio_reset; |
Matt Carlson | 3f0e3ad | 2009-11-02 14:24:36 +0000 | [diff] [blame] | 1338 | tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR); |
Lennert Buytenhek | 298cf9be | 2008-10-08 16:29:57 -0700 | [diff] [blame] | 1339 | tp->mdio_bus->irq = &tp->mdio_irq[0]; |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 1340 | |
| 1341 | for (i = 0; i < PHY_MAX_ADDR; i++) |
Lennert Buytenhek | 298cf9be | 2008-10-08 16:29:57 -0700 | [diff] [blame] | 1342 | tp->mdio_bus->irq[i] = PHY_POLL; |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 1343 | |
| 1344 | /* The bus registration will look for all the PHYs on the mdio bus. |
| 1345 | * Unfortunately, it does not ensure the PHY is powered up before |
| 1346 | * accessing the PHY ID registers. A chip reset is the |
| 1347 | * quickest way to bring the device back to an operational state.. |
| 1348 | */ |
| 1349 | if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) |
| 1350 | tg3_bmcr_reset(tp); |
| 1351 | |
Lennert Buytenhek | 298cf9be | 2008-10-08 16:29:57 -0700 | [diff] [blame] | 1352 | i = mdiobus_register(tp->mdio_bus); |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1353 | if (i) { |
Matt Carlson | ab96b24 | 2010-04-05 10:19:22 +0000 | [diff] [blame] | 1354 | dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); |
Matt Carlson | 9c61d6b | 2008-11-03 16:54:56 -0800 | [diff] [blame] | 1355 | mdiobus_free(tp->mdio_bus); |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1356 | return i; |
| 1357 | } |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 1358 | |
Matt Carlson | 3f0e3ad | 2009-11-02 14:24:36 +0000 | [diff] [blame] | 1359 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1360 | |
Matt Carlson | 9c61d6b | 2008-11-03 16:54:56 -0800 | [diff] [blame] | 1361 | if (!phydev || !phydev->drv) { |
Matt Carlson | ab96b24 | 2010-04-05 10:19:22 +0000 | [diff] [blame] | 1362 | dev_warn(&tp->pdev->dev, "No PHY devices\n"); |
Matt Carlson | 9c61d6b | 2008-11-03 16:54:56 -0800 | [diff] [blame] | 1363 | mdiobus_unregister(tp->mdio_bus); |
| 1364 | mdiobus_free(tp->mdio_bus); |
| 1365 | return -ENODEV; |
| 1366 | } |
| 1367 | |
| 1368 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { |
Matt Carlson | 6a443a0 | 2010-02-17 15:17:04 +0000 | [diff] [blame] | 1369 | case PHY_ID_BCM57780: |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 1370 | phydev->interface = PHY_INTERFACE_MODE_GMII; |
Matt Carlson | c704dc2 | 2009-11-02 14:32:12 +0000 | [diff] [blame] | 1371 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 1372 | break; |
Matt Carlson | 6a443a0 | 2010-02-17 15:17:04 +0000 | [diff] [blame] | 1373 | case PHY_ID_BCM50610: |
| 1374 | case PHY_ID_BCM50610M: |
Matt Carlson | 32e5a8d | 2009-11-02 14:31:39 +0000 | [diff] [blame] | 1375 | phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | |
Matt Carlson | c704dc2 | 2009-11-02 14:32:12 +0000 | [diff] [blame] | 1376 | PHY_BRCM_RX_REFCLK_UNUSED | |
Matt Carlson | 52fae08 | 2009-11-02 14:32:38 +0000 | [diff] [blame] | 1377 | PHY_BRCM_DIS_TXCRXC_NOENRGY | |
Matt Carlson | c704dc2 | 2009-11-02 14:32:12 +0000 | [diff] [blame] | 1378 | PHY_BRCM_AUTO_PWRDWN_ENABLE; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 1379 | if (tg3_flag(tp, RGMII_INBAND_DISABLE)) |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1380 | phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 1381 | if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1382 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 1383 | if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1384 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; |
Matt Carlson | fcb389d | 2008-11-03 16:55:44 -0800 | [diff] [blame] | 1385 | /* fallthru */ |
Matt Carlson | 6a443a0 | 2010-02-17 15:17:04 +0000 | [diff] [blame] | 1386 | case PHY_ID_RTL8211C: |
Matt Carlson | fcb389d | 2008-11-03 16:55:44 -0800 | [diff] [blame] | 1387 | phydev->interface = PHY_INTERFACE_MODE_RGMII; |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1388 | break; |
Matt Carlson | 6a443a0 | 2010-02-17 15:17:04 +0000 | [diff] [blame] | 1389 | case PHY_ID_RTL8201E: |
| 1390 | case PHY_ID_BCMAC131: |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1391 | phydev->interface = PHY_INTERFACE_MODE_MII; |
Matt Carlson | cdd4e09d | 2009-11-02 14:31:11 +0000 | [diff] [blame] | 1392 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 1393 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1394 | break; |
| 1395 | } |
| 1396 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 1397 | tg3_flag_set(tp, MDIOBUS_INITED); |
Matt Carlson | 9c61d6b | 2008-11-03 16:54:56 -0800 | [diff] [blame] | 1398 | |
| 1399 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
| 1400 | tg3_mdio_config_5785(tp); |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1401 | |
| 1402 | return 0; |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 1403 | } |
| 1404 | |
| 1405 | static void tg3_mdio_fini(struct tg3 *tp) |
| 1406 | { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 1407 | if (tg3_flag(tp, MDIOBUS_INITED)) { |
| 1408 | tg3_flag_clear(tp, MDIOBUS_INITED); |
Lennert Buytenhek | 298cf9be | 2008-10-08 16:29:57 -0700 | [diff] [blame] | 1409 | mdiobus_unregister(tp->mdio_bus); |
| 1410 | mdiobus_free(tp->mdio_bus); |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 1411 | } |
| 1412 | } |
| 1413 | |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1414 | /* tp->lock is held. */ |
Matt Carlson | 4ba526c | 2008-08-15 14:10:04 -0700 | [diff] [blame] | 1415 | static inline void tg3_generate_fw_event(struct tg3 *tp) |
| 1416 | { |
| 1417 | u32 val; |
| 1418 | |
| 1419 | val = tr32(GRC_RX_CPU_EVENT); |
| 1420 | val |= GRC_RX_CPU_DRIVER_EVENT; |
| 1421 | tw32_f(GRC_RX_CPU_EVENT, val); |
| 1422 | |
| 1423 | tp->last_event_jiffies = jiffies; |
| 1424 | } |
| 1425 | |
| 1426 | #define TG3_FW_EVENT_TIMEOUT_USEC 2500 |
| 1427 | |
| 1428 | /* tp->lock is held. */ |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1429 | static void tg3_wait_for_event_ack(struct tg3 *tp) |
| 1430 | { |
| 1431 | int i; |
Matt Carlson | 4ba526c | 2008-08-15 14:10:04 -0700 | [diff] [blame] | 1432 | unsigned int delay_cnt; |
| 1433 | long time_remain; |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1434 | |
Matt Carlson | 4ba526c | 2008-08-15 14:10:04 -0700 | [diff] [blame] | 1435 | /* If enough time has passed, no wait is necessary. */ |
| 1436 | time_remain = (long)(tp->last_event_jiffies + 1 + |
| 1437 | usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - |
| 1438 | (long)jiffies; |
| 1439 | if (time_remain < 0) |
| 1440 | return; |
| 1441 | |
| 1442 | /* Check if we can shorten the wait time. */ |
| 1443 | delay_cnt = jiffies_to_usecs(time_remain); |
| 1444 | if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC) |
| 1445 | delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC; |
| 1446 | delay_cnt = (delay_cnt >> 3) + 1; |
| 1447 | |
| 1448 | for (i = 0; i < delay_cnt; i++) { |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1449 | if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) |
| 1450 | break; |
Matt Carlson | 4ba526c | 2008-08-15 14:10:04 -0700 | [diff] [blame] | 1451 | udelay(8); |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1452 | } |
| 1453 | } |
| 1454 | |
| 1455 | /* tp->lock is held. */ |
| 1456 | static void tg3_ump_link_report(struct tg3 *tp) |
| 1457 | { |
| 1458 | u32 reg; |
| 1459 | u32 val; |
| 1460 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 1461 | if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF)) |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1462 | return; |
| 1463 | |
| 1464 | tg3_wait_for_event_ack(tp); |
| 1465 | |
| 1466 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); |
| 1467 | |
| 1468 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); |
| 1469 | |
| 1470 | val = 0; |
| 1471 | if (!tg3_readphy(tp, MII_BMCR, ®)) |
| 1472 | val = reg << 16; |
| 1473 | if (!tg3_readphy(tp, MII_BMSR, ®)) |
| 1474 | val |= (reg & 0xffff); |
| 1475 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val); |
| 1476 | |
| 1477 | val = 0; |
| 1478 | if (!tg3_readphy(tp, MII_ADVERTISE, ®)) |
| 1479 | val = reg << 16; |
| 1480 | if (!tg3_readphy(tp, MII_LPA, ®)) |
| 1481 | val |= (reg & 0xffff); |
| 1482 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val); |
| 1483 | |
| 1484 | val = 0; |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 1485 | if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1486 | if (!tg3_readphy(tp, MII_CTRL1000, ®)) |
| 1487 | val = reg << 16; |
| 1488 | if (!tg3_readphy(tp, MII_STAT1000, ®)) |
| 1489 | val |= (reg & 0xffff); |
| 1490 | } |
| 1491 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val); |
| 1492 | |
| 1493 | if (!tg3_readphy(tp, MII_PHYADDR, ®)) |
| 1494 | val = reg << 16; |
| 1495 | else |
| 1496 | val = 0; |
| 1497 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val); |
| 1498 | |
Matt Carlson | 4ba526c | 2008-08-15 14:10:04 -0700 | [diff] [blame] | 1499 | tg3_generate_fw_event(tp); |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1500 | } |
| 1501 | |
Matt Carlson | 8d5a89b | 2011-08-31 11:44:51 +0000 | [diff] [blame] | 1502 | /* tp->lock is held. */ |
| 1503 | static void tg3_stop_fw(struct tg3 *tp) |
| 1504 | { |
| 1505 | if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { |
| 1506 | /* Wait for RX cpu to ACK the previous event. */ |
| 1507 | tg3_wait_for_event_ack(tp); |
| 1508 | |
| 1509 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); |
| 1510 | |
| 1511 | tg3_generate_fw_event(tp); |
| 1512 | |
| 1513 | /* Wait for RX cpu to ACK this event. */ |
| 1514 | tg3_wait_for_event_ack(tp); |
| 1515 | } |
| 1516 | } |
| 1517 | |
Matt Carlson | fd6d3f0 | 2011-08-31 11:44:52 +0000 | [diff] [blame] | 1518 | /* tp->lock is held. */ |
| 1519 | static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) |
| 1520 | { |
| 1521 | tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, |
| 1522 | NIC_SRAM_FIRMWARE_MBOX_MAGIC1); |
| 1523 | |
| 1524 | if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { |
| 1525 | switch (kind) { |
| 1526 | case RESET_KIND_INIT: |
| 1527 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, |
| 1528 | DRV_STATE_START); |
| 1529 | break; |
| 1530 | |
| 1531 | case RESET_KIND_SHUTDOWN: |
| 1532 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, |
| 1533 | DRV_STATE_UNLOAD); |
| 1534 | break; |
| 1535 | |
| 1536 | case RESET_KIND_SUSPEND: |
| 1537 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, |
| 1538 | DRV_STATE_SUSPEND); |
| 1539 | break; |
| 1540 | |
| 1541 | default: |
| 1542 | break; |
| 1543 | } |
| 1544 | } |
| 1545 | |
| 1546 | if (kind == RESET_KIND_INIT || |
| 1547 | kind == RESET_KIND_SUSPEND) |
| 1548 | tg3_ape_driver_state_change(tp, kind); |
| 1549 | } |
| 1550 | |
| 1551 | /* tp->lock is held. */ |
| 1552 | static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) |
| 1553 | { |
| 1554 | if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { |
| 1555 | switch (kind) { |
| 1556 | case RESET_KIND_INIT: |
| 1557 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, |
| 1558 | DRV_STATE_START_DONE); |
| 1559 | break; |
| 1560 | |
| 1561 | case RESET_KIND_SHUTDOWN: |
| 1562 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, |
| 1563 | DRV_STATE_UNLOAD_DONE); |
| 1564 | break; |
| 1565 | |
| 1566 | default: |
| 1567 | break; |
| 1568 | } |
| 1569 | } |
| 1570 | |
| 1571 | if (kind == RESET_KIND_SHUTDOWN) |
| 1572 | tg3_ape_driver_state_change(tp, kind); |
| 1573 | } |
| 1574 | |
| 1575 | /* tp->lock is held. */ |
| 1576 | static void tg3_write_sig_legacy(struct tg3 *tp, int kind) |
| 1577 | { |
| 1578 | if (tg3_flag(tp, ENABLE_ASF)) { |
| 1579 | switch (kind) { |
| 1580 | case RESET_KIND_INIT: |
| 1581 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, |
| 1582 | DRV_STATE_START); |
| 1583 | break; |
| 1584 | |
| 1585 | case RESET_KIND_SHUTDOWN: |
| 1586 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, |
| 1587 | DRV_STATE_UNLOAD); |
| 1588 | break; |
| 1589 | |
| 1590 | case RESET_KIND_SUSPEND: |
| 1591 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, |
| 1592 | DRV_STATE_SUSPEND); |
| 1593 | break; |
| 1594 | |
| 1595 | default: |
| 1596 | break; |
| 1597 | } |
| 1598 | } |
| 1599 | } |
| 1600 | |
| 1601 | static int tg3_poll_fw(struct tg3 *tp) |
| 1602 | { |
| 1603 | int i; |
| 1604 | u32 val; |
| 1605 | |
| 1606 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
| 1607 | /* Wait up to 20ms for init done. */ |
| 1608 | for (i = 0; i < 200; i++) { |
| 1609 | if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) |
| 1610 | return 0; |
| 1611 | udelay(100); |
| 1612 | } |
| 1613 | return -ENODEV; |
| 1614 | } |
| 1615 | |
| 1616 | /* Wait for firmware initialization to complete. */ |
| 1617 | for (i = 0; i < 100000; i++) { |
| 1618 | tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); |
| 1619 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) |
| 1620 | break; |
| 1621 | udelay(10); |
| 1622 | } |
| 1623 | |
| 1624 | /* Chip might not be fitted with firmware. Some Sun onboard |
| 1625 | * parts are configured like that. So don't signal the timeout |
| 1626 | * of the above loop as an error, but do report the lack of |
| 1627 | * running firmware once. |
| 1628 | */ |
| 1629 | if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) { |
| 1630 | tg3_flag_set(tp, NO_FWARE_REPORTED); |
| 1631 | |
| 1632 | netdev_info(tp->dev, "No firmware running\n"); |
| 1633 | } |
| 1634 | |
| 1635 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { |
| 1636 | /* The 57765 A0 needs a little more |
| 1637 | * time to do some important work. |
| 1638 | */ |
| 1639 | mdelay(10); |
| 1640 | } |
| 1641 | |
| 1642 | return 0; |
| 1643 | } |
| 1644 | |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1645 | static void tg3_link_report(struct tg3 *tp) |
| 1646 | { |
| 1647 | if (!netif_carrier_ok(tp->dev)) { |
Joe Perches | 05dbe00 | 2010-02-17 19:44:19 +0000 | [diff] [blame] | 1648 | netif_info(tp, link, tp->dev, "Link is down\n"); |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1649 | tg3_ump_link_report(tp); |
| 1650 | } else if (netif_msg_link(tp)) { |
Joe Perches | 05dbe00 | 2010-02-17 19:44:19 +0000 | [diff] [blame] | 1651 | netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", |
| 1652 | (tp->link_config.active_speed == SPEED_1000 ? |
| 1653 | 1000 : |
| 1654 | (tp->link_config.active_speed == SPEED_100 ? |
| 1655 | 100 : 10)), |
| 1656 | (tp->link_config.active_duplex == DUPLEX_FULL ? |
| 1657 | "full" : "half")); |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1658 | |
Joe Perches | 05dbe00 | 2010-02-17 19:44:19 +0000 | [diff] [blame] | 1659 | netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", |
| 1660 | (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? |
| 1661 | "on" : "off", |
| 1662 | (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? |
| 1663 | "on" : "off"); |
Matt Carlson | 4700783 | 2011-04-20 07:57:43 +0000 | [diff] [blame] | 1664 | |
| 1665 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) |
| 1666 | netdev_info(tp->dev, "EEE is %s\n", |
| 1667 | tp->setlpicnt ? "enabled" : "disabled"); |
| 1668 | |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1669 | tg3_ump_link_report(tp); |
| 1670 | } |
| 1671 | } |
| 1672 | |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1673 | static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) |
| 1674 | { |
| 1675 | u16 miireg; |
| 1676 | |
Steve Glendinning | e18ce34 | 2008-12-16 02:00:00 -0800 | [diff] [blame] | 1677 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1678 | miireg = ADVERTISE_1000XPAUSE; |
Steve Glendinning | e18ce34 | 2008-12-16 02:00:00 -0800 | [diff] [blame] | 1679 | else if (flow_ctrl & FLOW_CTRL_TX) |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1680 | miireg = ADVERTISE_1000XPSE_ASYM; |
Steve Glendinning | e18ce34 | 2008-12-16 02:00:00 -0800 | [diff] [blame] | 1681 | else if (flow_ctrl & FLOW_CTRL_RX) |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1682 | miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; |
| 1683 | else |
| 1684 | miireg = 0; |
| 1685 | |
| 1686 | return miireg; |
| 1687 | } |
| 1688 | |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1689 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) |
| 1690 | { |
| 1691 | u8 cap = 0; |
| 1692 | |
Matt Carlson | f3791cd | 2011-11-21 15:01:17 +0000 | [diff] [blame] | 1693 | if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) { |
| 1694 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
| 1695 | } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) { |
| 1696 | if (lcladv & ADVERTISE_1000XPAUSE) |
| 1697 | cap = FLOW_CTRL_RX; |
| 1698 | if (rmtadv & ADVERTISE_1000XPAUSE) |
Steve Glendinning | e18ce34 | 2008-12-16 02:00:00 -0800 | [diff] [blame] | 1699 | cap = FLOW_CTRL_TX; |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1700 | } |
| 1701 | |
| 1702 | return cap; |
| 1703 | } |
| 1704 | |
Matt Carlson | f51f356 | 2008-05-25 23:45:08 -0700 | [diff] [blame] | 1705 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1706 | { |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1707 | u8 autoneg; |
Matt Carlson | f51f356 | 2008-05-25 23:45:08 -0700 | [diff] [blame] | 1708 | u8 flowctrl = 0; |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1709 | u32 old_rx_mode = tp->rx_mode; |
| 1710 | u32 old_tx_mode = tp->tx_mode; |
| 1711 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 1712 | if (tg3_flag(tp, USE_PHYLIB)) |
Matt Carlson | 3f0e3ad | 2009-11-02 14:24:36 +0000 | [diff] [blame] | 1713 | autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1714 | else |
| 1715 | autoneg = tp->link_config.autoneg; |
| 1716 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 1717 | if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) { |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 1718 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
Matt Carlson | f51f356 | 2008-05-25 23:45:08 -0700 | [diff] [blame] | 1719 | flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1720 | else |
Steve Glendinning | bc02ff9 | 2008-12-16 02:00:48 -0800 | [diff] [blame] | 1721 | flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
Matt Carlson | f51f356 | 2008-05-25 23:45:08 -0700 | [diff] [blame] | 1722 | } else |
| 1723 | flowctrl = tp->link_config.flowctrl; |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1724 | |
Matt Carlson | f51f356 | 2008-05-25 23:45:08 -0700 | [diff] [blame] | 1725 | tp->link_config.active_flowctrl = flowctrl; |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1726 | |
Steve Glendinning | e18ce34 | 2008-12-16 02:00:00 -0800 | [diff] [blame] | 1727 | if (flowctrl & FLOW_CTRL_RX) |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1728 | tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; |
| 1729 | else |
| 1730 | tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; |
| 1731 | |
Matt Carlson | f51f356 | 2008-05-25 23:45:08 -0700 | [diff] [blame] | 1732 | if (old_rx_mode != tp->rx_mode) |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1733 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1734 | |
Steve Glendinning | e18ce34 | 2008-12-16 02:00:00 -0800 | [diff] [blame] | 1735 | if (flowctrl & FLOW_CTRL_TX) |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1736 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; |
| 1737 | else |
| 1738 | tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; |
| 1739 | |
Matt Carlson | f51f356 | 2008-05-25 23:45:08 -0700 | [diff] [blame] | 1740 | if (old_tx_mode != tp->tx_mode) |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1741 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
Matt Carlson | 95e2869 | 2008-05-25 23:44:14 -0700 | [diff] [blame] | 1742 | } |
| 1743 | |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1744 | static void tg3_adjust_link(struct net_device *dev) |
| 1745 | { |
| 1746 | u8 oldflowctrl, linkmesg = 0; |
| 1747 | u32 mac_mode, lcl_adv, rmt_adv; |
| 1748 | struct tg3 *tp = netdev_priv(dev); |
Matt Carlson | 3f0e3ad | 2009-11-02 14:24:36 +0000 | [diff] [blame] | 1749 | struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1750 | |
Matt Carlson | 24bb4fb | 2009-10-05 17:55:29 +0000 | [diff] [blame] | 1751 | spin_lock_bh(&tp->lock); |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1752 | |
| 1753 | mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | |
| 1754 | MAC_MODE_HALF_DUPLEX); |
| 1755 | |
| 1756 | oldflowctrl = tp->link_config.active_flowctrl; |
| 1757 | |
| 1758 | if (phydev->link) { |
| 1759 | lcl_adv = 0; |
| 1760 | rmt_adv = 0; |
| 1761 | |
| 1762 | if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) |
| 1763 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
Matt Carlson | c3df074 | 2009-11-02 14:27:02 +0000 | [diff] [blame] | 1764 | else if (phydev->speed == SPEED_1000 || |
| 1765 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1766 | mac_mode |= MAC_MODE_PORT_MODE_GMII; |
Matt Carlson | c3df074 | 2009-11-02 14:27:02 +0000 | [diff] [blame] | 1767 | else |
| 1768 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1769 | |
| 1770 | if (phydev->duplex == DUPLEX_HALF) |
| 1771 | mac_mode |= MAC_MODE_HALF_DUPLEX; |
| 1772 | else { |
Matt Carlson | f88788f | 2011-12-14 11:10:00 +0000 | [diff] [blame] | 1773 | lcl_adv = mii_advertise_flowctrl( |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1774 | tp->link_config.flowctrl); |
| 1775 | |
| 1776 | if (phydev->pause) |
| 1777 | rmt_adv = LPA_PAUSE_CAP; |
| 1778 | if (phydev->asym_pause) |
| 1779 | rmt_adv |= LPA_PAUSE_ASYM; |
| 1780 | } |
| 1781 | |
| 1782 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); |
| 1783 | } else |
| 1784 | mac_mode |= MAC_MODE_PORT_MODE_GMII; |
| 1785 | |
| 1786 | if (mac_mode != tp->mac_mode) { |
| 1787 | tp->mac_mode = mac_mode; |
| 1788 | tw32_f(MAC_MODE, tp->mac_mode); |
| 1789 | udelay(40); |
| 1790 | } |
| 1791 | |
Matt Carlson | fcb389d | 2008-11-03 16:55:44 -0800 | [diff] [blame] | 1792 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
| 1793 | if (phydev->speed == SPEED_10) |
| 1794 | tw32(MAC_MI_STAT, |
| 1795 | MAC_MI_STAT_10MBPS_MODE | |
| 1796 | MAC_MI_STAT_LNKSTAT_ATTN_ENAB); |
| 1797 | else |
| 1798 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); |
| 1799 | } |
| 1800 | |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1801 | if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) |
| 1802 | tw32(MAC_TX_LENGTHS, |
| 1803 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
| 1804 | (6 << TX_LENGTHS_IPG_SHIFT) | |
| 1805 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); |
| 1806 | else |
| 1807 | tw32(MAC_TX_LENGTHS, |
| 1808 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
| 1809 | (6 << TX_LENGTHS_IPG_SHIFT) | |
| 1810 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); |
| 1811 | |
| 1812 | if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) || |
| 1813 | (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) || |
| 1814 | phydev->speed != tp->link_config.active_speed || |
| 1815 | phydev->duplex != tp->link_config.active_duplex || |
| 1816 | oldflowctrl != tp->link_config.active_flowctrl) |
Matt Carlson | c6cdf43 | 2010-04-05 10:19:26 +0000 | [diff] [blame] | 1817 | linkmesg = 1; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1818 | |
| 1819 | tp->link_config.active_speed = phydev->speed; |
| 1820 | tp->link_config.active_duplex = phydev->duplex; |
| 1821 | |
Matt Carlson | 24bb4fb | 2009-10-05 17:55:29 +0000 | [diff] [blame] | 1822 | spin_unlock_bh(&tp->lock); |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1823 | |
| 1824 | if (linkmesg) |
| 1825 | tg3_link_report(tp); |
| 1826 | } |
| 1827 | |
| 1828 | static int tg3_phy_init(struct tg3 *tp) |
| 1829 | { |
| 1830 | struct phy_device *phydev; |
| 1831 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 1832 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1833 | return 0; |
| 1834 | |
| 1835 | /* Bring the PHY back to a known state. */ |
| 1836 | tg3_bmcr_reset(tp); |
| 1837 | |
Matt Carlson | 3f0e3ad | 2009-11-02 14:24:36 +0000 | [diff] [blame] | 1838 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1839 | |
| 1840 | /* Attach the MAC to the PHY. */ |
Kay Sievers | fb28ad3 | 2008-11-10 13:55:14 -0800 | [diff] [blame] | 1841 | phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link, |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 1842 | phydev->dev_flags, phydev->interface); |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1843 | if (IS_ERR(phydev)) { |
Matt Carlson | ab96b24 | 2010-04-05 10:19:22 +0000 | [diff] [blame] | 1844 | dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1845 | return PTR_ERR(phydev); |
| 1846 | } |
| 1847 | |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1848 | /* Mask with MAC supported features. */ |
Matt Carlson | 9c61d6b | 2008-11-03 16:54:56 -0800 | [diff] [blame] | 1849 | switch (phydev->interface) { |
| 1850 | case PHY_INTERFACE_MODE_GMII: |
| 1851 | case PHY_INTERFACE_MODE_RGMII: |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 1852 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 1853 | phydev->supported &= (PHY_GBIT_FEATURES | |
| 1854 | SUPPORTED_Pause | |
| 1855 | SUPPORTED_Asym_Pause); |
| 1856 | break; |
| 1857 | } |
| 1858 | /* fallthru */ |
Matt Carlson | 9c61d6b | 2008-11-03 16:54:56 -0800 | [diff] [blame] | 1859 | case PHY_INTERFACE_MODE_MII: |
| 1860 | phydev->supported &= (PHY_BASIC_FEATURES | |
| 1861 | SUPPORTED_Pause | |
| 1862 | SUPPORTED_Asym_Pause); |
| 1863 | break; |
| 1864 | default: |
Matt Carlson | 3f0e3ad | 2009-11-02 14:24:36 +0000 | [diff] [blame] | 1865 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
Matt Carlson | 9c61d6b | 2008-11-03 16:54:56 -0800 | [diff] [blame] | 1866 | return -EINVAL; |
| 1867 | } |
| 1868 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 1869 | tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1870 | |
| 1871 | phydev->advertising = phydev->supported; |
| 1872 | |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1873 | return 0; |
| 1874 | } |
| 1875 | |
| 1876 | static void tg3_phy_start(struct tg3 *tp) |
| 1877 | { |
| 1878 | struct phy_device *phydev; |
| 1879 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 1880 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1881 | return; |
| 1882 | |
Matt Carlson | 3f0e3ad | 2009-11-02 14:24:36 +0000 | [diff] [blame] | 1883 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1884 | |
Matt Carlson | 80096068 | 2010-08-02 11:26:06 +0000 | [diff] [blame] | 1885 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
| 1886 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1887 | phydev->speed = tp->link_config.orig_speed; |
| 1888 | phydev->duplex = tp->link_config.orig_duplex; |
| 1889 | phydev->autoneg = tp->link_config.orig_autoneg; |
| 1890 | phydev->advertising = tp->link_config.orig_advertising; |
| 1891 | } |
| 1892 | |
| 1893 | phy_start(phydev); |
| 1894 | |
| 1895 | phy_start_aneg(phydev); |
| 1896 | } |
| 1897 | |
| 1898 | static void tg3_phy_stop(struct tg3 *tp) |
| 1899 | { |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 1900 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1901 | return; |
| 1902 | |
Matt Carlson | 3f0e3ad | 2009-11-02 14:24:36 +0000 | [diff] [blame] | 1903 | phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1904 | } |
| 1905 | |
| 1906 | static void tg3_phy_fini(struct tg3 *tp) |
| 1907 | { |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 1908 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
Matt Carlson | 3f0e3ad | 2009-11-02 14:24:36 +0000 | [diff] [blame] | 1909 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 1910 | tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 1911 | } |
| 1912 | } |
| 1913 | |
Matt Carlson | 941ec90 | 2011-08-19 13:58:23 +0000 | [diff] [blame] | 1914 | static int tg3_phy_set_extloopbk(struct tg3 *tp) |
| 1915 | { |
| 1916 | int err; |
| 1917 | u32 val; |
| 1918 | |
| 1919 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) |
| 1920 | return 0; |
| 1921 | |
| 1922 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
| 1923 | /* Cannot do read-modify-write on 5401 */ |
| 1924 | err = tg3_phy_auxctl_write(tp, |
| 1925 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, |
| 1926 | MII_TG3_AUXCTL_ACTL_EXTLOOPBK | |
| 1927 | 0x4c20); |
| 1928 | goto done; |
| 1929 | } |
| 1930 | |
| 1931 | err = tg3_phy_auxctl_read(tp, |
| 1932 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); |
| 1933 | if (err) |
| 1934 | return err; |
| 1935 | |
| 1936 | val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK; |
| 1937 | err = tg3_phy_auxctl_write(tp, |
| 1938 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val); |
| 1939 | |
| 1940 | done: |
| 1941 | return err; |
| 1942 | } |
| 1943 | |
Matt Carlson | 7f97a4b | 2009-08-25 10:10:03 +0000 | [diff] [blame] | 1944 | static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) |
| 1945 | { |
| 1946 | u32 phytest; |
| 1947 | |
| 1948 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { |
| 1949 | u32 phy; |
| 1950 | |
| 1951 | tg3_writephy(tp, MII_TG3_FET_TEST, |
| 1952 | phytest | MII_TG3_FET_SHADOW_EN); |
| 1953 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { |
| 1954 | if (enable) |
| 1955 | phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD; |
| 1956 | else |
| 1957 | phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD; |
| 1958 | tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); |
| 1959 | } |
| 1960 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); |
| 1961 | } |
| 1962 | } |
| 1963 | |
Matt Carlson | 6833c04 | 2008-11-21 17:18:59 -0800 | [diff] [blame] | 1964 | static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) |
| 1965 | { |
| 1966 | u32 reg; |
| 1967 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 1968 | if (!tg3_flag(tp, 5705_PLUS) || |
| 1969 | (tg3_flag(tp, 5717_PLUS) && |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 1970 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
Matt Carlson | 6833c04 | 2008-11-21 17:18:59 -0800 | [diff] [blame] | 1971 | return; |
| 1972 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 1973 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
Matt Carlson | 7f97a4b | 2009-08-25 10:10:03 +0000 | [diff] [blame] | 1974 | tg3_phy_fet_toggle_apd(tp, enable); |
| 1975 | return; |
| 1976 | } |
| 1977 | |
Matt Carlson | 6833c04 | 2008-11-21 17:18:59 -0800 | [diff] [blame] | 1978 | reg = MII_TG3_MISC_SHDW_WREN | |
| 1979 | MII_TG3_MISC_SHDW_SCR5_SEL | |
| 1980 | MII_TG3_MISC_SHDW_SCR5_LPED | |
| 1981 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | |
| 1982 | MII_TG3_MISC_SHDW_SCR5_SDTL | |
| 1983 | MII_TG3_MISC_SHDW_SCR5_C125OE; |
| 1984 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable) |
| 1985 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; |
| 1986 | |
| 1987 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); |
| 1988 | |
| 1989 | |
| 1990 | reg = MII_TG3_MISC_SHDW_WREN | |
| 1991 | MII_TG3_MISC_SHDW_APD_SEL | |
| 1992 | MII_TG3_MISC_SHDW_APD_WKTM_84MS; |
| 1993 | if (enable) |
| 1994 | reg |= MII_TG3_MISC_SHDW_APD_ENABLE; |
| 1995 | |
| 1996 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); |
| 1997 | } |
| 1998 | |
Matt Carlson | 9ef8ca9 | 2007-07-11 19:48:29 -0700 | [diff] [blame] | 1999 | static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) |
| 2000 | { |
| 2001 | u32 phy; |
| 2002 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 2003 | if (!tg3_flag(tp, 5705_PLUS) || |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 2004 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
Matt Carlson | 9ef8ca9 | 2007-07-11 19:48:29 -0700 | [diff] [blame] | 2005 | return; |
| 2006 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 2007 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
Matt Carlson | 9ef8ca9 | 2007-07-11 19:48:29 -0700 | [diff] [blame] | 2008 | u32 ephy; |
| 2009 | |
Matt Carlson | 535ef6e | 2009-08-25 10:09:36 +0000 | [diff] [blame] | 2010 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { |
| 2011 | u32 reg = MII_TG3_FET_SHDW_MISCCTRL; |
| 2012 | |
| 2013 | tg3_writephy(tp, MII_TG3_FET_TEST, |
| 2014 | ephy | MII_TG3_FET_SHADOW_EN); |
| 2015 | if (!tg3_readphy(tp, reg, &phy)) { |
Matt Carlson | 9ef8ca9 | 2007-07-11 19:48:29 -0700 | [diff] [blame] | 2016 | if (enable) |
Matt Carlson | 535ef6e | 2009-08-25 10:09:36 +0000 | [diff] [blame] | 2017 | phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
Matt Carlson | 9ef8ca9 | 2007-07-11 19:48:29 -0700 | [diff] [blame] | 2018 | else |
Matt Carlson | 535ef6e | 2009-08-25 10:09:36 +0000 | [diff] [blame] | 2019 | phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
| 2020 | tg3_writephy(tp, reg, phy); |
Matt Carlson | 9ef8ca9 | 2007-07-11 19:48:29 -0700 | [diff] [blame] | 2021 | } |
Matt Carlson | 535ef6e | 2009-08-25 10:09:36 +0000 | [diff] [blame] | 2022 | tg3_writephy(tp, MII_TG3_FET_TEST, ephy); |
Matt Carlson | 9ef8ca9 | 2007-07-11 19:48:29 -0700 | [diff] [blame] | 2023 | } |
| 2024 | } else { |
Matt Carlson | 15ee95c | 2011-04-20 07:57:40 +0000 | [diff] [blame] | 2025 | int ret; |
| 2026 | |
| 2027 | ret = tg3_phy_auxctl_read(tp, |
| 2028 | MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); |
| 2029 | if (!ret) { |
Matt Carlson | 9ef8ca9 | 2007-07-11 19:48:29 -0700 | [diff] [blame] | 2030 | if (enable) |
| 2031 | phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX; |
| 2032 | else |
| 2033 | phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX; |
Matt Carlson | b4bd292 | 2011-04-20 07:57:41 +0000 | [diff] [blame] | 2034 | tg3_phy_auxctl_write(tp, |
| 2035 | MII_TG3_AUXCTL_SHDWSEL_MISC, phy); |
Matt Carlson | 9ef8ca9 | 2007-07-11 19:48:29 -0700 | [diff] [blame] | 2036 | } |
| 2037 | } |
| 2038 | } |
| 2039 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2040 | static void tg3_phy_set_wirespeed(struct tg3 *tp) |
| 2041 | { |
Matt Carlson | 15ee95c | 2011-04-20 07:57:40 +0000 | [diff] [blame] | 2042 | int ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2043 | u32 val; |
| 2044 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 2045 | if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2046 | return; |
| 2047 | |
Matt Carlson | 15ee95c | 2011-04-20 07:57:40 +0000 | [diff] [blame] | 2048 | ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); |
| 2049 | if (!ret) |
Matt Carlson | b4bd292 | 2011-04-20 07:57:41 +0000 | [diff] [blame] | 2050 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, |
| 2051 | val | MII_TG3_AUXCTL_MISC_WIRESPD_EN); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2052 | } |
| 2053 | |
Matt Carlson | b2a5c19 | 2008-04-03 21:44:44 -0700 | [diff] [blame] | 2054 | static void tg3_phy_apply_otp(struct tg3 *tp) |
| 2055 | { |
| 2056 | u32 otp, phy; |
| 2057 | |
| 2058 | if (!tp->phy_otp) |
| 2059 | return; |
| 2060 | |
| 2061 | otp = tp->phy_otp; |
| 2062 | |
Matt Carlson | 1d36ba4 | 2011-04-20 07:57:42 +0000 | [diff] [blame] | 2063 | if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) |
| 2064 | return; |
Matt Carlson | b2a5c19 | 2008-04-03 21:44:44 -0700 | [diff] [blame] | 2065 | |
| 2066 | phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT); |
| 2067 | phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT; |
| 2068 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); |
| 2069 | |
| 2070 | phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) | |
| 2071 | ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT); |
| 2072 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); |
| 2073 | |
| 2074 | phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT); |
| 2075 | phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ; |
| 2076 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); |
| 2077 | |
| 2078 | phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT); |
| 2079 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); |
| 2080 | |
| 2081 | phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT); |
| 2082 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); |
| 2083 | |
| 2084 | phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) | |
| 2085 | ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT); |
| 2086 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); |
| 2087 | |
Matt Carlson | 1d36ba4 | 2011-04-20 07:57:42 +0000 | [diff] [blame] | 2088 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
Matt Carlson | b2a5c19 | 2008-04-03 21:44:44 -0700 | [diff] [blame] | 2089 | } |
| 2090 | |
Matt Carlson | 52b02d0 | 2010-10-14 10:37:41 +0000 | [diff] [blame] | 2091 | static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) |
| 2092 | { |
| 2093 | u32 val; |
| 2094 | |
| 2095 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) |
| 2096 | return; |
| 2097 | |
| 2098 | tp->setlpicnt = 0; |
| 2099 | |
| 2100 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
| 2101 | current_link_up == 1 && |
Matt Carlson | a6b68da | 2010-12-06 08:28:52 +0000 | [diff] [blame] | 2102 | tp->link_config.active_duplex == DUPLEX_FULL && |
| 2103 | (tp->link_config.active_speed == SPEED_100 || |
| 2104 | tp->link_config.active_speed == SPEED_1000)) { |
Matt Carlson | 52b02d0 | 2010-10-14 10:37:41 +0000 | [diff] [blame] | 2105 | u32 eeectl; |
| 2106 | |
| 2107 | if (tp->link_config.active_speed == SPEED_1000) |
| 2108 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US; |
| 2109 | else |
| 2110 | eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US; |
| 2111 | |
| 2112 | tw32(TG3_CPMU_EEE_CTRL, eeectl); |
| 2113 | |
Matt Carlson | 3110f5f5 | 2010-12-06 08:28:50 +0000 | [diff] [blame] | 2114 | tg3_phy_cl45_read(tp, MDIO_MMD_AN, |
| 2115 | TG3_CL45_D7_EEERES_STAT, &val); |
Matt Carlson | 52b02d0 | 2010-10-14 10:37:41 +0000 | [diff] [blame] | 2116 | |
Matt Carlson | b0c5943 | 2011-05-19 12:12:48 +0000 | [diff] [blame] | 2117 | if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T || |
| 2118 | val == TG3_CL45_D7_EEERES_STAT_LP_100TX) |
Matt Carlson | 52b02d0 | 2010-10-14 10:37:41 +0000 | [diff] [blame] | 2119 | tp->setlpicnt = 2; |
| 2120 | } |
| 2121 | |
| 2122 | if (!tp->setlpicnt) { |
Matt Carlson | b715ce9 | 2011-07-20 10:20:52 +0000 | [diff] [blame] | 2123 | if (current_link_up == 1 && |
| 2124 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
| 2125 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000); |
| 2126 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
| 2127 | } |
| 2128 | |
Matt Carlson | 52b02d0 | 2010-10-14 10:37:41 +0000 | [diff] [blame] | 2129 | val = tr32(TG3_CPMU_EEE_MODE); |
| 2130 | tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE); |
| 2131 | } |
| 2132 | } |
| 2133 | |
Matt Carlson | b0c5943 | 2011-05-19 12:12:48 +0000 | [diff] [blame] | 2134 | static void tg3_phy_eee_enable(struct tg3 *tp) |
| 2135 | { |
| 2136 | u32 val; |
| 2137 | |
| 2138 | if (tp->link_config.active_speed == SPEED_1000 && |
| 2139 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
| 2140 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
Matt Carlson | 55086ad | 2011-12-14 11:09:59 +0000 | [diff] [blame] | 2141 | tg3_flag(tp, 57765_CLASS)) && |
Matt Carlson | b0c5943 | 2011-05-19 12:12:48 +0000 | [diff] [blame] | 2142 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
Matt Carlson | b715ce9 | 2011-07-20 10:20:52 +0000 | [diff] [blame] | 2143 | val = MII_TG3_DSP_TAP26_ALNOKO | |
| 2144 | MII_TG3_DSP_TAP26_RMRXSTO; |
| 2145 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); |
Matt Carlson | b0c5943 | 2011-05-19 12:12:48 +0000 | [diff] [blame] | 2146 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
| 2147 | } |
| 2148 | |
| 2149 | val = tr32(TG3_CPMU_EEE_MODE); |
| 2150 | tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE); |
| 2151 | } |
| 2152 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2153 | static int tg3_wait_macro_done(struct tg3 *tp) |
| 2154 | { |
| 2155 | int limit = 100; |
| 2156 | |
| 2157 | while (limit--) { |
| 2158 | u32 tmp32; |
| 2159 | |
Matt Carlson | f08aa1a | 2010-08-02 11:26:05 +0000 | [diff] [blame] | 2160 | if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2161 | if ((tmp32 & 0x1000) == 0) |
| 2162 | break; |
| 2163 | } |
| 2164 | } |
Roel Kluin | d4675b5 | 2009-02-12 16:33:27 -0800 | [diff] [blame] | 2165 | if (limit < 0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2166 | return -EBUSY; |
| 2167 | |
| 2168 | return 0; |
| 2169 | } |
| 2170 | |
| 2171 | static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) |
| 2172 | { |
| 2173 | static const u32 test_pat[4][6] = { |
| 2174 | { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 }, |
| 2175 | { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 }, |
| 2176 | { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 }, |
| 2177 | { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 } |
| 2178 | }; |
| 2179 | int chan; |
| 2180 | |
| 2181 | for (chan = 0; chan < 4; chan++) { |
| 2182 | int i; |
| 2183 | |
| 2184 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
| 2185 | (chan * 0x2000) | 0x0200); |
Matt Carlson | f08aa1a | 2010-08-02 11:26:05 +0000 | [diff] [blame] | 2186 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2187 | |
| 2188 | for (i = 0; i < 6; i++) |
| 2189 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, |
| 2190 | test_pat[chan][i]); |
| 2191 | |
Matt Carlson | f08aa1a | 2010-08-02 11:26:05 +0000 | [diff] [blame] | 2192 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2193 | if (tg3_wait_macro_done(tp)) { |
| 2194 | *resetp = 1; |
| 2195 | return -EBUSY; |
| 2196 | } |
| 2197 | |
| 2198 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
| 2199 | (chan * 0x2000) | 0x0200); |
Matt Carlson | f08aa1a | 2010-08-02 11:26:05 +0000 | [diff] [blame] | 2200 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2201 | if (tg3_wait_macro_done(tp)) { |
| 2202 | *resetp = 1; |
| 2203 | return -EBUSY; |
| 2204 | } |
| 2205 | |
Matt Carlson | f08aa1a | 2010-08-02 11:26:05 +0000 | [diff] [blame] | 2206 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2207 | if (tg3_wait_macro_done(tp)) { |
| 2208 | *resetp = 1; |
| 2209 | return -EBUSY; |
| 2210 | } |
| 2211 | |
| 2212 | for (i = 0; i < 6; i += 2) { |
| 2213 | u32 low, high; |
| 2214 | |
| 2215 | if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || |
| 2216 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || |
| 2217 | tg3_wait_macro_done(tp)) { |
| 2218 | *resetp = 1; |
| 2219 | return -EBUSY; |
| 2220 | } |
| 2221 | low &= 0x7fff; |
| 2222 | high &= 0x000f; |
| 2223 | if (low != test_pat[chan][i] || |
| 2224 | high != test_pat[chan][i+1]) { |
| 2225 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); |
| 2226 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); |
| 2227 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); |
| 2228 | |
| 2229 | return -EBUSY; |
| 2230 | } |
| 2231 | } |
| 2232 | } |
| 2233 | |
| 2234 | return 0; |
| 2235 | } |
| 2236 | |
| 2237 | static int tg3_phy_reset_chanpat(struct tg3 *tp) |
| 2238 | { |
| 2239 | int chan; |
| 2240 | |
| 2241 | for (chan = 0; chan < 4; chan++) { |
| 2242 | int i; |
| 2243 | |
| 2244 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
| 2245 | (chan * 0x2000) | 0x0200); |
Matt Carlson | f08aa1a | 2010-08-02 11:26:05 +0000 | [diff] [blame] | 2246 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2247 | for (i = 0; i < 6; i++) |
| 2248 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); |
Matt Carlson | f08aa1a | 2010-08-02 11:26:05 +0000 | [diff] [blame] | 2249 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2250 | if (tg3_wait_macro_done(tp)) |
| 2251 | return -EBUSY; |
| 2252 | } |
| 2253 | |
| 2254 | return 0; |
| 2255 | } |
| 2256 | |
| 2257 | static int tg3_phy_reset_5703_4_5(struct tg3 *tp) |
| 2258 | { |
| 2259 | u32 reg32, phy9_orig; |
| 2260 | int retries, do_phy_reset, err; |
| 2261 | |
| 2262 | retries = 10; |
| 2263 | do_phy_reset = 1; |
| 2264 | do { |
| 2265 | if (do_phy_reset) { |
| 2266 | err = tg3_bmcr_reset(tp); |
| 2267 | if (err) |
| 2268 | return err; |
| 2269 | do_phy_reset = 0; |
| 2270 | } |
| 2271 | |
| 2272 | /* Disable transmitter and interrupt. */ |
| 2273 | if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) |
| 2274 | continue; |
| 2275 | |
| 2276 | reg32 |= 0x3000; |
| 2277 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); |
| 2278 | |
| 2279 | /* Set full-duplex, 1000 mbps. */ |
| 2280 | tg3_writephy(tp, MII_BMCR, |
Matt Carlson | 221c563 | 2011-06-13 13:39:01 +0000 | [diff] [blame] | 2281 | BMCR_FULLDPLX | BMCR_SPEED1000); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2282 | |
| 2283 | /* Set to master mode. */ |
Matt Carlson | 221c563 | 2011-06-13 13:39:01 +0000 | [diff] [blame] | 2284 | if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2285 | continue; |
| 2286 | |
Matt Carlson | 221c563 | 2011-06-13 13:39:01 +0000 | [diff] [blame] | 2287 | tg3_writephy(tp, MII_CTRL1000, |
| 2288 | CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2289 | |
Matt Carlson | 1d36ba4 | 2011-04-20 07:57:42 +0000 | [diff] [blame] | 2290 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); |
| 2291 | if (err) |
| 2292 | return err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2293 | |
| 2294 | /* Block the PHY control access. */ |
Matt Carlson | 6ee7c0a | 2010-08-02 11:26:04 +0000 | [diff] [blame] | 2295 | tg3_phydsp_write(tp, 0x8005, 0x0800); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2296 | |
| 2297 | err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); |
| 2298 | if (!err) |
| 2299 | break; |
| 2300 | } while (--retries); |
| 2301 | |
| 2302 | err = tg3_phy_reset_chanpat(tp); |
| 2303 | if (err) |
| 2304 | return err; |
| 2305 | |
Matt Carlson | 6ee7c0a | 2010-08-02 11:26:04 +0000 | [diff] [blame] | 2306 | tg3_phydsp_write(tp, 0x8005, 0x0000); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2307 | |
| 2308 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); |
Matt Carlson | f08aa1a | 2010-08-02 11:26:05 +0000 | [diff] [blame] | 2309 | tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2310 | |
Matt Carlson | 1d36ba4 | 2011-04-20 07:57:42 +0000 | [diff] [blame] | 2311 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2312 | |
Matt Carlson | 221c563 | 2011-06-13 13:39:01 +0000 | [diff] [blame] | 2313 | tg3_writephy(tp, MII_CTRL1000, phy9_orig); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2314 | |
| 2315 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { |
| 2316 | reg32 &= ~0x3000; |
| 2317 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); |
| 2318 | } else if (!err) |
| 2319 | err = -EBUSY; |
| 2320 | |
| 2321 | return err; |
| 2322 | } |
| 2323 | |
| 2324 | /* This will reset the tigon3 PHY if there is no valid |
| 2325 | * link unless the FORCE argument is non-zero. |
| 2326 | */ |
| 2327 | static int tg3_phy_reset(struct tg3 *tp) |
| 2328 | { |
Matt Carlson | f833c4c | 2010-09-15 09:00:01 +0000 | [diff] [blame] | 2329 | u32 val, cpmuctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2330 | int err; |
| 2331 | |
Michael Chan | 60189dd | 2006-12-17 17:08:07 -0800 | [diff] [blame] | 2332 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
Michael Chan | 60189dd | 2006-12-17 17:08:07 -0800 | [diff] [blame] | 2333 | val = tr32(GRC_MISC_CFG); |
| 2334 | tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); |
| 2335 | udelay(40); |
| 2336 | } |
Matt Carlson | f833c4c | 2010-09-15 09:00:01 +0000 | [diff] [blame] | 2337 | err = tg3_readphy(tp, MII_BMSR, &val); |
| 2338 | err |= tg3_readphy(tp, MII_BMSR, &val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2339 | if (err != 0) |
| 2340 | return -EBUSY; |
| 2341 | |
Michael Chan | c8e1e82 | 2006-04-29 18:55:17 -0700 | [diff] [blame] | 2342 | if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) { |
| 2343 | netif_carrier_off(tp->dev); |
| 2344 | tg3_link_report(tp); |
| 2345 | } |
| 2346 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2347 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || |
| 2348 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
| 2349 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
| 2350 | err = tg3_phy_reset_5703_4_5(tp); |
| 2351 | if (err) |
| 2352 | return err; |
| 2353 | goto out; |
| 2354 | } |
| 2355 | |
Matt Carlson | b2a5c19 | 2008-04-03 21:44:44 -0700 | [diff] [blame] | 2356 | cpmuctrl = 0; |
| 2357 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
| 2358 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { |
| 2359 | cpmuctrl = tr32(TG3_CPMU_CTRL); |
| 2360 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) |
| 2361 | tw32(TG3_CPMU_CTRL, |
| 2362 | cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY); |
| 2363 | } |
| 2364 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2365 | err = tg3_bmcr_reset(tp); |
| 2366 | if (err) |
| 2367 | return err; |
| 2368 | |
Matt Carlson | b2a5c19 | 2008-04-03 21:44:44 -0700 | [diff] [blame] | 2369 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) { |
Matt Carlson | f833c4c | 2010-09-15 09:00:01 +0000 | [diff] [blame] | 2370 | val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz; |
| 2371 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val); |
Matt Carlson | b2a5c19 | 2008-04-03 21:44:44 -0700 | [diff] [blame] | 2372 | |
| 2373 | tw32(TG3_CPMU_CTRL, cpmuctrl); |
| 2374 | } |
| 2375 | |
Matt Carlson | bcb37f6 | 2008-11-03 16:52:09 -0800 | [diff] [blame] | 2376 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
| 2377 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { |
Matt Carlson | ce057f0 | 2007-11-12 21:08:03 -0800 | [diff] [blame] | 2378 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
| 2379 | if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == |
| 2380 | CPMU_LSPD_1000MB_MACCLK_12_5) { |
| 2381 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; |
| 2382 | udelay(40); |
| 2383 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); |
| 2384 | } |
| 2385 | } |
| 2386 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 2387 | if (tg3_flag(tp, 5717_PLUS) && |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 2388 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) |
Matt Carlson | ecf1410 | 2010-01-20 16:58:05 +0000 | [diff] [blame] | 2389 | return 0; |
| 2390 | |
Matt Carlson | b2a5c19 | 2008-04-03 21:44:44 -0700 | [diff] [blame] | 2391 | tg3_phy_apply_otp(tp); |
| 2392 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 2393 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
Matt Carlson | 6833c04 | 2008-11-21 17:18:59 -0800 | [diff] [blame] | 2394 | tg3_phy_toggle_apd(tp, true); |
| 2395 | else |
| 2396 | tg3_phy_toggle_apd(tp, false); |
| 2397 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2398 | out: |
Matt Carlson | 1d36ba4 | 2011-04-20 07:57:42 +0000 | [diff] [blame] | 2399 | if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && |
| 2400 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
Matt Carlson | 6ee7c0a | 2010-08-02 11:26:04 +0000 | [diff] [blame] | 2401 | tg3_phydsp_write(tp, 0x201f, 0x2aaa); |
| 2402 | tg3_phydsp_write(tp, 0x000a, 0x0323); |
Matt Carlson | 1d36ba4 | 2011-04-20 07:57:42 +0000 | [diff] [blame] | 2403 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2404 | } |
Matt Carlson | 1d36ba4 | 2011-04-20 07:57:42 +0000 | [diff] [blame] | 2405 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 2406 | if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { |
Matt Carlson | f08aa1a | 2010-08-02 11:26:05 +0000 | [diff] [blame] | 2407 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); |
| 2408 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2409 | } |
Matt Carlson | 1d36ba4 | 2011-04-20 07:57:42 +0000 | [diff] [blame] | 2410 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 2411 | if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { |
Matt Carlson | 1d36ba4 | 2011-04-20 07:57:42 +0000 | [diff] [blame] | 2412 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
| 2413 | tg3_phydsp_write(tp, 0x000a, 0x310b); |
| 2414 | tg3_phydsp_write(tp, 0x201f, 0x9506); |
| 2415 | tg3_phydsp_write(tp, 0x401f, 0x14e2); |
| 2416 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
| 2417 | } |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 2418 | } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { |
Matt Carlson | 1d36ba4 | 2011-04-20 07:57:42 +0000 | [diff] [blame] | 2419 | if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
| 2420 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); |
| 2421 | if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { |
| 2422 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); |
| 2423 | tg3_writephy(tp, MII_TG3_TEST1, |
| 2424 | MII_TG3_TEST1_TRIM_EN | 0x4); |
| 2425 | } else |
| 2426 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); |
| 2427 | |
| 2428 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
| 2429 | } |
Michael Chan | c424cb2 | 2006-04-29 18:56:34 -0700 | [diff] [blame] | 2430 | } |
Matt Carlson | 1d36ba4 | 2011-04-20 07:57:42 +0000 | [diff] [blame] | 2431 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2432 | /* Set Extended packet length bit (bit 14) on all chips that */ |
| 2433 | /* support jumbo frames */ |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 2434 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2435 | /* Cannot do read-modify-write on 5401 */ |
Matt Carlson | b4bd292 | 2011-04-20 07:57:41 +0000 | [diff] [blame] | 2436 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 2437 | } else if (tg3_flag(tp, JUMBO_CAPABLE)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2438 | /* Set bit 14 with read-modify-write to preserve other bits */ |
Matt Carlson | 15ee95c | 2011-04-20 07:57:40 +0000 | [diff] [blame] | 2439 | err = tg3_phy_auxctl_read(tp, |
| 2440 | MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); |
| 2441 | if (!err) |
Matt Carlson | b4bd292 | 2011-04-20 07:57:41 +0000 | [diff] [blame] | 2442 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, |
| 2443 | val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2444 | } |
| 2445 | |
| 2446 | /* Set phy register 0x10 bit 0 to high fifo elasticity to support |
| 2447 | * jumbo frames transmission. |
| 2448 | */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 2449 | if (tg3_flag(tp, JUMBO_CAPABLE)) { |
Matt Carlson | f833c4c | 2010-09-15 09:00:01 +0000 | [diff] [blame] | 2450 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) |
Matt Carlson | c6cdf43 | 2010-04-05 10:19:26 +0000 | [diff] [blame] | 2451 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
Matt Carlson | f833c4c | 2010-09-15 09:00:01 +0000 | [diff] [blame] | 2452 | val | MII_TG3_EXT_CTRL_FIFO_ELASTIC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2453 | } |
| 2454 | |
Michael Chan | 715116a | 2006-09-27 16:09:25 -0700 | [diff] [blame] | 2455 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
Michael Chan | 715116a | 2006-09-27 16:09:25 -0700 | [diff] [blame] | 2456 | /* adjust output voltage */ |
Matt Carlson | 535ef6e | 2009-08-25 10:09:36 +0000 | [diff] [blame] | 2457 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); |
Michael Chan | 715116a | 2006-09-27 16:09:25 -0700 | [diff] [blame] | 2458 | } |
| 2459 | |
Matt Carlson | 9ef8ca9 | 2007-07-11 19:48:29 -0700 | [diff] [blame] | 2460 | tg3_phy_toggle_automdix(tp, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2461 | tg3_phy_set_wirespeed(tp); |
| 2462 | return 0; |
| 2463 | } |
| 2464 | |
Matt Carlson | 3a1e19d | 2011-07-13 09:27:32 +0000 | [diff] [blame] | 2465 | #define TG3_GPIO_MSG_DRVR_PRES 0x00000001 |
| 2466 | #define TG3_GPIO_MSG_NEED_VAUX 0x00000002 |
| 2467 | #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \ |
| 2468 | TG3_GPIO_MSG_NEED_VAUX) |
| 2469 | #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \ |
| 2470 | ((TG3_GPIO_MSG_DRVR_PRES << 0) | \ |
| 2471 | (TG3_GPIO_MSG_DRVR_PRES << 4) | \ |
| 2472 | (TG3_GPIO_MSG_DRVR_PRES << 8) | \ |
| 2473 | (TG3_GPIO_MSG_DRVR_PRES << 12)) |
| 2474 | |
| 2475 | #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \ |
| 2476 | ((TG3_GPIO_MSG_NEED_VAUX << 0) | \ |
| 2477 | (TG3_GPIO_MSG_NEED_VAUX << 4) | \ |
| 2478 | (TG3_GPIO_MSG_NEED_VAUX << 8) | \ |
| 2479 | (TG3_GPIO_MSG_NEED_VAUX << 12)) |
| 2480 | |
| 2481 | static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat) |
| 2482 | { |
| 2483 | u32 status, shift; |
| 2484 | |
| 2485 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
| 2486 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) |
| 2487 | status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG); |
| 2488 | else |
| 2489 | status = tr32(TG3_CPMU_DRV_STATUS); |
| 2490 | |
| 2491 | shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn; |
| 2492 | status &= ~(TG3_GPIO_MSG_MASK << shift); |
| 2493 | status |= (newstat << shift); |
| 2494 | |
| 2495 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
| 2496 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) |
| 2497 | tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status); |
| 2498 | else |
| 2499 | tw32(TG3_CPMU_DRV_STATUS, status); |
| 2500 | |
| 2501 | return status >> TG3_APE_GPIO_MSG_SHIFT; |
| 2502 | } |
| 2503 | |
Matt Carlson | 520b275 | 2011-06-13 13:39:02 +0000 | [diff] [blame] | 2504 | static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp) |
| 2505 | { |
| 2506 | if (!tg3_flag(tp, IS_NIC)) |
| 2507 | return 0; |
| 2508 | |
Matt Carlson | 3a1e19d | 2011-07-13 09:27:32 +0000 | [diff] [blame] | 2509 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
| 2510 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
| 2511 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { |
| 2512 | if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) |
| 2513 | return -EIO; |
Matt Carlson | 520b275 | 2011-06-13 13:39:02 +0000 | [diff] [blame] | 2514 | |
Matt Carlson | 3a1e19d | 2011-07-13 09:27:32 +0000 | [diff] [blame] | 2515 | tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES); |
| 2516 | |
| 2517 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, |
| 2518 | TG3_GRC_LCLCTL_PWRSW_DELAY); |
| 2519 | |
| 2520 | tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); |
| 2521 | } else { |
| 2522 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, |
| 2523 | TG3_GRC_LCLCTL_PWRSW_DELAY); |
| 2524 | } |
Matt Carlson | 6f5c8f83 | 2011-07-13 09:27:31 +0000 | [diff] [blame] | 2525 | |
Matt Carlson | 520b275 | 2011-06-13 13:39:02 +0000 | [diff] [blame] | 2526 | return 0; |
| 2527 | } |
| 2528 | |
| 2529 | static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp) |
| 2530 | { |
| 2531 | u32 grc_local_ctrl; |
| 2532 | |
| 2533 | if (!tg3_flag(tp, IS_NIC) || |
| 2534 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
| 2535 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) |
| 2536 | return; |
| 2537 | |
| 2538 | grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; |
| 2539 | |
| 2540 | tw32_wait_f(GRC_LOCAL_CTRL, |
| 2541 | grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1, |
| 2542 | TG3_GRC_LCLCTL_PWRSW_DELAY); |
| 2543 | |
| 2544 | tw32_wait_f(GRC_LOCAL_CTRL, |
| 2545 | grc_local_ctrl, |
| 2546 | TG3_GRC_LCLCTL_PWRSW_DELAY); |
| 2547 | |
| 2548 | tw32_wait_f(GRC_LOCAL_CTRL, |
| 2549 | grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1, |
| 2550 | TG3_GRC_LCLCTL_PWRSW_DELAY); |
| 2551 | } |
| 2552 | |
| 2553 | static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp) |
| 2554 | { |
| 2555 | if (!tg3_flag(tp, IS_NIC)) |
| 2556 | return; |
| 2557 | |
| 2558 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
| 2559 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { |
| 2560 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
| 2561 | (GRC_LCLCTRL_GPIO_OE0 | |
| 2562 | GRC_LCLCTRL_GPIO_OE1 | |
| 2563 | GRC_LCLCTRL_GPIO_OE2 | |
| 2564 | GRC_LCLCTRL_GPIO_OUTPUT0 | |
| 2565 | GRC_LCLCTRL_GPIO_OUTPUT1), |
| 2566 | TG3_GRC_LCLCTL_PWRSW_DELAY); |
| 2567 | } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
| 2568 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { |
| 2569 | /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ |
| 2570 | u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | |
| 2571 | GRC_LCLCTRL_GPIO_OE1 | |
| 2572 | GRC_LCLCTRL_GPIO_OE2 | |
| 2573 | GRC_LCLCTRL_GPIO_OUTPUT0 | |
| 2574 | GRC_LCLCTRL_GPIO_OUTPUT1 | |
| 2575 | tp->grc_local_ctrl; |
| 2576 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, |
| 2577 | TG3_GRC_LCLCTL_PWRSW_DELAY); |
| 2578 | |
| 2579 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2; |
| 2580 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, |
| 2581 | TG3_GRC_LCLCTL_PWRSW_DELAY); |
| 2582 | |
| 2583 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0; |
| 2584 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, |
| 2585 | TG3_GRC_LCLCTL_PWRSW_DELAY); |
| 2586 | } else { |
| 2587 | u32 no_gpio2; |
| 2588 | u32 grc_local_ctrl = 0; |
| 2589 | |
| 2590 | /* Workaround to prevent overdrawing Amps. */ |
| 2591 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
| 2592 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; |
| 2593 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
| 2594 | grc_local_ctrl, |
| 2595 | TG3_GRC_LCLCTL_PWRSW_DELAY); |
| 2596 | } |
| 2597 | |
| 2598 | /* On 5753 and variants, GPIO2 cannot be used. */ |
| 2599 | no_gpio2 = tp->nic_sram_data_cfg & |
| 2600 | NIC_SRAM_DATA_CFG_NO_GPIO2; |
| 2601 | |
| 2602 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | |
| 2603 | GRC_LCLCTRL_GPIO_OE1 | |
| 2604 | GRC_LCLCTRL_GPIO_OE2 | |
| 2605 | GRC_LCLCTRL_GPIO_OUTPUT1 | |
| 2606 | GRC_LCLCTRL_GPIO_OUTPUT2; |
| 2607 | if (no_gpio2) { |
| 2608 | grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 | |
| 2609 | GRC_LCLCTRL_GPIO_OUTPUT2); |
| 2610 | } |
| 2611 | tw32_wait_f(GRC_LOCAL_CTRL, |
| 2612 | tp->grc_local_ctrl | grc_local_ctrl, |
| 2613 | TG3_GRC_LCLCTL_PWRSW_DELAY); |
| 2614 | |
| 2615 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0; |
| 2616 | |
| 2617 | tw32_wait_f(GRC_LOCAL_CTRL, |
| 2618 | tp->grc_local_ctrl | grc_local_ctrl, |
| 2619 | TG3_GRC_LCLCTL_PWRSW_DELAY); |
| 2620 | |
| 2621 | if (!no_gpio2) { |
| 2622 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2; |
| 2623 | tw32_wait_f(GRC_LOCAL_CTRL, |
| 2624 | tp->grc_local_ctrl | grc_local_ctrl, |
| 2625 | TG3_GRC_LCLCTL_PWRSW_DELAY); |
| 2626 | } |
| 2627 | } |
Matt Carlson | 3a1e19d | 2011-07-13 09:27:32 +0000 | [diff] [blame] | 2628 | } |
Matt Carlson | 6f5c8f83 | 2011-07-13 09:27:31 +0000 | [diff] [blame] | 2629 | |
Matt Carlson | cd0d722 | 2011-07-13 09:27:33 +0000 | [diff] [blame] | 2630 | static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable) |
Matt Carlson | 3a1e19d | 2011-07-13 09:27:32 +0000 | [diff] [blame] | 2631 | { |
| 2632 | u32 msg = 0; |
| 2633 | |
| 2634 | /* Serialize power state transitions */ |
| 2635 | if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) |
| 2636 | return; |
| 2637 | |
Matt Carlson | cd0d722 | 2011-07-13 09:27:33 +0000 | [diff] [blame] | 2638 | if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable) |
Matt Carlson | 3a1e19d | 2011-07-13 09:27:32 +0000 | [diff] [blame] | 2639 | msg = TG3_GPIO_MSG_NEED_VAUX; |
| 2640 | |
| 2641 | msg = tg3_set_function_status(tp, msg); |
| 2642 | |
| 2643 | if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK) |
| 2644 | goto done; |
| 2645 | |
| 2646 | if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK) |
| 2647 | tg3_pwrsrc_switch_to_vaux(tp); |
| 2648 | else |
| 2649 | tg3_pwrsrc_die_with_vmain(tp); |
| 2650 | |
| 2651 | done: |
Matt Carlson | 6f5c8f83 | 2011-07-13 09:27:31 +0000 | [diff] [blame] | 2652 | tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); |
Matt Carlson | 520b275 | 2011-06-13 13:39:02 +0000 | [diff] [blame] | 2653 | } |
| 2654 | |
Matt Carlson | cd0d722 | 2011-07-13 09:27:33 +0000 | [diff] [blame] | 2655 | static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2656 | { |
Matt Carlson | 683644b | 2011-03-09 16:58:23 +0000 | [diff] [blame] | 2657 | bool need_vaux = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2658 | |
Matt Carlson | 334355a | 2010-01-20 16:58:10 +0000 | [diff] [blame] | 2659 | /* The GPIOs do something completely different on 57765. */ |
Matt Carlson | 55086ad | 2011-12-14 11:09:59 +0000 | [diff] [blame] | 2660 | if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2661 | return; |
| 2662 | |
Matt Carlson | 3a1e19d | 2011-07-13 09:27:32 +0000 | [diff] [blame] | 2663 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
| 2664 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
| 2665 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { |
Matt Carlson | cd0d722 | 2011-07-13 09:27:33 +0000 | [diff] [blame] | 2666 | tg3_frob_aux_power_5717(tp, include_wol ? |
| 2667 | tg3_flag(tp, WOL_ENABLE) != 0 : 0); |
Matt Carlson | 3a1e19d | 2011-07-13 09:27:32 +0000 | [diff] [blame] | 2668 | return; |
| 2669 | } |
| 2670 | |
| 2671 | if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { |
Michael Chan | 8c2dc7e | 2005-12-19 16:26:02 -0800 | [diff] [blame] | 2672 | struct net_device *dev_peer; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2673 | |
Michael Chan | 8c2dc7e | 2005-12-19 16:26:02 -0800 | [diff] [blame] | 2674 | dev_peer = pci_get_drvdata(tp->pdev_peer); |
Matt Carlson | 683644b | 2011-03-09 16:58:23 +0000 | [diff] [blame] | 2675 | |
Michael Chan | bc1c756 | 2006-03-20 17:48:03 -0800 | [diff] [blame] | 2676 | /* remove_one() may have been run on the peer. */ |
Matt Carlson | 683644b | 2011-03-09 16:58:23 +0000 | [diff] [blame] | 2677 | if (dev_peer) { |
| 2678 | struct tg3 *tp_peer = netdev_priv(dev_peer); |
| 2679 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 2680 | if (tg3_flag(tp_peer, INIT_COMPLETE)) |
Matt Carlson | 683644b | 2011-03-09 16:58:23 +0000 | [diff] [blame] | 2681 | return; |
| 2682 | |
Matt Carlson | cd0d722 | 2011-07-13 09:27:33 +0000 | [diff] [blame] | 2683 | if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) || |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 2684 | tg3_flag(tp_peer, ENABLE_ASF)) |
Matt Carlson | 683644b | 2011-03-09 16:58:23 +0000 | [diff] [blame] | 2685 | need_vaux = true; |
| 2686 | } |
Michael Chan | 8c2dc7e | 2005-12-19 16:26:02 -0800 | [diff] [blame] | 2687 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2688 | |
Matt Carlson | cd0d722 | 2011-07-13 09:27:33 +0000 | [diff] [blame] | 2689 | if ((include_wol && tg3_flag(tp, WOL_ENABLE)) || |
| 2690 | tg3_flag(tp, ENABLE_ASF)) |
Matt Carlson | 683644b | 2011-03-09 16:58:23 +0000 | [diff] [blame] | 2691 | need_vaux = true; |
| 2692 | |
Matt Carlson | 520b275 | 2011-06-13 13:39:02 +0000 | [diff] [blame] | 2693 | if (need_vaux) |
| 2694 | tg3_pwrsrc_switch_to_vaux(tp); |
| 2695 | else |
| 2696 | tg3_pwrsrc_die_with_vmain(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2697 | } |
| 2698 | |
Matt Carlson | e8f3f6c | 2007-07-11 19:47:55 -0700 | [diff] [blame] | 2699 | static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) |
| 2700 | { |
| 2701 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) |
| 2702 | return 1; |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 2703 | else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { |
Matt Carlson | e8f3f6c | 2007-07-11 19:47:55 -0700 | [diff] [blame] | 2704 | if (speed != SPEED_10) |
| 2705 | return 1; |
| 2706 | } else if (speed == SPEED_10) |
| 2707 | return 1; |
| 2708 | |
| 2709 | return 0; |
| 2710 | } |
| 2711 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2712 | static int tg3_setup_phy(struct tg3 *, int); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2713 | static int tg3_halt_cpu(struct tg3 *, u32); |
| 2714 | |
Matt Carlson | 0a459aa | 2008-11-03 16:54:15 -0800 | [diff] [blame] | 2715 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) |
Michael Chan | 15c3b69 | 2006-03-22 01:06:52 -0800 | [diff] [blame] | 2716 | { |
Matt Carlson | ce057f0 | 2007-11-12 21:08:03 -0800 | [diff] [blame] | 2717 | u32 val; |
| 2718 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 2719 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
Michael Chan | 5129724 | 2007-02-13 12:17:57 -0800 | [diff] [blame] | 2720 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
| 2721 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); |
| 2722 | u32 serdes_cfg = tr32(MAC_SERDES_CFG); |
| 2723 | |
| 2724 | sg_dig_ctrl |= |
| 2725 | SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET; |
| 2726 | tw32(SG_DIG_CTRL, sg_dig_ctrl); |
| 2727 | tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15)); |
| 2728 | } |
Michael Chan | 3f7045c | 2006-09-27 16:02:29 -0700 | [diff] [blame] | 2729 | return; |
Michael Chan | 5129724 | 2007-02-13 12:17:57 -0800 | [diff] [blame] | 2730 | } |
Michael Chan | 3f7045c | 2006-09-27 16:02:29 -0700 | [diff] [blame] | 2731 | |
Michael Chan | 60189dd | 2006-12-17 17:08:07 -0800 | [diff] [blame] | 2732 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
Michael Chan | 60189dd | 2006-12-17 17:08:07 -0800 | [diff] [blame] | 2733 | tg3_bmcr_reset(tp); |
| 2734 | val = tr32(GRC_MISC_CFG); |
| 2735 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); |
| 2736 | udelay(40); |
| 2737 | return; |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 2738 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
Matt Carlson | 0e5f784 | 2009-11-02 14:26:38 +0000 | [diff] [blame] | 2739 | u32 phytest; |
| 2740 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { |
| 2741 | u32 phy; |
| 2742 | |
| 2743 | tg3_writephy(tp, MII_ADVERTISE, 0); |
| 2744 | tg3_writephy(tp, MII_BMCR, |
| 2745 | BMCR_ANENABLE | BMCR_ANRESTART); |
| 2746 | |
| 2747 | tg3_writephy(tp, MII_TG3_FET_TEST, |
| 2748 | phytest | MII_TG3_FET_SHADOW_EN); |
| 2749 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { |
| 2750 | phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD; |
| 2751 | tg3_writephy(tp, |
| 2752 | MII_TG3_FET_SHDW_AUXMODE4, |
| 2753 | phy); |
| 2754 | } |
| 2755 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); |
| 2756 | } |
| 2757 | return; |
Matt Carlson | 0a459aa | 2008-11-03 16:54:15 -0800 | [diff] [blame] | 2758 | } else if (do_low_power) { |
Michael Chan | 715116a | 2006-09-27 16:09:25 -0700 | [diff] [blame] | 2759 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
| 2760 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); |
Matt Carlson | 0a459aa | 2008-11-03 16:54:15 -0800 | [diff] [blame] | 2761 | |
Matt Carlson | b4bd292 | 2011-04-20 07:57:41 +0000 | [diff] [blame] | 2762 | val = MII_TG3_AUXCTL_PCTL_100TX_LPWR | |
| 2763 | MII_TG3_AUXCTL_PCTL_SPR_ISOLATE | |
| 2764 | MII_TG3_AUXCTL_PCTL_VREG_11V; |
| 2765 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val); |
Michael Chan | 715116a | 2006-09-27 16:09:25 -0700 | [diff] [blame] | 2766 | } |
Michael Chan | 3f7045c | 2006-09-27 16:02:29 -0700 | [diff] [blame] | 2767 | |
Michael Chan | 15c3b69 | 2006-03-22 01:06:52 -0800 | [diff] [blame] | 2768 | /* The PHY should not be powered down on some chips because |
| 2769 | * of bugs. |
| 2770 | */ |
| 2771 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
| 2772 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
| 2773 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 && |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 2774 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) |
Michael Chan | 15c3b69 | 2006-03-22 01:06:52 -0800 | [diff] [blame] | 2775 | return; |
Matt Carlson | ce057f0 | 2007-11-12 21:08:03 -0800 | [diff] [blame] | 2776 | |
Matt Carlson | bcb37f6 | 2008-11-03 16:52:09 -0800 | [diff] [blame] | 2777 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
| 2778 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { |
Matt Carlson | ce057f0 | 2007-11-12 21:08:03 -0800 | [diff] [blame] | 2779 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
| 2780 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; |
| 2781 | val |= CPMU_LSPD_1000MB_MACCLK_12_5; |
| 2782 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); |
| 2783 | } |
| 2784 | |
Michael Chan | 15c3b69 | 2006-03-22 01:06:52 -0800 | [diff] [blame] | 2785 | tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); |
| 2786 | } |
| 2787 | |
Matt Carlson | 3f00789 | 2008-11-03 16:51:36 -0800 | [diff] [blame] | 2788 | /* tp->lock is held. */ |
Matt Carlson | ffbcfed | 2009-02-25 14:24:28 +0000 | [diff] [blame] | 2789 | static int tg3_nvram_lock(struct tg3 *tp) |
| 2790 | { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 2791 | if (tg3_flag(tp, NVRAM)) { |
Matt Carlson | ffbcfed | 2009-02-25 14:24:28 +0000 | [diff] [blame] | 2792 | int i; |
| 2793 | |
| 2794 | if (tp->nvram_lock_cnt == 0) { |
| 2795 | tw32(NVRAM_SWARB, SWARB_REQ_SET1); |
| 2796 | for (i = 0; i < 8000; i++) { |
| 2797 | if (tr32(NVRAM_SWARB) & SWARB_GNT1) |
| 2798 | break; |
| 2799 | udelay(20); |
| 2800 | } |
| 2801 | if (i == 8000) { |
| 2802 | tw32(NVRAM_SWARB, SWARB_REQ_CLR1); |
| 2803 | return -ENODEV; |
| 2804 | } |
| 2805 | } |
| 2806 | tp->nvram_lock_cnt++; |
| 2807 | } |
| 2808 | return 0; |
| 2809 | } |
| 2810 | |
| 2811 | /* tp->lock is held. */ |
| 2812 | static void tg3_nvram_unlock(struct tg3 *tp) |
| 2813 | { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 2814 | if (tg3_flag(tp, NVRAM)) { |
Matt Carlson | ffbcfed | 2009-02-25 14:24:28 +0000 | [diff] [blame] | 2815 | if (tp->nvram_lock_cnt > 0) |
| 2816 | tp->nvram_lock_cnt--; |
| 2817 | if (tp->nvram_lock_cnt == 0) |
| 2818 | tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); |
| 2819 | } |
| 2820 | } |
| 2821 | |
| 2822 | /* tp->lock is held. */ |
| 2823 | static void tg3_enable_nvram_access(struct tg3 *tp) |
| 2824 | { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 2825 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { |
Matt Carlson | ffbcfed | 2009-02-25 14:24:28 +0000 | [diff] [blame] | 2826 | u32 nvaccess = tr32(NVRAM_ACCESS); |
| 2827 | |
| 2828 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); |
| 2829 | } |
| 2830 | } |
| 2831 | |
| 2832 | /* tp->lock is held. */ |
| 2833 | static void tg3_disable_nvram_access(struct tg3 *tp) |
| 2834 | { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 2835 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { |
Matt Carlson | ffbcfed | 2009-02-25 14:24:28 +0000 | [diff] [blame] | 2836 | u32 nvaccess = tr32(NVRAM_ACCESS); |
| 2837 | |
| 2838 | tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); |
| 2839 | } |
| 2840 | } |
| 2841 | |
| 2842 | static int tg3_nvram_read_using_eeprom(struct tg3 *tp, |
| 2843 | u32 offset, u32 *val) |
| 2844 | { |
| 2845 | u32 tmp; |
| 2846 | int i; |
| 2847 | |
| 2848 | if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) |
| 2849 | return -EINVAL; |
| 2850 | |
| 2851 | tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | |
| 2852 | EEPROM_ADDR_DEVID_MASK | |
| 2853 | EEPROM_ADDR_READ); |
| 2854 | tw32(GRC_EEPROM_ADDR, |
| 2855 | tmp | |
| 2856 | (0 << EEPROM_ADDR_DEVID_SHIFT) | |
| 2857 | ((offset << EEPROM_ADDR_ADDR_SHIFT) & |
| 2858 | EEPROM_ADDR_ADDR_MASK) | |
| 2859 | EEPROM_ADDR_READ | EEPROM_ADDR_START); |
| 2860 | |
| 2861 | for (i = 0; i < 1000; i++) { |
| 2862 | tmp = tr32(GRC_EEPROM_ADDR); |
| 2863 | |
| 2864 | if (tmp & EEPROM_ADDR_COMPLETE) |
| 2865 | break; |
| 2866 | msleep(1); |
| 2867 | } |
| 2868 | if (!(tmp & EEPROM_ADDR_COMPLETE)) |
| 2869 | return -EBUSY; |
| 2870 | |
Matt Carlson | 62cedd1 | 2009-04-20 14:52:29 -0700 | [diff] [blame] | 2871 | tmp = tr32(GRC_EEPROM_DATA); |
| 2872 | |
| 2873 | /* |
| 2874 | * The data will always be opposite the native endian |
| 2875 | * format. Perform a blind byteswap to compensate. |
| 2876 | */ |
| 2877 | *val = swab32(tmp); |
| 2878 | |
Matt Carlson | ffbcfed | 2009-02-25 14:24:28 +0000 | [diff] [blame] | 2879 | return 0; |
| 2880 | } |
| 2881 | |
| 2882 | #define NVRAM_CMD_TIMEOUT 10000 |
| 2883 | |
| 2884 | static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) |
| 2885 | { |
| 2886 | int i; |
| 2887 | |
| 2888 | tw32(NVRAM_CMD, nvram_cmd); |
| 2889 | for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { |
| 2890 | udelay(10); |
| 2891 | if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { |
| 2892 | udelay(10); |
| 2893 | break; |
| 2894 | } |
| 2895 | } |
| 2896 | |
| 2897 | if (i == NVRAM_CMD_TIMEOUT) |
| 2898 | return -EBUSY; |
| 2899 | |
| 2900 | return 0; |
| 2901 | } |
| 2902 | |
| 2903 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) |
| 2904 | { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 2905 | if (tg3_flag(tp, NVRAM) && |
| 2906 | tg3_flag(tp, NVRAM_BUFFERED) && |
| 2907 | tg3_flag(tp, FLASH) && |
| 2908 | !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && |
Matt Carlson | ffbcfed | 2009-02-25 14:24:28 +0000 | [diff] [blame] | 2909 | (tp->nvram_jedecnum == JEDEC_ATMEL)) |
| 2910 | |
| 2911 | addr = ((addr / tp->nvram_pagesize) << |
| 2912 | ATMEL_AT45DB0X1B_PAGE_POS) + |
| 2913 | (addr % tp->nvram_pagesize); |
| 2914 | |
| 2915 | return addr; |
| 2916 | } |
| 2917 | |
| 2918 | static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) |
| 2919 | { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 2920 | if (tg3_flag(tp, NVRAM) && |
| 2921 | tg3_flag(tp, NVRAM_BUFFERED) && |
| 2922 | tg3_flag(tp, FLASH) && |
| 2923 | !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && |
Matt Carlson | ffbcfed | 2009-02-25 14:24:28 +0000 | [diff] [blame] | 2924 | (tp->nvram_jedecnum == JEDEC_ATMEL)) |
| 2925 | |
| 2926 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * |
| 2927 | tp->nvram_pagesize) + |
| 2928 | (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); |
| 2929 | |
| 2930 | return addr; |
| 2931 | } |
| 2932 | |
Matt Carlson | e4f3411 | 2009-02-25 14:25:00 +0000 | [diff] [blame] | 2933 | /* NOTE: Data read in from NVRAM is byteswapped according to |
| 2934 | * the byteswapping settings for all other register accesses. |
| 2935 | * tg3 devices are BE devices, so on a BE machine, the data |
| 2936 | * returned will be exactly as it is seen in NVRAM. On a LE |
| 2937 | * machine, the 32-bit value will be byteswapped. |
| 2938 | */ |
Matt Carlson | ffbcfed | 2009-02-25 14:24:28 +0000 | [diff] [blame] | 2939 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) |
| 2940 | { |
| 2941 | int ret; |
| 2942 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 2943 | if (!tg3_flag(tp, NVRAM)) |
Matt Carlson | ffbcfed | 2009-02-25 14:24:28 +0000 | [diff] [blame] | 2944 | return tg3_nvram_read_using_eeprom(tp, offset, val); |
| 2945 | |
| 2946 | offset = tg3_nvram_phys_addr(tp, offset); |
| 2947 | |
| 2948 | if (offset > NVRAM_ADDR_MSK) |
| 2949 | return -EINVAL; |
| 2950 | |
| 2951 | ret = tg3_nvram_lock(tp); |
| 2952 | if (ret) |
| 2953 | return ret; |
| 2954 | |
| 2955 | tg3_enable_nvram_access(tp); |
| 2956 | |
| 2957 | tw32(NVRAM_ADDR, offset); |
| 2958 | ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | |
| 2959 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); |
| 2960 | |
| 2961 | if (ret == 0) |
Matt Carlson | e4f3411 | 2009-02-25 14:25:00 +0000 | [diff] [blame] | 2962 | *val = tr32(NVRAM_RDDATA); |
Matt Carlson | ffbcfed | 2009-02-25 14:24:28 +0000 | [diff] [blame] | 2963 | |
| 2964 | tg3_disable_nvram_access(tp); |
| 2965 | |
| 2966 | tg3_nvram_unlock(tp); |
| 2967 | |
| 2968 | return ret; |
| 2969 | } |
| 2970 | |
Matt Carlson | a9dc529 | 2009-02-25 14:25:30 +0000 | [diff] [blame] | 2971 | /* Ensures NVRAM data is in bytestream format. */ |
| 2972 | static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) |
Matt Carlson | ffbcfed | 2009-02-25 14:24:28 +0000 | [diff] [blame] | 2973 | { |
| 2974 | u32 v; |
Matt Carlson | a9dc529 | 2009-02-25 14:25:30 +0000 | [diff] [blame] | 2975 | int res = tg3_nvram_read(tp, offset, &v); |
Matt Carlson | ffbcfed | 2009-02-25 14:24:28 +0000 | [diff] [blame] | 2976 | if (!res) |
Matt Carlson | a9dc529 | 2009-02-25 14:25:30 +0000 | [diff] [blame] | 2977 | *val = cpu_to_be32(v); |
Matt Carlson | ffbcfed | 2009-02-25 14:24:28 +0000 | [diff] [blame] | 2978 | return res; |
| 2979 | } |
| 2980 | |
Matt Carlson | dbe9b92 | 2012-02-13 10:20:09 +0000 | [diff] [blame] | 2981 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, |
| 2982 | u32 offset, u32 len, u8 *buf) |
| 2983 | { |
| 2984 | int i, j, rc = 0; |
| 2985 | u32 val; |
| 2986 | |
| 2987 | for (i = 0; i < len; i += 4) { |
| 2988 | u32 addr; |
| 2989 | __be32 data; |
| 2990 | |
| 2991 | addr = offset + i; |
| 2992 | |
| 2993 | memcpy(&data, buf + i, 4); |
| 2994 | |
| 2995 | /* |
| 2996 | * The SEEPROM interface expects the data to always be opposite |
| 2997 | * the native endian format. We accomplish this by reversing |
| 2998 | * all the operations that would have been performed on the |
| 2999 | * data from a call to tg3_nvram_read_be32(). |
| 3000 | */ |
| 3001 | tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data))); |
| 3002 | |
| 3003 | val = tr32(GRC_EEPROM_ADDR); |
| 3004 | tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); |
| 3005 | |
| 3006 | val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK | |
| 3007 | EEPROM_ADDR_READ); |
| 3008 | tw32(GRC_EEPROM_ADDR, val | |
| 3009 | (0 << EEPROM_ADDR_DEVID_SHIFT) | |
| 3010 | (addr & EEPROM_ADDR_ADDR_MASK) | |
| 3011 | EEPROM_ADDR_START | |
| 3012 | EEPROM_ADDR_WRITE); |
| 3013 | |
| 3014 | for (j = 0; j < 1000; j++) { |
| 3015 | val = tr32(GRC_EEPROM_ADDR); |
| 3016 | |
| 3017 | if (val & EEPROM_ADDR_COMPLETE) |
| 3018 | break; |
| 3019 | msleep(1); |
| 3020 | } |
| 3021 | if (!(val & EEPROM_ADDR_COMPLETE)) { |
| 3022 | rc = -EBUSY; |
| 3023 | break; |
| 3024 | } |
| 3025 | } |
| 3026 | |
| 3027 | return rc; |
| 3028 | } |
| 3029 | |
| 3030 | /* offset and length are dword aligned */ |
| 3031 | static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, |
| 3032 | u8 *buf) |
| 3033 | { |
| 3034 | int ret = 0; |
| 3035 | u32 pagesize = tp->nvram_pagesize; |
| 3036 | u32 pagemask = pagesize - 1; |
| 3037 | u32 nvram_cmd; |
| 3038 | u8 *tmp; |
| 3039 | |
| 3040 | tmp = kmalloc(pagesize, GFP_KERNEL); |
| 3041 | if (tmp == NULL) |
| 3042 | return -ENOMEM; |
| 3043 | |
| 3044 | while (len) { |
| 3045 | int j; |
| 3046 | u32 phy_addr, page_off, size; |
| 3047 | |
| 3048 | phy_addr = offset & ~pagemask; |
| 3049 | |
| 3050 | for (j = 0; j < pagesize; j += 4) { |
| 3051 | ret = tg3_nvram_read_be32(tp, phy_addr + j, |
| 3052 | (__be32 *) (tmp + j)); |
| 3053 | if (ret) |
| 3054 | break; |
| 3055 | } |
| 3056 | if (ret) |
| 3057 | break; |
| 3058 | |
| 3059 | page_off = offset & pagemask; |
| 3060 | size = pagesize; |
| 3061 | if (len < size) |
| 3062 | size = len; |
| 3063 | |
| 3064 | len -= size; |
| 3065 | |
| 3066 | memcpy(tmp + page_off, buf, size); |
| 3067 | |
| 3068 | offset = offset + (pagesize - page_off); |
| 3069 | |
| 3070 | tg3_enable_nvram_access(tp); |
| 3071 | |
| 3072 | /* |
| 3073 | * Before we can erase the flash page, we need |
| 3074 | * to issue a special "write enable" command. |
| 3075 | */ |
| 3076 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; |
| 3077 | |
| 3078 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) |
| 3079 | break; |
| 3080 | |
| 3081 | /* Erase the target page */ |
| 3082 | tw32(NVRAM_ADDR, phy_addr); |
| 3083 | |
| 3084 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR | |
| 3085 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE; |
| 3086 | |
| 3087 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) |
| 3088 | break; |
| 3089 | |
| 3090 | /* Issue another write enable to start the write. */ |
| 3091 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; |
| 3092 | |
| 3093 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) |
| 3094 | break; |
| 3095 | |
| 3096 | for (j = 0; j < pagesize; j += 4) { |
| 3097 | __be32 data; |
| 3098 | |
| 3099 | data = *((__be32 *) (tmp + j)); |
| 3100 | |
| 3101 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
| 3102 | |
| 3103 | tw32(NVRAM_ADDR, phy_addr + j); |
| 3104 | |
| 3105 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | |
| 3106 | NVRAM_CMD_WR; |
| 3107 | |
| 3108 | if (j == 0) |
| 3109 | nvram_cmd |= NVRAM_CMD_FIRST; |
| 3110 | else if (j == (pagesize - 4)) |
| 3111 | nvram_cmd |= NVRAM_CMD_LAST; |
| 3112 | |
| 3113 | ret = tg3_nvram_exec_cmd(tp, nvram_cmd); |
| 3114 | if (ret) |
| 3115 | break; |
| 3116 | } |
| 3117 | if (ret) |
| 3118 | break; |
| 3119 | } |
| 3120 | |
| 3121 | nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE; |
| 3122 | tg3_nvram_exec_cmd(tp, nvram_cmd); |
| 3123 | |
| 3124 | kfree(tmp); |
| 3125 | |
| 3126 | return ret; |
| 3127 | } |
| 3128 | |
| 3129 | /* offset and length are dword aligned */ |
| 3130 | static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, |
| 3131 | u8 *buf) |
| 3132 | { |
| 3133 | int i, ret = 0; |
| 3134 | |
| 3135 | for (i = 0; i < len; i += 4, offset += 4) { |
| 3136 | u32 page_off, phy_addr, nvram_cmd; |
| 3137 | __be32 data; |
| 3138 | |
| 3139 | memcpy(&data, buf + i, 4); |
| 3140 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
| 3141 | |
| 3142 | page_off = offset % tp->nvram_pagesize; |
| 3143 | |
| 3144 | phy_addr = tg3_nvram_phys_addr(tp, offset); |
| 3145 | |
| 3146 | tw32(NVRAM_ADDR, phy_addr); |
| 3147 | |
| 3148 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR; |
| 3149 | |
| 3150 | if (page_off == 0 || i == 0) |
| 3151 | nvram_cmd |= NVRAM_CMD_FIRST; |
| 3152 | if (page_off == (tp->nvram_pagesize - 4)) |
| 3153 | nvram_cmd |= NVRAM_CMD_LAST; |
| 3154 | |
| 3155 | if (i == (len - 4)) |
| 3156 | nvram_cmd |= NVRAM_CMD_LAST; |
| 3157 | |
| 3158 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && |
| 3159 | !tg3_flag(tp, 5755_PLUS) && |
| 3160 | (tp->nvram_jedecnum == JEDEC_ST) && |
| 3161 | (nvram_cmd & NVRAM_CMD_FIRST)) { |
| 3162 | u32 cmd; |
| 3163 | |
| 3164 | cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; |
| 3165 | ret = tg3_nvram_exec_cmd(tp, cmd); |
| 3166 | if (ret) |
| 3167 | break; |
| 3168 | } |
| 3169 | if (!tg3_flag(tp, FLASH)) { |
| 3170 | /* We always do complete word writes to eeprom. */ |
| 3171 | nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST); |
| 3172 | } |
| 3173 | |
| 3174 | ret = tg3_nvram_exec_cmd(tp, nvram_cmd); |
| 3175 | if (ret) |
| 3176 | break; |
| 3177 | } |
| 3178 | return ret; |
| 3179 | } |
| 3180 | |
| 3181 | /* offset and length are dword aligned */ |
| 3182 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) |
| 3183 | { |
| 3184 | int ret; |
| 3185 | |
| 3186 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) { |
| 3187 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & |
| 3188 | ~GRC_LCLCTRL_GPIO_OUTPUT1); |
| 3189 | udelay(40); |
| 3190 | } |
| 3191 | |
| 3192 | if (!tg3_flag(tp, NVRAM)) { |
| 3193 | ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); |
| 3194 | } else { |
| 3195 | u32 grc_mode; |
| 3196 | |
| 3197 | ret = tg3_nvram_lock(tp); |
| 3198 | if (ret) |
| 3199 | return ret; |
| 3200 | |
| 3201 | tg3_enable_nvram_access(tp); |
| 3202 | if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) |
| 3203 | tw32(NVRAM_WRITE1, 0x406); |
| 3204 | |
| 3205 | grc_mode = tr32(GRC_MODE); |
| 3206 | tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); |
| 3207 | |
| 3208 | if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) { |
| 3209 | ret = tg3_nvram_write_block_buffered(tp, offset, len, |
| 3210 | buf); |
| 3211 | } else { |
| 3212 | ret = tg3_nvram_write_block_unbuffered(tp, offset, len, |
| 3213 | buf); |
| 3214 | } |
| 3215 | |
| 3216 | grc_mode = tr32(GRC_MODE); |
| 3217 | tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); |
| 3218 | |
| 3219 | tg3_disable_nvram_access(tp); |
| 3220 | tg3_nvram_unlock(tp); |
| 3221 | } |
| 3222 | |
| 3223 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) { |
| 3224 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
| 3225 | udelay(40); |
| 3226 | } |
| 3227 | |
| 3228 | return ret; |
| 3229 | } |
| 3230 | |
Matt Carlson | 997b4f1 | 2011-08-31 11:44:53 +0000 | [diff] [blame] | 3231 | #define RX_CPU_SCRATCH_BASE 0x30000 |
| 3232 | #define RX_CPU_SCRATCH_SIZE 0x04000 |
| 3233 | #define TX_CPU_SCRATCH_BASE 0x34000 |
| 3234 | #define TX_CPU_SCRATCH_SIZE 0x04000 |
| 3235 | |
| 3236 | /* tp->lock is held. */ |
| 3237 | static int tg3_halt_cpu(struct tg3 *tp, u32 offset) |
| 3238 | { |
| 3239 | int i; |
| 3240 | |
| 3241 | BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); |
| 3242 | |
| 3243 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
| 3244 | u32 val = tr32(GRC_VCPU_EXT_CTRL); |
| 3245 | |
| 3246 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); |
| 3247 | return 0; |
| 3248 | } |
| 3249 | if (offset == RX_CPU_BASE) { |
| 3250 | for (i = 0; i < 10000; i++) { |
| 3251 | tw32(offset + CPU_STATE, 0xffffffff); |
| 3252 | tw32(offset + CPU_MODE, CPU_MODE_HALT); |
| 3253 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) |
| 3254 | break; |
| 3255 | } |
| 3256 | |
| 3257 | tw32(offset + CPU_STATE, 0xffffffff); |
| 3258 | tw32_f(offset + CPU_MODE, CPU_MODE_HALT); |
| 3259 | udelay(10); |
| 3260 | } else { |
| 3261 | for (i = 0; i < 10000; i++) { |
| 3262 | tw32(offset + CPU_STATE, 0xffffffff); |
| 3263 | tw32(offset + CPU_MODE, CPU_MODE_HALT); |
| 3264 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) |
| 3265 | break; |
| 3266 | } |
| 3267 | } |
| 3268 | |
| 3269 | if (i >= 10000) { |
| 3270 | netdev_err(tp->dev, "%s timed out, %s CPU\n", |
| 3271 | __func__, offset == RX_CPU_BASE ? "RX" : "TX"); |
| 3272 | return -ENODEV; |
| 3273 | } |
| 3274 | |
| 3275 | /* Clear firmware's nvram arbitration. */ |
| 3276 | if (tg3_flag(tp, NVRAM)) |
| 3277 | tw32(NVRAM_SWARB, SWARB_REQ_CLR0); |
| 3278 | return 0; |
| 3279 | } |
| 3280 | |
| 3281 | struct fw_info { |
| 3282 | unsigned int fw_base; |
| 3283 | unsigned int fw_len; |
| 3284 | const __be32 *fw_data; |
| 3285 | }; |
| 3286 | |
| 3287 | /* tp->lock is held. */ |
| 3288 | static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, |
| 3289 | u32 cpu_scratch_base, int cpu_scratch_size, |
| 3290 | struct fw_info *info) |
| 3291 | { |
| 3292 | int err, lock_err, i; |
| 3293 | void (*write_op)(struct tg3 *, u32, u32); |
| 3294 | |
| 3295 | if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) { |
| 3296 | netdev_err(tp->dev, |
| 3297 | "%s: Trying to load TX cpu firmware which is 5705\n", |
| 3298 | __func__); |
| 3299 | return -EINVAL; |
| 3300 | } |
| 3301 | |
| 3302 | if (tg3_flag(tp, 5705_PLUS)) |
| 3303 | write_op = tg3_write_mem; |
| 3304 | else |
| 3305 | write_op = tg3_write_indirect_reg32; |
| 3306 | |
| 3307 | /* It is possible that bootcode is still loading at this point. |
| 3308 | * Get the nvram lock first before halting the cpu. |
| 3309 | */ |
| 3310 | lock_err = tg3_nvram_lock(tp); |
| 3311 | err = tg3_halt_cpu(tp, cpu_base); |
| 3312 | if (!lock_err) |
| 3313 | tg3_nvram_unlock(tp); |
| 3314 | if (err) |
| 3315 | goto out; |
| 3316 | |
| 3317 | for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) |
| 3318 | write_op(tp, cpu_scratch_base + i, 0); |
| 3319 | tw32(cpu_base + CPU_STATE, 0xffffffff); |
| 3320 | tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT); |
| 3321 | for (i = 0; i < (info->fw_len / sizeof(u32)); i++) |
| 3322 | write_op(tp, (cpu_scratch_base + |
| 3323 | (info->fw_base & 0xffff) + |
| 3324 | (i * sizeof(u32))), |
| 3325 | be32_to_cpu(info->fw_data[i])); |
| 3326 | |
| 3327 | err = 0; |
| 3328 | |
| 3329 | out: |
| 3330 | return err; |
| 3331 | } |
| 3332 | |
| 3333 | /* tp->lock is held. */ |
| 3334 | static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) |
| 3335 | { |
| 3336 | struct fw_info info; |
| 3337 | const __be32 *fw_data; |
| 3338 | int err, i; |
| 3339 | |
| 3340 | fw_data = (void *)tp->fw->data; |
| 3341 | |
| 3342 | /* Firmware blob starts with version numbers, followed by |
| 3343 | start address and length. We are setting complete length. |
| 3344 | length = end_address_of_bss - start_address_of_text. |
| 3345 | Remainder is the blob to be loaded contiguously |
| 3346 | from start address. */ |
| 3347 | |
| 3348 | info.fw_base = be32_to_cpu(fw_data[1]); |
| 3349 | info.fw_len = tp->fw->size - 12; |
| 3350 | info.fw_data = &fw_data[3]; |
| 3351 | |
| 3352 | err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, |
| 3353 | RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE, |
| 3354 | &info); |
| 3355 | if (err) |
| 3356 | return err; |
| 3357 | |
| 3358 | err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, |
| 3359 | TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE, |
| 3360 | &info); |
| 3361 | if (err) |
| 3362 | return err; |
| 3363 | |
| 3364 | /* Now startup only the RX cpu. */ |
| 3365 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); |
| 3366 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
| 3367 | |
| 3368 | for (i = 0; i < 5; i++) { |
| 3369 | if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) |
| 3370 | break; |
| 3371 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); |
| 3372 | tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); |
| 3373 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
| 3374 | udelay(1000); |
| 3375 | } |
| 3376 | if (i >= 5) { |
| 3377 | netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " |
| 3378 | "should be %08x\n", __func__, |
| 3379 | tr32(RX_CPU_BASE + CPU_PC), info.fw_base); |
| 3380 | return -ENODEV; |
| 3381 | } |
| 3382 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); |
| 3383 | tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000); |
| 3384 | |
| 3385 | return 0; |
| 3386 | } |
| 3387 | |
| 3388 | /* tp->lock is held. */ |
| 3389 | static int tg3_load_tso_firmware(struct tg3 *tp) |
| 3390 | { |
| 3391 | struct fw_info info; |
| 3392 | const __be32 *fw_data; |
| 3393 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; |
| 3394 | int err, i; |
| 3395 | |
| 3396 | if (tg3_flag(tp, HW_TSO_1) || |
| 3397 | tg3_flag(tp, HW_TSO_2) || |
| 3398 | tg3_flag(tp, HW_TSO_3)) |
| 3399 | return 0; |
| 3400 | |
| 3401 | fw_data = (void *)tp->fw->data; |
| 3402 | |
| 3403 | /* Firmware blob starts with version numbers, followed by |
| 3404 | start address and length. We are setting complete length. |
| 3405 | length = end_address_of_bss - start_address_of_text. |
| 3406 | Remainder is the blob to be loaded contiguously |
| 3407 | from start address. */ |
| 3408 | |
| 3409 | info.fw_base = be32_to_cpu(fw_data[1]); |
| 3410 | cpu_scratch_size = tp->fw_len; |
| 3411 | info.fw_len = tp->fw->size - 12; |
| 3412 | info.fw_data = &fw_data[3]; |
| 3413 | |
| 3414 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
| 3415 | cpu_base = RX_CPU_BASE; |
| 3416 | cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705; |
| 3417 | } else { |
| 3418 | cpu_base = TX_CPU_BASE; |
| 3419 | cpu_scratch_base = TX_CPU_SCRATCH_BASE; |
| 3420 | cpu_scratch_size = TX_CPU_SCRATCH_SIZE; |
| 3421 | } |
| 3422 | |
| 3423 | err = tg3_load_firmware_cpu(tp, cpu_base, |
| 3424 | cpu_scratch_base, cpu_scratch_size, |
| 3425 | &info); |
| 3426 | if (err) |
| 3427 | return err; |
| 3428 | |
| 3429 | /* Now startup the cpu. */ |
| 3430 | tw32(cpu_base + CPU_STATE, 0xffffffff); |
| 3431 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
| 3432 | |
| 3433 | for (i = 0; i < 5; i++) { |
| 3434 | if (tr32(cpu_base + CPU_PC) == info.fw_base) |
| 3435 | break; |
| 3436 | tw32(cpu_base + CPU_STATE, 0xffffffff); |
| 3437 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); |
| 3438 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
| 3439 | udelay(1000); |
| 3440 | } |
| 3441 | if (i >= 5) { |
| 3442 | netdev_err(tp->dev, |
| 3443 | "%s fails to set CPU PC, is %08x should be %08x\n", |
| 3444 | __func__, tr32(cpu_base + CPU_PC), info.fw_base); |
| 3445 | return -ENODEV; |
| 3446 | } |
| 3447 | tw32(cpu_base + CPU_STATE, 0xffffffff); |
| 3448 | tw32_f(cpu_base + CPU_MODE, 0x00000000); |
| 3449 | return 0; |
| 3450 | } |
| 3451 | |
| 3452 | |
Matt Carlson | ffbcfed | 2009-02-25 14:24:28 +0000 | [diff] [blame] | 3453 | /* tp->lock is held. */ |
Matt Carlson | 3f00789 | 2008-11-03 16:51:36 -0800 | [diff] [blame] | 3454 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) |
| 3455 | { |
| 3456 | u32 addr_high, addr_low; |
| 3457 | int i; |
| 3458 | |
| 3459 | addr_high = ((tp->dev->dev_addr[0] << 8) | |
| 3460 | tp->dev->dev_addr[1]); |
| 3461 | addr_low = ((tp->dev->dev_addr[2] << 24) | |
| 3462 | (tp->dev->dev_addr[3] << 16) | |
| 3463 | (tp->dev->dev_addr[4] << 8) | |
| 3464 | (tp->dev->dev_addr[5] << 0)); |
| 3465 | for (i = 0; i < 4; i++) { |
| 3466 | if (i == 1 && skip_mac_1) |
| 3467 | continue; |
| 3468 | tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high); |
| 3469 | tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); |
| 3470 | } |
| 3471 | |
| 3472 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || |
| 3473 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
| 3474 | for (i = 0; i < 12; i++) { |
| 3475 | tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); |
| 3476 | tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); |
| 3477 | } |
| 3478 | } |
| 3479 | |
| 3480 | addr_high = (tp->dev->dev_addr[0] + |
| 3481 | tp->dev->dev_addr[1] + |
| 3482 | tp->dev->dev_addr[2] + |
| 3483 | tp->dev->dev_addr[3] + |
| 3484 | tp->dev->dev_addr[4] + |
| 3485 | tp->dev->dev_addr[5]) & |
| 3486 | TX_BACKOFF_SEED_MASK; |
| 3487 | tw32(MAC_TX_BACKOFF_SEED, addr_high); |
| 3488 | } |
| 3489 | |
Rafael J. Wysocki | c866b7e | 2010-12-25 12:56:23 +0000 | [diff] [blame] | 3490 | static void tg3_enable_register_access(struct tg3 *tp) |
| 3491 | { |
| 3492 | /* |
| 3493 | * Make sure register accesses (indirect or otherwise) will function |
| 3494 | * correctly. |
| 3495 | */ |
| 3496 | pci_write_config_dword(tp->pdev, |
| 3497 | TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); |
| 3498 | } |
| 3499 | |
| 3500 | static int tg3_power_up(struct tg3 *tp) |
| 3501 | { |
Matt Carlson | bed9829 | 2011-07-13 09:27:29 +0000 | [diff] [blame] | 3502 | int err; |
| 3503 | |
Rafael J. Wysocki | c866b7e | 2010-12-25 12:56:23 +0000 | [diff] [blame] | 3504 | tg3_enable_register_access(tp); |
| 3505 | |
Matt Carlson | bed9829 | 2011-07-13 09:27:29 +0000 | [diff] [blame] | 3506 | err = pci_set_power_state(tp->pdev, PCI_D0); |
| 3507 | if (!err) { |
| 3508 | /* Switch out of Vaux if it is a NIC */ |
| 3509 | tg3_pwrsrc_switch_to_vmain(tp); |
| 3510 | } else { |
| 3511 | netdev_err(tp->dev, "Transition to D0 failed\n"); |
| 3512 | } |
Rafael J. Wysocki | c866b7e | 2010-12-25 12:56:23 +0000 | [diff] [blame] | 3513 | |
Matt Carlson | bed9829 | 2011-07-13 09:27:29 +0000 | [diff] [blame] | 3514 | return err; |
Rafael J. Wysocki | c866b7e | 2010-12-25 12:56:23 +0000 | [diff] [blame] | 3515 | } |
| 3516 | |
| 3517 | static int tg3_power_down_prepare(struct tg3 *tp) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3518 | { |
| 3519 | u32 misc_host_ctrl; |
Matt Carlson | 0a459aa | 2008-11-03 16:54:15 -0800 | [diff] [blame] | 3520 | bool device_should_wake, do_low_power; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3521 | |
Rafael J. Wysocki | c866b7e | 2010-12-25 12:56:23 +0000 | [diff] [blame] | 3522 | tg3_enable_register_access(tp); |
Matt Carlson | 5e7dfd0 | 2008-11-21 17:18:16 -0800 | [diff] [blame] | 3523 | |
| 3524 | /* Restore the CLKREQ setting. */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 3525 | if (tg3_flag(tp, CLKREQ_BUG)) { |
Matt Carlson | 5e7dfd0 | 2008-11-21 17:18:16 -0800 | [diff] [blame] | 3526 | u16 lnkctl; |
| 3527 | |
| 3528 | pci_read_config_word(tp->pdev, |
Jon Mason | 708ebb3 | 2011-06-27 12:56:50 +0000 | [diff] [blame] | 3529 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
Matt Carlson | 5e7dfd0 | 2008-11-21 17:18:16 -0800 | [diff] [blame] | 3530 | &lnkctl); |
| 3531 | lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN; |
| 3532 | pci_write_config_word(tp->pdev, |
Jon Mason | 708ebb3 | 2011-06-27 12:56:50 +0000 | [diff] [blame] | 3533 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
Matt Carlson | 5e7dfd0 | 2008-11-21 17:18:16 -0800 | [diff] [blame] | 3534 | lnkctl); |
| 3535 | } |
| 3536 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3537 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
| 3538 | tw32(TG3PCI_MISC_HOST_CTRL, |
| 3539 | misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); |
| 3540 | |
Rafael J. Wysocki | c866b7e | 2010-12-25 12:56:23 +0000 | [diff] [blame] | 3541 | device_should_wake = device_may_wakeup(&tp->pdev->dev) && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 3542 | tg3_flag(tp, WOL_ENABLE); |
Matt Carlson | 05ac4cb | 2008-11-03 16:53:46 -0800 | [diff] [blame] | 3543 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 3544 | if (tg3_flag(tp, USE_PHYLIB)) { |
Matt Carlson | 0a459aa | 2008-11-03 16:54:15 -0800 | [diff] [blame] | 3545 | do_low_power = false; |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 3546 | if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && |
Matt Carlson | 80096068 | 2010-08-02 11:26:06 +0000 | [diff] [blame] | 3547 | !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 3548 | struct phy_device *phydev; |
Matt Carlson | 0a459aa | 2008-11-03 16:54:15 -0800 | [diff] [blame] | 3549 | u32 phyid, advertising; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 3550 | |
Matt Carlson | 3f0e3ad | 2009-11-02 14:24:36 +0000 | [diff] [blame] | 3551 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 3552 | |
Matt Carlson | 80096068 | 2010-08-02 11:26:06 +0000 | [diff] [blame] | 3553 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 3554 | |
| 3555 | tp->link_config.orig_speed = phydev->speed; |
| 3556 | tp->link_config.orig_duplex = phydev->duplex; |
| 3557 | tp->link_config.orig_autoneg = phydev->autoneg; |
| 3558 | tp->link_config.orig_advertising = phydev->advertising; |
| 3559 | |
| 3560 | advertising = ADVERTISED_TP | |
| 3561 | ADVERTISED_Pause | |
| 3562 | ADVERTISED_Autoneg | |
| 3563 | ADVERTISED_10baseT_Half; |
| 3564 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 3565 | if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) { |
| 3566 | if (tg3_flag(tp, WOL_SPEED_100MB)) |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 3567 | advertising |= |
| 3568 | ADVERTISED_100baseT_Half | |
| 3569 | ADVERTISED_100baseT_Full | |
| 3570 | ADVERTISED_10baseT_Full; |
| 3571 | else |
| 3572 | advertising |= ADVERTISED_10baseT_Full; |
| 3573 | } |
| 3574 | |
| 3575 | phydev->advertising = advertising; |
| 3576 | |
| 3577 | phy_start_aneg(phydev); |
Matt Carlson | 0a459aa | 2008-11-03 16:54:15 -0800 | [diff] [blame] | 3578 | |
| 3579 | phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; |
Matt Carlson | 6a443a0 | 2010-02-17 15:17:04 +0000 | [diff] [blame] | 3580 | if (phyid != PHY_ID_BCMAC131) { |
| 3581 | phyid &= PHY_BCM_OUI_MASK; |
| 3582 | if (phyid == PHY_BCM_OUI_1 || |
| 3583 | phyid == PHY_BCM_OUI_2 || |
| 3584 | phyid == PHY_BCM_OUI_3) |
Matt Carlson | 0a459aa | 2008-11-03 16:54:15 -0800 | [diff] [blame] | 3585 | do_low_power = true; |
| 3586 | } |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 3587 | } |
Matt Carlson | dd47700 | 2008-05-25 23:45:58 -0700 | [diff] [blame] | 3588 | } else { |
Matt Carlson | 2023276 | 2008-12-21 20:18:56 -0800 | [diff] [blame] | 3589 | do_low_power = true; |
Matt Carlson | 0a459aa | 2008-11-03 16:54:15 -0800 | [diff] [blame] | 3590 | |
Matt Carlson | 80096068 | 2010-08-02 11:26:06 +0000 | [diff] [blame] | 3591 | if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
| 3592 | tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; |
Matt Carlson | dd47700 | 2008-05-25 23:45:58 -0700 | [diff] [blame] | 3593 | tp->link_config.orig_speed = tp->link_config.speed; |
| 3594 | tp->link_config.orig_duplex = tp->link_config.duplex; |
| 3595 | tp->link_config.orig_autoneg = tp->link_config.autoneg; |
| 3596 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3597 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 3598 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
Matt Carlson | dd47700 | 2008-05-25 23:45:58 -0700 | [diff] [blame] | 3599 | tp->link_config.speed = SPEED_10; |
| 3600 | tp->link_config.duplex = DUPLEX_HALF; |
| 3601 | tp->link_config.autoneg = AUTONEG_ENABLE; |
| 3602 | tg3_setup_phy(tp, 0); |
| 3603 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3604 | } |
| 3605 | |
Michael Chan | b5d3772 | 2006-09-27 16:06:21 -0700 | [diff] [blame] | 3606 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
| 3607 | u32 val; |
| 3608 | |
| 3609 | val = tr32(GRC_VCPU_EXT_CTRL); |
| 3610 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 3611 | } else if (!tg3_flag(tp, ENABLE_ASF)) { |
Michael Chan | 6921d20 | 2005-12-13 21:15:53 -0800 | [diff] [blame] | 3612 | int i; |
| 3613 | u32 val; |
| 3614 | |
| 3615 | for (i = 0; i < 200; i++) { |
| 3616 | tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); |
| 3617 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) |
| 3618 | break; |
| 3619 | msleep(1); |
| 3620 | } |
| 3621 | } |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 3622 | if (tg3_flag(tp, WOL_CAP)) |
Gary Zambrano | a85feb8 | 2007-05-05 11:52:19 -0700 | [diff] [blame] | 3623 | tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | |
| 3624 | WOL_DRV_STATE_SHUTDOWN | |
| 3625 | WOL_DRV_WOL | |
| 3626 | WOL_SET_MAGIC_PKT); |
Michael Chan | 6921d20 | 2005-12-13 21:15:53 -0800 | [diff] [blame] | 3627 | |
Matt Carlson | 05ac4cb | 2008-11-03 16:53:46 -0800 | [diff] [blame] | 3628 | if (device_should_wake) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3629 | u32 mac_mode; |
| 3630 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 3631 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
Matt Carlson | b4bd292 | 2011-04-20 07:57:41 +0000 | [diff] [blame] | 3632 | if (do_low_power && |
| 3633 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { |
| 3634 | tg3_phy_auxctl_write(tp, |
| 3635 | MII_TG3_AUXCTL_SHDWSEL_PWRCTL, |
| 3636 | MII_TG3_AUXCTL_PCTL_WOL_EN | |
| 3637 | MII_TG3_AUXCTL_PCTL_100TX_LPWR | |
| 3638 | MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC); |
Matt Carlson | dd47700 | 2008-05-25 23:45:58 -0700 | [diff] [blame] | 3639 | udelay(40); |
| 3640 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3641 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 3642 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
Michael Chan | 3f7045c | 2006-09-27 16:02:29 -0700 | [diff] [blame] | 3643 | mac_mode = MAC_MODE_PORT_MODE_GMII; |
| 3644 | else |
| 3645 | mac_mode = MAC_MODE_PORT_MODE_MII; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3646 | |
Matt Carlson | e8f3f6c | 2007-07-11 19:47:55 -0700 | [diff] [blame] | 3647 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; |
| 3648 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
| 3649 | ASIC_REV_5700) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 3650 | u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ? |
Matt Carlson | e8f3f6c | 2007-07-11 19:47:55 -0700 | [diff] [blame] | 3651 | SPEED_100 : SPEED_10; |
| 3652 | if (tg3_5700_link_polarity(tp, speed)) |
| 3653 | mac_mode |= MAC_MODE_LINK_POLARITY; |
| 3654 | else |
| 3655 | mac_mode &= ~MAC_MODE_LINK_POLARITY; |
| 3656 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3657 | } else { |
| 3658 | mac_mode = MAC_MODE_PORT_MODE_TBI; |
| 3659 | } |
| 3660 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 3661 | if (!tg3_flag(tp, 5750_PLUS)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3662 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
| 3663 | |
Matt Carlson | 05ac4cb | 2008-11-03 16:53:46 -0800 | [diff] [blame] | 3664 | mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 3665 | if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) && |
| 3666 | (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE))) |
Matt Carlson | 05ac4cb | 2008-11-03 16:53:46 -0800 | [diff] [blame] | 3667 | mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3668 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 3669 | if (tg3_flag(tp, ENABLE_APE)) |
Matt Carlson | d2394e6b | 2010-11-24 08:31:47 +0000 | [diff] [blame] | 3670 | mac_mode |= MAC_MODE_APE_TX_EN | |
| 3671 | MAC_MODE_APE_RX_EN | |
| 3672 | MAC_MODE_TDE_ENABLE; |
Matt Carlson | 3bda125 | 2008-08-15 14:08:22 -0700 | [diff] [blame] | 3673 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3674 | tw32_f(MAC_MODE, mac_mode); |
| 3675 | udelay(100); |
| 3676 | |
| 3677 | tw32_f(MAC_RX_MODE, RX_MODE_ENABLE); |
| 3678 | udelay(10); |
| 3679 | } |
| 3680 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 3681 | if (!tg3_flag(tp, WOL_SPEED_100MB) && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3682 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
| 3683 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { |
| 3684 | u32 base_val; |
| 3685 | |
| 3686 | base_val = tp->pci_clock_ctrl; |
| 3687 | base_val |= (CLOCK_CTRL_RXCLK_DISABLE | |
| 3688 | CLOCK_CTRL_TXCLK_DISABLE); |
| 3689 | |
Michael Chan | b401e9e | 2005-12-19 16:27:04 -0800 | [diff] [blame] | 3690 | tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK | |
| 3691 | CLOCK_CTRL_PWRDOWN_PLL133, 40); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 3692 | } else if (tg3_flag(tp, 5780_CLASS) || |
| 3693 | tg3_flag(tp, CPMU_PRESENT) || |
Matt Carlson | 6ff6f81 | 2011-05-19 12:12:54 +0000 | [diff] [blame] | 3694 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
Michael Chan | 4cf78e4 | 2005-07-25 12:29:19 -0700 | [diff] [blame] | 3695 | /* do nothing */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 3696 | } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3697 | u32 newbits1, newbits2; |
| 3698 | |
| 3699 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
| 3700 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { |
| 3701 | newbits1 = (CLOCK_CTRL_RXCLK_DISABLE | |
| 3702 | CLOCK_CTRL_TXCLK_DISABLE | |
| 3703 | CLOCK_CTRL_ALTCLK); |
| 3704 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 3705 | } else if (tg3_flag(tp, 5705_PLUS)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3706 | newbits1 = CLOCK_CTRL_625_CORE; |
| 3707 | newbits2 = newbits1 | CLOCK_CTRL_ALTCLK; |
| 3708 | } else { |
| 3709 | newbits1 = CLOCK_CTRL_ALTCLK; |
| 3710 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; |
| 3711 | } |
| 3712 | |
Michael Chan | b401e9e | 2005-12-19 16:27:04 -0800 | [diff] [blame] | 3713 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, |
| 3714 | 40); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3715 | |
Michael Chan | b401e9e | 2005-12-19 16:27:04 -0800 | [diff] [blame] | 3716 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, |
| 3717 | 40); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3718 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 3719 | if (!tg3_flag(tp, 5705_PLUS)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3720 | u32 newbits3; |
| 3721 | |
| 3722 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
| 3723 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { |
| 3724 | newbits3 = (CLOCK_CTRL_RXCLK_DISABLE | |
| 3725 | CLOCK_CTRL_TXCLK_DISABLE | |
| 3726 | CLOCK_CTRL_44MHZ_CORE); |
| 3727 | } else { |
| 3728 | newbits3 = CLOCK_CTRL_44MHZ_CORE; |
| 3729 | } |
| 3730 | |
Michael Chan | b401e9e | 2005-12-19 16:27:04 -0800 | [diff] [blame] | 3731 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
| 3732 | tp->pci_clock_ctrl | newbits3, 40); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3733 | } |
| 3734 | } |
| 3735 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 3736 | if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF)) |
Matt Carlson | 0a459aa | 2008-11-03 16:54:15 -0800 | [diff] [blame] | 3737 | tg3_power_down_phy(tp, do_low_power); |
Michael Chan | 6921d20 | 2005-12-13 21:15:53 -0800 | [diff] [blame] | 3738 | |
Matt Carlson | cd0d722 | 2011-07-13 09:27:33 +0000 | [diff] [blame] | 3739 | tg3_frob_aux_power(tp, true); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3740 | |
| 3741 | /* Workaround for unstable PLL clock */ |
| 3742 | if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || |
| 3743 | (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { |
| 3744 | u32 val = tr32(0x7d00); |
| 3745 | |
| 3746 | val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); |
| 3747 | tw32(0x7d00, val); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 3748 | if (!tg3_flag(tp, ENABLE_ASF)) { |
Michael Chan | ec41c7d | 2006-01-17 02:40:55 -0800 | [diff] [blame] | 3749 | int err; |
| 3750 | |
| 3751 | err = tg3_nvram_lock(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3752 | tg3_halt_cpu(tp, RX_CPU_BASE); |
Michael Chan | ec41c7d | 2006-01-17 02:40:55 -0800 | [diff] [blame] | 3753 | if (!err) |
| 3754 | tg3_nvram_unlock(tp); |
Michael Chan | 6921d20 | 2005-12-13 21:15:53 -0800 | [diff] [blame] | 3755 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3756 | } |
| 3757 | |
Michael Chan | bbadf50 | 2006-04-06 21:46:34 -0700 | [diff] [blame] | 3758 | tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); |
| 3759 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3760 | return 0; |
| 3761 | } |
| 3762 | |
Rafael J. Wysocki | c866b7e | 2010-12-25 12:56:23 +0000 | [diff] [blame] | 3763 | static void tg3_power_down(struct tg3 *tp) |
| 3764 | { |
| 3765 | tg3_power_down_prepare(tp); |
| 3766 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 3767 | pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); |
Rafael J. Wysocki | c866b7e | 2010-12-25 12:56:23 +0000 | [diff] [blame] | 3768 | pci_set_power_state(tp->pdev, PCI_D3hot); |
| 3769 | } |
| 3770 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3771 | static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) |
| 3772 | { |
| 3773 | switch (val & MII_TG3_AUX_STAT_SPDMASK) { |
| 3774 | case MII_TG3_AUX_STAT_10HALF: |
| 3775 | *speed = SPEED_10; |
| 3776 | *duplex = DUPLEX_HALF; |
| 3777 | break; |
| 3778 | |
| 3779 | case MII_TG3_AUX_STAT_10FULL: |
| 3780 | *speed = SPEED_10; |
| 3781 | *duplex = DUPLEX_FULL; |
| 3782 | break; |
| 3783 | |
| 3784 | case MII_TG3_AUX_STAT_100HALF: |
| 3785 | *speed = SPEED_100; |
| 3786 | *duplex = DUPLEX_HALF; |
| 3787 | break; |
| 3788 | |
| 3789 | case MII_TG3_AUX_STAT_100FULL: |
| 3790 | *speed = SPEED_100; |
| 3791 | *duplex = DUPLEX_FULL; |
| 3792 | break; |
| 3793 | |
| 3794 | case MII_TG3_AUX_STAT_1000HALF: |
| 3795 | *speed = SPEED_1000; |
| 3796 | *duplex = DUPLEX_HALF; |
| 3797 | break; |
| 3798 | |
| 3799 | case MII_TG3_AUX_STAT_1000FULL: |
| 3800 | *speed = SPEED_1000; |
| 3801 | *duplex = DUPLEX_FULL; |
| 3802 | break; |
| 3803 | |
| 3804 | default: |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 3805 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
Michael Chan | 715116a | 2006-09-27 16:09:25 -0700 | [diff] [blame] | 3806 | *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : |
| 3807 | SPEED_10; |
| 3808 | *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : |
| 3809 | DUPLEX_HALF; |
| 3810 | break; |
| 3811 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3812 | *speed = SPEED_INVALID; |
| 3813 | *duplex = DUPLEX_INVALID; |
| 3814 | break; |
Stephen Hemminger | 855e111 | 2008-04-16 16:37:28 -0700 | [diff] [blame] | 3815 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3816 | } |
| 3817 | |
Matt Carlson | 42b64a4 | 2011-05-19 12:12:49 +0000 | [diff] [blame] | 3818 | static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3819 | { |
Matt Carlson | 42b64a4 | 2011-05-19 12:12:49 +0000 | [diff] [blame] | 3820 | int err = 0; |
| 3821 | u32 val, new_adv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3822 | |
Matt Carlson | 42b64a4 | 2011-05-19 12:12:49 +0000 | [diff] [blame] | 3823 | new_adv = ADVERTISE_CSMA; |
Hiroaki SHIMODA | 202ff1c | 2011-11-22 04:05:41 +0000 | [diff] [blame] | 3824 | new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL; |
Matt Carlson | f88788f | 2011-12-14 11:10:00 +0000 | [diff] [blame] | 3825 | new_adv |= mii_advertise_flowctrl(flowctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3826 | |
Matt Carlson | 42b64a4 | 2011-05-19 12:12:49 +0000 | [diff] [blame] | 3827 | err = tg3_writephy(tp, MII_ADVERTISE, new_adv); |
| 3828 | if (err) |
| 3829 | goto done; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3830 | |
Matt Carlson | 4f27209 | 2011-12-14 11:09:57 +0000 | [diff] [blame] | 3831 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
| 3832 | new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise); |
Matt Carlson | ba4d07a | 2007-12-20 20:08:00 -0800 | [diff] [blame] | 3833 | |
Matt Carlson | 4f27209 | 2011-12-14 11:09:57 +0000 | [diff] [blame] | 3834 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || |
| 3835 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) |
| 3836 | new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; |
Matt Carlson | ba4d07a | 2007-12-20 20:08:00 -0800 | [diff] [blame] | 3837 | |
Matt Carlson | 4f27209 | 2011-12-14 11:09:57 +0000 | [diff] [blame] | 3838 | err = tg3_writephy(tp, MII_CTRL1000, new_adv); |
| 3839 | if (err) |
| 3840 | goto done; |
| 3841 | } |
Matt Carlson | ba4d07a | 2007-12-20 20:08:00 -0800 | [diff] [blame] | 3842 | |
Matt Carlson | 42b64a4 | 2011-05-19 12:12:49 +0000 | [diff] [blame] | 3843 | if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) |
| 3844 | goto done; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3845 | |
Matt Carlson | 42b64a4 | 2011-05-19 12:12:49 +0000 | [diff] [blame] | 3846 | tw32(TG3_CPMU_EEE_MODE, |
| 3847 | tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE); |
Matt Carlson | ba4d07a | 2007-12-20 20:08:00 -0800 | [diff] [blame] | 3848 | |
Matt Carlson | 42b64a4 | 2011-05-19 12:12:49 +0000 | [diff] [blame] | 3849 | err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp); |
| 3850 | if (!err) { |
| 3851 | u32 err2; |
Matt Carlson | 52b02d0 | 2010-10-14 10:37:41 +0000 | [diff] [blame] | 3852 | |
Matt Carlson | a6b68da | 2010-12-06 08:28:52 +0000 | [diff] [blame] | 3853 | val = 0; |
Matt Carlson | 42b64a4 | 2011-05-19 12:12:49 +0000 | [diff] [blame] | 3854 | /* Advertise 100-BaseTX EEE ability */ |
| 3855 | if (advertise & ADVERTISED_100baseT_Full) |
| 3856 | val |= MDIO_AN_EEE_ADV_100TX; |
| 3857 | /* Advertise 1000-BaseT EEE ability */ |
| 3858 | if (advertise & ADVERTISED_1000baseT_Full) |
| 3859 | val |= MDIO_AN_EEE_ADV_1000T; |
| 3860 | err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); |
Matt Carlson | b715ce9 | 2011-07-20 10:20:52 +0000 | [diff] [blame] | 3861 | if (err) |
| 3862 | val = 0; |
| 3863 | |
| 3864 | switch (GET_ASIC_REV(tp->pci_chip_rev_id)) { |
| 3865 | case ASIC_REV_5717: |
| 3866 | case ASIC_REV_57765: |
Matt Carlson | 55086ad | 2011-12-14 11:09:59 +0000 | [diff] [blame] | 3867 | case ASIC_REV_57766: |
Matt Carlson | b715ce9 | 2011-07-20 10:20:52 +0000 | [diff] [blame] | 3868 | case ASIC_REV_5719: |
| 3869 | /* If we advertised any eee advertisements above... */ |
| 3870 | if (val) |
| 3871 | val = MII_TG3_DSP_TAP26_ALNOKO | |
| 3872 | MII_TG3_DSP_TAP26_RMRXSTO | |
| 3873 | MII_TG3_DSP_TAP26_OPCSINPT; |
| 3874 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); |
| 3875 | /* Fall through */ |
| 3876 | case ASIC_REV_5720: |
| 3877 | if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) |
| 3878 | tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | |
| 3879 | MII_TG3_DSP_CH34TP2_HIBW01); |
| 3880 | } |
Matt Carlson | 52b02d0 | 2010-10-14 10:37:41 +0000 | [diff] [blame] | 3881 | |
Matt Carlson | 42b64a4 | 2011-05-19 12:12:49 +0000 | [diff] [blame] | 3882 | err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
| 3883 | if (!err) |
| 3884 | err = err2; |
| 3885 | } |
| 3886 | |
| 3887 | done: |
| 3888 | return err; |
| 3889 | } |
| 3890 | |
| 3891 | static void tg3_phy_copper_begin(struct tg3 *tp) |
| 3892 | { |
| 3893 | u32 new_adv; |
| 3894 | int i; |
| 3895 | |
| 3896 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
| 3897 | new_adv = ADVERTISED_10baseT_Half | |
| 3898 | ADVERTISED_10baseT_Full; |
| 3899 | if (tg3_flag(tp, WOL_SPEED_100MB)) |
| 3900 | new_adv |= ADVERTISED_100baseT_Half | |
| 3901 | ADVERTISED_100baseT_Full; |
| 3902 | |
| 3903 | tg3_phy_autoneg_cfg(tp, new_adv, |
| 3904 | FLOW_CTRL_TX | FLOW_CTRL_RX); |
| 3905 | } else if (tp->link_config.speed == SPEED_INVALID) { |
| 3906 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) |
| 3907 | tp->link_config.advertising &= |
| 3908 | ~(ADVERTISED_1000baseT_Half | |
| 3909 | ADVERTISED_1000baseT_Full); |
| 3910 | |
| 3911 | tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, |
| 3912 | tp->link_config.flowctrl); |
| 3913 | } else { |
| 3914 | /* Asking for a specific link mode. */ |
| 3915 | if (tp->link_config.speed == SPEED_1000) { |
| 3916 | if (tp->link_config.duplex == DUPLEX_FULL) |
| 3917 | new_adv = ADVERTISED_1000baseT_Full; |
| 3918 | else |
| 3919 | new_adv = ADVERTISED_1000baseT_Half; |
| 3920 | } else if (tp->link_config.speed == SPEED_100) { |
| 3921 | if (tp->link_config.duplex == DUPLEX_FULL) |
| 3922 | new_adv = ADVERTISED_100baseT_Full; |
| 3923 | else |
| 3924 | new_adv = ADVERTISED_100baseT_Half; |
| 3925 | } else { |
| 3926 | if (tp->link_config.duplex == DUPLEX_FULL) |
| 3927 | new_adv = ADVERTISED_10baseT_Full; |
| 3928 | else |
| 3929 | new_adv = ADVERTISED_10baseT_Half; |
| 3930 | } |
| 3931 | |
| 3932 | tg3_phy_autoneg_cfg(tp, new_adv, |
| 3933 | tp->link_config.flowctrl); |
Matt Carlson | 52b02d0 | 2010-10-14 10:37:41 +0000 | [diff] [blame] | 3934 | } |
| 3935 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3936 | if (tp->link_config.autoneg == AUTONEG_DISABLE && |
| 3937 | tp->link_config.speed != SPEED_INVALID) { |
| 3938 | u32 bmcr, orig_bmcr; |
| 3939 | |
| 3940 | tp->link_config.active_speed = tp->link_config.speed; |
| 3941 | tp->link_config.active_duplex = tp->link_config.duplex; |
| 3942 | |
| 3943 | bmcr = 0; |
| 3944 | switch (tp->link_config.speed) { |
| 3945 | default: |
| 3946 | case SPEED_10: |
| 3947 | break; |
| 3948 | |
| 3949 | case SPEED_100: |
| 3950 | bmcr |= BMCR_SPEED100; |
| 3951 | break; |
| 3952 | |
| 3953 | case SPEED_1000: |
Matt Carlson | 221c563 | 2011-06-13 13:39:01 +0000 | [diff] [blame] | 3954 | bmcr |= BMCR_SPEED1000; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3955 | break; |
Stephen Hemminger | 855e111 | 2008-04-16 16:37:28 -0700 | [diff] [blame] | 3956 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3957 | |
| 3958 | if (tp->link_config.duplex == DUPLEX_FULL) |
| 3959 | bmcr |= BMCR_FULLDPLX; |
| 3960 | |
| 3961 | if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && |
| 3962 | (bmcr != orig_bmcr)) { |
| 3963 | tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); |
| 3964 | for (i = 0; i < 1500; i++) { |
| 3965 | u32 tmp; |
| 3966 | |
| 3967 | udelay(10); |
| 3968 | if (tg3_readphy(tp, MII_BMSR, &tmp) || |
| 3969 | tg3_readphy(tp, MII_BMSR, &tmp)) |
| 3970 | continue; |
| 3971 | if (!(tmp & BMSR_LSTATUS)) { |
| 3972 | udelay(40); |
| 3973 | break; |
| 3974 | } |
| 3975 | } |
| 3976 | tg3_writephy(tp, MII_BMCR, bmcr); |
| 3977 | udelay(40); |
| 3978 | } |
| 3979 | } else { |
| 3980 | tg3_writephy(tp, MII_BMCR, |
| 3981 | BMCR_ANENABLE | BMCR_ANRESTART); |
| 3982 | } |
| 3983 | } |
| 3984 | |
| 3985 | static int tg3_init_5401phy_dsp(struct tg3 *tp) |
| 3986 | { |
| 3987 | int err; |
| 3988 | |
| 3989 | /* Turn off tap power management. */ |
| 3990 | /* Set Extended packet length bit */ |
Matt Carlson | b4bd292 | 2011-04-20 07:57:41 +0000 | [diff] [blame] | 3991 | err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3992 | |
Matt Carlson | 6ee7c0a | 2010-08-02 11:26:04 +0000 | [diff] [blame] | 3993 | err |= tg3_phydsp_write(tp, 0x0012, 0x1804); |
| 3994 | err |= tg3_phydsp_write(tp, 0x0013, 0x1204); |
| 3995 | err |= tg3_phydsp_write(tp, 0x8006, 0x0132); |
| 3996 | err |= tg3_phydsp_write(tp, 0x8006, 0x0232); |
| 3997 | err |= tg3_phydsp_write(tp, 0x201f, 0x0a20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3998 | |
| 3999 | udelay(40); |
| 4000 | |
| 4001 | return err; |
| 4002 | } |
| 4003 | |
Matt Carlson | e2bf73e | 2011-12-08 14:40:15 +0000 | [diff] [blame] | 4004 | static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4005 | { |
Matt Carlson | e2bf73e | 2011-12-08 14:40:15 +0000 | [diff] [blame] | 4006 | u32 advmsk, tgtadv, advertising; |
Michael Chan | 3600d91 | 2006-12-07 00:21:48 -0800 | [diff] [blame] | 4007 | |
Matt Carlson | e2bf73e | 2011-12-08 14:40:15 +0000 | [diff] [blame] | 4008 | advertising = tp->link_config.advertising; |
| 4009 | tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4010 | |
Matt Carlson | e2bf73e | 2011-12-08 14:40:15 +0000 | [diff] [blame] | 4011 | advmsk = ADVERTISE_ALL; |
| 4012 | if (tp->link_config.active_duplex == DUPLEX_FULL) { |
Matt Carlson | f88788f | 2011-12-14 11:10:00 +0000 | [diff] [blame] | 4013 | tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl); |
Matt Carlson | e2bf73e | 2011-12-08 14:40:15 +0000 | [diff] [blame] | 4014 | advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
| 4015 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4016 | |
Matt Carlson | e2bf73e | 2011-12-08 14:40:15 +0000 | [diff] [blame] | 4017 | if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) |
| 4018 | return false; |
| 4019 | |
| 4020 | if ((*lcladv & advmsk) != tgtadv) |
| 4021 | return false; |
Matt Carlson | b99d2a5 | 2011-08-31 11:44:47 +0000 | [diff] [blame] | 4022 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 4023 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4024 | u32 tg3_ctrl; |
| 4025 | |
Matt Carlson | e2bf73e | 2011-12-08 14:40:15 +0000 | [diff] [blame] | 4026 | tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising); |
Michael Chan | 3600d91 | 2006-12-07 00:21:48 -0800 | [diff] [blame] | 4027 | |
Matt Carlson | 221c563 | 2011-06-13 13:39:01 +0000 | [diff] [blame] | 4028 | if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl)) |
Matt Carlson | e2bf73e | 2011-12-08 14:40:15 +0000 | [diff] [blame] | 4029 | return false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4030 | |
Matt Carlson | b99d2a5 | 2011-08-31 11:44:47 +0000 | [diff] [blame] | 4031 | tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL); |
Matt Carlson | e2bf73e | 2011-12-08 14:40:15 +0000 | [diff] [blame] | 4032 | if (tg3_ctrl != tgtadv) |
| 4033 | return false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4034 | } |
Matt Carlson | 93a700a | 2011-08-31 11:44:54 +0000 | [diff] [blame] | 4035 | |
Matt Carlson | e2bf73e | 2011-12-08 14:40:15 +0000 | [diff] [blame] | 4036 | return true; |
Matt Carlson | ef167e2 | 2007-12-20 20:10:01 -0800 | [diff] [blame] | 4037 | } |
| 4038 | |
Matt Carlson | 859edb2 | 2011-12-08 14:40:16 +0000 | [diff] [blame] | 4039 | static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv) |
| 4040 | { |
| 4041 | u32 lpeth = 0; |
| 4042 | |
| 4043 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
| 4044 | u32 val; |
| 4045 | |
| 4046 | if (tg3_readphy(tp, MII_STAT1000, &val)) |
| 4047 | return false; |
| 4048 | |
| 4049 | lpeth = mii_stat1000_to_ethtool_lpa_t(val); |
| 4050 | } |
| 4051 | |
| 4052 | if (tg3_readphy(tp, MII_LPA, rmtadv)) |
| 4053 | return false; |
| 4054 | |
| 4055 | lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv); |
| 4056 | tp->link_config.rmt_adv = lpeth; |
| 4057 | |
| 4058 | return true; |
| 4059 | } |
| 4060 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4061 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) |
| 4062 | { |
| 4063 | int current_link_up; |
Matt Carlson | f833c4c | 2010-09-15 09:00:01 +0000 | [diff] [blame] | 4064 | u32 bmsr, val; |
Matt Carlson | ef167e2 | 2007-12-20 20:10:01 -0800 | [diff] [blame] | 4065 | u32 lcl_adv, rmt_adv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4066 | u16 current_speed; |
| 4067 | u8 current_duplex; |
| 4068 | int i, err; |
| 4069 | |
| 4070 | tw32(MAC_EVENT, 0); |
| 4071 | |
| 4072 | tw32_f(MAC_STATUS, |
| 4073 | (MAC_STATUS_SYNC_CHANGED | |
| 4074 | MAC_STATUS_CFG_CHANGED | |
| 4075 | MAC_STATUS_MI_COMPLETION | |
| 4076 | MAC_STATUS_LNKSTATE_CHANGED)); |
| 4077 | udelay(40); |
| 4078 | |
Matt Carlson | 8ef2142 | 2008-05-02 16:47:53 -0700 | [diff] [blame] | 4079 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
| 4080 | tw32_f(MAC_MI_MODE, |
| 4081 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); |
| 4082 | udelay(80); |
| 4083 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4084 | |
Matt Carlson | b4bd292 | 2011-04-20 07:57:41 +0000 | [diff] [blame] | 4085 | tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4086 | |
| 4087 | /* Some third-party PHYs need to be reset on link going |
| 4088 | * down. |
| 4089 | */ |
| 4090 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || |
| 4091 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
| 4092 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && |
| 4093 | netif_carrier_ok(tp->dev)) { |
| 4094 | tg3_readphy(tp, MII_BMSR, &bmsr); |
| 4095 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && |
| 4096 | !(bmsr & BMSR_LSTATUS)) |
| 4097 | force_reset = 1; |
| 4098 | } |
| 4099 | if (force_reset) |
| 4100 | tg3_phy_reset(tp); |
| 4101 | |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 4102 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4103 | tg3_readphy(tp, MII_BMSR, &bmsr); |
| 4104 | if (tg3_readphy(tp, MII_BMSR, &bmsr) || |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 4105 | !tg3_flag(tp, INIT_COMPLETE)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4106 | bmsr = 0; |
| 4107 | |
| 4108 | if (!(bmsr & BMSR_LSTATUS)) { |
| 4109 | err = tg3_init_5401phy_dsp(tp); |
| 4110 | if (err) |
| 4111 | return err; |
| 4112 | |
| 4113 | tg3_readphy(tp, MII_BMSR, &bmsr); |
| 4114 | for (i = 0; i < 1000; i++) { |
| 4115 | udelay(10); |
| 4116 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && |
| 4117 | (bmsr & BMSR_LSTATUS)) { |
| 4118 | udelay(40); |
| 4119 | break; |
| 4120 | } |
| 4121 | } |
| 4122 | |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 4123 | if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == |
| 4124 | TG3_PHY_REV_BCM5401_B0 && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4125 | !(bmsr & BMSR_LSTATUS) && |
| 4126 | tp->link_config.active_speed == SPEED_1000) { |
| 4127 | err = tg3_phy_reset(tp); |
| 4128 | if (!err) |
| 4129 | err = tg3_init_5401phy_dsp(tp); |
| 4130 | if (err) |
| 4131 | return err; |
| 4132 | } |
| 4133 | } |
| 4134 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || |
| 4135 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { |
| 4136 | /* 5701 {A0,B0} CRC bug workaround */ |
| 4137 | tg3_writephy(tp, 0x15, 0x0a75); |
Matt Carlson | f08aa1a | 2010-08-02 11:26:05 +0000 | [diff] [blame] | 4138 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); |
| 4139 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); |
| 4140 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4141 | } |
| 4142 | |
| 4143 | /* Clear pending interrupts... */ |
Matt Carlson | f833c4c | 2010-09-15 09:00:01 +0000 | [diff] [blame] | 4144 | tg3_readphy(tp, MII_TG3_ISTAT, &val); |
| 4145 | tg3_readphy(tp, MII_TG3_ISTAT, &val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4146 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 4147 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4148 | tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 4149 | else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4150 | tg3_writephy(tp, MII_TG3_IMASK, ~0); |
| 4151 | |
| 4152 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
| 4153 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { |
| 4154 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) |
| 4155 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
| 4156 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); |
| 4157 | else |
| 4158 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); |
| 4159 | } |
| 4160 | |
| 4161 | current_link_up = 0; |
| 4162 | current_speed = SPEED_INVALID; |
| 4163 | current_duplex = DUPLEX_INVALID; |
Matt Carlson | e348c5e | 2011-11-21 15:01:20 +0000 | [diff] [blame] | 4164 | tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; |
Matt Carlson | 859edb2 | 2011-12-08 14:40:16 +0000 | [diff] [blame] | 4165 | tp->link_config.rmt_adv = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4166 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 4167 | if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { |
Matt Carlson | 15ee95c | 2011-04-20 07:57:40 +0000 | [diff] [blame] | 4168 | err = tg3_phy_auxctl_read(tp, |
| 4169 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, |
| 4170 | &val); |
| 4171 | if (!err && !(val & (1 << 10))) { |
Matt Carlson | b4bd292 | 2011-04-20 07:57:41 +0000 | [diff] [blame] | 4172 | tg3_phy_auxctl_write(tp, |
| 4173 | MII_TG3_AUXCTL_SHDWSEL_MISCTEST, |
| 4174 | val | (1 << 10)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4175 | goto relink; |
| 4176 | } |
| 4177 | } |
| 4178 | |
| 4179 | bmsr = 0; |
| 4180 | for (i = 0; i < 100; i++) { |
| 4181 | tg3_readphy(tp, MII_BMSR, &bmsr); |
| 4182 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && |
| 4183 | (bmsr & BMSR_LSTATUS)) |
| 4184 | break; |
| 4185 | udelay(40); |
| 4186 | } |
| 4187 | |
| 4188 | if (bmsr & BMSR_LSTATUS) { |
| 4189 | u32 aux_stat, bmcr; |
| 4190 | |
| 4191 | tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); |
| 4192 | for (i = 0; i < 2000; i++) { |
| 4193 | udelay(10); |
| 4194 | if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && |
| 4195 | aux_stat) |
| 4196 | break; |
| 4197 | } |
| 4198 | |
| 4199 | tg3_aux_stat_to_speed_duplex(tp, aux_stat, |
| 4200 | ¤t_speed, |
| 4201 | ¤t_duplex); |
| 4202 | |
| 4203 | bmcr = 0; |
| 4204 | for (i = 0; i < 200; i++) { |
| 4205 | tg3_readphy(tp, MII_BMCR, &bmcr); |
| 4206 | if (tg3_readphy(tp, MII_BMCR, &bmcr)) |
| 4207 | continue; |
| 4208 | if (bmcr && bmcr != 0x7fff) |
| 4209 | break; |
| 4210 | udelay(10); |
| 4211 | } |
| 4212 | |
Matt Carlson | ef167e2 | 2007-12-20 20:10:01 -0800 | [diff] [blame] | 4213 | lcl_adv = 0; |
| 4214 | rmt_adv = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4215 | |
Matt Carlson | ef167e2 | 2007-12-20 20:10:01 -0800 | [diff] [blame] | 4216 | tp->link_config.active_speed = current_speed; |
| 4217 | tp->link_config.active_duplex = current_duplex; |
| 4218 | |
| 4219 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { |
| 4220 | if ((bmcr & BMCR_ANENABLE) && |
Matt Carlson | e2bf73e | 2011-12-08 14:40:15 +0000 | [diff] [blame] | 4221 | tg3_phy_copper_an_config_ok(tp, &lcl_adv) && |
Matt Carlson | 859edb2 | 2011-12-08 14:40:16 +0000 | [diff] [blame] | 4222 | tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv)) |
Matt Carlson | e2bf73e | 2011-12-08 14:40:15 +0000 | [diff] [blame] | 4223 | current_link_up = 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4224 | } else { |
| 4225 | if (!(bmcr & BMCR_ANENABLE) && |
| 4226 | tp->link_config.speed == current_speed && |
Matt Carlson | ef167e2 | 2007-12-20 20:10:01 -0800 | [diff] [blame] | 4227 | tp->link_config.duplex == current_duplex && |
| 4228 | tp->link_config.flowctrl == |
| 4229 | tp->link_config.active_flowctrl) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4230 | current_link_up = 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4231 | } |
| 4232 | } |
| 4233 | |
Matt Carlson | ef167e2 | 2007-12-20 20:10:01 -0800 | [diff] [blame] | 4234 | if (current_link_up == 1 && |
Matt Carlson | e348c5e | 2011-11-21 15:01:20 +0000 | [diff] [blame] | 4235 | tp->link_config.active_duplex == DUPLEX_FULL) { |
| 4236 | u32 reg, bit; |
| 4237 | |
| 4238 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
| 4239 | reg = MII_TG3_FET_GEN_STAT; |
| 4240 | bit = MII_TG3_FET_GEN_STAT_MDIXSTAT; |
| 4241 | } else { |
| 4242 | reg = MII_TG3_EXT_STAT; |
| 4243 | bit = MII_TG3_EXT_STAT_MDIX; |
| 4244 | } |
| 4245 | |
| 4246 | if (!tg3_readphy(tp, reg, &val) && (val & bit)) |
| 4247 | tp->phy_flags |= TG3_PHYFLG_MDIX_STATE; |
| 4248 | |
Matt Carlson | ef167e2 | 2007-12-20 20:10:01 -0800 | [diff] [blame] | 4249 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); |
Matt Carlson | e348c5e | 2011-11-21 15:01:20 +0000 | [diff] [blame] | 4250 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4251 | } |
| 4252 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4253 | relink: |
Matt Carlson | 80096068 | 2010-08-02 11:26:06 +0000 | [diff] [blame] | 4254 | if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4255 | tg3_phy_copper_begin(tp); |
| 4256 | |
Matt Carlson | f833c4c | 2010-09-15 09:00:01 +0000 | [diff] [blame] | 4257 | tg3_readphy(tp, MII_BMSR, &bmsr); |
Mahesh Bandewar | 06c03c0 | 2011-05-08 06:51:48 +0000 | [diff] [blame] | 4258 | if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || |
| 4259 | (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4260 | current_link_up = 1; |
| 4261 | } |
| 4262 | |
| 4263 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; |
| 4264 | if (current_link_up == 1) { |
| 4265 | if (tp->link_config.active_speed == SPEED_100 || |
| 4266 | tp->link_config.active_speed == SPEED_10) |
| 4267 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; |
| 4268 | else |
| 4269 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 4270 | } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) |
Matt Carlson | 7f97a4b | 2009-08-25 10:10:03 +0000 | [diff] [blame] | 4271 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; |
| 4272 | else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4273 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
| 4274 | |
| 4275 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; |
| 4276 | if (tp->link_config.active_duplex == DUPLEX_HALF) |
| 4277 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; |
| 4278 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4279 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
Matt Carlson | e8f3f6c | 2007-07-11 19:47:55 -0700 | [diff] [blame] | 4280 | if (current_link_up == 1 && |
| 4281 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4282 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
Matt Carlson | e8f3f6c | 2007-07-11 19:47:55 -0700 | [diff] [blame] | 4283 | else |
| 4284 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4285 | } |
| 4286 | |
| 4287 | /* ??? Without this setting Netgear GA302T PHY does not |
| 4288 | * ??? send/receive packets... |
| 4289 | */ |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 4290 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4291 | tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { |
| 4292 | tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; |
| 4293 | tw32_f(MAC_MI_MODE, tp->mi_mode); |
| 4294 | udelay(80); |
| 4295 | } |
| 4296 | |
| 4297 | tw32_f(MAC_MODE, tp->mac_mode); |
| 4298 | udelay(40); |
| 4299 | |
Matt Carlson | 52b02d0 | 2010-10-14 10:37:41 +0000 | [diff] [blame] | 4300 | tg3_phy_eee_adjust(tp, current_link_up); |
| 4301 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 4302 | if (tg3_flag(tp, USE_LINKCHG_REG)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4303 | /* Polled via timer. */ |
| 4304 | tw32_f(MAC_EVENT, 0); |
| 4305 | } else { |
| 4306 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); |
| 4307 | } |
| 4308 | udelay(40); |
| 4309 | |
| 4310 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && |
| 4311 | current_link_up == 1 && |
| 4312 | tp->link_config.active_speed == SPEED_1000 && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 4313 | (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4314 | udelay(120); |
| 4315 | tw32_f(MAC_STATUS, |
| 4316 | (MAC_STATUS_SYNC_CHANGED | |
| 4317 | MAC_STATUS_CFG_CHANGED)); |
| 4318 | udelay(40); |
| 4319 | tg3_write_mem(tp, |
| 4320 | NIC_SRAM_FIRMWARE_MBOX, |
| 4321 | NIC_SRAM_FIRMWARE_MBOX_MAGIC2); |
| 4322 | } |
| 4323 | |
Matt Carlson | 5e7dfd0 | 2008-11-21 17:18:16 -0800 | [diff] [blame] | 4324 | /* Prevent send BD corruption. */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 4325 | if (tg3_flag(tp, CLKREQ_BUG)) { |
Matt Carlson | 5e7dfd0 | 2008-11-21 17:18:16 -0800 | [diff] [blame] | 4326 | u16 oldlnkctl, newlnkctl; |
| 4327 | |
| 4328 | pci_read_config_word(tp->pdev, |
Jon Mason | 708ebb3 | 2011-06-27 12:56:50 +0000 | [diff] [blame] | 4329 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
Matt Carlson | 5e7dfd0 | 2008-11-21 17:18:16 -0800 | [diff] [blame] | 4330 | &oldlnkctl); |
| 4331 | if (tp->link_config.active_speed == SPEED_100 || |
| 4332 | tp->link_config.active_speed == SPEED_10) |
| 4333 | newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN; |
| 4334 | else |
| 4335 | newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN; |
| 4336 | if (newlnkctl != oldlnkctl) |
| 4337 | pci_write_config_word(tp->pdev, |
Matt Carlson | 93a700a | 2011-08-31 11:44:54 +0000 | [diff] [blame] | 4338 | pci_pcie_cap(tp->pdev) + |
| 4339 | PCI_EXP_LNKCTL, newlnkctl); |
Matt Carlson | 5e7dfd0 | 2008-11-21 17:18:16 -0800 | [diff] [blame] | 4340 | } |
| 4341 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4342 | if (current_link_up != netif_carrier_ok(tp->dev)) { |
| 4343 | if (current_link_up) |
| 4344 | netif_carrier_on(tp->dev); |
| 4345 | else |
| 4346 | netif_carrier_off(tp->dev); |
| 4347 | tg3_link_report(tp); |
| 4348 | } |
| 4349 | |
| 4350 | return 0; |
| 4351 | } |
| 4352 | |
| 4353 | struct tg3_fiber_aneginfo { |
| 4354 | int state; |
| 4355 | #define ANEG_STATE_UNKNOWN 0 |
| 4356 | #define ANEG_STATE_AN_ENABLE 1 |
| 4357 | #define ANEG_STATE_RESTART_INIT 2 |
| 4358 | #define ANEG_STATE_RESTART 3 |
| 4359 | #define ANEG_STATE_DISABLE_LINK_OK 4 |
| 4360 | #define ANEG_STATE_ABILITY_DETECT_INIT 5 |
| 4361 | #define ANEG_STATE_ABILITY_DETECT 6 |
| 4362 | #define ANEG_STATE_ACK_DETECT_INIT 7 |
| 4363 | #define ANEG_STATE_ACK_DETECT 8 |
| 4364 | #define ANEG_STATE_COMPLETE_ACK_INIT 9 |
| 4365 | #define ANEG_STATE_COMPLETE_ACK 10 |
| 4366 | #define ANEG_STATE_IDLE_DETECT_INIT 11 |
| 4367 | #define ANEG_STATE_IDLE_DETECT 12 |
| 4368 | #define ANEG_STATE_LINK_OK 13 |
| 4369 | #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 |
| 4370 | #define ANEG_STATE_NEXT_PAGE_WAIT 15 |
| 4371 | |
| 4372 | u32 flags; |
| 4373 | #define MR_AN_ENABLE 0x00000001 |
| 4374 | #define MR_RESTART_AN 0x00000002 |
| 4375 | #define MR_AN_COMPLETE 0x00000004 |
| 4376 | #define MR_PAGE_RX 0x00000008 |
| 4377 | #define MR_NP_LOADED 0x00000010 |
| 4378 | #define MR_TOGGLE_TX 0x00000020 |
| 4379 | #define MR_LP_ADV_FULL_DUPLEX 0x00000040 |
| 4380 | #define MR_LP_ADV_HALF_DUPLEX 0x00000080 |
| 4381 | #define MR_LP_ADV_SYM_PAUSE 0x00000100 |
| 4382 | #define MR_LP_ADV_ASYM_PAUSE 0x00000200 |
| 4383 | #define MR_LP_ADV_REMOTE_FAULT1 0x00000400 |
| 4384 | #define MR_LP_ADV_REMOTE_FAULT2 0x00000800 |
| 4385 | #define MR_LP_ADV_NEXT_PAGE 0x00001000 |
| 4386 | #define MR_TOGGLE_RX 0x00002000 |
| 4387 | #define MR_NP_RX 0x00004000 |
| 4388 | |
| 4389 | #define MR_LINK_OK 0x80000000 |
| 4390 | |
| 4391 | unsigned long link_time, cur_time; |
| 4392 | |
| 4393 | u32 ability_match_cfg; |
| 4394 | int ability_match_count; |
| 4395 | |
| 4396 | char ability_match, idle_match, ack_match; |
| 4397 | |
| 4398 | u32 txconfig, rxconfig; |
| 4399 | #define ANEG_CFG_NP 0x00000080 |
| 4400 | #define ANEG_CFG_ACK 0x00000040 |
| 4401 | #define ANEG_CFG_RF2 0x00000020 |
| 4402 | #define ANEG_CFG_RF1 0x00000010 |
| 4403 | #define ANEG_CFG_PS2 0x00000001 |
| 4404 | #define ANEG_CFG_PS1 0x00008000 |
| 4405 | #define ANEG_CFG_HD 0x00004000 |
| 4406 | #define ANEG_CFG_FD 0x00002000 |
| 4407 | #define ANEG_CFG_INVAL 0x00001f06 |
| 4408 | |
| 4409 | }; |
| 4410 | #define ANEG_OK 0 |
| 4411 | #define ANEG_DONE 1 |
| 4412 | #define ANEG_TIMER_ENAB 2 |
| 4413 | #define ANEG_FAILED -1 |
| 4414 | |
| 4415 | #define ANEG_STATE_SETTLE_TIME 10000 |
| 4416 | |
| 4417 | static int tg3_fiber_aneg_smachine(struct tg3 *tp, |
| 4418 | struct tg3_fiber_aneginfo *ap) |
| 4419 | { |
Matt Carlson | 5be73b4 | 2007-12-20 20:09:29 -0800 | [diff] [blame] | 4420 | u16 flowctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4421 | unsigned long delta; |
| 4422 | u32 rx_cfg_reg; |
| 4423 | int ret; |
| 4424 | |
| 4425 | if (ap->state == ANEG_STATE_UNKNOWN) { |
| 4426 | ap->rxconfig = 0; |
| 4427 | ap->link_time = 0; |
| 4428 | ap->cur_time = 0; |
| 4429 | ap->ability_match_cfg = 0; |
| 4430 | ap->ability_match_count = 0; |
| 4431 | ap->ability_match = 0; |
| 4432 | ap->idle_match = 0; |
| 4433 | ap->ack_match = 0; |
| 4434 | } |
| 4435 | ap->cur_time++; |
| 4436 | |
| 4437 | if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { |
| 4438 | rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); |
| 4439 | |
| 4440 | if (rx_cfg_reg != ap->ability_match_cfg) { |
| 4441 | ap->ability_match_cfg = rx_cfg_reg; |
| 4442 | ap->ability_match = 0; |
| 4443 | ap->ability_match_count = 0; |
| 4444 | } else { |
| 4445 | if (++ap->ability_match_count > 1) { |
| 4446 | ap->ability_match = 1; |
| 4447 | ap->ability_match_cfg = rx_cfg_reg; |
| 4448 | } |
| 4449 | } |
| 4450 | if (rx_cfg_reg & ANEG_CFG_ACK) |
| 4451 | ap->ack_match = 1; |
| 4452 | else |
| 4453 | ap->ack_match = 0; |
| 4454 | |
| 4455 | ap->idle_match = 0; |
| 4456 | } else { |
| 4457 | ap->idle_match = 1; |
| 4458 | ap->ability_match_cfg = 0; |
| 4459 | ap->ability_match_count = 0; |
| 4460 | ap->ability_match = 0; |
| 4461 | ap->ack_match = 0; |
| 4462 | |
| 4463 | rx_cfg_reg = 0; |
| 4464 | } |
| 4465 | |
| 4466 | ap->rxconfig = rx_cfg_reg; |
| 4467 | ret = ANEG_OK; |
| 4468 | |
Matt Carlson | 33f401a | 2010-04-05 10:19:27 +0000 | [diff] [blame] | 4469 | switch (ap->state) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4470 | case ANEG_STATE_UNKNOWN: |
| 4471 | if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) |
| 4472 | ap->state = ANEG_STATE_AN_ENABLE; |
| 4473 | |
| 4474 | /* fallthru */ |
| 4475 | case ANEG_STATE_AN_ENABLE: |
| 4476 | ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); |
| 4477 | if (ap->flags & MR_AN_ENABLE) { |
| 4478 | ap->link_time = 0; |
| 4479 | ap->cur_time = 0; |
| 4480 | ap->ability_match_cfg = 0; |
| 4481 | ap->ability_match_count = 0; |
| 4482 | ap->ability_match = 0; |
| 4483 | ap->idle_match = 0; |
| 4484 | ap->ack_match = 0; |
| 4485 | |
| 4486 | ap->state = ANEG_STATE_RESTART_INIT; |
| 4487 | } else { |
| 4488 | ap->state = ANEG_STATE_DISABLE_LINK_OK; |
| 4489 | } |
| 4490 | break; |
| 4491 | |
| 4492 | case ANEG_STATE_RESTART_INIT: |
| 4493 | ap->link_time = ap->cur_time; |
| 4494 | ap->flags &= ~(MR_NP_LOADED); |
| 4495 | ap->txconfig = 0; |
| 4496 | tw32(MAC_TX_AUTO_NEG, 0); |
| 4497 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; |
| 4498 | tw32_f(MAC_MODE, tp->mac_mode); |
| 4499 | udelay(40); |
| 4500 | |
| 4501 | ret = ANEG_TIMER_ENAB; |
| 4502 | ap->state = ANEG_STATE_RESTART; |
| 4503 | |
| 4504 | /* fallthru */ |
| 4505 | case ANEG_STATE_RESTART: |
| 4506 | delta = ap->cur_time - ap->link_time; |
Matt Carlson | 859a58879 | 2010-04-05 10:19:28 +0000 | [diff] [blame] | 4507 | if (delta > ANEG_STATE_SETTLE_TIME) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4508 | ap->state = ANEG_STATE_ABILITY_DETECT_INIT; |
Matt Carlson | 859a58879 | 2010-04-05 10:19:28 +0000 | [diff] [blame] | 4509 | else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4510 | ret = ANEG_TIMER_ENAB; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4511 | break; |
| 4512 | |
| 4513 | case ANEG_STATE_DISABLE_LINK_OK: |
| 4514 | ret = ANEG_DONE; |
| 4515 | break; |
| 4516 | |
| 4517 | case ANEG_STATE_ABILITY_DETECT_INIT: |
| 4518 | ap->flags &= ~(MR_TOGGLE_TX); |
Matt Carlson | 5be73b4 | 2007-12-20 20:09:29 -0800 | [diff] [blame] | 4519 | ap->txconfig = ANEG_CFG_FD; |
| 4520 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
| 4521 | if (flowctrl & ADVERTISE_1000XPAUSE) |
| 4522 | ap->txconfig |= ANEG_CFG_PS1; |
| 4523 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) |
| 4524 | ap->txconfig |= ANEG_CFG_PS2; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4525 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); |
| 4526 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; |
| 4527 | tw32_f(MAC_MODE, tp->mac_mode); |
| 4528 | udelay(40); |
| 4529 | |
| 4530 | ap->state = ANEG_STATE_ABILITY_DETECT; |
| 4531 | break; |
| 4532 | |
| 4533 | case ANEG_STATE_ABILITY_DETECT: |
Matt Carlson | 859a58879 | 2010-04-05 10:19:28 +0000 | [diff] [blame] | 4534 | if (ap->ability_match != 0 && ap->rxconfig != 0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4535 | ap->state = ANEG_STATE_ACK_DETECT_INIT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4536 | break; |
| 4537 | |
| 4538 | case ANEG_STATE_ACK_DETECT_INIT: |
| 4539 | ap->txconfig |= ANEG_CFG_ACK; |
| 4540 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); |
| 4541 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; |
| 4542 | tw32_f(MAC_MODE, tp->mac_mode); |
| 4543 | udelay(40); |
| 4544 | |
| 4545 | ap->state = ANEG_STATE_ACK_DETECT; |
| 4546 | |
| 4547 | /* fallthru */ |
| 4548 | case ANEG_STATE_ACK_DETECT: |
| 4549 | if (ap->ack_match != 0) { |
| 4550 | if ((ap->rxconfig & ~ANEG_CFG_ACK) == |
| 4551 | (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { |
| 4552 | ap->state = ANEG_STATE_COMPLETE_ACK_INIT; |
| 4553 | } else { |
| 4554 | ap->state = ANEG_STATE_AN_ENABLE; |
| 4555 | } |
| 4556 | } else if (ap->ability_match != 0 && |
| 4557 | ap->rxconfig == 0) { |
| 4558 | ap->state = ANEG_STATE_AN_ENABLE; |
| 4559 | } |
| 4560 | break; |
| 4561 | |
| 4562 | case ANEG_STATE_COMPLETE_ACK_INIT: |
| 4563 | if (ap->rxconfig & ANEG_CFG_INVAL) { |
| 4564 | ret = ANEG_FAILED; |
| 4565 | break; |
| 4566 | } |
| 4567 | ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | |
| 4568 | MR_LP_ADV_HALF_DUPLEX | |
| 4569 | MR_LP_ADV_SYM_PAUSE | |
| 4570 | MR_LP_ADV_ASYM_PAUSE | |
| 4571 | MR_LP_ADV_REMOTE_FAULT1 | |
| 4572 | MR_LP_ADV_REMOTE_FAULT2 | |
| 4573 | MR_LP_ADV_NEXT_PAGE | |
| 4574 | MR_TOGGLE_RX | |
| 4575 | MR_NP_RX); |
| 4576 | if (ap->rxconfig & ANEG_CFG_FD) |
| 4577 | ap->flags |= MR_LP_ADV_FULL_DUPLEX; |
| 4578 | if (ap->rxconfig & ANEG_CFG_HD) |
| 4579 | ap->flags |= MR_LP_ADV_HALF_DUPLEX; |
| 4580 | if (ap->rxconfig & ANEG_CFG_PS1) |
| 4581 | ap->flags |= MR_LP_ADV_SYM_PAUSE; |
| 4582 | if (ap->rxconfig & ANEG_CFG_PS2) |
| 4583 | ap->flags |= MR_LP_ADV_ASYM_PAUSE; |
| 4584 | if (ap->rxconfig & ANEG_CFG_RF1) |
| 4585 | ap->flags |= MR_LP_ADV_REMOTE_FAULT1; |
| 4586 | if (ap->rxconfig & ANEG_CFG_RF2) |
| 4587 | ap->flags |= MR_LP_ADV_REMOTE_FAULT2; |
| 4588 | if (ap->rxconfig & ANEG_CFG_NP) |
| 4589 | ap->flags |= MR_LP_ADV_NEXT_PAGE; |
| 4590 | |
| 4591 | ap->link_time = ap->cur_time; |
| 4592 | |
| 4593 | ap->flags ^= (MR_TOGGLE_TX); |
| 4594 | if (ap->rxconfig & 0x0008) |
| 4595 | ap->flags |= MR_TOGGLE_RX; |
| 4596 | if (ap->rxconfig & ANEG_CFG_NP) |
| 4597 | ap->flags |= MR_NP_RX; |
| 4598 | ap->flags |= MR_PAGE_RX; |
| 4599 | |
| 4600 | ap->state = ANEG_STATE_COMPLETE_ACK; |
| 4601 | ret = ANEG_TIMER_ENAB; |
| 4602 | break; |
| 4603 | |
| 4604 | case ANEG_STATE_COMPLETE_ACK: |
| 4605 | if (ap->ability_match != 0 && |
| 4606 | ap->rxconfig == 0) { |
| 4607 | ap->state = ANEG_STATE_AN_ENABLE; |
| 4608 | break; |
| 4609 | } |
| 4610 | delta = ap->cur_time - ap->link_time; |
| 4611 | if (delta > ANEG_STATE_SETTLE_TIME) { |
| 4612 | if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { |
| 4613 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; |
| 4614 | } else { |
| 4615 | if ((ap->txconfig & ANEG_CFG_NP) == 0 && |
| 4616 | !(ap->flags & MR_NP_RX)) { |
| 4617 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; |
| 4618 | } else { |
| 4619 | ret = ANEG_FAILED; |
| 4620 | } |
| 4621 | } |
| 4622 | } |
| 4623 | break; |
| 4624 | |
| 4625 | case ANEG_STATE_IDLE_DETECT_INIT: |
| 4626 | ap->link_time = ap->cur_time; |
| 4627 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; |
| 4628 | tw32_f(MAC_MODE, tp->mac_mode); |
| 4629 | udelay(40); |
| 4630 | |
| 4631 | ap->state = ANEG_STATE_IDLE_DETECT; |
| 4632 | ret = ANEG_TIMER_ENAB; |
| 4633 | break; |
| 4634 | |
| 4635 | case ANEG_STATE_IDLE_DETECT: |
| 4636 | if (ap->ability_match != 0 && |
| 4637 | ap->rxconfig == 0) { |
| 4638 | ap->state = ANEG_STATE_AN_ENABLE; |
| 4639 | break; |
| 4640 | } |
| 4641 | delta = ap->cur_time - ap->link_time; |
| 4642 | if (delta > ANEG_STATE_SETTLE_TIME) { |
| 4643 | /* XXX another gem from the Broadcom driver :( */ |
| 4644 | ap->state = ANEG_STATE_LINK_OK; |
| 4645 | } |
| 4646 | break; |
| 4647 | |
| 4648 | case ANEG_STATE_LINK_OK: |
| 4649 | ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); |
| 4650 | ret = ANEG_DONE; |
| 4651 | break; |
| 4652 | |
| 4653 | case ANEG_STATE_NEXT_PAGE_WAIT_INIT: |
| 4654 | /* ??? unimplemented */ |
| 4655 | break; |
| 4656 | |
| 4657 | case ANEG_STATE_NEXT_PAGE_WAIT: |
| 4658 | /* ??? unimplemented */ |
| 4659 | break; |
| 4660 | |
| 4661 | default: |
| 4662 | ret = ANEG_FAILED; |
| 4663 | break; |
Stephen Hemminger | 855e111 | 2008-04-16 16:37:28 -0700 | [diff] [blame] | 4664 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4665 | |
| 4666 | return ret; |
| 4667 | } |
| 4668 | |
Matt Carlson | 5be73b4 | 2007-12-20 20:09:29 -0800 | [diff] [blame] | 4669 | static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4670 | { |
| 4671 | int res = 0; |
| 4672 | struct tg3_fiber_aneginfo aninfo; |
| 4673 | int status = ANEG_FAILED; |
| 4674 | unsigned int tick; |
| 4675 | u32 tmp; |
| 4676 | |
| 4677 | tw32_f(MAC_TX_AUTO_NEG, 0); |
| 4678 | |
| 4679 | tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; |
| 4680 | tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII); |
| 4681 | udelay(40); |
| 4682 | |
| 4683 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); |
| 4684 | udelay(40); |
| 4685 | |
| 4686 | memset(&aninfo, 0, sizeof(aninfo)); |
| 4687 | aninfo.flags |= MR_AN_ENABLE; |
| 4688 | aninfo.state = ANEG_STATE_UNKNOWN; |
| 4689 | aninfo.cur_time = 0; |
| 4690 | tick = 0; |
| 4691 | while (++tick < 195000) { |
| 4692 | status = tg3_fiber_aneg_smachine(tp, &aninfo); |
| 4693 | if (status == ANEG_DONE || status == ANEG_FAILED) |
| 4694 | break; |
| 4695 | |
| 4696 | udelay(1); |
| 4697 | } |
| 4698 | |
| 4699 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; |
| 4700 | tw32_f(MAC_MODE, tp->mac_mode); |
| 4701 | udelay(40); |
| 4702 | |
Matt Carlson | 5be73b4 | 2007-12-20 20:09:29 -0800 | [diff] [blame] | 4703 | *txflags = aninfo.txconfig; |
| 4704 | *rxflags = aninfo.flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4705 | |
| 4706 | if (status == ANEG_DONE && |
| 4707 | (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK | |
| 4708 | MR_LP_ADV_FULL_DUPLEX))) |
| 4709 | res = 1; |
| 4710 | |
| 4711 | return res; |
| 4712 | } |
| 4713 | |
| 4714 | static void tg3_init_bcm8002(struct tg3 *tp) |
| 4715 | { |
| 4716 | u32 mac_status = tr32(MAC_STATUS); |
| 4717 | int i; |
| 4718 | |
| 4719 | /* Reset when initting first time or we have a link. */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 4720 | if (tg3_flag(tp, INIT_COMPLETE) && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4721 | !(mac_status & MAC_STATUS_PCS_SYNCED)) |
| 4722 | return; |
| 4723 | |
| 4724 | /* Set PLL lock range. */ |
| 4725 | tg3_writephy(tp, 0x16, 0x8007); |
| 4726 | |
| 4727 | /* SW reset */ |
| 4728 | tg3_writephy(tp, MII_BMCR, BMCR_RESET); |
| 4729 | |
| 4730 | /* Wait for reset to complete. */ |
| 4731 | /* XXX schedule_timeout() ... */ |
| 4732 | for (i = 0; i < 500; i++) |
| 4733 | udelay(10); |
| 4734 | |
| 4735 | /* Config mode; select PMA/Ch 1 regs. */ |
| 4736 | tg3_writephy(tp, 0x10, 0x8411); |
| 4737 | |
| 4738 | /* Enable auto-lock and comdet, select txclk for tx. */ |
| 4739 | tg3_writephy(tp, 0x11, 0x0a10); |
| 4740 | |
| 4741 | tg3_writephy(tp, 0x18, 0x00a0); |
| 4742 | tg3_writephy(tp, 0x16, 0x41ff); |
| 4743 | |
| 4744 | /* Assert and deassert POR. */ |
| 4745 | tg3_writephy(tp, 0x13, 0x0400); |
| 4746 | udelay(40); |
| 4747 | tg3_writephy(tp, 0x13, 0x0000); |
| 4748 | |
| 4749 | tg3_writephy(tp, 0x11, 0x0a50); |
| 4750 | udelay(40); |
| 4751 | tg3_writephy(tp, 0x11, 0x0a10); |
| 4752 | |
| 4753 | /* Wait for signal to stabilize */ |
| 4754 | /* XXX schedule_timeout() ... */ |
| 4755 | for (i = 0; i < 15000; i++) |
| 4756 | udelay(10); |
| 4757 | |
| 4758 | /* Deselect the channel register so we can read the PHYID |
| 4759 | * later. |
| 4760 | */ |
| 4761 | tg3_writephy(tp, 0x10, 0x8011); |
| 4762 | } |
| 4763 | |
| 4764 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) |
| 4765 | { |
Matt Carlson | 82cd3d1 | 2007-12-20 20:09:00 -0800 | [diff] [blame] | 4766 | u16 flowctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4767 | u32 sg_dig_ctrl, sg_dig_status; |
| 4768 | u32 serdes_cfg, expected_sg_dig_ctrl; |
| 4769 | int workaround, port_a; |
| 4770 | int current_link_up; |
| 4771 | |
| 4772 | serdes_cfg = 0; |
| 4773 | expected_sg_dig_ctrl = 0; |
| 4774 | workaround = 0; |
| 4775 | port_a = 1; |
| 4776 | current_link_up = 0; |
| 4777 | |
| 4778 | if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 && |
| 4779 | tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) { |
| 4780 | workaround = 1; |
| 4781 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) |
| 4782 | port_a = 0; |
| 4783 | |
| 4784 | /* preserve bits 0-11,13,14 for signal pre-emphasis */ |
| 4785 | /* preserve bits 20-23 for voltage regulator */ |
| 4786 | serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; |
| 4787 | } |
| 4788 | |
| 4789 | sg_dig_ctrl = tr32(SG_DIG_CTRL); |
| 4790 | |
| 4791 | if (tp->link_config.autoneg != AUTONEG_ENABLE) { |
Matt Carlson | c98f6e3 | 2007-12-20 20:08:32 -0800 | [diff] [blame] | 4792 | if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4793 | if (workaround) { |
| 4794 | u32 val = serdes_cfg; |
| 4795 | |
| 4796 | if (port_a) |
| 4797 | val |= 0xc010000; |
| 4798 | else |
| 4799 | val |= 0x4010000; |
| 4800 | tw32_f(MAC_SERDES_CFG, val); |
| 4801 | } |
Matt Carlson | c98f6e3 | 2007-12-20 20:08:32 -0800 | [diff] [blame] | 4802 | |
| 4803 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4804 | } |
| 4805 | if (mac_status & MAC_STATUS_PCS_SYNCED) { |
| 4806 | tg3_setup_flow_control(tp, 0, 0); |
| 4807 | current_link_up = 1; |
| 4808 | } |
| 4809 | goto out; |
| 4810 | } |
| 4811 | |
| 4812 | /* Want auto-negotiation. */ |
Matt Carlson | c98f6e3 | 2007-12-20 20:08:32 -0800 | [diff] [blame] | 4813 | expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4814 | |
Matt Carlson | 82cd3d1 | 2007-12-20 20:09:00 -0800 | [diff] [blame] | 4815 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
| 4816 | if (flowctrl & ADVERTISE_1000XPAUSE) |
| 4817 | expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP; |
| 4818 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) |
| 4819 | expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4820 | |
| 4821 | if (sg_dig_ctrl != expected_sg_dig_ctrl) { |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 4822 | if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && |
Michael Chan | 3d3ebe7 | 2006-09-27 15:59:15 -0700 | [diff] [blame] | 4823 | tp->serdes_counter && |
| 4824 | ((mac_status & (MAC_STATUS_PCS_SYNCED | |
| 4825 | MAC_STATUS_RCVD_CFG)) == |
| 4826 | MAC_STATUS_PCS_SYNCED)) { |
| 4827 | tp->serdes_counter--; |
| 4828 | current_link_up = 1; |
| 4829 | goto out; |
| 4830 | } |
| 4831 | restart_autoneg: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4832 | if (workaround) |
| 4833 | tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000); |
Matt Carlson | c98f6e3 | 2007-12-20 20:08:32 -0800 | [diff] [blame] | 4834 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4835 | udelay(5); |
| 4836 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl); |
| 4837 | |
Michael Chan | 3d3ebe7 | 2006-09-27 15:59:15 -0700 | [diff] [blame] | 4838 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 4839 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4840 | } else if (mac_status & (MAC_STATUS_PCS_SYNCED | |
| 4841 | MAC_STATUS_SIGNAL_DET)) { |
Michael Chan | 3d3ebe7 | 2006-09-27 15:59:15 -0700 | [diff] [blame] | 4842 | sg_dig_status = tr32(SG_DIG_STATUS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4843 | mac_status = tr32(MAC_STATUS); |
| 4844 | |
Matt Carlson | c98f6e3 | 2007-12-20 20:08:32 -0800 | [diff] [blame] | 4845 | if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4846 | (mac_status & MAC_STATUS_PCS_SYNCED)) { |
Matt Carlson | 82cd3d1 | 2007-12-20 20:09:00 -0800 | [diff] [blame] | 4847 | u32 local_adv = 0, remote_adv = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4848 | |
Matt Carlson | 82cd3d1 | 2007-12-20 20:09:00 -0800 | [diff] [blame] | 4849 | if (sg_dig_ctrl & SG_DIG_PAUSE_CAP) |
| 4850 | local_adv |= ADVERTISE_1000XPAUSE; |
| 4851 | if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE) |
| 4852 | local_adv |= ADVERTISE_1000XPSE_ASYM; |
| 4853 | |
Matt Carlson | c98f6e3 | 2007-12-20 20:08:32 -0800 | [diff] [blame] | 4854 | if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE) |
Matt Carlson | 82cd3d1 | 2007-12-20 20:09:00 -0800 | [diff] [blame] | 4855 | remote_adv |= LPA_1000XPAUSE; |
Matt Carlson | c98f6e3 | 2007-12-20 20:08:32 -0800 | [diff] [blame] | 4856 | if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE) |
Matt Carlson | 82cd3d1 | 2007-12-20 20:09:00 -0800 | [diff] [blame] | 4857 | remote_adv |= LPA_1000XPAUSE_ASYM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4858 | |
Matt Carlson | 859edb2 | 2011-12-08 14:40:16 +0000 | [diff] [blame] | 4859 | tp->link_config.rmt_adv = |
| 4860 | mii_adv_to_ethtool_adv_x(remote_adv); |
| 4861 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4862 | tg3_setup_flow_control(tp, local_adv, remote_adv); |
| 4863 | current_link_up = 1; |
Michael Chan | 3d3ebe7 | 2006-09-27 15:59:15 -0700 | [diff] [blame] | 4864 | tp->serdes_counter = 0; |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 4865 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
Matt Carlson | c98f6e3 | 2007-12-20 20:08:32 -0800 | [diff] [blame] | 4866 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { |
Michael Chan | 3d3ebe7 | 2006-09-27 15:59:15 -0700 | [diff] [blame] | 4867 | if (tp->serdes_counter) |
| 4868 | tp->serdes_counter--; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4869 | else { |
| 4870 | if (workaround) { |
| 4871 | u32 val = serdes_cfg; |
| 4872 | |
| 4873 | if (port_a) |
| 4874 | val |= 0xc010000; |
| 4875 | else |
| 4876 | val |= 0x4010000; |
| 4877 | |
| 4878 | tw32_f(MAC_SERDES_CFG, val); |
| 4879 | } |
| 4880 | |
Matt Carlson | c98f6e3 | 2007-12-20 20:08:32 -0800 | [diff] [blame] | 4881 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4882 | udelay(40); |
| 4883 | |
| 4884 | /* Link parallel detection - link is up */ |
| 4885 | /* only if we have PCS_SYNC and not */ |
| 4886 | /* receiving config code words */ |
| 4887 | mac_status = tr32(MAC_STATUS); |
| 4888 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && |
| 4889 | !(mac_status & MAC_STATUS_RCVD_CFG)) { |
| 4890 | tg3_setup_flow_control(tp, 0, 0); |
| 4891 | current_link_up = 1; |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 4892 | tp->phy_flags |= |
| 4893 | TG3_PHYFLG_PARALLEL_DETECT; |
Michael Chan | 3d3ebe7 | 2006-09-27 15:59:15 -0700 | [diff] [blame] | 4894 | tp->serdes_counter = |
| 4895 | SERDES_PARALLEL_DET_TIMEOUT; |
| 4896 | } else |
| 4897 | goto restart_autoneg; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4898 | } |
| 4899 | } |
Michael Chan | 3d3ebe7 | 2006-09-27 15:59:15 -0700 | [diff] [blame] | 4900 | } else { |
| 4901 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 4902 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4903 | } |
| 4904 | |
| 4905 | out: |
| 4906 | return current_link_up; |
| 4907 | } |
| 4908 | |
| 4909 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) |
| 4910 | { |
| 4911 | int current_link_up = 0; |
| 4912 | |
Michael Chan | 5cf64b8a | 2007-05-05 12:11:21 -0700 | [diff] [blame] | 4913 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4914 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4915 | |
| 4916 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { |
Matt Carlson | 5be73b4 | 2007-12-20 20:09:29 -0800 | [diff] [blame] | 4917 | u32 txflags, rxflags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4918 | int i; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 4919 | |
Matt Carlson | 5be73b4 | 2007-12-20 20:09:29 -0800 | [diff] [blame] | 4920 | if (fiber_autoneg(tp, &txflags, &rxflags)) { |
| 4921 | u32 local_adv = 0, remote_adv = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4922 | |
Matt Carlson | 5be73b4 | 2007-12-20 20:09:29 -0800 | [diff] [blame] | 4923 | if (txflags & ANEG_CFG_PS1) |
| 4924 | local_adv |= ADVERTISE_1000XPAUSE; |
| 4925 | if (txflags & ANEG_CFG_PS2) |
| 4926 | local_adv |= ADVERTISE_1000XPSE_ASYM; |
| 4927 | |
| 4928 | if (rxflags & MR_LP_ADV_SYM_PAUSE) |
| 4929 | remote_adv |= LPA_1000XPAUSE; |
| 4930 | if (rxflags & MR_LP_ADV_ASYM_PAUSE) |
| 4931 | remote_adv |= LPA_1000XPAUSE_ASYM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4932 | |
Matt Carlson | 859edb2 | 2011-12-08 14:40:16 +0000 | [diff] [blame] | 4933 | tp->link_config.rmt_adv = |
| 4934 | mii_adv_to_ethtool_adv_x(remote_adv); |
| 4935 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4936 | tg3_setup_flow_control(tp, local_adv, remote_adv); |
| 4937 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4938 | current_link_up = 1; |
| 4939 | } |
| 4940 | for (i = 0; i < 30; i++) { |
| 4941 | udelay(20); |
| 4942 | tw32_f(MAC_STATUS, |
| 4943 | (MAC_STATUS_SYNC_CHANGED | |
| 4944 | MAC_STATUS_CFG_CHANGED)); |
| 4945 | udelay(40); |
| 4946 | if ((tr32(MAC_STATUS) & |
| 4947 | (MAC_STATUS_SYNC_CHANGED | |
| 4948 | MAC_STATUS_CFG_CHANGED)) == 0) |
| 4949 | break; |
| 4950 | } |
| 4951 | |
| 4952 | mac_status = tr32(MAC_STATUS); |
| 4953 | if (current_link_up == 0 && |
| 4954 | (mac_status & MAC_STATUS_PCS_SYNCED) && |
| 4955 | !(mac_status & MAC_STATUS_RCVD_CFG)) |
| 4956 | current_link_up = 1; |
| 4957 | } else { |
Matt Carlson | 5be73b4 | 2007-12-20 20:09:29 -0800 | [diff] [blame] | 4958 | tg3_setup_flow_control(tp, 0, 0); |
| 4959 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4960 | /* Forcing 1000FD link up. */ |
| 4961 | current_link_up = 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4962 | |
| 4963 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); |
| 4964 | udelay(40); |
Matt Carlson | e8f3f6c | 2007-07-11 19:47:55 -0700 | [diff] [blame] | 4965 | |
| 4966 | tw32_f(MAC_MODE, tp->mac_mode); |
| 4967 | udelay(40); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4968 | } |
| 4969 | |
| 4970 | out: |
| 4971 | return current_link_up; |
| 4972 | } |
| 4973 | |
| 4974 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) |
| 4975 | { |
| 4976 | u32 orig_pause_cfg; |
| 4977 | u16 orig_active_speed; |
| 4978 | u8 orig_active_duplex; |
| 4979 | u32 mac_status; |
| 4980 | int current_link_up; |
| 4981 | int i; |
| 4982 | |
Matt Carlson | 8d01862 | 2007-12-20 20:05:44 -0800 | [diff] [blame] | 4983 | orig_pause_cfg = tp->link_config.active_flowctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4984 | orig_active_speed = tp->link_config.active_speed; |
| 4985 | orig_active_duplex = tp->link_config.active_duplex; |
| 4986 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 4987 | if (!tg3_flag(tp, HW_AUTONEG) && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4988 | netif_carrier_ok(tp->dev) && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 4989 | tg3_flag(tp, INIT_COMPLETE)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4990 | mac_status = tr32(MAC_STATUS); |
| 4991 | mac_status &= (MAC_STATUS_PCS_SYNCED | |
| 4992 | MAC_STATUS_SIGNAL_DET | |
| 4993 | MAC_STATUS_CFG_CHANGED | |
| 4994 | MAC_STATUS_RCVD_CFG); |
| 4995 | if (mac_status == (MAC_STATUS_PCS_SYNCED | |
| 4996 | MAC_STATUS_SIGNAL_DET)) { |
| 4997 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | |
| 4998 | MAC_STATUS_CFG_CHANGED)); |
| 4999 | return 0; |
| 5000 | } |
| 5001 | } |
| 5002 | |
| 5003 | tw32_f(MAC_TX_AUTO_NEG, 0); |
| 5004 | |
| 5005 | tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); |
| 5006 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; |
| 5007 | tw32_f(MAC_MODE, tp->mac_mode); |
| 5008 | udelay(40); |
| 5009 | |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 5010 | if (tp->phy_id == TG3_PHY_ID_BCM8002) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5011 | tg3_init_bcm8002(tp); |
| 5012 | |
| 5013 | /* Enable link change event even when serdes polling. */ |
| 5014 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); |
| 5015 | udelay(40); |
| 5016 | |
| 5017 | current_link_up = 0; |
Matt Carlson | 859edb2 | 2011-12-08 14:40:16 +0000 | [diff] [blame] | 5018 | tp->link_config.rmt_adv = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5019 | mac_status = tr32(MAC_STATUS); |
| 5020 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 5021 | if (tg3_flag(tp, HW_AUTONEG)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5022 | current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); |
| 5023 | else |
| 5024 | current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); |
| 5025 | |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 5026 | tp->napi[0].hw_status->status = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5027 | (SD_STATUS_UPDATED | |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 5028 | (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5029 | |
| 5030 | for (i = 0; i < 100; i++) { |
| 5031 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | |
| 5032 | MAC_STATUS_CFG_CHANGED)); |
| 5033 | udelay(5); |
| 5034 | if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | |
Michael Chan | 3d3ebe7 | 2006-09-27 15:59:15 -0700 | [diff] [blame] | 5035 | MAC_STATUS_CFG_CHANGED | |
| 5036 | MAC_STATUS_LNKSTATE_CHANGED)) == 0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5037 | break; |
| 5038 | } |
| 5039 | |
| 5040 | mac_status = tr32(MAC_STATUS); |
| 5041 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { |
| 5042 | current_link_up = 0; |
Michael Chan | 3d3ebe7 | 2006-09-27 15:59:15 -0700 | [diff] [blame] | 5043 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
| 5044 | tp->serdes_counter == 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5045 | tw32_f(MAC_MODE, (tp->mac_mode | |
| 5046 | MAC_MODE_SEND_CONFIGS)); |
| 5047 | udelay(1); |
| 5048 | tw32_f(MAC_MODE, tp->mac_mode); |
| 5049 | } |
| 5050 | } |
| 5051 | |
| 5052 | if (current_link_up == 1) { |
| 5053 | tp->link_config.active_speed = SPEED_1000; |
| 5054 | tp->link_config.active_duplex = DUPLEX_FULL; |
| 5055 | tw32(MAC_LED_CTRL, (tp->led_ctrl | |
| 5056 | LED_CTRL_LNKLED_OVERRIDE | |
| 5057 | LED_CTRL_1000MBPS_ON)); |
| 5058 | } else { |
| 5059 | tp->link_config.active_speed = SPEED_INVALID; |
| 5060 | tp->link_config.active_duplex = DUPLEX_INVALID; |
| 5061 | tw32(MAC_LED_CTRL, (tp->led_ctrl | |
| 5062 | LED_CTRL_LNKLED_OVERRIDE | |
| 5063 | LED_CTRL_TRAFFIC_OVERRIDE)); |
| 5064 | } |
| 5065 | |
| 5066 | if (current_link_up != netif_carrier_ok(tp->dev)) { |
| 5067 | if (current_link_up) |
| 5068 | netif_carrier_on(tp->dev); |
| 5069 | else |
| 5070 | netif_carrier_off(tp->dev); |
| 5071 | tg3_link_report(tp); |
| 5072 | } else { |
Matt Carlson | 8d01862 | 2007-12-20 20:05:44 -0800 | [diff] [blame] | 5073 | u32 now_pause_cfg = tp->link_config.active_flowctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5074 | if (orig_pause_cfg != now_pause_cfg || |
| 5075 | orig_active_speed != tp->link_config.active_speed || |
| 5076 | orig_active_duplex != tp->link_config.active_duplex) |
| 5077 | tg3_link_report(tp); |
| 5078 | } |
| 5079 | |
| 5080 | return 0; |
| 5081 | } |
| 5082 | |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5083 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) |
| 5084 | { |
| 5085 | int current_link_up, err = 0; |
| 5086 | u32 bmsr, bmcr; |
| 5087 | u16 current_speed; |
| 5088 | u8 current_duplex; |
Matt Carlson | ef167e2 | 2007-12-20 20:10:01 -0800 | [diff] [blame] | 5089 | u32 local_adv, remote_adv; |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5090 | |
| 5091 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
| 5092 | tw32_f(MAC_MODE, tp->mac_mode); |
| 5093 | udelay(40); |
| 5094 | |
| 5095 | tw32(MAC_EVENT, 0); |
| 5096 | |
| 5097 | tw32_f(MAC_STATUS, |
| 5098 | (MAC_STATUS_SYNC_CHANGED | |
| 5099 | MAC_STATUS_CFG_CHANGED | |
| 5100 | MAC_STATUS_MI_COMPLETION | |
| 5101 | MAC_STATUS_LNKSTATE_CHANGED)); |
| 5102 | udelay(40); |
| 5103 | |
| 5104 | if (force_reset) |
| 5105 | tg3_phy_reset(tp); |
| 5106 | |
| 5107 | current_link_up = 0; |
| 5108 | current_speed = SPEED_INVALID; |
| 5109 | current_duplex = DUPLEX_INVALID; |
Matt Carlson | 859edb2 | 2011-12-08 14:40:16 +0000 | [diff] [blame] | 5110 | tp->link_config.rmt_adv = 0; |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5111 | |
| 5112 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); |
| 5113 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); |
Michael Chan | d4d2c55 | 2006-03-20 17:47:20 -0800 | [diff] [blame] | 5114 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
| 5115 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) |
| 5116 | bmsr |= BMSR_LSTATUS; |
| 5117 | else |
| 5118 | bmsr &= ~BMSR_LSTATUS; |
| 5119 | } |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5120 | |
| 5121 | err |= tg3_readphy(tp, MII_BMCR, &bmcr); |
| 5122 | |
| 5123 | if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 5124 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5125 | /* do nothing, just check for link up at the end */ |
| 5126 | } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { |
Matt Carlson | 28011cf | 2011-11-16 18:36:59 -0500 | [diff] [blame] | 5127 | u32 adv, newadv; |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5128 | |
| 5129 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); |
Matt Carlson | 28011cf | 2011-11-16 18:36:59 -0500 | [diff] [blame] | 5130 | newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF | |
| 5131 | ADVERTISE_1000XPAUSE | |
| 5132 | ADVERTISE_1000XPSE_ASYM | |
| 5133 | ADVERTISE_SLCT); |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5134 | |
Matt Carlson | 28011cf | 2011-11-16 18:36:59 -0500 | [diff] [blame] | 5135 | newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
Matt Carlson | 37f0702 | 2011-11-17 14:30:55 +0000 | [diff] [blame] | 5136 | newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising); |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5137 | |
Matt Carlson | 28011cf | 2011-11-16 18:36:59 -0500 | [diff] [blame] | 5138 | if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) { |
| 5139 | tg3_writephy(tp, MII_ADVERTISE, newadv); |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5140 | bmcr |= BMCR_ANENABLE | BMCR_ANRESTART; |
| 5141 | tg3_writephy(tp, MII_BMCR, bmcr); |
| 5142 | |
| 5143 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); |
Michael Chan | 3d3ebe7 | 2006-09-27 15:59:15 -0700 | [diff] [blame] | 5144 | tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 5145 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5146 | |
| 5147 | return err; |
| 5148 | } |
| 5149 | } else { |
| 5150 | u32 new_bmcr; |
| 5151 | |
| 5152 | bmcr &= ~BMCR_SPEED1000; |
| 5153 | new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX); |
| 5154 | |
| 5155 | if (tp->link_config.duplex == DUPLEX_FULL) |
| 5156 | new_bmcr |= BMCR_FULLDPLX; |
| 5157 | |
| 5158 | if (new_bmcr != bmcr) { |
| 5159 | /* BMCR_SPEED1000 is a reserved bit that needs |
| 5160 | * to be set on write. |
| 5161 | */ |
| 5162 | new_bmcr |= BMCR_SPEED1000; |
| 5163 | |
| 5164 | /* Force a linkdown */ |
| 5165 | if (netif_carrier_ok(tp->dev)) { |
| 5166 | u32 adv; |
| 5167 | |
| 5168 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); |
| 5169 | adv &= ~(ADVERTISE_1000XFULL | |
| 5170 | ADVERTISE_1000XHALF | |
| 5171 | ADVERTISE_SLCT); |
| 5172 | tg3_writephy(tp, MII_ADVERTISE, adv); |
| 5173 | tg3_writephy(tp, MII_BMCR, bmcr | |
| 5174 | BMCR_ANRESTART | |
| 5175 | BMCR_ANENABLE); |
| 5176 | udelay(10); |
| 5177 | netif_carrier_off(tp->dev); |
| 5178 | } |
| 5179 | tg3_writephy(tp, MII_BMCR, new_bmcr); |
| 5180 | bmcr = new_bmcr; |
| 5181 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); |
| 5182 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); |
Michael Chan | d4d2c55 | 2006-03-20 17:47:20 -0800 | [diff] [blame] | 5183 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
| 5184 | ASIC_REV_5714) { |
| 5185 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) |
| 5186 | bmsr |= BMSR_LSTATUS; |
| 5187 | else |
| 5188 | bmsr &= ~BMSR_LSTATUS; |
| 5189 | } |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 5190 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5191 | } |
| 5192 | } |
| 5193 | |
| 5194 | if (bmsr & BMSR_LSTATUS) { |
| 5195 | current_speed = SPEED_1000; |
| 5196 | current_link_up = 1; |
| 5197 | if (bmcr & BMCR_FULLDPLX) |
| 5198 | current_duplex = DUPLEX_FULL; |
| 5199 | else |
| 5200 | current_duplex = DUPLEX_HALF; |
| 5201 | |
Matt Carlson | ef167e2 | 2007-12-20 20:10:01 -0800 | [diff] [blame] | 5202 | local_adv = 0; |
| 5203 | remote_adv = 0; |
| 5204 | |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5205 | if (bmcr & BMCR_ANENABLE) { |
Matt Carlson | ef167e2 | 2007-12-20 20:10:01 -0800 | [diff] [blame] | 5206 | u32 common; |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5207 | |
| 5208 | err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); |
| 5209 | err |= tg3_readphy(tp, MII_LPA, &remote_adv); |
| 5210 | common = local_adv & remote_adv; |
| 5211 | if (common & (ADVERTISE_1000XHALF | |
| 5212 | ADVERTISE_1000XFULL)) { |
| 5213 | if (common & ADVERTISE_1000XFULL) |
| 5214 | current_duplex = DUPLEX_FULL; |
| 5215 | else |
| 5216 | current_duplex = DUPLEX_HALF; |
Matt Carlson | 859edb2 | 2011-12-08 14:40:16 +0000 | [diff] [blame] | 5217 | |
| 5218 | tp->link_config.rmt_adv = |
| 5219 | mii_adv_to_ethtool_adv_x(remote_adv); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 5220 | } else if (!tg3_flag(tp, 5780_CLASS)) { |
Matt Carlson | 57d8b88 | 2010-06-05 17:24:35 +0000 | [diff] [blame] | 5221 | /* Link is up via parallel detect */ |
Matt Carlson | 859a58879 | 2010-04-05 10:19:28 +0000 | [diff] [blame] | 5222 | } else { |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5223 | current_link_up = 0; |
Matt Carlson | 859a58879 | 2010-04-05 10:19:28 +0000 | [diff] [blame] | 5224 | } |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5225 | } |
| 5226 | } |
| 5227 | |
Matt Carlson | ef167e2 | 2007-12-20 20:10:01 -0800 | [diff] [blame] | 5228 | if (current_link_up == 1 && current_duplex == DUPLEX_FULL) |
| 5229 | tg3_setup_flow_control(tp, local_adv, remote_adv); |
| 5230 | |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5231 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; |
| 5232 | if (tp->link_config.active_duplex == DUPLEX_HALF) |
| 5233 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; |
| 5234 | |
| 5235 | tw32_f(MAC_MODE, tp->mac_mode); |
| 5236 | udelay(40); |
| 5237 | |
| 5238 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); |
| 5239 | |
| 5240 | tp->link_config.active_speed = current_speed; |
| 5241 | tp->link_config.active_duplex = current_duplex; |
| 5242 | |
| 5243 | if (current_link_up != netif_carrier_ok(tp->dev)) { |
| 5244 | if (current_link_up) |
| 5245 | netif_carrier_on(tp->dev); |
| 5246 | else { |
| 5247 | netif_carrier_off(tp->dev); |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 5248 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5249 | } |
| 5250 | tg3_link_report(tp); |
| 5251 | } |
| 5252 | return err; |
| 5253 | } |
| 5254 | |
| 5255 | static void tg3_serdes_parallel_detect(struct tg3 *tp) |
| 5256 | { |
Michael Chan | 3d3ebe7 | 2006-09-27 15:59:15 -0700 | [diff] [blame] | 5257 | if (tp->serdes_counter) { |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5258 | /* Give autoneg time to complete. */ |
Michael Chan | 3d3ebe7 | 2006-09-27 15:59:15 -0700 | [diff] [blame] | 5259 | tp->serdes_counter--; |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5260 | return; |
| 5261 | } |
Matt Carlson | c6cdf43 | 2010-04-05 10:19:26 +0000 | [diff] [blame] | 5262 | |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5263 | if (!netif_carrier_ok(tp->dev) && |
| 5264 | (tp->link_config.autoneg == AUTONEG_ENABLE)) { |
| 5265 | u32 bmcr; |
| 5266 | |
| 5267 | tg3_readphy(tp, MII_BMCR, &bmcr); |
| 5268 | if (bmcr & BMCR_ANENABLE) { |
| 5269 | u32 phy1, phy2; |
| 5270 | |
| 5271 | /* Select shadow register 0x1f */ |
Matt Carlson | f08aa1a | 2010-08-02 11:26:05 +0000 | [diff] [blame] | 5272 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); |
| 5273 | tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5274 | |
| 5275 | /* Select expansion interrupt status register */ |
Matt Carlson | f08aa1a | 2010-08-02 11:26:05 +0000 | [diff] [blame] | 5276 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
| 5277 | MII_TG3_DSP_EXP1_INT_STAT); |
| 5278 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); |
| 5279 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5280 | |
| 5281 | if ((phy1 & 0x10) && !(phy2 & 0x20)) { |
| 5282 | /* We have signal detect and not receiving |
| 5283 | * config code words, link is up by parallel |
| 5284 | * detection. |
| 5285 | */ |
| 5286 | |
| 5287 | bmcr &= ~BMCR_ANENABLE; |
| 5288 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; |
| 5289 | tg3_writephy(tp, MII_BMCR, bmcr); |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 5290 | tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5291 | } |
| 5292 | } |
Matt Carlson | 859a58879 | 2010-04-05 10:19:28 +0000 | [diff] [blame] | 5293 | } else if (netif_carrier_ok(tp->dev) && |
| 5294 | (tp->link_config.autoneg == AUTONEG_ENABLE) && |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 5295 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5296 | u32 phy2; |
| 5297 | |
| 5298 | /* Select expansion interrupt status register */ |
Matt Carlson | f08aa1a | 2010-08-02 11:26:05 +0000 | [diff] [blame] | 5299 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, |
| 5300 | MII_TG3_DSP_EXP1_INT_STAT); |
| 5301 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5302 | if (phy2 & 0x20) { |
| 5303 | u32 bmcr; |
| 5304 | |
| 5305 | /* Config code words received, turn on autoneg. */ |
| 5306 | tg3_readphy(tp, MII_BMCR, &bmcr); |
| 5307 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); |
| 5308 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 5309 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5310 | |
| 5311 | } |
| 5312 | } |
| 5313 | } |
| 5314 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5315 | static int tg3_setup_phy(struct tg3 *tp, int force_reset) |
| 5316 | { |
Matt Carlson | f2096f9 | 2011-04-05 14:22:48 +0000 | [diff] [blame] | 5317 | u32 val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5318 | int err; |
| 5319 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 5320 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5321 | err = tg3_setup_fiber_phy(tp, force_reset); |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 5322 | else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 5323 | err = tg3_setup_fiber_mii_phy(tp, force_reset); |
Matt Carlson | 859a58879 | 2010-04-05 10:19:28 +0000 | [diff] [blame] | 5324 | else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5325 | err = tg3_setup_copper_phy(tp, force_reset); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5326 | |
Matt Carlson | bcb37f6 | 2008-11-03 16:52:09 -0800 | [diff] [blame] | 5327 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
Matt Carlson | f2096f9 | 2011-04-05 14:22:48 +0000 | [diff] [blame] | 5328 | u32 scale; |
Matt Carlson | aa6c91f | 2007-11-12 21:18:04 -0800 | [diff] [blame] | 5329 | |
| 5330 | val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; |
| 5331 | if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5) |
| 5332 | scale = 65; |
| 5333 | else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25) |
| 5334 | scale = 6; |
| 5335 | else |
| 5336 | scale = 12; |
| 5337 | |
| 5338 | val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; |
| 5339 | val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT); |
| 5340 | tw32(GRC_MISC_CFG, val); |
| 5341 | } |
| 5342 | |
Matt Carlson | f2096f9 | 2011-04-05 14:22:48 +0000 | [diff] [blame] | 5343 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
| 5344 | (6 << TX_LENGTHS_IPG_SHIFT); |
| 5345 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
| 5346 | val |= tr32(MAC_TX_LENGTHS) & |
| 5347 | (TX_LENGTHS_JMB_FRM_LEN_MSK | |
| 5348 | TX_LENGTHS_CNT_DWN_VAL_MSK); |
| 5349 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5350 | if (tp->link_config.active_speed == SPEED_1000 && |
| 5351 | tp->link_config.active_duplex == DUPLEX_HALF) |
Matt Carlson | f2096f9 | 2011-04-05 14:22:48 +0000 | [diff] [blame] | 5352 | tw32(MAC_TX_LENGTHS, val | |
| 5353 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5354 | else |
Matt Carlson | f2096f9 | 2011-04-05 14:22:48 +0000 | [diff] [blame] | 5355 | tw32(MAC_TX_LENGTHS, val | |
| 5356 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5357 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 5358 | if (!tg3_flag(tp, 5705_PLUS)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5359 | if (netif_carrier_ok(tp->dev)) { |
| 5360 | tw32(HOSTCC_STAT_COAL_TICKS, |
David S. Miller | 15f9850 | 2005-05-18 22:49:26 -0700 | [diff] [blame] | 5361 | tp->coal.stats_block_coalesce_usecs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5362 | } else { |
| 5363 | tw32(HOSTCC_STAT_COAL_TICKS, 0); |
| 5364 | } |
| 5365 | } |
| 5366 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 5367 | if (tg3_flag(tp, ASPM_WORKAROUND)) { |
Matt Carlson | f2096f9 | 2011-04-05 14:22:48 +0000 | [diff] [blame] | 5368 | val = tr32(PCIE_PWR_MGMT_THRESH); |
Matt Carlson | 8ed5d97 | 2007-05-07 00:25:49 -0700 | [diff] [blame] | 5369 | if (!netif_carrier_ok(tp->dev)) |
| 5370 | val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | |
| 5371 | tp->pwrmgmt_thresh; |
| 5372 | else |
| 5373 | val |= PCIE_PWR_MGMT_L1_THRESH_MSK; |
| 5374 | tw32(PCIE_PWR_MGMT_THRESH, val); |
| 5375 | } |
| 5376 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5377 | return err; |
| 5378 | } |
| 5379 | |
Matt Carlson | 66cfd1b | 2010-09-30 10:34:30 +0000 | [diff] [blame] | 5380 | static inline int tg3_irq_sync(struct tg3 *tp) |
| 5381 | { |
| 5382 | return tp->irq_sync; |
| 5383 | } |
| 5384 | |
Matt Carlson | 97bd8e4 | 2011-04-13 11:05:04 +0000 | [diff] [blame] | 5385 | static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len) |
| 5386 | { |
| 5387 | int i; |
| 5388 | |
| 5389 | dst = (u32 *)((u8 *)dst + off); |
| 5390 | for (i = 0; i < len; i += sizeof(u32)) |
| 5391 | *dst++ = tr32(off + i); |
| 5392 | } |
| 5393 | |
| 5394 | static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs) |
| 5395 | { |
| 5396 | tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0); |
| 5397 | tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200); |
| 5398 | tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0); |
| 5399 | tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0); |
| 5400 | tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04); |
| 5401 | tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80); |
| 5402 | tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48); |
| 5403 | tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04); |
| 5404 | tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20); |
| 5405 | tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c); |
| 5406 | tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c); |
| 5407 | tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c); |
| 5408 | tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44); |
| 5409 | tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04); |
| 5410 | tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20); |
| 5411 | tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14); |
| 5412 | tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08); |
| 5413 | tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08); |
| 5414 | tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100); |
| 5415 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 5416 | if (tg3_flag(tp, SUPPORT_MSIX)) |
Matt Carlson | 97bd8e4 | 2011-04-13 11:05:04 +0000 | [diff] [blame] | 5417 | tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180); |
| 5418 | |
| 5419 | tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10); |
| 5420 | tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58); |
| 5421 | tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08); |
| 5422 | tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08); |
| 5423 | tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04); |
| 5424 | tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04); |
| 5425 | tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04); |
| 5426 | tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04); |
| 5427 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 5428 | if (!tg3_flag(tp, 5705_PLUS)) { |
Matt Carlson | 97bd8e4 | 2011-04-13 11:05:04 +0000 | [diff] [blame] | 5429 | tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04); |
| 5430 | tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04); |
| 5431 | tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04); |
| 5432 | } |
| 5433 | |
| 5434 | tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110); |
| 5435 | tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120); |
| 5436 | tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c); |
| 5437 | tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04); |
| 5438 | tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c); |
| 5439 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 5440 | if (tg3_flag(tp, NVRAM)) |
Matt Carlson | 97bd8e4 | 2011-04-13 11:05:04 +0000 | [diff] [blame] | 5441 | tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24); |
| 5442 | } |
| 5443 | |
| 5444 | static void tg3_dump_state(struct tg3 *tp) |
| 5445 | { |
| 5446 | int i; |
| 5447 | u32 *regs; |
| 5448 | |
| 5449 | regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC); |
| 5450 | if (!regs) { |
| 5451 | netdev_err(tp->dev, "Failed allocating register dump buffer\n"); |
| 5452 | return; |
| 5453 | } |
| 5454 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 5455 | if (tg3_flag(tp, PCI_EXPRESS)) { |
Matt Carlson | 97bd8e4 | 2011-04-13 11:05:04 +0000 | [diff] [blame] | 5456 | /* Read up to but not including private PCI registers */ |
| 5457 | for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32)) |
| 5458 | regs[i / sizeof(u32)] = tr32(i); |
| 5459 | } else |
| 5460 | tg3_dump_legacy_regs(tp, regs); |
| 5461 | |
| 5462 | for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) { |
| 5463 | if (!regs[i + 0] && !regs[i + 1] && |
| 5464 | !regs[i + 2] && !regs[i + 3]) |
| 5465 | continue; |
| 5466 | |
| 5467 | netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", |
| 5468 | i * 4, |
| 5469 | regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]); |
| 5470 | } |
| 5471 | |
| 5472 | kfree(regs); |
| 5473 | |
| 5474 | for (i = 0; i < tp->irq_cnt; i++) { |
| 5475 | struct tg3_napi *tnapi = &tp->napi[i]; |
| 5476 | |
| 5477 | /* SW status block */ |
| 5478 | netdev_err(tp->dev, |
| 5479 | "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n", |
| 5480 | i, |
| 5481 | tnapi->hw_status->status, |
| 5482 | tnapi->hw_status->status_tag, |
| 5483 | tnapi->hw_status->rx_jumbo_consumer, |
| 5484 | tnapi->hw_status->rx_consumer, |
| 5485 | tnapi->hw_status->rx_mini_consumer, |
| 5486 | tnapi->hw_status->idx[0].rx_producer, |
| 5487 | tnapi->hw_status->idx[0].tx_consumer); |
| 5488 | |
| 5489 | netdev_err(tp->dev, |
| 5490 | "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n", |
| 5491 | i, |
| 5492 | tnapi->last_tag, tnapi->last_irq_tag, |
| 5493 | tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending, |
| 5494 | tnapi->rx_rcb_ptr, |
| 5495 | tnapi->prodring.rx_std_prod_idx, |
| 5496 | tnapi->prodring.rx_std_cons_idx, |
| 5497 | tnapi->prodring.rx_jmb_prod_idx, |
| 5498 | tnapi->prodring.rx_jmb_cons_idx); |
| 5499 | } |
| 5500 | } |
| 5501 | |
Michael Chan | df3e654 | 2006-05-26 17:48:07 -0700 | [diff] [blame] | 5502 | /* This is called whenever we suspect that the system chipset is re- |
| 5503 | * ordering the sequence of MMIO to the tx send mailbox. The symptom |
| 5504 | * is bogus tx completions. We try to recover by setting the |
| 5505 | * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later |
| 5506 | * in the workqueue. |
| 5507 | */ |
| 5508 | static void tg3_tx_recover(struct tg3 *tp) |
| 5509 | { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 5510 | BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) || |
Michael Chan | df3e654 | 2006-05-26 17:48:07 -0700 | [diff] [blame] | 5511 | tp->write32_tx_mbox == tg3_write_indirect_mbox); |
| 5512 | |
Matt Carlson | 5129c3a | 2010-04-05 10:19:23 +0000 | [diff] [blame] | 5513 | netdev_warn(tp->dev, |
| 5514 | "The system may be re-ordering memory-mapped I/O " |
| 5515 | "cycles to the network device, attempting to recover. " |
| 5516 | "Please report the problem to the driver maintainer " |
| 5517 | "and include system chipset information.\n"); |
Michael Chan | df3e654 | 2006-05-26 17:48:07 -0700 | [diff] [blame] | 5518 | |
| 5519 | spin_lock(&tp->lock); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 5520 | tg3_flag_set(tp, TX_RECOVERY_PENDING); |
Michael Chan | df3e654 | 2006-05-26 17:48:07 -0700 | [diff] [blame] | 5521 | spin_unlock(&tp->lock); |
| 5522 | } |
| 5523 | |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 5524 | static inline u32 tg3_tx_avail(struct tg3_napi *tnapi) |
Michael Chan | 1b2a720 | 2006-08-07 21:46:02 -0700 | [diff] [blame] | 5525 | { |
Matt Carlson | f65aac1 | 2010-08-02 11:26:03 +0000 | [diff] [blame] | 5526 | /* Tell compiler to fetch tx indices from memory. */ |
| 5527 | barrier(); |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 5528 | return tnapi->tx_pending - |
| 5529 | ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); |
Michael Chan | 1b2a720 | 2006-08-07 21:46:02 -0700 | [diff] [blame] | 5530 | } |
| 5531 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5532 | /* Tigon3 never reports partial packet sends. So we do not |
| 5533 | * need special logic to handle SKBs that have not had all |
| 5534 | * of their frags sent yet, like SunGEM does. |
| 5535 | */ |
Matt Carlson | 17375d2 | 2009-08-28 14:02:18 +0000 | [diff] [blame] | 5536 | static void tg3_tx(struct tg3_napi *tnapi) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5537 | { |
Matt Carlson | 17375d2 | 2009-08-28 14:02:18 +0000 | [diff] [blame] | 5538 | struct tg3 *tp = tnapi->tp; |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 5539 | u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 5540 | u32 sw_idx = tnapi->tx_cons; |
Matt Carlson | fe5f578 | 2009-09-01 13:09:39 +0000 | [diff] [blame] | 5541 | struct netdev_queue *txq; |
| 5542 | int index = tnapi - tp->napi; |
Tom Herbert | 298376d | 2011-11-28 16:33:30 +0000 | [diff] [blame] | 5543 | unsigned int pkts_compl = 0, bytes_compl = 0; |
Matt Carlson | fe5f578 | 2009-09-01 13:09:39 +0000 | [diff] [blame] | 5544 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 5545 | if (tg3_flag(tp, ENABLE_TSS)) |
Matt Carlson | fe5f578 | 2009-09-01 13:09:39 +0000 | [diff] [blame] | 5546 | index--; |
| 5547 | |
| 5548 | txq = netdev_get_tx_queue(tp->dev, index); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5549 | |
| 5550 | while (sw_idx != hw_idx) { |
Matt Carlson | df8944c | 2011-07-27 14:20:46 +0000 | [diff] [blame] | 5551 | struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5552 | struct sk_buff *skb = ri->skb; |
Michael Chan | df3e654 | 2006-05-26 17:48:07 -0700 | [diff] [blame] | 5553 | int i, tx_bug = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5554 | |
Michael Chan | df3e654 | 2006-05-26 17:48:07 -0700 | [diff] [blame] | 5555 | if (unlikely(skb == NULL)) { |
| 5556 | tg3_tx_recover(tp); |
| 5557 | return; |
| 5558 | } |
| 5559 | |
Alexander Duyck | f4188d8 | 2009-12-02 16:48:38 +0000 | [diff] [blame] | 5560 | pci_unmap_single(tp->pdev, |
FUJITA Tomonori | 4e5e4f0 | 2010-04-12 14:32:09 +0000 | [diff] [blame] | 5561 | dma_unmap_addr(ri, mapping), |
Alexander Duyck | f4188d8 | 2009-12-02 16:48:38 +0000 | [diff] [blame] | 5562 | skb_headlen(skb), |
| 5563 | PCI_DMA_TODEVICE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5564 | |
| 5565 | ri->skb = NULL; |
| 5566 | |
Matt Carlson | e01ee14 | 2011-07-27 14:20:50 +0000 | [diff] [blame] | 5567 | while (ri->fragmented) { |
| 5568 | ri->fragmented = false; |
| 5569 | sw_idx = NEXT_TX(sw_idx); |
| 5570 | ri = &tnapi->tx_buffers[sw_idx]; |
| 5571 | } |
| 5572 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5573 | sw_idx = NEXT_TX(sw_idx); |
| 5574 | |
| 5575 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 5576 | ri = &tnapi->tx_buffers[sw_idx]; |
Michael Chan | df3e654 | 2006-05-26 17:48:07 -0700 | [diff] [blame] | 5577 | if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) |
| 5578 | tx_bug = 1; |
Alexander Duyck | f4188d8 | 2009-12-02 16:48:38 +0000 | [diff] [blame] | 5579 | |
| 5580 | pci_unmap_page(tp->pdev, |
FUJITA Tomonori | 4e5e4f0 | 2010-04-12 14:32:09 +0000 | [diff] [blame] | 5581 | dma_unmap_addr(ri, mapping), |
Eric Dumazet | 9e903e0 | 2011-10-18 21:00:24 +0000 | [diff] [blame] | 5582 | skb_frag_size(&skb_shinfo(skb)->frags[i]), |
Alexander Duyck | f4188d8 | 2009-12-02 16:48:38 +0000 | [diff] [blame] | 5583 | PCI_DMA_TODEVICE); |
Matt Carlson | e01ee14 | 2011-07-27 14:20:50 +0000 | [diff] [blame] | 5584 | |
| 5585 | while (ri->fragmented) { |
| 5586 | ri->fragmented = false; |
| 5587 | sw_idx = NEXT_TX(sw_idx); |
| 5588 | ri = &tnapi->tx_buffers[sw_idx]; |
| 5589 | } |
| 5590 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5591 | sw_idx = NEXT_TX(sw_idx); |
| 5592 | } |
| 5593 | |
Tom Herbert | 298376d | 2011-11-28 16:33:30 +0000 | [diff] [blame] | 5594 | pkts_compl++; |
| 5595 | bytes_compl += skb->len; |
| 5596 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 5597 | dev_kfree_skb(skb); |
Michael Chan | df3e654 | 2006-05-26 17:48:07 -0700 | [diff] [blame] | 5598 | |
| 5599 | if (unlikely(tx_bug)) { |
| 5600 | tg3_tx_recover(tp); |
| 5601 | return; |
| 5602 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5603 | } |
| 5604 | |
Tom Herbert | 298376d | 2011-11-28 16:33:30 +0000 | [diff] [blame] | 5605 | netdev_completed_queue(tp->dev, pkts_compl, bytes_compl); |
| 5606 | |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 5607 | tnapi->tx_cons = sw_idx; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5608 | |
Michael Chan | 1b2a720 | 2006-08-07 21:46:02 -0700 | [diff] [blame] | 5609 | /* Need to make the tx_cons update visible to tg3_start_xmit() |
| 5610 | * before checking for netif_queue_stopped(). Without the |
| 5611 | * memory barrier, there is a small possibility that tg3_start_xmit() |
| 5612 | * will miss it and cause the queue to be stopped forever. |
| 5613 | */ |
| 5614 | smp_mb(); |
| 5615 | |
Matt Carlson | fe5f578 | 2009-09-01 13:09:39 +0000 | [diff] [blame] | 5616 | if (unlikely(netif_tx_queue_stopped(txq) && |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 5617 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) { |
Matt Carlson | fe5f578 | 2009-09-01 13:09:39 +0000 | [diff] [blame] | 5618 | __netif_tx_lock(txq, smp_processor_id()); |
| 5619 | if (netif_tx_queue_stopped(txq) && |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 5620 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))) |
Matt Carlson | fe5f578 | 2009-09-01 13:09:39 +0000 | [diff] [blame] | 5621 | netif_tx_wake_queue(txq); |
| 5622 | __netif_tx_unlock(txq); |
Michael Chan | 51b9146 | 2005-09-01 17:41:28 -0700 | [diff] [blame] | 5623 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5624 | } |
| 5625 | |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5626 | static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) |
Matt Carlson | 2b2cdb6 | 2009-11-13 13:03:48 +0000 | [diff] [blame] | 5627 | { |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5628 | if (!ri->data) |
Matt Carlson | 2b2cdb6 | 2009-11-13 13:03:48 +0000 | [diff] [blame] | 5629 | return; |
| 5630 | |
FUJITA Tomonori | 4e5e4f0 | 2010-04-12 14:32:09 +0000 | [diff] [blame] | 5631 | pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping), |
Matt Carlson | 2b2cdb6 | 2009-11-13 13:03:48 +0000 | [diff] [blame] | 5632 | map_sz, PCI_DMA_FROMDEVICE); |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5633 | kfree(ri->data); |
| 5634 | ri->data = NULL; |
Matt Carlson | 2b2cdb6 | 2009-11-13 13:03:48 +0000 | [diff] [blame] | 5635 | } |
| 5636 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5637 | /* Returns size of skb allocated or < 0 on error. |
| 5638 | * |
| 5639 | * We only need to fill in the address because the other members |
| 5640 | * of the RX descriptor are invariant, see tg3_init_rings. |
| 5641 | * |
| 5642 | * Note the purposeful assymetry of cpu vs. chip accesses. For |
| 5643 | * posting buffers we only dirty the first cache line of the RX |
| 5644 | * descriptor (containing the address). Whereas for the RX status |
| 5645 | * buffers the cpu only reads the last cacheline of the RX descriptor |
| 5646 | * (to fetch the error flags, vlan tag, checksum, and opaque cookie). |
| 5647 | */ |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5648 | static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, |
Matt Carlson | a389616 | 2009-11-13 13:03:44 +0000 | [diff] [blame] | 5649 | u32 opaque_key, u32 dest_idx_unmasked) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5650 | { |
| 5651 | struct tg3_rx_buffer_desc *desc; |
Matt Carlson | f94e290 | 2010-10-14 10:37:42 +0000 | [diff] [blame] | 5652 | struct ring_info *map; |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5653 | u8 *data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5654 | dma_addr_t mapping; |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5655 | int skb_size, data_size, dest_idx; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5656 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5657 | switch (opaque_key) { |
| 5658 | case RXD_OPAQUE_RING_STD: |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 5659 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 5660 | desc = &tpr->rx_std[dest_idx]; |
| 5661 | map = &tpr->rx_std_buffers[dest_idx]; |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5662 | data_size = tp->rx_pkt_map_sz; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5663 | break; |
| 5664 | |
| 5665 | case RXD_OPAQUE_RING_JUMBO: |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 5666 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
Matt Carlson | 79ed5ac | 2009-08-28 14:00:55 +0000 | [diff] [blame] | 5667 | desc = &tpr->rx_jmb[dest_idx].std; |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 5668 | map = &tpr->rx_jmb_buffers[dest_idx]; |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5669 | data_size = TG3_RX_JMB_MAP_SZ; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5670 | break; |
| 5671 | |
| 5672 | default: |
| 5673 | return -EINVAL; |
Stephen Hemminger | 855e111 | 2008-04-16 16:37:28 -0700 | [diff] [blame] | 5674 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5675 | |
| 5676 | /* Do not overwrite any of the map or rp information |
| 5677 | * until we are sure we can commit to a new buffer. |
| 5678 | * |
| 5679 | * Callers depend upon this behavior and assume that |
| 5680 | * we leave everything unchanged if we fail. |
| 5681 | */ |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5682 | skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) + |
| 5683 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); |
| 5684 | data = kmalloc(skb_size, GFP_ATOMIC); |
| 5685 | if (!data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5686 | return -ENOMEM; |
| 5687 | |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5688 | mapping = pci_map_single(tp->pdev, |
| 5689 | data + TG3_RX_OFFSET(tp), |
| 5690 | data_size, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5691 | PCI_DMA_FROMDEVICE); |
Matt Carlson | a21771d | 2009-11-02 14:25:31 +0000 | [diff] [blame] | 5692 | if (pci_dma_mapping_error(tp->pdev, mapping)) { |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5693 | kfree(data); |
Matt Carlson | a21771d | 2009-11-02 14:25:31 +0000 | [diff] [blame] | 5694 | return -EIO; |
| 5695 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5696 | |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5697 | map->data = data; |
FUJITA Tomonori | 4e5e4f0 | 2010-04-12 14:32:09 +0000 | [diff] [blame] | 5698 | dma_unmap_addr_set(map, mapping, mapping); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5699 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5700 | desc->addr_hi = ((u64)mapping >> 32); |
| 5701 | desc->addr_lo = ((u64)mapping & 0xffffffff); |
| 5702 | |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5703 | return data_size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5704 | } |
| 5705 | |
| 5706 | /* We only need to move over in the address because the other |
| 5707 | * members of the RX descriptor are invariant. See notes above |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5708 | * tg3_alloc_rx_data for full details. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5709 | */ |
Matt Carlson | a389616 | 2009-11-13 13:03:44 +0000 | [diff] [blame] | 5710 | static void tg3_recycle_rx(struct tg3_napi *tnapi, |
| 5711 | struct tg3_rx_prodring_set *dpr, |
| 5712 | u32 opaque_key, int src_idx, |
| 5713 | u32 dest_idx_unmasked) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5714 | { |
Matt Carlson | 17375d2 | 2009-08-28 14:02:18 +0000 | [diff] [blame] | 5715 | struct tg3 *tp = tnapi->tp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5716 | struct tg3_rx_buffer_desc *src_desc, *dest_desc; |
| 5717 | struct ring_info *src_map, *dest_map; |
Matt Carlson | 8fea32b | 2010-09-15 08:59:58 +0000 | [diff] [blame] | 5718 | struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; |
Matt Carlson | c6cdf43 | 2010-04-05 10:19:26 +0000 | [diff] [blame] | 5719 | int dest_idx; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5720 | |
| 5721 | switch (opaque_key) { |
| 5722 | case RXD_OPAQUE_RING_STD: |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 5723 | dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; |
Matt Carlson | a389616 | 2009-11-13 13:03:44 +0000 | [diff] [blame] | 5724 | dest_desc = &dpr->rx_std[dest_idx]; |
| 5725 | dest_map = &dpr->rx_std_buffers[dest_idx]; |
| 5726 | src_desc = &spr->rx_std[src_idx]; |
| 5727 | src_map = &spr->rx_std_buffers[src_idx]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5728 | break; |
| 5729 | |
| 5730 | case RXD_OPAQUE_RING_JUMBO: |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 5731 | dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; |
Matt Carlson | a389616 | 2009-11-13 13:03:44 +0000 | [diff] [blame] | 5732 | dest_desc = &dpr->rx_jmb[dest_idx].std; |
| 5733 | dest_map = &dpr->rx_jmb_buffers[dest_idx]; |
| 5734 | src_desc = &spr->rx_jmb[src_idx].std; |
| 5735 | src_map = &spr->rx_jmb_buffers[src_idx]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5736 | break; |
| 5737 | |
| 5738 | default: |
| 5739 | return; |
Stephen Hemminger | 855e111 | 2008-04-16 16:37:28 -0700 | [diff] [blame] | 5740 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5741 | |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5742 | dest_map->data = src_map->data; |
FUJITA Tomonori | 4e5e4f0 | 2010-04-12 14:32:09 +0000 | [diff] [blame] | 5743 | dma_unmap_addr_set(dest_map, mapping, |
| 5744 | dma_unmap_addr(src_map, mapping)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5745 | dest_desc->addr_hi = src_desc->addr_hi; |
| 5746 | dest_desc->addr_lo = src_desc->addr_lo; |
Matt Carlson | e92967b | 2010-02-12 14:47:06 +0000 | [diff] [blame] | 5747 | |
| 5748 | /* Ensure that the update to the skb happens after the physical |
| 5749 | * addresses have been transferred to the new BD location. |
| 5750 | */ |
| 5751 | smp_wmb(); |
| 5752 | |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5753 | src_map->data = NULL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5754 | } |
| 5755 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5756 | /* The RX ring scheme is composed of multiple rings which post fresh |
| 5757 | * buffers to the chip, and one special ring the chip uses to report |
| 5758 | * status back to the host. |
| 5759 | * |
| 5760 | * The special ring reports the status of received packets to the |
| 5761 | * host. The chip does not write into the original descriptor the |
| 5762 | * RX buffer was obtained from. The chip simply takes the original |
| 5763 | * descriptor as provided by the host, updates the status and length |
| 5764 | * field, then writes this into the next status ring entry. |
| 5765 | * |
| 5766 | * Each ring the host uses to post buffers to the chip is described |
| 5767 | * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives, |
| 5768 | * it is first placed into the on-chip ram. When the packet's length |
| 5769 | * is known, it walks down the TG3_BDINFO entries to select the ring. |
| 5770 | * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO |
| 5771 | * which is within the range of the new packet's length is chosen. |
| 5772 | * |
| 5773 | * The "separate ring for rx status" scheme may sound queer, but it makes |
| 5774 | * sense from a cache coherency perspective. If only the host writes |
| 5775 | * to the buffer post rings, and only the chip writes to the rx status |
| 5776 | * rings, then cache lines never move beyond shared-modified state. |
| 5777 | * If both the host and chip were to write into the same ring, cache line |
| 5778 | * eviction could occur since both entities want it in an exclusive state. |
| 5779 | */ |
Matt Carlson | 17375d2 | 2009-08-28 14:02:18 +0000 | [diff] [blame] | 5780 | static int tg3_rx(struct tg3_napi *tnapi, int budget) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5781 | { |
Matt Carlson | 17375d2 | 2009-08-28 14:02:18 +0000 | [diff] [blame] | 5782 | struct tg3 *tp = tnapi->tp; |
Michael Chan | f92905d | 2006-06-29 20:14:29 -0700 | [diff] [blame] | 5783 | u32 work_mask, rx_std_posted = 0; |
Matt Carlson | 4361935 | 2009-11-13 13:03:47 +0000 | [diff] [blame] | 5784 | u32 std_prod_idx, jmb_prod_idx; |
Matt Carlson | 7233448 | 2009-08-28 14:03:01 +0000 | [diff] [blame] | 5785 | u32 sw_idx = tnapi->rx_rcb_ptr; |
Michael Chan | 483ba50 | 2005-04-25 15:14:03 -0700 | [diff] [blame] | 5786 | u16 hw_idx; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5787 | int received; |
Matt Carlson | 8fea32b | 2010-09-15 08:59:58 +0000 | [diff] [blame] | 5788 | struct tg3_rx_prodring_set *tpr = &tnapi->prodring; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5789 | |
Matt Carlson | 8d9d7cf | 2009-09-01 13:19:05 +0000 | [diff] [blame] | 5790 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5791 | /* |
| 5792 | * We need to order the read of hw_idx and the read of |
| 5793 | * the opaque cookie. |
| 5794 | */ |
| 5795 | rmb(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5796 | work_mask = 0; |
| 5797 | received = 0; |
Matt Carlson | 4361935 | 2009-11-13 13:03:47 +0000 | [diff] [blame] | 5798 | std_prod_idx = tpr->rx_std_prod_idx; |
| 5799 | jmb_prod_idx = tpr->rx_jmb_prod_idx; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5800 | while (sw_idx != hw_idx && budget > 0) { |
Matt Carlson | afc081f | 2009-11-13 13:03:43 +0000 | [diff] [blame] | 5801 | struct ring_info *ri; |
Matt Carlson | 7233448 | 2009-08-28 14:03:01 +0000 | [diff] [blame] | 5802 | struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5803 | unsigned int len; |
| 5804 | struct sk_buff *skb; |
| 5805 | dma_addr_t dma_addr; |
| 5806 | u32 opaque_key, desc_idx, *post_ptr; |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5807 | u8 *data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5808 | |
| 5809 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; |
| 5810 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; |
| 5811 | if (opaque_key == RXD_OPAQUE_RING_STD) { |
Matt Carlson | 8fea32b | 2010-09-15 08:59:58 +0000 | [diff] [blame] | 5812 | ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; |
FUJITA Tomonori | 4e5e4f0 | 2010-04-12 14:32:09 +0000 | [diff] [blame] | 5813 | dma_addr = dma_unmap_addr(ri, mapping); |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5814 | data = ri->data; |
Matt Carlson | 4361935 | 2009-11-13 13:03:47 +0000 | [diff] [blame] | 5815 | post_ptr = &std_prod_idx; |
Michael Chan | f92905d | 2006-06-29 20:14:29 -0700 | [diff] [blame] | 5816 | rx_std_posted++; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5817 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { |
Matt Carlson | 8fea32b | 2010-09-15 08:59:58 +0000 | [diff] [blame] | 5818 | ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; |
FUJITA Tomonori | 4e5e4f0 | 2010-04-12 14:32:09 +0000 | [diff] [blame] | 5819 | dma_addr = dma_unmap_addr(ri, mapping); |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5820 | data = ri->data; |
Matt Carlson | 4361935 | 2009-11-13 13:03:47 +0000 | [diff] [blame] | 5821 | post_ptr = &jmb_prod_idx; |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 5822 | } else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5823 | goto next_pkt_nopost; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5824 | |
| 5825 | work_mask |= opaque_key; |
| 5826 | |
| 5827 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && |
| 5828 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) { |
| 5829 | drop_it: |
Matt Carlson | a389616 | 2009-11-13 13:03:44 +0000 | [diff] [blame] | 5830 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5831 | desc_idx, *post_ptr); |
| 5832 | drop_it_no_recycle: |
| 5833 | /* Other statistics kept track of by card. */ |
Eric Dumazet | b0057c5 | 2010-10-10 19:55:52 +0000 | [diff] [blame] | 5834 | tp->rx_dropped++; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5835 | goto next_pkt; |
| 5836 | } |
| 5837 | |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5838 | prefetch(data + TG3_RX_OFFSET(tp)); |
Matt Carlson | ad82926 | 2008-11-21 17:16:16 -0800 | [diff] [blame] | 5839 | len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - |
| 5840 | ETH_FCS_LEN; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5841 | |
Matt Carlson | d2757fc | 2010-04-12 06:58:27 +0000 | [diff] [blame] | 5842 | if (len > TG3_RX_COPY_THRESH(tp)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5843 | int skb_size; |
| 5844 | |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5845 | skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key, |
Matt Carlson | afc081f | 2009-11-13 13:03:43 +0000 | [diff] [blame] | 5846 | *post_ptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5847 | if (skb_size < 0) |
| 5848 | goto drop_it; |
| 5849 | |
Matt Carlson | 287be12 | 2009-08-28 13:58:46 +0000 | [diff] [blame] | 5850 | pci_unmap_single(tp->pdev, dma_addr, skb_size, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5851 | PCI_DMA_FROMDEVICE); |
| 5852 | |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5853 | skb = build_skb(data); |
| 5854 | if (!skb) { |
| 5855 | kfree(data); |
| 5856 | goto drop_it_no_recycle; |
| 5857 | } |
| 5858 | skb_reserve(skb, TG3_RX_OFFSET(tp)); |
| 5859 | /* Ensure that the update to the data happens |
Matt Carlson | 61e800c | 2010-02-17 15:16:54 +0000 | [diff] [blame] | 5860 | * after the usage of the old DMA mapping. |
| 5861 | */ |
| 5862 | smp_wmb(); |
| 5863 | |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5864 | ri->data = NULL; |
Matt Carlson | 61e800c | 2010-02-17 15:16:54 +0000 | [diff] [blame] | 5865 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5866 | } else { |
Matt Carlson | a389616 | 2009-11-13 13:03:44 +0000 | [diff] [blame] | 5867 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5868 | desc_idx, *post_ptr); |
| 5869 | |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5870 | skb = netdev_alloc_skb(tp->dev, |
| 5871 | len + TG3_RAW_IP_ALIGN); |
| 5872 | if (skb == NULL) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5873 | goto drop_it_no_recycle; |
| 5874 | |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5875 | skb_reserve(skb, TG3_RAW_IP_ALIGN); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5876 | pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5877 | memcpy(skb->data, |
| 5878 | data + TG3_RX_OFFSET(tp), |
| 5879 | len); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5880 | pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5881 | } |
| 5882 | |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 5883 | skb_put(skb, len); |
Michał Mirosław | dc66891 | 2011-04-07 03:35:07 +0000 | [diff] [blame] | 5884 | if ((tp->dev->features & NETIF_F_RXCSUM) && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5885 | (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && |
| 5886 | (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) |
| 5887 | >> RXD_TCPCSUM_SHIFT) == 0xffff)) |
| 5888 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
| 5889 | else |
Eric Dumazet | bc8acf2 | 2010-09-02 13:07:41 -0700 | [diff] [blame] | 5890 | skb_checksum_none_assert(skb); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5891 | |
| 5892 | skb->protocol = eth_type_trans(skb, tp->dev); |
Matt Carlson | f7b493e | 2009-02-25 14:21:52 +0000 | [diff] [blame] | 5893 | |
| 5894 | if (len > (tp->dev->mtu + ETH_HLEN) && |
| 5895 | skb->protocol != htons(ETH_P_8021Q)) { |
| 5896 | dev_kfree_skb(skb); |
Eric Dumazet | b0057c5 | 2010-10-10 19:55:52 +0000 | [diff] [blame] | 5897 | goto drop_it_no_recycle; |
Matt Carlson | f7b493e | 2009-02-25 14:21:52 +0000 | [diff] [blame] | 5898 | } |
| 5899 | |
Matt Carlson | 9dc7a11 | 2010-04-12 06:58:28 +0000 | [diff] [blame] | 5900 | if (desc->type_flags & RXD_FLAG_VLAN && |
Matt Carlson | bf933c8 | 2011-01-25 15:58:49 +0000 | [diff] [blame] | 5901 | !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) |
| 5902 | __vlan_hwaccel_put_tag(skb, |
| 5903 | desc->err_vlan & RXD_VLAN_MASK); |
Matt Carlson | 9dc7a11 | 2010-04-12 06:58:28 +0000 | [diff] [blame] | 5904 | |
Matt Carlson | bf933c8 | 2011-01-25 15:58:49 +0000 | [diff] [blame] | 5905 | napi_gro_receive(&tnapi->napi, skb); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5906 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5907 | received++; |
| 5908 | budget--; |
| 5909 | |
| 5910 | next_pkt: |
| 5911 | (*post_ptr)++; |
Michael Chan | f92905d | 2006-06-29 20:14:29 -0700 | [diff] [blame] | 5912 | |
| 5913 | if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 5914 | tpr->rx_std_prod_idx = std_prod_idx & |
| 5915 | tp->rx_std_ring_mask; |
Matt Carlson | 86cfe4f | 2010-01-12 10:11:37 +0000 | [diff] [blame] | 5916 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
| 5917 | tpr->rx_std_prod_idx); |
Michael Chan | f92905d | 2006-06-29 20:14:29 -0700 | [diff] [blame] | 5918 | work_mask &= ~RXD_OPAQUE_RING_STD; |
| 5919 | rx_std_posted = 0; |
| 5920 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5921 | next_pkt_nopost: |
Michael Chan | 483ba50 | 2005-04-25 15:14:03 -0700 | [diff] [blame] | 5922 | sw_idx++; |
Matt Carlson | 7cb32cf | 2010-09-30 10:34:36 +0000 | [diff] [blame] | 5923 | sw_idx &= tp->rx_ret_ring_mask; |
Michael Chan | 52f6d69 | 2005-04-25 15:14:32 -0700 | [diff] [blame] | 5924 | |
| 5925 | /* Refresh hw_idx to see if there is new work */ |
| 5926 | if (sw_idx == hw_idx) { |
Matt Carlson | 8d9d7cf | 2009-09-01 13:19:05 +0000 | [diff] [blame] | 5927 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
Michael Chan | 52f6d69 | 2005-04-25 15:14:32 -0700 | [diff] [blame] | 5928 | rmb(); |
| 5929 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5930 | } |
| 5931 | |
| 5932 | /* ACK the status ring. */ |
Matt Carlson | 7233448 | 2009-08-28 14:03:01 +0000 | [diff] [blame] | 5933 | tnapi->rx_rcb_ptr = sw_idx; |
| 5934 | tw32_rx_mbox(tnapi->consmbox, sw_idx); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5935 | |
| 5936 | /* Refill RX ring(s). */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 5937 | if (!tg3_flag(tp, ENABLE_RSS)) { |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 5938 | if (work_mask & RXD_OPAQUE_RING_STD) { |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 5939 | tpr->rx_std_prod_idx = std_prod_idx & |
| 5940 | tp->rx_std_ring_mask; |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 5941 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
| 5942 | tpr->rx_std_prod_idx); |
| 5943 | } |
| 5944 | if (work_mask & RXD_OPAQUE_RING_JUMBO) { |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 5945 | tpr->rx_jmb_prod_idx = jmb_prod_idx & |
| 5946 | tp->rx_jmb_ring_mask; |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 5947 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, |
| 5948 | tpr->rx_jmb_prod_idx); |
| 5949 | } |
| 5950 | mmiowb(); |
| 5951 | } else if (work_mask) { |
| 5952 | /* rx_std_buffers[] and rx_jmb_buffers[] entries must be |
| 5953 | * updated before the producer indices can be updated. |
| 5954 | */ |
| 5955 | smp_wmb(); |
| 5956 | |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 5957 | tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; |
| 5958 | tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 5959 | |
Matt Carlson | e4af1af | 2010-02-12 14:47:05 +0000 | [diff] [blame] | 5960 | if (tnapi != &tp->napi[1]) |
| 5961 | napi_schedule(&tp->napi[1].napi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5962 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5963 | |
| 5964 | return received; |
| 5965 | } |
| 5966 | |
Matt Carlson | 35f2d7d | 2009-11-13 13:03:41 +0000 | [diff] [blame] | 5967 | static void tg3_poll_link(struct tg3 *tp) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5968 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5969 | /* handle link change and other phy events */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 5970 | if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { |
Matt Carlson | 35f2d7d | 2009-11-13 13:03:41 +0000 | [diff] [blame] | 5971 | struct tg3_hw_status *sblk = tp->napi[0].hw_status; |
| 5972 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5973 | if (sblk->status & SD_STATUS_LINK_CHG) { |
| 5974 | sblk->status = SD_STATUS_UPDATED | |
Matt Carlson | 35f2d7d | 2009-11-13 13:03:41 +0000 | [diff] [blame] | 5975 | (sblk->status & ~SD_STATUS_LINK_CHG); |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 5976 | spin_lock(&tp->lock); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 5977 | if (tg3_flag(tp, USE_PHYLIB)) { |
Matt Carlson | dd47700 | 2008-05-25 23:45:58 -0700 | [diff] [blame] | 5978 | tw32_f(MAC_STATUS, |
| 5979 | (MAC_STATUS_SYNC_CHANGED | |
| 5980 | MAC_STATUS_CFG_CHANGED | |
| 5981 | MAC_STATUS_MI_COMPLETION | |
| 5982 | MAC_STATUS_LNKSTATE_CHANGED)); |
| 5983 | udelay(40); |
| 5984 | } else |
| 5985 | tg3_setup_phy(tp, 0); |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 5986 | spin_unlock(&tp->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5987 | } |
| 5988 | } |
Matt Carlson | 35f2d7d | 2009-11-13 13:03:41 +0000 | [diff] [blame] | 5989 | } |
| 5990 | |
Matt Carlson | f89f38b | 2010-02-12 14:47:07 +0000 | [diff] [blame] | 5991 | static int tg3_rx_prodring_xfer(struct tg3 *tp, |
| 5992 | struct tg3_rx_prodring_set *dpr, |
| 5993 | struct tg3_rx_prodring_set *spr) |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 5994 | { |
| 5995 | u32 si, di, cpycnt, src_prod_idx; |
Matt Carlson | f89f38b | 2010-02-12 14:47:07 +0000 | [diff] [blame] | 5996 | int i, err = 0; |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 5997 | |
| 5998 | while (1) { |
| 5999 | src_prod_idx = spr->rx_std_prod_idx; |
| 6000 | |
| 6001 | /* Make sure updates to the rx_std_buffers[] entries and the |
| 6002 | * standard producer index are seen in the correct order. |
| 6003 | */ |
| 6004 | smp_rmb(); |
| 6005 | |
| 6006 | if (spr->rx_std_cons_idx == src_prod_idx) |
| 6007 | break; |
| 6008 | |
| 6009 | if (spr->rx_std_cons_idx < src_prod_idx) |
| 6010 | cpycnt = src_prod_idx - spr->rx_std_cons_idx; |
| 6011 | else |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 6012 | cpycnt = tp->rx_std_ring_mask + 1 - |
| 6013 | spr->rx_std_cons_idx; |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 6014 | |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 6015 | cpycnt = min(cpycnt, |
| 6016 | tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 6017 | |
| 6018 | si = spr->rx_std_cons_idx; |
| 6019 | di = dpr->rx_std_prod_idx; |
| 6020 | |
Matt Carlson | e92967b | 2010-02-12 14:47:06 +0000 | [diff] [blame] | 6021 | for (i = di; i < di + cpycnt; i++) { |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 6022 | if (dpr->rx_std_buffers[i].data) { |
Matt Carlson | e92967b | 2010-02-12 14:47:06 +0000 | [diff] [blame] | 6023 | cpycnt = i - di; |
Matt Carlson | f89f38b | 2010-02-12 14:47:07 +0000 | [diff] [blame] | 6024 | err = -ENOSPC; |
Matt Carlson | e92967b | 2010-02-12 14:47:06 +0000 | [diff] [blame] | 6025 | break; |
| 6026 | } |
| 6027 | } |
| 6028 | |
| 6029 | if (!cpycnt) |
| 6030 | break; |
| 6031 | |
| 6032 | /* Ensure that updates to the rx_std_buffers ring and the |
| 6033 | * shadowed hardware producer ring from tg3_recycle_skb() are |
| 6034 | * ordered correctly WRT the skb check above. |
| 6035 | */ |
| 6036 | smp_rmb(); |
| 6037 | |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 6038 | memcpy(&dpr->rx_std_buffers[di], |
| 6039 | &spr->rx_std_buffers[si], |
| 6040 | cpycnt * sizeof(struct ring_info)); |
| 6041 | |
| 6042 | for (i = 0; i < cpycnt; i++, di++, si++) { |
| 6043 | struct tg3_rx_buffer_desc *sbd, *dbd; |
| 6044 | sbd = &spr->rx_std[si]; |
| 6045 | dbd = &dpr->rx_std[di]; |
| 6046 | dbd->addr_hi = sbd->addr_hi; |
| 6047 | dbd->addr_lo = sbd->addr_lo; |
| 6048 | } |
| 6049 | |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 6050 | spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & |
| 6051 | tp->rx_std_ring_mask; |
| 6052 | dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & |
| 6053 | tp->rx_std_ring_mask; |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 6054 | } |
| 6055 | |
| 6056 | while (1) { |
| 6057 | src_prod_idx = spr->rx_jmb_prod_idx; |
| 6058 | |
| 6059 | /* Make sure updates to the rx_jmb_buffers[] entries and |
| 6060 | * the jumbo producer index are seen in the correct order. |
| 6061 | */ |
| 6062 | smp_rmb(); |
| 6063 | |
| 6064 | if (spr->rx_jmb_cons_idx == src_prod_idx) |
| 6065 | break; |
| 6066 | |
| 6067 | if (spr->rx_jmb_cons_idx < src_prod_idx) |
| 6068 | cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; |
| 6069 | else |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 6070 | cpycnt = tp->rx_jmb_ring_mask + 1 - |
| 6071 | spr->rx_jmb_cons_idx; |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 6072 | |
| 6073 | cpycnt = min(cpycnt, |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 6074 | tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 6075 | |
| 6076 | si = spr->rx_jmb_cons_idx; |
| 6077 | di = dpr->rx_jmb_prod_idx; |
| 6078 | |
Matt Carlson | e92967b | 2010-02-12 14:47:06 +0000 | [diff] [blame] | 6079 | for (i = di; i < di + cpycnt; i++) { |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 6080 | if (dpr->rx_jmb_buffers[i].data) { |
Matt Carlson | e92967b | 2010-02-12 14:47:06 +0000 | [diff] [blame] | 6081 | cpycnt = i - di; |
Matt Carlson | f89f38b | 2010-02-12 14:47:07 +0000 | [diff] [blame] | 6082 | err = -ENOSPC; |
Matt Carlson | e92967b | 2010-02-12 14:47:06 +0000 | [diff] [blame] | 6083 | break; |
| 6084 | } |
| 6085 | } |
| 6086 | |
| 6087 | if (!cpycnt) |
| 6088 | break; |
| 6089 | |
| 6090 | /* Ensure that updates to the rx_jmb_buffers ring and the |
| 6091 | * shadowed hardware producer ring from tg3_recycle_skb() are |
| 6092 | * ordered correctly WRT the skb check above. |
| 6093 | */ |
| 6094 | smp_rmb(); |
| 6095 | |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 6096 | memcpy(&dpr->rx_jmb_buffers[di], |
| 6097 | &spr->rx_jmb_buffers[si], |
| 6098 | cpycnt * sizeof(struct ring_info)); |
| 6099 | |
| 6100 | for (i = 0; i < cpycnt; i++, di++, si++) { |
| 6101 | struct tg3_rx_buffer_desc *sbd, *dbd; |
| 6102 | sbd = &spr->rx_jmb[si].std; |
| 6103 | dbd = &dpr->rx_jmb[di].std; |
| 6104 | dbd->addr_hi = sbd->addr_hi; |
| 6105 | dbd->addr_lo = sbd->addr_lo; |
| 6106 | } |
| 6107 | |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 6108 | spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & |
| 6109 | tp->rx_jmb_ring_mask; |
| 6110 | dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & |
| 6111 | tp->rx_jmb_ring_mask; |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 6112 | } |
Matt Carlson | f89f38b | 2010-02-12 14:47:07 +0000 | [diff] [blame] | 6113 | |
| 6114 | return err; |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 6115 | } |
| 6116 | |
Matt Carlson | 35f2d7d | 2009-11-13 13:03:41 +0000 | [diff] [blame] | 6117 | static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) |
| 6118 | { |
| 6119 | struct tg3 *tp = tnapi->tp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6120 | |
| 6121 | /* run TX completion thread */ |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 6122 | if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { |
Matt Carlson | 17375d2 | 2009-08-28 14:02:18 +0000 | [diff] [blame] | 6123 | tg3_tx(tnapi); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 6124 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
Michael Chan | 4fd7ab5 | 2007-10-12 01:39:50 -0700 | [diff] [blame] | 6125 | return work_done; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6126 | } |
| 6127 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6128 | /* run RX thread, within the bounds set by NAPI. |
| 6129 | * All RX "locking" is done by ensuring outside |
Stephen Hemminger | bea3348 | 2007-10-03 16:41:36 -0700 | [diff] [blame] | 6130 | * code synchronizes with tg3->napi.poll() |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6131 | */ |
Matt Carlson | 8d9d7cf | 2009-09-01 13:19:05 +0000 | [diff] [blame] | 6132 | if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
Matt Carlson | 17375d2 | 2009-08-28 14:02:18 +0000 | [diff] [blame] | 6133 | work_done += tg3_rx(tnapi, budget - work_done); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6134 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 6135 | if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { |
Matt Carlson | 8fea32b | 2010-09-15 08:59:58 +0000 | [diff] [blame] | 6136 | struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; |
Matt Carlson | f89f38b | 2010-02-12 14:47:07 +0000 | [diff] [blame] | 6137 | int i, err = 0; |
Matt Carlson | e4af1af | 2010-02-12 14:47:05 +0000 | [diff] [blame] | 6138 | u32 std_prod_idx = dpr->rx_std_prod_idx; |
| 6139 | u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 6140 | |
Matt Carlson | e4af1af | 2010-02-12 14:47:05 +0000 | [diff] [blame] | 6141 | for (i = 1; i < tp->irq_cnt; i++) |
Matt Carlson | f89f38b | 2010-02-12 14:47:07 +0000 | [diff] [blame] | 6142 | err |= tg3_rx_prodring_xfer(tp, dpr, |
Matt Carlson | 8fea32b | 2010-09-15 08:59:58 +0000 | [diff] [blame] | 6143 | &tp->napi[i].prodring); |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 6144 | |
| 6145 | wmb(); |
| 6146 | |
Matt Carlson | e4af1af | 2010-02-12 14:47:05 +0000 | [diff] [blame] | 6147 | if (std_prod_idx != dpr->rx_std_prod_idx) |
| 6148 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, |
| 6149 | dpr->rx_std_prod_idx); |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 6150 | |
Matt Carlson | e4af1af | 2010-02-12 14:47:05 +0000 | [diff] [blame] | 6151 | if (jmb_prod_idx != dpr->rx_jmb_prod_idx) |
| 6152 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, |
| 6153 | dpr->rx_jmb_prod_idx); |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 6154 | |
| 6155 | mmiowb(); |
Matt Carlson | f89f38b | 2010-02-12 14:47:07 +0000 | [diff] [blame] | 6156 | |
| 6157 | if (err) |
| 6158 | tw32_f(HOSTCC_MODE, tp->coal_now); |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 6159 | } |
| 6160 | |
David S. Miller | 6f53576 | 2007-10-11 18:08:29 -0700 | [diff] [blame] | 6161 | return work_done; |
| 6162 | } |
David S. Miller | f7383c2 | 2005-05-18 22:50:53 -0700 | [diff] [blame] | 6163 | |
Matt Carlson | db21997 | 2011-11-04 09:15:03 +0000 | [diff] [blame] | 6164 | static inline void tg3_reset_task_schedule(struct tg3 *tp) |
| 6165 | { |
| 6166 | if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) |
| 6167 | schedule_work(&tp->reset_task); |
| 6168 | } |
| 6169 | |
| 6170 | static inline void tg3_reset_task_cancel(struct tg3 *tp) |
| 6171 | { |
| 6172 | cancel_work_sync(&tp->reset_task); |
| 6173 | tg3_flag_clear(tp, RESET_TASK_PENDING); |
| 6174 | } |
| 6175 | |
Matt Carlson | 35f2d7d | 2009-11-13 13:03:41 +0000 | [diff] [blame] | 6176 | static int tg3_poll_msix(struct napi_struct *napi, int budget) |
| 6177 | { |
| 6178 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); |
| 6179 | struct tg3 *tp = tnapi->tp; |
| 6180 | int work_done = 0; |
| 6181 | struct tg3_hw_status *sblk = tnapi->hw_status; |
| 6182 | |
| 6183 | while (1) { |
| 6184 | work_done = tg3_poll_work(tnapi, work_done, budget); |
| 6185 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 6186 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
Matt Carlson | 35f2d7d | 2009-11-13 13:03:41 +0000 | [diff] [blame] | 6187 | goto tx_recovery; |
| 6188 | |
| 6189 | if (unlikely(work_done >= budget)) |
| 6190 | break; |
| 6191 | |
Matt Carlson | c6cdf43 | 2010-04-05 10:19:26 +0000 | [diff] [blame] | 6192 | /* tp->last_tag is used in tg3_int_reenable() below |
Matt Carlson | 35f2d7d | 2009-11-13 13:03:41 +0000 | [diff] [blame] | 6193 | * to tell the hw how much work has been processed, |
| 6194 | * so we must read it before checking for more work. |
| 6195 | */ |
| 6196 | tnapi->last_tag = sblk->status_tag; |
| 6197 | tnapi->last_irq_tag = tnapi->last_tag; |
| 6198 | rmb(); |
| 6199 | |
| 6200 | /* check for RX/TX work to do */ |
Matt Carlson | 6d40db7 | 2010-04-05 10:19:20 +0000 | [diff] [blame] | 6201 | if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && |
| 6202 | *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { |
Matt Carlson | 35f2d7d | 2009-11-13 13:03:41 +0000 | [diff] [blame] | 6203 | napi_complete(napi); |
| 6204 | /* Reenable interrupts. */ |
| 6205 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); |
| 6206 | mmiowb(); |
| 6207 | break; |
| 6208 | } |
| 6209 | } |
| 6210 | |
| 6211 | return work_done; |
| 6212 | |
| 6213 | tx_recovery: |
| 6214 | /* work_done is guaranteed to be less than budget. */ |
| 6215 | napi_complete(napi); |
Matt Carlson | db21997 | 2011-11-04 09:15:03 +0000 | [diff] [blame] | 6216 | tg3_reset_task_schedule(tp); |
Matt Carlson | 35f2d7d | 2009-11-13 13:03:41 +0000 | [diff] [blame] | 6217 | return work_done; |
| 6218 | } |
| 6219 | |
Matt Carlson | e64de4e | 2011-04-13 11:05:05 +0000 | [diff] [blame] | 6220 | static void tg3_process_error(struct tg3 *tp) |
| 6221 | { |
| 6222 | u32 val; |
| 6223 | bool real_error = false; |
| 6224 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 6225 | if (tg3_flag(tp, ERROR_PROCESSED)) |
Matt Carlson | e64de4e | 2011-04-13 11:05:05 +0000 | [diff] [blame] | 6226 | return; |
| 6227 | |
| 6228 | /* Check Flow Attention register */ |
| 6229 | val = tr32(HOSTCC_FLOW_ATTN); |
| 6230 | if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) { |
| 6231 | netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); |
| 6232 | real_error = true; |
| 6233 | } |
| 6234 | |
| 6235 | if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) { |
| 6236 | netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); |
| 6237 | real_error = true; |
| 6238 | } |
| 6239 | |
| 6240 | if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) { |
| 6241 | netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); |
| 6242 | real_error = true; |
| 6243 | } |
| 6244 | |
| 6245 | if (!real_error) |
| 6246 | return; |
| 6247 | |
| 6248 | tg3_dump_state(tp); |
| 6249 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 6250 | tg3_flag_set(tp, ERROR_PROCESSED); |
Matt Carlson | db21997 | 2011-11-04 09:15:03 +0000 | [diff] [blame] | 6251 | tg3_reset_task_schedule(tp); |
Matt Carlson | e64de4e | 2011-04-13 11:05:05 +0000 | [diff] [blame] | 6252 | } |
| 6253 | |
David S. Miller | 6f53576 | 2007-10-11 18:08:29 -0700 | [diff] [blame] | 6254 | static int tg3_poll(struct napi_struct *napi, int budget) |
| 6255 | { |
Matt Carlson | 8ef0442 | 2009-08-28 14:01:37 +0000 | [diff] [blame] | 6256 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); |
| 6257 | struct tg3 *tp = tnapi->tp; |
David S. Miller | 6f53576 | 2007-10-11 18:08:29 -0700 | [diff] [blame] | 6258 | int work_done = 0; |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 6259 | struct tg3_hw_status *sblk = tnapi->hw_status; |
David S. Miller | 6f53576 | 2007-10-11 18:08:29 -0700 | [diff] [blame] | 6260 | |
| 6261 | while (1) { |
Matt Carlson | e64de4e | 2011-04-13 11:05:05 +0000 | [diff] [blame] | 6262 | if (sblk->status & SD_STATUS_ERROR) |
| 6263 | tg3_process_error(tp); |
| 6264 | |
Matt Carlson | 35f2d7d | 2009-11-13 13:03:41 +0000 | [diff] [blame] | 6265 | tg3_poll_link(tp); |
| 6266 | |
Matt Carlson | 17375d2 | 2009-08-28 14:02:18 +0000 | [diff] [blame] | 6267 | work_done = tg3_poll_work(tnapi, work_done, budget); |
David S. Miller | 6f53576 | 2007-10-11 18:08:29 -0700 | [diff] [blame] | 6268 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 6269 | if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) |
David S. Miller | 6f53576 | 2007-10-11 18:08:29 -0700 | [diff] [blame] | 6270 | goto tx_recovery; |
| 6271 | |
| 6272 | if (unlikely(work_done >= budget)) |
| 6273 | break; |
| 6274 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 6275 | if (tg3_flag(tp, TAGGED_STATUS)) { |
Matt Carlson | 17375d2 | 2009-08-28 14:02:18 +0000 | [diff] [blame] | 6276 | /* tp->last_tag is used in tg3_int_reenable() below |
Michael Chan | 4fd7ab5 | 2007-10-12 01:39:50 -0700 | [diff] [blame] | 6277 | * to tell the hw how much work has been processed, |
| 6278 | * so we must read it before checking for more work. |
| 6279 | */ |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 6280 | tnapi->last_tag = sblk->status_tag; |
| 6281 | tnapi->last_irq_tag = tnapi->last_tag; |
Michael Chan | 4fd7ab5 | 2007-10-12 01:39:50 -0700 | [diff] [blame] | 6282 | rmb(); |
| 6283 | } else |
| 6284 | sblk->status &= ~SD_STATUS_UPDATED; |
| 6285 | |
Matt Carlson | 17375d2 | 2009-08-28 14:02:18 +0000 | [diff] [blame] | 6286 | if (likely(!tg3_has_work(tnapi))) { |
Ben Hutchings | 288379f | 2009-01-19 16:43:59 -0800 | [diff] [blame] | 6287 | napi_complete(napi); |
Matt Carlson | 17375d2 | 2009-08-28 14:02:18 +0000 | [diff] [blame] | 6288 | tg3_int_reenable(tnapi); |
David S. Miller | 6f53576 | 2007-10-11 18:08:29 -0700 | [diff] [blame] | 6289 | break; |
| 6290 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6291 | } |
| 6292 | |
Stephen Hemminger | bea3348 | 2007-10-03 16:41:36 -0700 | [diff] [blame] | 6293 | return work_done; |
David S. Miller | 6f53576 | 2007-10-11 18:08:29 -0700 | [diff] [blame] | 6294 | |
| 6295 | tx_recovery: |
Michael Chan | 4fd7ab5 | 2007-10-12 01:39:50 -0700 | [diff] [blame] | 6296 | /* work_done is guaranteed to be less than budget. */ |
Ben Hutchings | 288379f | 2009-01-19 16:43:59 -0800 | [diff] [blame] | 6297 | napi_complete(napi); |
Matt Carlson | db21997 | 2011-11-04 09:15:03 +0000 | [diff] [blame] | 6298 | tg3_reset_task_schedule(tp); |
Michael Chan | 4fd7ab5 | 2007-10-12 01:39:50 -0700 | [diff] [blame] | 6299 | return work_done; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6300 | } |
| 6301 | |
Matt Carlson | 66cfd1b | 2010-09-30 10:34:30 +0000 | [diff] [blame] | 6302 | static void tg3_napi_disable(struct tg3 *tp) |
| 6303 | { |
| 6304 | int i; |
| 6305 | |
| 6306 | for (i = tp->irq_cnt - 1; i >= 0; i--) |
| 6307 | napi_disable(&tp->napi[i].napi); |
| 6308 | } |
| 6309 | |
| 6310 | static void tg3_napi_enable(struct tg3 *tp) |
| 6311 | { |
| 6312 | int i; |
| 6313 | |
| 6314 | for (i = 0; i < tp->irq_cnt; i++) |
| 6315 | napi_enable(&tp->napi[i].napi); |
| 6316 | } |
| 6317 | |
| 6318 | static void tg3_napi_init(struct tg3 *tp) |
| 6319 | { |
| 6320 | int i; |
| 6321 | |
| 6322 | netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64); |
| 6323 | for (i = 1; i < tp->irq_cnt; i++) |
| 6324 | netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64); |
| 6325 | } |
| 6326 | |
| 6327 | static void tg3_napi_fini(struct tg3 *tp) |
| 6328 | { |
| 6329 | int i; |
| 6330 | |
| 6331 | for (i = 0; i < tp->irq_cnt; i++) |
| 6332 | netif_napi_del(&tp->napi[i].napi); |
| 6333 | } |
| 6334 | |
| 6335 | static inline void tg3_netif_stop(struct tg3 *tp) |
| 6336 | { |
| 6337 | tp->dev->trans_start = jiffies; /* prevent tx timeout */ |
| 6338 | tg3_napi_disable(tp); |
| 6339 | netif_tx_disable(tp->dev); |
| 6340 | } |
| 6341 | |
| 6342 | static inline void tg3_netif_start(struct tg3 *tp) |
| 6343 | { |
| 6344 | /* NOTE: unconditional netif_tx_wake_all_queues is only |
| 6345 | * appropriate so long as all callers are assured to |
| 6346 | * have free tx slots (such as after tg3_init_hw) |
| 6347 | */ |
| 6348 | netif_tx_wake_all_queues(tp->dev); |
| 6349 | |
| 6350 | tg3_napi_enable(tp); |
| 6351 | tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; |
| 6352 | tg3_enable_ints(tp); |
| 6353 | } |
| 6354 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 6355 | static void tg3_irq_quiesce(struct tg3 *tp) |
| 6356 | { |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 6357 | int i; |
| 6358 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 6359 | BUG_ON(tp->irq_sync); |
| 6360 | |
| 6361 | tp->irq_sync = 1; |
| 6362 | smp_mb(); |
| 6363 | |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 6364 | for (i = 0; i < tp->irq_cnt; i++) |
| 6365 | synchronize_irq(tp->napi[i].irq_vec); |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 6366 | } |
| 6367 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 6368 | /* Fully shutdown all tg3 driver activity elsewhere in the system. |
| 6369 | * If irq_sync is non-zero, then the IRQ handler must be synchronized |
| 6370 | * with as well. Most of the time, this is not necessary except when |
| 6371 | * shutting down the device. |
| 6372 | */ |
| 6373 | static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) |
| 6374 | { |
Michael Chan | 4696654 | 2007-07-11 19:47:19 -0700 | [diff] [blame] | 6375 | spin_lock_bh(&tp->lock); |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 6376 | if (irq_sync) |
| 6377 | tg3_irq_quiesce(tp); |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 6378 | } |
| 6379 | |
| 6380 | static inline void tg3_full_unlock(struct tg3 *tp) |
| 6381 | { |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 6382 | spin_unlock_bh(&tp->lock); |
| 6383 | } |
| 6384 | |
Michael Chan | fcfa0a3 | 2006-03-20 22:28:41 -0800 | [diff] [blame] | 6385 | /* One-shot MSI handler - Chip automatically disables interrupt |
| 6386 | * after sending MSI so driver doesn't have to do it. |
| 6387 | */ |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 6388 | static irqreturn_t tg3_msi_1shot(int irq, void *dev_id) |
Michael Chan | fcfa0a3 | 2006-03-20 22:28:41 -0800 | [diff] [blame] | 6389 | { |
Matt Carlson | 09943a1 | 2009-08-28 14:01:57 +0000 | [diff] [blame] | 6390 | struct tg3_napi *tnapi = dev_id; |
| 6391 | struct tg3 *tp = tnapi->tp; |
Michael Chan | fcfa0a3 | 2006-03-20 22:28:41 -0800 | [diff] [blame] | 6392 | |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 6393 | prefetch(tnapi->hw_status); |
Matt Carlson | 0c1d0e2 | 2009-09-01 13:16:33 +0000 | [diff] [blame] | 6394 | if (tnapi->rx_rcb) |
| 6395 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
Michael Chan | fcfa0a3 | 2006-03-20 22:28:41 -0800 | [diff] [blame] | 6396 | |
| 6397 | if (likely(!tg3_irq_sync(tp))) |
Matt Carlson | 09943a1 | 2009-08-28 14:01:57 +0000 | [diff] [blame] | 6398 | napi_schedule(&tnapi->napi); |
Michael Chan | fcfa0a3 | 2006-03-20 22:28:41 -0800 | [diff] [blame] | 6399 | |
| 6400 | return IRQ_HANDLED; |
| 6401 | } |
| 6402 | |
Michael Chan | 88b06bc2 | 2005-04-21 17:13:25 -0700 | [diff] [blame] | 6403 | /* MSI ISR - No need to check for interrupt sharing and no need to |
| 6404 | * flush status block and interrupt mailbox. PCI ordering rules |
| 6405 | * guarantee that MSI will arrive after the status block. |
| 6406 | */ |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 6407 | static irqreturn_t tg3_msi(int irq, void *dev_id) |
Michael Chan | 88b06bc2 | 2005-04-21 17:13:25 -0700 | [diff] [blame] | 6408 | { |
Matt Carlson | 09943a1 | 2009-08-28 14:01:57 +0000 | [diff] [blame] | 6409 | struct tg3_napi *tnapi = dev_id; |
| 6410 | struct tg3 *tp = tnapi->tp; |
Michael Chan | 88b06bc2 | 2005-04-21 17:13:25 -0700 | [diff] [blame] | 6411 | |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 6412 | prefetch(tnapi->hw_status); |
Matt Carlson | 0c1d0e2 | 2009-09-01 13:16:33 +0000 | [diff] [blame] | 6413 | if (tnapi->rx_rcb) |
| 6414 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
Michael Chan | 88b06bc2 | 2005-04-21 17:13:25 -0700 | [diff] [blame] | 6415 | /* |
David S. Miller | fac9b83 | 2005-05-18 22:46:34 -0700 | [diff] [blame] | 6416 | * Writing any value to intr-mbox-0 clears PCI INTA# and |
Michael Chan | 88b06bc2 | 2005-04-21 17:13:25 -0700 | [diff] [blame] | 6417 | * chip-internal interrupt pending events. |
David S. Miller | fac9b83 | 2005-05-18 22:46:34 -0700 | [diff] [blame] | 6418 | * Writing non-zero to intr-mbox-0 additional tells the |
Michael Chan | 88b06bc2 | 2005-04-21 17:13:25 -0700 | [diff] [blame] | 6419 | * NIC to stop sending us irqs, engaging "in-intr-handler" |
| 6420 | * event coalescing. |
| 6421 | */ |
Matt Carlson | 5b39de9 | 2011-08-31 11:44:50 +0000 | [diff] [blame] | 6422 | tw32_mailbox(tnapi->int_mbox, 0x00000001); |
Michael Chan | 6148748 | 2005-09-05 17:53:19 -0700 | [diff] [blame] | 6423 | if (likely(!tg3_irq_sync(tp))) |
Matt Carlson | 09943a1 | 2009-08-28 14:01:57 +0000 | [diff] [blame] | 6424 | napi_schedule(&tnapi->napi); |
Michael Chan | 6148748 | 2005-09-05 17:53:19 -0700 | [diff] [blame] | 6425 | |
Michael Chan | 88b06bc2 | 2005-04-21 17:13:25 -0700 | [diff] [blame] | 6426 | return IRQ_RETVAL(1); |
| 6427 | } |
| 6428 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 6429 | static irqreturn_t tg3_interrupt(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6430 | { |
Matt Carlson | 09943a1 | 2009-08-28 14:01:57 +0000 | [diff] [blame] | 6431 | struct tg3_napi *tnapi = dev_id; |
| 6432 | struct tg3 *tp = tnapi->tp; |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 6433 | struct tg3_hw_status *sblk = tnapi->hw_status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6434 | unsigned int handled = 1; |
| 6435 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6436 | /* In INTx mode, it is possible for the interrupt to arrive at |
| 6437 | * the CPU before the status block posted prior to the interrupt. |
| 6438 | * Reading the PCI State register will confirm whether the |
| 6439 | * interrupt is ours and will flush the status block. |
| 6440 | */ |
Michael Chan | d18edcb | 2007-03-24 20:57:11 -0700 | [diff] [blame] | 6441 | if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 6442 | if (tg3_flag(tp, CHIP_RESETTING) || |
Michael Chan | d18edcb | 2007-03-24 20:57:11 -0700 | [diff] [blame] | 6443 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { |
| 6444 | handled = 0; |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 6445 | goto out; |
David S. Miller | fac9b83 | 2005-05-18 22:46:34 -0700 | [diff] [blame] | 6446 | } |
Michael Chan | d18edcb | 2007-03-24 20:57:11 -0700 | [diff] [blame] | 6447 | } |
| 6448 | |
| 6449 | /* |
| 6450 | * Writing any value to intr-mbox-0 clears PCI INTA# and |
| 6451 | * chip-internal interrupt pending events. |
| 6452 | * Writing non-zero to intr-mbox-0 additional tells the |
| 6453 | * NIC to stop sending us irqs, engaging "in-intr-handler" |
| 6454 | * event coalescing. |
Michael Chan | c04cb34 | 2007-05-07 00:26:15 -0700 | [diff] [blame] | 6455 | * |
| 6456 | * Flush the mailbox to de-assert the IRQ immediately to prevent |
| 6457 | * spurious interrupts. The flush impacts performance but |
| 6458 | * excessive spurious interrupts can be worse in some cases. |
Michael Chan | d18edcb | 2007-03-24 20:57:11 -0700 | [diff] [blame] | 6459 | */ |
Michael Chan | c04cb34 | 2007-05-07 00:26:15 -0700 | [diff] [blame] | 6460 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
Michael Chan | d18edcb | 2007-03-24 20:57:11 -0700 | [diff] [blame] | 6461 | if (tg3_irq_sync(tp)) |
| 6462 | goto out; |
| 6463 | sblk->status &= ~SD_STATUS_UPDATED; |
Matt Carlson | 17375d2 | 2009-08-28 14:02:18 +0000 | [diff] [blame] | 6464 | if (likely(tg3_has_work(tnapi))) { |
Matt Carlson | 7233448 | 2009-08-28 14:03:01 +0000 | [diff] [blame] | 6465 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
Matt Carlson | 09943a1 | 2009-08-28 14:01:57 +0000 | [diff] [blame] | 6466 | napi_schedule(&tnapi->napi); |
Michael Chan | d18edcb | 2007-03-24 20:57:11 -0700 | [diff] [blame] | 6467 | } else { |
| 6468 | /* No work, shared interrupt perhaps? re-enable |
| 6469 | * interrupts, and flush that PCI write |
| 6470 | */ |
| 6471 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, |
| 6472 | 0x00000000); |
David S. Miller | fac9b83 | 2005-05-18 22:46:34 -0700 | [diff] [blame] | 6473 | } |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 6474 | out: |
David S. Miller | fac9b83 | 2005-05-18 22:46:34 -0700 | [diff] [blame] | 6475 | return IRQ_RETVAL(handled); |
| 6476 | } |
| 6477 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 6478 | static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) |
David S. Miller | fac9b83 | 2005-05-18 22:46:34 -0700 | [diff] [blame] | 6479 | { |
Matt Carlson | 09943a1 | 2009-08-28 14:01:57 +0000 | [diff] [blame] | 6480 | struct tg3_napi *tnapi = dev_id; |
| 6481 | struct tg3 *tp = tnapi->tp; |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 6482 | struct tg3_hw_status *sblk = tnapi->hw_status; |
David S. Miller | fac9b83 | 2005-05-18 22:46:34 -0700 | [diff] [blame] | 6483 | unsigned int handled = 1; |
| 6484 | |
David S. Miller | fac9b83 | 2005-05-18 22:46:34 -0700 | [diff] [blame] | 6485 | /* In INTx mode, it is possible for the interrupt to arrive at |
| 6486 | * the CPU before the status block posted prior to the interrupt. |
| 6487 | * Reading the PCI State register will confirm whether the |
| 6488 | * interrupt is ours and will flush the status block. |
| 6489 | */ |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 6490 | if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 6491 | if (tg3_flag(tp, CHIP_RESETTING) || |
Michael Chan | d18edcb | 2007-03-24 20:57:11 -0700 | [diff] [blame] | 6492 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { |
| 6493 | handled = 0; |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 6494 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6495 | } |
Michael Chan | d18edcb | 2007-03-24 20:57:11 -0700 | [diff] [blame] | 6496 | } |
| 6497 | |
| 6498 | /* |
| 6499 | * writing any value to intr-mbox-0 clears PCI INTA# and |
| 6500 | * chip-internal interrupt pending events. |
| 6501 | * writing non-zero to intr-mbox-0 additional tells the |
| 6502 | * NIC to stop sending us irqs, engaging "in-intr-handler" |
| 6503 | * event coalescing. |
Michael Chan | c04cb34 | 2007-05-07 00:26:15 -0700 | [diff] [blame] | 6504 | * |
| 6505 | * Flush the mailbox to de-assert the IRQ immediately to prevent |
| 6506 | * spurious interrupts. The flush impacts performance but |
| 6507 | * excessive spurious interrupts can be worse in some cases. |
Michael Chan | d18edcb | 2007-03-24 20:57:11 -0700 | [diff] [blame] | 6508 | */ |
Michael Chan | c04cb34 | 2007-05-07 00:26:15 -0700 | [diff] [blame] | 6509 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
Matt Carlson | 624f8e5 | 2009-04-20 06:55:01 +0000 | [diff] [blame] | 6510 | |
| 6511 | /* |
| 6512 | * In a shared interrupt configuration, sometimes other devices' |
| 6513 | * interrupts will scream. We record the current status tag here |
| 6514 | * so that the above check can report that the screaming interrupts |
| 6515 | * are unhandled. Eventually they will be silenced. |
| 6516 | */ |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 6517 | tnapi->last_irq_tag = sblk->status_tag; |
Matt Carlson | 624f8e5 | 2009-04-20 06:55:01 +0000 | [diff] [blame] | 6518 | |
Michael Chan | d18edcb | 2007-03-24 20:57:11 -0700 | [diff] [blame] | 6519 | if (tg3_irq_sync(tp)) |
| 6520 | goto out; |
Matt Carlson | 624f8e5 | 2009-04-20 06:55:01 +0000 | [diff] [blame] | 6521 | |
Matt Carlson | 7233448 | 2009-08-28 14:03:01 +0000 | [diff] [blame] | 6522 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
Matt Carlson | 624f8e5 | 2009-04-20 06:55:01 +0000 | [diff] [blame] | 6523 | |
Matt Carlson | 09943a1 | 2009-08-28 14:01:57 +0000 | [diff] [blame] | 6524 | napi_schedule(&tnapi->napi); |
Matt Carlson | 624f8e5 | 2009-04-20 06:55:01 +0000 | [diff] [blame] | 6525 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 6526 | out: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6527 | return IRQ_RETVAL(handled); |
| 6528 | } |
| 6529 | |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 6530 | /* ISR for interrupt test */ |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 6531 | static irqreturn_t tg3_test_isr(int irq, void *dev_id) |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 6532 | { |
Matt Carlson | 09943a1 | 2009-08-28 14:01:57 +0000 | [diff] [blame] | 6533 | struct tg3_napi *tnapi = dev_id; |
| 6534 | struct tg3 *tp = tnapi->tp; |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 6535 | struct tg3_hw_status *sblk = tnapi->hw_status; |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 6536 | |
Michael Chan | f9804dd | 2005-09-27 12:13:10 -0700 | [diff] [blame] | 6537 | if ((sblk->status & SD_STATUS_UPDATED) || |
| 6538 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 6539 | tg3_disable_ints(tp); |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 6540 | return IRQ_RETVAL(1); |
| 6541 | } |
| 6542 | return IRQ_RETVAL(0); |
| 6543 | } |
| 6544 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6545 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 6546 | static void tg3_poll_controller(struct net_device *dev) |
| 6547 | { |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 6548 | int i; |
Michael Chan | 88b06bc2 | 2005-04-21 17:13:25 -0700 | [diff] [blame] | 6549 | struct tg3 *tp = netdev_priv(dev); |
| 6550 | |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 6551 | for (i = 0; i < tp->irq_cnt; i++) |
Louis Rilling | fe234f0 | 2010-03-09 06:14:41 +0000 | [diff] [blame] | 6552 | tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6553 | } |
| 6554 | #endif |
| 6555 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6556 | static void tg3_tx_timeout(struct net_device *dev) |
| 6557 | { |
| 6558 | struct tg3 *tp = netdev_priv(dev); |
| 6559 | |
Michael Chan | b040875 | 2007-02-13 12:18:30 -0800 | [diff] [blame] | 6560 | if (netif_msg_tx_err(tp)) { |
Joe Perches | 05dbe00 | 2010-02-17 19:44:19 +0000 | [diff] [blame] | 6561 | netdev_err(dev, "transmit timed out, resetting\n"); |
Matt Carlson | 97bd8e4 | 2011-04-13 11:05:04 +0000 | [diff] [blame] | 6562 | tg3_dump_state(tp); |
Michael Chan | b040875 | 2007-02-13 12:18:30 -0800 | [diff] [blame] | 6563 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6564 | |
Matt Carlson | db21997 | 2011-11-04 09:15:03 +0000 | [diff] [blame] | 6565 | tg3_reset_task_schedule(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6566 | } |
| 6567 | |
Michael Chan | c58ec93 | 2005-09-17 00:46:27 -0700 | [diff] [blame] | 6568 | /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */ |
| 6569 | static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len) |
| 6570 | { |
| 6571 | u32 base = (u32) mapping & 0xffffffff; |
| 6572 | |
Eric Dumazet | 807540b | 2010-09-23 05:40:09 +0000 | [diff] [blame] | 6573 | return (base > 0xffffdcc0) && (base + len + 8 < base); |
Michael Chan | c58ec93 | 2005-09-17 00:46:27 -0700 | [diff] [blame] | 6574 | } |
| 6575 | |
Michael Chan | 72f2afb | 2006-03-06 19:28:35 -0800 | [diff] [blame] | 6576 | /* Test for DMA addresses > 40-bit */ |
| 6577 | static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, |
| 6578 | int len) |
| 6579 | { |
| 6580 | #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 6581 | if (tg3_flag(tp, 40BIT_DMA_BUG)) |
Eric Dumazet | 807540b | 2010-09-23 05:40:09 +0000 | [diff] [blame] | 6582 | return ((u64) mapping + len) > DMA_BIT_MASK(40); |
Michael Chan | 72f2afb | 2006-03-06 19:28:35 -0800 | [diff] [blame] | 6583 | return 0; |
| 6584 | #else |
| 6585 | return 0; |
| 6586 | #endif |
| 6587 | } |
| 6588 | |
Matt Carlson | d1a3b73 | 2011-07-27 14:20:51 +0000 | [diff] [blame] | 6589 | static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd, |
Matt Carlson | 92cd3a1 | 2011-07-27 14:20:47 +0000 | [diff] [blame] | 6590 | dma_addr_t mapping, u32 len, u32 flags, |
| 6591 | u32 mss, u32 vlan) |
Matt Carlson | 2ffcc98 | 2011-05-19 12:12:44 +0000 | [diff] [blame] | 6592 | { |
Matt Carlson | 92cd3a1 | 2011-07-27 14:20:47 +0000 | [diff] [blame] | 6593 | txbd->addr_hi = ((u64) mapping >> 32); |
| 6594 | txbd->addr_lo = ((u64) mapping & 0xffffffff); |
| 6595 | txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff); |
| 6596 | txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT); |
Matt Carlson | 2ffcc98 | 2011-05-19 12:12:44 +0000 | [diff] [blame] | 6597 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6598 | |
Matt Carlson | 84b67b2 | 2011-07-27 14:20:52 +0000 | [diff] [blame] | 6599 | static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget, |
Matt Carlson | d1a3b73 | 2011-07-27 14:20:51 +0000 | [diff] [blame] | 6600 | dma_addr_t map, u32 len, u32 flags, |
| 6601 | u32 mss, u32 vlan) |
| 6602 | { |
| 6603 | struct tg3 *tp = tnapi->tp; |
| 6604 | bool hwbug = false; |
| 6605 | |
| 6606 | if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8) |
Rusty Russell | 3db1cd5 | 2011-12-19 13:56:45 +0000 | [diff] [blame] | 6607 | hwbug = true; |
Matt Carlson | d1a3b73 | 2011-07-27 14:20:51 +0000 | [diff] [blame] | 6608 | |
| 6609 | if (tg3_4g_overflow_test(map, len)) |
Rusty Russell | 3db1cd5 | 2011-12-19 13:56:45 +0000 | [diff] [blame] | 6610 | hwbug = true; |
Matt Carlson | d1a3b73 | 2011-07-27 14:20:51 +0000 | [diff] [blame] | 6611 | |
| 6612 | if (tg3_40bit_overflow_test(tp, map, len)) |
Rusty Russell | 3db1cd5 | 2011-12-19 13:56:45 +0000 | [diff] [blame] | 6613 | hwbug = true; |
Matt Carlson | d1a3b73 | 2011-07-27 14:20:51 +0000 | [diff] [blame] | 6614 | |
Matt Carlson | a4cb428 | 2011-12-14 11:09:58 +0000 | [diff] [blame] | 6615 | if (tp->dma_limit) { |
Matt Carlson | b9e4548 | 2011-11-04 09:14:59 +0000 | [diff] [blame] | 6616 | u32 prvidx = *entry; |
Matt Carlson | e31aa98 | 2011-07-27 14:20:53 +0000 | [diff] [blame] | 6617 | u32 tmp_flag = flags & ~TXD_FLAG_END; |
Matt Carlson | a4cb428 | 2011-12-14 11:09:58 +0000 | [diff] [blame] | 6618 | while (len > tp->dma_limit && *budget) { |
| 6619 | u32 frag_len = tp->dma_limit; |
| 6620 | len -= tp->dma_limit; |
Matt Carlson | e31aa98 | 2011-07-27 14:20:53 +0000 | [diff] [blame] | 6621 | |
Matt Carlson | b9e4548 | 2011-11-04 09:14:59 +0000 | [diff] [blame] | 6622 | /* Avoid the 8byte DMA problem */ |
| 6623 | if (len <= 8) { |
Matt Carlson | a4cb428 | 2011-12-14 11:09:58 +0000 | [diff] [blame] | 6624 | len += tp->dma_limit / 2; |
| 6625 | frag_len = tp->dma_limit / 2; |
Matt Carlson | e31aa98 | 2011-07-27 14:20:53 +0000 | [diff] [blame] | 6626 | } |
| 6627 | |
Matt Carlson | b9e4548 | 2011-11-04 09:14:59 +0000 | [diff] [blame] | 6628 | tnapi->tx_buffers[*entry].fragmented = true; |
| 6629 | |
| 6630 | tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, |
| 6631 | frag_len, tmp_flag, mss, vlan); |
| 6632 | *budget -= 1; |
| 6633 | prvidx = *entry; |
| 6634 | *entry = NEXT_TX(*entry); |
| 6635 | |
Matt Carlson | e31aa98 | 2011-07-27 14:20:53 +0000 | [diff] [blame] | 6636 | map += frag_len; |
| 6637 | } |
| 6638 | |
| 6639 | if (len) { |
| 6640 | if (*budget) { |
| 6641 | tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, |
| 6642 | len, flags, mss, vlan); |
Matt Carlson | b9e4548 | 2011-11-04 09:14:59 +0000 | [diff] [blame] | 6643 | *budget -= 1; |
Matt Carlson | e31aa98 | 2011-07-27 14:20:53 +0000 | [diff] [blame] | 6644 | *entry = NEXT_TX(*entry); |
| 6645 | } else { |
Rusty Russell | 3db1cd5 | 2011-12-19 13:56:45 +0000 | [diff] [blame] | 6646 | hwbug = true; |
Matt Carlson | b9e4548 | 2011-11-04 09:14:59 +0000 | [diff] [blame] | 6647 | tnapi->tx_buffers[prvidx].fragmented = false; |
Matt Carlson | e31aa98 | 2011-07-27 14:20:53 +0000 | [diff] [blame] | 6648 | } |
| 6649 | } |
| 6650 | } else { |
Matt Carlson | 84b67b2 | 2011-07-27 14:20:52 +0000 | [diff] [blame] | 6651 | tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, |
| 6652 | len, flags, mss, vlan); |
Matt Carlson | e31aa98 | 2011-07-27 14:20:53 +0000 | [diff] [blame] | 6653 | *entry = NEXT_TX(*entry); |
| 6654 | } |
Matt Carlson | d1a3b73 | 2011-07-27 14:20:51 +0000 | [diff] [blame] | 6655 | |
| 6656 | return hwbug; |
| 6657 | } |
| 6658 | |
Matt Carlson | 0d681b2 | 2011-07-27 14:20:49 +0000 | [diff] [blame] | 6659 | static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last) |
Matt Carlson | 432aa7e | 2011-05-19 12:12:45 +0000 | [diff] [blame] | 6660 | { |
| 6661 | int i; |
Matt Carlson | 0d681b2 | 2011-07-27 14:20:49 +0000 | [diff] [blame] | 6662 | struct sk_buff *skb; |
Matt Carlson | df8944c | 2011-07-27 14:20:46 +0000 | [diff] [blame] | 6663 | struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry]; |
Matt Carlson | 432aa7e | 2011-05-19 12:12:45 +0000 | [diff] [blame] | 6664 | |
Matt Carlson | 0d681b2 | 2011-07-27 14:20:49 +0000 | [diff] [blame] | 6665 | skb = txb->skb; |
| 6666 | txb->skb = NULL; |
| 6667 | |
Matt Carlson | 432aa7e | 2011-05-19 12:12:45 +0000 | [diff] [blame] | 6668 | pci_unmap_single(tnapi->tp->pdev, |
| 6669 | dma_unmap_addr(txb, mapping), |
| 6670 | skb_headlen(skb), |
| 6671 | PCI_DMA_TODEVICE); |
Matt Carlson | e01ee14 | 2011-07-27 14:20:50 +0000 | [diff] [blame] | 6672 | |
| 6673 | while (txb->fragmented) { |
| 6674 | txb->fragmented = false; |
| 6675 | entry = NEXT_TX(entry); |
| 6676 | txb = &tnapi->tx_buffers[entry]; |
| 6677 | } |
| 6678 | |
Matt Carlson | ba1142e | 2011-11-04 09:15:00 +0000 | [diff] [blame] | 6679 | for (i = 0; i <= last; i++) { |
Eric Dumazet | 9e903e0 | 2011-10-18 21:00:24 +0000 | [diff] [blame] | 6680 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
Matt Carlson | 432aa7e | 2011-05-19 12:12:45 +0000 | [diff] [blame] | 6681 | |
| 6682 | entry = NEXT_TX(entry); |
| 6683 | txb = &tnapi->tx_buffers[entry]; |
| 6684 | |
| 6685 | pci_unmap_page(tnapi->tp->pdev, |
| 6686 | dma_unmap_addr(txb, mapping), |
Eric Dumazet | 9e903e0 | 2011-10-18 21:00:24 +0000 | [diff] [blame] | 6687 | skb_frag_size(frag), PCI_DMA_TODEVICE); |
Matt Carlson | e01ee14 | 2011-07-27 14:20:50 +0000 | [diff] [blame] | 6688 | |
| 6689 | while (txb->fragmented) { |
| 6690 | txb->fragmented = false; |
| 6691 | entry = NEXT_TX(entry); |
| 6692 | txb = &tnapi->tx_buffers[entry]; |
| 6693 | } |
Matt Carlson | 432aa7e | 2011-05-19 12:12:45 +0000 | [diff] [blame] | 6694 | } |
| 6695 | } |
| 6696 | |
Michael Chan | 72f2afb | 2006-03-06 19:28:35 -0800 | [diff] [blame] | 6697 | /* Workaround 4GB and 40-bit hardware DMA bugs. */ |
Matt Carlson | 24f4efd | 2009-11-13 13:03:35 +0000 | [diff] [blame] | 6698 | static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi, |
David S. Miller | 1805b2f | 2011-10-24 18:18:09 -0400 | [diff] [blame] | 6699 | struct sk_buff **pskb, |
Matt Carlson | 84b67b2 | 2011-07-27 14:20:52 +0000 | [diff] [blame] | 6700 | u32 *entry, u32 *budget, |
Matt Carlson | 92cd3a1 | 2011-07-27 14:20:47 +0000 | [diff] [blame] | 6701 | u32 base_flags, u32 mss, u32 vlan) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6702 | { |
Matt Carlson | 24f4efd | 2009-11-13 13:03:35 +0000 | [diff] [blame] | 6703 | struct tg3 *tp = tnapi->tp; |
David S. Miller | 1805b2f | 2011-10-24 18:18:09 -0400 | [diff] [blame] | 6704 | struct sk_buff *new_skb, *skb = *pskb; |
Michael Chan | c58ec93 | 2005-09-17 00:46:27 -0700 | [diff] [blame] | 6705 | dma_addr_t new_addr = 0; |
Matt Carlson | 432aa7e | 2011-05-19 12:12:45 +0000 | [diff] [blame] | 6706 | int ret = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6707 | |
Matt Carlson | 41588ba | 2008-04-19 18:12:33 -0700 | [diff] [blame] | 6708 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) |
| 6709 | new_skb = skb_copy(skb, GFP_ATOMIC); |
| 6710 | else { |
| 6711 | int more_headroom = 4 - ((unsigned long)skb->data & 3); |
| 6712 | |
| 6713 | new_skb = skb_copy_expand(skb, |
| 6714 | skb_headroom(skb) + more_headroom, |
| 6715 | skb_tailroom(skb), GFP_ATOMIC); |
| 6716 | } |
| 6717 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6718 | if (!new_skb) { |
Michael Chan | c58ec93 | 2005-09-17 00:46:27 -0700 | [diff] [blame] | 6719 | ret = -1; |
| 6720 | } else { |
| 6721 | /* New SKB is guaranteed to be linear. */ |
Alexander Duyck | f4188d8 | 2009-12-02 16:48:38 +0000 | [diff] [blame] | 6722 | new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, |
| 6723 | PCI_DMA_TODEVICE); |
| 6724 | /* Make sure the mapping succeeded */ |
| 6725 | if (pci_dma_mapping_error(tp->pdev, new_addr)) { |
Alexander Duyck | f4188d8 | 2009-12-02 16:48:38 +0000 | [diff] [blame] | 6726 | dev_kfree_skb(new_skb); |
Michael Chan | c58ec93 | 2005-09-17 00:46:27 -0700 | [diff] [blame] | 6727 | ret = -1; |
Michael Chan | c58ec93 | 2005-09-17 00:46:27 -0700 | [diff] [blame] | 6728 | } else { |
Matt Carlson | b9e4548 | 2011-11-04 09:14:59 +0000 | [diff] [blame] | 6729 | u32 save_entry = *entry; |
| 6730 | |
Matt Carlson | 92cd3a1 | 2011-07-27 14:20:47 +0000 | [diff] [blame] | 6731 | base_flags |= TXD_FLAG_END; |
| 6732 | |
Matt Carlson | 84b67b2 | 2011-07-27 14:20:52 +0000 | [diff] [blame] | 6733 | tnapi->tx_buffers[*entry].skb = new_skb; |
| 6734 | dma_unmap_addr_set(&tnapi->tx_buffers[*entry], |
Matt Carlson | 432aa7e | 2011-05-19 12:12:45 +0000 | [diff] [blame] | 6735 | mapping, new_addr); |
| 6736 | |
Matt Carlson | 84b67b2 | 2011-07-27 14:20:52 +0000 | [diff] [blame] | 6737 | if (tg3_tx_frag_set(tnapi, entry, budget, new_addr, |
Matt Carlson | d1a3b73 | 2011-07-27 14:20:51 +0000 | [diff] [blame] | 6738 | new_skb->len, base_flags, |
| 6739 | mss, vlan)) { |
Matt Carlson | ba1142e | 2011-11-04 09:15:00 +0000 | [diff] [blame] | 6740 | tg3_tx_skb_unmap(tnapi, save_entry, -1); |
Matt Carlson | d1a3b73 | 2011-07-27 14:20:51 +0000 | [diff] [blame] | 6741 | dev_kfree_skb(new_skb); |
| 6742 | ret = -1; |
| 6743 | } |
Michael Chan | c58ec93 | 2005-09-17 00:46:27 -0700 | [diff] [blame] | 6744 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6745 | } |
| 6746 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6747 | dev_kfree_skb(skb); |
David S. Miller | 1805b2f | 2011-10-24 18:18:09 -0400 | [diff] [blame] | 6748 | *pskb = new_skb; |
Michael Chan | c58ec93 | 2005-09-17 00:46:27 -0700 | [diff] [blame] | 6749 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6750 | } |
| 6751 | |
Matt Carlson | 2ffcc98 | 2011-05-19 12:12:44 +0000 | [diff] [blame] | 6752 | static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *); |
Michael Chan | 52c0fd8 | 2006-06-29 20:15:54 -0700 | [diff] [blame] | 6753 | |
| 6754 | /* Use GSO to workaround a rare TSO bug that may be triggered when the |
| 6755 | * TSO header is greater than 80 bytes. |
| 6756 | */ |
| 6757 | static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb) |
| 6758 | { |
| 6759 | struct sk_buff *segs, *nskb; |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 6760 | u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; |
Michael Chan | 52c0fd8 | 2006-06-29 20:15:54 -0700 | [diff] [blame] | 6761 | |
| 6762 | /* Estimate the number of fragments in the worst case */ |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 6763 | if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) { |
Michael Chan | 52c0fd8 | 2006-06-29 20:15:54 -0700 | [diff] [blame] | 6764 | netif_stop_queue(tp->dev); |
Matt Carlson | f65aac1 | 2010-08-02 11:26:03 +0000 | [diff] [blame] | 6765 | |
| 6766 | /* netif_tx_stop_queue() must be done before checking |
| 6767 | * checking tx index in tg3_tx_avail() below, because in |
| 6768 | * tg3_tx(), we update tx index before checking for |
| 6769 | * netif_tx_queue_stopped(). |
| 6770 | */ |
| 6771 | smp_mb(); |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 6772 | if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est) |
Michael Chan | 7f62ad5 | 2007-02-20 23:25:40 -0800 | [diff] [blame] | 6773 | return NETDEV_TX_BUSY; |
| 6774 | |
| 6775 | netif_wake_queue(tp->dev); |
Michael Chan | 52c0fd8 | 2006-06-29 20:15:54 -0700 | [diff] [blame] | 6776 | } |
| 6777 | |
| 6778 | segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO); |
Hirofumi Nakagawa | 801678c | 2008-04-29 01:03:09 -0700 | [diff] [blame] | 6779 | if (IS_ERR(segs)) |
Michael Chan | 52c0fd8 | 2006-06-29 20:15:54 -0700 | [diff] [blame] | 6780 | goto tg3_tso_bug_end; |
| 6781 | |
| 6782 | do { |
| 6783 | nskb = segs; |
| 6784 | segs = segs->next; |
| 6785 | nskb->next = NULL; |
Matt Carlson | 2ffcc98 | 2011-05-19 12:12:44 +0000 | [diff] [blame] | 6786 | tg3_start_xmit(nskb, tp->dev); |
Michael Chan | 52c0fd8 | 2006-06-29 20:15:54 -0700 | [diff] [blame] | 6787 | } while (segs); |
| 6788 | |
| 6789 | tg3_tso_bug_end: |
| 6790 | dev_kfree_skb(skb); |
| 6791 | |
| 6792 | return NETDEV_TX_OK; |
| 6793 | } |
Michael Chan | 52c0fd8 | 2006-06-29 20:15:54 -0700 | [diff] [blame] | 6794 | |
Michael Chan | 5a6f307 | 2006-03-20 22:28:05 -0800 | [diff] [blame] | 6795 | /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 6796 | * support TG3_FLAG_HW_TSO_1 or firmware TSO only. |
Michael Chan | 5a6f307 | 2006-03-20 22:28:05 -0800 | [diff] [blame] | 6797 | */ |
Matt Carlson | 2ffcc98 | 2011-05-19 12:12:44 +0000 | [diff] [blame] | 6798 | static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev) |
Michael Chan | 5a6f307 | 2006-03-20 22:28:05 -0800 | [diff] [blame] | 6799 | { |
| 6800 | struct tg3 *tp = netdev_priv(dev); |
Matt Carlson | 92cd3a1 | 2011-07-27 14:20:47 +0000 | [diff] [blame] | 6801 | u32 len, entry, base_flags, mss, vlan = 0; |
Matt Carlson | 84b67b2 | 2011-07-27 14:20:52 +0000 | [diff] [blame] | 6802 | u32 budget; |
Matt Carlson | 432aa7e | 2011-05-19 12:12:45 +0000 | [diff] [blame] | 6803 | int i = -1, would_hit_hwbug; |
David S. Miller | 90079ce | 2008-09-11 04:52:51 -0700 | [diff] [blame] | 6804 | dma_addr_t mapping; |
Matt Carlson | 24f4efd | 2009-11-13 13:03:35 +0000 | [diff] [blame] | 6805 | struct tg3_napi *tnapi; |
| 6806 | struct netdev_queue *txq; |
Matt Carlson | 432aa7e | 2011-05-19 12:12:45 +0000 | [diff] [blame] | 6807 | unsigned int last; |
Alexander Duyck | f4188d8 | 2009-12-02 16:48:38 +0000 | [diff] [blame] | 6808 | |
Matt Carlson | 24f4efd | 2009-11-13 13:03:35 +0000 | [diff] [blame] | 6809 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); |
| 6810 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 6811 | if (tg3_flag(tp, ENABLE_TSS)) |
Matt Carlson | 24f4efd | 2009-11-13 13:03:35 +0000 | [diff] [blame] | 6812 | tnapi++; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6813 | |
Matt Carlson | 84b67b2 | 2011-07-27 14:20:52 +0000 | [diff] [blame] | 6814 | budget = tg3_tx_avail(tnapi); |
| 6815 | |
Michael Chan | 00b7050 | 2006-06-17 21:58:45 -0700 | [diff] [blame] | 6816 | /* We are running in BH disabled context with netif_tx_lock |
Stephen Hemminger | bea3348 | 2007-10-03 16:41:36 -0700 | [diff] [blame] | 6817 | * and TX reclaim runs via tp->napi.poll inside of a software |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 6818 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
| 6819 | * no IRQ context deadlocks to worry about either. Rejoice! |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6820 | */ |
Matt Carlson | 84b67b2 | 2011-07-27 14:20:52 +0000 | [diff] [blame] | 6821 | if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) { |
Matt Carlson | 24f4efd | 2009-11-13 13:03:35 +0000 | [diff] [blame] | 6822 | if (!netif_tx_queue_stopped(txq)) { |
| 6823 | netif_tx_stop_queue(txq); |
Stephen Hemminger | 1f064a8 | 2005-12-06 17:36:44 -0800 | [diff] [blame] | 6824 | |
| 6825 | /* This is a hard error, log it. */ |
Matt Carlson | 5129c3a | 2010-04-05 10:19:23 +0000 | [diff] [blame] | 6826 | netdev_err(dev, |
| 6827 | "BUG! Tx Ring full when queue awake!\n"); |
Stephen Hemminger | 1f064a8 | 2005-12-06 17:36:44 -0800 | [diff] [blame] | 6828 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6829 | return NETDEV_TX_BUSY; |
| 6830 | } |
| 6831 | |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 6832 | entry = tnapi->tx_prod; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6833 | base_flags = 0; |
Patrick McHardy | 84fa793 | 2006-08-29 16:44:56 -0700 | [diff] [blame] | 6834 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6835 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
Matt Carlson | 24f4efd | 2009-11-13 13:03:35 +0000 | [diff] [blame] | 6836 | |
Matt Carlson | be98da6 | 2010-07-11 09:31:46 +0000 | [diff] [blame] | 6837 | mss = skb_shinfo(skb)->gso_size; |
| 6838 | if (mss) { |
Arnaldo Carvalho de Melo | eddc9ec | 2007-04-20 22:47:35 -0700 | [diff] [blame] | 6839 | struct iphdr *iph; |
Matt Carlson | 34195c3 | 2010-07-11 09:31:42 +0000 | [diff] [blame] | 6840 | u32 tcp_opt_len, hdr_len; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6841 | |
| 6842 | if (skb_header_cloned(skb) && |
Eric Dumazet | 4885543 | 2011-10-24 07:53:03 +0000 | [diff] [blame] | 6843 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) |
| 6844 | goto drop; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6845 | |
Matt Carlson | 34195c3 | 2010-07-11 09:31:42 +0000 | [diff] [blame] | 6846 | iph = ip_hdr(skb); |
Arnaldo Carvalho de Melo | ab6a5bb | 2007-03-18 17:43:48 -0700 | [diff] [blame] | 6847 | tcp_opt_len = tcp_optlen(skb); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6848 | |
Eric Dumazet | a5a1195 | 2012-01-23 01:22:09 +0000 | [diff] [blame] | 6849 | hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN; |
Matt Carlson | 34195c3 | 2010-07-11 09:31:42 +0000 | [diff] [blame] | 6850 | |
Eric Dumazet | a5a1195 | 2012-01-23 01:22:09 +0000 | [diff] [blame] | 6851 | if (!skb_is_gso_v6(skb)) { |
Matt Carlson | 34195c3 | 2010-07-11 09:31:42 +0000 | [diff] [blame] | 6852 | iph->check = 0; |
| 6853 | iph->tot_len = htons(mss + hdr_len); |
| 6854 | } |
| 6855 | |
Michael Chan | 52c0fd8 | 2006-06-29 20:15:54 -0700 | [diff] [blame] | 6856 | if (unlikely((ETH_HLEN + hdr_len) > 80) && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 6857 | tg3_flag(tp, TSO_BUG)) |
Matt Carlson | de6f31e | 2010-04-12 06:58:30 +0000 | [diff] [blame] | 6858 | return tg3_tso_bug(tp, skb); |
Michael Chan | 52c0fd8 | 2006-06-29 20:15:54 -0700 | [diff] [blame] | 6859 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6860 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
| 6861 | TXD_FLAG_CPU_POST_DMA); |
| 6862 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 6863 | if (tg3_flag(tp, HW_TSO_1) || |
| 6864 | tg3_flag(tp, HW_TSO_2) || |
| 6865 | tg3_flag(tp, HW_TSO_3)) { |
Arnaldo Carvalho de Melo | aa8223c | 2007-04-10 21:04:22 -0700 | [diff] [blame] | 6866 | tcp_hdr(skb)->check = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6867 | base_flags &= ~TXD_FLAG_TCPUDP_CSUM; |
Arnaldo Carvalho de Melo | aa8223c | 2007-04-10 21:04:22 -0700 | [diff] [blame] | 6868 | } else |
| 6869 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, |
| 6870 | iph->daddr, 0, |
| 6871 | IPPROTO_TCP, |
| 6872 | 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6873 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 6874 | if (tg3_flag(tp, HW_TSO_3)) { |
Matt Carlson | 615774f | 2009-11-13 13:03:39 +0000 | [diff] [blame] | 6875 | mss |= (hdr_len & 0xc) << 12; |
| 6876 | if (hdr_len & 0x10) |
| 6877 | base_flags |= 0x00000010; |
| 6878 | base_flags |= (hdr_len & 0x3e0) << 5; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 6879 | } else if (tg3_flag(tp, HW_TSO_2)) |
Matt Carlson | 92c6b8d | 2009-11-02 14:23:27 +0000 | [diff] [blame] | 6880 | mss |= hdr_len << 9; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 6881 | else if (tg3_flag(tp, HW_TSO_1) || |
Matt Carlson | 92c6b8d | 2009-11-02 14:23:27 +0000 | [diff] [blame] | 6882 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
Arnaldo Carvalho de Melo | eddc9ec | 2007-04-20 22:47:35 -0700 | [diff] [blame] | 6883 | if (tcp_opt_len || iph->ihl > 5) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6884 | int tsflags; |
| 6885 | |
Arnaldo Carvalho de Melo | eddc9ec | 2007-04-20 22:47:35 -0700 | [diff] [blame] | 6886 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6887 | mss |= (tsflags << 11); |
| 6888 | } |
| 6889 | } else { |
Arnaldo Carvalho de Melo | eddc9ec | 2007-04-20 22:47:35 -0700 | [diff] [blame] | 6890 | if (tcp_opt_len || iph->ihl > 5) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6891 | int tsflags; |
| 6892 | |
Arnaldo Carvalho de Melo | eddc9ec | 2007-04-20 22:47:35 -0700 | [diff] [blame] | 6893 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6894 | base_flags |= tsflags << 12; |
| 6895 | } |
| 6896 | } |
| 6897 | } |
Matt Carlson | bf933c8 | 2011-01-25 15:58:49 +0000 | [diff] [blame] | 6898 | |
Matt Carlson | 93a700a | 2011-08-31 11:44:54 +0000 | [diff] [blame] | 6899 | if (tg3_flag(tp, USE_JUMBO_BDFLAG) && |
| 6900 | !mss && skb->len > VLAN_ETH_FRAME_LEN) |
| 6901 | base_flags |= TXD_FLAG_JMB_PKT; |
| 6902 | |
Matt Carlson | 92cd3a1 | 2011-07-27 14:20:47 +0000 | [diff] [blame] | 6903 | if (vlan_tx_tag_present(skb)) { |
| 6904 | base_flags |= TXD_FLAG_VLAN; |
| 6905 | vlan = vlan_tx_tag_get(skb); |
| 6906 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6907 | |
Alexander Duyck | f4188d8 | 2009-12-02 16:48:38 +0000 | [diff] [blame] | 6908 | len = skb_headlen(skb); |
| 6909 | |
| 6910 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); |
Eric Dumazet | 4885543 | 2011-10-24 07:53:03 +0000 | [diff] [blame] | 6911 | if (pci_dma_mapping_error(tp->pdev, mapping)) |
| 6912 | goto drop; |
| 6913 | |
David S. Miller | 90079ce | 2008-09-11 04:52:51 -0700 | [diff] [blame] | 6914 | |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 6915 | tnapi->tx_buffers[entry].skb = skb; |
FUJITA Tomonori | 4e5e4f0 | 2010-04-12 14:32:09 +0000 | [diff] [blame] | 6916 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6917 | |
| 6918 | would_hit_hwbug = 0; |
| 6919 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 6920 | if (tg3_flag(tp, 5701_DMA_BUG)) |
Michael Chan | c58ec93 | 2005-09-17 00:46:27 -0700 | [diff] [blame] | 6921 | would_hit_hwbug = 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6922 | |
Matt Carlson | 84b67b2 | 2011-07-27 14:20:52 +0000 | [diff] [blame] | 6923 | if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags | |
Matt Carlson | d1a3b73 | 2011-07-27 14:20:51 +0000 | [diff] [blame] | 6924 | ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0), |
Matt Carlson | ba1142e | 2011-11-04 09:15:00 +0000 | [diff] [blame] | 6925 | mss, vlan)) { |
Matt Carlson | d1a3b73 | 2011-07-27 14:20:51 +0000 | [diff] [blame] | 6926 | would_hit_hwbug = 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6927 | /* Now loop through additional data fragments, and queue them. */ |
Matt Carlson | ba1142e | 2011-11-04 09:15:00 +0000 | [diff] [blame] | 6928 | } else if (skb_shinfo(skb)->nr_frags > 0) { |
Matt Carlson | 92cd3a1 | 2011-07-27 14:20:47 +0000 | [diff] [blame] | 6929 | u32 tmp_mss = mss; |
| 6930 | |
| 6931 | if (!tg3_flag(tp, HW_TSO_1) && |
| 6932 | !tg3_flag(tp, HW_TSO_2) && |
| 6933 | !tg3_flag(tp, HW_TSO_3)) |
| 6934 | tmp_mss = 0; |
| 6935 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6936 | last = skb_shinfo(skb)->nr_frags - 1; |
| 6937 | for (i = 0; i <= last; i++) { |
| 6938 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
| 6939 | |
Eric Dumazet | 9e903e0 | 2011-10-18 21:00:24 +0000 | [diff] [blame] | 6940 | len = skb_frag_size(frag); |
Ian Campbell | dc234d0 | 2011-08-24 22:28:11 +0000 | [diff] [blame] | 6941 | mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0, |
Ian Campbell | 5d6bcdf | 2011-10-06 11:10:48 +0100 | [diff] [blame] | 6942 | len, DMA_TO_DEVICE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6943 | |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 6944 | tnapi->tx_buffers[entry].skb = NULL; |
FUJITA Tomonori | 4e5e4f0 | 2010-04-12 14:32:09 +0000 | [diff] [blame] | 6945 | dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
Alexander Duyck | f4188d8 | 2009-12-02 16:48:38 +0000 | [diff] [blame] | 6946 | mapping); |
Ian Campbell | 5d6bcdf | 2011-10-06 11:10:48 +0100 | [diff] [blame] | 6947 | if (dma_mapping_error(&tp->pdev->dev, mapping)) |
Alexander Duyck | f4188d8 | 2009-12-02 16:48:38 +0000 | [diff] [blame] | 6948 | goto dma_error; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6949 | |
Matt Carlson | b9e4548 | 2011-11-04 09:14:59 +0000 | [diff] [blame] | 6950 | if (!budget || |
| 6951 | tg3_tx_frag_set(tnapi, &entry, &budget, mapping, |
Matt Carlson | 84b67b2 | 2011-07-27 14:20:52 +0000 | [diff] [blame] | 6952 | len, base_flags | |
| 6953 | ((i == last) ? TXD_FLAG_END : 0), |
Matt Carlson | b9e4548 | 2011-11-04 09:14:59 +0000 | [diff] [blame] | 6954 | tmp_mss, vlan)) { |
Matt Carlson | 92c6b8d | 2009-11-02 14:23:27 +0000 | [diff] [blame] | 6955 | would_hit_hwbug = 1; |
Matt Carlson | b9e4548 | 2011-11-04 09:14:59 +0000 | [diff] [blame] | 6956 | break; |
| 6957 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6958 | } |
| 6959 | } |
| 6960 | |
| 6961 | if (would_hit_hwbug) { |
Matt Carlson | 0d681b2 | 2011-07-27 14:20:49 +0000 | [diff] [blame] | 6962 | tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6963 | |
| 6964 | /* If the workaround fails due to memory/mapping |
| 6965 | * failure, silently drop this packet. |
| 6966 | */ |
Matt Carlson | 84b67b2 | 2011-07-27 14:20:52 +0000 | [diff] [blame] | 6967 | entry = tnapi->tx_prod; |
| 6968 | budget = tg3_tx_avail(tnapi); |
David S. Miller | 1805b2f | 2011-10-24 18:18:09 -0400 | [diff] [blame] | 6969 | if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget, |
Matt Carlson | 84b67b2 | 2011-07-27 14:20:52 +0000 | [diff] [blame] | 6970 | base_flags, mss, vlan)) |
Eric Dumazet | 4885543 | 2011-10-24 07:53:03 +0000 | [diff] [blame] | 6971 | goto drop_nofree; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6972 | } |
| 6973 | |
Richard Cochran | d515b45 | 2011-06-19 03:31:41 +0000 | [diff] [blame] | 6974 | skb_tx_timestamp(skb); |
Tom Herbert | 298376d | 2011-11-28 16:33:30 +0000 | [diff] [blame] | 6975 | netdev_sent_queue(tp->dev, skb->len); |
Richard Cochran | d515b45 | 2011-06-19 03:31:41 +0000 | [diff] [blame] | 6976 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6977 | /* Packets are ready, update Tx producer idx local and on card. */ |
Matt Carlson | 24f4efd | 2009-11-13 13:03:35 +0000 | [diff] [blame] | 6978 | tw32_tx_mbox(tnapi->prodmbox, entry); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6979 | |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 6980 | tnapi->tx_prod = entry; |
| 6981 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { |
Matt Carlson | 24f4efd | 2009-11-13 13:03:35 +0000 | [diff] [blame] | 6982 | netif_tx_stop_queue(txq); |
Matt Carlson | f65aac1 | 2010-08-02 11:26:03 +0000 | [diff] [blame] | 6983 | |
| 6984 | /* netif_tx_stop_queue() must be done before checking |
| 6985 | * checking tx index in tg3_tx_avail() below, because in |
| 6986 | * tg3_tx(), we update tx index before checking for |
| 6987 | * netif_tx_queue_stopped(). |
| 6988 | */ |
| 6989 | smp_mb(); |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 6990 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
Matt Carlson | 24f4efd | 2009-11-13 13:03:35 +0000 | [diff] [blame] | 6991 | netif_tx_wake_queue(txq); |
Michael Chan | 51b9146 | 2005-09-01 17:41:28 -0700 | [diff] [blame] | 6992 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6993 | |
Eric Dumazet | cdd0db0 | 2009-05-28 00:00:41 +0000 | [diff] [blame] | 6994 | mmiowb(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6995 | return NETDEV_TX_OK; |
Alexander Duyck | f4188d8 | 2009-12-02 16:48:38 +0000 | [diff] [blame] | 6996 | |
| 6997 | dma_error: |
Matt Carlson | ba1142e | 2011-11-04 09:15:00 +0000 | [diff] [blame] | 6998 | tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i); |
Matt Carlson | 432aa7e | 2011-05-19 12:12:45 +0000 | [diff] [blame] | 6999 | tnapi->tx_buffers[tnapi->tx_prod].skb = NULL; |
Eric Dumazet | 4885543 | 2011-10-24 07:53:03 +0000 | [diff] [blame] | 7000 | drop: |
| 7001 | dev_kfree_skb(skb); |
| 7002 | drop_nofree: |
| 7003 | tp->tx_dropped++; |
Alexander Duyck | f4188d8 | 2009-12-02 16:48:38 +0000 | [diff] [blame] | 7004 | return NETDEV_TX_OK; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7005 | } |
| 7006 | |
Matt Carlson | 6e01b20 | 2011-08-19 13:58:20 +0000 | [diff] [blame] | 7007 | static void tg3_mac_loopback(struct tg3 *tp, bool enable) |
| 7008 | { |
| 7009 | if (enable) { |
| 7010 | tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX | |
| 7011 | MAC_MODE_PORT_MODE_MASK); |
| 7012 | |
| 7013 | tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; |
| 7014 | |
| 7015 | if (!tg3_flag(tp, 5705_PLUS)) |
| 7016 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
| 7017 | |
| 7018 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) |
| 7019 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; |
| 7020 | else |
| 7021 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
| 7022 | } else { |
| 7023 | tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; |
| 7024 | |
| 7025 | if (tg3_flag(tp, 5705_PLUS) || |
| 7026 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || |
| 7027 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) |
| 7028 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; |
| 7029 | } |
| 7030 | |
| 7031 | tw32(MAC_MODE, tp->mac_mode); |
| 7032 | udelay(40); |
| 7033 | } |
| 7034 | |
Matt Carlson | 941ec90 | 2011-08-19 13:58:23 +0000 | [diff] [blame] | 7035 | static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk) |
Matt Carlson | 5e5a7f3 | 2011-08-19 13:58:21 +0000 | [diff] [blame] | 7036 | { |
Matt Carlson | 941ec90 | 2011-08-19 13:58:23 +0000 | [diff] [blame] | 7037 | u32 val, bmcr, mac_mode, ptest = 0; |
Matt Carlson | 5e5a7f3 | 2011-08-19 13:58:21 +0000 | [diff] [blame] | 7038 | |
| 7039 | tg3_phy_toggle_apd(tp, false); |
| 7040 | tg3_phy_toggle_automdix(tp, 0); |
| 7041 | |
Matt Carlson | 941ec90 | 2011-08-19 13:58:23 +0000 | [diff] [blame] | 7042 | if (extlpbk && tg3_phy_set_extloopbk(tp)) |
| 7043 | return -EIO; |
| 7044 | |
| 7045 | bmcr = BMCR_FULLDPLX; |
Matt Carlson | 5e5a7f3 | 2011-08-19 13:58:21 +0000 | [diff] [blame] | 7046 | switch (speed) { |
| 7047 | case SPEED_10: |
| 7048 | break; |
| 7049 | case SPEED_100: |
| 7050 | bmcr |= BMCR_SPEED100; |
| 7051 | break; |
| 7052 | case SPEED_1000: |
| 7053 | default: |
| 7054 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) { |
| 7055 | speed = SPEED_100; |
| 7056 | bmcr |= BMCR_SPEED100; |
| 7057 | } else { |
| 7058 | speed = SPEED_1000; |
| 7059 | bmcr |= BMCR_SPEED1000; |
| 7060 | } |
| 7061 | } |
| 7062 | |
Matt Carlson | 941ec90 | 2011-08-19 13:58:23 +0000 | [diff] [blame] | 7063 | if (extlpbk) { |
| 7064 | if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) { |
| 7065 | tg3_readphy(tp, MII_CTRL1000, &val); |
| 7066 | val |= CTL1000_AS_MASTER | |
| 7067 | CTL1000_ENABLE_MASTER; |
| 7068 | tg3_writephy(tp, MII_CTRL1000, val); |
| 7069 | } else { |
| 7070 | ptest = MII_TG3_FET_PTEST_TRIM_SEL | |
| 7071 | MII_TG3_FET_PTEST_TRIM_2; |
| 7072 | tg3_writephy(tp, MII_TG3_FET_PTEST, ptest); |
| 7073 | } |
| 7074 | } else |
| 7075 | bmcr |= BMCR_LOOPBACK; |
| 7076 | |
Matt Carlson | 5e5a7f3 | 2011-08-19 13:58:21 +0000 | [diff] [blame] | 7077 | tg3_writephy(tp, MII_BMCR, bmcr); |
| 7078 | |
| 7079 | /* The write needs to be flushed for the FETs */ |
| 7080 | if (tp->phy_flags & TG3_PHYFLG_IS_FET) |
| 7081 | tg3_readphy(tp, MII_BMCR, &bmcr); |
| 7082 | |
| 7083 | udelay(40); |
| 7084 | |
| 7085 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && |
| 7086 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
Matt Carlson | 941ec90 | 2011-08-19 13:58:23 +0000 | [diff] [blame] | 7087 | tg3_writephy(tp, MII_TG3_FET_PTEST, ptest | |
Matt Carlson | 5e5a7f3 | 2011-08-19 13:58:21 +0000 | [diff] [blame] | 7088 | MII_TG3_FET_PTEST_FRC_TX_LINK | |
| 7089 | MII_TG3_FET_PTEST_FRC_TX_LOCK); |
| 7090 | |
| 7091 | /* The write needs to be flushed for the AC131 */ |
| 7092 | tg3_readphy(tp, MII_TG3_FET_PTEST, &val); |
| 7093 | } |
| 7094 | |
| 7095 | /* Reset to prevent losing 1st rx packet intermittently */ |
| 7096 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
| 7097 | tg3_flag(tp, 5780_CLASS)) { |
| 7098 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
| 7099 | udelay(10); |
| 7100 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
| 7101 | } |
| 7102 | |
| 7103 | mac_mode = tp->mac_mode & |
| 7104 | ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); |
| 7105 | if (speed == SPEED_1000) |
| 7106 | mac_mode |= MAC_MODE_PORT_MODE_GMII; |
| 7107 | else |
| 7108 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
| 7109 | |
| 7110 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
| 7111 | u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; |
| 7112 | |
| 7113 | if (masked_phy_id == TG3_PHY_ID_BCM5401) |
| 7114 | mac_mode &= ~MAC_MODE_LINK_POLARITY; |
| 7115 | else if (masked_phy_id == TG3_PHY_ID_BCM5411) |
| 7116 | mac_mode |= MAC_MODE_LINK_POLARITY; |
| 7117 | |
| 7118 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
| 7119 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); |
| 7120 | } |
| 7121 | |
| 7122 | tw32(MAC_MODE, mac_mode); |
| 7123 | udelay(40); |
Matt Carlson | 941ec90 | 2011-08-19 13:58:23 +0000 | [diff] [blame] | 7124 | |
| 7125 | return 0; |
Matt Carlson | 5e5a7f3 | 2011-08-19 13:58:21 +0000 | [diff] [blame] | 7126 | } |
| 7127 | |
Michał Mirosław | c8f44af | 2011-11-15 15:29:55 +0000 | [diff] [blame] | 7128 | static void tg3_set_loopback(struct net_device *dev, netdev_features_t features) |
Mahesh Bandewar | 06c03c0 | 2011-05-08 06:51:48 +0000 | [diff] [blame] | 7129 | { |
| 7130 | struct tg3 *tp = netdev_priv(dev); |
| 7131 | |
| 7132 | if (features & NETIF_F_LOOPBACK) { |
| 7133 | if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) |
| 7134 | return; |
| 7135 | |
Mahesh Bandewar | 06c03c0 | 2011-05-08 06:51:48 +0000 | [diff] [blame] | 7136 | spin_lock_bh(&tp->lock); |
Matt Carlson | 6e01b20 | 2011-08-19 13:58:20 +0000 | [diff] [blame] | 7137 | tg3_mac_loopback(tp, true); |
Mahesh Bandewar | 06c03c0 | 2011-05-08 06:51:48 +0000 | [diff] [blame] | 7138 | netif_carrier_on(tp->dev); |
| 7139 | spin_unlock_bh(&tp->lock); |
| 7140 | netdev_info(dev, "Internal MAC loopback mode enabled.\n"); |
| 7141 | } else { |
| 7142 | if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) |
| 7143 | return; |
| 7144 | |
Mahesh Bandewar | 06c03c0 | 2011-05-08 06:51:48 +0000 | [diff] [blame] | 7145 | spin_lock_bh(&tp->lock); |
Matt Carlson | 6e01b20 | 2011-08-19 13:58:20 +0000 | [diff] [blame] | 7146 | tg3_mac_loopback(tp, false); |
Mahesh Bandewar | 06c03c0 | 2011-05-08 06:51:48 +0000 | [diff] [blame] | 7147 | /* Force link status check */ |
| 7148 | tg3_setup_phy(tp, 1); |
| 7149 | spin_unlock_bh(&tp->lock); |
| 7150 | netdev_info(dev, "Internal MAC loopback mode disabled.\n"); |
| 7151 | } |
| 7152 | } |
| 7153 | |
Michał Mirosław | c8f44af | 2011-11-15 15:29:55 +0000 | [diff] [blame] | 7154 | static netdev_features_t tg3_fix_features(struct net_device *dev, |
| 7155 | netdev_features_t features) |
Michał Mirosław | dc66891 | 2011-04-07 03:35:07 +0000 | [diff] [blame] | 7156 | { |
| 7157 | struct tg3 *tp = netdev_priv(dev); |
| 7158 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7159 | if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) |
Michał Mirosław | dc66891 | 2011-04-07 03:35:07 +0000 | [diff] [blame] | 7160 | features &= ~NETIF_F_ALL_TSO; |
| 7161 | |
| 7162 | return features; |
| 7163 | } |
| 7164 | |
Michał Mirosław | c8f44af | 2011-11-15 15:29:55 +0000 | [diff] [blame] | 7165 | static int tg3_set_features(struct net_device *dev, netdev_features_t features) |
Mahesh Bandewar | 06c03c0 | 2011-05-08 06:51:48 +0000 | [diff] [blame] | 7166 | { |
Michał Mirosław | c8f44af | 2011-11-15 15:29:55 +0000 | [diff] [blame] | 7167 | netdev_features_t changed = dev->features ^ features; |
Mahesh Bandewar | 06c03c0 | 2011-05-08 06:51:48 +0000 | [diff] [blame] | 7168 | |
| 7169 | if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) |
| 7170 | tg3_set_loopback(dev, features); |
| 7171 | |
| 7172 | return 0; |
| 7173 | } |
| 7174 | |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 7175 | static void tg3_rx_prodring_free(struct tg3 *tp, |
| 7176 | struct tg3_rx_prodring_set *tpr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7177 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7178 | int i; |
| 7179 | |
Matt Carlson | 8fea32b | 2010-09-15 08:59:58 +0000 | [diff] [blame] | 7180 | if (tpr != &tp->napi[0].prodring) { |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 7181 | for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 7182 | i = (i + 1) & tp->rx_std_ring_mask) |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 7183 | tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 7184 | tp->rx_pkt_map_sz); |
| 7185 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7186 | if (tg3_flag(tp, JUMBO_CAPABLE)) { |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 7187 | for (i = tpr->rx_jmb_cons_idx; |
| 7188 | i != tpr->rx_jmb_prod_idx; |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 7189 | i = (i + 1) & tp->rx_jmb_ring_mask) { |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 7190 | tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 7191 | TG3_RX_JMB_MAP_SZ); |
| 7192 | } |
| 7193 | } |
| 7194 | |
Matt Carlson | 2b2cdb6 | 2009-11-13 13:03:48 +0000 | [diff] [blame] | 7195 | return; |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 7196 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7197 | |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 7198 | for (i = 0; i <= tp->rx_std_ring_mask; i++) |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 7199 | tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], |
Matt Carlson | 2b2cdb6 | 2009-11-13 13:03:48 +0000 | [diff] [blame] | 7200 | tp->rx_pkt_map_sz); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7201 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7202 | if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 7203 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 7204 | tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], |
Matt Carlson | 2b2cdb6 | 2009-11-13 13:03:48 +0000 | [diff] [blame] | 7205 | TG3_RX_JMB_MAP_SZ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7206 | } |
| 7207 | } |
| 7208 | |
Matt Carlson | c6cdf43 | 2010-04-05 10:19:26 +0000 | [diff] [blame] | 7209 | /* Initialize rx rings for packet processing. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7210 | * |
| 7211 | * The chip has been shut down and the driver detached from |
| 7212 | * the networking, so no interrupts or new tx packets will |
| 7213 | * end up in the driver. tp->{tx,}lock are held and thus |
| 7214 | * we may not sleep. |
| 7215 | */ |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 7216 | static int tg3_rx_prodring_alloc(struct tg3 *tp, |
| 7217 | struct tg3_rx_prodring_set *tpr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7218 | { |
Matt Carlson | 287be12 | 2009-08-28 13:58:46 +0000 | [diff] [blame] | 7219 | u32 i, rx_pkt_dma_sz; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7220 | |
Matt Carlson | b196c7e | 2009-11-13 13:03:50 +0000 | [diff] [blame] | 7221 | tpr->rx_std_cons_idx = 0; |
| 7222 | tpr->rx_std_prod_idx = 0; |
| 7223 | tpr->rx_jmb_cons_idx = 0; |
| 7224 | tpr->rx_jmb_prod_idx = 0; |
| 7225 | |
Matt Carlson | 8fea32b | 2010-09-15 08:59:58 +0000 | [diff] [blame] | 7226 | if (tpr != &tp->napi[0].prodring) { |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 7227 | memset(&tpr->rx_std_buffers[0], 0, |
| 7228 | TG3_RX_STD_BUFF_RING_SIZE(tp)); |
Matt Carlson | 4803572 | 2010-10-14 10:37:43 +0000 | [diff] [blame] | 7229 | if (tpr->rx_jmb_buffers) |
Matt Carlson | 2b2cdb6 | 2009-11-13 13:03:48 +0000 | [diff] [blame] | 7230 | memset(&tpr->rx_jmb_buffers[0], 0, |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 7231 | TG3_RX_JMB_BUFF_RING_SIZE(tp)); |
Matt Carlson | 2b2cdb6 | 2009-11-13 13:03:48 +0000 | [diff] [blame] | 7232 | goto done; |
| 7233 | } |
| 7234 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7235 | /* Zero out all descriptors. */ |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 7236 | memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7237 | |
Matt Carlson | 287be12 | 2009-08-28 13:58:46 +0000 | [diff] [blame] | 7238 | rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7239 | if (tg3_flag(tp, 5780_CLASS) && |
Matt Carlson | 287be12 | 2009-08-28 13:58:46 +0000 | [diff] [blame] | 7240 | tp->dev->mtu > ETH_DATA_LEN) |
| 7241 | rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ; |
| 7242 | tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); |
Michael Chan | 7e72aad | 2005-07-25 12:31:17 -0700 | [diff] [blame] | 7243 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7244 | /* Initialize invariants of the rings, we only set this |
| 7245 | * stuff once. This works because the card does not |
| 7246 | * write into the rx buffer posting rings. |
| 7247 | */ |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 7248 | for (i = 0; i <= tp->rx_std_ring_mask; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7249 | struct tg3_rx_buffer_desc *rxd; |
| 7250 | |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 7251 | rxd = &tpr->rx_std[i]; |
Matt Carlson | 287be12 | 2009-08-28 13:58:46 +0000 | [diff] [blame] | 7252 | rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7253 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); |
| 7254 | rxd->opaque = (RXD_OPAQUE_RING_STD | |
| 7255 | (i << RXD_OPAQUE_INDEX_SHIFT)); |
| 7256 | } |
| 7257 | |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7258 | /* Now allocate fresh SKBs for each rx ring. */ |
| 7259 | for (i = 0; i < tp->rx_pending; i++) { |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 7260 | if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) { |
Matt Carlson | 5129c3a | 2010-04-05 10:19:23 +0000 | [diff] [blame] | 7261 | netdev_warn(tp->dev, |
| 7262 | "Using a smaller RX standard ring. Only " |
| 7263 | "%d out of %d buffers were allocated " |
| 7264 | "successfully\n", i, tp->rx_pending); |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7265 | if (i == 0) |
| 7266 | goto initfail; |
| 7267 | tp->rx_pending = i; |
| 7268 | break; |
| 7269 | } |
| 7270 | } |
| 7271 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7272 | if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7273 | goto done; |
| 7274 | |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 7275 | memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7276 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7277 | if (!tg3_flag(tp, JUMBO_RING_ENABLE)) |
Matt Carlson | 0d86df8 | 2010-02-17 15:17:00 +0000 | [diff] [blame] | 7278 | goto done; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7279 | |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 7280 | for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { |
Matt Carlson | 0d86df8 | 2010-02-17 15:17:00 +0000 | [diff] [blame] | 7281 | struct tg3_rx_buffer_desc *rxd; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7282 | |
Matt Carlson | 0d86df8 | 2010-02-17 15:17:00 +0000 | [diff] [blame] | 7283 | rxd = &tpr->rx_jmb[i].std; |
| 7284 | rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; |
| 7285 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | |
| 7286 | RXD_FLAG_JUMBO; |
| 7287 | rxd->opaque = (RXD_OPAQUE_RING_JUMBO | |
| 7288 | (i << RXD_OPAQUE_INDEX_SHIFT)); |
| 7289 | } |
| 7290 | |
| 7291 | for (i = 0; i < tp->rx_jumbo_pending; i++) { |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 7292 | if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) { |
Matt Carlson | 5129c3a | 2010-04-05 10:19:23 +0000 | [diff] [blame] | 7293 | netdev_warn(tp->dev, |
| 7294 | "Using a smaller RX jumbo ring. Only %d " |
| 7295 | "out of %d buffers were allocated " |
| 7296 | "successfully\n", i, tp->rx_jumbo_pending); |
Matt Carlson | 0d86df8 | 2010-02-17 15:17:00 +0000 | [diff] [blame] | 7297 | if (i == 0) |
| 7298 | goto initfail; |
| 7299 | tp->rx_jumbo_pending = i; |
| 7300 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7301 | } |
| 7302 | } |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7303 | |
| 7304 | done: |
Michael Chan | 32d8c57 | 2006-07-25 16:38:29 -0700 | [diff] [blame] | 7305 | return 0; |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7306 | |
| 7307 | initfail: |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 7308 | tg3_rx_prodring_free(tp, tpr); |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7309 | return -ENOMEM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7310 | } |
| 7311 | |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 7312 | static void tg3_rx_prodring_fini(struct tg3 *tp, |
| 7313 | struct tg3_rx_prodring_set *tpr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7314 | { |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 7315 | kfree(tpr->rx_std_buffers); |
| 7316 | tpr->rx_std_buffers = NULL; |
| 7317 | kfree(tpr->rx_jmb_buffers); |
| 7318 | tpr->rx_jmb_buffers = NULL; |
| 7319 | if (tpr->rx_std) { |
Matt Carlson | 4bae65c | 2010-11-24 08:31:52 +0000 | [diff] [blame] | 7320 | dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), |
| 7321 | tpr->rx_std, tpr->rx_std_mapping); |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 7322 | tpr->rx_std = NULL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7323 | } |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 7324 | if (tpr->rx_jmb) { |
Matt Carlson | 4bae65c | 2010-11-24 08:31:52 +0000 | [diff] [blame] | 7325 | dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), |
| 7326 | tpr->rx_jmb, tpr->rx_jmb_mapping); |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 7327 | tpr->rx_jmb = NULL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7328 | } |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7329 | } |
| 7330 | |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 7331 | static int tg3_rx_prodring_init(struct tg3 *tp, |
| 7332 | struct tg3_rx_prodring_set *tpr) |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7333 | { |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 7334 | tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), |
| 7335 | GFP_KERNEL); |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 7336 | if (!tpr->rx_std_buffers) |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7337 | return -ENOMEM; |
| 7338 | |
Matt Carlson | 4bae65c | 2010-11-24 08:31:52 +0000 | [diff] [blame] | 7339 | tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, |
| 7340 | TG3_RX_STD_RING_BYTES(tp), |
| 7341 | &tpr->rx_std_mapping, |
| 7342 | GFP_KERNEL); |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 7343 | if (!tpr->rx_std) |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7344 | goto err_out; |
| 7345 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7346 | if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 7347 | tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 7348 | GFP_KERNEL); |
| 7349 | if (!tpr->rx_jmb_buffers) |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7350 | goto err_out; |
| 7351 | |
Matt Carlson | 4bae65c | 2010-11-24 08:31:52 +0000 | [diff] [blame] | 7352 | tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, |
| 7353 | TG3_RX_JMB_RING_BYTES(tp), |
| 7354 | &tpr->rx_jmb_mapping, |
| 7355 | GFP_KERNEL); |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 7356 | if (!tpr->rx_jmb) |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7357 | goto err_out; |
| 7358 | } |
| 7359 | |
| 7360 | return 0; |
| 7361 | |
| 7362 | err_out: |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 7363 | tg3_rx_prodring_fini(tp, tpr); |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7364 | return -ENOMEM; |
| 7365 | } |
| 7366 | |
| 7367 | /* Free up pending packets in all rx/tx rings. |
| 7368 | * |
| 7369 | * The chip has been shut down and the driver detached from |
| 7370 | * the networking, so no interrupts or new tx packets will |
| 7371 | * end up in the driver. tp->{tx,}lock is not held and we are not |
| 7372 | * in an interrupt context and thus may sleep. |
| 7373 | */ |
| 7374 | static void tg3_free_rings(struct tg3 *tp) |
| 7375 | { |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7376 | int i, j; |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7377 | |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7378 | for (j = 0; j < tp->irq_cnt; j++) { |
| 7379 | struct tg3_napi *tnapi = &tp->napi[j]; |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7380 | |
Matt Carlson | 8fea32b | 2010-09-15 08:59:58 +0000 | [diff] [blame] | 7381 | tg3_rx_prodring_free(tp, &tnapi->prodring); |
Matt Carlson | b28f642 | 2010-06-05 17:24:32 +0000 | [diff] [blame] | 7382 | |
Matt Carlson | 0c1d0e2 | 2009-09-01 13:16:33 +0000 | [diff] [blame] | 7383 | if (!tnapi->tx_buffers) |
| 7384 | continue; |
| 7385 | |
Matt Carlson | 0d681b2 | 2011-07-27 14:20:49 +0000 | [diff] [blame] | 7386 | for (i = 0; i < TG3_TX_RING_SIZE; i++) { |
| 7387 | struct sk_buff *skb = tnapi->tx_buffers[i].skb; |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7388 | |
Matt Carlson | 0d681b2 | 2011-07-27 14:20:49 +0000 | [diff] [blame] | 7389 | if (!skb) |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7390 | continue; |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7391 | |
Matt Carlson | ba1142e | 2011-11-04 09:15:00 +0000 | [diff] [blame] | 7392 | tg3_tx_skb_unmap(tnapi, i, |
| 7393 | skb_shinfo(skb)->nr_frags - 1); |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7394 | |
| 7395 | dev_kfree_skb_any(skb); |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7396 | } |
Matt Carlson | 2b2cdb6 | 2009-11-13 13:03:48 +0000 | [diff] [blame] | 7397 | } |
Tom Herbert | 298376d | 2011-11-28 16:33:30 +0000 | [diff] [blame] | 7398 | netdev_reset_queue(tp->dev); |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7399 | } |
| 7400 | |
| 7401 | /* Initialize tx/rx rings for packet processing. |
| 7402 | * |
| 7403 | * The chip has been shut down and the driver detached from |
| 7404 | * the networking, so no interrupts or new tx packets will |
| 7405 | * end up in the driver. tp->{tx,}lock are held and thus |
| 7406 | * we may not sleep. |
| 7407 | */ |
| 7408 | static int tg3_init_rings(struct tg3 *tp) |
| 7409 | { |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7410 | int i; |
Matt Carlson | 7233448 | 2009-08-28 14:03:01 +0000 | [diff] [blame] | 7411 | |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7412 | /* Free up all the SKBs. */ |
| 7413 | tg3_free_rings(tp); |
| 7414 | |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7415 | for (i = 0; i < tp->irq_cnt; i++) { |
| 7416 | struct tg3_napi *tnapi = &tp->napi[i]; |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7417 | |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7418 | tnapi->last_tag = 0; |
| 7419 | tnapi->last_irq_tag = 0; |
| 7420 | tnapi->hw_status->status = 0; |
| 7421 | tnapi->hw_status->status_tag = 0; |
| 7422 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); |
| 7423 | |
| 7424 | tnapi->tx_prod = 0; |
| 7425 | tnapi->tx_cons = 0; |
Matt Carlson | 0c1d0e2 | 2009-09-01 13:16:33 +0000 | [diff] [blame] | 7426 | if (tnapi->tx_ring) |
| 7427 | memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7428 | |
| 7429 | tnapi->rx_rcb_ptr = 0; |
Matt Carlson | 0c1d0e2 | 2009-09-01 13:16:33 +0000 | [diff] [blame] | 7430 | if (tnapi->rx_rcb) |
| 7431 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); |
Matt Carlson | 2b2cdb6 | 2009-11-13 13:03:48 +0000 | [diff] [blame] | 7432 | |
Matt Carlson | 8fea32b | 2010-09-15 08:59:58 +0000 | [diff] [blame] | 7433 | if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { |
Matt Carlson | e4af1af | 2010-02-12 14:47:05 +0000 | [diff] [blame] | 7434 | tg3_free_rings(tp); |
Matt Carlson | 2b2cdb6 | 2009-11-13 13:03:48 +0000 | [diff] [blame] | 7435 | return -ENOMEM; |
Matt Carlson | e4af1af | 2010-02-12 14:47:05 +0000 | [diff] [blame] | 7436 | } |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7437 | } |
Matt Carlson | 7233448 | 2009-08-28 14:03:01 +0000 | [diff] [blame] | 7438 | |
Matt Carlson | 2b2cdb6 | 2009-11-13 13:03:48 +0000 | [diff] [blame] | 7439 | return 0; |
Matt Carlson | cf7a729 | 2009-08-28 13:59:57 +0000 | [diff] [blame] | 7440 | } |
| 7441 | |
| 7442 | /* |
| 7443 | * Must not be invoked with interrupt sources disabled and |
| 7444 | * the hardware shutdown down. |
| 7445 | */ |
| 7446 | static void tg3_free_consistent(struct tg3 *tp) |
| 7447 | { |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7448 | int i; |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 7449 | |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7450 | for (i = 0; i < tp->irq_cnt; i++) { |
| 7451 | struct tg3_napi *tnapi = &tp->napi[i]; |
| 7452 | |
| 7453 | if (tnapi->tx_ring) { |
Matt Carlson | 4bae65c | 2010-11-24 08:31:52 +0000 | [diff] [blame] | 7454 | dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7455 | tnapi->tx_ring, tnapi->tx_desc_mapping); |
| 7456 | tnapi->tx_ring = NULL; |
| 7457 | } |
| 7458 | |
| 7459 | kfree(tnapi->tx_buffers); |
| 7460 | tnapi->tx_buffers = NULL; |
| 7461 | |
| 7462 | if (tnapi->rx_rcb) { |
Matt Carlson | 4bae65c | 2010-11-24 08:31:52 +0000 | [diff] [blame] | 7463 | dma_free_coherent(&tp->pdev->dev, |
| 7464 | TG3_RX_RCB_RING_BYTES(tp), |
| 7465 | tnapi->rx_rcb, |
| 7466 | tnapi->rx_rcb_mapping); |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7467 | tnapi->rx_rcb = NULL; |
| 7468 | } |
| 7469 | |
Matt Carlson | 8fea32b | 2010-09-15 08:59:58 +0000 | [diff] [blame] | 7470 | tg3_rx_prodring_fini(tp, &tnapi->prodring); |
| 7471 | |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7472 | if (tnapi->hw_status) { |
Matt Carlson | 4bae65c | 2010-11-24 08:31:52 +0000 | [diff] [blame] | 7473 | dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, |
| 7474 | tnapi->hw_status, |
| 7475 | tnapi->status_mapping); |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7476 | tnapi->hw_status = NULL; |
| 7477 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7478 | } |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7479 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7480 | if (tp->hw_stats) { |
Matt Carlson | 4bae65c | 2010-11-24 08:31:52 +0000 | [diff] [blame] | 7481 | dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), |
| 7482 | tp->hw_stats, tp->stats_mapping); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7483 | tp->hw_stats = NULL; |
| 7484 | } |
| 7485 | } |
| 7486 | |
| 7487 | /* |
| 7488 | * Must not be invoked with interrupt sources disabled and |
| 7489 | * the hardware shutdown down. Can sleep. |
| 7490 | */ |
| 7491 | static int tg3_alloc_consistent(struct tg3 *tp) |
| 7492 | { |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7493 | int i; |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 7494 | |
Matt Carlson | 4bae65c | 2010-11-24 08:31:52 +0000 | [diff] [blame] | 7495 | tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, |
| 7496 | sizeof(struct tg3_hw_stats), |
| 7497 | &tp->stats_mapping, |
| 7498 | GFP_KERNEL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7499 | if (!tp->hw_stats) |
| 7500 | goto err_out; |
| 7501 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7502 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); |
| 7503 | |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7504 | for (i = 0; i < tp->irq_cnt; i++) { |
| 7505 | struct tg3_napi *tnapi = &tp->napi[i]; |
Matt Carlson | 8d9d7cf | 2009-09-01 13:19:05 +0000 | [diff] [blame] | 7506 | struct tg3_hw_status *sblk; |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7507 | |
Matt Carlson | 4bae65c | 2010-11-24 08:31:52 +0000 | [diff] [blame] | 7508 | tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, |
| 7509 | TG3_HW_STATUS_SIZE, |
| 7510 | &tnapi->status_mapping, |
| 7511 | GFP_KERNEL); |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7512 | if (!tnapi->hw_status) |
| 7513 | goto err_out; |
| 7514 | |
| 7515 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); |
Matt Carlson | 8d9d7cf | 2009-09-01 13:19:05 +0000 | [diff] [blame] | 7516 | sblk = tnapi->hw_status; |
| 7517 | |
Matt Carlson | 8fea32b | 2010-09-15 08:59:58 +0000 | [diff] [blame] | 7518 | if (tg3_rx_prodring_init(tp, &tnapi->prodring)) |
| 7519 | goto err_out; |
| 7520 | |
Matt Carlson | 19cfaec | 2009-12-03 08:36:20 +0000 | [diff] [blame] | 7521 | /* If multivector TSS is enabled, vector 0 does not handle |
| 7522 | * tx interrupts. Don't allocate any resources for it. |
| 7523 | */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7524 | if ((!i && !tg3_flag(tp, ENABLE_TSS)) || |
| 7525 | (i && tg3_flag(tp, ENABLE_TSS))) { |
Matt Carlson | df8944c | 2011-07-27 14:20:46 +0000 | [diff] [blame] | 7526 | tnapi->tx_buffers = kzalloc( |
| 7527 | sizeof(struct tg3_tx_ring_info) * |
| 7528 | TG3_TX_RING_SIZE, GFP_KERNEL); |
Matt Carlson | 19cfaec | 2009-12-03 08:36:20 +0000 | [diff] [blame] | 7529 | if (!tnapi->tx_buffers) |
| 7530 | goto err_out; |
| 7531 | |
Matt Carlson | 4bae65c | 2010-11-24 08:31:52 +0000 | [diff] [blame] | 7532 | tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, |
| 7533 | TG3_TX_RING_BYTES, |
| 7534 | &tnapi->tx_desc_mapping, |
| 7535 | GFP_KERNEL); |
Matt Carlson | 19cfaec | 2009-12-03 08:36:20 +0000 | [diff] [blame] | 7536 | if (!tnapi->tx_ring) |
| 7537 | goto err_out; |
| 7538 | } |
| 7539 | |
Matt Carlson | 8d9d7cf | 2009-09-01 13:19:05 +0000 | [diff] [blame] | 7540 | /* |
| 7541 | * When RSS is enabled, the status block format changes |
| 7542 | * slightly. The "rx_jumbo_consumer", "reserved", |
| 7543 | * and "rx_mini_consumer" members get mapped to the |
| 7544 | * other three rx return ring producer indexes. |
| 7545 | */ |
| 7546 | switch (i) { |
| 7547 | default: |
| 7548 | tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; |
| 7549 | break; |
| 7550 | case 2: |
| 7551 | tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer; |
| 7552 | break; |
| 7553 | case 3: |
| 7554 | tnapi->rx_rcb_prod_idx = &sblk->reserved; |
| 7555 | break; |
| 7556 | case 4: |
| 7557 | tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer; |
| 7558 | break; |
| 7559 | } |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7560 | |
Matt Carlson | 0c1d0e2 | 2009-09-01 13:16:33 +0000 | [diff] [blame] | 7561 | /* |
| 7562 | * If multivector RSS is enabled, vector 0 does not handle |
| 7563 | * rx or tx interrupts. Don't allocate any resources for it. |
| 7564 | */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7565 | if (!i && tg3_flag(tp, ENABLE_RSS)) |
Matt Carlson | 0c1d0e2 | 2009-09-01 13:16:33 +0000 | [diff] [blame] | 7566 | continue; |
| 7567 | |
Matt Carlson | 4bae65c | 2010-11-24 08:31:52 +0000 | [diff] [blame] | 7568 | tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, |
| 7569 | TG3_RX_RCB_RING_BYTES(tp), |
| 7570 | &tnapi->rx_rcb_mapping, |
| 7571 | GFP_KERNEL); |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7572 | if (!tnapi->rx_rcb) |
| 7573 | goto err_out; |
| 7574 | |
| 7575 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7576 | } |
| 7577 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7578 | return 0; |
| 7579 | |
| 7580 | err_out: |
| 7581 | tg3_free_consistent(tp); |
| 7582 | return -ENOMEM; |
| 7583 | } |
| 7584 | |
| 7585 | #define MAX_WAIT_CNT 1000 |
| 7586 | |
| 7587 | /* To stop a block, clear the enable bit and poll till it |
| 7588 | * clears. tp->lock is held. |
| 7589 | */ |
David S. Miller | b3b7d6b | 2005-05-05 14:40:20 -0700 | [diff] [blame] | 7590 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7591 | { |
| 7592 | unsigned int i; |
| 7593 | u32 val; |
| 7594 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7595 | if (tg3_flag(tp, 5705_PLUS)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7596 | switch (ofs) { |
| 7597 | case RCVLSC_MODE: |
| 7598 | case DMAC_MODE: |
| 7599 | case MBFREE_MODE: |
| 7600 | case BUFMGR_MODE: |
| 7601 | case MEMARB_MODE: |
| 7602 | /* We can't enable/disable these bits of the |
| 7603 | * 5705/5750, just say success. |
| 7604 | */ |
| 7605 | return 0; |
| 7606 | |
| 7607 | default: |
| 7608 | break; |
Stephen Hemminger | 855e111 | 2008-04-16 16:37:28 -0700 | [diff] [blame] | 7609 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7610 | } |
| 7611 | |
| 7612 | val = tr32(ofs); |
| 7613 | val &= ~enable_bit; |
| 7614 | tw32_f(ofs, val); |
| 7615 | |
| 7616 | for (i = 0; i < MAX_WAIT_CNT; i++) { |
| 7617 | udelay(100); |
| 7618 | val = tr32(ofs); |
| 7619 | if ((val & enable_bit) == 0) |
| 7620 | break; |
| 7621 | } |
| 7622 | |
David S. Miller | b3b7d6b | 2005-05-05 14:40:20 -0700 | [diff] [blame] | 7623 | if (i == MAX_WAIT_CNT && !silent) { |
Matt Carlson | 2445e46 | 2010-04-05 10:19:21 +0000 | [diff] [blame] | 7624 | dev_err(&tp->pdev->dev, |
| 7625 | "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n", |
| 7626 | ofs, enable_bit); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7627 | return -ENODEV; |
| 7628 | } |
| 7629 | |
| 7630 | return 0; |
| 7631 | } |
| 7632 | |
| 7633 | /* tp->lock is held. */ |
David S. Miller | b3b7d6b | 2005-05-05 14:40:20 -0700 | [diff] [blame] | 7634 | static int tg3_abort_hw(struct tg3 *tp, int silent) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7635 | { |
| 7636 | int i, err; |
| 7637 | |
| 7638 | tg3_disable_ints(tp); |
| 7639 | |
| 7640 | tp->rx_mode &= ~RX_MODE_ENABLE; |
| 7641 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
| 7642 | udelay(10); |
| 7643 | |
David S. Miller | b3b7d6b | 2005-05-05 14:40:20 -0700 | [diff] [blame] | 7644 | err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); |
| 7645 | err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); |
| 7646 | err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); |
| 7647 | err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); |
| 7648 | err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); |
| 7649 | err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7650 | |
David S. Miller | b3b7d6b | 2005-05-05 14:40:20 -0700 | [diff] [blame] | 7651 | err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); |
| 7652 | err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); |
| 7653 | err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); |
| 7654 | err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); |
| 7655 | err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); |
| 7656 | err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); |
| 7657 | err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7658 | |
| 7659 | tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; |
| 7660 | tw32_f(MAC_MODE, tp->mac_mode); |
| 7661 | udelay(40); |
| 7662 | |
| 7663 | tp->tx_mode &= ~TX_MODE_ENABLE; |
| 7664 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
| 7665 | |
| 7666 | for (i = 0; i < MAX_WAIT_CNT; i++) { |
| 7667 | udelay(100); |
| 7668 | if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) |
| 7669 | break; |
| 7670 | } |
| 7671 | if (i >= MAX_WAIT_CNT) { |
Matt Carlson | ab96b24 | 2010-04-05 10:19:22 +0000 | [diff] [blame] | 7672 | dev_err(&tp->pdev->dev, |
| 7673 | "%s timed out, TX_MODE_ENABLE will not clear " |
| 7674 | "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE)); |
Michael Chan | e6de8ad | 2005-05-05 14:42:41 -0700 | [diff] [blame] | 7675 | err |= -ENODEV; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7676 | } |
| 7677 | |
Michael Chan | e6de8ad | 2005-05-05 14:42:41 -0700 | [diff] [blame] | 7678 | err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); |
David S. Miller | b3b7d6b | 2005-05-05 14:40:20 -0700 | [diff] [blame] | 7679 | err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); |
| 7680 | err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7681 | |
| 7682 | tw32(FTQ_RESET, 0xffffffff); |
| 7683 | tw32(FTQ_RESET, 0x00000000); |
| 7684 | |
David S. Miller | b3b7d6b | 2005-05-05 14:40:20 -0700 | [diff] [blame] | 7685 | err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); |
| 7686 | err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7687 | |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7688 | for (i = 0; i < tp->irq_cnt; i++) { |
| 7689 | struct tg3_napi *tnapi = &tp->napi[i]; |
| 7690 | if (tnapi->hw_status) |
| 7691 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); |
| 7692 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7693 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7694 | return err; |
| 7695 | } |
| 7696 | |
Michael Chan | ee6a99b | 2007-07-18 21:49:10 -0700 | [diff] [blame] | 7697 | /* Save PCI command register before chip reset */ |
| 7698 | static void tg3_save_pci_state(struct tg3 *tp) |
| 7699 | { |
Matt Carlson | 8a6eac9 | 2007-10-21 16:17:55 -0700 | [diff] [blame] | 7700 | pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); |
Michael Chan | ee6a99b | 2007-07-18 21:49:10 -0700 | [diff] [blame] | 7701 | } |
| 7702 | |
| 7703 | /* Restore PCI state after chip reset */ |
| 7704 | static void tg3_restore_pci_state(struct tg3 *tp) |
| 7705 | { |
| 7706 | u32 val; |
| 7707 | |
| 7708 | /* Re-enable indirect register accesses. */ |
| 7709 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, |
| 7710 | tp->misc_host_ctrl); |
| 7711 | |
| 7712 | /* Set MAX PCI retry to zero. */ |
| 7713 | val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); |
| 7714 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7715 | tg3_flag(tp, PCIX_MODE)) |
Michael Chan | ee6a99b | 2007-07-18 21:49:10 -0700 | [diff] [blame] | 7716 | val |= PCISTATE_RETRY_SAME_DMA; |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 7717 | /* Allow reads and writes to the APE register and memory space. */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7718 | if (tg3_flag(tp, ENABLE_APE)) |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 7719 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | |
Matt Carlson | f92d9dc1 | 2010-06-05 17:24:30 +0000 | [diff] [blame] | 7720 | PCISTATE_ALLOW_APE_SHMEM_WR | |
| 7721 | PCISTATE_ALLOW_APE_PSPACE_WR; |
Michael Chan | ee6a99b | 2007-07-18 21:49:10 -0700 | [diff] [blame] | 7722 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); |
| 7723 | |
Matt Carlson | 8a6eac9 | 2007-10-21 16:17:55 -0700 | [diff] [blame] | 7724 | pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); |
Michael Chan | ee6a99b | 2007-07-18 21:49:10 -0700 | [diff] [blame] | 7725 | |
Matt Carlson | 2c55a3d | 2011-11-28 09:41:04 +0000 | [diff] [blame] | 7726 | if (!tg3_flag(tp, PCI_EXPRESS)) { |
| 7727 | pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, |
| 7728 | tp->pci_cacheline_sz); |
| 7729 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, |
| 7730 | tp->pci_lat_timer); |
Michael Chan | 114342f | 2007-10-15 02:12:26 -0700 | [diff] [blame] | 7731 | } |
Matt Carlson | 5f5c51e | 2007-11-12 21:19:37 -0800 | [diff] [blame] | 7732 | |
Michael Chan | ee6a99b | 2007-07-18 21:49:10 -0700 | [diff] [blame] | 7733 | /* Make sure PCI-X relaxed ordering bit is clear. */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7734 | if (tg3_flag(tp, PCIX_MODE)) { |
Matt Carlson | 9974a35 | 2007-10-07 23:27:28 -0700 | [diff] [blame] | 7735 | u16 pcix_cmd; |
| 7736 | |
| 7737 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, |
| 7738 | &pcix_cmd); |
| 7739 | pcix_cmd &= ~PCI_X_CMD_ERO; |
| 7740 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, |
| 7741 | pcix_cmd); |
| 7742 | } |
Michael Chan | ee6a99b | 2007-07-18 21:49:10 -0700 | [diff] [blame] | 7743 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7744 | if (tg3_flag(tp, 5780_CLASS)) { |
Michael Chan | ee6a99b | 2007-07-18 21:49:10 -0700 | [diff] [blame] | 7745 | |
| 7746 | /* Chip reset on 5780 will reset MSI enable bit, |
| 7747 | * so need to restore it. |
| 7748 | */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7749 | if (tg3_flag(tp, USING_MSI)) { |
Michael Chan | ee6a99b | 2007-07-18 21:49:10 -0700 | [diff] [blame] | 7750 | u16 ctrl; |
| 7751 | |
| 7752 | pci_read_config_word(tp->pdev, |
| 7753 | tp->msi_cap + PCI_MSI_FLAGS, |
| 7754 | &ctrl); |
| 7755 | pci_write_config_word(tp->pdev, |
| 7756 | tp->msi_cap + PCI_MSI_FLAGS, |
| 7757 | ctrl | PCI_MSI_FLAGS_ENABLE); |
| 7758 | val = tr32(MSGINT_MODE); |
| 7759 | tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE); |
| 7760 | } |
| 7761 | } |
| 7762 | } |
| 7763 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7764 | /* tp->lock is held. */ |
| 7765 | static int tg3_chip_reset(struct tg3 *tp) |
| 7766 | { |
| 7767 | u32 val; |
Michael Chan | 1ee582d | 2005-08-09 20:16:46 -0700 | [diff] [blame] | 7768 | void (*write_op)(struct tg3 *, u32, u32); |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 7769 | int i, err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7770 | |
David S. Miller | f49639e | 2006-06-09 11:58:36 -0700 | [diff] [blame] | 7771 | tg3_nvram_lock(tp); |
| 7772 | |
Matt Carlson | 77b483f | 2008-08-15 14:07:24 -0700 | [diff] [blame] | 7773 | tg3_ape_lock(tp, TG3_APE_LOCK_GRC); |
| 7774 | |
David S. Miller | f49639e | 2006-06-09 11:58:36 -0700 | [diff] [blame] | 7775 | /* No matching tg3_nvram_unlock() after this because |
| 7776 | * chip reset below will undo the nvram lock. |
| 7777 | */ |
| 7778 | tp->nvram_lock_cnt = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7779 | |
Michael Chan | ee6a99b | 2007-07-18 21:49:10 -0700 | [diff] [blame] | 7780 | /* GRC_MISC_CFG core clock reset will clear the memory |
| 7781 | * enable bit in PCI register 4 and the MSI enable bit |
| 7782 | * on some chips, so we save relevant registers here. |
| 7783 | */ |
| 7784 | tg3_save_pci_state(tp); |
| 7785 | |
Michael Chan | d9ab5ad | 2006-03-20 22:27:35 -0800 | [diff] [blame] | 7786 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7787 | tg3_flag(tp, 5755_PLUS)) |
Michael Chan | d9ab5ad | 2006-03-20 22:27:35 -0800 | [diff] [blame] | 7788 | tw32(GRC_FASTBOOT_PC, 0); |
| 7789 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7790 | /* |
| 7791 | * We must avoid the readl() that normally takes place. |
| 7792 | * It locks machines, causes machine checks, and other |
| 7793 | * fun things. So, temporarily disable the 5701 |
| 7794 | * hardware workaround, while we do the reset. |
| 7795 | */ |
Michael Chan | 1ee582d | 2005-08-09 20:16:46 -0700 | [diff] [blame] | 7796 | write_op = tp->write32; |
| 7797 | if (write_op == tg3_write_flush_reg32) |
| 7798 | tp->write32 = tg3_write32; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7799 | |
Michael Chan | d18edcb | 2007-03-24 20:57:11 -0700 | [diff] [blame] | 7800 | /* Prevent the irq handler from reading or writing PCI registers |
| 7801 | * during chip reset when the memory enable bit in the PCI command |
| 7802 | * register may be cleared. The chip does not generate interrupt |
| 7803 | * at this time, but the irq handler may still be called due to irq |
| 7804 | * sharing or irqpoll. |
| 7805 | */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7806 | tg3_flag_set(tp, CHIP_RESETTING); |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 7807 | for (i = 0; i < tp->irq_cnt; i++) { |
| 7808 | struct tg3_napi *tnapi = &tp->napi[i]; |
| 7809 | if (tnapi->hw_status) { |
| 7810 | tnapi->hw_status->status = 0; |
| 7811 | tnapi->hw_status->status_tag = 0; |
| 7812 | } |
| 7813 | tnapi->last_tag = 0; |
| 7814 | tnapi->last_irq_tag = 0; |
Michael Chan | b8fa2f3 | 2007-04-06 17:35:37 -0700 | [diff] [blame] | 7815 | } |
Michael Chan | d18edcb | 2007-03-24 20:57:11 -0700 | [diff] [blame] | 7816 | smp_mb(); |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 7817 | |
| 7818 | for (i = 0; i < tp->irq_cnt; i++) |
| 7819 | synchronize_irq(tp->napi[i].irq_vec); |
Michael Chan | d18edcb | 2007-03-24 20:57:11 -0700 | [diff] [blame] | 7820 | |
Matt Carlson | 255ca31 | 2009-08-25 10:07:27 +0000 | [diff] [blame] | 7821 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
| 7822 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; |
| 7823 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); |
| 7824 | } |
| 7825 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7826 | /* do the reset */ |
| 7827 | val = GRC_MISC_CFG_CORECLK_RESET; |
| 7828 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7829 | if (tg3_flag(tp, PCI_EXPRESS)) { |
Matt Carlson | 88075d9 | 2010-08-02 11:25:58 +0000 | [diff] [blame] | 7830 | /* Force PCIe 1.0a mode */ |
| 7831 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7832 | !tg3_flag(tp, 57765_PLUS) && |
Matt Carlson | 88075d9 | 2010-08-02 11:25:58 +0000 | [diff] [blame] | 7833 | tr32(TG3_PCIE_PHY_TSTCTL) == |
| 7834 | (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM)) |
| 7835 | tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM); |
| 7836 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7837 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { |
| 7838 | tw32(GRC_MISC_CFG, (1 << 29)); |
| 7839 | val |= (1 << 29); |
| 7840 | } |
| 7841 | } |
| 7842 | |
Michael Chan | b5d3772 | 2006-09-27 16:06:21 -0700 | [diff] [blame] | 7843 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
| 7844 | tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); |
| 7845 | tw32(GRC_VCPU_EXT_CTRL, |
| 7846 | tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); |
| 7847 | } |
| 7848 | |
Matt Carlson | f37500d | 2010-08-02 11:25:59 +0000 | [diff] [blame] | 7849 | /* Manage gphy power for all CPMU absent PCIe devices. */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7850 | if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7851 | val |= GRC_MISC_CFG_KEEP_GPHY_POWER; |
Matt Carlson | f37500d | 2010-08-02 11:25:59 +0000 | [diff] [blame] | 7852 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7853 | tw32(GRC_MISC_CFG, val); |
| 7854 | |
Michael Chan | 1ee582d | 2005-08-09 20:16:46 -0700 | [diff] [blame] | 7855 | /* restore 5701 hardware bug workaround write method */ |
| 7856 | tp->write32 = write_op; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7857 | |
| 7858 | /* Unfortunately, we have to delay before the PCI read back. |
| 7859 | * Some 575X chips even will not respond to a PCI cfg access |
| 7860 | * when the reset command is given to the chip. |
| 7861 | * |
| 7862 | * How do these hardware designers expect things to work |
| 7863 | * properly if the PCI write is posted for a long period |
| 7864 | * of time? It is always necessary to have some method by |
| 7865 | * which a register read back can occur to push the write |
| 7866 | * out which does the reset. |
| 7867 | * |
| 7868 | * For most tg3 variants the trick below was working. |
| 7869 | * Ho hum... |
| 7870 | */ |
| 7871 | udelay(120); |
| 7872 | |
| 7873 | /* Flush PCI posted writes. The normal MMIO registers |
| 7874 | * are inaccessible at this time so this is the only |
| 7875 | * way to make this reliably (actually, this is no longer |
| 7876 | * the case, see above). I tried to use indirect |
| 7877 | * register read/write but this upset some 5701 variants. |
| 7878 | */ |
| 7879 | pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); |
| 7880 | |
| 7881 | udelay(120); |
| 7882 | |
Jon Mason | 708ebb3 | 2011-06-27 12:56:50 +0000 | [diff] [blame] | 7883 | if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) { |
Matt Carlson | e712699 | 2009-08-25 10:08:16 +0000 | [diff] [blame] | 7884 | u16 val16; |
| 7885 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7886 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { |
| 7887 | int i; |
| 7888 | u32 cfg_val; |
| 7889 | |
| 7890 | /* Wait for link training to complete. */ |
| 7891 | for (i = 0; i < 5000; i++) |
| 7892 | udelay(100); |
| 7893 | |
| 7894 | pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); |
| 7895 | pci_write_config_dword(tp->pdev, 0xc4, |
| 7896 | cfg_val | (1 << 15)); |
| 7897 | } |
Matt Carlson | 5e7dfd0 | 2008-11-21 17:18:16 -0800 | [diff] [blame] | 7898 | |
Matt Carlson | e712699 | 2009-08-25 10:08:16 +0000 | [diff] [blame] | 7899 | /* Clear the "no snoop" and "relaxed ordering" bits. */ |
| 7900 | pci_read_config_word(tp->pdev, |
Jon Mason | 708ebb3 | 2011-06-27 12:56:50 +0000 | [diff] [blame] | 7901 | pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL, |
Matt Carlson | e712699 | 2009-08-25 10:08:16 +0000 | [diff] [blame] | 7902 | &val16); |
| 7903 | val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN | |
| 7904 | PCI_EXP_DEVCTL_NOSNOOP_EN); |
| 7905 | /* |
| 7906 | * Older PCIe devices only support the 128 byte |
| 7907 | * MPS setting. Enforce the restriction. |
Matt Carlson | 5e7dfd0 | 2008-11-21 17:18:16 -0800 | [diff] [blame] | 7908 | */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7909 | if (!tg3_flag(tp, CPMU_PRESENT)) |
Matt Carlson | e712699 | 2009-08-25 10:08:16 +0000 | [diff] [blame] | 7910 | val16 &= ~PCI_EXP_DEVCTL_PAYLOAD; |
Matt Carlson | 5e7dfd0 | 2008-11-21 17:18:16 -0800 | [diff] [blame] | 7911 | pci_write_config_word(tp->pdev, |
Jon Mason | 708ebb3 | 2011-06-27 12:56:50 +0000 | [diff] [blame] | 7912 | pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL, |
Matt Carlson | e712699 | 2009-08-25 10:08:16 +0000 | [diff] [blame] | 7913 | val16); |
Matt Carlson | 5e7dfd0 | 2008-11-21 17:18:16 -0800 | [diff] [blame] | 7914 | |
Matt Carlson | 5e7dfd0 | 2008-11-21 17:18:16 -0800 | [diff] [blame] | 7915 | /* Clear error status */ |
| 7916 | pci_write_config_word(tp->pdev, |
Jon Mason | 708ebb3 | 2011-06-27 12:56:50 +0000 | [diff] [blame] | 7917 | pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA, |
Matt Carlson | 5e7dfd0 | 2008-11-21 17:18:16 -0800 | [diff] [blame] | 7918 | PCI_EXP_DEVSTA_CED | |
| 7919 | PCI_EXP_DEVSTA_NFED | |
| 7920 | PCI_EXP_DEVSTA_FED | |
| 7921 | PCI_EXP_DEVSTA_URD); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7922 | } |
| 7923 | |
Michael Chan | ee6a99b | 2007-07-18 21:49:10 -0700 | [diff] [blame] | 7924 | tg3_restore_pci_state(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7925 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7926 | tg3_flag_clear(tp, CHIP_RESETTING); |
| 7927 | tg3_flag_clear(tp, ERROR_PROCESSED); |
Michael Chan | d18edcb | 2007-03-24 20:57:11 -0700 | [diff] [blame] | 7928 | |
Michael Chan | ee6a99b | 2007-07-18 21:49:10 -0700 | [diff] [blame] | 7929 | val = 0; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7930 | if (tg3_flag(tp, 5780_CLASS)) |
Michael Chan | 4cf78e4 | 2005-07-25 12:29:19 -0700 | [diff] [blame] | 7931 | val = tr32(MEMARB_MODE); |
Michael Chan | ee6a99b | 2007-07-18 21:49:10 -0700 | [diff] [blame] | 7932 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7933 | |
| 7934 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { |
| 7935 | tg3_stop_fw(tp); |
| 7936 | tw32(0x5000, 0x400); |
| 7937 | } |
| 7938 | |
| 7939 | tw32(GRC_MODE, tp->grc_mode); |
| 7940 | |
| 7941 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { |
Andy Gospodarek | ab0049b | 2007-09-06 20:42:14 +0100 | [diff] [blame] | 7942 | val = tr32(0xc4); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7943 | |
| 7944 | tw32(0xc4, val | (1 << 15)); |
| 7945 | } |
| 7946 | |
| 7947 | if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && |
| 7948 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
| 7949 | tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; |
| 7950 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) |
| 7951 | tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; |
| 7952 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); |
| 7953 | } |
| 7954 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 7955 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
Matt Carlson | 9e975cc | 2011-07-20 10:20:50 +0000 | [diff] [blame] | 7956 | tp->mac_mode = MAC_MODE_PORT_MODE_TBI; |
Matt Carlson | d2394e6b | 2010-11-24 08:31:47 +0000 | [diff] [blame] | 7957 | val = tp->mac_mode; |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 7958 | } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
Matt Carlson | 9e975cc | 2011-07-20 10:20:50 +0000 | [diff] [blame] | 7959 | tp->mac_mode = MAC_MODE_PORT_MODE_GMII; |
Matt Carlson | d2394e6b | 2010-11-24 08:31:47 +0000 | [diff] [blame] | 7960 | val = tp->mac_mode; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7961 | } else |
Matt Carlson | d2394e6b | 2010-11-24 08:31:47 +0000 | [diff] [blame] | 7962 | val = 0; |
| 7963 | |
| 7964 | tw32_f(MAC_MODE, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7965 | udelay(40); |
| 7966 | |
Matt Carlson | 77b483f | 2008-08-15 14:07:24 -0700 | [diff] [blame] | 7967 | tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); |
| 7968 | |
Michael Chan | 7a6f436 | 2006-09-27 16:03:31 -0700 | [diff] [blame] | 7969 | err = tg3_poll_fw(tp); |
| 7970 | if (err) |
| 7971 | return err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7972 | |
Matt Carlson | 0a9140c | 2009-08-28 12:27:50 +0000 | [diff] [blame] | 7973 | tg3_mdio_start(tp); |
| 7974 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7975 | if (tg3_flag(tp, PCI_EXPRESS) && |
Matt Carlson | f6eb9b1 | 2009-09-01 13:19:53 +0000 | [diff] [blame] | 7976 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && |
| 7977 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7978 | !tg3_flag(tp, 57765_PLUS)) { |
Andy Gospodarek | ab0049b | 2007-09-06 20:42:14 +0100 | [diff] [blame] | 7979 | val = tr32(0x7c00); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7980 | |
| 7981 | tw32(0x7c00, val | (1 << 25)); |
| 7982 | } |
| 7983 | |
Matt Carlson | d78b59f | 2011-04-05 14:22:46 +0000 | [diff] [blame] | 7984 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { |
| 7985 | val = tr32(TG3_CPMU_CLCK_ORIDE); |
| 7986 | tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN); |
| 7987 | } |
| 7988 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7989 | /* Reprobe ASF enable state. */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7990 | tg3_flag_clear(tp, ENABLE_ASF); |
| 7991 | tg3_flag_clear(tp, ASF_NEW_HANDSHAKE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7992 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
| 7993 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { |
| 7994 | u32 nic_cfg; |
| 7995 | |
| 7996 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); |
| 7997 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 7998 | tg3_flag_set(tp, ENABLE_ASF); |
Matt Carlson | 4ba526c | 2008-08-15 14:10:04 -0700 | [diff] [blame] | 7999 | tp->last_event_jiffies = jiffies; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8000 | if (tg3_flag(tp, 5750_PLUS)) |
| 8001 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8002 | } |
| 8003 | } |
| 8004 | |
| 8005 | return 0; |
| 8006 | } |
| 8007 | |
Matt Carlson | 92feeab | 2011-12-08 14:40:14 +0000 | [diff] [blame] | 8008 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *, |
| 8009 | struct rtnl_link_stats64 *); |
| 8010 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *, |
| 8011 | struct tg3_ethtool_stats *); |
| 8012 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8013 | /* tp->lock is held. */ |
Michael Chan | 944d980 | 2005-05-29 14:57:48 -0700 | [diff] [blame] | 8014 | static int tg3_halt(struct tg3 *tp, int kind, int silent) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8015 | { |
| 8016 | int err; |
| 8017 | |
| 8018 | tg3_stop_fw(tp); |
| 8019 | |
Michael Chan | 944d980 | 2005-05-29 14:57:48 -0700 | [diff] [blame] | 8020 | tg3_write_sig_pre_reset(tp, kind); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8021 | |
David S. Miller | b3b7d6b | 2005-05-05 14:40:20 -0700 | [diff] [blame] | 8022 | tg3_abort_hw(tp, silent); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8023 | err = tg3_chip_reset(tp); |
| 8024 | |
Matt Carlson | daba2a6 | 2009-04-20 06:58:52 +0000 | [diff] [blame] | 8025 | __tg3_set_mac_addr(tp, 0); |
| 8026 | |
Michael Chan | 944d980 | 2005-05-29 14:57:48 -0700 | [diff] [blame] | 8027 | tg3_write_sig_legacy(tp, kind); |
| 8028 | tg3_write_sig_post_reset(tp, kind); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8029 | |
Matt Carlson | 92feeab | 2011-12-08 14:40:14 +0000 | [diff] [blame] | 8030 | if (tp->hw_stats) { |
| 8031 | /* Save the stats across chip resets... */ |
| 8032 | tg3_get_stats64(tp->dev, &tp->net_stats_prev), |
| 8033 | tg3_get_estats(tp, &tp->estats_prev); |
| 8034 | |
| 8035 | /* And make sure the next sample is new data */ |
| 8036 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); |
| 8037 | } |
| 8038 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8039 | if (err) |
| 8040 | return err; |
| 8041 | |
| 8042 | return 0; |
| 8043 | } |
| 8044 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8045 | static int tg3_set_mac_addr(struct net_device *dev, void *p) |
| 8046 | { |
| 8047 | struct tg3 *tp = netdev_priv(dev); |
| 8048 | struct sockaddr *addr = p; |
Michael Chan | 986e0ae | 2007-05-05 12:10:20 -0700 | [diff] [blame] | 8049 | int err = 0, skip_mac_1 = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8050 | |
Michael Chan | f9804dd | 2005-09-27 12:13:10 -0700 | [diff] [blame] | 8051 | if (!is_valid_ether_addr(addr->sa_data)) |
| 8052 | return -EINVAL; |
| 8053 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8054 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
| 8055 | |
Michael Chan | e75f7c9 | 2006-03-20 21:33:26 -0800 | [diff] [blame] | 8056 | if (!netif_running(dev)) |
| 8057 | return 0; |
| 8058 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8059 | if (tg3_flag(tp, ENABLE_ASF)) { |
Michael Chan | 986e0ae | 2007-05-05 12:10:20 -0700 | [diff] [blame] | 8060 | u32 addr0_high, addr0_low, addr1_high, addr1_low; |
Michael Chan | 58712ef | 2006-04-29 18:58:01 -0700 | [diff] [blame] | 8061 | |
Michael Chan | 986e0ae | 2007-05-05 12:10:20 -0700 | [diff] [blame] | 8062 | addr0_high = tr32(MAC_ADDR_0_HIGH); |
| 8063 | addr0_low = tr32(MAC_ADDR_0_LOW); |
| 8064 | addr1_high = tr32(MAC_ADDR_1_HIGH); |
| 8065 | addr1_low = tr32(MAC_ADDR_1_LOW); |
| 8066 | |
| 8067 | /* Skip MAC addr 1 if ASF is using it. */ |
| 8068 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && |
| 8069 | !(addr1_high == 0 && addr1_low == 0)) |
| 8070 | skip_mac_1 = 1; |
Michael Chan | 58712ef | 2006-04-29 18:58:01 -0700 | [diff] [blame] | 8071 | } |
Michael Chan | 986e0ae | 2007-05-05 12:10:20 -0700 | [diff] [blame] | 8072 | spin_lock_bh(&tp->lock); |
| 8073 | __tg3_set_mac_addr(tp, skip_mac_1); |
| 8074 | spin_unlock_bh(&tp->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8075 | |
Michael Chan | b9ec6c1 | 2006-07-25 16:37:27 -0700 | [diff] [blame] | 8076 | return err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8077 | } |
| 8078 | |
| 8079 | /* tp->lock is held. */ |
| 8080 | static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, |
| 8081 | dma_addr_t mapping, u32 maxlen_flags, |
| 8082 | u32 nic_addr) |
| 8083 | { |
| 8084 | tg3_write_mem(tp, |
| 8085 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH), |
| 8086 | ((u64) mapping >> 32)); |
| 8087 | tg3_write_mem(tp, |
| 8088 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), |
| 8089 | ((u64) mapping & 0xffffffff)); |
| 8090 | tg3_write_mem(tp, |
| 8091 | (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS), |
| 8092 | maxlen_flags); |
| 8093 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8094 | if (!tg3_flag(tp, 5705_PLUS)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8095 | tg3_write_mem(tp, |
| 8096 | (bdinfo_addr + TG3_BDINFO_NIC_ADDR), |
| 8097 | nic_addr); |
| 8098 | } |
| 8099 | |
Michael Chan | d244c89 | 2005-07-05 14:42:33 -0700 | [diff] [blame] | 8100 | static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) |
David S. Miller | 15f9850 | 2005-05-18 22:49:26 -0700 | [diff] [blame] | 8101 | { |
Matt Carlson | b6080e1 | 2009-09-01 13:12:00 +0000 | [diff] [blame] | 8102 | int i; |
| 8103 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8104 | if (!tg3_flag(tp, ENABLE_TSS)) { |
Matt Carlson | b6080e1 | 2009-09-01 13:12:00 +0000 | [diff] [blame] | 8105 | tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); |
| 8106 | tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); |
| 8107 | tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); |
Matt Carlson | b6080e1 | 2009-09-01 13:12:00 +0000 | [diff] [blame] | 8108 | } else { |
| 8109 | tw32(HOSTCC_TXCOL_TICKS, 0); |
| 8110 | tw32(HOSTCC_TXMAX_FRAMES, 0); |
| 8111 | tw32(HOSTCC_TXCOAL_MAXF_INT, 0); |
Matt Carlson | 19cfaec | 2009-12-03 08:36:20 +0000 | [diff] [blame] | 8112 | } |
Matt Carlson | b6080e1 | 2009-09-01 13:12:00 +0000 | [diff] [blame] | 8113 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8114 | if (!tg3_flag(tp, ENABLE_RSS)) { |
Matt Carlson | 19cfaec | 2009-12-03 08:36:20 +0000 | [diff] [blame] | 8115 | tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); |
| 8116 | tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); |
| 8117 | tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); |
| 8118 | } else { |
Matt Carlson | b6080e1 | 2009-09-01 13:12:00 +0000 | [diff] [blame] | 8119 | tw32(HOSTCC_RXCOL_TICKS, 0); |
| 8120 | tw32(HOSTCC_RXMAX_FRAMES, 0); |
| 8121 | tw32(HOSTCC_RXCOAL_MAXF_INT, 0); |
David S. Miller | 15f9850 | 2005-05-18 22:49:26 -0700 | [diff] [blame] | 8122 | } |
Matt Carlson | b6080e1 | 2009-09-01 13:12:00 +0000 | [diff] [blame] | 8123 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8124 | if (!tg3_flag(tp, 5705_PLUS)) { |
David S. Miller | 15f9850 | 2005-05-18 22:49:26 -0700 | [diff] [blame] | 8125 | u32 val = ec->stats_block_coalesce_usecs; |
| 8126 | |
Matt Carlson | b6080e1 | 2009-09-01 13:12:00 +0000 | [diff] [blame] | 8127 | tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); |
| 8128 | tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); |
| 8129 | |
David S. Miller | 15f9850 | 2005-05-18 22:49:26 -0700 | [diff] [blame] | 8130 | if (!netif_carrier_ok(tp->dev)) |
| 8131 | val = 0; |
| 8132 | |
| 8133 | tw32(HOSTCC_STAT_COAL_TICKS, val); |
| 8134 | } |
Matt Carlson | b6080e1 | 2009-09-01 13:12:00 +0000 | [diff] [blame] | 8135 | |
| 8136 | for (i = 0; i < tp->irq_cnt - 1; i++) { |
| 8137 | u32 reg; |
| 8138 | |
| 8139 | reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18; |
| 8140 | tw32(reg, ec->rx_coalesce_usecs); |
Matt Carlson | b6080e1 | 2009-09-01 13:12:00 +0000 | [diff] [blame] | 8141 | reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18; |
| 8142 | tw32(reg, ec->rx_max_coalesced_frames); |
Matt Carlson | b6080e1 | 2009-09-01 13:12:00 +0000 | [diff] [blame] | 8143 | reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; |
| 8144 | tw32(reg, ec->rx_max_coalesced_frames_irq); |
Matt Carlson | 19cfaec | 2009-12-03 08:36:20 +0000 | [diff] [blame] | 8145 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8146 | if (tg3_flag(tp, ENABLE_TSS)) { |
Matt Carlson | 19cfaec | 2009-12-03 08:36:20 +0000 | [diff] [blame] | 8147 | reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18; |
| 8148 | tw32(reg, ec->tx_coalesce_usecs); |
| 8149 | reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18; |
| 8150 | tw32(reg, ec->tx_max_coalesced_frames); |
| 8151 | reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18; |
| 8152 | tw32(reg, ec->tx_max_coalesced_frames_irq); |
| 8153 | } |
Matt Carlson | b6080e1 | 2009-09-01 13:12:00 +0000 | [diff] [blame] | 8154 | } |
| 8155 | |
| 8156 | for (; i < tp->irq_max - 1; i++) { |
| 8157 | tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0); |
Matt Carlson | b6080e1 | 2009-09-01 13:12:00 +0000 | [diff] [blame] | 8158 | tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); |
Matt Carlson | b6080e1 | 2009-09-01 13:12:00 +0000 | [diff] [blame] | 8159 | tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); |
Matt Carlson | 19cfaec | 2009-12-03 08:36:20 +0000 | [diff] [blame] | 8160 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8161 | if (tg3_flag(tp, ENABLE_TSS)) { |
Matt Carlson | 19cfaec | 2009-12-03 08:36:20 +0000 | [diff] [blame] | 8162 | tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0); |
| 8163 | tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0); |
| 8164 | tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); |
| 8165 | } |
Matt Carlson | b6080e1 | 2009-09-01 13:12:00 +0000 | [diff] [blame] | 8166 | } |
David S. Miller | 15f9850 | 2005-05-18 22:49:26 -0700 | [diff] [blame] | 8167 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8168 | |
| 8169 | /* tp->lock is held. */ |
Matt Carlson | 2d31eca | 2009-09-01 12:53:31 +0000 | [diff] [blame] | 8170 | static void tg3_rings_reset(struct tg3 *tp) |
| 8171 | { |
| 8172 | int i; |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 8173 | u32 stblk, txrcb, rxrcb, limit; |
Matt Carlson | 2d31eca | 2009-09-01 12:53:31 +0000 | [diff] [blame] | 8174 | struct tg3_napi *tnapi = &tp->napi[0]; |
| 8175 | |
| 8176 | /* Disable all transmit rings but the first. */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8177 | if (!tg3_flag(tp, 5705_PLUS)) |
Matt Carlson | 2d31eca | 2009-09-01 12:53:31 +0000 | [diff] [blame] | 8178 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8179 | else if (tg3_flag(tp, 5717_PLUS)) |
Matt Carlson | 3d37728 | 2010-10-14 10:37:39 +0000 | [diff] [blame] | 8180 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; |
Matt Carlson | 55086ad | 2011-12-14 11:09:59 +0000 | [diff] [blame] | 8181 | else if (tg3_flag(tp, 57765_CLASS)) |
Matt Carlson | b703df6 | 2009-12-03 08:36:21 +0000 | [diff] [blame] | 8182 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; |
Matt Carlson | 2d31eca | 2009-09-01 12:53:31 +0000 | [diff] [blame] | 8183 | else |
| 8184 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; |
| 8185 | |
| 8186 | for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; |
| 8187 | txrcb < limit; txrcb += TG3_BDINFO_SIZE) |
| 8188 | tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, |
| 8189 | BDINFO_FLAGS_DISABLED); |
| 8190 | |
| 8191 | |
| 8192 | /* Disable all receive return rings but the first. */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8193 | if (tg3_flag(tp, 5717_PLUS)) |
Matt Carlson | f6eb9b1 | 2009-09-01 13:19:53 +0000 | [diff] [blame] | 8194 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8195 | else if (!tg3_flag(tp, 5705_PLUS)) |
Matt Carlson | 2d31eca | 2009-09-01 12:53:31 +0000 | [diff] [blame] | 8196 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; |
Matt Carlson | b703df6 | 2009-12-03 08:36:21 +0000 | [diff] [blame] | 8197 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
Matt Carlson | 55086ad | 2011-12-14 11:09:59 +0000 | [diff] [blame] | 8198 | tg3_flag(tp, 57765_CLASS)) |
Matt Carlson | 2d31eca | 2009-09-01 12:53:31 +0000 | [diff] [blame] | 8199 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; |
| 8200 | else |
| 8201 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; |
| 8202 | |
| 8203 | for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; |
| 8204 | rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) |
| 8205 | tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, |
| 8206 | BDINFO_FLAGS_DISABLED); |
| 8207 | |
| 8208 | /* Disable interrupts */ |
| 8209 | tw32_mailbox_f(tp->napi[0].int_mbox, 1); |
Matt Carlson | 0e6cf6a | 2011-06-13 13:38:55 +0000 | [diff] [blame] | 8210 | tp->napi[0].chk_msi_cnt = 0; |
| 8211 | tp->napi[0].last_rx_cons = 0; |
| 8212 | tp->napi[0].last_tx_cons = 0; |
Matt Carlson | 2d31eca | 2009-09-01 12:53:31 +0000 | [diff] [blame] | 8213 | |
| 8214 | /* Zero mailbox registers. */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8215 | if (tg3_flag(tp, SUPPORT_MSIX)) { |
Matt Carlson | 6fd45cb | 2010-09-15 08:59:57 +0000 | [diff] [blame] | 8216 | for (i = 1; i < tp->irq_max; i++) { |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 8217 | tp->napi[i].tx_prod = 0; |
| 8218 | tp->napi[i].tx_cons = 0; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8219 | if (tg3_flag(tp, ENABLE_TSS)) |
Matt Carlson | c2353a3 | 2010-01-20 16:58:08 +0000 | [diff] [blame] | 8220 | tw32_mailbox(tp->napi[i].prodmbox, 0); |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 8221 | tw32_rx_mbox(tp->napi[i].consmbox, 0); |
| 8222 | tw32_mailbox_f(tp->napi[i].int_mbox, 1); |
Matt Carlson | 7f23073 | 2011-08-31 11:44:48 +0000 | [diff] [blame] | 8223 | tp->napi[i].chk_msi_cnt = 0; |
Matt Carlson | 0e6cf6a | 2011-06-13 13:38:55 +0000 | [diff] [blame] | 8224 | tp->napi[i].last_rx_cons = 0; |
| 8225 | tp->napi[i].last_tx_cons = 0; |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 8226 | } |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8227 | if (!tg3_flag(tp, ENABLE_TSS)) |
Matt Carlson | c2353a3 | 2010-01-20 16:58:08 +0000 | [diff] [blame] | 8228 | tw32_mailbox(tp->napi[0].prodmbox, 0); |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 8229 | } else { |
| 8230 | tp->napi[0].tx_prod = 0; |
| 8231 | tp->napi[0].tx_cons = 0; |
| 8232 | tw32_mailbox(tp->napi[0].prodmbox, 0); |
| 8233 | tw32_rx_mbox(tp->napi[0].consmbox, 0); |
| 8234 | } |
Matt Carlson | 2d31eca | 2009-09-01 12:53:31 +0000 | [diff] [blame] | 8235 | |
| 8236 | /* Make sure the NIC-based send BD rings are disabled. */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8237 | if (!tg3_flag(tp, 5705_PLUS)) { |
Matt Carlson | 2d31eca | 2009-09-01 12:53:31 +0000 | [diff] [blame] | 8238 | u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW; |
| 8239 | for (i = 0; i < 16; i++) |
| 8240 | tw32_tx_mbox(mbox + i * 8, 0); |
| 8241 | } |
| 8242 | |
| 8243 | txrcb = NIC_SRAM_SEND_RCB; |
| 8244 | rxrcb = NIC_SRAM_RCV_RET_RCB; |
| 8245 | |
| 8246 | /* Clear status block in ram. */ |
| 8247 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); |
| 8248 | |
| 8249 | /* Set status block DMA address */ |
| 8250 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, |
| 8251 | ((u64) tnapi->status_mapping >> 32)); |
| 8252 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, |
| 8253 | ((u64) tnapi->status_mapping & 0xffffffff)); |
| 8254 | |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 8255 | if (tnapi->tx_ring) { |
| 8256 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, |
| 8257 | (TG3_TX_RING_SIZE << |
| 8258 | BDINFO_FLAGS_MAXLEN_SHIFT), |
| 8259 | NIC_SRAM_TX_BUFFER_DESC); |
| 8260 | txrcb += TG3_BDINFO_SIZE; |
| 8261 | } |
Matt Carlson | 2d31eca | 2009-09-01 12:53:31 +0000 | [diff] [blame] | 8262 | |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 8263 | if (tnapi->rx_rcb) { |
| 8264 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, |
Matt Carlson | 7cb32cf | 2010-09-30 10:34:36 +0000 | [diff] [blame] | 8265 | (tp->rx_ret_ring_mask + 1) << |
| 8266 | BDINFO_FLAGS_MAXLEN_SHIFT, 0); |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 8267 | rxrcb += TG3_BDINFO_SIZE; |
| 8268 | } |
| 8269 | |
| 8270 | stblk = HOSTCC_STATBLCK_RING1; |
| 8271 | |
| 8272 | for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { |
| 8273 | u64 mapping = (u64)tnapi->status_mapping; |
| 8274 | tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32); |
| 8275 | tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff); |
| 8276 | |
| 8277 | /* Clear status block in ram. */ |
| 8278 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); |
| 8279 | |
Matt Carlson | 19cfaec | 2009-12-03 08:36:20 +0000 | [diff] [blame] | 8280 | if (tnapi->tx_ring) { |
| 8281 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, |
| 8282 | (TG3_TX_RING_SIZE << |
| 8283 | BDINFO_FLAGS_MAXLEN_SHIFT), |
| 8284 | NIC_SRAM_TX_BUFFER_DESC); |
| 8285 | txrcb += TG3_BDINFO_SIZE; |
| 8286 | } |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 8287 | |
| 8288 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, |
Matt Carlson | 7cb32cf | 2010-09-30 10:34:36 +0000 | [diff] [blame] | 8289 | ((tp->rx_ret_ring_mask + 1) << |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 8290 | BDINFO_FLAGS_MAXLEN_SHIFT), 0); |
| 8291 | |
| 8292 | stblk += 8; |
Matt Carlson | f77a6a8 | 2009-09-01 13:04:37 +0000 | [diff] [blame] | 8293 | rxrcb += TG3_BDINFO_SIZE; |
| 8294 | } |
Matt Carlson | 2d31eca | 2009-09-01 12:53:31 +0000 | [diff] [blame] | 8295 | } |
| 8296 | |
Matt Carlson | eb07a94 | 2011-04-20 07:57:36 +0000 | [diff] [blame] | 8297 | static void tg3_setup_rxbd_thresholds(struct tg3 *tp) |
| 8298 | { |
| 8299 | u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh; |
| 8300 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8301 | if (!tg3_flag(tp, 5750_PLUS) || |
| 8302 | tg3_flag(tp, 5780_CLASS) || |
Matt Carlson | eb07a94 | 2011-04-20 07:57:36 +0000 | [diff] [blame] | 8303 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || |
Matt Carlson | 513aa6e | 2011-11-21 15:01:18 +0000 | [diff] [blame] | 8304 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
| 8305 | tg3_flag(tp, 57765_PLUS)) |
Matt Carlson | eb07a94 | 2011-04-20 07:57:36 +0000 | [diff] [blame] | 8306 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700; |
| 8307 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
| 8308 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) |
| 8309 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755; |
| 8310 | else |
| 8311 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906; |
| 8312 | |
| 8313 | nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); |
| 8314 | host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); |
| 8315 | |
| 8316 | val = min(nic_rep_thresh, host_rep_thresh); |
| 8317 | tw32(RCVBDI_STD_THRESH, val); |
| 8318 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8319 | if (tg3_flag(tp, 57765_PLUS)) |
Matt Carlson | eb07a94 | 2011-04-20 07:57:36 +0000 | [diff] [blame] | 8320 | tw32(STD_REPLENISH_LWM, bdcache_maxcnt); |
| 8321 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8322 | if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) |
Matt Carlson | eb07a94 | 2011-04-20 07:57:36 +0000 | [diff] [blame] | 8323 | return; |
| 8324 | |
Matt Carlson | 513aa6e | 2011-11-21 15:01:18 +0000 | [diff] [blame] | 8325 | bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700; |
Matt Carlson | eb07a94 | 2011-04-20 07:57:36 +0000 | [diff] [blame] | 8326 | |
| 8327 | host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); |
| 8328 | |
| 8329 | val = min(bdcache_maxcnt / 2, host_rep_thresh); |
| 8330 | tw32(RCVBDI_JUMBO_THRESH, val); |
| 8331 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8332 | if (tg3_flag(tp, 57765_PLUS)) |
Matt Carlson | eb07a94 | 2011-04-20 07:57:36 +0000 | [diff] [blame] | 8333 | tw32(JMB_REPLENISH_LWM, bdcache_maxcnt); |
| 8334 | } |
| 8335 | |
Matt Carlson | ccd5ba9 | 2012-02-13 10:20:08 +0000 | [diff] [blame] | 8336 | static inline u32 calc_crc(unsigned char *buf, int len) |
| 8337 | { |
| 8338 | u32 reg; |
| 8339 | u32 tmp; |
| 8340 | int j, k; |
| 8341 | |
| 8342 | reg = 0xffffffff; |
| 8343 | |
| 8344 | for (j = 0; j < len; j++) { |
| 8345 | reg ^= buf[j]; |
| 8346 | |
| 8347 | for (k = 0; k < 8; k++) { |
| 8348 | tmp = reg & 0x01; |
| 8349 | |
| 8350 | reg >>= 1; |
| 8351 | |
| 8352 | if (tmp) |
| 8353 | reg ^= 0xedb88320; |
| 8354 | } |
| 8355 | } |
| 8356 | |
| 8357 | return ~reg; |
| 8358 | } |
| 8359 | |
| 8360 | static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) |
| 8361 | { |
| 8362 | /* accept or reject all multicast frames */ |
| 8363 | tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0); |
| 8364 | tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0); |
| 8365 | tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0); |
| 8366 | tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0); |
| 8367 | } |
| 8368 | |
| 8369 | static void __tg3_set_rx_mode(struct net_device *dev) |
| 8370 | { |
| 8371 | struct tg3 *tp = netdev_priv(dev); |
| 8372 | u32 rx_mode; |
| 8373 | |
| 8374 | rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | |
| 8375 | RX_MODE_KEEP_VLAN_TAG); |
| 8376 | |
| 8377 | #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE) |
| 8378 | /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG |
| 8379 | * flag clear. |
| 8380 | */ |
| 8381 | if (!tg3_flag(tp, ENABLE_ASF)) |
| 8382 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; |
| 8383 | #endif |
| 8384 | |
| 8385 | if (dev->flags & IFF_PROMISC) { |
| 8386 | /* Promiscuous mode. */ |
| 8387 | rx_mode |= RX_MODE_PROMISC; |
| 8388 | } else if (dev->flags & IFF_ALLMULTI) { |
| 8389 | /* Accept all multicast. */ |
| 8390 | tg3_set_multi(tp, 1); |
| 8391 | } else if (netdev_mc_empty(dev)) { |
| 8392 | /* Reject all multicast. */ |
| 8393 | tg3_set_multi(tp, 0); |
| 8394 | } else { |
| 8395 | /* Accept one or more multicast(s). */ |
| 8396 | struct netdev_hw_addr *ha; |
| 8397 | u32 mc_filter[4] = { 0, }; |
| 8398 | u32 regidx; |
| 8399 | u32 bit; |
| 8400 | u32 crc; |
| 8401 | |
| 8402 | netdev_for_each_mc_addr(ha, dev) { |
| 8403 | crc = calc_crc(ha->addr, ETH_ALEN); |
| 8404 | bit = ~crc & 0x7f; |
| 8405 | regidx = (bit & 0x60) >> 5; |
| 8406 | bit &= 0x1f; |
| 8407 | mc_filter[regidx] |= (1 << bit); |
| 8408 | } |
| 8409 | |
| 8410 | tw32(MAC_HASH_REG_0, mc_filter[0]); |
| 8411 | tw32(MAC_HASH_REG_1, mc_filter[1]); |
| 8412 | tw32(MAC_HASH_REG_2, mc_filter[2]); |
| 8413 | tw32(MAC_HASH_REG_3, mc_filter[3]); |
| 8414 | } |
| 8415 | |
| 8416 | if (rx_mode != tp->rx_mode) { |
| 8417 | tp->rx_mode = rx_mode; |
| 8418 | tw32_f(MAC_RX_MODE, rx_mode); |
| 8419 | udelay(10); |
| 8420 | } |
| 8421 | } |
| 8422 | |
Matt Carlson | 9041547 | 2011-12-16 13:33:23 +0000 | [diff] [blame] | 8423 | static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp) |
| 8424 | { |
| 8425 | int i; |
| 8426 | |
| 8427 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) |
| 8428 | tp->rss_ind_tbl[i] = |
| 8429 | ethtool_rxfh_indir_default(i, tp->irq_cnt - 1); |
| 8430 | } |
| 8431 | |
| 8432 | static void tg3_rss_check_indir_tbl(struct tg3 *tp) |
Matt Carlson | bcebcc4 | 2011-12-14 11:10:01 +0000 | [diff] [blame] | 8433 | { |
| 8434 | int i; |
| 8435 | |
| 8436 | if (!tg3_flag(tp, SUPPORT_MSIX)) |
| 8437 | return; |
| 8438 | |
Matt Carlson | 9041547 | 2011-12-16 13:33:23 +0000 | [diff] [blame] | 8439 | if (tp->irq_cnt <= 2) { |
Matt Carlson | bcebcc4 | 2011-12-14 11:10:01 +0000 | [diff] [blame] | 8440 | memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl)); |
Matt Carlson | 9041547 | 2011-12-16 13:33:23 +0000 | [diff] [blame] | 8441 | return; |
| 8442 | } |
| 8443 | |
| 8444 | /* Validate table against current IRQ count */ |
| 8445 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) { |
| 8446 | if (tp->rss_ind_tbl[i] >= tp->irq_cnt - 1) |
| 8447 | break; |
| 8448 | } |
| 8449 | |
| 8450 | if (i != TG3_RSS_INDIR_TBL_SIZE) |
| 8451 | tg3_rss_init_dflt_indir_tbl(tp); |
Matt Carlson | bcebcc4 | 2011-12-14 11:10:01 +0000 | [diff] [blame] | 8452 | } |
| 8453 | |
Matt Carlson | 9041547 | 2011-12-16 13:33:23 +0000 | [diff] [blame] | 8454 | static void tg3_rss_write_indir_tbl(struct tg3 *tp) |
Matt Carlson | bcebcc4 | 2011-12-14 11:10:01 +0000 | [diff] [blame] | 8455 | { |
| 8456 | int i = 0; |
| 8457 | u32 reg = MAC_RSS_INDIR_TBL_0; |
| 8458 | |
| 8459 | while (i < TG3_RSS_INDIR_TBL_SIZE) { |
| 8460 | u32 val = tp->rss_ind_tbl[i]; |
| 8461 | i++; |
| 8462 | for (; i % 8; i++) { |
| 8463 | val <<= 4; |
| 8464 | val |= tp->rss_ind_tbl[i]; |
| 8465 | } |
| 8466 | tw32(reg, val); |
| 8467 | reg += 4; |
| 8468 | } |
| 8469 | } |
| 8470 | |
Matt Carlson | 2d31eca | 2009-09-01 12:53:31 +0000 | [diff] [blame] | 8471 | /* tp->lock is held. */ |
Gary Zambrano | 8e7a22e | 2006-04-29 18:59:13 -0700 | [diff] [blame] | 8472 | static int tg3_reset_hw(struct tg3 *tp, int reset_phy) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8473 | { |
| 8474 | u32 val, rdmac_mode; |
| 8475 | int i, err, limit; |
Matt Carlson | 8fea32b | 2010-09-15 08:59:58 +0000 | [diff] [blame] | 8476 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8477 | |
| 8478 | tg3_disable_ints(tp); |
| 8479 | |
| 8480 | tg3_stop_fw(tp); |
| 8481 | |
| 8482 | tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); |
| 8483 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8484 | if (tg3_flag(tp, INIT_COMPLETE)) |
Michael Chan | e6de8ad | 2005-05-05 14:42:41 -0700 | [diff] [blame] | 8485 | tg3_abort_hw(tp, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8486 | |
Matt Carlson | 699c019 | 2010-12-06 08:28:51 +0000 | [diff] [blame] | 8487 | /* Enable MAC control of LPI */ |
| 8488 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) { |
| 8489 | tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, |
| 8490 | TG3_CPMU_EEE_LNKIDL_PCIE_NL0 | |
| 8491 | TG3_CPMU_EEE_LNKIDL_UART_IDL); |
| 8492 | |
| 8493 | tw32_f(TG3_CPMU_EEE_CTRL, |
| 8494 | TG3_CPMU_EEE_CTRL_EXIT_20_1_US); |
| 8495 | |
Matt Carlson | a386b90 | 2010-12-06 08:28:53 +0000 | [diff] [blame] | 8496 | val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET | |
| 8497 | TG3_CPMU_EEEMD_LPI_IN_TX | |
| 8498 | TG3_CPMU_EEEMD_LPI_IN_RX | |
| 8499 | TG3_CPMU_EEEMD_EEE_ENABLE; |
| 8500 | |
| 8501 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) |
| 8502 | val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN; |
| 8503 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8504 | if (tg3_flag(tp, ENABLE_APE)) |
Matt Carlson | a386b90 | 2010-12-06 08:28:53 +0000 | [diff] [blame] | 8505 | val |= TG3_CPMU_EEEMD_APE_TX_DET_EN; |
| 8506 | |
| 8507 | tw32_f(TG3_CPMU_EEE_MODE, val); |
| 8508 | |
| 8509 | tw32_f(TG3_CPMU_EEE_DBTMR1, |
| 8510 | TG3_CPMU_DBTMR1_PCIEXIT_2047US | |
| 8511 | TG3_CPMU_DBTMR1_LNKIDLE_2047US); |
| 8512 | |
| 8513 | tw32_f(TG3_CPMU_EEE_DBTMR2, |
Matt Carlson | d7f2ab2 | 2011-01-25 15:58:56 +0000 | [diff] [blame] | 8514 | TG3_CPMU_DBTMR2_APE_TX_2047US | |
Matt Carlson | a386b90 | 2010-12-06 08:28:53 +0000 | [diff] [blame] | 8515 | TG3_CPMU_DBTMR2_TXIDXEQ_2047US); |
Matt Carlson | 699c019 | 2010-12-06 08:28:51 +0000 | [diff] [blame] | 8516 | } |
| 8517 | |
Matt Carlson | 603f117 | 2010-02-12 14:47:10 +0000 | [diff] [blame] | 8518 | if (reset_phy) |
Michael Chan | d4d2c55 | 2006-03-20 17:47:20 -0800 | [diff] [blame] | 8519 | tg3_phy_reset(tp); |
| 8520 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8521 | err = tg3_chip_reset(tp); |
| 8522 | if (err) |
| 8523 | return err; |
| 8524 | |
| 8525 | tg3_write_sig_legacy(tp, RESET_KIND_INIT); |
| 8526 | |
Matt Carlson | bcb37f6 | 2008-11-03 16:52:09 -0800 | [diff] [blame] | 8527 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
Matt Carlson | d30cdd2 | 2007-10-07 23:28:35 -0700 | [diff] [blame] | 8528 | val = tr32(TG3_CPMU_CTRL); |
| 8529 | val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); |
| 8530 | tw32(TG3_CPMU_CTRL, val); |
Matt Carlson | 9acb961 | 2007-11-12 21:10:06 -0800 | [diff] [blame] | 8531 | |
| 8532 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); |
| 8533 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; |
| 8534 | val |= CPMU_LSPD_10MB_MACCLK_6_25; |
| 8535 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); |
| 8536 | |
| 8537 | val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); |
| 8538 | val &= ~CPMU_LNK_AWARE_MACCLK_MASK; |
| 8539 | val |= CPMU_LNK_AWARE_MACCLK_6_25; |
| 8540 | tw32(TG3_CPMU_LNK_AWARE_PWRMD, val); |
| 8541 | |
| 8542 | val = tr32(TG3_CPMU_HST_ACC); |
| 8543 | val &= ~CPMU_HST_ACC_MACCLK_MASK; |
| 8544 | val |= CPMU_HST_ACC_MACCLK_6_25; |
| 8545 | tw32(TG3_CPMU_HST_ACC, val); |
Matt Carlson | d30cdd2 | 2007-10-07 23:28:35 -0700 | [diff] [blame] | 8546 | } |
| 8547 | |
Matt Carlson | 33466d9 | 2009-04-20 06:57:41 +0000 | [diff] [blame] | 8548 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
| 8549 | val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; |
| 8550 | val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | |
| 8551 | PCIE_PWR_MGMT_L1_THRESH_4MS; |
| 8552 | tw32(PCIE_PWR_MGMT_THRESH, val); |
Matt Carlson | 521e6b9 | 2009-08-25 10:06:01 +0000 | [diff] [blame] | 8553 | |
| 8554 | val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; |
| 8555 | tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); |
| 8556 | |
| 8557 | tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); |
Matt Carlson | 33466d9 | 2009-04-20 06:57:41 +0000 | [diff] [blame] | 8558 | |
Matt Carlson | f40386c | 2009-11-02 14:24:02 +0000 | [diff] [blame] | 8559 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; |
| 8560 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); |
Matt Carlson | 255ca31 | 2009-08-25 10:07:27 +0000 | [diff] [blame] | 8561 | } |
| 8562 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8563 | if (tg3_flag(tp, L1PLLPD_EN)) { |
Matt Carlson | 614b059 | 2010-01-20 16:58:02 +0000 | [diff] [blame] | 8564 | u32 grc_mode = tr32(GRC_MODE); |
| 8565 | |
| 8566 | /* Access the lower 1K of PL PCIE block registers. */ |
| 8567 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; |
| 8568 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); |
| 8569 | |
| 8570 | val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); |
| 8571 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, |
| 8572 | val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN); |
| 8573 | |
| 8574 | tw32(GRC_MODE, grc_mode); |
| 8575 | } |
| 8576 | |
Matt Carlson | 55086ad | 2011-12-14 11:09:59 +0000 | [diff] [blame] | 8577 | if (tg3_flag(tp, 57765_CLASS)) { |
Matt Carlson | 5093eed | 2010-11-24 08:31:45 +0000 | [diff] [blame] | 8578 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { |
| 8579 | u32 grc_mode = tr32(GRC_MODE); |
Matt Carlson | cea4646 | 2010-04-12 06:58:24 +0000 | [diff] [blame] | 8580 | |
Matt Carlson | 5093eed | 2010-11-24 08:31:45 +0000 | [diff] [blame] | 8581 | /* Access the lower 1K of PL PCIE block registers. */ |
| 8582 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; |
| 8583 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); |
Matt Carlson | cea4646 | 2010-04-12 06:58:24 +0000 | [diff] [blame] | 8584 | |
Matt Carlson | 5093eed | 2010-11-24 08:31:45 +0000 | [diff] [blame] | 8585 | val = tr32(TG3_PCIE_TLDLPL_PORT + |
| 8586 | TG3_PCIE_PL_LO_PHYCTL5); |
| 8587 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, |
| 8588 | val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); |
Matt Carlson | cea4646 | 2010-04-12 06:58:24 +0000 | [diff] [blame] | 8589 | |
Matt Carlson | 5093eed | 2010-11-24 08:31:45 +0000 | [diff] [blame] | 8590 | tw32(GRC_MODE, grc_mode); |
| 8591 | } |
Matt Carlson | a977dbe | 2010-04-12 06:58:26 +0000 | [diff] [blame] | 8592 | |
Matt Carlson | 1ff30a5 | 2011-05-19 12:12:46 +0000 | [diff] [blame] | 8593 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) { |
| 8594 | u32 grc_mode = tr32(GRC_MODE); |
| 8595 | |
| 8596 | /* Access the lower 1K of DL PCIE block registers. */ |
| 8597 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; |
| 8598 | tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL); |
| 8599 | |
| 8600 | val = tr32(TG3_PCIE_TLDLPL_PORT + |
| 8601 | TG3_PCIE_DL_LO_FTSMAX); |
| 8602 | val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK; |
| 8603 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX, |
| 8604 | val | TG3_PCIE_DL_LO_FTSMAX_VAL); |
| 8605 | |
| 8606 | tw32(GRC_MODE, grc_mode); |
| 8607 | } |
| 8608 | |
Matt Carlson | a977dbe | 2010-04-12 06:58:26 +0000 | [diff] [blame] | 8609 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); |
| 8610 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; |
| 8611 | val |= CPMU_LSPD_10MB_MACCLK_6_25; |
| 8612 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); |
Matt Carlson | cea4646 | 2010-04-12 06:58:24 +0000 | [diff] [blame] | 8613 | } |
| 8614 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8615 | /* This works around an issue with Athlon chipsets on |
| 8616 | * B3 tigon3 silicon. This bit has no effect on any |
| 8617 | * other revision. But do not set this on PCI Express |
Matt Carlson | 795d01c | 2007-10-07 23:28:17 -0700 | [diff] [blame] | 8618 | * chips and don't even touch the clocks if the CPMU is present. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8619 | */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8620 | if (!tg3_flag(tp, CPMU_PRESENT)) { |
| 8621 | if (!tg3_flag(tp, PCI_EXPRESS)) |
Matt Carlson | 795d01c | 2007-10-07 23:28:17 -0700 | [diff] [blame] | 8622 | tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; |
| 8623 | tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); |
| 8624 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8625 | |
| 8626 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8627 | tg3_flag(tp, PCIX_MODE)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8628 | val = tr32(TG3PCI_PCISTATE); |
| 8629 | val |= PCISTATE_RETRY_SAME_DMA; |
| 8630 | tw32(TG3PCI_PCISTATE, val); |
| 8631 | } |
| 8632 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8633 | if (tg3_flag(tp, ENABLE_APE)) { |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 8634 | /* Allow reads and writes to the |
| 8635 | * APE register and memory space. |
| 8636 | */ |
| 8637 | val = tr32(TG3PCI_PCISTATE); |
| 8638 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | |
Matt Carlson | f92d9dc1 | 2010-06-05 17:24:30 +0000 | [diff] [blame] | 8639 | PCISTATE_ALLOW_APE_SHMEM_WR | |
| 8640 | PCISTATE_ALLOW_APE_PSPACE_WR; |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 8641 | tw32(TG3PCI_PCISTATE, val); |
| 8642 | } |
| 8643 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8644 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) { |
| 8645 | /* Enable some hw fixes. */ |
| 8646 | val = tr32(TG3PCI_MSI_DATA); |
| 8647 | val |= (1 << 26) | (1 << 28) | (1 << 29); |
| 8648 | tw32(TG3PCI_MSI_DATA, val); |
| 8649 | } |
| 8650 | |
| 8651 | /* Descriptor ring init may make accesses to the |
| 8652 | * NIC SRAM area to setup the TX descriptors, so we |
| 8653 | * can only do this after the hardware has been |
| 8654 | * successfully reset. |
| 8655 | */ |
Michael Chan | 32d8c57 | 2006-07-25 16:38:29 -0700 | [diff] [blame] | 8656 | err = tg3_init_rings(tp); |
| 8657 | if (err) |
| 8658 | return err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8659 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8660 | if (tg3_flag(tp, 57765_PLUS)) { |
Matt Carlson | cbf9ca6 | 2009-11-13 13:03:40 +0000 | [diff] [blame] | 8661 | val = tr32(TG3PCI_DMA_RW_CTRL) & |
| 8662 | ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; |
Matt Carlson | 1a31902 | 2010-04-12 06:58:25 +0000 | [diff] [blame] | 8663 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) |
| 8664 | val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; |
Matt Carlson | 55086ad | 2011-12-14 11:09:59 +0000 | [diff] [blame] | 8665 | if (!tg3_flag(tp, 57765_CLASS) && |
Matt Carlson | 0aebff4 | 2011-04-25 12:42:45 +0000 | [diff] [blame] | 8666 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) |
| 8667 | val |= DMA_RWCTRL_TAGGED_STAT_WA; |
Matt Carlson | cbf9ca6 | 2009-11-13 13:03:40 +0000 | [diff] [blame] | 8668 | tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); |
| 8669 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && |
| 8670 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { |
Matt Carlson | d30cdd2 | 2007-10-07 23:28:35 -0700 | [diff] [blame] | 8671 | /* This value is determined during the probe time DMA |
| 8672 | * engine test, tg3_test_dma. |
| 8673 | */ |
| 8674 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); |
| 8675 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8676 | |
| 8677 | tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | |
| 8678 | GRC_MODE_4X_NIC_SEND_RINGS | |
| 8679 | GRC_MODE_NO_TX_PHDR_CSUM | |
| 8680 | GRC_MODE_NO_RX_PHDR_CSUM); |
| 8681 | tp->grc_mode |= GRC_MODE_HOST_SENDBDS; |
Michael Chan | d2d746f | 2006-04-06 21:45:39 -0700 | [diff] [blame] | 8682 | |
| 8683 | /* Pseudo-header checksum is done by hardware logic and not |
| 8684 | * the offload processers, so make the chip do the pseudo- |
| 8685 | * header checksums on receive. For transmit it is more |
| 8686 | * convenient to do the pseudo-header checksum in software |
| 8687 | * as Linux does that on transmit for us in all cases. |
| 8688 | */ |
| 8689 | tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8690 | |
| 8691 | tw32(GRC_MODE, |
| 8692 | tp->grc_mode | |
| 8693 | (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP)); |
| 8694 | |
| 8695 | /* Setup the timer prescalar register. Clock is always 66Mhz. */ |
| 8696 | val = tr32(GRC_MISC_CFG); |
| 8697 | val &= ~0xff; |
| 8698 | val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT); |
| 8699 | tw32(GRC_MISC_CFG, val); |
| 8700 | |
| 8701 | /* Initialize MBUF/DESC pool. */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8702 | if (tg3_flag(tp, 5750_PLUS)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8703 | /* Do nothing. */ |
| 8704 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { |
| 8705 | tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); |
| 8706 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) |
| 8707 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); |
| 8708 | else |
| 8709 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); |
| 8710 | tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); |
| 8711 | tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8712 | } else if (tg3_flag(tp, TSO_CAPABLE)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8713 | int fw_len; |
| 8714 | |
Jaswinder Singh Rajput | 077f849 | 2009-01-04 16:11:25 -0800 | [diff] [blame] | 8715 | fw_len = tp->fw_len; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8716 | fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); |
| 8717 | tw32(BUFMGR_MB_POOL_ADDR, |
| 8718 | NIC_SRAM_MBUF_POOL_BASE5705 + fw_len); |
| 8719 | tw32(BUFMGR_MB_POOL_SIZE, |
| 8720 | NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); |
| 8721 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8722 | |
Michael Chan | 0f893dc | 2005-07-25 12:30:38 -0700 | [diff] [blame] | 8723 | if (tp->dev->mtu <= ETH_DATA_LEN) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8724 | tw32(BUFMGR_MB_RDMA_LOW_WATER, |
| 8725 | tp->bufmgr_config.mbuf_read_dma_low_water); |
| 8726 | tw32(BUFMGR_MB_MACRX_LOW_WATER, |
| 8727 | tp->bufmgr_config.mbuf_mac_rx_low_water); |
| 8728 | tw32(BUFMGR_MB_HIGH_WATER, |
| 8729 | tp->bufmgr_config.mbuf_high_water); |
| 8730 | } else { |
| 8731 | tw32(BUFMGR_MB_RDMA_LOW_WATER, |
| 8732 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); |
| 8733 | tw32(BUFMGR_MB_MACRX_LOW_WATER, |
| 8734 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); |
| 8735 | tw32(BUFMGR_MB_HIGH_WATER, |
| 8736 | tp->bufmgr_config.mbuf_high_water_jumbo); |
| 8737 | } |
| 8738 | tw32(BUFMGR_DMA_LOW_WATER, |
| 8739 | tp->bufmgr_config.dma_low_water); |
| 8740 | tw32(BUFMGR_DMA_HIGH_WATER, |
| 8741 | tp->bufmgr_config.dma_high_water); |
| 8742 | |
Matt Carlson | d309a46 | 2010-09-30 10:34:31 +0000 | [diff] [blame] | 8743 | val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE; |
| 8744 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) |
| 8745 | val |= BUFMGR_MODE_NO_TX_UNDERRUN; |
Matt Carlson | 4d95847 | 2011-04-20 07:57:35 +0000 | [diff] [blame] | 8746 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
| 8747 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || |
| 8748 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) |
| 8749 | val |= BUFMGR_MODE_MBLOW_ATTN_ENAB; |
Matt Carlson | d309a46 | 2010-09-30 10:34:31 +0000 | [diff] [blame] | 8750 | tw32(BUFMGR_MODE, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8751 | for (i = 0; i < 2000; i++) { |
| 8752 | if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) |
| 8753 | break; |
| 8754 | udelay(10); |
| 8755 | } |
| 8756 | if (i >= 2000) { |
Joe Perches | 05dbe00 | 2010-02-17 19:44:19 +0000 | [diff] [blame] | 8757 | netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8758 | return -ENODEV; |
| 8759 | } |
| 8760 | |
Matt Carlson | eb07a94 | 2011-04-20 07:57:36 +0000 | [diff] [blame] | 8761 | if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1) |
| 8762 | tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); |
Michael Chan | b5d3772 | 2006-09-27 16:06:21 -0700 | [diff] [blame] | 8763 | |
Matt Carlson | eb07a94 | 2011-04-20 07:57:36 +0000 | [diff] [blame] | 8764 | tg3_setup_rxbd_thresholds(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8765 | |
| 8766 | /* Initialize TG3_BDINFO's at: |
| 8767 | * RCVDBDI_STD_BD: standard eth size rx ring |
| 8768 | * RCVDBDI_JUMBO_BD: jumbo frame rx ring |
| 8769 | * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) |
| 8770 | * |
| 8771 | * like so: |
| 8772 | * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring |
| 8773 | * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | |
| 8774 | * ring attribute flags |
| 8775 | * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM |
| 8776 | * |
| 8777 | * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. |
| 8778 | * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. |
| 8779 | * |
| 8780 | * The size of each ring is fixed in the firmware, but the location is |
| 8781 | * configurable. |
| 8782 | */ |
| 8783 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 8784 | ((u64) tpr->rx_std_mapping >> 32)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8785 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 8786 | ((u64) tpr->rx_std_mapping & 0xffffffff)); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8787 | if (!tg3_flag(tp, 5717_PLUS)) |
Matt Carlson | 87668d3 | 2009-11-13 13:03:34 +0000 | [diff] [blame] | 8788 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, |
| 8789 | NIC_SRAM_RX_BUFFER_DESC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8790 | |
Matt Carlson | fdb72b3 | 2009-08-28 13:57:12 +0000 | [diff] [blame] | 8791 | /* Disable the mini ring */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8792 | if (!tg3_flag(tp, 5705_PLUS)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8793 | tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, |
| 8794 | BDINFO_FLAGS_DISABLED); |
| 8795 | |
Matt Carlson | fdb72b3 | 2009-08-28 13:57:12 +0000 | [diff] [blame] | 8796 | /* Program the jumbo buffer descriptor ring control |
| 8797 | * blocks on those devices that have them. |
| 8798 | */ |
Matt Carlson | a051294 | 2011-07-27 14:20:54 +0000 | [diff] [blame] | 8799 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8800 | (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8801 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8802 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8803 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 8804 | ((u64) tpr->rx_jmb_mapping >> 32)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8805 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
Matt Carlson | 21f581a | 2009-08-28 14:00:25 +0000 | [diff] [blame] | 8806 | ((u64) tpr->rx_jmb_mapping & 0xffffffff)); |
Matt Carlson | de9f523 | 2011-04-05 14:22:43 +0000 | [diff] [blame] | 8807 | val = TG3_RX_JMB_RING_SIZE(tp) << |
| 8808 | BDINFO_FLAGS_MAXLEN_SHIFT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8809 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, |
Matt Carlson | de9f523 | 2011-04-05 14:22:43 +0000 | [diff] [blame] | 8810 | val | BDINFO_FLAGS_USE_EXT_RECV); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8811 | if (!tg3_flag(tp, USE_JUMBO_BDFLAG) || |
Matt Carlson | 55086ad | 2011-12-14 11:09:59 +0000 | [diff] [blame] | 8812 | tg3_flag(tp, 57765_CLASS)) |
Matt Carlson | 87668d3 | 2009-11-13 13:03:34 +0000 | [diff] [blame] | 8813 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, |
| 8814 | NIC_SRAM_RX_JUMBO_BUFFER_DESC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8815 | } else { |
| 8816 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, |
| 8817 | BDINFO_FLAGS_DISABLED); |
| 8818 | } |
| 8819 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8820 | if (tg3_flag(tp, 57765_PLUS)) { |
Matt Carlson | fa6b2aa | 2011-11-21 15:01:19 +0000 | [diff] [blame] | 8821 | val = TG3_RX_STD_RING_SIZE(tp); |
Matt Carlson | 7cb32cf | 2010-09-30 10:34:36 +0000 | [diff] [blame] | 8822 | val <<= BDINFO_FLAGS_MAXLEN_SHIFT; |
| 8823 | val |= (TG3_RX_STD_DMA_SZ << 2); |
| 8824 | } else |
Matt Carlson | 04380d4 | 2010-04-12 06:58:29 +0000 | [diff] [blame] | 8825 | val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT; |
Matt Carlson | fdb72b3 | 2009-08-28 13:57:12 +0000 | [diff] [blame] | 8826 | } else |
Matt Carlson | de9f523 | 2011-04-05 14:22:43 +0000 | [diff] [blame] | 8827 | val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT; |
Matt Carlson | fdb72b3 | 2009-08-28 13:57:12 +0000 | [diff] [blame] | 8828 | |
| 8829 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8830 | |
Matt Carlson | 411da64 | 2009-11-13 13:03:46 +0000 | [diff] [blame] | 8831 | tpr->rx_std_prod_idx = tp->rx_pending; |
Matt Carlson | 66711e6 | 2009-11-13 13:03:49 +0000 | [diff] [blame] | 8832 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8833 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8834 | tpr->rx_jmb_prod_idx = |
| 8835 | tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; |
Matt Carlson | 66711e6 | 2009-11-13 13:03:49 +0000 | [diff] [blame] | 8836 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8837 | |
Matt Carlson | 2d31eca | 2009-09-01 12:53:31 +0000 | [diff] [blame] | 8838 | tg3_rings_reset(tp); |
| 8839 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8840 | /* Initialize MAC address and backoff seed. */ |
Michael Chan | 986e0ae | 2007-05-05 12:10:20 -0700 | [diff] [blame] | 8841 | __tg3_set_mac_addr(tp, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8842 | |
| 8843 | /* MTU + ethernet header + FCS + optional VLAN tag */ |
Matt Carlson | f7b493e | 2009-02-25 14:21:52 +0000 | [diff] [blame] | 8844 | tw32(MAC_RX_MTU_SIZE, |
| 8845 | tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8846 | |
| 8847 | /* The slot time is changed by tg3_setup_phy if we |
| 8848 | * run at gigabit with half duplex. |
| 8849 | */ |
Matt Carlson | f2096f9 | 2011-04-05 14:22:48 +0000 | [diff] [blame] | 8850 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
| 8851 | (6 << TX_LENGTHS_IPG_SHIFT) | |
| 8852 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT); |
| 8853 | |
| 8854 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
| 8855 | val |= tr32(MAC_TX_LENGTHS) & |
| 8856 | (TX_LENGTHS_JMB_FRM_LEN_MSK | |
| 8857 | TX_LENGTHS_CNT_DWN_VAL_MSK); |
| 8858 | |
| 8859 | tw32(MAC_TX_LENGTHS, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8860 | |
| 8861 | /* Receive rules. */ |
| 8862 | tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS); |
| 8863 | tw32(RCVLPC_CONFIG, 0x0181); |
| 8864 | |
| 8865 | /* Calculate RDMAC_MODE setting early, we need it to determine |
| 8866 | * the RCVLPC_STATE_ENABLE mask. |
| 8867 | */ |
| 8868 | rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB | |
| 8869 | RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB | |
| 8870 | RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB | |
| 8871 | RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | |
| 8872 | RDMAC_MODE_LNGREAD_ENAB); |
Michael Chan | 85e94ce | 2005-04-21 17:05:28 -0700 | [diff] [blame] | 8873 | |
Matt Carlson | deabaac | 2010-11-24 08:31:50 +0000 | [diff] [blame] | 8874 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
Matt Carlson | 0339e4e | 2010-02-12 14:47:09 +0000 | [diff] [blame] | 8875 | rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS; |
| 8876 | |
Matt Carlson | 57e6983 | 2008-05-25 23:48:31 -0700 | [diff] [blame] | 8877 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 8878 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
| 8879 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
Matt Carlson | d30cdd2 | 2007-10-07 23:28:35 -0700 | [diff] [blame] | 8880 | rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | |
| 8881 | RDMAC_MODE_MBUF_RBD_CRPT_ENAB | |
| 8882 | RDMAC_MODE_MBUF_SBD_CRPT_ENAB; |
| 8883 | |
Matt Carlson | c590893 | 2011-03-09 16:58:25 +0000 | [diff] [blame] | 8884 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
| 8885 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8886 | if (tg3_flag(tp, TSO_CAPABLE) && |
Matt Carlson | c13e371 | 2007-05-05 11:50:04 -0700 | [diff] [blame] | 8887 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8888 | rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; |
| 8889 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8890 | !tg3_flag(tp, IS_5788)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8891 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; |
| 8892 | } |
| 8893 | } |
| 8894 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8895 | if (tg3_flag(tp, PCI_EXPRESS)) |
Michael Chan | 85e94ce | 2005-04-21 17:05:28 -0700 | [diff] [blame] | 8896 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; |
| 8897 | |
Matt Carlson | 55086ad | 2011-12-14 11:09:59 +0000 | [diff] [blame] | 8898 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) |
| 8899 | rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR; |
| 8900 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8901 | if (tg3_flag(tp, HW_TSO_1) || |
| 8902 | tg3_flag(tp, HW_TSO_2) || |
| 8903 | tg3_flag(tp, HW_TSO_3)) |
Matt Carlson | 027455a | 2008-12-21 20:19:30 -0800 | [diff] [blame] | 8904 | rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; |
| 8905 | |
Matt Carlson | 108a6c1 | 2011-05-19 12:12:47 +0000 | [diff] [blame] | 8906 | if (tg3_flag(tp, 57765_PLUS) || |
Matt Carlson | e849cdc | 2009-11-13 13:03:38 +0000 | [diff] [blame] | 8907 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
Matt Carlson | 027455a | 2008-12-21 20:19:30 -0800 | [diff] [blame] | 8908 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
| 8909 | rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8910 | |
Matt Carlson | f2096f9 | 2011-04-05 14:22:48 +0000 | [diff] [blame] | 8911 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
| 8912 | rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET; |
| 8913 | |
Matt Carlson | 41a8a7e | 2010-09-15 08:59:53 +0000 | [diff] [blame] | 8914 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
| 8915 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
| 8916 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
| 8917 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8918 | tg3_flag(tp, 57765_PLUS)) { |
Matt Carlson | 41a8a7e | 2010-09-15 08:59:53 +0000 | [diff] [blame] | 8919 | val = tr32(TG3_RDMA_RSRVCTRL_REG); |
Matt Carlson | d78b59f | 2011-04-05 14:22:46 +0000 | [diff] [blame] | 8920 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
| 8921 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { |
Matt Carlson | b4495ed | 2011-01-25 15:58:47 +0000 | [diff] [blame] | 8922 | val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK | |
| 8923 | TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK | |
| 8924 | TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK); |
| 8925 | val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B | |
| 8926 | TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K | |
| 8927 | TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K; |
Matt Carlson | b75cc0e | 2010-11-24 08:31:46 +0000 | [diff] [blame] | 8928 | } |
Matt Carlson | 41a8a7e | 2010-09-15 08:59:53 +0000 | [diff] [blame] | 8929 | tw32(TG3_RDMA_RSRVCTRL_REG, |
| 8930 | val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); |
| 8931 | } |
| 8932 | |
Matt Carlson | d78b59f | 2011-04-05 14:22:46 +0000 | [diff] [blame] | 8933 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
| 8934 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { |
Matt Carlson | d309a46 | 2010-09-30 10:34:31 +0000 | [diff] [blame] | 8935 | val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); |
| 8936 | tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val | |
| 8937 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K | |
| 8938 | TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K); |
| 8939 | } |
| 8940 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8941 | /* Receive/send statistics. */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8942 | if (tg3_flag(tp, 5750_PLUS)) { |
Michael Chan | 1661394 | 2006-06-29 20:15:13 -0700 | [diff] [blame] | 8943 | val = tr32(RCVLPC_STATS_ENABLE); |
| 8944 | val &= ~RCVLPC_STATSENAB_DACK_FIX; |
| 8945 | tw32(RCVLPC_STATS_ENABLE, val); |
| 8946 | } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8947 | tg3_flag(tp, TSO_CAPABLE)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8948 | val = tr32(RCVLPC_STATS_ENABLE); |
| 8949 | val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX; |
| 8950 | tw32(RCVLPC_STATS_ENABLE, val); |
| 8951 | } else { |
| 8952 | tw32(RCVLPC_STATS_ENABLE, 0xffffff); |
| 8953 | } |
| 8954 | tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE); |
| 8955 | tw32(SNDDATAI_STATSENAB, 0xffffff); |
| 8956 | tw32(SNDDATAI_STATSCTRL, |
| 8957 | (SNDDATAI_SCTRL_ENABLE | |
| 8958 | SNDDATAI_SCTRL_FASTUPD)); |
| 8959 | |
| 8960 | /* Setup host coalescing engine. */ |
| 8961 | tw32(HOSTCC_MODE, 0); |
| 8962 | for (i = 0; i < 2000; i++) { |
| 8963 | if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) |
| 8964 | break; |
| 8965 | udelay(10); |
| 8966 | } |
| 8967 | |
Michael Chan | d244c89 | 2005-07-05 14:42:33 -0700 | [diff] [blame] | 8968 | __tg3_set_coalesce(tp, &tp->coal); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8969 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8970 | if (!tg3_flag(tp, 5705_PLUS)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8971 | /* Status/statistics block address. See tg3_timer, |
| 8972 | * the tg3_periodic_fetch_stats call there, and |
| 8973 | * tg3_get_stats to see how this works for 5705/5750 chips. |
| 8974 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8975 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, |
| 8976 | ((u64) tp->stats_mapping >> 32)); |
| 8977 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, |
| 8978 | ((u64) tp->stats_mapping & 0xffffffff)); |
| 8979 | tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK); |
Matt Carlson | 2d31eca | 2009-09-01 12:53:31 +0000 | [diff] [blame] | 8980 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8981 | tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK); |
Matt Carlson | 2d31eca | 2009-09-01 12:53:31 +0000 | [diff] [blame] | 8982 | |
| 8983 | /* Clear statistics and status block memory areas */ |
| 8984 | for (i = NIC_SRAM_STATS_BLK; |
| 8985 | i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE; |
| 8986 | i += sizeof(u32)) { |
| 8987 | tg3_write_mem(tp, i, 0); |
| 8988 | udelay(40); |
| 8989 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8990 | } |
| 8991 | |
| 8992 | tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); |
| 8993 | |
| 8994 | tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE); |
| 8995 | tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 8996 | if (!tg3_flag(tp, 5705_PLUS)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8997 | tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE); |
| 8998 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 8999 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
| 9000 | tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; |
Michael Chan | c94e394 | 2005-09-27 12:12:42 -0700 | [diff] [blame] | 9001 | /* reset to prevent losing 1st rx packet intermittently */ |
| 9002 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
| 9003 | udelay(10); |
| 9004 | } |
| 9005 | |
Matt Carlson | 3bda125 | 2008-08-15 14:08:22 -0700 | [diff] [blame] | 9006 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | |
Matt Carlson | 9e975cc | 2011-07-20 10:20:50 +0000 | [diff] [blame] | 9007 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | |
| 9008 | MAC_MODE_FHDE_ENABLE; |
| 9009 | if (tg3_flag(tp, ENABLE_APE)) |
| 9010 | tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9011 | if (!tg3_flag(tp, 5705_PLUS) && |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 9012 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
Matt Carlson | e8f3f6c | 2007-07-11 19:47:55 -0700 | [diff] [blame] | 9013 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
| 9014 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9015 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); |
| 9016 | udelay(40); |
| 9017 | |
Michael Chan | 314fba3 | 2005-04-21 17:07:04 -0700 | [diff] [blame] | 9018 | /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9019 | * If TG3_FLAG_IS_NIC is zero, we should read the |
Michael Chan | 314fba3 | 2005-04-21 17:07:04 -0700 | [diff] [blame] | 9020 | * register to preserve the GPIO settings for LOMs. The GPIOs, |
| 9021 | * whether used as inputs or outputs, are set by boot code after |
| 9022 | * reset. |
| 9023 | */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9024 | if (!tg3_flag(tp, IS_NIC)) { |
Michael Chan | 314fba3 | 2005-04-21 17:07:04 -0700 | [diff] [blame] | 9025 | u32 gpio_mask; |
| 9026 | |
Michael Chan | 9d26e21 | 2006-12-07 00:21:14 -0800 | [diff] [blame] | 9027 | gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 | |
| 9028 | GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 | |
| 9029 | GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2; |
Michael Chan | 3e7d83b | 2005-04-21 17:10:36 -0700 | [diff] [blame] | 9030 | |
| 9031 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) |
| 9032 | gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | |
| 9033 | GRC_LCLCTRL_GPIO_OUTPUT3; |
| 9034 | |
Michael Chan | af36e6b | 2006-03-23 01:28:06 -0800 | [diff] [blame] | 9035 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
| 9036 | gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; |
| 9037 | |
Gary Zambrano | aaf8446 | 2007-05-05 11:51:45 -0700 | [diff] [blame] | 9038 | tp->grc_local_ctrl &= ~gpio_mask; |
Michael Chan | 314fba3 | 2005-04-21 17:07:04 -0700 | [diff] [blame] | 9039 | tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; |
| 9040 | |
| 9041 | /* GPIO1 must be driven high for eeprom write protect */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9042 | if (tg3_flag(tp, EEPROM_WRITE_PROT)) |
Michael Chan | 9d26e21 | 2006-12-07 00:21:14 -0800 | [diff] [blame] | 9043 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | |
| 9044 | GRC_LCLCTRL_GPIO_OUTPUT1); |
Michael Chan | 314fba3 | 2005-04-21 17:07:04 -0700 | [diff] [blame] | 9045 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9046 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
| 9047 | udelay(100); |
| 9048 | |
Matt Carlson | c3b5003 | 2012-01-17 15:27:23 +0000 | [diff] [blame] | 9049 | if (tg3_flag(tp, USING_MSIX)) { |
Matt Carlson | baf8a94 | 2009-09-01 13:13:00 +0000 | [diff] [blame] | 9050 | val = tr32(MSGINT_MODE); |
Matt Carlson | c3b5003 | 2012-01-17 15:27:23 +0000 | [diff] [blame] | 9051 | val |= MSGINT_MODE_ENABLE; |
| 9052 | if (tp->irq_cnt > 1) |
| 9053 | val |= MSGINT_MODE_MULTIVEC_EN; |
Matt Carlson | 5b39de9 | 2011-08-31 11:44:50 +0000 | [diff] [blame] | 9054 | if (!tg3_flag(tp, 1SHOT_MSI)) |
| 9055 | val |= MSGINT_MODE_ONE_SHOT_DISABLE; |
Matt Carlson | baf8a94 | 2009-09-01 13:13:00 +0000 | [diff] [blame] | 9056 | tw32(MSGINT_MODE, val); |
| 9057 | } |
| 9058 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9059 | if (!tg3_flag(tp, 5705_PLUS)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9060 | tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); |
| 9061 | udelay(40); |
| 9062 | } |
| 9063 | |
| 9064 | val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB | |
| 9065 | WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB | |
| 9066 | WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB | |
| 9067 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | |
| 9068 | WDMAC_MODE_LNGREAD_ENAB); |
| 9069 | |
Matt Carlson | c590893 | 2011-03-09 16:58:25 +0000 | [diff] [blame] | 9070 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
| 9071 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9072 | if (tg3_flag(tp, TSO_CAPABLE) && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9073 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || |
| 9074 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { |
| 9075 | /* nothing */ |
| 9076 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9077 | !tg3_flag(tp, IS_5788)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9078 | val |= WDMAC_MODE_RX_ACCEL; |
| 9079 | } |
| 9080 | } |
| 9081 | |
Michael Chan | d9ab5ad | 2006-03-20 22:27:35 -0800 | [diff] [blame] | 9082 | /* Enable host coalescing bug fix */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9083 | if (tg3_flag(tp, 5755_PLUS)) |
Matt Carlson | f51f356 | 2008-05-25 23:45:08 -0700 | [diff] [blame] | 9084 | val |= WDMAC_MODE_STATUS_TAG_FIX; |
Michael Chan | d9ab5ad | 2006-03-20 22:27:35 -0800 | [diff] [blame] | 9085 | |
Matt Carlson | 788a035 | 2009-11-02 14:26:03 +0000 | [diff] [blame] | 9086 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
| 9087 | val |= WDMAC_MODE_BURST_ALL_DATA; |
| 9088 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9089 | tw32_f(WDMAC_MODE, val); |
| 9090 | udelay(40); |
| 9091 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9092 | if (tg3_flag(tp, PCIX_MODE)) { |
Matt Carlson | 9974a35 | 2007-10-07 23:27:28 -0700 | [diff] [blame] | 9093 | u16 pcix_cmd; |
| 9094 | |
| 9095 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, |
| 9096 | &pcix_cmd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9097 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { |
Matt Carlson | 9974a35 | 2007-10-07 23:27:28 -0700 | [diff] [blame] | 9098 | pcix_cmd &= ~PCI_X_CMD_MAX_READ; |
| 9099 | pcix_cmd |= PCI_X_CMD_READ_2K; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9100 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
Matt Carlson | 9974a35 | 2007-10-07 23:27:28 -0700 | [diff] [blame] | 9101 | pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ); |
| 9102 | pcix_cmd |= PCI_X_CMD_READ_2K; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9103 | } |
Matt Carlson | 9974a35 | 2007-10-07 23:27:28 -0700 | [diff] [blame] | 9104 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, |
| 9105 | pcix_cmd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9106 | } |
| 9107 | |
| 9108 | tw32_f(RDMAC_MODE, rdmac_mode); |
| 9109 | udelay(40); |
| 9110 | |
| 9111 | tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9112 | if (!tg3_flag(tp, 5705_PLUS)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9113 | tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); |
Matt Carlson | 9936bcf | 2007-10-10 18:03:07 -0700 | [diff] [blame] | 9114 | |
| 9115 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
| 9116 | tw32(SNDDATAC_MODE, |
| 9117 | SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY); |
| 9118 | else |
| 9119 | tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); |
| 9120 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9121 | tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); |
| 9122 | tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); |
Matt Carlson | 7cb32cf | 2010-09-30 10:34:36 +0000 | [diff] [blame] | 9123 | val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9124 | if (tg3_flag(tp, LRG_PROD_RING_CAP)) |
Matt Carlson | 7cb32cf | 2010-09-30 10:34:36 +0000 | [diff] [blame] | 9125 | val |= RCVDBDI_MODE_LRG_RING_SZ; |
| 9126 | tw32(RCVDBDI_MODE, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9127 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9128 | if (tg3_flag(tp, HW_TSO_1) || |
| 9129 | tg3_flag(tp, HW_TSO_2) || |
| 9130 | tg3_flag(tp, HW_TSO_3)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9131 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); |
Matt Carlson | baf8a94 | 2009-09-01 13:13:00 +0000 | [diff] [blame] | 9132 | val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9133 | if (tg3_flag(tp, ENABLE_TSS)) |
Matt Carlson | baf8a94 | 2009-09-01 13:13:00 +0000 | [diff] [blame] | 9134 | val |= SNDBDI_MODE_MULTI_TXQ_EN; |
| 9135 | tw32(SNDBDI_MODE, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9136 | tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); |
| 9137 | |
| 9138 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { |
| 9139 | err = tg3_load_5701_a0_firmware_fix(tp); |
| 9140 | if (err) |
| 9141 | return err; |
| 9142 | } |
| 9143 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9144 | if (tg3_flag(tp, TSO_CAPABLE)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9145 | err = tg3_load_tso_firmware(tp); |
| 9146 | if (err) |
| 9147 | return err; |
| 9148 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9149 | |
| 9150 | tp->tx_mode = TX_MODE_ENABLE; |
Matt Carlson | f2096f9 | 2011-04-05 14:22:48 +0000 | [diff] [blame] | 9151 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9152 | if (tg3_flag(tp, 5755_PLUS) || |
Matt Carlson | b1d0521 | 2010-06-05 17:24:31 +0000 | [diff] [blame] | 9153 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
| 9154 | tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; |
Matt Carlson | f2096f9 | 2011-04-05 14:22:48 +0000 | [diff] [blame] | 9155 | |
| 9156 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { |
| 9157 | val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE; |
| 9158 | tp->tx_mode &= ~val; |
| 9159 | tp->tx_mode |= tr32(MAC_TX_MODE) & val; |
| 9160 | } |
| 9161 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9162 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
| 9163 | udelay(100); |
| 9164 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9165 | if (tg3_flag(tp, ENABLE_RSS)) { |
Matt Carlson | bcebcc4 | 2011-12-14 11:10:01 +0000 | [diff] [blame] | 9166 | tg3_rss_write_indir_tbl(tp); |
Matt Carlson | baf8a94 | 2009-09-01 13:13:00 +0000 | [diff] [blame] | 9167 | |
| 9168 | /* Setup the "secret" hash key. */ |
| 9169 | tw32(MAC_RSS_HASH_KEY_0, 0x5f865437); |
| 9170 | tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc); |
| 9171 | tw32(MAC_RSS_HASH_KEY_2, 0x50103a45); |
| 9172 | tw32(MAC_RSS_HASH_KEY_3, 0x36621985); |
| 9173 | tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8); |
| 9174 | tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e); |
| 9175 | tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556); |
| 9176 | tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe); |
| 9177 | tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7); |
| 9178 | tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481); |
| 9179 | } |
| 9180 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9181 | tp->rx_mode = RX_MODE_ENABLE; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9182 | if (tg3_flag(tp, 5755_PLUS)) |
Michael Chan | af36e6b | 2006-03-23 01:28:06 -0800 | [diff] [blame] | 9183 | tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; |
| 9184 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9185 | if (tg3_flag(tp, ENABLE_RSS)) |
Matt Carlson | baf8a94 | 2009-09-01 13:13:00 +0000 | [diff] [blame] | 9186 | tp->rx_mode |= RX_MODE_RSS_ENABLE | |
| 9187 | RX_MODE_RSS_ITBL_HASH_BITS_7 | |
| 9188 | RX_MODE_RSS_IPV6_HASH_EN | |
| 9189 | RX_MODE_RSS_TCP_IPV6_HASH_EN | |
| 9190 | RX_MODE_RSS_IPV4_HASH_EN | |
| 9191 | RX_MODE_RSS_TCP_IPV4_HASH_EN; |
| 9192 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9193 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
| 9194 | udelay(10); |
| 9195 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9196 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
| 9197 | |
| 9198 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 9199 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9200 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
| 9201 | udelay(10); |
| 9202 | } |
| 9203 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
| 9204 | udelay(10); |
| 9205 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 9206 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9207 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 9208 | !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9209 | /* Set drive transmission level to 1.2V */ |
| 9210 | /* only if the signal pre-emphasis bit is not set */ |
| 9211 | val = tr32(MAC_SERDES_CFG); |
| 9212 | val &= 0xfffff000; |
| 9213 | val |= 0x880; |
| 9214 | tw32(MAC_SERDES_CFG, val); |
| 9215 | } |
| 9216 | if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) |
| 9217 | tw32(MAC_SERDES_CFG, 0x616000); |
| 9218 | } |
| 9219 | |
| 9220 | /* Prevent chip from dropping frames when flow control |
| 9221 | * is enabled. |
| 9222 | */ |
Matt Carlson | 55086ad | 2011-12-14 11:09:59 +0000 | [diff] [blame] | 9223 | if (tg3_flag(tp, 57765_CLASS)) |
Matt Carlson | 666bc83 | 2010-01-20 16:58:03 +0000 | [diff] [blame] | 9224 | val = 1; |
| 9225 | else |
| 9226 | val = 2; |
| 9227 | tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9228 | |
| 9229 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 9230 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9231 | /* Use hardware link auto-negotiation */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9232 | tg3_flag_set(tp, HW_AUTONEG); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9233 | } |
| 9234 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 9235 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
Matt Carlson | 6ff6f81 | 2011-05-19 12:12:54 +0000 | [diff] [blame] | 9236 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
Michael Chan | d4d2c55 | 2006-03-20 17:47:20 -0800 | [diff] [blame] | 9237 | u32 tmp; |
| 9238 | |
| 9239 | tmp = tr32(SERDES_RX_CTRL); |
| 9240 | tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT); |
| 9241 | tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; |
| 9242 | tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; |
| 9243 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
| 9244 | } |
| 9245 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9246 | if (!tg3_flag(tp, USE_PHYLIB)) { |
Matt Carlson | 80096068 | 2010-08-02 11:26:06 +0000 | [diff] [blame] | 9247 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { |
| 9248 | tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; |
Matt Carlson | dd47700 | 2008-05-25 23:45:58 -0700 | [diff] [blame] | 9249 | tp->link_config.speed = tp->link_config.orig_speed; |
| 9250 | tp->link_config.duplex = tp->link_config.orig_duplex; |
| 9251 | tp->link_config.autoneg = tp->link_config.orig_autoneg; |
| 9252 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9253 | |
Matt Carlson | dd47700 | 2008-05-25 23:45:58 -0700 | [diff] [blame] | 9254 | err = tg3_setup_phy(tp, 0); |
| 9255 | if (err) |
| 9256 | return err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9257 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 9258 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
| 9259 | !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { |
Matt Carlson | dd47700 | 2008-05-25 23:45:58 -0700 | [diff] [blame] | 9260 | u32 tmp; |
| 9261 | |
| 9262 | /* Clear CRC stats. */ |
| 9263 | if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { |
| 9264 | tg3_writephy(tp, MII_TG3_TEST1, |
| 9265 | tmp | MII_TG3_TEST1_CRC_EN); |
Matt Carlson | f08aa1a | 2010-08-02 11:26:05 +0000 | [diff] [blame] | 9266 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp); |
Matt Carlson | dd47700 | 2008-05-25 23:45:58 -0700 | [diff] [blame] | 9267 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9268 | } |
| 9269 | } |
| 9270 | |
| 9271 | __tg3_set_rx_mode(tp->dev); |
| 9272 | |
| 9273 | /* Initialize receive rules. */ |
| 9274 | tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); |
| 9275 | tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); |
| 9276 | tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); |
| 9277 | tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); |
| 9278 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9279 | if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9280 | limit = 8; |
| 9281 | else |
| 9282 | limit = 16; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9283 | if (tg3_flag(tp, ENABLE_ASF)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9284 | limit -= 4; |
| 9285 | switch (limit) { |
| 9286 | case 16: |
| 9287 | tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); |
| 9288 | case 15: |
| 9289 | tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); |
| 9290 | case 14: |
| 9291 | tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); |
| 9292 | case 13: |
| 9293 | tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); |
| 9294 | case 12: |
| 9295 | tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); |
| 9296 | case 11: |
| 9297 | tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); |
| 9298 | case 10: |
| 9299 | tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); |
| 9300 | case 9: |
| 9301 | tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); |
| 9302 | case 8: |
| 9303 | tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); |
| 9304 | case 7: |
| 9305 | tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); |
| 9306 | case 6: |
| 9307 | tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); |
| 9308 | case 5: |
| 9309 | tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); |
| 9310 | case 4: |
| 9311 | /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ |
| 9312 | case 3: |
| 9313 | /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ |
| 9314 | case 2: |
| 9315 | case 1: |
| 9316 | |
| 9317 | default: |
| 9318 | break; |
Stephen Hemminger | 855e111 | 2008-04-16 16:37:28 -0700 | [diff] [blame] | 9319 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9320 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9321 | if (tg3_flag(tp, ENABLE_APE)) |
Matt Carlson | 9ce768e | 2007-10-11 19:49:11 -0700 | [diff] [blame] | 9322 | /* Write our heartbeat update interval to APE. */ |
| 9323 | tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, |
| 9324 | APE_HOST_HEARTBEAT_INT_DISABLE); |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 9325 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9326 | tg3_write_sig_post_reset(tp, RESET_KIND_INIT); |
| 9327 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9328 | return 0; |
| 9329 | } |
| 9330 | |
| 9331 | /* Called at device open time to get the chip ready for |
| 9332 | * packet processing. Invoked with tp->lock held. |
| 9333 | */ |
Gary Zambrano | 8e7a22e | 2006-04-29 18:59:13 -0700 | [diff] [blame] | 9334 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9335 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9336 | tg3_switch_clocks(tp); |
| 9337 | |
| 9338 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); |
| 9339 | |
Matt Carlson | 2f751b6 | 2008-08-04 23:17:34 -0700 | [diff] [blame] | 9340 | return tg3_reset_hw(tp, reset_phy); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9341 | } |
| 9342 | |
Matt Carlson | ebf3312 | 2012-02-13 10:20:05 +0000 | [diff] [blame] | 9343 | /* Restart hardware after configuration changes, self-test, etc. |
| 9344 | * Invoked with tp->lock held. |
| 9345 | */ |
| 9346 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) |
| 9347 | __releases(tp->lock) |
| 9348 | __acquires(tp->lock) |
| 9349 | { |
| 9350 | int err; |
| 9351 | |
| 9352 | err = tg3_init_hw(tp, reset_phy); |
| 9353 | if (err) { |
| 9354 | netdev_err(tp->dev, |
| 9355 | "Failed to re-initialize device, aborting\n"); |
| 9356 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
| 9357 | tg3_full_unlock(tp); |
| 9358 | del_timer_sync(&tp->timer); |
| 9359 | tp->irq_sync = 0; |
| 9360 | tg3_napi_enable(tp); |
| 9361 | dev_close(tp->dev); |
| 9362 | tg3_full_lock(tp, 0); |
| 9363 | } |
| 9364 | return err; |
| 9365 | } |
| 9366 | |
Matt Carlson | 9a21fb8 | 2012-02-13 10:20:06 +0000 | [diff] [blame] | 9367 | static void tg3_reset_task(struct work_struct *work) |
| 9368 | { |
| 9369 | struct tg3 *tp = container_of(work, struct tg3, reset_task); |
| 9370 | int err; |
| 9371 | |
| 9372 | tg3_full_lock(tp, 0); |
| 9373 | |
| 9374 | if (!netif_running(tp->dev)) { |
| 9375 | tg3_flag_clear(tp, RESET_TASK_PENDING); |
| 9376 | tg3_full_unlock(tp); |
| 9377 | return; |
| 9378 | } |
| 9379 | |
| 9380 | tg3_full_unlock(tp); |
| 9381 | |
| 9382 | tg3_phy_stop(tp); |
| 9383 | |
| 9384 | tg3_netif_stop(tp); |
| 9385 | |
| 9386 | tg3_full_lock(tp, 1); |
| 9387 | |
| 9388 | if (tg3_flag(tp, TX_RECOVERY_PENDING)) { |
| 9389 | tp->write32_tx_mbox = tg3_write32_tx_mbox; |
| 9390 | tp->write32_rx_mbox = tg3_write_flush_reg32; |
| 9391 | tg3_flag_set(tp, MBOX_WRITE_REORDER); |
| 9392 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); |
| 9393 | } |
| 9394 | |
| 9395 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); |
| 9396 | err = tg3_init_hw(tp, 1); |
| 9397 | if (err) |
| 9398 | goto out; |
| 9399 | |
| 9400 | tg3_netif_start(tp); |
| 9401 | |
| 9402 | out: |
| 9403 | tg3_full_unlock(tp); |
| 9404 | |
| 9405 | if (!err) |
| 9406 | tg3_phy_start(tp); |
| 9407 | |
| 9408 | tg3_flag_clear(tp, RESET_TASK_PENDING); |
| 9409 | } |
| 9410 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9411 | #define TG3_STAT_ADD32(PSTAT, REG) \ |
| 9412 | do { u32 __val = tr32(REG); \ |
| 9413 | (PSTAT)->low += __val; \ |
| 9414 | if ((PSTAT)->low < __val) \ |
| 9415 | (PSTAT)->high += 1; \ |
| 9416 | } while (0) |
| 9417 | |
| 9418 | static void tg3_periodic_fetch_stats(struct tg3 *tp) |
| 9419 | { |
| 9420 | struct tg3_hw_stats *sp = tp->hw_stats; |
| 9421 | |
| 9422 | if (!netif_carrier_ok(tp->dev)) |
| 9423 | return; |
| 9424 | |
| 9425 | TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); |
| 9426 | TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); |
| 9427 | TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); |
| 9428 | TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); |
| 9429 | TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); |
| 9430 | TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); |
| 9431 | TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); |
| 9432 | TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); |
| 9433 | TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); |
| 9434 | TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); |
| 9435 | TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); |
| 9436 | TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); |
| 9437 | TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); |
| 9438 | |
| 9439 | TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); |
| 9440 | TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); |
| 9441 | TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); |
| 9442 | TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); |
| 9443 | TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); |
| 9444 | TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); |
| 9445 | TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); |
| 9446 | TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); |
| 9447 | TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); |
| 9448 | TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); |
| 9449 | TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); |
| 9450 | TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); |
| 9451 | TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); |
| 9452 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); |
Michael Chan | 463d305 | 2006-05-22 16:36:27 -0700 | [diff] [blame] | 9453 | |
| 9454 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); |
Matt Carlson | 310050f | 2011-05-19 12:12:55 +0000 | [diff] [blame] | 9455 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && |
| 9456 | tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 && |
| 9457 | tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) { |
Matt Carlson | 4d95847 | 2011-04-20 07:57:35 +0000 | [diff] [blame] | 9458 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); |
| 9459 | } else { |
| 9460 | u32 val = tr32(HOSTCC_FLOW_ATTN); |
| 9461 | val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0; |
| 9462 | if (val) { |
| 9463 | tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM); |
| 9464 | sp->rx_discards.low += val; |
| 9465 | if (sp->rx_discards.low < val) |
| 9466 | sp->rx_discards.high += 1; |
| 9467 | } |
| 9468 | sp->mbuf_lwm_thresh_hit = sp->rx_discards; |
| 9469 | } |
Michael Chan | 463d305 | 2006-05-22 16:36:27 -0700 | [diff] [blame] | 9470 | TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9471 | } |
| 9472 | |
Matt Carlson | 0e6cf6a | 2011-06-13 13:38:55 +0000 | [diff] [blame] | 9473 | static void tg3_chk_missed_msi(struct tg3 *tp) |
| 9474 | { |
| 9475 | u32 i; |
| 9476 | |
| 9477 | for (i = 0; i < tp->irq_cnt; i++) { |
| 9478 | struct tg3_napi *tnapi = &tp->napi[i]; |
| 9479 | |
| 9480 | if (tg3_has_work(tnapi)) { |
| 9481 | if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr && |
| 9482 | tnapi->last_tx_cons == tnapi->tx_cons) { |
| 9483 | if (tnapi->chk_msi_cnt < 1) { |
| 9484 | tnapi->chk_msi_cnt++; |
| 9485 | return; |
| 9486 | } |
Matt Carlson | 7f23073 | 2011-08-31 11:44:48 +0000 | [diff] [blame] | 9487 | tg3_msi(0, tnapi); |
Matt Carlson | 0e6cf6a | 2011-06-13 13:38:55 +0000 | [diff] [blame] | 9488 | } |
| 9489 | } |
| 9490 | tnapi->chk_msi_cnt = 0; |
| 9491 | tnapi->last_rx_cons = tnapi->rx_rcb_ptr; |
| 9492 | tnapi->last_tx_cons = tnapi->tx_cons; |
| 9493 | } |
| 9494 | } |
| 9495 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9496 | static void tg3_timer(unsigned long __opaque) |
| 9497 | { |
| 9498 | struct tg3 *tp = (struct tg3 *) __opaque; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9499 | |
Matt Carlson | 5b19062 | 2011-11-04 09:15:04 +0000 | [diff] [blame] | 9500 | if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) |
Michael Chan | f475f16 | 2006-03-27 23:20:14 -0800 | [diff] [blame] | 9501 | goto restart_timer; |
| 9502 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 9503 | spin_lock(&tp->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9504 | |
Matt Carlson | 0e6cf6a | 2011-06-13 13:38:55 +0000 | [diff] [blame] | 9505 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
Matt Carlson | 55086ad | 2011-12-14 11:09:59 +0000 | [diff] [blame] | 9506 | tg3_flag(tp, 57765_CLASS)) |
Matt Carlson | 0e6cf6a | 2011-06-13 13:38:55 +0000 | [diff] [blame] | 9507 | tg3_chk_missed_msi(tp); |
| 9508 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9509 | if (!tg3_flag(tp, TAGGED_STATUS)) { |
David S. Miller | fac9b83 | 2005-05-18 22:46:34 -0700 | [diff] [blame] | 9510 | /* All of this garbage is because when using non-tagged |
| 9511 | * IRQ status the mailbox/status_block protocol the chip |
| 9512 | * uses with the cpu is race prone. |
| 9513 | */ |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 9514 | if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { |
David S. Miller | fac9b83 | 2005-05-18 22:46:34 -0700 | [diff] [blame] | 9515 | tw32(GRC_LOCAL_CTRL, |
| 9516 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); |
| 9517 | } else { |
| 9518 | tw32(HOSTCC_MODE, tp->coalesce_mode | |
Matt Carlson | fd2ce37 | 2009-09-01 12:51:13 +0000 | [diff] [blame] | 9519 | HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW); |
David S. Miller | fac9b83 | 2005-05-18 22:46:34 -0700 | [diff] [blame] | 9520 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9521 | |
David S. Miller | fac9b83 | 2005-05-18 22:46:34 -0700 | [diff] [blame] | 9522 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 9523 | spin_unlock(&tp->lock); |
Matt Carlson | db21997 | 2011-11-04 09:15:03 +0000 | [diff] [blame] | 9524 | tg3_reset_task_schedule(tp); |
Matt Carlson | 5b19062 | 2011-11-04 09:15:04 +0000 | [diff] [blame] | 9525 | goto restart_timer; |
David S. Miller | fac9b83 | 2005-05-18 22:46:34 -0700 | [diff] [blame] | 9526 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9527 | } |
| 9528 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9529 | /* This part only runs once per second. */ |
| 9530 | if (!--tp->timer_counter) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9531 | if (tg3_flag(tp, 5705_PLUS)) |
David S. Miller | fac9b83 | 2005-05-18 22:46:34 -0700 | [diff] [blame] | 9532 | tg3_periodic_fetch_stats(tp); |
| 9533 | |
Matt Carlson | b0c5943 | 2011-05-19 12:12:48 +0000 | [diff] [blame] | 9534 | if (tp->setlpicnt && !--tp->setlpicnt) |
| 9535 | tg3_phy_eee_enable(tp); |
Matt Carlson | 52b02d0 | 2010-10-14 10:37:41 +0000 | [diff] [blame] | 9536 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9537 | if (tg3_flag(tp, USE_LINKCHG_REG)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9538 | u32 mac_stat; |
| 9539 | int phy_event; |
| 9540 | |
| 9541 | mac_stat = tr32(MAC_STATUS); |
| 9542 | |
| 9543 | phy_event = 0; |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 9544 | if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9545 | if (mac_stat & MAC_STATUS_MI_INTERRUPT) |
| 9546 | phy_event = 1; |
| 9547 | } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) |
| 9548 | phy_event = 1; |
| 9549 | |
| 9550 | if (phy_event) |
| 9551 | tg3_setup_phy(tp, 0); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9552 | } else if (tg3_flag(tp, POLL_SERDES)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9553 | u32 mac_stat = tr32(MAC_STATUS); |
| 9554 | int need_setup = 0; |
| 9555 | |
| 9556 | if (netif_carrier_ok(tp->dev) && |
| 9557 | (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) { |
| 9558 | need_setup = 1; |
| 9559 | } |
Matt Carlson | be98da6 | 2010-07-11 09:31:46 +0000 | [diff] [blame] | 9560 | if (!netif_carrier_ok(tp->dev) && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9561 | (mac_stat & (MAC_STATUS_PCS_SYNCED | |
| 9562 | MAC_STATUS_SIGNAL_DET))) { |
| 9563 | need_setup = 1; |
| 9564 | } |
| 9565 | if (need_setup) { |
Michael Chan | 3d3ebe7 | 2006-09-27 15:59:15 -0700 | [diff] [blame] | 9566 | if (!tp->serdes_counter) { |
| 9567 | tw32_f(MAC_MODE, |
| 9568 | (tp->mac_mode & |
| 9569 | ~MAC_MODE_PORT_MODE_MASK)); |
| 9570 | udelay(40); |
| 9571 | tw32_f(MAC_MODE, tp->mac_mode); |
| 9572 | udelay(40); |
| 9573 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9574 | tg3_setup_phy(tp, 0); |
| 9575 | } |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 9576 | } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9577 | tg3_flag(tp, 5780_CLASS)) { |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 9578 | tg3_serdes_parallel_detect(tp); |
Matt Carlson | 57d8b88 | 2010-06-05 17:24:35 +0000 | [diff] [blame] | 9579 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9580 | |
| 9581 | tp->timer_counter = tp->timer_multiplier; |
| 9582 | } |
| 9583 | |
Michael Chan | 130b8e4 | 2006-09-27 16:00:40 -0700 | [diff] [blame] | 9584 | /* Heartbeat is only sent once every 2 seconds. |
| 9585 | * |
| 9586 | * The heartbeat is to tell the ASF firmware that the host |
| 9587 | * driver is still alive. In the event that the OS crashes, |
| 9588 | * ASF needs to reset the hardware to free up the FIFO space |
| 9589 | * that may be filled with rx packets destined for the host. |
| 9590 | * If the FIFO is full, ASF will no longer function properly. |
| 9591 | * |
| 9592 | * Unintended resets have been reported on real time kernels |
| 9593 | * where the timer doesn't run on time. Netpoll will also have |
| 9594 | * same problem. |
| 9595 | * |
| 9596 | * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware |
| 9597 | * to check the ring condition when the heartbeat is expiring |
| 9598 | * before doing the reset. This will prevent most unintended |
| 9599 | * resets. |
| 9600 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9601 | if (!--tp->asf_counter) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9602 | if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { |
Matt Carlson | 7c5026a | 2008-05-02 16:49:29 -0700 | [diff] [blame] | 9603 | tg3_wait_for_event_ack(tp); |
| 9604 | |
Michael Chan | bbadf50 | 2006-04-06 21:46:34 -0700 | [diff] [blame] | 9605 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, |
Michael Chan | 130b8e4 | 2006-09-27 16:00:40 -0700 | [diff] [blame] | 9606 | FWCMD_NICDRV_ALIVE3); |
Michael Chan | bbadf50 | 2006-04-06 21:46:34 -0700 | [diff] [blame] | 9607 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); |
Matt Carlson | c6cdf43 | 2010-04-05 10:19:26 +0000 | [diff] [blame] | 9608 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, |
| 9609 | TG3_FW_UPDATE_TIMEOUT_SEC); |
Matt Carlson | 4ba526c | 2008-08-15 14:10:04 -0700 | [diff] [blame] | 9610 | |
| 9611 | tg3_generate_fw_event(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9612 | } |
| 9613 | tp->asf_counter = tp->asf_multiplier; |
| 9614 | } |
| 9615 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 9616 | spin_unlock(&tp->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9617 | |
Michael Chan | f475f16 | 2006-03-27 23:20:14 -0800 | [diff] [blame] | 9618 | restart_timer: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9619 | tp->timer.expires = jiffies + tp->timer_offset; |
| 9620 | add_timer(&tp->timer); |
| 9621 | } |
| 9622 | |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 9623 | static int tg3_request_irq(struct tg3 *tp, int irq_num) |
Michael Chan | fcfa0a3 | 2006-03-20 22:28:41 -0800 | [diff] [blame] | 9624 | { |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 9625 | irq_handler_t fn; |
Michael Chan | fcfa0a3 | 2006-03-20 22:28:41 -0800 | [diff] [blame] | 9626 | unsigned long flags; |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 9627 | char *name; |
| 9628 | struct tg3_napi *tnapi = &tp->napi[irq_num]; |
| 9629 | |
| 9630 | if (tp->irq_cnt == 1) |
| 9631 | name = tp->dev->name; |
| 9632 | else { |
| 9633 | name = &tnapi->irq_lbl[0]; |
| 9634 | snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num); |
| 9635 | name[IFNAMSIZ-1] = 0; |
| 9636 | } |
Michael Chan | fcfa0a3 | 2006-03-20 22:28:41 -0800 | [diff] [blame] | 9637 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9638 | if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { |
Michael Chan | fcfa0a3 | 2006-03-20 22:28:41 -0800 | [diff] [blame] | 9639 | fn = tg3_msi; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9640 | if (tg3_flag(tp, 1SHOT_MSI)) |
Michael Chan | fcfa0a3 | 2006-03-20 22:28:41 -0800 | [diff] [blame] | 9641 | fn = tg3_msi_1shot; |
Javier Martinez Canillas | ab392d2 | 2011-03-28 16:27:31 +0000 | [diff] [blame] | 9642 | flags = 0; |
Michael Chan | fcfa0a3 | 2006-03-20 22:28:41 -0800 | [diff] [blame] | 9643 | } else { |
| 9644 | fn = tg3_interrupt; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9645 | if (tg3_flag(tp, TAGGED_STATUS)) |
Michael Chan | fcfa0a3 | 2006-03-20 22:28:41 -0800 | [diff] [blame] | 9646 | fn = tg3_interrupt_tagged; |
Javier Martinez Canillas | ab392d2 | 2011-03-28 16:27:31 +0000 | [diff] [blame] | 9647 | flags = IRQF_SHARED; |
Michael Chan | fcfa0a3 | 2006-03-20 22:28:41 -0800 | [diff] [blame] | 9648 | } |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 9649 | |
| 9650 | return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); |
Michael Chan | fcfa0a3 | 2006-03-20 22:28:41 -0800 | [diff] [blame] | 9651 | } |
| 9652 | |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9653 | static int tg3_test_interrupt(struct tg3 *tp) |
| 9654 | { |
Matt Carlson | 09943a1 | 2009-08-28 14:01:57 +0000 | [diff] [blame] | 9655 | struct tg3_napi *tnapi = &tp->napi[0]; |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9656 | struct net_device *dev = tp->dev; |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 9657 | int err, i, intr_ok = 0; |
Matt Carlson | f6eb9b1 | 2009-09-01 13:19:53 +0000 | [diff] [blame] | 9658 | u32 val; |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9659 | |
Michael Chan | d4bc392 | 2005-05-29 14:59:20 -0700 | [diff] [blame] | 9660 | if (!netif_running(dev)) |
| 9661 | return -ENODEV; |
| 9662 | |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9663 | tg3_disable_ints(tp); |
| 9664 | |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 9665 | free_irq(tnapi->irq_vec, tnapi); |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9666 | |
Matt Carlson | f6eb9b1 | 2009-09-01 13:19:53 +0000 | [diff] [blame] | 9667 | /* |
| 9668 | * Turn off MSI one shot mode. Otherwise this test has no |
| 9669 | * observable way to know whether the interrupt was delivered. |
| 9670 | */ |
Matt Carlson | 3aa1cdf | 2011-07-20 10:20:55 +0000 | [diff] [blame] | 9671 | if (tg3_flag(tp, 57765_PLUS)) { |
Matt Carlson | f6eb9b1 | 2009-09-01 13:19:53 +0000 | [diff] [blame] | 9672 | val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; |
| 9673 | tw32(MSGINT_MODE, val); |
| 9674 | } |
| 9675 | |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 9676 | err = request_irq(tnapi->irq_vec, tg3_test_isr, |
Matt Carlson | 09943a1 | 2009-08-28 14:01:57 +0000 | [diff] [blame] | 9677 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi); |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9678 | if (err) |
| 9679 | return err; |
| 9680 | |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 9681 | tnapi->hw_status->status &= ~SD_STATUS_UPDATED; |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9682 | tg3_enable_ints(tp); |
| 9683 | |
| 9684 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
Matt Carlson | fd2ce37 | 2009-09-01 12:51:13 +0000 | [diff] [blame] | 9685 | tnapi->coal_now); |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9686 | |
| 9687 | for (i = 0; i < 5; i++) { |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 9688 | u32 int_mbox, misc_host_ctrl; |
| 9689 | |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 9690 | int_mbox = tr32_mailbox(tnapi->int_mbox); |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 9691 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
| 9692 | |
| 9693 | if ((int_mbox != 0) || |
| 9694 | (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) { |
| 9695 | intr_ok = 1; |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9696 | break; |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 9697 | } |
| 9698 | |
Matt Carlson | 3aa1cdf | 2011-07-20 10:20:55 +0000 | [diff] [blame] | 9699 | if (tg3_flag(tp, 57765_PLUS) && |
| 9700 | tnapi->hw_status->status_tag != tnapi->last_tag) |
| 9701 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
| 9702 | |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9703 | msleep(10); |
| 9704 | } |
| 9705 | |
| 9706 | tg3_disable_ints(tp); |
| 9707 | |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 9708 | free_irq(tnapi->irq_vec, tnapi); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 9709 | |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 9710 | err = tg3_request_irq(tp, 0); |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9711 | |
| 9712 | if (err) |
| 9713 | return err; |
| 9714 | |
Matt Carlson | f6eb9b1 | 2009-09-01 13:19:53 +0000 | [diff] [blame] | 9715 | if (intr_ok) { |
| 9716 | /* Reenable MSI one shot mode. */ |
Matt Carlson | 5b39de9 | 2011-08-31 11:44:50 +0000 | [diff] [blame] | 9717 | if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) { |
Matt Carlson | f6eb9b1 | 2009-09-01 13:19:53 +0000 | [diff] [blame] | 9718 | val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; |
| 9719 | tw32(MSGINT_MODE, val); |
| 9720 | } |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9721 | return 0; |
Matt Carlson | f6eb9b1 | 2009-09-01 13:19:53 +0000 | [diff] [blame] | 9722 | } |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9723 | |
| 9724 | return -EIO; |
| 9725 | } |
| 9726 | |
| 9727 | /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is |
| 9728 | * successfully restored |
| 9729 | */ |
| 9730 | static int tg3_test_msi(struct tg3 *tp) |
| 9731 | { |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9732 | int err; |
| 9733 | u16 pci_cmd; |
| 9734 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9735 | if (!tg3_flag(tp, USING_MSI)) |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9736 | return 0; |
| 9737 | |
| 9738 | /* Turn off SERR reporting in case MSI terminates with Master |
| 9739 | * Abort. |
| 9740 | */ |
| 9741 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); |
| 9742 | pci_write_config_word(tp->pdev, PCI_COMMAND, |
| 9743 | pci_cmd & ~PCI_COMMAND_SERR); |
| 9744 | |
| 9745 | err = tg3_test_interrupt(tp); |
| 9746 | |
| 9747 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); |
| 9748 | |
| 9749 | if (!err) |
| 9750 | return 0; |
| 9751 | |
| 9752 | /* other failures */ |
| 9753 | if (err != -EIO) |
| 9754 | return err; |
| 9755 | |
| 9756 | /* MSI test failed, go back to INTx mode */ |
Matt Carlson | 5129c3a | 2010-04-05 10:19:23 +0000 | [diff] [blame] | 9757 | netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " |
| 9758 | "to INTx mode. Please report this failure to the PCI " |
| 9759 | "maintainer and include system chipset information\n"); |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9760 | |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 9761 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
Matt Carlson | 09943a1 | 2009-08-28 14:01:57 +0000 | [diff] [blame] | 9762 | |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9763 | pci_disable_msi(tp->pdev); |
| 9764 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9765 | tg3_flag_clear(tp, USING_MSI); |
Andre Detsch | dc8bf1b | 2010-04-26 07:27:07 +0000 | [diff] [blame] | 9766 | tp->napi[0].irq_vec = tp->pdev->irq; |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9767 | |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 9768 | err = tg3_request_irq(tp, 0); |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9769 | if (err) |
| 9770 | return err; |
| 9771 | |
| 9772 | /* Need to reset the chip because the MSI cycle may have terminated |
| 9773 | * with Master Abort. |
| 9774 | */ |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 9775 | tg3_full_lock(tp, 1); |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9776 | |
Michael Chan | 944d980 | 2005-05-29 14:57:48 -0700 | [diff] [blame] | 9777 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
Gary Zambrano | 8e7a22e | 2006-04-29 18:59:13 -0700 | [diff] [blame] | 9778 | err = tg3_init_hw(tp, 1); |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9779 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 9780 | tg3_full_unlock(tp); |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9781 | |
| 9782 | if (err) |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 9783 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 9784 | |
| 9785 | return err; |
| 9786 | } |
| 9787 | |
Matt Carlson | 9e9fd12 | 2009-01-19 16:57:45 -0800 | [diff] [blame] | 9788 | static int tg3_request_firmware(struct tg3 *tp) |
| 9789 | { |
| 9790 | const __be32 *fw_data; |
| 9791 | |
| 9792 | if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { |
Joe Perches | 05dbe00 | 2010-02-17 19:44:19 +0000 | [diff] [blame] | 9793 | netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", |
| 9794 | tp->fw_needed); |
Matt Carlson | 9e9fd12 | 2009-01-19 16:57:45 -0800 | [diff] [blame] | 9795 | return -ENOENT; |
| 9796 | } |
| 9797 | |
| 9798 | fw_data = (void *)tp->fw->data; |
| 9799 | |
| 9800 | /* Firmware blob starts with version numbers, followed by |
| 9801 | * start address and _full_ length including BSS sections |
| 9802 | * (which must be longer than the actual data, of course |
| 9803 | */ |
| 9804 | |
| 9805 | tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */ |
| 9806 | if (tp->fw_len < (tp->fw->size - 12)) { |
Joe Perches | 05dbe00 | 2010-02-17 19:44:19 +0000 | [diff] [blame] | 9807 | netdev_err(tp->dev, "bogus length %d in \"%s\"\n", |
| 9808 | tp->fw_len, tp->fw_needed); |
Matt Carlson | 9e9fd12 | 2009-01-19 16:57:45 -0800 | [diff] [blame] | 9809 | release_firmware(tp->fw); |
| 9810 | tp->fw = NULL; |
| 9811 | return -EINVAL; |
| 9812 | } |
| 9813 | |
| 9814 | /* We no longer need firmware; we have it. */ |
| 9815 | tp->fw_needed = NULL; |
| 9816 | return 0; |
| 9817 | } |
| 9818 | |
Matt Carlson | 679563f | 2009-09-01 12:55:46 +0000 | [diff] [blame] | 9819 | static bool tg3_enable_msix(struct tg3 *tp) |
| 9820 | { |
Matt Carlson | c3b5003 | 2012-01-17 15:27:23 +0000 | [diff] [blame] | 9821 | int i, rc; |
Matt Carlson | 679563f | 2009-09-01 12:55:46 +0000 | [diff] [blame] | 9822 | struct msix_entry msix_ent[tp->irq_max]; |
| 9823 | |
Matt Carlson | c3b5003 | 2012-01-17 15:27:23 +0000 | [diff] [blame] | 9824 | tp->irq_cnt = num_online_cpus(); |
| 9825 | if (tp->irq_cnt > 1) { |
| 9826 | /* We want as many rx rings enabled as there are cpus. |
| 9827 | * In multiqueue MSI-X mode, the first MSI-X vector |
| 9828 | * only deals with link interrupts, etc, so we add |
| 9829 | * one to the number of vectors we are requesting. |
| 9830 | */ |
| 9831 | tp->irq_cnt = min_t(unsigned, tp->irq_cnt + 1, tp->irq_max); |
| 9832 | } |
Matt Carlson | 679563f | 2009-09-01 12:55:46 +0000 | [diff] [blame] | 9833 | |
| 9834 | for (i = 0; i < tp->irq_max; i++) { |
| 9835 | msix_ent[i].entry = i; |
| 9836 | msix_ent[i].vector = 0; |
| 9837 | } |
| 9838 | |
| 9839 | rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt); |
Matt Carlson | 2430b03 | 2010-06-05 17:24:34 +0000 | [diff] [blame] | 9840 | if (rc < 0) { |
| 9841 | return false; |
| 9842 | } else if (rc != 0) { |
Matt Carlson | 679563f | 2009-09-01 12:55:46 +0000 | [diff] [blame] | 9843 | if (pci_enable_msix(tp->pdev, msix_ent, rc)) |
| 9844 | return false; |
Joe Perches | 05dbe00 | 2010-02-17 19:44:19 +0000 | [diff] [blame] | 9845 | netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", |
| 9846 | tp->irq_cnt, rc); |
Matt Carlson | 679563f | 2009-09-01 12:55:46 +0000 | [diff] [blame] | 9847 | tp->irq_cnt = rc; |
| 9848 | } |
| 9849 | |
| 9850 | for (i = 0; i < tp->irq_max; i++) |
| 9851 | tp->napi[i].irq_vec = msix_ent[i].vector; |
| 9852 | |
Ben Hutchings | 2ddaad3 | 2010-09-27 22:11:51 -0700 | [diff] [blame] | 9853 | netif_set_real_num_tx_queues(tp->dev, 1); |
| 9854 | rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1; |
| 9855 | if (netif_set_real_num_rx_queues(tp->dev, rc)) { |
| 9856 | pci_disable_msix(tp->pdev); |
| 9857 | return false; |
| 9858 | } |
Matt Carlson | b92b904 | 2010-11-24 08:31:51 +0000 | [diff] [blame] | 9859 | |
| 9860 | if (tp->irq_cnt > 1) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9861 | tg3_flag_set(tp, ENABLE_RSS); |
Matt Carlson | d78b59f | 2011-04-05 14:22:46 +0000 | [diff] [blame] | 9862 | |
| 9863 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
| 9864 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9865 | tg3_flag_set(tp, ENABLE_TSS); |
Matt Carlson | b92b904 | 2010-11-24 08:31:51 +0000 | [diff] [blame] | 9866 | netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1); |
| 9867 | } |
| 9868 | } |
Matt Carlson | 2430b03 | 2010-06-05 17:24:34 +0000 | [diff] [blame] | 9869 | |
Matt Carlson | 679563f | 2009-09-01 12:55:46 +0000 | [diff] [blame] | 9870 | return true; |
| 9871 | } |
| 9872 | |
Matt Carlson | 07b0173 | 2009-08-28 14:01:15 +0000 | [diff] [blame] | 9873 | static void tg3_ints_init(struct tg3 *tp) |
| 9874 | { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9875 | if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) && |
| 9876 | !tg3_flag(tp, TAGGED_STATUS)) { |
Matt Carlson | 07b0173 | 2009-08-28 14:01:15 +0000 | [diff] [blame] | 9877 | /* All MSI supporting chips should support tagged |
| 9878 | * status. Assert that this is the case. |
| 9879 | */ |
Matt Carlson | 5129c3a | 2010-04-05 10:19:23 +0000 | [diff] [blame] | 9880 | netdev_warn(tp->dev, |
| 9881 | "MSI without TAGGED_STATUS? Not using MSI\n"); |
Matt Carlson | 679563f | 2009-09-01 12:55:46 +0000 | [diff] [blame] | 9882 | goto defcfg; |
Matt Carlson | 07b0173 | 2009-08-28 14:01:15 +0000 | [diff] [blame] | 9883 | } |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 9884 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9885 | if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp)) |
| 9886 | tg3_flag_set(tp, USING_MSIX); |
| 9887 | else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) |
| 9888 | tg3_flag_set(tp, USING_MSI); |
Matt Carlson | 679563f | 2009-09-01 12:55:46 +0000 | [diff] [blame] | 9889 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9890 | if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { |
Matt Carlson | 679563f | 2009-09-01 12:55:46 +0000 | [diff] [blame] | 9891 | u32 msi_mode = tr32(MSGINT_MODE); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9892 | if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) |
Matt Carlson | baf8a94 | 2009-09-01 13:13:00 +0000 | [diff] [blame] | 9893 | msi_mode |= MSGINT_MODE_MULTIVEC_EN; |
Matt Carlson | 5b39de9 | 2011-08-31 11:44:50 +0000 | [diff] [blame] | 9894 | if (!tg3_flag(tp, 1SHOT_MSI)) |
| 9895 | msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE; |
Matt Carlson | 679563f | 2009-09-01 12:55:46 +0000 | [diff] [blame] | 9896 | tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); |
| 9897 | } |
| 9898 | defcfg: |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9899 | if (!tg3_flag(tp, USING_MSIX)) { |
Matt Carlson | 679563f | 2009-09-01 12:55:46 +0000 | [diff] [blame] | 9900 | tp->irq_cnt = 1; |
| 9901 | tp->napi[0].irq_vec = tp->pdev->irq; |
Ben Hutchings | 2ddaad3 | 2010-09-27 22:11:51 -0700 | [diff] [blame] | 9902 | netif_set_real_num_tx_queues(tp->dev, 1); |
Matt Carlson | 8540788 | 2010-10-06 13:40:58 -0700 | [diff] [blame] | 9903 | netif_set_real_num_rx_queues(tp->dev, 1); |
Matt Carlson | 679563f | 2009-09-01 12:55:46 +0000 | [diff] [blame] | 9904 | } |
Matt Carlson | 07b0173 | 2009-08-28 14:01:15 +0000 | [diff] [blame] | 9905 | } |
| 9906 | |
| 9907 | static void tg3_ints_fini(struct tg3 *tp) |
| 9908 | { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9909 | if (tg3_flag(tp, USING_MSIX)) |
Matt Carlson | 679563f | 2009-09-01 12:55:46 +0000 | [diff] [blame] | 9910 | pci_disable_msix(tp->pdev); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9911 | else if (tg3_flag(tp, USING_MSI)) |
Matt Carlson | 679563f | 2009-09-01 12:55:46 +0000 | [diff] [blame] | 9912 | pci_disable_msi(tp->pdev); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9913 | tg3_flag_clear(tp, USING_MSI); |
| 9914 | tg3_flag_clear(tp, USING_MSIX); |
| 9915 | tg3_flag_clear(tp, ENABLE_RSS); |
| 9916 | tg3_flag_clear(tp, ENABLE_TSS); |
Matt Carlson | 07b0173 | 2009-08-28 14:01:15 +0000 | [diff] [blame] | 9917 | } |
| 9918 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9919 | static int tg3_open(struct net_device *dev) |
| 9920 | { |
| 9921 | struct tg3 *tp = netdev_priv(dev); |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 9922 | int i, err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9923 | |
Matt Carlson | 9e9fd12 | 2009-01-19 16:57:45 -0800 | [diff] [blame] | 9924 | if (tp->fw_needed) { |
| 9925 | err = tg3_request_firmware(tp); |
| 9926 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { |
| 9927 | if (err) |
| 9928 | return err; |
| 9929 | } else if (err) { |
Joe Perches | 05dbe00 | 2010-02-17 19:44:19 +0000 | [diff] [blame] | 9930 | netdev_warn(tp->dev, "TSO capability disabled\n"); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9931 | tg3_flag_clear(tp, TSO_CAPABLE); |
| 9932 | } else if (!tg3_flag(tp, TSO_CAPABLE)) { |
Joe Perches | 05dbe00 | 2010-02-17 19:44:19 +0000 | [diff] [blame] | 9933 | netdev_notice(tp->dev, "TSO capability restored\n"); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9934 | tg3_flag_set(tp, TSO_CAPABLE); |
Matt Carlson | 9e9fd12 | 2009-01-19 16:57:45 -0800 | [diff] [blame] | 9935 | } |
| 9936 | } |
| 9937 | |
Michael Chan | c49a156 | 2006-12-17 17:07:29 -0800 | [diff] [blame] | 9938 | netif_carrier_off(tp->dev); |
| 9939 | |
Rafael J. Wysocki | c866b7e | 2010-12-25 12:56:23 +0000 | [diff] [blame] | 9940 | err = tg3_power_up(tp); |
Matt Carlson | 2f751b6 | 2008-08-04 23:17:34 -0700 | [diff] [blame] | 9941 | if (err) |
Michael Chan | bc1c756 | 2006-03-20 17:48:03 -0800 | [diff] [blame] | 9942 | return err; |
Matt Carlson | 2f751b6 | 2008-08-04 23:17:34 -0700 | [diff] [blame] | 9943 | |
| 9944 | tg3_full_lock(tp, 0); |
Michael Chan | bc1c756 | 2006-03-20 17:48:03 -0800 | [diff] [blame] | 9945 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9946 | tg3_disable_ints(tp); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 9947 | tg3_flag_clear(tp, INIT_COMPLETE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9948 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 9949 | tg3_full_unlock(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9950 | |
Matt Carlson | 679563f | 2009-09-01 12:55:46 +0000 | [diff] [blame] | 9951 | /* |
| 9952 | * Setup interrupts first so we know how |
| 9953 | * many NAPI resources to allocate |
| 9954 | */ |
| 9955 | tg3_ints_init(tp); |
| 9956 | |
Matt Carlson | 9041547 | 2011-12-16 13:33:23 +0000 | [diff] [blame] | 9957 | tg3_rss_check_indir_tbl(tp); |
Matt Carlson | bcebcc4 | 2011-12-14 11:10:01 +0000 | [diff] [blame] | 9958 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9959 | /* The placement of this call is tied |
| 9960 | * to the setup and use of Host TX descriptors. |
| 9961 | */ |
| 9962 | err = tg3_alloc_consistent(tp); |
| 9963 | if (err) |
Matt Carlson | 679563f | 2009-09-01 12:55:46 +0000 | [diff] [blame] | 9964 | goto err_out1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9965 | |
Matt Carlson | 66cfd1b | 2010-09-30 10:34:30 +0000 | [diff] [blame] | 9966 | tg3_napi_init(tp); |
| 9967 | |
Matt Carlson | fed9781 | 2009-09-01 13:10:19 +0000 | [diff] [blame] | 9968 | tg3_napi_enable(tp); |
Stephen Hemminger | bea3348 | 2007-10-03 16:41:36 -0700 | [diff] [blame] | 9969 | |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 9970 | for (i = 0; i < tp->irq_cnt; i++) { |
| 9971 | struct tg3_napi *tnapi = &tp->napi[i]; |
| 9972 | err = tg3_request_irq(tp, i); |
| 9973 | if (err) { |
Matt Carlson | 5bc0918 | 2011-11-04 09:15:01 +0000 | [diff] [blame] | 9974 | for (i--; i >= 0; i--) { |
| 9975 | tnapi = &tp->napi[i]; |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 9976 | free_irq(tnapi->irq_vec, tnapi); |
Matt Carlson | 5bc0918 | 2011-11-04 09:15:01 +0000 | [diff] [blame] | 9977 | } |
| 9978 | goto err_out2; |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 9979 | } |
| 9980 | } |
Matt Carlson | 07b0173 | 2009-08-28 14:01:15 +0000 | [diff] [blame] | 9981 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 9982 | tg3_full_lock(tp, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9983 | |
Gary Zambrano | 8e7a22e | 2006-04-29 18:59:13 -0700 | [diff] [blame] | 9984 | err = tg3_init_hw(tp, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9985 | if (err) { |
Michael Chan | 944d980 | 2005-05-29 14:57:48 -0700 | [diff] [blame] | 9986 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9987 | tg3_free_rings(tp); |
| 9988 | } else { |
Matt Carlson | 0e6cf6a | 2011-06-13 13:38:55 +0000 | [diff] [blame] | 9989 | if (tg3_flag(tp, TAGGED_STATUS) && |
Matt Carlson | 55086ad | 2011-12-14 11:09:59 +0000 | [diff] [blame] | 9990 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && |
| 9991 | !tg3_flag(tp, 57765_CLASS)) |
David S. Miller | fac9b83 | 2005-05-18 22:46:34 -0700 | [diff] [blame] | 9992 | tp->timer_offset = HZ; |
| 9993 | else |
| 9994 | tp->timer_offset = HZ / 10; |
| 9995 | |
| 9996 | BUG_ON(tp->timer_offset > HZ); |
| 9997 | tp->timer_counter = tp->timer_multiplier = |
| 9998 | (HZ / tp->timer_offset); |
| 9999 | tp->asf_counter = tp->asf_multiplier = |
Michael Chan | 28fbef7 | 2005-10-26 15:48:35 -0700 | [diff] [blame] | 10000 | ((HZ / tp->timer_offset) * 2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10001 | |
| 10002 | init_timer(&tp->timer); |
| 10003 | tp->timer.expires = jiffies + tp->timer_offset; |
| 10004 | tp->timer.data = (unsigned long) tp; |
| 10005 | tp->timer.function = tg3_timer; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10006 | } |
| 10007 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 10008 | tg3_full_unlock(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10009 | |
Matt Carlson | 07b0173 | 2009-08-28 14:01:15 +0000 | [diff] [blame] | 10010 | if (err) |
Matt Carlson | 679563f | 2009-09-01 12:55:46 +0000 | [diff] [blame] | 10011 | goto err_out3; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10012 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10013 | if (tg3_flag(tp, USING_MSI)) { |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 10014 | err = tg3_test_msi(tp); |
David S. Miller | fac9b83 | 2005-05-18 22:46:34 -0700 | [diff] [blame] | 10015 | |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 10016 | if (err) { |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 10017 | tg3_full_lock(tp, 0); |
Michael Chan | 944d980 | 2005-05-29 14:57:48 -0700 | [diff] [blame] | 10018 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 10019 | tg3_free_rings(tp); |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 10020 | tg3_full_unlock(tp); |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 10021 | |
Matt Carlson | 679563f | 2009-09-01 12:55:46 +0000 | [diff] [blame] | 10022 | goto err_out2; |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 10023 | } |
Michael Chan | fcfa0a3 | 2006-03-20 22:28:41 -0800 | [diff] [blame] | 10024 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10025 | if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { |
Matt Carlson | f6eb9b1 | 2009-09-01 13:19:53 +0000 | [diff] [blame] | 10026 | u32 val = tr32(PCIE_TRANSACTION_CFG); |
Michael Chan | fcfa0a3 | 2006-03-20 22:28:41 -0800 | [diff] [blame] | 10027 | |
Matt Carlson | f6eb9b1 | 2009-09-01 13:19:53 +0000 | [diff] [blame] | 10028 | tw32(PCIE_TRANSACTION_CFG, |
| 10029 | val | PCIE_TRANS_CFG_1SHOT_MSI); |
Michael Chan | fcfa0a3 | 2006-03-20 22:28:41 -0800 | [diff] [blame] | 10030 | } |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 10031 | } |
| 10032 | |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10033 | tg3_phy_start(tp); |
| 10034 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 10035 | tg3_full_lock(tp, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10036 | |
Michael Chan | 7938109 | 2005-04-21 17:13:59 -0700 | [diff] [blame] | 10037 | add_timer(&tp->timer); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10038 | tg3_flag_set(tp, INIT_COMPLETE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10039 | tg3_enable_ints(tp); |
| 10040 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 10041 | tg3_full_unlock(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10042 | |
Matt Carlson | fe5f578 | 2009-09-01 13:09:39 +0000 | [diff] [blame] | 10043 | netif_tx_start_all_queues(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10044 | |
Mahesh Bandewar | 06c03c0 | 2011-05-08 06:51:48 +0000 | [diff] [blame] | 10045 | /* |
| 10046 | * Reset loopback feature if it was turned on while the device was down |
| 10047 | * make sure that it's installed properly now. |
| 10048 | */ |
| 10049 | if (dev->features & NETIF_F_LOOPBACK) |
| 10050 | tg3_set_loopback(dev, dev->features); |
| 10051 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10052 | return 0; |
Matt Carlson | 07b0173 | 2009-08-28 14:01:15 +0000 | [diff] [blame] | 10053 | |
Matt Carlson | 679563f | 2009-09-01 12:55:46 +0000 | [diff] [blame] | 10054 | err_out3: |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 10055 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
| 10056 | struct tg3_napi *tnapi = &tp->napi[i]; |
| 10057 | free_irq(tnapi->irq_vec, tnapi); |
| 10058 | } |
Matt Carlson | 07b0173 | 2009-08-28 14:01:15 +0000 | [diff] [blame] | 10059 | |
Matt Carlson | 679563f | 2009-09-01 12:55:46 +0000 | [diff] [blame] | 10060 | err_out2: |
Matt Carlson | fed9781 | 2009-09-01 13:10:19 +0000 | [diff] [blame] | 10061 | tg3_napi_disable(tp); |
Matt Carlson | 66cfd1b | 2010-09-30 10:34:30 +0000 | [diff] [blame] | 10062 | tg3_napi_fini(tp); |
Matt Carlson | 07b0173 | 2009-08-28 14:01:15 +0000 | [diff] [blame] | 10063 | tg3_free_consistent(tp); |
Matt Carlson | 679563f | 2009-09-01 12:55:46 +0000 | [diff] [blame] | 10064 | |
| 10065 | err_out1: |
| 10066 | tg3_ints_fini(tp); |
Matt Carlson | cd0d722 | 2011-07-13 09:27:33 +0000 | [diff] [blame] | 10067 | tg3_frob_aux_power(tp, false); |
| 10068 | pci_set_power_state(tp->pdev, PCI_D3hot); |
Matt Carlson | 07b0173 | 2009-08-28 14:01:15 +0000 | [diff] [blame] | 10069 | return err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10070 | } |
| 10071 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10072 | static int tg3_close(struct net_device *dev) |
| 10073 | { |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 10074 | int i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10075 | struct tg3 *tp = netdev_priv(dev); |
| 10076 | |
Matt Carlson | fed9781 | 2009-09-01 13:10:19 +0000 | [diff] [blame] | 10077 | tg3_napi_disable(tp); |
Matt Carlson | db21997 | 2011-11-04 09:15:03 +0000 | [diff] [blame] | 10078 | tg3_reset_task_cancel(tp); |
Michael Chan | 7faa006 | 2006-02-02 17:29:28 -0800 | [diff] [blame] | 10079 | |
Matt Carlson | fe5f578 | 2009-09-01 13:09:39 +0000 | [diff] [blame] | 10080 | netif_tx_stop_all_queues(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10081 | |
| 10082 | del_timer_sync(&tp->timer); |
| 10083 | |
Matt Carlson | 24bb4fb | 2009-10-05 17:55:29 +0000 | [diff] [blame] | 10084 | tg3_phy_stop(tp); |
| 10085 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 10086 | tg3_full_lock(tp, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10087 | |
| 10088 | tg3_disable_ints(tp); |
| 10089 | |
Michael Chan | 944d980 | 2005-05-29 14:57:48 -0700 | [diff] [blame] | 10090 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10091 | tg3_free_rings(tp); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10092 | tg3_flag_clear(tp, INIT_COMPLETE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10093 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 10094 | tg3_full_unlock(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10095 | |
Matt Carlson | 4f125f4 | 2009-09-01 12:55:02 +0000 | [diff] [blame] | 10096 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
| 10097 | struct tg3_napi *tnapi = &tp->napi[i]; |
| 10098 | free_irq(tnapi->irq_vec, tnapi); |
| 10099 | } |
Matt Carlson | 07b0173 | 2009-08-28 14:01:15 +0000 | [diff] [blame] | 10100 | |
| 10101 | tg3_ints_fini(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10102 | |
Matt Carlson | 92feeab | 2011-12-08 14:40:14 +0000 | [diff] [blame] | 10103 | /* Clear stats across close / open calls */ |
| 10104 | memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev)); |
| 10105 | memset(&tp->estats_prev, 0, sizeof(tp->estats_prev)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10106 | |
Matt Carlson | 66cfd1b | 2010-09-30 10:34:30 +0000 | [diff] [blame] | 10107 | tg3_napi_fini(tp); |
| 10108 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10109 | tg3_free_consistent(tp); |
| 10110 | |
Rafael J. Wysocki | c866b7e | 2010-12-25 12:56:23 +0000 | [diff] [blame] | 10111 | tg3_power_down(tp); |
Michael Chan | bc1c756 | 2006-03-20 17:48:03 -0800 | [diff] [blame] | 10112 | |
| 10113 | netif_carrier_off(tp->dev); |
| 10114 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10115 | return 0; |
| 10116 | } |
| 10117 | |
Eric Dumazet | 511d222 | 2010-07-07 20:44:24 +0000 | [diff] [blame] | 10118 | static inline u64 get_stat64(tg3_stat64_t *val) |
Stefan Buehler | 816f8b8 | 2008-08-15 14:10:54 -0700 | [diff] [blame] | 10119 | { |
| 10120 | return ((u64)val->high << 32) | ((u64)val->low); |
| 10121 | } |
| 10122 | |
Eric Dumazet | 511d222 | 2010-07-07 20:44:24 +0000 | [diff] [blame] | 10123 | static u64 calc_crc_errors(struct tg3 *tp) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10124 | { |
| 10125 | struct tg3_hw_stats *hw_stats = tp->hw_stats; |
| 10126 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 10127 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10128 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
| 10129 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10130 | u32 val; |
| 10131 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 10132 | spin_lock_bh(&tp->lock); |
Michael Chan | 569a5df | 2007-02-13 12:18:15 -0800 | [diff] [blame] | 10133 | if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { |
| 10134 | tg3_writephy(tp, MII_TG3_TEST1, |
| 10135 | val | MII_TG3_TEST1_CRC_EN); |
Matt Carlson | f08aa1a | 2010-08-02 11:26:05 +0000 | [diff] [blame] | 10136 | tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10137 | } else |
| 10138 | val = 0; |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 10139 | spin_unlock_bh(&tp->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10140 | |
| 10141 | tp->phy_crc_errors += val; |
| 10142 | |
| 10143 | return tp->phy_crc_errors; |
| 10144 | } |
| 10145 | |
| 10146 | return get_stat64(&hw_stats->rx_fcs_errors); |
| 10147 | } |
| 10148 | |
| 10149 | #define ESTAT_ADD(member) \ |
| 10150 | estats->member = old_estats->member + \ |
Eric Dumazet | 511d222 | 2010-07-07 20:44:24 +0000 | [diff] [blame] | 10151 | get_stat64(&hw_stats->member) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10152 | |
Matt Carlson | 0e6c9da | 2011-12-08 14:40:13 +0000 | [diff] [blame] | 10153 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp, |
| 10154 | struct tg3_ethtool_stats *estats) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10155 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10156 | struct tg3_ethtool_stats *old_estats = &tp->estats_prev; |
| 10157 | struct tg3_hw_stats *hw_stats = tp->hw_stats; |
| 10158 | |
| 10159 | if (!hw_stats) |
| 10160 | return old_estats; |
| 10161 | |
| 10162 | ESTAT_ADD(rx_octets); |
| 10163 | ESTAT_ADD(rx_fragments); |
| 10164 | ESTAT_ADD(rx_ucast_packets); |
| 10165 | ESTAT_ADD(rx_mcast_packets); |
| 10166 | ESTAT_ADD(rx_bcast_packets); |
| 10167 | ESTAT_ADD(rx_fcs_errors); |
| 10168 | ESTAT_ADD(rx_align_errors); |
| 10169 | ESTAT_ADD(rx_xon_pause_rcvd); |
| 10170 | ESTAT_ADD(rx_xoff_pause_rcvd); |
| 10171 | ESTAT_ADD(rx_mac_ctrl_rcvd); |
| 10172 | ESTAT_ADD(rx_xoff_entered); |
| 10173 | ESTAT_ADD(rx_frame_too_long_errors); |
| 10174 | ESTAT_ADD(rx_jabbers); |
| 10175 | ESTAT_ADD(rx_undersize_packets); |
| 10176 | ESTAT_ADD(rx_in_length_errors); |
| 10177 | ESTAT_ADD(rx_out_length_errors); |
| 10178 | ESTAT_ADD(rx_64_or_less_octet_packets); |
| 10179 | ESTAT_ADD(rx_65_to_127_octet_packets); |
| 10180 | ESTAT_ADD(rx_128_to_255_octet_packets); |
| 10181 | ESTAT_ADD(rx_256_to_511_octet_packets); |
| 10182 | ESTAT_ADD(rx_512_to_1023_octet_packets); |
| 10183 | ESTAT_ADD(rx_1024_to_1522_octet_packets); |
| 10184 | ESTAT_ADD(rx_1523_to_2047_octet_packets); |
| 10185 | ESTAT_ADD(rx_2048_to_4095_octet_packets); |
| 10186 | ESTAT_ADD(rx_4096_to_8191_octet_packets); |
| 10187 | ESTAT_ADD(rx_8192_to_9022_octet_packets); |
| 10188 | |
| 10189 | ESTAT_ADD(tx_octets); |
| 10190 | ESTAT_ADD(tx_collisions); |
| 10191 | ESTAT_ADD(tx_xon_sent); |
| 10192 | ESTAT_ADD(tx_xoff_sent); |
| 10193 | ESTAT_ADD(tx_flow_control); |
| 10194 | ESTAT_ADD(tx_mac_errors); |
| 10195 | ESTAT_ADD(tx_single_collisions); |
| 10196 | ESTAT_ADD(tx_mult_collisions); |
| 10197 | ESTAT_ADD(tx_deferred); |
| 10198 | ESTAT_ADD(tx_excessive_collisions); |
| 10199 | ESTAT_ADD(tx_late_collisions); |
| 10200 | ESTAT_ADD(tx_collide_2times); |
| 10201 | ESTAT_ADD(tx_collide_3times); |
| 10202 | ESTAT_ADD(tx_collide_4times); |
| 10203 | ESTAT_ADD(tx_collide_5times); |
| 10204 | ESTAT_ADD(tx_collide_6times); |
| 10205 | ESTAT_ADD(tx_collide_7times); |
| 10206 | ESTAT_ADD(tx_collide_8times); |
| 10207 | ESTAT_ADD(tx_collide_9times); |
| 10208 | ESTAT_ADD(tx_collide_10times); |
| 10209 | ESTAT_ADD(tx_collide_11times); |
| 10210 | ESTAT_ADD(tx_collide_12times); |
| 10211 | ESTAT_ADD(tx_collide_13times); |
| 10212 | ESTAT_ADD(tx_collide_14times); |
| 10213 | ESTAT_ADD(tx_collide_15times); |
| 10214 | ESTAT_ADD(tx_ucast_packets); |
| 10215 | ESTAT_ADD(tx_mcast_packets); |
| 10216 | ESTAT_ADD(tx_bcast_packets); |
| 10217 | ESTAT_ADD(tx_carrier_sense_errors); |
| 10218 | ESTAT_ADD(tx_discards); |
| 10219 | ESTAT_ADD(tx_errors); |
| 10220 | |
| 10221 | ESTAT_ADD(dma_writeq_full); |
| 10222 | ESTAT_ADD(dma_write_prioq_full); |
| 10223 | ESTAT_ADD(rxbds_empty); |
| 10224 | ESTAT_ADD(rx_discards); |
| 10225 | ESTAT_ADD(rx_errors); |
| 10226 | ESTAT_ADD(rx_threshold_hit); |
| 10227 | |
| 10228 | ESTAT_ADD(dma_readq_full); |
| 10229 | ESTAT_ADD(dma_read_prioq_full); |
| 10230 | ESTAT_ADD(tx_comp_queue_full); |
| 10231 | |
| 10232 | ESTAT_ADD(ring_set_send_prod_index); |
| 10233 | ESTAT_ADD(ring_status_update); |
| 10234 | ESTAT_ADD(nic_irqs); |
| 10235 | ESTAT_ADD(nic_avoided_irqs); |
| 10236 | ESTAT_ADD(nic_tx_threshold_hit); |
| 10237 | |
Matt Carlson | 4452d09 | 2011-05-19 12:12:51 +0000 | [diff] [blame] | 10238 | ESTAT_ADD(mbuf_lwm_thresh_hit); |
| 10239 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10240 | return estats; |
| 10241 | } |
| 10242 | |
Eric Dumazet | 511d222 | 2010-07-07 20:44:24 +0000 | [diff] [blame] | 10243 | static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev, |
| 10244 | struct rtnl_link_stats64 *stats) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10245 | { |
| 10246 | struct tg3 *tp = netdev_priv(dev); |
Eric Dumazet | 511d222 | 2010-07-07 20:44:24 +0000 | [diff] [blame] | 10247 | struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10248 | struct tg3_hw_stats *hw_stats = tp->hw_stats; |
| 10249 | |
| 10250 | if (!hw_stats) |
| 10251 | return old_stats; |
| 10252 | |
| 10253 | stats->rx_packets = old_stats->rx_packets + |
| 10254 | get_stat64(&hw_stats->rx_ucast_packets) + |
| 10255 | get_stat64(&hw_stats->rx_mcast_packets) + |
| 10256 | get_stat64(&hw_stats->rx_bcast_packets); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10257 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10258 | stats->tx_packets = old_stats->tx_packets + |
| 10259 | get_stat64(&hw_stats->tx_ucast_packets) + |
| 10260 | get_stat64(&hw_stats->tx_mcast_packets) + |
| 10261 | get_stat64(&hw_stats->tx_bcast_packets); |
| 10262 | |
| 10263 | stats->rx_bytes = old_stats->rx_bytes + |
| 10264 | get_stat64(&hw_stats->rx_octets); |
| 10265 | stats->tx_bytes = old_stats->tx_bytes + |
| 10266 | get_stat64(&hw_stats->tx_octets); |
| 10267 | |
| 10268 | stats->rx_errors = old_stats->rx_errors + |
John W. Linville | 4f63b87 | 2005-09-12 14:43:18 -0700 | [diff] [blame] | 10269 | get_stat64(&hw_stats->rx_errors); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10270 | stats->tx_errors = old_stats->tx_errors + |
| 10271 | get_stat64(&hw_stats->tx_errors) + |
| 10272 | get_stat64(&hw_stats->tx_mac_errors) + |
| 10273 | get_stat64(&hw_stats->tx_carrier_sense_errors) + |
| 10274 | get_stat64(&hw_stats->tx_discards); |
| 10275 | |
| 10276 | stats->multicast = old_stats->multicast + |
| 10277 | get_stat64(&hw_stats->rx_mcast_packets); |
| 10278 | stats->collisions = old_stats->collisions + |
| 10279 | get_stat64(&hw_stats->tx_collisions); |
| 10280 | |
| 10281 | stats->rx_length_errors = old_stats->rx_length_errors + |
| 10282 | get_stat64(&hw_stats->rx_frame_too_long_errors) + |
| 10283 | get_stat64(&hw_stats->rx_undersize_packets); |
| 10284 | |
| 10285 | stats->rx_over_errors = old_stats->rx_over_errors + |
| 10286 | get_stat64(&hw_stats->rxbds_empty); |
| 10287 | stats->rx_frame_errors = old_stats->rx_frame_errors + |
| 10288 | get_stat64(&hw_stats->rx_align_errors); |
| 10289 | stats->tx_aborted_errors = old_stats->tx_aborted_errors + |
| 10290 | get_stat64(&hw_stats->tx_discards); |
| 10291 | stats->tx_carrier_errors = old_stats->tx_carrier_errors + |
| 10292 | get_stat64(&hw_stats->tx_carrier_sense_errors); |
| 10293 | |
| 10294 | stats->rx_crc_errors = old_stats->rx_crc_errors + |
| 10295 | calc_crc_errors(tp); |
| 10296 | |
John W. Linville | 4f63b87 | 2005-09-12 14:43:18 -0700 | [diff] [blame] | 10297 | stats->rx_missed_errors = old_stats->rx_missed_errors + |
| 10298 | get_stat64(&hw_stats->rx_discards); |
| 10299 | |
Eric Dumazet | b0057c5 | 2010-10-10 19:55:52 +0000 | [diff] [blame] | 10300 | stats->rx_dropped = tp->rx_dropped; |
Eric Dumazet | 4885543 | 2011-10-24 07:53:03 +0000 | [diff] [blame] | 10301 | stats->tx_dropped = tp->tx_dropped; |
Eric Dumazet | b0057c5 | 2010-10-10 19:55:52 +0000 | [diff] [blame] | 10302 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10303 | return stats; |
| 10304 | } |
| 10305 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10306 | static int tg3_get_regs_len(struct net_device *dev) |
| 10307 | { |
Matt Carlson | 97bd8e4 | 2011-04-13 11:05:04 +0000 | [diff] [blame] | 10308 | return TG3_REG_BLK_SIZE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10309 | } |
| 10310 | |
| 10311 | static void tg3_get_regs(struct net_device *dev, |
| 10312 | struct ethtool_regs *regs, void *_p) |
| 10313 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10314 | struct tg3 *tp = netdev_priv(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10315 | |
| 10316 | regs->version = 0; |
| 10317 | |
Matt Carlson | 97bd8e4 | 2011-04-13 11:05:04 +0000 | [diff] [blame] | 10318 | memset(_p, 0, TG3_REG_BLK_SIZE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10319 | |
Matt Carlson | 80096068 | 2010-08-02 11:26:06 +0000 | [diff] [blame] | 10320 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
Michael Chan | bc1c756 | 2006-03-20 17:48:03 -0800 | [diff] [blame] | 10321 | return; |
| 10322 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 10323 | tg3_full_lock(tp, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10324 | |
Matt Carlson | 97bd8e4 | 2011-04-13 11:05:04 +0000 | [diff] [blame] | 10325 | tg3_dump_legacy_regs(tp, (u32 *)_p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10326 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 10327 | tg3_full_unlock(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10328 | } |
| 10329 | |
| 10330 | static int tg3_get_eeprom_len(struct net_device *dev) |
| 10331 | { |
| 10332 | struct tg3 *tp = netdev_priv(dev); |
| 10333 | |
| 10334 | return tp->nvram_size; |
| 10335 | } |
| 10336 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10337 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
| 10338 | { |
| 10339 | struct tg3 *tp = netdev_priv(dev); |
| 10340 | int ret; |
| 10341 | u8 *pd; |
Al Viro | b9fc7dc | 2007-12-17 22:59:57 -0800 | [diff] [blame] | 10342 | u32 i, offset, len, b_offset, b_count; |
Matt Carlson | a9dc529 | 2009-02-25 14:25:30 +0000 | [diff] [blame] | 10343 | __be32 val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10344 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10345 | if (tg3_flag(tp, NO_NVRAM)) |
Matt Carlson | df259d8 | 2009-04-20 06:57:14 +0000 | [diff] [blame] | 10346 | return -EINVAL; |
| 10347 | |
Matt Carlson | 80096068 | 2010-08-02 11:26:06 +0000 | [diff] [blame] | 10348 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
Michael Chan | bc1c756 | 2006-03-20 17:48:03 -0800 | [diff] [blame] | 10349 | return -EAGAIN; |
| 10350 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10351 | offset = eeprom->offset; |
| 10352 | len = eeprom->len; |
| 10353 | eeprom->len = 0; |
| 10354 | |
| 10355 | eeprom->magic = TG3_EEPROM_MAGIC; |
| 10356 | |
| 10357 | if (offset & 3) { |
| 10358 | /* adjustments to start on required 4 byte boundary */ |
| 10359 | b_offset = offset & 3; |
| 10360 | b_count = 4 - b_offset; |
| 10361 | if (b_count > len) { |
| 10362 | /* i.e. offset=1 len=2 */ |
| 10363 | b_count = len; |
| 10364 | } |
Matt Carlson | a9dc529 | 2009-02-25 14:25:30 +0000 | [diff] [blame] | 10365 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10366 | if (ret) |
| 10367 | return ret; |
Matt Carlson | be98da6 | 2010-07-11 09:31:46 +0000 | [diff] [blame] | 10368 | memcpy(data, ((char *)&val) + b_offset, b_count); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10369 | len -= b_count; |
| 10370 | offset += b_count; |
Matt Carlson | c6cdf43 | 2010-04-05 10:19:26 +0000 | [diff] [blame] | 10371 | eeprom->len += b_count; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10372 | } |
| 10373 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 10374 | /* read bytes up to the last 4 byte boundary */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10375 | pd = &data[eeprom->len]; |
| 10376 | for (i = 0; i < (len - (len & 3)); i += 4) { |
Matt Carlson | a9dc529 | 2009-02-25 14:25:30 +0000 | [diff] [blame] | 10377 | ret = tg3_nvram_read_be32(tp, offset + i, &val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10378 | if (ret) { |
| 10379 | eeprom->len += i; |
| 10380 | return ret; |
| 10381 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10382 | memcpy(pd + i, &val, 4); |
| 10383 | } |
| 10384 | eeprom->len += i; |
| 10385 | |
| 10386 | if (len & 3) { |
| 10387 | /* read last bytes not ending on 4 byte boundary */ |
| 10388 | pd = &data[eeprom->len]; |
| 10389 | b_count = len & 3; |
| 10390 | b_offset = offset + len - b_count; |
Matt Carlson | a9dc529 | 2009-02-25 14:25:30 +0000 | [diff] [blame] | 10391 | ret = tg3_nvram_read_be32(tp, b_offset, &val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10392 | if (ret) |
| 10393 | return ret; |
Al Viro | b9fc7dc | 2007-12-17 22:59:57 -0800 | [diff] [blame] | 10394 | memcpy(pd, &val, b_count); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10395 | eeprom->len += b_count; |
| 10396 | } |
| 10397 | return 0; |
| 10398 | } |
| 10399 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10400 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
| 10401 | { |
| 10402 | struct tg3 *tp = netdev_priv(dev); |
| 10403 | int ret; |
Al Viro | b9fc7dc | 2007-12-17 22:59:57 -0800 | [diff] [blame] | 10404 | u32 offset, len, b_offset, odd_len; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10405 | u8 *buf; |
Matt Carlson | a9dc529 | 2009-02-25 14:25:30 +0000 | [diff] [blame] | 10406 | __be32 start, end; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10407 | |
Matt Carlson | 80096068 | 2010-08-02 11:26:06 +0000 | [diff] [blame] | 10408 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
Michael Chan | bc1c756 | 2006-03-20 17:48:03 -0800 | [diff] [blame] | 10409 | return -EAGAIN; |
| 10410 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10411 | if (tg3_flag(tp, NO_NVRAM) || |
Matt Carlson | df259d8 | 2009-04-20 06:57:14 +0000 | [diff] [blame] | 10412 | eeprom->magic != TG3_EEPROM_MAGIC) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10413 | return -EINVAL; |
| 10414 | |
| 10415 | offset = eeprom->offset; |
| 10416 | len = eeprom->len; |
| 10417 | |
| 10418 | if ((b_offset = (offset & 3))) { |
| 10419 | /* adjustments to start on required 4 byte boundary */ |
Matt Carlson | a9dc529 | 2009-02-25 14:25:30 +0000 | [diff] [blame] | 10420 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10421 | if (ret) |
| 10422 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10423 | len += b_offset; |
| 10424 | offset &= ~3; |
Michael Chan | 1c8594b | 2005-04-21 17:12:46 -0700 | [diff] [blame] | 10425 | if (len < 4) |
| 10426 | len = 4; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10427 | } |
| 10428 | |
| 10429 | odd_len = 0; |
Michael Chan | 1c8594b | 2005-04-21 17:12:46 -0700 | [diff] [blame] | 10430 | if (len & 3) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10431 | /* adjustments to end on required 4 byte boundary */ |
| 10432 | odd_len = 1; |
| 10433 | len = (len + 3) & ~3; |
Matt Carlson | a9dc529 | 2009-02-25 14:25:30 +0000 | [diff] [blame] | 10434 | ret = tg3_nvram_read_be32(tp, offset+len-4, &end); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10435 | if (ret) |
| 10436 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10437 | } |
| 10438 | |
| 10439 | buf = data; |
| 10440 | if (b_offset || odd_len) { |
| 10441 | buf = kmalloc(len, GFP_KERNEL); |
Andy Gospodarek | ab0049b | 2007-09-06 20:42:14 +0100 | [diff] [blame] | 10442 | if (!buf) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10443 | return -ENOMEM; |
| 10444 | if (b_offset) |
| 10445 | memcpy(buf, &start, 4); |
| 10446 | if (odd_len) |
| 10447 | memcpy(buf+len-4, &end, 4); |
| 10448 | memcpy(buf + b_offset, data, eeprom->len); |
| 10449 | } |
| 10450 | |
| 10451 | ret = tg3_nvram_write_block(tp, offset, len, buf); |
| 10452 | |
| 10453 | if (buf != data) |
| 10454 | kfree(buf); |
| 10455 | |
| 10456 | return ret; |
| 10457 | } |
| 10458 | |
| 10459 | static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
| 10460 | { |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10461 | struct tg3 *tp = netdev_priv(dev); |
| 10462 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10463 | if (tg3_flag(tp, USE_PHYLIB)) { |
Matt Carlson | 3f0e3ad | 2009-11-02 14:24:36 +0000 | [diff] [blame] | 10464 | struct phy_device *phydev; |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 10465 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10466 | return -EAGAIN; |
Matt Carlson | 3f0e3ad | 2009-11-02 14:24:36 +0000 | [diff] [blame] | 10467 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
| 10468 | return phy_ethtool_gset(phydev, cmd); |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10469 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10470 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10471 | cmd->supported = (SUPPORTED_Autoneg); |
| 10472 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 10473 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10474 | cmd->supported |= (SUPPORTED_1000baseT_Half | |
| 10475 | SUPPORTED_1000baseT_Full); |
| 10476 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 10477 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10478 | cmd->supported |= (SUPPORTED_100baseT_Half | |
| 10479 | SUPPORTED_100baseT_Full | |
| 10480 | SUPPORTED_10baseT_Half | |
| 10481 | SUPPORTED_10baseT_Full | |
Matt Carlson | 3bebab5 | 2007-11-12 21:22:40 -0800 | [diff] [blame] | 10482 | SUPPORTED_TP); |
Karsten Keil | ef34814 | 2006-05-12 12:49:08 -0700 | [diff] [blame] | 10483 | cmd->port = PORT_TP; |
| 10484 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10485 | cmd->supported |= SUPPORTED_FIBRE; |
Karsten Keil | ef34814 | 2006-05-12 12:49:08 -0700 | [diff] [blame] | 10486 | cmd->port = PORT_FIBRE; |
| 10487 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10488 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10489 | cmd->advertising = tp->link_config.advertising; |
Matt Carlson | 5bb0977 | 2011-06-13 13:39:00 +0000 | [diff] [blame] | 10490 | if (tg3_flag(tp, PAUSE_AUTONEG)) { |
| 10491 | if (tp->link_config.flowctrl & FLOW_CTRL_RX) { |
| 10492 | if (tp->link_config.flowctrl & FLOW_CTRL_TX) { |
| 10493 | cmd->advertising |= ADVERTISED_Pause; |
| 10494 | } else { |
| 10495 | cmd->advertising |= ADVERTISED_Pause | |
| 10496 | ADVERTISED_Asym_Pause; |
| 10497 | } |
| 10498 | } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { |
| 10499 | cmd->advertising |= ADVERTISED_Asym_Pause; |
| 10500 | } |
| 10501 | } |
Matt Carlson | 859edb2 | 2011-12-08 14:40:16 +0000 | [diff] [blame] | 10502 | if (netif_running(dev) && netif_carrier_ok(dev)) { |
David Decotigny | 7073949 | 2011-04-27 18:32:40 +0000 | [diff] [blame] | 10503 | ethtool_cmd_speed_set(cmd, tp->link_config.active_speed); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10504 | cmd->duplex = tp->link_config.active_duplex; |
Matt Carlson | 859edb2 | 2011-12-08 14:40:16 +0000 | [diff] [blame] | 10505 | cmd->lp_advertising = tp->link_config.rmt_adv; |
Matt Carlson | e348c5e | 2011-11-21 15:01:20 +0000 | [diff] [blame] | 10506 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { |
| 10507 | if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE) |
| 10508 | cmd->eth_tp_mdix = ETH_TP_MDI_X; |
| 10509 | else |
| 10510 | cmd->eth_tp_mdix = ETH_TP_MDI; |
| 10511 | } |
Matt Carlson | 64c2218 | 2010-10-14 10:37:44 +0000 | [diff] [blame] | 10512 | } else { |
David Decotigny | 7073949 | 2011-04-27 18:32:40 +0000 | [diff] [blame] | 10513 | ethtool_cmd_speed_set(cmd, SPEED_INVALID); |
Matt Carlson | 64c2218 | 2010-10-14 10:37:44 +0000 | [diff] [blame] | 10514 | cmd->duplex = DUPLEX_INVALID; |
Matt Carlson | e348c5e | 2011-11-21 15:01:20 +0000 | [diff] [blame] | 10515 | cmd->eth_tp_mdix = ETH_TP_MDI_INVALID; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10516 | } |
Matt Carlson | 882e979 | 2009-09-01 13:21:36 +0000 | [diff] [blame] | 10517 | cmd->phy_address = tp->phy_addr; |
Matt Carlson | 7e5856b | 2009-02-25 14:23:01 +0000 | [diff] [blame] | 10518 | cmd->transceiver = XCVR_INTERNAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10519 | cmd->autoneg = tp->link_config.autoneg; |
| 10520 | cmd->maxtxpkt = 0; |
| 10521 | cmd->maxrxpkt = 0; |
| 10522 | return 0; |
| 10523 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10524 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10525 | static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
| 10526 | { |
| 10527 | struct tg3 *tp = netdev_priv(dev); |
David Decotigny | 25db033 | 2011-04-27 18:32:39 +0000 | [diff] [blame] | 10528 | u32 speed = ethtool_cmd_speed(cmd); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10529 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10530 | if (tg3_flag(tp, USE_PHYLIB)) { |
Matt Carlson | 3f0e3ad | 2009-11-02 14:24:36 +0000 | [diff] [blame] | 10531 | struct phy_device *phydev; |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 10532 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10533 | return -EAGAIN; |
Matt Carlson | 3f0e3ad | 2009-11-02 14:24:36 +0000 | [diff] [blame] | 10534 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
| 10535 | return phy_ethtool_sset(phydev, cmd); |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10536 | } |
| 10537 | |
Matt Carlson | 7e5856b | 2009-02-25 14:23:01 +0000 | [diff] [blame] | 10538 | if (cmd->autoneg != AUTONEG_ENABLE && |
| 10539 | cmd->autoneg != AUTONEG_DISABLE) |
Michael Chan | 37ff238 | 2005-10-26 15:49:51 -0700 | [diff] [blame] | 10540 | return -EINVAL; |
Matt Carlson | 7e5856b | 2009-02-25 14:23:01 +0000 | [diff] [blame] | 10541 | |
| 10542 | if (cmd->autoneg == AUTONEG_DISABLE && |
| 10543 | cmd->duplex != DUPLEX_FULL && |
| 10544 | cmd->duplex != DUPLEX_HALF) |
Michael Chan | 37ff238 | 2005-10-26 15:49:51 -0700 | [diff] [blame] | 10545 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10546 | |
Matt Carlson | 7e5856b | 2009-02-25 14:23:01 +0000 | [diff] [blame] | 10547 | if (cmd->autoneg == AUTONEG_ENABLE) { |
| 10548 | u32 mask = ADVERTISED_Autoneg | |
| 10549 | ADVERTISED_Pause | |
| 10550 | ADVERTISED_Asym_Pause; |
| 10551 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 10552 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
Matt Carlson | 7e5856b | 2009-02-25 14:23:01 +0000 | [diff] [blame] | 10553 | mask |= ADVERTISED_1000baseT_Half | |
| 10554 | ADVERTISED_1000baseT_Full; |
| 10555 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 10556 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
Matt Carlson | 7e5856b | 2009-02-25 14:23:01 +0000 | [diff] [blame] | 10557 | mask |= ADVERTISED_100baseT_Half | |
| 10558 | ADVERTISED_100baseT_Full | |
| 10559 | ADVERTISED_10baseT_Half | |
| 10560 | ADVERTISED_10baseT_Full | |
| 10561 | ADVERTISED_TP; |
| 10562 | else |
| 10563 | mask |= ADVERTISED_FIBRE; |
| 10564 | |
| 10565 | if (cmd->advertising & ~mask) |
| 10566 | return -EINVAL; |
| 10567 | |
| 10568 | mask &= (ADVERTISED_1000baseT_Half | |
| 10569 | ADVERTISED_1000baseT_Full | |
| 10570 | ADVERTISED_100baseT_Half | |
| 10571 | ADVERTISED_100baseT_Full | |
| 10572 | ADVERTISED_10baseT_Half | |
| 10573 | ADVERTISED_10baseT_Full); |
| 10574 | |
| 10575 | cmd->advertising &= mask; |
| 10576 | } else { |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 10577 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { |
David Decotigny | 25db033 | 2011-04-27 18:32:39 +0000 | [diff] [blame] | 10578 | if (speed != SPEED_1000) |
Matt Carlson | 7e5856b | 2009-02-25 14:23:01 +0000 | [diff] [blame] | 10579 | return -EINVAL; |
| 10580 | |
| 10581 | if (cmd->duplex != DUPLEX_FULL) |
| 10582 | return -EINVAL; |
| 10583 | } else { |
David Decotigny | 25db033 | 2011-04-27 18:32:39 +0000 | [diff] [blame] | 10584 | if (speed != SPEED_100 && |
| 10585 | speed != SPEED_10) |
Matt Carlson | 7e5856b | 2009-02-25 14:23:01 +0000 | [diff] [blame] | 10586 | return -EINVAL; |
| 10587 | } |
| 10588 | } |
| 10589 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 10590 | tg3_full_lock(tp, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10591 | |
| 10592 | tp->link_config.autoneg = cmd->autoneg; |
| 10593 | if (cmd->autoneg == AUTONEG_ENABLE) { |
Andy Gospodarek | 405d8e5 | 2007-10-08 01:08:47 -0700 | [diff] [blame] | 10594 | tp->link_config.advertising = (cmd->advertising | |
| 10595 | ADVERTISED_Autoneg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10596 | tp->link_config.speed = SPEED_INVALID; |
| 10597 | tp->link_config.duplex = DUPLEX_INVALID; |
| 10598 | } else { |
| 10599 | tp->link_config.advertising = 0; |
David Decotigny | 25db033 | 2011-04-27 18:32:39 +0000 | [diff] [blame] | 10600 | tp->link_config.speed = speed; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10601 | tp->link_config.duplex = cmd->duplex; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10602 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10603 | |
Michael Chan | 24fcad6 | 2006-12-17 17:06:46 -0800 | [diff] [blame] | 10604 | tp->link_config.orig_speed = tp->link_config.speed; |
| 10605 | tp->link_config.orig_duplex = tp->link_config.duplex; |
| 10606 | tp->link_config.orig_autoneg = tp->link_config.autoneg; |
| 10607 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10608 | if (netif_running(dev)) |
| 10609 | tg3_setup_phy(tp, 1); |
| 10610 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 10611 | tg3_full_unlock(tp); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10612 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10613 | return 0; |
| 10614 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10615 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10616 | static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
| 10617 | { |
| 10618 | struct tg3 *tp = netdev_priv(dev); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10619 | |
Rick Jones | 68aad78 | 2011-11-07 13:29:27 +0000 | [diff] [blame] | 10620 | strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); |
| 10621 | strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); |
| 10622 | strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version)); |
| 10623 | strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10624 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10625 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10626 | static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
| 10627 | { |
| 10628 | struct tg3 *tp = netdev_priv(dev); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10629 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10630 | if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) |
Gary Zambrano | a85feb8 | 2007-05-05 11:52:19 -0700 | [diff] [blame] | 10631 | wol->supported = WAKE_MAGIC; |
| 10632 | else |
| 10633 | wol->supported = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10634 | wol->wolopts = 0; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10635 | if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10636 | wol->wolopts = WAKE_MAGIC; |
| 10637 | memset(&wol->sopass, 0, sizeof(wol->sopass)); |
| 10638 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10639 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10640 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
| 10641 | { |
| 10642 | struct tg3 *tp = netdev_priv(dev); |
Rafael J. Wysocki | 12dac07 | 2008-07-30 16:37:33 -0700 | [diff] [blame] | 10643 | struct device *dp = &tp->pdev->dev; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10644 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10645 | if (wol->wolopts & ~WAKE_MAGIC) |
| 10646 | return -EINVAL; |
| 10647 | if ((wol->wolopts & WAKE_MAGIC) && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10648 | !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp))) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10649 | return -EINVAL; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10650 | |
Rafael J. Wysocki | f2dc0d1 | 2010-10-25 13:01:55 +0000 | [diff] [blame] | 10651 | device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); |
| 10652 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 10653 | spin_lock_bh(&tp->lock); |
Rafael J. Wysocki | f2dc0d1 | 2010-10-25 13:01:55 +0000 | [diff] [blame] | 10654 | if (device_may_wakeup(dp)) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10655 | tg3_flag_set(tp, WOL_ENABLE); |
Rafael J. Wysocki | f2dc0d1 | 2010-10-25 13:01:55 +0000 | [diff] [blame] | 10656 | else |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10657 | tg3_flag_clear(tp, WOL_ENABLE); |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 10658 | spin_unlock_bh(&tp->lock); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10659 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10660 | return 0; |
| 10661 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10662 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10663 | static u32 tg3_get_msglevel(struct net_device *dev) |
| 10664 | { |
| 10665 | struct tg3 *tp = netdev_priv(dev); |
| 10666 | return tp->msg_enable; |
| 10667 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10668 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10669 | static void tg3_set_msglevel(struct net_device *dev, u32 value) |
| 10670 | { |
| 10671 | struct tg3 *tp = netdev_priv(dev); |
| 10672 | tp->msg_enable = value; |
| 10673 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10674 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10675 | static int tg3_nway_reset(struct net_device *dev) |
| 10676 | { |
| 10677 | struct tg3 *tp = netdev_priv(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10678 | int r; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10679 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10680 | if (!netif_running(dev)) |
| 10681 | return -EAGAIN; |
| 10682 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 10683 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
Michael Chan | c94e394 | 2005-09-27 12:12:42 -0700 | [diff] [blame] | 10684 | return -EINVAL; |
| 10685 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10686 | if (tg3_flag(tp, USE_PHYLIB)) { |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 10687 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10688 | return -EAGAIN; |
Matt Carlson | 3f0e3ad | 2009-11-02 14:24:36 +0000 | [diff] [blame] | 10689 | r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10690 | } else { |
| 10691 | u32 bmcr; |
| 10692 | |
| 10693 | spin_lock_bh(&tp->lock); |
| 10694 | r = -EINVAL; |
| 10695 | tg3_readphy(tp, MII_BMCR, &bmcr); |
| 10696 | if (!tg3_readphy(tp, MII_BMCR, &bmcr) && |
| 10697 | ((bmcr & BMCR_ANENABLE) || |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 10698 | (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10699 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | |
| 10700 | BMCR_ANENABLE); |
| 10701 | r = 0; |
| 10702 | } |
| 10703 | spin_unlock_bh(&tp->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10704 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10705 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10706 | return r; |
| 10707 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10708 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10709 | static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
| 10710 | { |
| 10711 | struct tg3 *tp = netdev_priv(dev); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10712 | |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 10713 | ering->rx_max_pending = tp->rx_std_ring_mask; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10714 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 10715 | ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; |
Michael Chan | 4f81c32 | 2006-03-20 21:33:42 -0800 | [diff] [blame] | 10716 | else |
| 10717 | ering->rx_jumbo_max_pending = 0; |
| 10718 | |
| 10719 | ering->tx_max_pending = TG3_TX_RING_SIZE - 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10720 | |
| 10721 | ering->rx_pending = tp->rx_pending; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10722 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) |
Michael Chan | 4f81c32 | 2006-03-20 21:33:42 -0800 | [diff] [blame] | 10723 | ering->rx_jumbo_pending = tp->rx_jumbo_pending; |
| 10724 | else |
| 10725 | ering->rx_jumbo_pending = 0; |
| 10726 | |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 10727 | ering->tx_pending = tp->napi[0].tx_pending; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10728 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10729 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10730 | static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
| 10731 | { |
| 10732 | struct tg3 *tp = netdev_priv(dev); |
Matt Carlson | 646c9ed | 2009-09-01 12:58:41 +0000 | [diff] [blame] | 10733 | int i, irq_sync = 0, err = 0; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10734 | |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 10735 | if ((ering->rx_pending > tp->rx_std_ring_mask) || |
| 10736 | (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || |
Michael Chan | bc3a925 | 2006-10-18 20:55:18 -0700 | [diff] [blame] | 10737 | (ering->tx_pending > TG3_TX_RING_SIZE - 1) || |
| 10738 | (ering->tx_pending <= MAX_SKB_FRAGS) || |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10739 | (tg3_flag(tp, TSO_BUG) && |
Michael Chan | bc3a925 | 2006-10-18 20:55:18 -0700 | [diff] [blame] | 10740 | (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10741 | return -EINVAL; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10742 | |
Michael Chan | bbe832c | 2005-06-24 20:20:04 -0700 | [diff] [blame] | 10743 | if (netif_running(dev)) { |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10744 | tg3_phy_stop(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10745 | tg3_netif_stop(tp); |
Michael Chan | bbe832c | 2005-06-24 20:20:04 -0700 | [diff] [blame] | 10746 | irq_sync = 1; |
| 10747 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10748 | |
Michael Chan | bbe832c | 2005-06-24 20:20:04 -0700 | [diff] [blame] | 10749 | tg3_full_lock(tp, irq_sync); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10750 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10751 | tp->rx_pending = ering->rx_pending; |
| 10752 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10753 | if (tg3_flag(tp, MAX_RXPEND_64) && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10754 | tp->rx_pending > 63) |
| 10755 | tp->rx_pending = 63; |
| 10756 | tp->rx_jumbo_pending = ering->rx_jumbo_pending; |
Matt Carlson | 646c9ed | 2009-09-01 12:58:41 +0000 | [diff] [blame] | 10757 | |
Matt Carlson | 6fd45cb | 2010-09-15 08:59:57 +0000 | [diff] [blame] | 10758 | for (i = 0; i < tp->irq_max; i++) |
Matt Carlson | 646c9ed | 2009-09-01 12:58:41 +0000 | [diff] [blame] | 10759 | tp->napi[i].tx_pending = ering->tx_pending; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10760 | |
| 10761 | if (netif_running(dev)) { |
Michael Chan | 944d980 | 2005-05-29 14:57:48 -0700 | [diff] [blame] | 10762 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
Michael Chan | b9ec6c1 | 2006-07-25 16:37:27 -0700 | [diff] [blame] | 10763 | err = tg3_restart_hw(tp, 1); |
| 10764 | if (!err) |
| 10765 | tg3_netif_start(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10766 | } |
| 10767 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 10768 | tg3_full_unlock(tp); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10769 | |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10770 | if (irq_sync && !err) |
| 10771 | tg3_phy_start(tp); |
| 10772 | |
Michael Chan | b9ec6c1 | 2006-07-25 16:37:27 -0700 | [diff] [blame] | 10773 | return err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10774 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10775 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10776 | static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
| 10777 | { |
| 10778 | struct tg3 *tp = netdev_priv(dev); |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10779 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10780 | epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); |
Matt Carlson | 8d01862 | 2007-12-20 20:05:44 -0800 | [diff] [blame] | 10781 | |
Matt Carlson | 4a2db50 | 2011-12-08 14:40:17 +0000 | [diff] [blame] | 10782 | if (tp->link_config.flowctrl & FLOW_CTRL_RX) |
Matt Carlson | 8d01862 | 2007-12-20 20:05:44 -0800 | [diff] [blame] | 10783 | epause->rx_pause = 1; |
| 10784 | else |
| 10785 | epause->rx_pause = 0; |
| 10786 | |
Matt Carlson | 4a2db50 | 2011-12-08 14:40:17 +0000 | [diff] [blame] | 10787 | if (tp->link_config.flowctrl & FLOW_CTRL_TX) |
Matt Carlson | 8d01862 | 2007-12-20 20:05:44 -0800 | [diff] [blame] | 10788 | epause->tx_pause = 1; |
| 10789 | else |
| 10790 | epause->tx_pause = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10791 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10792 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10793 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
| 10794 | { |
| 10795 | struct tg3 *tp = netdev_priv(dev); |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10796 | int err = 0; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10797 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10798 | if (tg3_flag(tp, USE_PHYLIB)) { |
Matt Carlson | 2712168 | 2010-02-17 15:16:57 +0000 | [diff] [blame] | 10799 | u32 newadv; |
| 10800 | struct phy_device *phydev; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10801 | |
Matt Carlson | 2712168 | 2010-02-17 15:16:57 +0000 | [diff] [blame] | 10802 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10803 | |
Matt Carlson | 2712168 | 2010-02-17 15:16:57 +0000 | [diff] [blame] | 10804 | if (!(phydev->supported & SUPPORTED_Pause) || |
| 10805 | (!(phydev->supported & SUPPORTED_Asym_Pause) && |
Nicolas Kaiser | 2259dca | 2010-10-07 23:29:27 +0000 | [diff] [blame] | 10806 | (epause->rx_pause != epause->tx_pause))) |
Matt Carlson | 2712168 | 2010-02-17 15:16:57 +0000 | [diff] [blame] | 10807 | return -EINVAL; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10808 | |
Matt Carlson | 2712168 | 2010-02-17 15:16:57 +0000 | [diff] [blame] | 10809 | tp->link_config.flowctrl = 0; |
| 10810 | if (epause->rx_pause) { |
| 10811 | tp->link_config.flowctrl |= FLOW_CTRL_RX; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10812 | |
Matt Carlson | 2712168 | 2010-02-17 15:16:57 +0000 | [diff] [blame] | 10813 | if (epause->tx_pause) { |
Steve Glendinning | e18ce34 | 2008-12-16 02:00:00 -0800 | [diff] [blame] | 10814 | tp->link_config.flowctrl |= FLOW_CTRL_TX; |
Matt Carlson | 2712168 | 2010-02-17 15:16:57 +0000 | [diff] [blame] | 10815 | newadv = ADVERTISED_Pause; |
| 10816 | } else |
| 10817 | newadv = ADVERTISED_Pause | |
| 10818 | ADVERTISED_Asym_Pause; |
| 10819 | } else if (epause->tx_pause) { |
| 10820 | tp->link_config.flowctrl |= FLOW_CTRL_TX; |
| 10821 | newadv = ADVERTISED_Asym_Pause; |
| 10822 | } else |
| 10823 | newadv = 0; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10824 | |
Matt Carlson | 2712168 | 2010-02-17 15:16:57 +0000 | [diff] [blame] | 10825 | if (epause->autoneg) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10826 | tg3_flag_set(tp, PAUSE_AUTONEG); |
Matt Carlson | 2712168 | 2010-02-17 15:16:57 +0000 | [diff] [blame] | 10827 | else |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10828 | tg3_flag_clear(tp, PAUSE_AUTONEG); |
Matt Carlson | 2712168 | 2010-02-17 15:16:57 +0000 | [diff] [blame] | 10829 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 10830 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
Matt Carlson | 2712168 | 2010-02-17 15:16:57 +0000 | [diff] [blame] | 10831 | u32 oldadv = phydev->advertising & |
| 10832 | (ADVERTISED_Pause | ADVERTISED_Asym_Pause); |
| 10833 | if (oldadv != newadv) { |
| 10834 | phydev->advertising &= |
| 10835 | ~(ADVERTISED_Pause | |
| 10836 | ADVERTISED_Asym_Pause); |
| 10837 | phydev->advertising |= newadv; |
| 10838 | if (phydev->autoneg) { |
| 10839 | /* |
| 10840 | * Always renegotiate the link to |
| 10841 | * inform our link partner of our |
| 10842 | * flow control settings, even if the |
| 10843 | * flow control is forced. Let |
| 10844 | * tg3_adjust_link() do the final |
| 10845 | * flow control setup. |
| 10846 | */ |
| 10847 | return phy_start_aneg(phydev); |
| 10848 | } |
| 10849 | } |
| 10850 | |
| 10851 | if (!epause->autoneg) |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10852 | tg3_setup_flow_control(tp, 0, 0); |
Matt Carlson | 2712168 | 2010-02-17 15:16:57 +0000 | [diff] [blame] | 10853 | } else { |
| 10854 | tp->link_config.orig_advertising &= |
| 10855 | ~(ADVERTISED_Pause | |
| 10856 | ADVERTISED_Asym_Pause); |
| 10857 | tp->link_config.orig_advertising |= newadv; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10858 | } |
| 10859 | } else { |
| 10860 | int irq_sync = 0; |
| 10861 | |
| 10862 | if (netif_running(dev)) { |
| 10863 | tg3_netif_stop(tp); |
| 10864 | irq_sync = 1; |
| 10865 | } |
| 10866 | |
| 10867 | tg3_full_lock(tp, irq_sync); |
| 10868 | |
| 10869 | if (epause->autoneg) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10870 | tg3_flag_set(tp, PAUSE_AUTONEG); |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10871 | else |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 10872 | tg3_flag_clear(tp, PAUSE_AUTONEG); |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10873 | if (epause->rx_pause) |
Steve Glendinning | e18ce34 | 2008-12-16 02:00:00 -0800 | [diff] [blame] | 10874 | tp->link_config.flowctrl |= FLOW_CTRL_RX; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10875 | else |
Steve Glendinning | e18ce34 | 2008-12-16 02:00:00 -0800 | [diff] [blame] | 10876 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10877 | if (epause->tx_pause) |
Steve Glendinning | e18ce34 | 2008-12-16 02:00:00 -0800 | [diff] [blame] | 10878 | tp->link_config.flowctrl |= FLOW_CTRL_TX; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10879 | else |
Steve Glendinning | e18ce34 | 2008-12-16 02:00:00 -0800 | [diff] [blame] | 10880 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 10881 | |
| 10882 | if (netif_running(dev)) { |
| 10883 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
| 10884 | err = tg3_restart_hw(tp, 1); |
| 10885 | if (!err) |
| 10886 | tg3_netif_start(tp); |
| 10887 | } |
| 10888 | |
| 10889 | tg3_full_unlock(tp); |
Michael Chan | bbe832c | 2005-06-24 20:20:04 -0700 | [diff] [blame] | 10890 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10891 | |
Michael Chan | b9ec6c1 | 2006-07-25 16:37:27 -0700 | [diff] [blame] | 10892 | return err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10893 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 10894 | |
Matt Carlson | de6f31e | 2010-04-12 06:58:30 +0000 | [diff] [blame] | 10895 | static int tg3_get_sset_count(struct net_device *dev, int sset) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10896 | { |
Jeff Garzik | b9f2c04 | 2007-10-03 18:07:32 -0700 | [diff] [blame] | 10897 | switch (sset) { |
| 10898 | case ETH_SS_TEST: |
| 10899 | return TG3_NUM_TEST; |
| 10900 | case ETH_SS_STATS: |
| 10901 | return TG3_NUM_STATS; |
| 10902 | default: |
| 10903 | return -EOPNOTSUPP; |
| 10904 | } |
Michael Chan | 4cafd3f | 2005-05-29 14:56:34 -0700 | [diff] [blame] | 10905 | } |
| 10906 | |
Matt Carlson | 9041547 | 2011-12-16 13:33:23 +0000 | [diff] [blame] | 10907 | static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, |
| 10908 | u32 *rules __always_unused) |
| 10909 | { |
| 10910 | struct tg3 *tp = netdev_priv(dev); |
| 10911 | |
| 10912 | if (!tg3_flag(tp, SUPPORT_MSIX)) |
| 10913 | return -EOPNOTSUPP; |
| 10914 | |
| 10915 | switch (info->cmd) { |
| 10916 | case ETHTOOL_GRXRINGS: |
| 10917 | if (netif_running(tp->dev)) |
| 10918 | info->data = tp->irq_cnt; |
| 10919 | else { |
| 10920 | info->data = num_online_cpus(); |
| 10921 | if (info->data > TG3_IRQ_MAX_VECS_RSS) |
| 10922 | info->data = TG3_IRQ_MAX_VECS_RSS; |
| 10923 | } |
| 10924 | |
| 10925 | /* The first interrupt vector only |
| 10926 | * handles link interrupts. |
| 10927 | */ |
| 10928 | info->data -= 1; |
| 10929 | return 0; |
| 10930 | |
| 10931 | default: |
| 10932 | return -EOPNOTSUPP; |
| 10933 | } |
| 10934 | } |
| 10935 | |
| 10936 | static u32 tg3_get_rxfh_indir_size(struct net_device *dev) |
| 10937 | { |
| 10938 | u32 size = 0; |
| 10939 | struct tg3 *tp = netdev_priv(dev); |
| 10940 | |
| 10941 | if (tg3_flag(tp, SUPPORT_MSIX)) |
| 10942 | size = TG3_RSS_INDIR_TBL_SIZE; |
| 10943 | |
| 10944 | return size; |
| 10945 | } |
| 10946 | |
| 10947 | static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir) |
| 10948 | { |
| 10949 | struct tg3 *tp = netdev_priv(dev); |
| 10950 | int i; |
| 10951 | |
| 10952 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) |
| 10953 | indir[i] = tp->rss_ind_tbl[i]; |
| 10954 | |
| 10955 | return 0; |
| 10956 | } |
| 10957 | |
| 10958 | static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir) |
| 10959 | { |
| 10960 | struct tg3 *tp = netdev_priv(dev); |
| 10961 | size_t i; |
| 10962 | |
| 10963 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) |
| 10964 | tp->rss_ind_tbl[i] = indir[i]; |
| 10965 | |
| 10966 | if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS)) |
| 10967 | return 0; |
| 10968 | |
| 10969 | /* It is legal to write the indirection |
| 10970 | * table while the device is running. |
| 10971 | */ |
| 10972 | tg3_full_lock(tp, 0); |
| 10973 | tg3_rss_write_indir_tbl(tp); |
| 10974 | tg3_full_unlock(tp); |
| 10975 | |
| 10976 | return 0; |
| 10977 | } |
| 10978 | |
Matt Carlson | de6f31e | 2010-04-12 06:58:30 +0000 | [diff] [blame] | 10979 | static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10980 | { |
| 10981 | switch (stringset) { |
| 10982 | case ETH_SS_STATS: |
| 10983 | memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys)); |
| 10984 | break; |
Michael Chan | 4cafd3f | 2005-05-29 14:56:34 -0700 | [diff] [blame] | 10985 | case ETH_SS_TEST: |
| 10986 | memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys)); |
| 10987 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10988 | default: |
| 10989 | WARN_ON(1); /* we need a WARN() */ |
| 10990 | break; |
| 10991 | } |
| 10992 | } |
| 10993 | |
stephen hemminger | 81b8709 | 2011-04-04 08:43:50 +0000 | [diff] [blame] | 10994 | static int tg3_set_phys_id(struct net_device *dev, |
| 10995 | enum ethtool_phys_id_state state) |
Michael Chan | 4009a93 | 2005-09-05 17:52:54 -0700 | [diff] [blame] | 10996 | { |
| 10997 | struct tg3 *tp = netdev_priv(dev); |
Michael Chan | 4009a93 | 2005-09-05 17:52:54 -0700 | [diff] [blame] | 10998 | |
| 10999 | if (!netif_running(tp->dev)) |
| 11000 | return -EAGAIN; |
| 11001 | |
stephen hemminger | 81b8709 | 2011-04-04 08:43:50 +0000 | [diff] [blame] | 11002 | switch (state) { |
| 11003 | case ETHTOOL_ID_ACTIVE: |
Allan, Bruce W | fce5592 | 2011-04-13 13:09:10 +0000 | [diff] [blame] | 11004 | return 1; /* cycle on/off once per second */ |
Michael Chan | 4009a93 | 2005-09-05 17:52:54 -0700 | [diff] [blame] | 11005 | |
stephen hemminger | 81b8709 | 2011-04-04 08:43:50 +0000 | [diff] [blame] | 11006 | case ETHTOOL_ID_ON: |
| 11007 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | |
| 11008 | LED_CTRL_1000MBPS_ON | |
| 11009 | LED_CTRL_100MBPS_ON | |
| 11010 | LED_CTRL_10MBPS_ON | |
| 11011 | LED_CTRL_TRAFFIC_OVERRIDE | |
| 11012 | LED_CTRL_TRAFFIC_BLINK | |
| 11013 | LED_CTRL_TRAFFIC_LED); |
| 11014 | break; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 11015 | |
stephen hemminger | 81b8709 | 2011-04-04 08:43:50 +0000 | [diff] [blame] | 11016 | case ETHTOOL_ID_OFF: |
| 11017 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | |
| 11018 | LED_CTRL_TRAFFIC_OVERRIDE); |
| 11019 | break; |
Michael Chan | 4009a93 | 2005-09-05 17:52:54 -0700 | [diff] [blame] | 11020 | |
stephen hemminger | 81b8709 | 2011-04-04 08:43:50 +0000 | [diff] [blame] | 11021 | case ETHTOOL_ID_INACTIVE: |
| 11022 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
| 11023 | break; |
Michael Chan | 4009a93 | 2005-09-05 17:52:54 -0700 | [diff] [blame] | 11024 | } |
stephen hemminger | 81b8709 | 2011-04-04 08:43:50 +0000 | [diff] [blame] | 11025 | |
Michael Chan | 4009a93 | 2005-09-05 17:52:54 -0700 | [diff] [blame] | 11026 | return 0; |
| 11027 | } |
| 11028 | |
Matt Carlson | de6f31e | 2010-04-12 06:58:30 +0000 | [diff] [blame] | 11029 | static void tg3_get_ethtool_stats(struct net_device *dev, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11030 | struct ethtool_stats *estats, u64 *tmp_stats) |
| 11031 | { |
| 11032 | struct tg3 *tp = netdev_priv(dev); |
Matt Carlson | 0e6c9da | 2011-12-08 14:40:13 +0000 | [diff] [blame] | 11033 | |
| 11034 | tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11035 | } |
| 11036 | |
Matt Carlson | 535a490 | 2011-07-20 10:20:56 +0000 | [diff] [blame] | 11037 | static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen) |
Matt Carlson | c3e9450 | 2011-04-13 11:05:08 +0000 | [diff] [blame] | 11038 | { |
| 11039 | int i; |
| 11040 | __be32 *buf; |
| 11041 | u32 offset = 0, len = 0; |
| 11042 | u32 magic, val; |
| 11043 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 11044 | if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic)) |
Matt Carlson | c3e9450 | 2011-04-13 11:05:08 +0000 | [diff] [blame] | 11045 | return NULL; |
| 11046 | |
| 11047 | if (magic == TG3_EEPROM_MAGIC) { |
| 11048 | for (offset = TG3_NVM_DIR_START; |
| 11049 | offset < TG3_NVM_DIR_END; |
| 11050 | offset += TG3_NVM_DIRENT_SIZE) { |
| 11051 | if (tg3_nvram_read(tp, offset, &val)) |
| 11052 | return NULL; |
| 11053 | |
| 11054 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == |
| 11055 | TG3_NVM_DIRTYPE_EXTVPD) |
| 11056 | break; |
| 11057 | } |
| 11058 | |
| 11059 | if (offset != TG3_NVM_DIR_END) { |
| 11060 | len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4; |
| 11061 | if (tg3_nvram_read(tp, offset + 4, &offset)) |
| 11062 | return NULL; |
| 11063 | |
| 11064 | offset = tg3_nvram_logical_addr(tp, offset); |
| 11065 | } |
| 11066 | } |
| 11067 | |
| 11068 | if (!offset || !len) { |
| 11069 | offset = TG3_NVM_VPD_OFF; |
| 11070 | len = TG3_NVM_VPD_LEN; |
| 11071 | } |
| 11072 | |
| 11073 | buf = kmalloc(len, GFP_KERNEL); |
| 11074 | if (buf == NULL) |
| 11075 | return NULL; |
| 11076 | |
| 11077 | if (magic == TG3_EEPROM_MAGIC) { |
| 11078 | for (i = 0; i < len; i += 4) { |
| 11079 | /* The data is in little-endian format in NVRAM. |
| 11080 | * Use the big-endian read routines to preserve |
| 11081 | * the byte order as it exists in NVRAM. |
| 11082 | */ |
| 11083 | if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4])) |
| 11084 | goto error; |
| 11085 | } |
| 11086 | } else { |
| 11087 | u8 *ptr; |
| 11088 | ssize_t cnt; |
| 11089 | unsigned int pos = 0; |
| 11090 | |
| 11091 | ptr = (u8 *)&buf[0]; |
| 11092 | for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) { |
| 11093 | cnt = pci_read_vpd(tp->pdev, pos, |
| 11094 | len - pos, ptr); |
| 11095 | if (cnt == -ETIMEDOUT || cnt == -EINTR) |
| 11096 | cnt = 0; |
| 11097 | else if (cnt < 0) |
| 11098 | goto error; |
| 11099 | } |
| 11100 | if (pos != len) |
| 11101 | goto error; |
| 11102 | } |
| 11103 | |
Matt Carlson | 535a490 | 2011-07-20 10:20:56 +0000 | [diff] [blame] | 11104 | *vpdlen = len; |
| 11105 | |
Matt Carlson | c3e9450 | 2011-04-13 11:05:08 +0000 | [diff] [blame] | 11106 | return buf; |
| 11107 | |
| 11108 | error: |
| 11109 | kfree(buf); |
| 11110 | return NULL; |
| 11111 | } |
| 11112 | |
Michael Chan | 566f86a | 2005-05-29 14:56:58 -0700 | [diff] [blame] | 11113 | #define NVRAM_TEST_SIZE 0x100 |
Matt Carlson | a5767de | 2007-11-12 21:10:58 -0800 | [diff] [blame] | 11114 | #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14 |
| 11115 | #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18 |
| 11116 | #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c |
Matt Carlson | 727a6d9 | 2011-06-13 13:38:58 +0000 | [diff] [blame] | 11117 | #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20 |
| 11118 | #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24 |
Matt Carlson | bda18fa | 2011-07-20 10:20:57 +0000 | [diff] [blame] | 11119 | #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50 |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 11120 | #define NVRAM_SELFBOOT_HW_SIZE 0x20 |
| 11121 | #define NVRAM_SELFBOOT_DATA_SIZE 0x1c |
Michael Chan | 566f86a | 2005-05-29 14:56:58 -0700 | [diff] [blame] | 11122 | |
| 11123 | static int tg3_test_nvram(struct tg3 *tp) |
| 11124 | { |
Matt Carlson | 535a490 | 2011-07-20 10:20:56 +0000 | [diff] [blame] | 11125 | u32 csum, magic, len; |
Matt Carlson | a9dc529 | 2009-02-25 14:25:30 +0000 | [diff] [blame] | 11126 | __be32 *buf; |
Andy Gospodarek | ab0049b | 2007-09-06 20:42:14 +0100 | [diff] [blame] | 11127 | int i, j, k, err = 0, size; |
Michael Chan | 566f86a | 2005-05-29 14:56:58 -0700 | [diff] [blame] | 11128 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 11129 | if (tg3_flag(tp, NO_NVRAM)) |
Matt Carlson | df259d8 | 2009-04-20 06:57:14 +0000 | [diff] [blame] | 11130 | return 0; |
| 11131 | |
Matt Carlson | e4f3411 | 2009-02-25 14:25:00 +0000 | [diff] [blame] | 11132 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
Michael Chan | 1b27777 | 2006-03-20 22:27:48 -0800 | [diff] [blame] | 11133 | return -EIO; |
| 11134 | |
Michael Chan | 1b27777 | 2006-03-20 22:27:48 -0800 | [diff] [blame] | 11135 | if (magic == TG3_EEPROM_MAGIC) |
| 11136 | size = NVRAM_TEST_SIZE; |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 11137 | else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { |
Matt Carlson | a5767de | 2007-11-12 21:10:58 -0800 | [diff] [blame] | 11138 | if ((magic & TG3_EEPROM_SB_FORMAT_MASK) == |
| 11139 | TG3_EEPROM_SB_FORMAT_1) { |
| 11140 | switch (magic & TG3_EEPROM_SB_REVISION_MASK) { |
| 11141 | case TG3_EEPROM_SB_REVISION_0: |
| 11142 | size = NVRAM_SELFBOOT_FORMAT1_0_SIZE; |
| 11143 | break; |
| 11144 | case TG3_EEPROM_SB_REVISION_2: |
| 11145 | size = NVRAM_SELFBOOT_FORMAT1_2_SIZE; |
| 11146 | break; |
| 11147 | case TG3_EEPROM_SB_REVISION_3: |
| 11148 | size = NVRAM_SELFBOOT_FORMAT1_3_SIZE; |
| 11149 | break; |
Matt Carlson | 727a6d9 | 2011-06-13 13:38:58 +0000 | [diff] [blame] | 11150 | case TG3_EEPROM_SB_REVISION_4: |
| 11151 | size = NVRAM_SELFBOOT_FORMAT1_4_SIZE; |
| 11152 | break; |
| 11153 | case TG3_EEPROM_SB_REVISION_5: |
| 11154 | size = NVRAM_SELFBOOT_FORMAT1_5_SIZE; |
| 11155 | break; |
| 11156 | case TG3_EEPROM_SB_REVISION_6: |
| 11157 | size = NVRAM_SELFBOOT_FORMAT1_6_SIZE; |
| 11158 | break; |
Matt Carlson | a5767de | 2007-11-12 21:10:58 -0800 | [diff] [blame] | 11159 | default: |
Matt Carlson | 727a6d9 | 2011-06-13 13:38:58 +0000 | [diff] [blame] | 11160 | return -EIO; |
Matt Carlson | a5767de | 2007-11-12 21:10:58 -0800 | [diff] [blame] | 11161 | } |
| 11162 | } else |
Michael Chan | 1b27777 | 2006-03-20 22:27:48 -0800 | [diff] [blame] | 11163 | return 0; |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 11164 | } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
| 11165 | size = NVRAM_SELFBOOT_HW_SIZE; |
| 11166 | else |
Michael Chan | 1b27777 | 2006-03-20 22:27:48 -0800 | [diff] [blame] | 11167 | return -EIO; |
| 11168 | |
| 11169 | buf = kmalloc(size, GFP_KERNEL); |
Michael Chan | 566f86a | 2005-05-29 14:56:58 -0700 | [diff] [blame] | 11170 | if (buf == NULL) |
| 11171 | return -ENOMEM; |
| 11172 | |
Michael Chan | 1b27777 | 2006-03-20 22:27:48 -0800 | [diff] [blame] | 11173 | err = -EIO; |
| 11174 | for (i = 0, j = 0; i < size; i += 4, j++) { |
Matt Carlson | a9dc529 | 2009-02-25 14:25:30 +0000 | [diff] [blame] | 11175 | err = tg3_nvram_read_be32(tp, i, &buf[j]); |
| 11176 | if (err) |
Michael Chan | 566f86a | 2005-05-29 14:56:58 -0700 | [diff] [blame] | 11177 | break; |
Michael Chan | 566f86a | 2005-05-29 14:56:58 -0700 | [diff] [blame] | 11178 | } |
Michael Chan | 1b27777 | 2006-03-20 22:27:48 -0800 | [diff] [blame] | 11179 | if (i < size) |
Michael Chan | 566f86a | 2005-05-29 14:56:58 -0700 | [diff] [blame] | 11180 | goto out; |
| 11181 | |
Michael Chan | 1b27777 | 2006-03-20 22:27:48 -0800 | [diff] [blame] | 11182 | /* Selfboot format */ |
Matt Carlson | a9dc529 | 2009-02-25 14:25:30 +0000 | [diff] [blame] | 11183 | magic = be32_to_cpu(buf[0]); |
Al Viro | b9fc7dc | 2007-12-17 22:59:57 -0800 | [diff] [blame] | 11184 | if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 11185 | TG3_EEPROM_MAGIC_FW) { |
Michael Chan | 1b27777 | 2006-03-20 22:27:48 -0800 | [diff] [blame] | 11186 | u8 *buf8 = (u8 *) buf, csum8 = 0; |
| 11187 | |
Al Viro | b9fc7dc | 2007-12-17 22:59:57 -0800 | [diff] [blame] | 11188 | if ((magic & TG3_EEPROM_SB_REVISION_MASK) == |
Matt Carlson | a5767de | 2007-11-12 21:10:58 -0800 | [diff] [blame] | 11189 | TG3_EEPROM_SB_REVISION_2) { |
| 11190 | /* For rev 2, the csum doesn't include the MBA. */ |
| 11191 | for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++) |
| 11192 | csum8 += buf8[i]; |
| 11193 | for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++) |
| 11194 | csum8 += buf8[i]; |
| 11195 | } else { |
| 11196 | for (i = 0; i < size; i++) |
| 11197 | csum8 += buf8[i]; |
| 11198 | } |
Michael Chan | 1b27777 | 2006-03-20 22:27:48 -0800 | [diff] [blame] | 11199 | |
Adrian Bunk | ad96b48 | 2006-04-05 22:21:04 -0700 | [diff] [blame] | 11200 | if (csum8 == 0) { |
| 11201 | err = 0; |
| 11202 | goto out; |
| 11203 | } |
| 11204 | |
| 11205 | err = -EIO; |
| 11206 | goto out; |
Michael Chan | 1b27777 | 2006-03-20 22:27:48 -0800 | [diff] [blame] | 11207 | } |
Michael Chan | 566f86a | 2005-05-29 14:56:58 -0700 | [diff] [blame] | 11208 | |
Al Viro | b9fc7dc | 2007-12-17 22:59:57 -0800 | [diff] [blame] | 11209 | if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 11210 | TG3_EEPROM_MAGIC_HW) { |
| 11211 | u8 data[NVRAM_SELFBOOT_DATA_SIZE]; |
Matt Carlson | a9dc529 | 2009-02-25 14:25:30 +0000 | [diff] [blame] | 11212 | u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 11213 | u8 *buf8 = (u8 *) buf; |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 11214 | |
| 11215 | /* Separate the parity bits and the data bytes. */ |
| 11216 | for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { |
| 11217 | if ((i == 0) || (i == 8)) { |
| 11218 | int l; |
| 11219 | u8 msk; |
| 11220 | |
| 11221 | for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) |
| 11222 | parity[k++] = buf8[i] & msk; |
| 11223 | i++; |
Matt Carlson | 859a58879 | 2010-04-05 10:19:28 +0000 | [diff] [blame] | 11224 | } else if (i == 16) { |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 11225 | int l; |
| 11226 | u8 msk; |
| 11227 | |
| 11228 | for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1) |
| 11229 | parity[k++] = buf8[i] & msk; |
| 11230 | i++; |
| 11231 | |
| 11232 | for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1) |
| 11233 | parity[k++] = buf8[i] & msk; |
| 11234 | i++; |
| 11235 | } |
| 11236 | data[j++] = buf8[i]; |
| 11237 | } |
| 11238 | |
| 11239 | err = -EIO; |
| 11240 | for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) { |
| 11241 | u8 hw8 = hweight8(data[i]); |
| 11242 | |
| 11243 | if ((hw8 & 0x1) && parity[i]) |
| 11244 | goto out; |
| 11245 | else if (!(hw8 & 0x1) && !parity[i]) |
| 11246 | goto out; |
| 11247 | } |
| 11248 | err = 0; |
| 11249 | goto out; |
| 11250 | } |
| 11251 | |
Matt Carlson | 01c3a39 | 2011-03-09 16:58:20 +0000 | [diff] [blame] | 11252 | err = -EIO; |
| 11253 | |
Michael Chan | 566f86a | 2005-05-29 14:56:58 -0700 | [diff] [blame] | 11254 | /* Bootstrap checksum at offset 0x10 */ |
| 11255 | csum = calc_crc((unsigned char *) buf, 0x10); |
Matt Carlson | 01c3a39 | 2011-03-09 16:58:20 +0000 | [diff] [blame] | 11256 | if (csum != le32_to_cpu(buf[0x10/4])) |
Michael Chan | 566f86a | 2005-05-29 14:56:58 -0700 | [diff] [blame] | 11257 | goto out; |
| 11258 | |
| 11259 | /* Manufacturing block starts at offset 0x74, checksum at 0xfc */ |
| 11260 | csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88); |
Matt Carlson | 01c3a39 | 2011-03-09 16:58:20 +0000 | [diff] [blame] | 11261 | if (csum != le32_to_cpu(buf[0xfc/4])) |
Matt Carlson | a9dc529 | 2009-02-25 14:25:30 +0000 | [diff] [blame] | 11262 | goto out; |
Michael Chan | 566f86a | 2005-05-29 14:56:58 -0700 | [diff] [blame] | 11263 | |
Matt Carlson | c3e9450 | 2011-04-13 11:05:08 +0000 | [diff] [blame] | 11264 | kfree(buf); |
| 11265 | |
Matt Carlson | 535a490 | 2011-07-20 10:20:56 +0000 | [diff] [blame] | 11266 | buf = tg3_vpd_readblock(tp, &len); |
Matt Carlson | c3e9450 | 2011-04-13 11:05:08 +0000 | [diff] [blame] | 11267 | if (!buf) |
| 11268 | return -ENOMEM; |
Matt Carlson | d4894f3 | 2011-03-09 16:58:21 +0000 | [diff] [blame] | 11269 | |
Matt Carlson | 535a490 | 2011-07-20 10:20:56 +0000 | [diff] [blame] | 11270 | i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA); |
Matt Carlson | d4894f3 | 2011-03-09 16:58:21 +0000 | [diff] [blame] | 11271 | if (i > 0) { |
| 11272 | j = pci_vpd_lrdt_size(&((u8 *)buf)[i]); |
| 11273 | if (j < 0) |
| 11274 | goto out; |
| 11275 | |
Matt Carlson | 535a490 | 2011-07-20 10:20:56 +0000 | [diff] [blame] | 11276 | if (i + PCI_VPD_LRDT_TAG_SIZE + j > len) |
Matt Carlson | d4894f3 | 2011-03-09 16:58:21 +0000 | [diff] [blame] | 11277 | goto out; |
| 11278 | |
| 11279 | i += PCI_VPD_LRDT_TAG_SIZE; |
| 11280 | j = pci_vpd_find_info_keyword((u8 *)buf, i, j, |
| 11281 | PCI_VPD_RO_KEYWORD_CHKSUM); |
| 11282 | if (j > 0) { |
| 11283 | u8 csum8 = 0; |
| 11284 | |
| 11285 | j += PCI_VPD_INFO_FLD_HDR_SIZE; |
| 11286 | |
| 11287 | for (i = 0; i <= j; i++) |
| 11288 | csum8 += ((u8 *)buf)[i]; |
| 11289 | |
| 11290 | if (csum8) |
| 11291 | goto out; |
| 11292 | } |
| 11293 | } |
| 11294 | |
Michael Chan | 566f86a | 2005-05-29 14:56:58 -0700 | [diff] [blame] | 11295 | err = 0; |
| 11296 | |
| 11297 | out: |
| 11298 | kfree(buf); |
| 11299 | return err; |
| 11300 | } |
| 11301 | |
Michael Chan | ca43007 | 2005-05-29 14:57:23 -0700 | [diff] [blame] | 11302 | #define TG3_SERDES_TIMEOUT_SEC 2 |
| 11303 | #define TG3_COPPER_TIMEOUT_SEC 6 |
| 11304 | |
| 11305 | static int tg3_test_link(struct tg3 *tp) |
| 11306 | { |
| 11307 | int i, max; |
| 11308 | |
| 11309 | if (!netif_running(tp->dev)) |
| 11310 | return -ENODEV; |
| 11311 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 11312 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
Michael Chan | ca43007 | 2005-05-29 14:57:23 -0700 | [diff] [blame] | 11313 | max = TG3_SERDES_TIMEOUT_SEC; |
| 11314 | else |
| 11315 | max = TG3_COPPER_TIMEOUT_SEC; |
| 11316 | |
| 11317 | for (i = 0; i < max; i++) { |
| 11318 | if (netif_carrier_ok(tp->dev)) |
| 11319 | return 0; |
| 11320 | |
| 11321 | if (msleep_interruptible(1000)) |
| 11322 | break; |
| 11323 | } |
| 11324 | |
| 11325 | return -EIO; |
| 11326 | } |
| 11327 | |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 11328 | /* Only test the commonly used registers */ |
David S. Miller | 30ca3e3 | 2006-03-20 23:02:36 -0800 | [diff] [blame] | 11329 | static int tg3_test_registers(struct tg3 *tp) |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 11330 | { |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 11331 | int i, is_5705, is_5750; |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 11332 | u32 offset, read_mask, write_mask, val, save_val, read_val; |
| 11333 | static struct { |
| 11334 | u16 offset; |
| 11335 | u16 flags; |
| 11336 | #define TG3_FL_5705 0x1 |
| 11337 | #define TG3_FL_NOT_5705 0x2 |
| 11338 | #define TG3_FL_NOT_5788 0x4 |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 11339 | #define TG3_FL_NOT_5750 0x8 |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 11340 | u32 read_mask; |
| 11341 | u32 write_mask; |
| 11342 | } reg_tbl[] = { |
| 11343 | /* MAC Control Registers */ |
| 11344 | { MAC_MODE, TG3_FL_NOT_5705, |
| 11345 | 0x00000000, 0x00ef6f8c }, |
| 11346 | { MAC_MODE, TG3_FL_5705, |
| 11347 | 0x00000000, 0x01ef6b8c }, |
| 11348 | { MAC_STATUS, TG3_FL_NOT_5705, |
| 11349 | 0x03800107, 0x00000000 }, |
| 11350 | { MAC_STATUS, TG3_FL_5705, |
| 11351 | 0x03800100, 0x00000000 }, |
| 11352 | { MAC_ADDR_0_HIGH, 0x0000, |
| 11353 | 0x00000000, 0x0000ffff }, |
| 11354 | { MAC_ADDR_0_LOW, 0x0000, |
Matt Carlson | c6cdf43 | 2010-04-05 10:19:26 +0000 | [diff] [blame] | 11355 | 0x00000000, 0xffffffff }, |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 11356 | { MAC_RX_MTU_SIZE, 0x0000, |
| 11357 | 0x00000000, 0x0000ffff }, |
| 11358 | { MAC_TX_MODE, 0x0000, |
| 11359 | 0x00000000, 0x00000070 }, |
| 11360 | { MAC_TX_LENGTHS, 0x0000, |
| 11361 | 0x00000000, 0x00003fff }, |
| 11362 | { MAC_RX_MODE, TG3_FL_NOT_5705, |
| 11363 | 0x00000000, 0x000007fc }, |
| 11364 | { MAC_RX_MODE, TG3_FL_5705, |
| 11365 | 0x00000000, 0x000007dc }, |
| 11366 | { MAC_HASH_REG_0, 0x0000, |
| 11367 | 0x00000000, 0xffffffff }, |
| 11368 | { MAC_HASH_REG_1, 0x0000, |
| 11369 | 0x00000000, 0xffffffff }, |
| 11370 | { MAC_HASH_REG_2, 0x0000, |
| 11371 | 0x00000000, 0xffffffff }, |
| 11372 | { MAC_HASH_REG_3, 0x0000, |
| 11373 | 0x00000000, 0xffffffff }, |
| 11374 | |
| 11375 | /* Receive Data and Receive BD Initiator Control Registers. */ |
| 11376 | { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705, |
| 11377 | 0x00000000, 0xffffffff }, |
| 11378 | { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705, |
| 11379 | 0x00000000, 0xffffffff }, |
| 11380 | { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705, |
| 11381 | 0x00000000, 0x00000003 }, |
| 11382 | { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705, |
| 11383 | 0x00000000, 0xffffffff }, |
| 11384 | { RCVDBDI_STD_BD+0, 0x0000, |
| 11385 | 0x00000000, 0xffffffff }, |
| 11386 | { RCVDBDI_STD_BD+4, 0x0000, |
| 11387 | 0x00000000, 0xffffffff }, |
| 11388 | { RCVDBDI_STD_BD+8, 0x0000, |
| 11389 | 0x00000000, 0xffff0002 }, |
| 11390 | { RCVDBDI_STD_BD+0xc, 0x0000, |
| 11391 | 0x00000000, 0xffffffff }, |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 11392 | |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 11393 | /* Receive BD Initiator Control Registers. */ |
| 11394 | { RCVBDI_STD_THRESH, TG3_FL_NOT_5705, |
| 11395 | 0x00000000, 0xffffffff }, |
| 11396 | { RCVBDI_STD_THRESH, TG3_FL_5705, |
| 11397 | 0x00000000, 0x000003ff }, |
| 11398 | { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705, |
| 11399 | 0x00000000, 0xffffffff }, |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 11400 | |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 11401 | /* Host Coalescing Control Registers. */ |
| 11402 | { HOSTCC_MODE, TG3_FL_NOT_5705, |
| 11403 | 0x00000000, 0x00000004 }, |
| 11404 | { HOSTCC_MODE, TG3_FL_5705, |
| 11405 | 0x00000000, 0x000000f6 }, |
| 11406 | { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705, |
| 11407 | 0x00000000, 0xffffffff }, |
| 11408 | { HOSTCC_RXCOL_TICKS, TG3_FL_5705, |
| 11409 | 0x00000000, 0x000003ff }, |
| 11410 | { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705, |
| 11411 | 0x00000000, 0xffffffff }, |
| 11412 | { HOSTCC_TXCOL_TICKS, TG3_FL_5705, |
| 11413 | 0x00000000, 0x000003ff }, |
| 11414 | { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705, |
| 11415 | 0x00000000, 0xffffffff }, |
| 11416 | { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, |
| 11417 | 0x00000000, 0x000000ff }, |
| 11418 | { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705, |
| 11419 | 0x00000000, 0xffffffff }, |
| 11420 | { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, |
| 11421 | 0x00000000, 0x000000ff }, |
| 11422 | { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705, |
| 11423 | 0x00000000, 0xffffffff }, |
| 11424 | { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705, |
| 11425 | 0x00000000, 0xffffffff }, |
| 11426 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705, |
| 11427 | 0x00000000, 0xffffffff }, |
| 11428 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, |
| 11429 | 0x00000000, 0x000000ff }, |
| 11430 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705, |
| 11431 | 0x00000000, 0xffffffff }, |
| 11432 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, |
| 11433 | 0x00000000, 0x000000ff }, |
| 11434 | { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705, |
| 11435 | 0x00000000, 0xffffffff }, |
| 11436 | { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705, |
| 11437 | 0x00000000, 0xffffffff }, |
| 11438 | { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705, |
| 11439 | 0x00000000, 0xffffffff }, |
| 11440 | { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, |
| 11441 | 0x00000000, 0xffffffff }, |
| 11442 | { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, |
| 11443 | 0x00000000, 0xffffffff }, |
| 11444 | { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000, |
| 11445 | 0xffffffff, 0x00000000 }, |
| 11446 | { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000, |
| 11447 | 0xffffffff, 0x00000000 }, |
| 11448 | |
| 11449 | /* Buffer Manager Control Registers. */ |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 11450 | { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750, |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 11451 | 0x00000000, 0x007fff80 }, |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 11452 | { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750, |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 11453 | 0x00000000, 0x007fffff }, |
| 11454 | { BUFMGR_MB_RDMA_LOW_WATER, 0x0000, |
| 11455 | 0x00000000, 0x0000003f }, |
| 11456 | { BUFMGR_MB_MACRX_LOW_WATER, 0x0000, |
| 11457 | 0x00000000, 0x000001ff }, |
| 11458 | { BUFMGR_MB_HIGH_WATER, 0x0000, |
| 11459 | 0x00000000, 0x000001ff }, |
| 11460 | { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705, |
| 11461 | 0xffffffff, 0x00000000 }, |
| 11462 | { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705, |
| 11463 | 0xffffffff, 0x00000000 }, |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 11464 | |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 11465 | /* Mailbox Registers */ |
| 11466 | { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, |
| 11467 | 0x00000000, 0x000001ff }, |
| 11468 | { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705, |
| 11469 | 0x00000000, 0x000001ff }, |
| 11470 | { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000, |
| 11471 | 0x00000000, 0x000007ff }, |
| 11472 | { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000, |
| 11473 | 0x00000000, 0x000001ff }, |
| 11474 | |
| 11475 | { 0xffff, 0x0000, 0x00000000, 0x00000000 }, |
| 11476 | }; |
| 11477 | |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 11478 | is_5705 = is_5750 = 0; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 11479 | if (tg3_flag(tp, 5705_PLUS)) { |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 11480 | is_5705 = 1; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 11481 | if (tg3_flag(tp, 5750_PLUS)) |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 11482 | is_5750 = 1; |
| 11483 | } |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 11484 | |
| 11485 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { |
| 11486 | if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) |
| 11487 | continue; |
| 11488 | |
| 11489 | if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) |
| 11490 | continue; |
| 11491 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 11492 | if (tg3_flag(tp, IS_5788) && |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 11493 | (reg_tbl[i].flags & TG3_FL_NOT_5788)) |
| 11494 | continue; |
| 11495 | |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 11496 | if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) |
| 11497 | continue; |
| 11498 | |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 11499 | offset = (u32) reg_tbl[i].offset; |
| 11500 | read_mask = reg_tbl[i].read_mask; |
| 11501 | write_mask = reg_tbl[i].write_mask; |
| 11502 | |
| 11503 | /* Save the original register content */ |
| 11504 | save_val = tr32(offset); |
| 11505 | |
| 11506 | /* Determine the read-only value. */ |
| 11507 | read_val = save_val & read_mask; |
| 11508 | |
| 11509 | /* Write zero to the register, then make sure the read-only bits |
| 11510 | * are not changed and the read/write bits are all zeros. |
| 11511 | */ |
| 11512 | tw32(offset, 0); |
| 11513 | |
| 11514 | val = tr32(offset); |
| 11515 | |
| 11516 | /* Test the read-only and read/write bits. */ |
| 11517 | if (((val & read_mask) != read_val) || (val & write_mask)) |
| 11518 | goto out; |
| 11519 | |
| 11520 | /* Write ones to all the bits defined by RdMask and WrMask, then |
| 11521 | * make sure the read-only bits are not changed and the |
| 11522 | * read/write bits are all ones. |
| 11523 | */ |
| 11524 | tw32(offset, read_mask | write_mask); |
| 11525 | |
| 11526 | val = tr32(offset); |
| 11527 | |
| 11528 | /* Test the read-only bits. */ |
| 11529 | if ((val & read_mask) != read_val) |
| 11530 | goto out; |
| 11531 | |
| 11532 | /* Test the read/write bits. */ |
| 11533 | if ((val & write_mask) != write_mask) |
| 11534 | goto out; |
| 11535 | |
| 11536 | tw32(offset, save_val); |
| 11537 | } |
| 11538 | |
| 11539 | return 0; |
| 11540 | |
| 11541 | out: |
Michael Chan | 9f88f29 | 2006-12-07 00:22:54 -0800 | [diff] [blame] | 11542 | if (netif_msg_hw(tp)) |
Matt Carlson | 2445e46 | 2010-04-05 10:19:21 +0000 | [diff] [blame] | 11543 | netdev_err(tp->dev, |
| 11544 | "Register test failed at offset %x\n", offset); |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 11545 | tw32(offset, save_val); |
| 11546 | return -EIO; |
| 11547 | } |
| 11548 | |
Michael Chan | 7942e1d | 2005-05-29 14:58:36 -0700 | [diff] [blame] | 11549 | static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) |
| 11550 | { |
Arjan van de Ven | f71e130 | 2006-03-03 21:33:57 -0500 | [diff] [blame] | 11551 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a }; |
Michael Chan | 7942e1d | 2005-05-29 14:58:36 -0700 | [diff] [blame] | 11552 | int i; |
| 11553 | u32 j; |
| 11554 | |
Alejandro Martinez Ruiz | e9edda6 | 2007-10-15 03:37:43 +0200 | [diff] [blame] | 11555 | for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { |
Michael Chan | 7942e1d | 2005-05-29 14:58:36 -0700 | [diff] [blame] | 11556 | for (j = 0; j < len; j += 4) { |
| 11557 | u32 val; |
| 11558 | |
| 11559 | tg3_write_mem(tp, offset + j, test_pattern[i]); |
| 11560 | tg3_read_mem(tp, offset + j, &val); |
| 11561 | if (val != test_pattern[i]) |
| 11562 | return -EIO; |
| 11563 | } |
| 11564 | } |
| 11565 | return 0; |
| 11566 | } |
| 11567 | |
| 11568 | static int tg3_test_memory(struct tg3 *tp) |
| 11569 | { |
| 11570 | static struct mem_entry { |
| 11571 | u32 offset; |
| 11572 | u32 len; |
| 11573 | } mem_tbl_570x[] = { |
Michael Chan | 3869019 | 2005-12-19 16:27:28 -0800 | [diff] [blame] | 11574 | { 0x00000000, 0x00b50}, |
Michael Chan | 7942e1d | 2005-05-29 14:58:36 -0700 | [diff] [blame] | 11575 | { 0x00002000, 0x1c000}, |
| 11576 | { 0xffffffff, 0x00000} |
| 11577 | }, mem_tbl_5705[] = { |
| 11578 | { 0x00000100, 0x0000c}, |
| 11579 | { 0x00000200, 0x00008}, |
Michael Chan | 7942e1d | 2005-05-29 14:58:36 -0700 | [diff] [blame] | 11580 | { 0x00004000, 0x00800}, |
| 11581 | { 0x00006000, 0x01000}, |
| 11582 | { 0x00008000, 0x02000}, |
| 11583 | { 0x00010000, 0x0e000}, |
| 11584 | { 0xffffffff, 0x00000} |
Michael Chan | 79f4d13 | 2006-03-20 22:28:57 -0800 | [diff] [blame] | 11585 | }, mem_tbl_5755[] = { |
| 11586 | { 0x00000200, 0x00008}, |
| 11587 | { 0x00004000, 0x00800}, |
| 11588 | { 0x00006000, 0x00800}, |
| 11589 | { 0x00008000, 0x02000}, |
| 11590 | { 0x00010000, 0x0c000}, |
| 11591 | { 0xffffffff, 0x00000} |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 11592 | }, mem_tbl_5906[] = { |
| 11593 | { 0x00000200, 0x00008}, |
| 11594 | { 0x00004000, 0x00400}, |
| 11595 | { 0x00006000, 0x00400}, |
| 11596 | { 0x00008000, 0x01000}, |
| 11597 | { 0x00010000, 0x01000}, |
| 11598 | { 0xffffffff, 0x00000} |
Matt Carlson | 8b5a6c4 | 2010-01-20 16:58:06 +0000 | [diff] [blame] | 11599 | }, mem_tbl_5717[] = { |
| 11600 | { 0x00000200, 0x00008}, |
| 11601 | { 0x00010000, 0x0a000}, |
| 11602 | { 0x00020000, 0x13c00}, |
| 11603 | { 0xffffffff, 0x00000} |
| 11604 | }, mem_tbl_57765[] = { |
| 11605 | { 0x00000200, 0x00008}, |
| 11606 | { 0x00004000, 0x00800}, |
| 11607 | { 0x00006000, 0x09800}, |
| 11608 | { 0x00010000, 0x0a000}, |
| 11609 | { 0xffffffff, 0x00000} |
Michael Chan | 7942e1d | 2005-05-29 14:58:36 -0700 | [diff] [blame] | 11610 | }; |
| 11611 | struct mem_entry *mem_tbl; |
| 11612 | int err = 0; |
| 11613 | int i; |
| 11614 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 11615 | if (tg3_flag(tp, 5717_PLUS)) |
Matt Carlson | 8b5a6c4 | 2010-01-20 16:58:06 +0000 | [diff] [blame] | 11616 | mem_tbl = mem_tbl_5717; |
Matt Carlson | 55086ad | 2011-12-14 11:09:59 +0000 | [diff] [blame] | 11617 | else if (tg3_flag(tp, 57765_CLASS)) |
Matt Carlson | 8b5a6c4 | 2010-01-20 16:58:06 +0000 | [diff] [blame] | 11618 | mem_tbl = mem_tbl_57765; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 11619 | else if (tg3_flag(tp, 5755_PLUS)) |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 11620 | mem_tbl = mem_tbl_5755; |
| 11621 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
| 11622 | mem_tbl = mem_tbl_5906; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 11623 | else if (tg3_flag(tp, 5705_PLUS)) |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 11624 | mem_tbl = mem_tbl_5705; |
| 11625 | else |
Michael Chan | 7942e1d | 2005-05-29 14:58:36 -0700 | [diff] [blame] | 11626 | mem_tbl = mem_tbl_570x; |
| 11627 | |
| 11628 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { |
Matt Carlson | be98da6 | 2010-07-11 09:31:46 +0000 | [diff] [blame] | 11629 | err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len); |
| 11630 | if (err) |
Michael Chan | 7942e1d | 2005-05-29 14:58:36 -0700 | [diff] [blame] | 11631 | break; |
| 11632 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 11633 | |
Michael Chan | 7942e1d | 2005-05-29 14:58:36 -0700 | [diff] [blame] | 11634 | return err; |
| 11635 | } |
| 11636 | |
Matt Carlson | bb158d6 | 2011-04-25 12:42:47 +0000 | [diff] [blame] | 11637 | #define TG3_TSO_MSS 500 |
| 11638 | |
| 11639 | #define TG3_TSO_IP_HDR_LEN 20 |
| 11640 | #define TG3_TSO_TCP_HDR_LEN 20 |
| 11641 | #define TG3_TSO_TCP_OPT_LEN 12 |
| 11642 | |
| 11643 | static const u8 tg3_tso_header[] = { |
| 11644 | 0x08, 0x00, |
| 11645 | 0x45, 0x00, 0x00, 0x00, |
| 11646 | 0x00, 0x00, 0x40, 0x00, |
| 11647 | 0x40, 0x06, 0x00, 0x00, |
| 11648 | 0x0a, 0x00, 0x00, 0x01, |
| 11649 | 0x0a, 0x00, 0x00, 0x02, |
| 11650 | 0x0d, 0x00, 0xe0, 0x00, |
| 11651 | 0x00, 0x00, 0x01, 0x00, |
| 11652 | 0x00, 0x00, 0x02, 0x00, |
| 11653 | 0x80, 0x10, 0x10, 0x00, |
| 11654 | 0x14, 0x09, 0x00, 0x00, |
| 11655 | 0x01, 0x01, 0x08, 0x0a, |
| 11656 | 0x11, 0x11, 0x11, 0x11, |
| 11657 | 0x11, 0x11, 0x11, 0x11, |
| 11658 | }; |
Michael Chan | 9f40dea | 2005-09-05 17:53:06 -0700 | [diff] [blame] | 11659 | |
Matt Carlson | 28a4595 | 2011-08-19 13:58:22 +0000 | [diff] [blame] | 11660 | static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback) |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11661 | { |
Matt Carlson | 5e5a7f3 | 2011-08-19 13:58:21 +0000 | [diff] [blame] | 11662 | u32 rx_start_idx, rx_idx, tx_idx, opaque_key; |
Matt Carlson | bb158d6 | 2011-04-25 12:42:47 +0000 | [diff] [blame] | 11663 | u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val; |
Matt Carlson | 84b67b2 | 2011-07-27 14:20:52 +0000 | [diff] [blame] | 11664 | u32 budget; |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 11665 | struct sk_buff *skb; |
| 11666 | u8 *tx_data, *rx_data; |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11667 | dma_addr_t map; |
| 11668 | int num_pkts, tx_len, rx_len, i, err; |
| 11669 | struct tg3_rx_buffer_desc *desc; |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 11670 | struct tg3_napi *tnapi, *rnapi; |
Matt Carlson | 8fea32b | 2010-09-15 08:59:58 +0000 | [diff] [blame] | 11671 | struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11672 | |
Matt Carlson | c887340 | 2010-02-12 14:47:11 +0000 | [diff] [blame] | 11673 | tnapi = &tp->napi[0]; |
| 11674 | rnapi = &tp->napi[0]; |
Matt Carlson | 0c1d0e2 | 2009-09-01 13:16:33 +0000 | [diff] [blame] | 11675 | if (tp->irq_cnt > 1) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 11676 | if (tg3_flag(tp, ENABLE_RSS)) |
Matt Carlson | 1da85aa | 2010-09-30 10:34:34 +0000 | [diff] [blame] | 11677 | rnapi = &tp->napi[1]; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 11678 | if (tg3_flag(tp, ENABLE_TSS)) |
Matt Carlson | c887340 | 2010-02-12 14:47:11 +0000 | [diff] [blame] | 11679 | tnapi = &tp->napi[1]; |
Matt Carlson | 0c1d0e2 | 2009-09-01 13:16:33 +0000 | [diff] [blame] | 11680 | } |
Matt Carlson | fd2ce37 | 2009-09-01 12:51:13 +0000 | [diff] [blame] | 11681 | coal_now = tnapi->coal_now | rnapi->coal_now; |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 11682 | |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11683 | err = -EIO; |
| 11684 | |
Matt Carlson | 4852a86 | 2011-04-13 11:05:07 +0000 | [diff] [blame] | 11685 | tx_len = pktsz; |
David S. Miller | a20e9c6 | 2006-07-31 22:38:16 -0700 | [diff] [blame] | 11686 | skb = netdev_alloc_skb(tp->dev, tx_len); |
Jesper Juhl | a50bb7b | 2006-05-09 23:14:35 -0700 | [diff] [blame] | 11687 | if (!skb) |
| 11688 | return -ENOMEM; |
| 11689 | |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11690 | tx_data = skb_put(skb, tx_len); |
| 11691 | memcpy(tx_data, tp->dev->dev_addr, 6); |
| 11692 | memset(tx_data + 6, 0x0, 8); |
| 11693 | |
Matt Carlson | 4852a86 | 2011-04-13 11:05:07 +0000 | [diff] [blame] | 11694 | tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN); |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11695 | |
Matt Carlson | 28a4595 | 2011-08-19 13:58:22 +0000 | [diff] [blame] | 11696 | if (tso_loopback) { |
Matt Carlson | bb158d6 | 2011-04-25 12:42:47 +0000 | [diff] [blame] | 11697 | struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN]; |
| 11698 | |
| 11699 | u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN + |
| 11700 | TG3_TSO_TCP_OPT_LEN; |
| 11701 | |
| 11702 | memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header, |
| 11703 | sizeof(tg3_tso_header)); |
| 11704 | mss = TG3_TSO_MSS; |
| 11705 | |
| 11706 | val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header); |
| 11707 | num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS); |
| 11708 | |
| 11709 | /* Set the total length field in the IP header */ |
| 11710 | iph->tot_len = htons((u16)(mss + hdr_len)); |
| 11711 | |
| 11712 | base_flags = (TXD_FLAG_CPU_PRE_DMA | |
| 11713 | TXD_FLAG_CPU_POST_DMA); |
| 11714 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 11715 | if (tg3_flag(tp, HW_TSO_1) || |
| 11716 | tg3_flag(tp, HW_TSO_2) || |
| 11717 | tg3_flag(tp, HW_TSO_3)) { |
Matt Carlson | bb158d6 | 2011-04-25 12:42:47 +0000 | [diff] [blame] | 11718 | struct tcphdr *th; |
| 11719 | val = ETH_HLEN + TG3_TSO_IP_HDR_LEN; |
| 11720 | th = (struct tcphdr *)&tx_data[val]; |
| 11721 | th->check = 0; |
| 11722 | } else |
| 11723 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
| 11724 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 11725 | if (tg3_flag(tp, HW_TSO_3)) { |
Matt Carlson | bb158d6 | 2011-04-25 12:42:47 +0000 | [diff] [blame] | 11726 | mss |= (hdr_len & 0xc) << 12; |
| 11727 | if (hdr_len & 0x10) |
| 11728 | base_flags |= 0x00000010; |
| 11729 | base_flags |= (hdr_len & 0x3e0) << 5; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 11730 | } else if (tg3_flag(tp, HW_TSO_2)) |
Matt Carlson | bb158d6 | 2011-04-25 12:42:47 +0000 | [diff] [blame] | 11731 | mss |= hdr_len << 9; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 11732 | else if (tg3_flag(tp, HW_TSO_1) || |
Matt Carlson | bb158d6 | 2011-04-25 12:42:47 +0000 | [diff] [blame] | 11733 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
| 11734 | mss |= (TG3_TSO_TCP_OPT_LEN << 9); |
| 11735 | } else { |
| 11736 | base_flags |= (TG3_TSO_TCP_OPT_LEN << 10); |
| 11737 | } |
| 11738 | |
| 11739 | data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header); |
| 11740 | } else { |
| 11741 | num_pkts = 1; |
| 11742 | data_off = ETH_HLEN; |
| 11743 | } |
| 11744 | |
| 11745 | for (i = data_off; i < tx_len; i++) |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11746 | tx_data[i] = (u8) (i & 0xff); |
| 11747 | |
Alexander Duyck | f4188d8 | 2009-12-02 16:48:38 +0000 | [diff] [blame] | 11748 | map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); |
| 11749 | if (pci_dma_mapping_error(tp->pdev, map)) { |
Matt Carlson | a21771d | 2009-11-02 14:25:31 +0000 | [diff] [blame] | 11750 | dev_kfree_skb(skb); |
| 11751 | return -EIO; |
| 11752 | } |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11753 | |
Matt Carlson | 0d681b2 | 2011-07-27 14:20:49 +0000 | [diff] [blame] | 11754 | val = tnapi->tx_prod; |
| 11755 | tnapi->tx_buffers[val].skb = skb; |
| 11756 | dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map); |
| 11757 | |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11758 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
Matt Carlson | fd2ce37 | 2009-09-01 12:51:13 +0000 | [diff] [blame] | 11759 | rnapi->coal_now); |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11760 | |
| 11761 | udelay(10); |
| 11762 | |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 11763 | rx_start_idx = rnapi->hw_status->idx[0].rx_producer; |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11764 | |
Matt Carlson | 84b67b2 | 2011-07-27 14:20:52 +0000 | [diff] [blame] | 11765 | budget = tg3_tx_avail(tnapi); |
| 11766 | if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len, |
Matt Carlson | d1a3b73 | 2011-07-27 14:20:51 +0000 | [diff] [blame] | 11767 | base_flags | TXD_FLAG_END, mss, 0)) { |
| 11768 | tnapi->tx_buffers[val].skb = NULL; |
| 11769 | dev_kfree_skb(skb); |
| 11770 | return -EIO; |
| 11771 | } |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11772 | |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 11773 | tnapi->tx_prod++; |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11774 | |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 11775 | tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); |
| 11776 | tr32_mailbox(tnapi->prodmbox); |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11777 | |
| 11778 | udelay(10); |
| 11779 | |
Matt Carlson | 303fc92 | 2009-11-02 14:27:34 +0000 | [diff] [blame] | 11780 | /* 350 usec to allow enough time on some 10/100 Mbps devices. */ |
| 11781 | for (i = 0; i < 35; i++) { |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11782 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
Matt Carlson | fd2ce37 | 2009-09-01 12:51:13 +0000 | [diff] [blame] | 11783 | coal_now); |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11784 | |
| 11785 | udelay(10); |
| 11786 | |
Matt Carlson | 898a56f | 2009-08-28 14:02:40 +0000 | [diff] [blame] | 11787 | tx_idx = tnapi->hw_status->idx[0].tx_consumer; |
| 11788 | rx_idx = rnapi->hw_status->idx[0].rx_producer; |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 11789 | if ((tx_idx == tnapi->tx_prod) && |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11790 | (rx_idx == (rx_start_idx + num_pkts))) |
| 11791 | break; |
| 11792 | } |
| 11793 | |
Matt Carlson | ba1142e | 2011-11-04 09:15:00 +0000 | [diff] [blame] | 11794 | tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1); |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11795 | dev_kfree_skb(skb); |
| 11796 | |
Matt Carlson | f3f3f27 | 2009-08-28 14:03:21 +0000 | [diff] [blame] | 11797 | if (tx_idx != tnapi->tx_prod) |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11798 | goto out; |
| 11799 | |
| 11800 | if (rx_idx != rx_start_idx + num_pkts) |
| 11801 | goto out; |
| 11802 | |
Matt Carlson | bb158d6 | 2011-04-25 12:42:47 +0000 | [diff] [blame] | 11803 | val = data_off; |
| 11804 | while (rx_idx != rx_start_idx) { |
| 11805 | desc = &rnapi->rx_rcb[rx_start_idx++]; |
| 11806 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; |
| 11807 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11808 | |
Matt Carlson | bb158d6 | 2011-04-25 12:42:47 +0000 | [diff] [blame] | 11809 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && |
| 11810 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) |
Matt Carlson | 4852a86 | 2011-04-13 11:05:07 +0000 | [diff] [blame] | 11811 | goto out; |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11812 | |
Matt Carlson | bb158d6 | 2011-04-25 12:42:47 +0000 | [diff] [blame] | 11813 | rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) |
| 11814 | - ETH_FCS_LEN; |
| 11815 | |
Matt Carlson | 28a4595 | 2011-08-19 13:58:22 +0000 | [diff] [blame] | 11816 | if (!tso_loopback) { |
Matt Carlson | bb158d6 | 2011-04-25 12:42:47 +0000 | [diff] [blame] | 11817 | if (rx_len != tx_len) |
| 11818 | goto out; |
| 11819 | |
| 11820 | if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) { |
| 11821 | if (opaque_key != RXD_OPAQUE_RING_STD) |
| 11822 | goto out; |
| 11823 | } else { |
| 11824 | if (opaque_key != RXD_OPAQUE_RING_JUMBO) |
| 11825 | goto out; |
| 11826 | } |
| 11827 | } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && |
| 11828 | (desc->ip_tcp_csum & RXD_TCPCSUM_MASK) |
Matt Carlson | 54e0a67 | 2011-05-19 12:12:50 +0000 | [diff] [blame] | 11829 | >> RXD_TCPCSUM_SHIFT != 0xffff) { |
Matt Carlson | bb158d6 | 2011-04-25 12:42:47 +0000 | [diff] [blame] | 11830 | goto out; |
| 11831 | } |
| 11832 | |
| 11833 | if (opaque_key == RXD_OPAQUE_RING_STD) { |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 11834 | rx_data = tpr->rx_std_buffers[desc_idx].data; |
Matt Carlson | bb158d6 | 2011-04-25 12:42:47 +0000 | [diff] [blame] | 11835 | map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], |
| 11836 | mapping); |
| 11837 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 11838 | rx_data = tpr->rx_jmb_buffers[desc_idx].data; |
Matt Carlson | bb158d6 | 2011-04-25 12:42:47 +0000 | [diff] [blame] | 11839 | map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], |
| 11840 | mapping); |
| 11841 | } else |
Matt Carlson | 4852a86 | 2011-04-13 11:05:07 +0000 | [diff] [blame] | 11842 | goto out; |
| 11843 | |
Matt Carlson | bb158d6 | 2011-04-25 12:42:47 +0000 | [diff] [blame] | 11844 | pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, |
| 11845 | PCI_DMA_FROMDEVICE); |
| 11846 | |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 11847 | rx_data += TG3_RX_OFFSET(tp); |
Matt Carlson | bb158d6 | 2011-04-25 12:42:47 +0000 | [diff] [blame] | 11848 | for (i = data_off; i < rx_len; i++, val++) { |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 11849 | if (*(rx_data + i) != (u8) (val & 0xff)) |
Matt Carlson | bb158d6 | 2011-04-25 12:42:47 +0000 | [diff] [blame] | 11850 | goto out; |
| 11851 | } |
Matt Carlson | 4852a86 | 2011-04-13 11:05:07 +0000 | [diff] [blame] | 11852 | } |
| 11853 | |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11854 | err = 0; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 11855 | |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 11856 | /* tg3_free_rings will unmap and free the rx_data */ |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 11857 | out: |
| 11858 | return err; |
| 11859 | } |
| 11860 | |
Matt Carlson | 00c266b | 2011-04-25 12:42:46 +0000 | [diff] [blame] | 11861 | #define TG3_STD_LOOPBACK_FAILED 1 |
| 11862 | #define TG3_JMB_LOOPBACK_FAILED 2 |
Matt Carlson | bb158d6 | 2011-04-25 12:42:47 +0000 | [diff] [blame] | 11863 | #define TG3_TSO_LOOPBACK_FAILED 4 |
Matt Carlson | 28a4595 | 2011-08-19 13:58:22 +0000 | [diff] [blame] | 11864 | #define TG3_LOOPBACK_FAILED \ |
| 11865 | (TG3_STD_LOOPBACK_FAILED | \ |
| 11866 | TG3_JMB_LOOPBACK_FAILED | \ |
| 11867 | TG3_TSO_LOOPBACK_FAILED) |
Matt Carlson | 00c266b | 2011-04-25 12:42:46 +0000 | [diff] [blame] | 11868 | |
Matt Carlson | 941ec90 | 2011-08-19 13:58:23 +0000 | [diff] [blame] | 11869 | static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk) |
Michael Chan | 9f40dea | 2005-09-05 17:53:06 -0700 | [diff] [blame] | 11870 | { |
Matt Carlson | 28a4595 | 2011-08-19 13:58:22 +0000 | [diff] [blame] | 11871 | int err = -EIO; |
Matt Carlson | 2215e24 | 2011-08-19 13:58:19 +0000 | [diff] [blame] | 11872 | u32 eee_cap; |
Michael Chan | 9f40dea | 2005-09-05 17:53:06 -0700 | [diff] [blame] | 11873 | |
Matt Carlson | ab78904 | 2011-01-25 15:58:54 +0000 | [diff] [blame] | 11874 | eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; |
| 11875 | tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; |
| 11876 | |
Matt Carlson | 28a4595 | 2011-08-19 13:58:22 +0000 | [diff] [blame] | 11877 | if (!netif_running(tp->dev)) { |
| 11878 | data[0] = TG3_LOOPBACK_FAILED; |
| 11879 | data[1] = TG3_LOOPBACK_FAILED; |
Matt Carlson | 941ec90 | 2011-08-19 13:58:23 +0000 | [diff] [blame] | 11880 | if (do_extlpbk) |
| 11881 | data[2] = TG3_LOOPBACK_FAILED; |
Matt Carlson | 28a4595 | 2011-08-19 13:58:22 +0000 | [diff] [blame] | 11882 | goto done; |
| 11883 | } |
| 11884 | |
Michael Chan | b9ec6c1 | 2006-07-25 16:37:27 -0700 | [diff] [blame] | 11885 | err = tg3_reset_hw(tp, 1); |
Matt Carlson | ab78904 | 2011-01-25 15:58:54 +0000 | [diff] [blame] | 11886 | if (err) { |
Matt Carlson | 28a4595 | 2011-08-19 13:58:22 +0000 | [diff] [blame] | 11887 | data[0] = TG3_LOOPBACK_FAILED; |
| 11888 | data[1] = TG3_LOOPBACK_FAILED; |
Matt Carlson | 941ec90 | 2011-08-19 13:58:23 +0000 | [diff] [blame] | 11889 | if (do_extlpbk) |
| 11890 | data[2] = TG3_LOOPBACK_FAILED; |
Matt Carlson | ab78904 | 2011-01-25 15:58:54 +0000 | [diff] [blame] | 11891 | goto done; |
| 11892 | } |
Michael Chan | 9f40dea | 2005-09-05 17:53:06 -0700 | [diff] [blame] | 11893 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 11894 | if (tg3_flag(tp, ENABLE_RSS)) { |
Matt Carlson | 4a85f09 | 2011-04-20 07:57:37 +0000 | [diff] [blame] | 11895 | int i; |
| 11896 | |
| 11897 | /* Reroute all rx packets to the 1st queue */ |
| 11898 | for (i = MAC_RSS_INDIR_TBL_0; |
| 11899 | i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4) |
| 11900 | tw32(i, 0x0); |
| 11901 | } |
| 11902 | |
Matt Carlson | 6e01b20 | 2011-08-19 13:58:20 +0000 | [diff] [blame] | 11903 | /* HW errata - mac loopback fails in some cases on 5780. |
| 11904 | * Normal traffic and PHY loopback are not affected by |
| 11905 | * errata. Also, the MAC loopback test is deprecated for |
| 11906 | * all newer ASIC revisions. |
| 11907 | */ |
| 11908 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 && |
| 11909 | !tg3_flag(tp, CPMU_PRESENT)) { |
| 11910 | tg3_mac_loopback(tp, true); |
Matt Carlson | 9936bcf | 2007-10-10 18:03:07 -0700 | [diff] [blame] | 11911 | |
Matt Carlson | 28a4595 | 2011-08-19 13:58:22 +0000 | [diff] [blame] | 11912 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) |
| 11913 | data[0] |= TG3_STD_LOOPBACK_FAILED; |
Matt Carlson | 6e01b20 | 2011-08-19 13:58:20 +0000 | [diff] [blame] | 11914 | |
| 11915 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && |
Matt Carlson | 28a4595 | 2011-08-19 13:58:22 +0000 | [diff] [blame] | 11916 | tg3_run_loopback(tp, 9000 + ETH_HLEN, false)) |
| 11917 | data[0] |= TG3_JMB_LOOPBACK_FAILED; |
Matt Carlson | 6e01b20 | 2011-08-19 13:58:20 +0000 | [diff] [blame] | 11918 | |
| 11919 | tg3_mac_loopback(tp, false); |
| 11920 | } |
Matt Carlson | 4852a86 | 2011-04-13 11:05:07 +0000 | [diff] [blame] | 11921 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 11922 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 11923 | !tg3_flag(tp, USE_PHYLIB)) { |
Matt Carlson | 5e5a7f3 | 2011-08-19 13:58:21 +0000 | [diff] [blame] | 11924 | int i; |
| 11925 | |
Matt Carlson | 941ec90 | 2011-08-19 13:58:23 +0000 | [diff] [blame] | 11926 | tg3_phy_lpbk_set(tp, 0, false); |
Matt Carlson | 5e5a7f3 | 2011-08-19 13:58:21 +0000 | [diff] [blame] | 11927 | |
| 11928 | /* Wait for link */ |
| 11929 | for (i = 0; i < 100; i++) { |
| 11930 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) |
| 11931 | break; |
| 11932 | mdelay(1); |
| 11933 | } |
| 11934 | |
Matt Carlson | 28a4595 | 2011-08-19 13:58:22 +0000 | [diff] [blame] | 11935 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) |
| 11936 | data[1] |= TG3_STD_LOOPBACK_FAILED; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 11937 | if (tg3_flag(tp, TSO_CAPABLE) && |
Matt Carlson | 28a4595 | 2011-08-19 13:58:22 +0000 | [diff] [blame] | 11938 | tg3_run_loopback(tp, ETH_FRAME_LEN, true)) |
| 11939 | data[1] |= TG3_TSO_LOOPBACK_FAILED; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 11940 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && |
Matt Carlson | 28a4595 | 2011-08-19 13:58:22 +0000 | [diff] [blame] | 11941 | tg3_run_loopback(tp, 9000 + ETH_HLEN, false)) |
| 11942 | data[1] |= TG3_JMB_LOOPBACK_FAILED; |
Michael Chan | 9f40dea | 2005-09-05 17:53:06 -0700 | [diff] [blame] | 11943 | |
Matt Carlson | 941ec90 | 2011-08-19 13:58:23 +0000 | [diff] [blame] | 11944 | if (do_extlpbk) { |
| 11945 | tg3_phy_lpbk_set(tp, 0, true); |
| 11946 | |
| 11947 | /* All link indications report up, but the hardware |
| 11948 | * isn't really ready for about 20 msec. Double it |
| 11949 | * to be sure. |
| 11950 | */ |
| 11951 | mdelay(40); |
| 11952 | |
| 11953 | if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) |
| 11954 | data[2] |= TG3_STD_LOOPBACK_FAILED; |
| 11955 | if (tg3_flag(tp, TSO_CAPABLE) && |
| 11956 | tg3_run_loopback(tp, ETH_FRAME_LEN, true)) |
| 11957 | data[2] |= TG3_TSO_LOOPBACK_FAILED; |
| 11958 | if (tg3_flag(tp, JUMBO_RING_ENABLE) && |
| 11959 | tg3_run_loopback(tp, 9000 + ETH_HLEN, false)) |
| 11960 | data[2] |= TG3_JMB_LOOPBACK_FAILED; |
| 11961 | } |
| 11962 | |
Matt Carlson | 5e5a7f3 | 2011-08-19 13:58:21 +0000 | [diff] [blame] | 11963 | /* Re-enable gphy autopowerdown. */ |
| 11964 | if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) |
| 11965 | tg3_phy_toggle_apd(tp, true); |
| 11966 | } |
Matt Carlson | 6833c04 | 2008-11-21 17:18:59 -0800 | [diff] [blame] | 11967 | |
Matt Carlson | 941ec90 | 2011-08-19 13:58:23 +0000 | [diff] [blame] | 11968 | err = (data[0] | data[1] | data[2]) ? -EIO : 0; |
Matt Carlson | 28a4595 | 2011-08-19 13:58:22 +0000 | [diff] [blame] | 11969 | |
Matt Carlson | ab78904 | 2011-01-25 15:58:54 +0000 | [diff] [blame] | 11970 | done: |
| 11971 | tp->phy_flags |= eee_cap; |
| 11972 | |
Michael Chan | 9f40dea | 2005-09-05 17:53:06 -0700 | [diff] [blame] | 11973 | return err; |
| 11974 | } |
| 11975 | |
Michael Chan | 4cafd3f | 2005-05-29 14:56:34 -0700 | [diff] [blame] | 11976 | static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, |
| 11977 | u64 *data) |
| 11978 | { |
Michael Chan | 566f86a | 2005-05-29 14:56:58 -0700 | [diff] [blame] | 11979 | struct tg3 *tp = netdev_priv(dev); |
Matt Carlson | 941ec90 | 2011-08-19 13:58:23 +0000 | [diff] [blame] | 11980 | bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB; |
Michael Chan | 566f86a | 2005-05-29 14:56:58 -0700 | [diff] [blame] | 11981 | |
Matt Carlson | bed9829 | 2011-07-13 09:27:29 +0000 | [diff] [blame] | 11982 | if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && |
| 11983 | tg3_power_up(tp)) { |
| 11984 | etest->flags |= ETH_TEST_FL_FAILED; |
| 11985 | memset(data, 1, sizeof(u64) * TG3_NUM_TEST); |
| 11986 | return; |
| 11987 | } |
Michael Chan | bc1c756 | 2006-03-20 17:48:03 -0800 | [diff] [blame] | 11988 | |
Michael Chan | 566f86a | 2005-05-29 14:56:58 -0700 | [diff] [blame] | 11989 | memset(data, 0, sizeof(u64) * TG3_NUM_TEST); |
| 11990 | |
| 11991 | if (tg3_test_nvram(tp) != 0) { |
| 11992 | etest->flags |= ETH_TEST_FL_FAILED; |
| 11993 | data[0] = 1; |
| 11994 | } |
Matt Carlson | 941ec90 | 2011-08-19 13:58:23 +0000 | [diff] [blame] | 11995 | if (!doextlpbk && tg3_test_link(tp)) { |
Michael Chan | ca43007 | 2005-05-29 14:57:23 -0700 | [diff] [blame] | 11996 | etest->flags |= ETH_TEST_FL_FAILED; |
| 11997 | data[1] = 1; |
| 11998 | } |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 11999 | if (etest->flags & ETH_TEST_FL_OFFLINE) { |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 12000 | int err, err2 = 0, irq_sync = 0; |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 12001 | |
Michael Chan | bbe832c | 2005-06-24 20:20:04 -0700 | [diff] [blame] | 12002 | if (netif_running(dev)) { |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 12003 | tg3_phy_stop(tp); |
Michael Chan | bbe832c | 2005-06-24 20:20:04 -0700 | [diff] [blame] | 12004 | tg3_netif_stop(tp); |
| 12005 | irq_sync = 1; |
| 12006 | } |
| 12007 | |
| 12008 | tg3_full_lock(tp, irq_sync); |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 12009 | |
| 12010 | tg3_halt(tp, RESET_KIND_SUSPEND, 1); |
Michael Chan | ec41c7d | 2006-01-17 02:40:55 -0800 | [diff] [blame] | 12011 | err = tg3_nvram_lock(tp); |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 12012 | tg3_halt_cpu(tp, RX_CPU_BASE); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12013 | if (!tg3_flag(tp, 5705_PLUS)) |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 12014 | tg3_halt_cpu(tp, TX_CPU_BASE); |
Michael Chan | ec41c7d | 2006-01-17 02:40:55 -0800 | [diff] [blame] | 12015 | if (!err) |
| 12016 | tg3_nvram_unlock(tp); |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 12017 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 12018 | if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) |
Michael Chan | d9ab5ad | 2006-03-20 22:27:35 -0800 | [diff] [blame] | 12019 | tg3_phy_reset(tp); |
| 12020 | |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 12021 | if (tg3_test_registers(tp) != 0) { |
| 12022 | etest->flags |= ETH_TEST_FL_FAILED; |
| 12023 | data[2] = 1; |
| 12024 | } |
Matt Carlson | 28a4595 | 2011-08-19 13:58:22 +0000 | [diff] [blame] | 12025 | |
Michael Chan | 7942e1d | 2005-05-29 14:58:36 -0700 | [diff] [blame] | 12026 | if (tg3_test_memory(tp) != 0) { |
| 12027 | etest->flags |= ETH_TEST_FL_FAILED; |
| 12028 | data[3] = 1; |
| 12029 | } |
Matt Carlson | 28a4595 | 2011-08-19 13:58:22 +0000 | [diff] [blame] | 12030 | |
Matt Carlson | 941ec90 | 2011-08-19 13:58:23 +0000 | [diff] [blame] | 12031 | if (doextlpbk) |
| 12032 | etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; |
| 12033 | |
| 12034 | if (tg3_test_loopback(tp, &data[4], doextlpbk)) |
Michael Chan | c76949a | 2005-05-29 14:58:59 -0700 | [diff] [blame] | 12035 | etest->flags |= ETH_TEST_FL_FAILED; |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 12036 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 12037 | tg3_full_unlock(tp); |
| 12038 | |
Michael Chan | d4bc392 | 2005-05-29 14:59:20 -0700 | [diff] [blame] | 12039 | if (tg3_test_interrupt(tp) != 0) { |
| 12040 | etest->flags |= ETH_TEST_FL_FAILED; |
Matt Carlson | 941ec90 | 2011-08-19 13:58:23 +0000 | [diff] [blame] | 12041 | data[7] = 1; |
Michael Chan | d4bc392 | 2005-05-29 14:59:20 -0700 | [diff] [blame] | 12042 | } |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 12043 | |
| 12044 | tg3_full_lock(tp, 0); |
Michael Chan | d4bc392 | 2005-05-29 14:59:20 -0700 | [diff] [blame] | 12045 | |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 12046 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
| 12047 | if (netif_running(dev)) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12048 | tg3_flag_set(tp, INIT_COMPLETE); |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 12049 | err2 = tg3_restart_hw(tp, 1); |
| 12050 | if (!err2) |
Michael Chan | b9ec6c1 | 2006-07-25 16:37:27 -0700 | [diff] [blame] | 12051 | tg3_netif_start(tp); |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 12052 | } |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 12053 | |
| 12054 | tg3_full_unlock(tp); |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 12055 | |
| 12056 | if (irq_sync && !err2) |
| 12057 | tg3_phy_start(tp); |
Michael Chan | a71116d | 2005-05-29 14:58:11 -0700 | [diff] [blame] | 12058 | } |
Matt Carlson | 80096068 | 2010-08-02 11:26:06 +0000 | [diff] [blame] | 12059 | if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) |
Rafael J. Wysocki | c866b7e | 2010-12-25 12:56:23 +0000 | [diff] [blame] | 12060 | tg3_power_down(tp); |
Michael Chan | bc1c756 | 2006-03-20 17:48:03 -0800 | [diff] [blame] | 12061 | |
Michael Chan | 4cafd3f | 2005-05-29 14:56:34 -0700 | [diff] [blame] | 12062 | } |
| 12063 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12064 | static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
| 12065 | { |
| 12066 | struct mii_ioctl_data *data = if_mii(ifr); |
| 12067 | struct tg3 *tp = netdev_priv(dev); |
| 12068 | int err; |
| 12069 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12070 | if (tg3_flag(tp, USE_PHYLIB)) { |
Matt Carlson | 3f0e3ad | 2009-11-02 14:24:36 +0000 | [diff] [blame] | 12071 | struct phy_device *phydev; |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 12072 | if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 12073 | return -EAGAIN; |
Matt Carlson | 3f0e3ad | 2009-11-02 14:24:36 +0000 | [diff] [blame] | 12074 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
Richard Cochran | 28b0411 | 2010-07-17 08:48:55 +0000 | [diff] [blame] | 12075 | return phy_mii_ioctl(phydev, ifr, cmd); |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 12076 | } |
| 12077 | |
Matt Carlson | 33f401a | 2010-04-05 10:19:27 +0000 | [diff] [blame] | 12078 | switch (cmd) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12079 | case SIOCGMIIPHY: |
Matt Carlson | 882e979 | 2009-09-01 13:21:36 +0000 | [diff] [blame] | 12080 | data->phy_id = tp->phy_addr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12081 | |
| 12082 | /* fallthru */ |
| 12083 | case SIOCGMIIREG: { |
| 12084 | u32 mii_regval; |
| 12085 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 12086 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12087 | break; /* We have no PHY */ |
| 12088 | |
Matt Carlson | 34eea5a | 2011-04-20 07:57:38 +0000 | [diff] [blame] | 12089 | if (!netif_running(dev)) |
Michael Chan | bc1c756 | 2006-03-20 17:48:03 -0800 | [diff] [blame] | 12090 | return -EAGAIN; |
| 12091 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 12092 | spin_lock_bh(&tp->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12093 | err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 12094 | spin_unlock_bh(&tp->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12095 | |
| 12096 | data->val_out = mii_regval; |
| 12097 | |
| 12098 | return err; |
| 12099 | } |
| 12100 | |
| 12101 | case SIOCSMIIREG: |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 12102 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12103 | break; /* We have no PHY */ |
| 12104 | |
Matt Carlson | 34eea5a | 2011-04-20 07:57:38 +0000 | [diff] [blame] | 12105 | if (!netif_running(dev)) |
Michael Chan | bc1c756 | 2006-03-20 17:48:03 -0800 | [diff] [blame] | 12106 | return -EAGAIN; |
| 12107 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 12108 | spin_lock_bh(&tp->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12109 | err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 12110 | spin_unlock_bh(&tp->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12111 | |
| 12112 | return err; |
| 12113 | |
| 12114 | default: |
| 12115 | /* do nothing */ |
| 12116 | break; |
| 12117 | } |
| 12118 | return -EOPNOTSUPP; |
| 12119 | } |
| 12120 | |
David S. Miller | 15f9850 | 2005-05-18 22:49:26 -0700 | [diff] [blame] | 12121 | static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
| 12122 | { |
| 12123 | struct tg3 *tp = netdev_priv(dev); |
| 12124 | |
| 12125 | memcpy(ec, &tp->coal, sizeof(*ec)); |
| 12126 | return 0; |
| 12127 | } |
| 12128 | |
Michael Chan | d244c89 | 2005-07-05 14:42:33 -0700 | [diff] [blame] | 12129 | static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
| 12130 | { |
| 12131 | struct tg3 *tp = netdev_priv(dev); |
| 12132 | u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0; |
| 12133 | u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0; |
| 12134 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12135 | if (!tg3_flag(tp, 5705_PLUS)) { |
Michael Chan | d244c89 | 2005-07-05 14:42:33 -0700 | [diff] [blame] | 12136 | max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT; |
| 12137 | max_txcoal_tick_int = MAX_TXCOAL_TICK_INT; |
| 12138 | max_stat_coal_ticks = MAX_STAT_COAL_TICKS; |
| 12139 | min_stat_coal_ticks = MIN_STAT_COAL_TICKS; |
| 12140 | } |
| 12141 | |
| 12142 | if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || |
| 12143 | (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || |
| 12144 | (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || |
| 12145 | (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || |
| 12146 | (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || |
| 12147 | (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || |
| 12148 | (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || |
| 12149 | (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || |
| 12150 | (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || |
| 12151 | (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) |
| 12152 | return -EINVAL; |
| 12153 | |
| 12154 | /* No rx interrupts will be generated if both are zero */ |
| 12155 | if ((ec->rx_coalesce_usecs == 0) && |
| 12156 | (ec->rx_max_coalesced_frames == 0)) |
| 12157 | return -EINVAL; |
| 12158 | |
| 12159 | /* No tx interrupts will be generated if both are zero */ |
| 12160 | if ((ec->tx_coalesce_usecs == 0) && |
| 12161 | (ec->tx_max_coalesced_frames == 0)) |
| 12162 | return -EINVAL; |
| 12163 | |
| 12164 | /* Only copy relevant parameters, ignore all others. */ |
| 12165 | tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; |
| 12166 | tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; |
| 12167 | tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; |
| 12168 | tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; |
| 12169 | tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; |
| 12170 | tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; |
| 12171 | tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; |
| 12172 | tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; |
| 12173 | tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; |
| 12174 | |
| 12175 | if (netif_running(dev)) { |
| 12176 | tg3_full_lock(tp, 0); |
| 12177 | __tg3_set_coalesce(tp, &tp->coal); |
| 12178 | tg3_full_unlock(tp); |
| 12179 | } |
| 12180 | return 0; |
| 12181 | } |
| 12182 | |
Jeff Garzik | 7282d49 | 2006-09-13 14:30:00 -0400 | [diff] [blame] | 12183 | static const struct ethtool_ops tg3_ethtool_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12184 | .get_settings = tg3_get_settings, |
| 12185 | .set_settings = tg3_set_settings, |
| 12186 | .get_drvinfo = tg3_get_drvinfo, |
| 12187 | .get_regs_len = tg3_get_regs_len, |
| 12188 | .get_regs = tg3_get_regs, |
| 12189 | .get_wol = tg3_get_wol, |
| 12190 | .set_wol = tg3_set_wol, |
| 12191 | .get_msglevel = tg3_get_msglevel, |
| 12192 | .set_msglevel = tg3_set_msglevel, |
| 12193 | .nway_reset = tg3_nway_reset, |
| 12194 | .get_link = ethtool_op_get_link, |
| 12195 | .get_eeprom_len = tg3_get_eeprom_len, |
| 12196 | .get_eeprom = tg3_get_eeprom, |
| 12197 | .set_eeprom = tg3_set_eeprom, |
| 12198 | .get_ringparam = tg3_get_ringparam, |
| 12199 | .set_ringparam = tg3_set_ringparam, |
| 12200 | .get_pauseparam = tg3_get_pauseparam, |
| 12201 | .set_pauseparam = tg3_set_pauseparam, |
Michael Chan | 4cafd3f | 2005-05-29 14:56:34 -0700 | [diff] [blame] | 12202 | .self_test = tg3_self_test, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12203 | .get_strings = tg3_get_strings, |
stephen hemminger | 81b8709 | 2011-04-04 08:43:50 +0000 | [diff] [blame] | 12204 | .set_phys_id = tg3_set_phys_id, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12205 | .get_ethtool_stats = tg3_get_ethtool_stats, |
David S. Miller | 15f9850 | 2005-05-18 22:49:26 -0700 | [diff] [blame] | 12206 | .get_coalesce = tg3_get_coalesce, |
Michael Chan | d244c89 | 2005-07-05 14:42:33 -0700 | [diff] [blame] | 12207 | .set_coalesce = tg3_set_coalesce, |
Jeff Garzik | b9f2c04 | 2007-10-03 18:07:32 -0700 | [diff] [blame] | 12208 | .get_sset_count = tg3_get_sset_count, |
Matt Carlson | 9041547 | 2011-12-16 13:33:23 +0000 | [diff] [blame] | 12209 | .get_rxnfc = tg3_get_rxnfc, |
| 12210 | .get_rxfh_indir_size = tg3_get_rxfh_indir_size, |
| 12211 | .get_rxfh_indir = tg3_get_rxfh_indir, |
| 12212 | .set_rxfh_indir = tg3_set_rxfh_indir, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12213 | }; |
| 12214 | |
Matt Carlson | ccd5ba9 | 2012-02-13 10:20:08 +0000 | [diff] [blame] | 12215 | static void tg3_set_rx_mode(struct net_device *dev) |
| 12216 | { |
| 12217 | struct tg3 *tp = netdev_priv(dev); |
| 12218 | |
| 12219 | if (!netif_running(dev)) |
| 12220 | return; |
| 12221 | |
| 12222 | tg3_full_lock(tp, 0); |
| 12223 | __tg3_set_rx_mode(dev); |
| 12224 | tg3_full_unlock(tp); |
| 12225 | } |
| 12226 | |
Matt Carlson | faf1627 | 2012-02-13 10:20:07 +0000 | [diff] [blame] | 12227 | static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, |
| 12228 | int new_mtu) |
| 12229 | { |
| 12230 | dev->mtu = new_mtu; |
| 12231 | |
| 12232 | if (new_mtu > ETH_DATA_LEN) { |
| 12233 | if (tg3_flag(tp, 5780_CLASS)) { |
| 12234 | netdev_update_features(dev); |
| 12235 | tg3_flag_clear(tp, TSO_CAPABLE); |
| 12236 | } else { |
| 12237 | tg3_flag_set(tp, JUMBO_RING_ENABLE); |
| 12238 | } |
| 12239 | } else { |
| 12240 | if (tg3_flag(tp, 5780_CLASS)) { |
| 12241 | tg3_flag_set(tp, TSO_CAPABLE); |
| 12242 | netdev_update_features(dev); |
| 12243 | } |
| 12244 | tg3_flag_clear(tp, JUMBO_RING_ENABLE); |
| 12245 | } |
| 12246 | } |
| 12247 | |
| 12248 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) |
| 12249 | { |
| 12250 | struct tg3 *tp = netdev_priv(dev); |
| 12251 | int err; |
| 12252 | |
| 12253 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) |
| 12254 | return -EINVAL; |
| 12255 | |
| 12256 | if (!netif_running(dev)) { |
| 12257 | /* We'll just catch it later when the |
| 12258 | * device is up'd. |
| 12259 | */ |
| 12260 | tg3_set_mtu(dev, tp, new_mtu); |
| 12261 | return 0; |
| 12262 | } |
| 12263 | |
| 12264 | tg3_phy_stop(tp); |
| 12265 | |
| 12266 | tg3_netif_stop(tp); |
| 12267 | |
| 12268 | tg3_full_lock(tp, 1); |
| 12269 | |
| 12270 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
| 12271 | |
| 12272 | tg3_set_mtu(dev, tp, new_mtu); |
| 12273 | |
| 12274 | err = tg3_restart_hw(tp, 0); |
| 12275 | |
| 12276 | if (!err) |
| 12277 | tg3_netif_start(tp); |
| 12278 | |
| 12279 | tg3_full_unlock(tp); |
| 12280 | |
| 12281 | if (!err) |
| 12282 | tg3_phy_start(tp); |
| 12283 | |
| 12284 | return err; |
| 12285 | } |
| 12286 | |
| 12287 | static const struct net_device_ops tg3_netdev_ops = { |
| 12288 | .ndo_open = tg3_open, |
| 12289 | .ndo_stop = tg3_close, |
| 12290 | .ndo_start_xmit = tg3_start_xmit, |
| 12291 | .ndo_get_stats64 = tg3_get_stats64, |
| 12292 | .ndo_validate_addr = eth_validate_addr, |
| 12293 | .ndo_set_rx_mode = tg3_set_rx_mode, |
| 12294 | .ndo_set_mac_address = tg3_set_mac_addr, |
| 12295 | .ndo_do_ioctl = tg3_ioctl, |
| 12296 | .ndo_tx_timeout = tg3_tx_timeout, |
| 12297 | .ndo_change_mtu = tg3_change_mtu, |
| 12298 | .ndo_fix_features = tg3_fix_features, |
| 12299 | .ndo_set_features = tg3_set_features, |
| 12300 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 12301 | .ndo_poll_controller = tg3_poll_controller, |
| 12302 | #endif |
| 12303 | }; |
| 12304 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12305 | static void __devinit tg3_get_eeprom_size(struct tg3 *tp) |
| 12306 | { |
Michael Chan | 1b27777 | 2006-03-20 22:27:48 -0800 | [diff] [blame] | 12307 | u32 cursize, val, magic; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12308 | |
| 12309 | tp->nvram_size = EEPROM_CHIP_SIZE; |
| 12310 | |
Matt Carlson | e4f3411 | 2009-02-25 14:25:00 +0000 | [diff] [blame] | 12311 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12312 | return; |
| 12313 | |
Michael Chan | b16250e | 2006-09-27 16:10:14 -0700 | [diff] [blame] | 12314 | if ((magic != TG3_EEPROM_MAGIC) && |
| 12315 | ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) && |
| 12316 | ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12317 | return; |
| 12318 | |
| 12319 | /* |
| 12320 | * Size the chip by reading offsets at increasing powers of two. |
| 12321 | * When we encounter our validation signature, we know the addressing |
| 12322 | * has wrapped around, and thus have our chip size. |
| 12323 | */ |
Michael Chan | 1b27777 | 2006-03-20 22:27:48 -0800 | [diff] [blame] | 12324 | cursize = 0x10; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12325 | |
| 12326 | while (cursize < tp->nvram_size) { |
Matt Carlson | e4f3411 | 2009-02-25 14:25:00 +0000 | [diff] [blame] | 12327 | if (tg3_nvram_read(tp, cursize, &val) != 0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12328 | return; |
| 12329 | |
Michael Chan | 1820180 | 2006-03-20 22:29:15 -0800 | [diff] [blame] | 12330 | if (val == magic) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12331 | break; |
| 12332 | |
| 12333 | cursize <<= 1; |
| 12334 | } |
| 12335 | |
| 12336 | tp->nvram_size = cursize; |
| 12337 | } |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 12338 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12339 | static void __devinit tg3_get_nvram_size(struct tg3 *tp) |
| 12340 | { |
| 12341 | u32 val; |
| 12342 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12343 | if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0) |
Michael Chan | 1b27777 | 2006-03-20 22:27:48 -0800 | [diff] [blame] | 12344 | return; |
| 12345 | |
| 12346 | /* Selfboot format */ |
Michael Chan | 1820180 | 2006-03-20 22:29:15 -0800 | [diff] [blame] | 12347 | if (val != TG3_EEPROM_MAGIC) { |
Michael Chan | 1b27777 | 2006-03-20 22:27:48 -0800 | [diff] [blame] | 12348 | tg3_get_eeprom_size(tp); |
| 12349 | return; |
| 12350 | } |
| 12351 | |
Matt Carlson | 6d348f2 | 2009-02-25 14:25:52 +0000 | [diff] [blame] | 12352 | if (tg3_nvram_read(tp, 0xf0, &val) == 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12353 | if (val != 0) { |
Matt Carlson | 6d348f2 | 2009-02-25 14:25:52 +0000 | [diff] [blame] | 12354 | /* This is confusing. We want to operate on the |
| 12355 | * 16-bit value at offset 0xf2. The tg3_nvram_read() |
| 12356 | * call will read from NVRAM and byteswap the data |
| 12357 | * according to the byteswapping settings for all |
| 12358 | * other register accesses. This ensures the data we |
| 12359 | * want will always reside in the lower 16-bits. |
| 12360 | * However, the data in NVRAM is in LE format, which |
| 12361 | * means the data from the NVRAM read will always be |
| 12362 | * opposite the endianness of the CPU. The 16-bit |
| 12363 | * byteswap then brings the data to CPU endianness. |
| 12364 | */ |
| 12365 | tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12366 | return; |
| 12367 | } |
| 12368 | } |
Matt Carlson | fd1122a | 2008-05-02 16:48:36 -0700 | [diff] [blame] | 12369 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12370 | } |
| 12371 | |
| 12372 | static void __devinit tg3_get_nvram_info(struct tg3 *tp) |
| 12373 | { |
| 12374 | u32 nvcfg1; |
| 12375 | |
| 12376 | nvcfg1 = tr32(NVRAM_CFG1); |
| 12377 | if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12378 | tg3_flag_set(tp, FLASH); |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12379 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12380 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
| 12381 | tw32(NVRAM_CFG1, nvcfg1); |
| 12382 | } |
| 12383 | |
Matt Carlson | 6ff6f81 | 2011-05-19 12:12:54 +0000 | [diff] [blame] | 12384 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12385 | tg3_flag(tp, 5780_CLASS)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12386 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12387 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: |
| 12388 | tp->nvram_jedecnum = JEDEC_ATMEL; |
| 12389 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12390 | tg3_flag_set(tp, NVRAM_BUFFERED); |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12391 | break; |
| 12392 | case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED: |
| 12393 | tp->nvram_jedecnum = JEDEC_ATMEL; |
| 12394 | tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; |
| 12395 | break; |
| 12396 | case FLASH_VENDOR_ATMEL_EEPROM: |
| 12397 | tp->nvram_jedecnum = JEDEC_ATMEL; |
| 12398 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12399 | tg3_flag_set(tp, NVRAM_BUFFERED); |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12400 | break; |
| 12401 | case FLASH_VENDOR_ST: |
| 12402 | tp->nvram_jedecnum = JEDEC_ST; |
| 12403 | tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12404 | tg3_flag_set(tp, NVRAM_BUFFERED); |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12405 | break; |
| 12406 | case FLASH_VENDOR_SAIFUN: |
| 12407 | tp->nvram_jedecnum = JEDEC_SAIFUN; |
| 12408 | tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; |
| 12409 | break; |
| 12410 | case FLASH_VENDOR_SST_SMALL: |
| 12411 | case FLASH_VENDOR_SST_LARGE: |
| 12412 | tp->nvram_jedecnum = JEDEC_SST; |
| 12413 | tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; |
| 12414 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12415 | } |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12416 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12417 | tp->nvram_jedecnum = JEDEC_ATMEL; |
| 12418 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12419 | tg3_flag_set(tp, NVRAM_BUFFERED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12420 | } |
| 12421 | } |
| 12422 | |
Matt Carlson | a1b950d | 2009-09-01 13:20:17 +0000 | [diff] [blame] | 12423 | static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) |
| 12424 | { |
| 12425 | switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { |
| 12426 | case FLASH_5752PAGE_SIZE_256: |
| 12427 | tp->nvram_pagesize = 256; |
| 12428 | break; |
| 12429 | case FLASH_5752PAGE_SIZE_512: |
| 12430 | tp->nvram_pagesize = 512; |
| 12431 | break; |
| 12432 | case FLASH_5752PAGE_SIZE_1K: |
| 12433 | tp->nvram_pagesize = 1024; |
| 12434 | break; |
| 12435 | case FLASH_5752PAGE_SIZE_2K: |
| 12436 | tp->nvram_pagesize = 2048; |
| 12437 | break; |
| 12438 | case FLASH_5752PAGE_SIZE_4K: |
| 12439 | tp->nvram_pagesize = 4096; |
| 12440 | break; |
| 12441 | case FLASH_5752PAGE_SIZE_264: |
| 12442 | tp->nvram_pagesize = 264; |
| 12443 | break; |
| 12444 | case FLASH_5752PAGE_SIZE_528: |
| 12445 | tp->nvram_pagesize = 528; |
| 12446 | break; |
| 12447 | } |
| 12448 | } |
| 12449 | |
Michael Chan | 361b4ac | 2005-04-21 17:11:21 -0700 | [diff] [blame] | 12450 | static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp) |
| 12451 | { |
| 12452 | u32 nvcfg1; |
| 12453 | |
| 12454 | nvcfg1 = tr32(NVRAM_CFG1); |
| 12455 | |
Michael Chan | e6af301 | 2005-04-21 17:12:05 -0700 | [diff] [blame] | 12456 | /* NVRAM protection for TPM */ |
| 12457 | if (nvcfg1 & (1 << 27)) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12458 | tg3_flag_set(tp, PROTECTED_NVRAM); |
Michael Chan | e6af301 | 2005-04-21 17:12:05 -0700 | [diff] [blame] | 12459 | |
Michael Chan | 361b4ac | 2005-04-21 17:11:21 -0700 | [diff] [blame] | 12460 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12461 | case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: |
| 12462 | case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: |
| 12463 | tp->nvram_jedecnum = JEDEC_ATMEL; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12464 | tg3_flag_set(tp, NVRAM_BUFFERED); |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12465 | break; |
| 12466 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: |
| 12467 | tp->nvram_jedecnum = JEDEC_ATMEL; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12468 | tg3_flag_set(tp, NVRAM_BUFFERED); |
| 12469 | tg3_flag_set(tp, FLASH); |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12470 | break; |
| 12471 | case FLASH_5752VENDOR_ST_M45PE10: |
| 12472 | case FLASH_5752VENDOR_ST_M45PE20: |
| 12473 | case FLASH_5752VENDOR_ST_M45PE40: |
| 12474 | tp->nvram_jedecnum = JEDEC_ST; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12475 | tg3_flag_set(tp, NVRAM_BUFFERED); |
| 12476 | tg3_flag_set(tp, FLASH); |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12477 | break; |
Michael Chan | 361b4ac | 2005-04-21 17:11:21 -0700 | [diff] [blame] | 12478 | } |
| 12479 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12480 | if (tg3_flag(tp, FLASH)) { |
Matt Carlson | a1b950d | 2009-09-01 13:20:17 +0000 | [diff] [blame] | 12481 | tg3_nvram_get_pagesize(tp, nvcfg1); |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12482 | } else { |
Michael Chan | 361b4ac | 2005-04-21 17:11:21 -0700 | [diff] [blame] | 12483 | /* For eeprom, set pagesize to maximum eeprom size */ |
| 12484 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
| 12485 | |
| 12486 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
| 12487 | tw32(NVRAM_CFG1, nvcfg1); |
| 12488 | } |
| 12489 | } |
| 12490 | |
Michael Chan | d3c7b88 | 2006-03-23 01:28:25 -0800 | [diff] [blame] | 12491 | static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) |
| 12492 | { |
Matt Carlson | 989a9d2 | 2007-05-05 11:51:05 -0700 | [diff] [blame] | 12493 | u32 nvcfg1, protect = 0; |
Michael Chan | d3c7b88 | 2006-03-23 01:28:25 -0800 | [diff] [blame] | 12494 | |
| 12495 | nvcfg1 = tr32(NVRAM_CFG1); |
| 12496 | |
| 12497 | /* NVRAM protection for TPM */ |
Matt Carlson | 989a9d2 | 2007-05-05 11:51:05 -0700 | [diff] [blame] | 12498 | if (nvcfg1 & (1 << 27)) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12499 | tg3_flag_set(tp, PROTECTED_NVRAM); |
Matt Carlson | 989a9d2 | 2007-05-05 11:51:05 -0700 | [diff] [blame] | 12500 | protect = 1; |
| 12501 | } |
Michael Chan | d3c7b88 | 2006-03-23 01:28:25 -0800 | [diff] [blame] | 12502 | |
Matt Carlson | 989a9d2 | 2007-05-05 11:51:05 -0700 | [diff] [blame] | 12503 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; |
| 12504 | switch (nvcfg1) { |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12505 | case FLASH_5755VENDOR_ATMEL_FLASH_1: |
| 12506 | case FLASH_5755VENDOR_ATMEL_FLASH_2: |
| 12507 | case FLASH_5755VENDOR_ATMEL_FLASH_3: |
| 12508 | case FLASH_5755VENDOR_ATMEL_FLASH_5: |
| 12509 | tp->nvram_jedecnum = JEDEC_ATMEL; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12510 | tg3_flag_set(tp, NVRAM_BUFFERED); |
| 12511 | tg3_flag_set(tp, FLASH); |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12512 | tp->nvram_pagesize = 264; |
| 12513 | if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || |
| 12514 | nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5) |
| 12515 | tp->nvram_size = (protect ? 0x3e200 : |
| 12516 | TG3_NVRAM_SIZE_512KB); |
| 12517 | else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) |
| 12518 | tp->nvram_size = (protect ? 0x1f200 : |
| 12519 | TG3_NVRAM_SIZE_256KB); |
| 12520 | else |
| 12521 | tp->nvram_size = (protect ? 0x1f200 : |
| 12522 | TG3_NVRAM_SIZE_128KB); |
| 12523 | break; |
| 12524 | case FLASH_5752VENDOR_ST_M45PE10: |
| 12525 | case FLASH_5752VENDOR_ST_M45PE20: |
| 12526 | case FLASH_5752VENDOR_ST_M45PE40: |
| 12527 | tp->nvram_jedecnum = JEDEC_ST; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12528 | tg3_flag_set(tp, NVRAM_BUFFERED); |
| 12529 | tg3_flag_set(tp, FLASH); |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12530 | tp->nvram_pagesize = 256; |
| 12531 | if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) |
| 12532 | tp->nvram_size = (protect ? |
| 12533 | TG3_NVRAM_SIZE_64KB : |
| 12534 | TG3_NVRAM_SIZE_128KB); |
| 12535 | else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) |
| 12536 | tp->nvram_size = (protect ? |
| 12537 | TG3_NVRAM_SIZE_64KB : |
| 12538 | TG3_NVRAM_SIZE_256KB); |
| 12539 | else |
| 12540 | tp->nvram_size = (protect ? |
| 12541 | TG3_NVRAM_SIZE_128KB : |
| 12542 | TG3_NVRAM_SIZE_512KB); |
| 12543 | break; |
Michael Chan | d3c7b88 | 2006-03-23 01:28:25 -0800 | [diff] [blame] | 12544 | } |
| 12545 | } |
| 12546 | |
Michael Chan | 1b27777 | 2006-03-20 22:27:48 -0800 | [diff] [blame] | 12547 | static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp) |
| 12548 | { |
| 12549 | u32 nvcfg1; |
| 12550 | |
| 12551 | nvcfg1 = tr32(NVRAM_CFG1); |
| 12552 | |
| 12553 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12554 | case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ: |
| 12555 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: |
| 12556 | case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ: |
| 12557 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: |
| 12558 | tp->nvram_jedecnum = JEDEC_ATMEL; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12559 | tg3_flag_set(tp, NVRAM_BUFFERED); |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12560 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
Michael Chan | 1b27777 | 2006-03-20 22:27:48 -0800 | [diff] [blame] | 12561 | |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12562 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
| 12563 | tw32(NVRAM_CFG1, nvcfg1); |
| 12564 | break; |
| 12565 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: |
| 12566 | case FLASH_5755VENDOR_ATMEL_FLASH_1: |
| 12567 | case FLASH_5755VENDOR_ATMEL_FLASH_2: |
| 12568 | case FLASH_5755VENDOR_ATMEL_FLASH_3: |
| 12569 | tp->nvram_jedecnum = JEDEC_ATMEL; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12570 | tg3_flag_set(tp, NVRAM_BUFFERED); |
| 12571 | tg3_flag_set(tp, FLASH); |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12572 | tp->nvram_pagesize = 264; |
| 12573 | break; |
| 12574 | case FLASH_5752VENDOR_ST_M45PE10: |
| 12575 | case FLASH_5752VENDOR_ST_M45PE20: |
| 12576 | case FLASH_5752VENDOR_ST_M45PE40: |
| 12577 | tp->nvram_jedecnum = JEDEC_ST; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12578 | tg3_flag_set(tp, NVRAM_BUFFERED); |
| 12579 | tg3_flag_set(tp, FLASH); |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12580 | tp->nvram_pagesize = 256; |
| 12581 | break; |
Michael Chan | 1b27777 | 2006-03-20 22:27:48 -0800 | [diff] [blame] | 12582 | } |
| 12583 | } |
| 12584 | |
Matt Carlson | 6b91fa0 | 2007-10-10 18:01:09 -0700 | [diff] [blame] | 12585 | static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp) |
| 12586 | { |
| 12587 | u32 nvcfg1, protect = 0; |
| 12588 | |
| 12589 | nvcfg1 = tr32(NVRAM_CFG1); |
| 12590 | |
| 12591 | /* NVRAM protection for TPM */ |
| 12592 | if (nvcfg1 & (1 << 27)) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12593 | tg3_flag_set(tp, PROTECTED_NVRAM); |
Matt Carlson | 6b91fa0 | 2007-10-10 18:01:09 -0700 | [diff] [blame] | 12594 | protect = 1; |
| 12595 | } |
| 12596 | |
| 12597 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; |
| 12598 | switch (nvcfg1) { |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12599 | case FLASH_5761VENDOR_ATMEL_ADB021D: |
| 12600 | case FLASH_5761VENDOR_ATMEL_ADB041D: |
| 12601 | case FLASH_5761VENDOR_ATMEL_ADB081D: |
| 12602 | case FLASH_5761VENDOR_ATMEL_ADB161D: |
| 12603 | case FLASH_5761VENDOR_ATMEL_MDB021D: |
| 12604 | case FLASH_5761VENDOR_ATMEL_MDB041D: |
| 12605 | case FLASH_5761VENDOR_ATMEL_MDB081D: |
| 12606 | case FLASH_5761VENDOR_ATMEL_MDB161D: |
| 12607 | tp->nvram_jedecnum = JEDEC_ATMEL; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12608 | tg3_flag_set(tp, NVRAM_BUFFERED); |
| 12609 | tg3_flag_set(tp, FLASH); |
| 12610 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12611 | tp->nvram_pagesize = 256; |
| 12612 | break; |
| 12613 | case FLASH_5761VENDOR_ST_A_M45PE20: |
| 12614 | case FLASH_5761VENDOR_ST_A_M45PE40: |
| 12615 | case FLASH_5761VENDOR_ST_A_M45PE80: |
| 12616 | case FLASH_5761VENDOR_ST_A_M45PE16: |
| 12617 | case FLASH_5761VENDOR_ST_M_M45PE20: |
| 12618 | case FLASH_5761VENDOR_ST_M_M45PE40: |
| 12619 | case FLASH_5761VENDOR_ST_M_M45PE80: |
| 12620 | case FLASH_5761VENDOR_ST_M_M45PE16: |
| 12621 | tp->nvram_jedecnum = JEDEC_ST; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12622 | tg3_flag_set(tp, NVRAM_BUFFERED); |
| 12623 | tg3_flag_set(tp, FLASH); |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12624 | tp->nvram_pagesize = 256; |
| 12625 | break; |
Matt Carlson | 6b91fa0 | 2007-10-10 18:01:09 -0700 | [diff] [blame] | 12626 | } |
| 12627 | |
| 12628 | if (protect) { |
| 12629 | tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); |
| 12630 | } else { |
| 12631 | switch (nvcfg1) { |
Matt Carlson | 8590a60 | 2009-08-28 12:29:16 +0000 | [diff] [blame] | 12632 | case FLASH_5761VENDOR_ATMEL_ADB161D: |
| 12633 | case FLASH_5761VENDOR_ATMEL_MDB161D: |
| 12634 | case FLASH_5761VENDOR_ST_A_M45PE16: |
| 12635 | case FLASH_5761VENDOR_ST_M_M45PE16: |
| 12636 | tp->nvram_size = TG3_NVRAM_SIZE_2MB; |
| 12637 | break; |
| 12638 | case FLASH_5761VENDOR_ATMEL_ADB081D: |
| 12639 | case FLASH_5761VENDOR_ATMEL_MDB081D: |
| 12640 | case FLASH_5761VENDOR_ST_A_M45PE80: |
| 12641 | case FLASH_5761VENDOR_ST_M_M45PE80: |
| 12642 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; |
| 12643 | break; |
| 12644 | case FLASH_5761VENDOR_ATMEL_ADB041D: |
| 12645 | case FLASH_5761VENDOR_ATMEL_MDB041D: |
| 12646 | case FLASH_5761VENDOR_ST_A_M45PE40: |
| 12647 | case FLASH_5761VENDOR_ST_M_M45PE40: |
| 12648 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; |
| 12649 | break; |
| 12650 | case FLASH_5761VENDOR_ATMEL_ADB021D: |
| 12651 | case FLASH_5761VENDOR_ATMEL_MDB021D: |
| 12652 | case FLASH_5761VENDOR_ST_A_M45PE20: |
| 12653 | case FLASH_5761VENDOR_ST_M_M45PE20: |
| 12654 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; |
| 12655 | break; |
Matt Carlson | 6b91fa0 | 2007-10-10 18:01:09 -0700 | [diff] [blame] | 12656 | } |
| 12657 | } |
| 12658 | } |
| 12659 | |
Michael Chan | b5d3772 | 2006-09-27 16:06:21 -0700 | [diff] [blame] | 12660 | static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) |
| 12661 | { |
| 12662 | tp->nvram_jedecnum = JEDEC_ATMEL; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12663 | tg3_flag_set(tp, NVRAM_BUFFERED); |
Michael Chan | b5d3772 | 2006-09-27 16:06:21 -0700 | [diff] [blame] | 12664 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
| 12665 | } |
| 12666 | |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 12667 | static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp) |
| 12668 | { |
| 12669 | u32 nvcfg1; |
| 12670 | |
| 12671 | nvcfg1 = tr32(NVRAM_CFG1); |
| 12672 | |
| 12673 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
| 12674 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: |
| 12675 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: |
| 12676 | tp->nvram_jedecnum = JEDEC_ATMEL; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12677 | tg3_flag_set(tp, NVRAM_BUFFERED); |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 12678 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
| 12679 | |
| 12680 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
| 12681 | tw32(NVRAM_CFG1, nvcfg1); |
| 12682 | return; |
| 12683 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: |
| 12684 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: |
| 12685 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: |
| 12686 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: |
| 12687 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: |
| 12688 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: |
| 12689 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: |
| 12690 | tp->nvram_jedecnum = JEDEC_ATMEL; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12691 | tg3_flag_set(tp, NVRAM_BUFFERED); |
| 12692 | tg3_flag_set(tp, FLASH); |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 12693 | |
| 12694 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
| 12695 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: |
| 12696 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: |
| 12697 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: |
| 12698 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; |
| 12699 | break; |
| 12700 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: |
| 12701 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: |
| 12702 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; |
| 12703 | break; |
| 12704 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: |
| 12705 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: |
| 12706 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; |
| 12707 | break; |
| 12708 | } |
| 12709 | break; |
| 12710 | case FLASH_5752VENDOR_ST_M45PE10: |
| 12711 | case FLASH_5752VENDOR_ST_M45PE20: |
| 12712 | case FLASH_5752VENDOR_ST_M45PE40: |
| 12713 | tp->nvram_jedecnum = JEDEC_ST; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12714 | tg3_flag_set(tp, NVRAM_BUFFERED); |
| 12715 | tg3_flag_set(tp, FLASH); |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 12716 | |
| 12717 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
| 12718 | case FLASH_5752VENDOR_ST_M45PE10: |
| 12719 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; |
| 12720 | break; |
| 12721 | case FLASH_5752VENDOR_ST_M45PE20: |
| 12722 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; |
| 12723 | break; |
| 12724 | case FLASH_5752VENDOR_ST_M45PE40: |
| 12725 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; |
| 12726 | break; |
| 12727 | } |
| 12728 | break; |
| 12729 | default: |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12730 | tg3_flag_set(tp, NO_NVRAM); |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 12731 | return; |
| 12732 | } |
| 12733 | |
Matt Carlson | a1b950d | 2009-09-01 13:20:17 +0000 | [diff] [blame] | 12734 | tg3_nvram_get_pagesize(tp, nvcfg1); |
| 12735 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12736 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
Matt Carlson | a1b950d | 2009-09-01 13:20:17 +0000 | [diff] [blame] | 12737 | } |
| 12738 | |
| 12739 | |
| 12740 | static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp) |
| 12741 | { |
| 12742 | u32 nvcfg1; |
| 12743 | |
| 12744 | nvcfg1 = tr32(NVRAM_CFG1); |
| 12745 | |
| 12746 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
| 12747 | case FLASH_5717VENDOR_ATMEL_EEPROM: |
| 12748 | case FLASH_5717VENDOR_MICRO_EEPROM: |
| 12749 | tp->nvram_jedecnum = JEDEC_ATMEL; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12750 | tg3_flag_set(tp, NVRAM_BUFFERED); |
Matt Carlson | a1b950d | 2009-09-01 13:20:17 +0000 | [diff] [blame] | 12751 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
| 12752 | |
| 12753 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
| 12754 | tw32(NVRAM_CFG1, nvcfg1); |
| 12755 | return; |
| 12756 | case FLASH_5717VENDOR_ATMEL_MDB011D: |
| 12757 | case FLASH_5717VENDOR_ATMEL_ADB011B: |
| 12758 | case FLASH_5717VENDOR_ATMEL_ADB011D: |
| 12759 | case FLASH_5717VENDOR_ATMEL_MDB021D: |
| 12760 | case FLASH_5717VENDOR_ATMEL_ADB021B: |
| 12761 | case FLASH_5717VENDOR_ATMEL_ADB021D: |
| 12762 | case FLASH_5717VENDOR_ATMEL_45USPT: |
| 12763 | tp->nvram_jedecnum = JEDEC_ATMEL; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12764 | tg3_flag_set(tp, NVRAM_BUFFERED); |
| 12765 | tg3_flag_set(tp, FLASH); |
Matt Carlson | a1b950d | 2009-09-01 13:20:17 +0000 | [diff] [blame] | 12766 | |
| 12767 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
| 12768 | case FLASH_5717VENDOR_ATMEL_MDB021D: |
Matt Carlson | 66ee33b | 2011-04-05 14:22:51 +0000 | [diff] [blame] | 12769 | /* Detect size with tg3_nvram_get_size() */ |
| 12770 | break; |
Matt Carlson | a1b950d | 2009-09-01 13:20:17 +0000 | [diff] [blame] | 12771 | case FLASH_5717VENDOR_ATMEL_ADB021B: |
| 12772 | case FLASH_5717VENDOR_ATMEL_ADB021D: |
| 12773 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; |
| 12774 | break; |
| 12775 | default: |
| 12776 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; |
| 12777 | break; |
| 12778 | } |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 12779 | break; |
Matt Carlson | a1b950d | 2009-09-01 13:20:17 +0000 | [diff] [blame] | 12780 | case FLASH_5717VENDOR_ST_M_M25PE10: |
| 12781 | case FLASH_5717VENDOR_ST_A_M25PE10: |
| 12782 | case FLASH_5717VENDOR_ST_M_M45PE10: |
| 12783 | case FLASH_5717VENDOR_ST_A_M45PE10: |
| 12784 | case FLASH_5717VENDOR_ST_M_M25PE20: |
| 12785 | case FLASH_5717VENDOR_ST_A_M25PE20: |
| 12786 | case FLASH_5717VENDOR_ST_M_M45PE20: |
| 12787 | case FLASH_5717VENDOR_ST_A_M45PE20: |
| 12788 | case FLASH_5717VENDOR_ST_25USPT: |
| 12789 | case FLASH_5717VENDOR_ST_45USPT: |
| 12790 | tp->nvram_jedecnum = JEDEC_ST; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12791 | tg3_flag_set(tp, NVRAM_BUFFERED); |
| 12792 | tg3_flag_set(tp, FLASH); |
Matt Carlson | a1b950d | 2009-09-01 13:20:17 +0000 | [diff] [blame] | 12793 | |
| 12794 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
| 12795 | case FLASH_5717VENDOR_ST_M_M25PE20: |
Matt Carlson | a1b950d | 2009-09-01 13:20:17 +0000 | [diff] [blame] | 12796 | case FLASH_5717VENDOR_ST_M_M45PE20: |
Matt Carlson | 66ee33b | 2011-04-05 14:22:51 +0000 | [diff] [blame] | 12797 | /* Detect size with tg3_nvram_get_size() */ |
| 12798 | break; |
| 12799 | case FLASH_5717VENDOR_ST_A_M25PE20: |
Matt Carlson | a1b950d | 2009-09-01 13:20:17 +0000 | [diff] [blame] | 12800 | case FLASH_5717VENDOR_ST_A_M45PE20: |
| 12801 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; |
| 12802 | break; |
| 12803 | default: |
| 12804 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; |
| 12805 | break; |
| 12806 | } |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 12807 | break; |
Matt Carlson | a1b950d | 2009-09-01 13:20:17 +0000 | [diff] [blame] | 12808 | default: |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12809 | tg3_flag_set(tp, NO_NVRAM); |
Matt Carlson | a1b950d | 2009-09-01 13:20:17 +0000 | [diff] [blame] | 12810 | return; |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 12811 | } |
Matt Carlson | a1b950d | 2009-09-01 13:20:17 +0000 | [diff] [blame] | 12812 | |
| 12813 | tg3_nvram_get_pagesize(tp, nvcfg1); |
| 12814 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12815 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 12816 | } |
| 12817 | |
Matt Carlson | 9b91b5f | 2011-04-05 14:22:47 +0000 | [diff] [blame] | 12818 | static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp) |
| 12819 | { |
| 12820 | u32 nvcfg1, nvmpinstrp; |
| 12821 | |
| 12822 | nvcfg1 = tr32(NVRAM_CFG1); |
| 12823 | nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK; |
| 12824 | |
| 12825 | switch (nvmpinstrp) { |
| 12826 | case FLASH_5720_EEPROM_HD: |
| 12827 | case FLASH_5720_EEPROM_LD: |
| 12828 | tp->nvram_jedecnum = JEDEC_ATMEL; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12829 | tg3_flag_set(tp, NVRAM_BUFFERED); |
Matt Carlson | 9b91b5f | 2011-04-05 14:22:47 +0000 | [diff] [blame] | 12830 | |
| 12831 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
| 12832 | tw32(NVRAM_CFG1, nvcfg1); |
| 12833 | if (nvmpinstrp == FLASH_5720_EEPROM_HD) |
| 12834 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; |
| 12835 | else |
| 12836 | tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; |
| 12837 | return; |
| 12838 | case FLASH_5720VENDOR_M_ATMEL_DB011D: |
| 12839 | case FLASH_5720VENDOR_A_ATMEL_DB011B: |
| 12840 | case FLASH_5720VENDOR_A_ATMEL_DB011D: |
| 12841 | case FLASH_5720VENDOR_M_ATMEL_DB021D: |
| 12842 | case FLASH_5720VENDOR_A_ATMEL_DB021B: |
| 12843 | case FLASH_5720VENDOR_A_ATMEL_DB021D: |
| 12844 | case FLASH_5720VENDOR_M_ATMEL_DB041D: |
| 12845 | case FLASH_5720VENDOR_A_ATMEL_DB041B: |
| 12846 | case FLASH_5720VENDOR_A_ATMEL_DB041D: |
| 12847 | case FLASH_5720VENDOR_M_ATMEL_DB081D: |
| 12848 | case FLASH_5720VENDOR_A_ATMEL_DB081D: |
| 12849 | case FLASH_5720VENDOR_ATMEL_45USPT: |
| 12850 | tp->nvram_jedecnum = JEDEC_ATMEL; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12851 | tg3_flag_set(tp, NVRAM_BUFFERED); |
| 12852 | tg3_flag_set(tp, FLASH); |
Matt Carlson | 9b91b5f | 2011-04-05 14:22:47 +0000 | [diff] [blame] | 12853 | |
| 12854 | switch (nvmpinstrp) { |
| 12855 | case FLASH_5720VENDOR_M_ATMEL_DB021D: |
| 12856 | case FLASH_5720VENDOR_A_ATMEL_DB021B: |
| 12857 | case FLASH_5720VENDOR_A_ATMEL_DB021D: |
| 12858 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; |
| 12859 | break; |
| 12860 | case FLASH_5720VENDOR_M_ATMEL_DB041D: |
| 12861 | case FLASH_5720VENDOR_A_ATMEL_DB041B: |
| 12862 | case FLASH_5720VENDOR_A_ATMEL_DB041D: |
| 12863 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; |
| 12864 | break; |
| 12865 | case FLASH_5720VENDOR_M_ATMEL_DB081D: |
| 12866 | case FLASH_5720VENDOR_A_ATMEL_DB081D: |
| 12867 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; |
| 12868 | break; |
| 12869 | default: |
| 12870 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; |
| 12871 | break; |
| 12872 | } |
| 12873 | break; |
| 12874 | case FLASH_5720VENDOR_M_ST_M25PE10: |
| 12875 | case FLASH_5720VENDOR_M_ST_M45PE10: |
| 12876 | case FLASH_5720VENDOR_A_ST_M25PE10: |
| 12877 | case FLASH_5720VENDOR_A_ST_M45PE10: |
| 12878 | case FLASH_5720VENDOR_M_ST_M25PE20: |
| 12879 | case FLASH_5720VENDOR_M_ST_M45PE20: |
| 12880 | case FLASH_5720VENDOR_A_ST_M25PE20: |
| 12881 | case FLASH_5720VENDOR_A_ST_M45PE20: |
| 12882 | case FLASH_5720VENDOR_M_ST_M25PE40: |
| 12883 | case FLASH_5720VENDOR_M_ST_M45PE40: |
| 12884 | case FLASH_5720VENDOR_A_ST_M25PE40: |
| 12885 | case FLASH_5720VENDOR_A_ST_M45PE40: |
| 12886 | case FLASH_5720VENDOR_M_ST_M25PE80: |
| 12887 | case FLASH_5720VENDOR_M_ST_M45PE80: |
| 12888 | case FLASH_5720VENDOR_A_ST_M25PE80: |
| 12889 | case FLASH_5720VENDOR_A_ST_M45PE80: |
| 12890 | case FLASH_5720VENDOR_ST_25USPT: |
| 12891 | case FLASH_5720VENDOR_ST_45USPT: |
| 12892 | tp->nvram_jedecnum = JEDEC_ST; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12893 | tg3_flag_set(tp, NVRAM_BUFFERED); |
| 12894 | tg3_flag_set(tp, FLASH); |
Matt Carlson | 9b91b5f | 2011-04-05 14:22:47 +0000 | [diff] [blame] | 12895 | |
| 12896 | switch (nvmpinstrp) { |
| 12897 | case FLASH_5720VENDOR_M_ST_M25PE20: |
| 12898 | case FLASH_5720VENDOR_M_ST_M45PE20: |
| 12899 | case FLASH_5720VENDOR_A_ST_M25PE20: |
| 12900 | case FLASH_5720VENDOR_A_ST_M45PE20: |
| 12901 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; |
| 12902 | break; |
| 12903 | case FLASH_5720VENDOR_M_ST_M25PE40: |
| 12904 | case FLASH_5720VENDOR_M_ST_M45PE40: |
| 12905 | case FLASH_5720VENDOR_A_ST_M25PE40: |
| 12906 | case FLASH_5720VENDOR_A_ST_M45PE40: |
| 12907 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; |
| 12908 | break; |
| 12909 | case FLASH_5720VENDOR_M_ST_M25PE80: |
| 12910 | case FLASH_5720VENDOR_M_ST_M45PE80: |
| 12911 | case FLASH_5720VENDOR_A_ST_M25PE80: |
| 12912 | case FLASH_5720VENDOR_A_ST_M45PE80: |
| 12913 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; |
| 12914 | break; |
| 12915 | default: |
| 12916 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; |
| 12917 | break; |
| 12918 | } |
| 12919 | break; |
| 12920 | default: |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12921 | tg3_flag_set(tp, NO_NVRAM); |
Matt Carlson | 9b91b5f | 2011-04-05 14:22:47 +0000 | [diff] [blame] | 12922 | return; |
| 12923 | } |
| 12924 | |
| 12925 | tg3_nvram_get_pagesize(tp, nvcfg1); |
| 12926 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12927 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
Matt Carlson | 9b91b5f | 2011-04-05 14:22:47 +0000 | [diff] [blame] | 12928 | } |
| 12929 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12930 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ |
| 12931 | static void __devinit tg3_nvram_init(struct tg3 *tp) |
| 12932 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12933 | tw32_f(GRC_EEPROM_ADDR, |
| 12934 | (EEPROM_ADDR_FSM_RESET | |
| 12935 | (EEPROM_DEFAULT_CLOCK_PERIOD << |
| 12936 | EEPROM_ADDR_CLKPERD_SHIFT))); |
| 12937 | |
Michael Chan | 9d57f01 | 2006-12-07 00:23:25 -0800 | [diff] [blame] | 12938 | msleep(1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12939 | |
| 12940 | /* Enable seeprom accesses. */ |
| 12941 | tw32_f(GRC_LOCAL_CTRL, |
| 12942 | tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); |
| 12943 | udelay(100); |
| 12944 | |
| 12945 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
| 12946 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12947 | tg3_flag_set(tp, NVRAM); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12948 | |
Michael Chan | ec41c7d | 2006-01-17 02:40:55 -0800 | [diff] [blame] | 12949 | if (tg3_nvram_lock(tp)) { |
Matt Carlson | 5129c3a | 2010-04-05 10:19:23 +0000 | [diff] [blame] | 12950 | netdev_warn(tp->dev, |
| 12951 | "Cannot get nvram lock, %s failed\n", |
Joe Perches | 05dbe00 | 2010-02-17 19:44:19 +0000 | [diff] [blame] | 12952 | __func__); |
Michael Chan | ec41c7d | 2006-01-17 02:40:55 -0800 | [diff] [blame] | 12953 | return; |
| 12954 | } |
Michael Chan | e6af301 | 2005-04-21 17:12:05 -0700 | [diff] [blame] | 12955 | tg3_enable_nvram_access(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12956 | |
Matt Carlson | 989a9d2 | 2007-05-05 11:51:05 -0700 | [diff] [blame] | 12957 | tp->nvram_size = 0; |
| 12958 | |
Michael Chan | 361b4ac | 2005-04-21 17:11:21 -0700 | [diff] [blame] | 12959 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) |
| 12960 | tg3_get_5752_nvram_info(tp); |
Michael Chan | d3c7b88 | 2006-03-23 01:28:25 -0800 | [diff] [blame] | 12961 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
| 12962 | tg3_get_5755_nvram_info(tp); |
Matt Carlson | d30cdd2 | 2007-10-07 23:28:35 -0700 | [diff] [blame] | 12963 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
Matt Carlson | 57e6983 | 2008-05-25 23:48:31 -0700 | [diff] [blame] | 12964 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
| 12965 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
Michael Chan | 1b27777 | 2006-03-20 22:27:48 -0800 | [diff] [blame] | 12966 | tg3_get_5787_nvram_info(tp); |
Matt Carlson | 6b91fa0 | 2007-10-10 18:01:09 -0700 | [diff] [blame] | 12967 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
| 12968 | tg3_get_5761_nvram_info(tp); |
Michael Chan | b5d3772 | 2006-09-27 16:06:21 -0700 | [diff] [blame] | 12969 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
| 12970 | tg3_get_5906_nvram_info(tp); |
Matt Carlson | b703df6 | 2009-12-03 08:36:21 +0000 | [diff] [blame] | 12971 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
Matt Carlson | 55086ad | 2011-12-14 11:09:59 +0000 | [diff] [blame] | 12972 | tg3_flag(tp, 57765_CLASS)) |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 12973 | tg3_get_57780_nvram_info(tp); |
Matt Carlson | 9b91b5f | 2011-04-05 14:22:47 +0000 | [diff] [blame] | 12974 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
| 12975 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) |
Matt Carlson | a1b950d | 2009-09-01 13:20:17 +0000 | [diff] [blame] | 12976 | tg3_get_5717_nvram_info(tp); |
Matt Carlson | 9b91b5f | 2011-04-05 14:22:47 +0000 | [diff] [blame] | 12977 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
| 12978 | tg3_get_5720_nvram_info(tp); |
Michael Chan | 361b4ac | 2005-04-21 17:11:21 -0700 | [diff] [blame] | 12979 | else |
| 12980 | tg3_get_nvram_info(tp); |
| 12981 | |
Matt Carlson | 989a9d2 | 2007-05-05 11:51:05 -0700 | [diff] [blame] | 12982 | if (tp->nvram_size == 0) |
| 12983 | tg3_get_nvram_size(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12984 | |
Michael Chan | e6af301 | 2005-04-21 17:12:05 -0700 | [diff] [blame] | 12985 | tg3_disable_nvram_access(tp); |
Michael Chan | 381291b | 2005-12-13 21:08:21 -0800 | [diff] [blame] | 12986 | tg3_nvram_unlock(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12987 | |
| 12988 | } else { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 12989 | tg3_flag_clear(tp, NVRAM); |
| 12990 | tg3_flag_clear(tp, NVRAM_BUFFERED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12991 | |
| 12992 | tg3_get_eeprom_size(tp); |
| 12993 | } |
| 12994 | } |
| 12995 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12996 | struct subsys_tbl_ent { |
| 12997 | u16 subsys_vendor, subsys_devid; |
| 12998 | u32 phy_id; |
| 12999 | }; |
| 13000 | |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13001 | static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13002 | /* Broadcom boards. */ |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13003 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13004 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 }, |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13005 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13006 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 }, |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13007 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13008 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 }, |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13009 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
| 13010 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 }, |
| 13011 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13012 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 }, |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13013 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13014 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 }, |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13015 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
| 13016 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 }, |
| 13017 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13018 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 }, |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13019 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13020 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 }, |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13021 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13022 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 }, |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13023 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13024 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13025 | |
| 13026 | /* 3com boards. */ |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13027 | { TG3PCI_SUBVENDOR_ID_3COM, |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13028 | TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 }, |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13029 | { TG3PCI_SUBVENDOR_ID_3COM, |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13030 | TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 }, |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13031 | { TG3PCI_SUBVENDOR_ID_3COM, |
| 13032 | TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 }, |
| 13033 | { TG3PCI_SUBVENDOR_ID_3COM, |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13034 | TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 }, |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13035 | { TG3PCI_SUBVENDOR_ID_3COM, |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13036 | TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13037 | |
| 13038 | /* DELL boards. */ |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13039 | { TG3PCI_SUBVENDOR_ID_DELL, |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13040 | TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 }, |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13041 | { TG3PCI_SUBVENDOR_ID_DELL, |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13042 | TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 }, |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13043 | { TG3PCI_SUBVENDOR_ID_DELL, |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13044 | TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 }, |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13045 | { TG3PCI_SUBVENDOR_ID_DELL, |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13046 | TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13047 | |
| 13048 | /* Compaq boards. */ |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13049 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13050 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 }, |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13051 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13052 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 }, |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13053 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
| 13054 | TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 }, |
| 13055 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13056 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 }, |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13057 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13058 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13059 | |
| 13060 | /* IBM boards. */ |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13061 | { TG3PCI_SUBVENDOR_ID_IBM, |
| 13062 | TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13063 | }; |
| 13064 | |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13065 | static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13066 | { |
| 13067 | int i; |
| 13068 | |
| 13069 | for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) { |
| 13070 | if ((subsys_id_to_phy_id[i].subsys_vendor == |
| 13071 | tp->pdev->subsystem_vendor) && |
| 13072 | (subsys_id_to_phy_id[i].subsys_devid == |
| 13073 | tp->pdev->subsystem_device)) |
| 13074 | return &subsys_id_to_phy_id[i]; |
| 13075 | } |
| 13076 | return NULL; |
| 13077 | } |
| 13078 | |
Michael Chan | 7d0c41e | 2005-04-21 17:06:20 -0700 | [diff] [blame] | 13079 | static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13080 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13081 | u32 val; |
David S. Miller | f49639e | 2006-06-09 11:58:36 -0700 | [diff] [blame] | 13082 | |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13083 | tp->phy_id = TG3_PHY_ID_INVALID; |
Michael Chan | 7d0c41e | 2005-04-21 17:06:20 -0700 | [diff] [blame] | 13084 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; |
| 13085 | |
Gary Zambrano | a85feb8 | 2007-05-05 11:52:19 -0700 | [diff] [blame] | 13086 | /* Assume an onboard device and WOL capable by default. */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13087 | tg3_flag_set(tp, EEPROM_WRITE_PROT); |
| 13088 | tg3_flag_set(tp, WOL_CAP); |
David S. Miller | 72b845e | 2006-03-14 14:11:48 -0800 | [diff] [blame] | 13089 | |
Michael Chan | b5d3772 | 2006-09-27 16:06:21 -0700 | [diff] [blame] | 13090 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
Michael Chan | 9d26e21 | 2006-12-07 00:21:14 -0800 | [diff] [blame] | 13091 | if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13092 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
| 13093 | tg3_flag_set(tp, IS_NIC); |
Michael Chan | 9d26e21 | 2006-12-07 00:21:14 -0800 | [diff] [blame] | 13094 | } |
Matt Carlson | 0527ba3 | 2007-10-10 18:03:30 -0700 | [diff] [blame] | 13095 | val = tr32(VCPU_CFGSHDW); |
| 13096 | if (val & VCPU_CFGSHDW_ASPM_DBNC) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13097 | tg3_flag_set(tp, ASPM_WORKAROUND); |
Matt Carlson | 0527ba3 | 2007-10-10 18:03:30 -0700 | [diff] [blame] | 13098 | if ((val & VCPU_CFGSHDW_WOL_ENABLE) && |
Rafael J. Wysocki | 6fdbab9 | 2011-04-28 11:02:15 +0000 | [diff] [blame] | 13099 | (val & VCPU_CFGSHDW_WOL_MAGPKT)) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13100 | tg3_flag_set(tp, WOL_ENABLE); |
Rafael J. Wysocki | 6fdbab9 | 2011-04-28 11:02:15 +0000 | [diff] [blame] | 13101 | device_set_wakeup_enable(&tp->pdev->dev, true); |
| 13102 | } |
Matt Carlson | 05ac4cb | 2008-11-03 16:53:46 -0800 | [diff] [blame] | 13103 | goto done; |
Michael Chan | b5d3772 | 2006-09-27 16:06:21 -0700 | [diff] [blame] | 13104 | } |
| 13105 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13106 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
| 13107 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { |
| 13108 | u32 nic_cfg, led_cfg; |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 13109 | u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id; |
Michael Chan | 7d0c41e | 2005-04-21 17:06:20 -0700 | [diff] [blame] | 13110 | int eeprom_phy_serdes = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13111 | |
| 13112 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); |
| 13113 | tp->nic_sram_data_cfg = nic_cfg; |
| 13114 | |
| 13115 | tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); |
| 13116 | ver >>= NIC_SRAM_DATA_VER_SHIFT; |
Matt Carlson | 6ff6f81 | 2011-05-19 12:12:54 +0000 | [diff] [blame] | 13117 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
| 13118 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && |
| 13119 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13120 | (ver > 0) && (ver < 0x100)) |
| 13121 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); |
| 13122 | |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 13123 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
| 13124 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); |
| 13125 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13126 | if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == |
| 13127 | NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) |
| 13128 | eeprom_phy_serdes = 1; |
| 13129 | |
| 13130 | tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); |
| 13131 | if (nic_phy_id != 0) { |
| 13132 | u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK; |
| 13133 | u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK; |
| 13134 | |
| 13135 | eeprom_phy_id = (id1 >> 16) << 10; |
| 13136 | eeprom_phy_id |= (id2 & 0xfc00) << 16; |
| 13137 | eeprom_phy_id |= (id2 & 0x03ff) << 0; |
| 13138 | } else |
| 13139 | eeprom_phy_id = 0; |
| 13140 | |
Michael Chan | 7d0c41e | 2005-04-21 17:06:20 -0700 | [diff] [blame] | 13141 | tp->phy_id = eeprom_phy_id; |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 13142 | if (eeprom_phy_serdes) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13143 | if (!tg3_flag(tp, 5705_PLUS)) |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 13144 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
Matt Carlson | a50d079 | 2010-06-05 17:24:37 +0000 | [diff] [blame] | 13145 | else |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 13146 | tp->phy_flags |= TG3_PHYFLG_MII_SERDES; |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 13147 | } |
Michael Chan | 7d0c41e | 2005-04-21 17:06:20 -0700 | [diff] [blame] | 13148 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13149 | if (tg3_flag(tp, 5750_PLUS)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13150 | led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | |
| 13151 | SHASTA_EXT_LED_MODE_MASK); |
John W. Linville | cbf4685 | 2005-04-21 17:01:29 -0700 | [diff] [blame] | 13152 | else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13153 | led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK; |
| 13154 | |
| 13155 | switch (led_cfg) { |
| 13156 | default: |
| 13157 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1: |
| 13158 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; |
| 13159 | break; |
| 13160 | |
| 13161 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2: |
| 13162 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; |
| 13163 | break; |
| 13164 | |
| 13165 | case NIC_SRAM_DATA_CFG_LED_MODE_MAC: |
| 13166 | tp->led_ctrl = LED_CTRL_MODE_MAC; |
Michael Chan | 9ba2779 | 2005-06-06 15:16:20 -0700 | [diff] [blame] | 13167 | |
| 13168 | /* Default to PHY_1_MODE if 0 (MAC_MODE) is |
| 13169 | * read on some older 5700/5701 bootcode. |
| 13170 | */ |
| 13171 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
| 13172 | ASIC_REV_5700 || |
| 13173 | GET_ASIC_REV(tp->pci_chip_rev_id) == |
| 13174 | ASIC_REV_5701) |
| 13175 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; |
| 13176 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13177 | break; |
| 13178 | |
| 13179 | case SHASTA_EXT_LED_SHARED: |
| 13180 | tp->led_ctrl = LED_CTRL_MODE_SHARED; |
| 13181 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && |
| 13182 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A1) |
| 13183 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | |
| 13184 | LED_CTRL_MODE_PHY_2); |
| 13185 | break; |
| 13186 | |
| 13187 | case SHASTA_EXT_LED_MAC: |
| 13188 | tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; |
| 13189 | break; |
| 13190 | |
| 13191 | case SHASTA_EXT_LED_COMBO: |
| 13192 | tp->led_ctrl = LED_CTRL_MODE_COMBO; |
| 13193 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) |
| 13194 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | |
| 13195 | LED_CTRL_MODE_PHY_2); |
| 13196 | break; |
| 13197 | |
Stephen Hemminger | 855e111 | 2008-04-16 16:37:28 -0700 | [diff] [blame] | 13198 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13199 | |
| 13200 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
| 13201 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && |
| 13202 | tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) |
| 13203 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; |
| 13204 | |
Matt Carlson | b2a5c19 | 2008-04-03 21:44:44 -0700 | [diff] [blame] | 13205 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) |
| 13206 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; |
Matt Carlson | 5f60891 | 2007-11-12 21:17:07 -0800 | [diff] [blame] | 13207 | |
Michael Chan | 9d26e21 | 2006-12-07 00:21:14 -0800 | [diff] [blame] | 13208 | if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13209 | tg3_flag_set(tp, EEPROM_WRITE_PROT); |
Michael Chan | 9d26e21 | 2006-12-07 00:21:14 -0800 | [diff] [blame] | 13210 | if ((tp->pdev->subsystem_vendor == |
| 13211 | PCI_VENDOR_ID_ARIMA) && |
| 13212 | (tp->pdev->subsystem_device == 0x205a || |
| 13213 | tp->pdev->subsystem_device == 0x2063)) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13214 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
Michael Chan | 9d26e21 | 2006-12-07 00:21:14 -0800 | [diff] [blame] | 13215 | } else { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13216 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
| 13217 | tg3_flag_set(tp, IS_NIC); |
Michael Chan | 9d26e21 | 2006-12-07 00:21:14 -0800 | [diff] [blame] | 13218 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13219 | |
| 13220 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13221 | tg3_flag_set(tp, ENABLE_ASF); |
| 13222 | if (tg3_flag(tp, 5750_PLUS)) |
| 13223 | tg3_flag_set(tp, ASF_NEW_HANDSHAKE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13224 | } |
Matt Carlson | b2b98d4 | 2008-11-03 16:52:32 -0800 | [diff] [blame] | 13225 | |
| 13226 | if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13227 | tg3_flag(tp, 5750_PLUS)) |
| 13228 | tg3_flag_set(tp, ENABLE_APE); |
Matt Carlson | b2b98d4 | 2008-11-03 16:52:32 -0800 | [diff] [blame] | 13229 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 13230 | if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && |
Gary Zambrano | a85feb8 | 2007-05-05 11:52:19 -0700 | [diff] [blame] | 13231 | !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13232 | tg3_flag_clear(tp, WOL_CAP); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13233 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13234 | if (tg3_flag(tp, WOL_CAP) && |
Rafael J. Wysocki | 6fdbab9 | 2011-04-28 11:02:15 +0000 | [diff] [blame] | 13235 | (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13236 | tg3_flag_set(tp, WOL_ENABLE); |
Rafael J. Wysocki | 6fdbab9 | 2011-04-28 11:02:15 +0000 | [diff] [blame] | 13237 | device_set_wakeup_enable(&tp->pdev->dev, true); |
| 13238 | } |
Matt Carlson | 0527ba3 | 2007-10-10 18:03:30 -0700 | [diff] [blame] | 13239 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13240 | if (cfg2 & (1 << 17)) |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 13241 | tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13242 | |
| 13243 | /* serdes signal pre-emphasis in register 0x590 set by */ |
| 13244 | /* bootcode if bit 18 is set */ |
| 13245 | if (cfg2 & (1 << 18)) |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 13246 | tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; |
Matt Carlson | 8ed5d97 | 2007-05-07 00:25:49 -0700 | [diff] [blame] | 13247 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13248 | if ((tg3_flag(tp, 57765_PLUS) || |
| 13249 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
| 13250 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) && |
Matt Carlson | 6833c04 | 2008-11-21 17:18:59 -0800 | [diff] [blame] | 13251 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 13252 | tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; |
Matt Carlson | 6833c04 | 2008-11-21 17:18:59 -0800 | [diff] [blame] | 13253 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13254 | if (tg3_flag(tp, PCI_EXPRESS) && |
Matt Carlson | 8c69b1e | 2010-08-02 11:26:00 +0000 | [diff] [blame] | 13255 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13256 | !tg3_flag(tp, 57765_PLUS)) { |
Matt Carlson | 8ed5d97 | 2007-05-07 00:25:49 -0700 | [diff] [blame] | 13257 | u32 cfg3; |
| 13258 | |
| 13259 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); |
| 13260 | if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13261 | tg3_flag_set(tp, ASPM_WORKAROUND); |
Matt Carlson | 8ed5d97 | 2007-05-07 00:25:49 -0700 | [diff] [blame] | 13262 | } |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 13263 | |
Matt Carlson | 1441706 | 2010-02-17 15:16:59 +0000 | [diff] [blame] | 13264 | if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13265 | tg3_flag_set(tp, RGMII_INBAND_DISABLE); |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 13266 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13267 | tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN); |
Matt Carlson | a9daf36 | 2008-05-25 23:49:44 -0700 | [diff] [blame] | 13268 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13269 | tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13270 | } |
Matt Carlson | 05ac4cb | 2008-11-03 16:53:46 -0800 | [diff] [blame] | 13271 | done: |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13272 | if (tg3_flag(tp, WOL_CAP)) |
Rafael J. Wysocki | 43067ed | 2011-02-10 06:53:09 +0000 | [diff] [blame] | 13273 | device_set_wakeup_enable(&tp->pdev->dev, |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13274 | tg3_flag(tp, WOL_ENABLE)); |
Rafael J. Wysocki | 43067ed | 2011-02-10 06:53:09 +0000 | [diff] [blame] | 13275 | else |
| 13276 | device_set_wakeup_capable(&tp->pdev->dev, false); |
Michael Chan | 7d0c41e | 2005-04-21 17:06:20 -0700 | [diff] [blame] | 13277 | } |
| 13278 | |
Matt Carlson | b2a5c19 | 2008-04-03 21:44:44 -0700 | [diff] [blame] | 13279 | static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd) |
| 13280 | { |
| 13281 | int i; |
| 13282 | u32 val; |
| 13283 | |
| 13284 | tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START); |
| 13285 | tw32(OTP_CTRL, cmd); |
| 13286 | |
| 13287 | /* Wait for up to 1 ms for command to execute. */ |
| 13288 | for (i = 0; i < 100; i++) { |
| 13289 | val = tr32(OTP_STATUS); |
| 13290 | if (val & OTP_STATUS_CMD_DONE) |
| 13291 | break; |
| 13292 | udelay(10); |
| 13293 | } |
| 13294 | |
| 13295 | return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; |
| 13296 | } |
| 13297 | |
| 13298 | /* Read the gphy configuration from the OTP region of the chip. The gphy |
| 13299 | * configuration is a 32-bit value that straddles the alignment boundary. |
| 13300 | * We do two 32-bit reads and then shift and merge the results. |
| 13301 | */ |
| 13302 | static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp) |
| 13303 | { |
| 13304 | u32 bhalf_otp, thalf_otp; |
| 13305 | |
| 13306 | tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC); |
| 13307 | |
| 13308 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) |
| 13309 | return 0; |
| 13310 | |
| 13311 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1); |
| 13312 | |
| 13313 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) |
| 13314 | return 0; |
| 13315 | |
| 13316 | thalf_otp = tr32(OTP_READ_DATA); |
| 13317 | |
| 13318 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2); |
| 13319 | |
| 13320 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) |
| 13321 | return 0; |
| 13322 | |
| 13323 | bhalf_otp = tr32(OTP_READ_DATA); |
| 13324 | |
| 13325 | return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16); |
| 13326 | } |
| 13327 | |
Matt Carlson | e256f8a | 2011-03-09 16:58:24 +0000 | [diff] [blame] | 13328 | static void __devinit tg3_phy_init_link_config(struct tg3 *tp) |
| 13329 | { |
Hiroaki SHIMODA | 202ff1c | 2011-11-22 04:05:41 +0000 | [diff] [blame] | 13330 | u32 adv = ADVERTISED_Autoneg; |
Matt Carlson | e256f8a | 2011-03-09 16:58:24 +0000 | [diff] [blame] | 13331 | |
| 13332 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) |
| 13333 | adv |= ADVERTISED_1000baseT_Half | |
| 13334 | ADVERTISED_1000baseT_Full; |
| 13335 | |
| 13336 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
| 13337 | adv |= ADVERTISED_100baseT_Half | |
| 13338 | ADVERTISED_100baseT_Full | |
| 13339 | ADVERTISED_10baseT_Half | |
| 13340 | ADVERTISED_10baseT_Full | |
| 13341 | ADVERTISED_TP; |
| 13342 | else |
| 13343 | adv |= ADVERTISED_FIBRE; |
| 13344 | |
| 13345 | tp->link_config.advertising = adv; |
| 13346 | tp->link_config.speed = SPEED_INVALID; |
| 13347 | tp->link_config.duplex = DUPLEX_INVALID; |
| 13348 | tp->link_config.autoneg = AUTONEG_ENABLE; |
| 13349 | tp->link_config.active_speed = SPEED_INVALID; |
| 13350 | tp->link_config.active_duplex = DUPLEX_INVALID; |
| 13351 | tp->link_config.orig_speed = SPEED_INVALID; |
| 13352 | tp->link_config.orig_duplex = DUPLEX_INVALID; |
| 13353 | tp->link_config.orig_autoneg = AUTONEG_INVALID; |
| 13354 | } |
| 13355 | |
Michael Chan | 7d0c41e | 2005-04-21 17:06:20 -0700 | [diff] [blame] | 13356 | static int __devinit tg3_phy_probe(struct tg3 *tp) |
| 13357 | { |
| 13358 | u32 hw_phy_id_1, hw_phy_id_2; |
| 13359 | u32 hw_phy_id, hw_phy_id_masked; |
| 13360 | int err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13361 | |
Matt Carlson | e256f8a | 2011-03-09 16:58:24 +0000 | [diff] [blame] | 13362 | /* flow control autonegotiation is default behavior */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13363 | tg3_flag_set(tp, PAUSE_AUTONEG); |
Matt Carlson | e256f8a | 2011-03-09 16:58:24 +0000 | [diff] [blame] | 13364 | tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; |
| 13365 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13366 | if (tg3_flag(tp, USE_PHYLIB)) |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 13367 | return tg3_phy_init(tp); |
| 13368 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13369 | /* Reading the PHY ID register can conflict with ASF |
Nick Andrew | 877d031 | 2009-01-26 11:06:57 +0100 | [diff] [blame] | 13370 | * firmware access to the PHY hardware. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13371 | */ |
| 13372 | err = 0; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13373 | if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) { |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13374 | hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13375 | } else { |
| 13376 | /* Now read the physical PHY_ID from the chip and verify |
| 13377 | * that it is sane. If it doesn't look good, we fall back |
| 13378 | * to either the hard-coded table based PHY_ID and failing |
| 13379 | * that the value found in the eeprom area. |
| 13380 | */ |
| 13381 | err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); |
| 13382 | err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); |
| 13383 | |
| 13384 | hw_phy_id = (hw_phy_id_1 & 0xffff) << 10; |
| 13385 | hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; |
| 13386 | hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; |
| 13387 | |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13388 | hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13389 | } |
| 13390 | |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13391 | if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13392 | tp->phy_id = hw_phy_id; |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13393 | if (hw_phy_id_masked == TG3_PHY_ID_BCM8002) |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 13394 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
Michael Chan | da6b2d0 | 2005-08-19 12:54:29 -0700 | [diff] [blame] | 13395 | else |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 13396 | tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13397 | } else { |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13398 | if (tp->phy_id != TG3_PHY_ID_INVALID) { |
Michael Chan | 7d0c41e | 2005-04-21 17:06:20 -0700 | [diff] [blame] | 13399 | /* Do nothing, phy ID already set up in |
| 13400 | * tg3_get_eeprom_hw_cfg(). |
| 13401 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13402 | } else { |
| 13403 | struct subsys_tbl_ent *p; |
| 13404 | |
| 13405 | /* No eeprom signature? Try the hardcoded |
| 13406 | * subsys device table. |
| 13407 | */ |
Matt Carlson | 24daf2b | 2010-02-17 15:17:02 +0000 | [diff] [blame] | 13408 | p = tg3_lookup_by_subsys(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13409 | if (!p) |
| 13410 | return -ENODEV; |
| 13411 | |
| 13412 | tp->phy_id = p->phy_id; |
| 13413 | if (!tp->phy_id || |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13414 | tp->phy_id == TG3_PHY_ID_BCM8002) |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 13415 | tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13416 | } |
| 13417 | } |
| 13418 | |
Matt Carlson | a6b68da | 2010-12-06 08:28:52 +0000 | [diff] [blame] | 13419 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
Matt Carlson | 5baa5e9 | 2011-07-20 10:20:53 +0000 | [diff] [blame] | 13420 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
| 13421 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 || |
| 13422 | (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 && |
Matt Carlson | a6b68da | 2010-12-06 08:28:52 +0000 | [diff] [blame] | 13423 | tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) || |
| 13424 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 && |
| 13425 | tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))) |
Matt Carlson | 52b02d0 | 2010-10-14 10:37:41 +0000 | [diff] [blame] | 13426 | tp->phy_flags |= TG3_PHYFLG_EEE_CAP; |
| 13427 | |
Matt Carlson | e256f8a | 2011-03-09 16:58:24 +0000 | [diff] [blame] | 13428 | tg3_phy_init_link_config(tp); |
| 13429 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 13430 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13431 | !tg3_flag(tp, ENABLE_APE) && |
| 13432 | !tg3_flag(tp, ENABLE_ASF)) { |
Matt Carlson | e2bf73e | 2011-12-08 14:40:15 +0000 | [diff] [blame] | 13433 | u32 bmsr, dummy; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13434 | |
| 13435 | tg3_readphy(tp, MII_BMSR, &bmsr); |
| 13436 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && |
| 13437 | (bmsr & BMSR_LSTATUS)) |
| 13438 | goto skip_phy_reset; |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 13439 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13440 | err = tg3_phy_reset(tp); |
| 13441 | if (err) |
| 13442 | return err; |
| 13443 | |
Matt Carlson | 42b64a4 | 2011-05-19 12:12:49 +0000 | [diff] [blame] | 13444 | tg3_phy_set_wirespeed(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13445 | |
Matt Carlson | e2bf73e | 2011-12-08 14:40:15 +0000 | [diff] [blame] | 13446 | if (!tg3_phy_copper_an_config_ok(tp, &dummy)) { |
Matt Carlson | 42b64a4 | 2011-05-19 12:12:49 +0000 | [diff] [blame] | 13447 | tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, |
| 13448 | tp->link_config.flowctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13449 | |
| 13450 | tg3_writephy(tp, MII_BMCR, |
| 13451 | BMCR_ANENABLE | BMCR_ANRESTART); |
| 13452 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13453 | } |
| 13454 | |
| 13455 | skip_phy_reset: |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 13456 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13457 | err = tg3_init_5401phy_dsp(tp); |
| 13458 | if (err) |
| 13459 | return err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13460 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13461 | err = tg3_init_5401phy_dsp(tp); |
| 13462 | } |
| 13463 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13464 | return err; |
| 13465 | } |
| 13466 | |
Matt Carlson | 184b890 | 2010-04-05 10:19:25 +0000 | [diff] [blame] | 13467 | static void __devinit tg3_read_vpd(struct tg3 *tp) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13468 | { |
Matt Carlson | a4a8bb1 | 2010-09-15 09:00:00 +0000 | [diff] [blame] | 13469 | u8 *vpd_data; |
Matt Carlson | 4181b2c | 2010-02-26 14:04:45 +0000 | [diff] [blame] | 13470 | unsigned int block_end, rosize, len; |
Matt Carlson | 535a490 | 2011-07-20 10:20:56 +0000 | [diff] [blame] | 13471 | u32 vpdlen; |
Matt Carlson | 184b890 | 2010-04-05 10:19:25 +0000 | [diff] [blame] | 13472 | int j, i = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13473 | |
Matt Carlson | 535a490 | 2011-07-20 10:20:56 +0000 | [diff] [blame] | 13474 | vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen); |
Matt Carlson | a4a8bb1 | 2010-09-15 09:00:00 +0000 | [diff] [blame] | 13475 | if (!vpd_data) |
| 13476 | goto out_no_vpd; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13477 | |
Matt Carlson | 535a490 | 2011-07-20 10:20:56 +0000 | [diff] [blame] | 13478 | i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA); |
Matt Carlson | 4181b2c | 2010-02-26 14:04:45 +0000 | [diff] [blame] | 13479 | if (i < 0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13480 | goto out_not_found; |
Matt Carlson | 4181b2c | 2010-02-26 14:04:45 +0000 | [diff] [blame] | 13481 | |
| 13482 | rosize = pci_vpd_lrdt_size(&vpd_data[i]); |
| 13483 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize; |
| 13484 | i += PCI_VPD_LRDT_TAG_SIZE; |
| 13485 | |
Matt Carlson | 535a490 | 2011-07-20 10:20:56 +0000 | [diff] [blame] | 13486 | if (block_end > vpdlen) |
Matt Carlson | 4181b2c | 2010-02-26 14:04:45 +0000 | [diff] [blame] | 13487 | goto out_not_found; |
| 13488 | |
Matt Carlson | 184b890 | 2010-04-05 10:19:25 +0000 | [diff] [blame] | 13489 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
| 13490 | PCI_VPD_RO_KEYWORD_MFR_ID); |
| 13491 | if (j > 0) { |
| 13492 | len = pci_vpd_info_field_size(&vpd_data[j]); |
| 13493 | |
| 13494 | j += PCI_VPD_INFO_FLD_HDR_SIZE; |
| 13495 | if (j + len > block_end || len != 4 || |
| 13496 | memcmp(&vpd_data[j], "1028", 4)) |
| 13497 | goto partno; |
| 13498 | |
| 13499 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
| 13500 | PCI_VPD_RO_KEYWORD_VENDOR0); |
| 13501 | if (j < 0) |
| 13502 | goto partno; |
| 13503 | |
| 13504 | len = pci_vpd_info_field_size(&vpd_data[j]); |
| 13505 | |
| 13506 | j += PCI_VPD_INFO_FLD_HDR_SIZE; |
| 13507 | if (j + len > block_end) |
| 13508 | goto partno; |
| 13509 | |
| 13510 | memcpy(tp->fw_ver, &vpd_data[j], len); |
Matt Carlson | 535a490 | 2011-07-20 10:20:56 +0000 | [diff] [blame] | 13511 | strncat(tp->fw_ver, " bc ", vpdlen - len - 1); |
Matt Carlson | 184b890 | 2010-04-05 10:19:25 +0000 | [diff] [blame] | 13512 | } |
| 13513 | |
| 13514 | partno: |
Matt Carlson | 4181b2c | 2010-02-26 14:04:45 +0000 | [diff] [blame] | 13515 | i = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
| 13516 | PCI_VPD_RO_KEYWORD_PARTNO); |
| 13517 | if (i < 0) |
| 13518 | goto out_not_found; |
| 13519 | |
| 13520 | len = pci_vpd_info_field_size(&vpd_data[i]); |
| 13521 | |
| 13522 | i += PCI_VPD_INFO_FLD_HDR_SIZE; |
| 13523 | if (len > TG3_BPN_SIZE || |
Matt Carlson | 535a490 | 2011-07-20 10:20:56 +0000 | [diff] [blame] | 13524 | (len + i) > vpdlen) |
Matt Carlson | 4181b2c | 2010-02-26 14:04:45 +0000 | [diff] [blame] | 13525 | goto out_not_found; |
| 13526 | |
| 13527 | memcpy(tp->board_part_number, &vpd_data[i], len); |
| 13528 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13529 | out_not_found: |
Matt Carlson | a4a8bb1 | 2010-09-15 09:00:00 +0000 | [diff] [blame] | 13530 | kfree(vpd_data); |
Matt Carlson | 37a949c | 2010-09-30 10:34:33 +0000 | [diff] [blame] | 13531 | if (tp->board_part_number[0]) |
Matt Carlson | a4a8bb1 | 2010-09-15 09:00:00 +0000 | [diff] [blame] | 13532 | return; |
| 13533 | |
| 13534 | out_no_vpd: |
Matt Carlson | 37a949c | 2010-09-30 10:34:33 +0000 | [diff] [blame] | 13535 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { |
| 13536 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717) |
| 13537 | strcpy(tp->board_part_number, "BCM5717"); |
| 13538 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) |
| 13539 | strcpy(tp->board_part_number, "BCM5718"); |
| 13540 | else |
| 13541 | goto nomatch; |
| 13542 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
| 13543 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) |
| 13544 | strcpy(tp->board_part_number, "BCM57780"); |
| 13545 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) |
| 13546 | strcpy(tp->board_part_number, "BCM57760"); |
| 13547 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) |
| 13548 | strcpy(tp->board_part_number, "BCM57790"); |
| 13549 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) |
| 13550 | strcpy(tp->board_part_number, "BCM57788"); |
| 13551 | else |
| 13552 | goto nomatch; |
| 13553 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { |
| 13554 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) |
| 13555 | strcpy(tp->board_part_number, "BCM57761"); |
| 13556 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) |
| 13557 | strcpy(tp->board_part_number, "BCM57765"); |
| 13558 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) |
| 13559 | strcpy(tp->board_part_number, "BCM57781"); |
| 13560 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) |
| 13561 | strcpy(tp->board_part_number, "BCM57785"); |
| 13562 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) |
| 13563 | strcpy(tp->board_part_number, "BCM57791"); |
| 13564 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) |
| 13565 | strcpy(tp->board_part_number, "BCM57795"); |
| 13566 | else |
| 13567 | goto nomatch; |
Matt Carlson | 55086ad | 2011-12-14 11:09:59 +0000 | [diff] [blame] | 13568 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) { |
| 13569 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762) |
| 13570 | strcpy(tp->board_part_number, "BCM57762"); |
| 13571 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766) |
| 13572 | strcpy(tp->board_part_number, "BCM57766"); |
| 13573 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782) |
| 13574 | strcpy(tp->board_part_number, "BCM57782"); |
| 13575 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) |
| 13576 | strcpy(tp->board_part_number, "BCM57786"); |
| 13577 | else |
| 13578 | goto nomatch; |
Matt Carlson | 37a949c | 2010-09-30 10:34:33 +0000 | [diff] [blame] | 13579 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
Michael Chan | b5d3772 | 2006-09-27 16:06:21 -0700 | [diff] [blame] | 13580 | strcpy(tp->board_part_number, "BCM95906"); |
Matt Carlson | 37a949c | 2010-09-30 10:34:33 +0000 | [diff] [blame] | 13581 | } else { |
| 13582 | nomatch: |
Michael Chan | b5d3772 | 2006-09-27 16:06:21 -0700 | [diff] [blame] | 13583 | strcpy(tp->board_part_number, "none"); |
Matt Carlson | 37a949c | 2010-09-30 10:34:33 +0000 | [diff] [blame] | 13584 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13585 | } |
| 13586 | |
Matt Carlson | 9c8a620 | 2007-10-21 16:16:08 -0700 | [diff] [blame] | 13587 | static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) |
| 13588 | { |
| 13589 | u32 val; |
| 13590 | |
Matt Carlson | e4f3411 | 2009-02-25 14:25:00 +0000 | [diff] [blame] | 13591 | if (tg3_nvram_read(tp, offset, &val) || |
Matt Carlson | 9c8a620 | 2007-10-21 16:16:08 -0700 | [diff] [blame] | 13592 | (val & 0xfc000000) != 0x0c000000 || |
Matt Carlson | e4f3411 | 2009-02-25 14:25:00 +0000 | [diff] [blame] | 13593 | tg3_nvram_read(tp, offset + 4, &val) || |
Matt Carlson | 9c8a620 | 2007-10-21 16:16:08 -0700 | [diff] [blame] | 13594 | val != 0) |
| 13595 | return 0; |
| 13596 | |
| 13597 | return 1; |
| 13598 | } |
| 13599 | |
Matt Carlson | acd9c11 | 2009-02-25 14:26:33 +0000 | [diff] [blame] | 13600 | static void __devinit tg3_read_bc_ver(struct tg3 *tp) |
| 13601 | { |
Matt Carlson | ff3a7cb | 2009-02-25 14:26:58 +0000 | [diff] [blame] | 13602 | u32 val, offset, start, ver_offset; |
Matt Carlson | 75f9936 | 2010-04-05 10:19:24 +0000 | [diff] [blame] | 13603 | int i, dst_off; |
Matt Carlson | ff3a7cb | 2009-02-25 14:26:58 +0000 | [diff] [blame] | 13604 | bool newver = false; |
Matt Carlson | acd9c11 | 2009-02-25 14:26:33 +0000 | [diff] [blame] | 13605 | |
| 13606 | if (tg3_nvram_read(tp, 0xc, &offset) || |
| 13607 | tg3_nvram_read(tp, 0x4, &start)) |
| 13608 | return; |
| 13609 | |
| 13610 | offset = tg3_nvram_logical_addr(tp, offset); |
| 13611 | |
Matt Carlson | ff3a7cb | 2009-02-25 14:26:58 +0000 | [diff] [blame] | 13612 | if (tg3_nvram_read(tp, offset, &val)) |
Matt Carlson | acd9c11 | 2009-02-25 14:26:33 +0000 | [diff] [blame] | 13613 | return; |
| 13614 | |
Matt Carlson | ff3a7cb | 2009-02-25 14:26:58 +0000 | [diff] [blame] | 13615 | if ((val & 0xfc000000) == 0x0c000000) { |
| 13616 | if (tg3_nvram_read(tp, offset + 4, &val)) |
Matt Carlson | acd9c11 | 2009-02-25 14:26:33 +0000 | [diff] [blame] | 13617 | return; |
| 13618 | |
Matt Carlson | ff3a7cb | 2009-02-25 14:26:58 +0000 | [diff] [blame] | 13619 | if (val == 0) |
| 13620 | newver = true; |
| 13621 | } |
| 13622 | |
Matt Carlson | 75f9936 | 2010-04-05 10:19:24 +0000 | [diff] [blame] | 13623 | dst_off = strlen(tp->fw_ver); |
| 13624 | |
Matt Carlson | ff3a7cb | 2009-02-25 14:26:58 +0000 | [diff] [blame] | 13625 | if (newver) { |
Matt Carlson | 75f9936 | 2010-04-05 10:19:24 +0000 | [diff] [blame] | 13626 | if (TG3_VER_SIZE - dst_off < 16 || |
| 13627 | tg3_nvram_read(tp, offset + 8, &ver_offset)) |
Matt Carlson | ff3a7cb | 2009-02-25 14:26:58 +0000 | [diff] [blame] | 13628 | return; |
| 13629 | |
| 13630 | offset = offset + ver_offset - start; |
| 13631 | for (i = 0; i < 16; i += 4) { |
| 13632 | __be32 v; |
| 13633 | if (tg3_nvram_read_be32(tp, offset + i, &v)) |
| 13634 | return; |
| 13635 | |
Matt Carlson | 75f9936 | 2010-04-05 10:19:24 +0000 | [diff] [blame] | 13636 | memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); |
Matt Carlson | ff3a7cb | 2009-02-25 14:26:58 +0000 | [diff] [blame] | 13637 | } |
| 13638 | } else { |
| 13639 | u32 major, minor; |
| 13640 | |
| 13641 | if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) |
| 13642 | return; |
| 13643 | |
| 13644 | major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >> |
| 13645 | TG3_NVM_BCVER_MAJSFT; |
| 13646 | minor = ver_offset & TG3_NVM_BCVER_MINMSK; |
Matt Carlson | 75f9936 | 2010-04-05 10:19:24 +0000 | [diff] [blame] | 13647 | snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, |
| 13648 | "v%d.%02d", major, minor); |
Matt Carlson | acd9c11 | 2009-02-25 14:26:33 +0000 | [diff] [blame] | 13649 | } |
| 13650 | } |
| 13651 | |
Matt Carlson | a6f6cb1 | 2009-02-25 14:27:43 +0000 | [diff] [blame] | 13652 | static void __devinit tg3_read_hwsb_ver(struct tg3 *tp) |
| 13653 | { |
| 13654 | u32 val, major, minor; |
| 13655 | |
| 13656 | /* Use native endian representation */ |
| 13657 | if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) |
| 13658 | return; |
| 13659 | |
| 13660 | major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >> |
| 13661 | TG3_NVM_HWSB_CFG1_MAJSFT; |
| 13662 | minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >> |
| 13663 | TG3_NVM_HWSB_CFG1_MINSFT; |
| 13664 | |
| 13665 | snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); |
| 13666 | } |
| 13667 | |
Matt Carlson | dfe00d7 | 2008-11-21 17:19:41 -0800 | [diff] [blame] | 13668 | static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) |
| 13669 | { |
| 13670 | u32 offset, major, minor, build; |
| 13671 | |
Matt Carlson | 75f9936 | 2010-04-05 10:19:24 +0000 | [diff] [blame] | 13672 | strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); |
Matt Carlson | dfe00d7 | 2008-11-21 17:19:41 -0800 | [diff] [blame] | 13673 | |
| 13674 | if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) |
| 13675 | return; |
| 13676 | |
| 13677 | switch (val & TG3_EEPROM_SB_REVISION_MASK) { |
| 13678 | case TG3_EEPROM_SB_REVISION_0: |
| 13679 | offset = TG3_EEPROM_SB_F1R0_EDH_OFF; |
| 13680 | break; |
| 13681 | case TG3_EEPROM_SB_REVISION_2: |
| 13682 | offset = TG3_EEPROM_SB_F1R2_EDH_OFF; |
| 13683 | break; |
| 13684 | case TG3_EEPROM_SB_REVISION_3: |
| 13685 | offset = TG3_EEPROM_SB_F1R3_EDH_OFF; |
| 13686 | break; |
Matt Carlson | a4153d4 | 2010-02-17 15:16:56 +0000 | [diff] [blame] | 13687 | case TG3_EEPROM_SB_REVISION_4: |
| 13688 | offset = TG3_EEPROM_SB_F1R4_EDH_OFF; |
| 13689 | break; |
| 13690 | case TG3_EEPROM_SB_REVISION_5: |
| 13691 | offset = TG3_EEPROM_SB_F1R5_EDH_OFF; |
| 13692 | break; |
Matt Carlson | bba226a | 2010-10-14 10:37:38 +0000 | [diff] [blame] | 13693 | case TG3_EEPROM_SB_REVISION_6: |
| 13694 | offset = TG3_EEPROM_SB_F1R6_EDH_OFF; |
| 13695 | break; |
Matt Carlson | dfe00d7 | 2008-11-21 17:19:41 -0800 | [diff] [blame] | 13696 | default: |
| 13697 | return; |
| 13698 | } |
| 13699 | |
Matt Carlson | e4f3411 | 2009-02-25 14:25:00 +0000 | [diff] [blame] | 13700 | if (tg3_nvram_read(tp, offset, &val)) |
Matt Carlson | dfe00d7 | 2008-11-21 17:19:41 -0800 | [diff] [blame] | 13701 | return; |
| 13702 | |
| 13703 | build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> |
| 13704 | TG3_EEPROM_SB_EDH_BLD_SHFT; |
| 13705 | major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >> |
| 13706 | TG3_EEPROM_SB_EDH_MAJ_SHFT; |
| 13707 | minor = val & TG3_EEPROM_SB_EDH_MIN_MASK; |
| 13708 | |
| 13709 | if (minor > 99 || build > 26) |
| 13710 | return; |
| 13711 | |
Matt Carlson | 75f9936 | 2010-04-05 10:19:24 +0000 | [diff] [blame] | 13712 | offset = strlen(tp->fw_ver); |
| 13713 | snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, |
| 13714 | " v%d.%02d", major, minor); |
Matt Carlson | dfe00d7 | 2008-11-21 17:19:41 -0800 | [diff] [blame] | 13715 | |
| 13716 | if (build > 0) { |
Matt Carlson | 75f9936 | 2010-04-05 10:19:24 +0000 | [diff] [blame] | 13717 | offset = strlen(tp->fw_ver); |
| 13718 | if (offset < TG3_VER_SIZE - 1) |
| 13719 | tp->fw_ver[offset] = 'a' + build - 1; |
Matt Carlson | dfe00d7 | 2008-11-21 17:19:41 -0800 | [diff] [blame] | 13720 | } |
| 13721 | } |
| 13722 | |
Matt Carlson | acd9c11 | 2009-02-25 14:26:33 +0000 | [diff] [blame] | 13723 | static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp) |
Michael Chan | c4e6575 | 2006-03-20 22:29:32 -0800 | [diff] [blame] | 13724 | { |
| 13725 | u32 val, offset, start; |
Matt Carlson | acd9c11 | 2009-02-25 14:26:33 +0000 | [diff] [blame] | 13726 | int i, vlen; |
Matt Carlson | 9c8a620 | 2007-10-21 16:16:08 -0700 | [diff] [blame] | 13727 | |
| 13728 | for (offset = TG3_NVM_DIR_START; |
| 13729 | offset < TG3_NVM_DIR_END; |
| 13730 | offset += TG3_NVM_DIRENT_SIZE) { |
Matt Carlson | e4f3411 | 2009-02-25 14:25:00 +0000 | [diff] [blame] | 13731 | if (tg3_nvram_read(tp, offset, &val)) |
Matt Carlson | 9c8a620 | 2007-10-21 16:16:08 -0700 | [diff] [blame] | 13732 | return; |
| 13733 | |
| 13734 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) |
| 13735 | break; |
| 13736 | } |
| 13737 | |
| 13738 | if (offset == TG3_NVM_DIR_END) |
| 13739 | return; |
| 13740 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13741 | if (!tg3_flag(tp, 5705_PLUS)) |
Matt Carlson | 9c8a620 | 2007-10-21 16:16:08 -0700 | [diff] [blame] | 13742 | start = 0x08000000; |
Matt Carlson | e4f3411 | 2009-02-25 14:25:00 +0000 | [diff] [blame] | 13743 | else if (tg3_nvram_read(tp, offset - 4, &start)) |
Matt Carlson | 9c8a620 | 2007-10-21 16:16:08 -0700 | [diff] [blame] | 13744 | return; |
| 13745 | |
Matt Carlson | e4f3411 | 2009-02-25 14:25:00 +0000 | [diff] [blame] | 13746 | if (tg3_nvram_read(tp, offset + 4, &offset) || |
Matt Carlson | 9c8a620 | 2007-10-21 16:16:08 -0700 | [diff] [blame] | 13747 | !tg3_fw_img_is_valid(tp, offset) || |
Matt Carlson | e4f3411 | 2009-02-25 14:25:00 +0000 | [diff] [blame] | 13748 | tg3_nvram_read(tp, offset + 8, &val)) |
Matt Carlson | 9c8a620 | 2007-10-21 16:16:08 -0700 | [diff] [blame] | 13749 | return; |
| 13750 | |
| 13751 | offset += val - start; |
| 13752 | |
Matt Carlson | acd9c11 | 2009-02-25 14:26:33 +0000 | [diff] [blame] | 13753 | vlen = strlen(tp->fw_ver); |
Matt Carlson | 9c8a620 | 2007-10-21 16:16:08 -0700 | [diff] [blame] | 13754 | |
Matt Carlson | acd9c11 | 2009-02-25 14:26:33 +0000 | [diff] [blame] | 13755 | tp->fw_ver[vlen++] = ','; |
| 13756 | tp->fw_ver[vlen++] = ' '; |
Matt Carlson | 9c8a620 | 2007-10-21 16:16:08 -0700 | [diff] [blame] | 13757 | |
| 13758 | for (i = 0; i < 4; i++) { |
Matt Carlson | a9dc529 | 2009-02-25 14:25:30 +0000 | [diff] [blame] | 13759 | __be32 v; |
| 13760 | if (tg3_nvram_read_be32(tp, offset, &v)) |
Matt Carlson | 9c8a620 | 2007-10-21 16:16:08 -0700 | [diff] [blame] | 13761 | return; |
| 13762 | |
Al Viro | b9fc7dc | 2007-12-17 22:59:57 -0800 | [diff] [blame] | 13763 | offset += sizeof(v); |
Matt Carlson | 9c8a620 | 2007-10-21 16:16:08 -0700 | [diff] [blame] | 13764 | |
Matt Carlson | acd9c11 | 2009-02-25 14:26:33 +0000 | [diff] [blame] | 13765 | if (vlen > TG3_VER_SIZE - sizeof(v)) { |
| 13766 | memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); |
Matt Carlson | 9c8a620 | 2007-10-21 16:16:08 -0700 | [diff] [blame] | 13767 | break; |
| 13768 | } |
| 13769 | |
Matt Carlson | acd9c11 | 2009-02-25 14:26:33 +0000 | [diff] [blame] | 13770 | memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); |
| 13771 | vlen += sizeof(v); |
Matt Carlson | 9c8a620 | 2007-10-21 16:16:08 -0700 | [diff] [blame] | 13772 | } |
Matt Carlson | acd9c11 | 2009-02-25 14:26:33 +0000 | [diff] [blame] | 13773 | } |
| 13774 | |
Matt Carlson | 7fd7644 | 2009-02-25 14:27:20 +0000 | [diff] [blame] | 13775 | static void __devinit tg3_read_dash_ver(struct tg3 *tp) |
| 13776 | { |
| 13777 | int vlen; |
| 13778 | u32 apedata; |
Matt Carlson | ecc7964 | 2010-08-02 11:26:01 +0000 | [diff] [blame] | 13779 | char *fwtype; |
Matt Carlson | 7fd7644 | 2009-02-25 14:27:20 +0000 | [diff] [blame] | 13780 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13781 | if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF)) |
Matt Carlson | 7fd7644 | 2009-02-25 14:27:20 +0000 | [diff] [blame] | 13782 | return; |
| 13783 | |
| 13784 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); |
| 13785 | if (apedata != APE_SEG_SIG_MAGIC) |
| 13786 | return; |
| 13787 | |
| 13788 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); |
| 13789 | if (!(apedata & APE_FW_STATUS_READY)) |
| 13790 | return; |
| 13791 | |
| 13792 | apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); |
| 13793 | |
Matt Carlson | dc6d074 | 2010-09-15 08:59:55 +0000 | [diff] [blame] | 13794 | if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13795 | tg3_flag_set(tp, APE_HAS_NCSI); |
Matt Carlson | ecc7964 | 2010-08-02 11:26:01 +0000 | [diff] [blame] | 13796 | fwtype = "NCSI"; |
Matt Carlson | dc6d074 | 2010-09-15 08:59:55 +0000 | [diff] [blame] | 13797 | } else { |
Matt Carlson | ecc7964 | 2010-08-02 11:26:01 +0000 | [diff] [blame] | 13798 | fwtype = "DASH"; |
Matt Carlson | dc6d074 | 2010-09-15 08:59:55 +0000 | [diff] [blame] | 13799 | } |
Matt Carlson | ecc7964 | 2010-08-02 11:26:01 +0000 | [diff] [blame] | 13800 | |
Matt Carlson | 7fd7644 | 2009-02-25 14:27:20 +0000 | [diff] [blame] | 13801 | vlen = strlen(tp->fw_ver); |
| 13802 | |
Matt Carlson | ecc7964 | 2010-08-02 11:26:01 +0000 | [diff] [blame] | 13803 | snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", |
| 13804 | fwtype, |
Matt Carlson | 7fd7644 | 2009-02-25 14:27:20 +0000 | [diff] [blame] | 13805 | (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT, |
| 13806 | (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT, |
| 13807 | (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT, |
| 13808 | (apedata & APE_FW_VERSION_BLDMSK)); |
| 13809 | } |
| 13810 | |
Matt Carlson | acd9c11 | 2009-02-25 14:26:33 +0000 | [diff] [blame] | 13811 | static void __devinit tg3_read_fw_ver(struct tg3 *tp) |
| 13812 | { |
| 13813 | u32 val; |
Matt Carlson | 75f9936 | 2010-04-05 10:19:24 +0000 | [diff] [blame] | 13814 | bool vpd_vers = false; |
| 13815 | |
| 13816 | if (tp->fw_ver[0] != 0) |
| 13817 | vpd_vers = true; |
Matt Carlson | acd9c11 | 2009-02-25 14:26:33 +0000 | [diff] [blame] | 13818 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13819 | if (tg3_flag(tp, NO_NVRAM)) { |
Matt Carlson | 75f9936 | 2010-04-05 10:19:24 +0000 | [diff] [blame] | 13820 | strcat(tp->fw_ver, "sb"); |
Matt Carlson | df259d8 | 2009-04-20 06:57:14 +0000 | [diff] [blame] | 13821 | return; |
| 13822 | } |
| 13823 | |
Matt Carlson | acd9c11 | 2009-02-25 14:26:33 +0000 | [diff] [blame] | 13824 | if (tg3_nvram_read(tp, 0, &val)) |
| 13825 | return; |
| 13826 | |
| 13827 | if (val == TG3_EEPROM_MAGIC) |
| 13828 | tg3_read_bc_ver(tp); |
| 13829 | else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) |
| 13830 | tg3_read_sb_ver(tp, val); |
Matt Carlson | a6f6cb1 | 2009-02-25 14:27:43 +0000 | [diff] [blame] | 13831 | else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
| 13832 | tg3_read_hwsb_ver(tp); |
Matt Carlson | acd9c11 | 2009-02-25 14:26:33 +0000 | [diff] [blame] | 13833 | else |
| 13834 | return; |
| 13835 | |
Matt Carlson | c9cab24 | 2011-07-13 09:27:27 +0000 | [diff] [blame] | 13836 | if (vpd_vers) |
Matt Carlson | 75f9936 | 2010-04-05 10:19:24 +0000 | [diff] [blame] | 13837 | goto done; |
Matt Carlson | acd9c11 | 2009-02-25 14:26:33 +0000 | [diff] [blame] | 13838 | |
Matt Carlson | c9cab24 | 2011-07-13 09:27:27 +0000 | [diff] [blame] | 13839 | if (tg3_flag(tp, ENABLE_APE)) { |
| 13840 | if (tg3_flag(tp, ENABLE_ASF)) |
| 13841 | tg3_read_dash_ver(tp); |
| 13842 | } else if (tg3_flag(tp, ENABLE_ASF)) { |
| 13843 | tg3_read_mgmtfw_ver(tp); |
| 13844 | } |
Matt Carlson | 9c8a620 | 2007-10-21 16:16:08 -0700 | [diff] [blame] | 13845 | |
Matt Carlson | 75f9936 | 2010-04-05 10:19:24 +0000 | [diff] [blame] | 13846 | done: |
Matt Carlson | 9c8a620 | 2007-10-21 16:16:08 -0700 | [diff] [blame] | 13847 | tp->fw_ver[TG3_VER_SIZE - 1] = 0; |
Michael Chan | c4e6575 | 2006-03-20 22:29:32 -0800 | [diff] [blame] | 13848 | } |
| 13849 | |
Matt Carlson | 7cb32cf | 2010-09-30 10:34:36 +0000 | [diff] [blame] | 13850 | static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) |
| 13851 | { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13852 | if (tg3_flag(tp, LRG_PROD_RING_CAP)) |
Matt Carlson | de9f523 | 2011-04-05 14:22:43 +0000 | [diff] [blame] | 13853 | return TG3_RX_RET_MAX_SIZE_5717; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 13854 | else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) |
Matt Carlson | de9f523 | 2011-04-05 14:22:43 +0000 | [diff] [blame] | 13855 | return TG3_RX_RET_MAX_SIZE_5700; |
Matt Carlson | 7cb32cf | 2010-09-30 10:34:36 +0000 | [diff] [blame] | 13856 | else |
Matt Carlson | de9f523 | 2011-04-05 14:22:43 +0000 | [diff] [blame] | 13857 | return TG3_RX_RET_MAX_SIZE_5705; |
Matt Carlson | 7cb32cf | 2010-09-30 10:34:36 +0000 | [diff] [blame] | 13858 | } |
| 13859 | |
Matt Carlson | 4143470 | 2011-03-09 16:58:22 +0000 | [diff] [blame] | 13860 | static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = { |
Joe Perches | 895950c | 2010-12-21 02:16:08 -0800 | [diff] [blame] | 13861 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) }, |
| 13862 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) }, |
| 13863 | { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) }, |
| 13864 | { }, |
| 13865 | }; |
| 13866 | |
Matt Carlson | 16c7fa7 | 2012-02-13 10:20:10 +0000 | [diff] [blame^] | 13867 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp) |
| 13868 | { |
| 13869 | struct pci_dev *peer; |
| 13870 | unsigned int func, devnr = tp->pdev->devfn & ~7; |
| 13871 | |
| 13872 | for (func = 0; func < 8; func++) { |
| 13873 | peer = pci_get_slot(tp->pdev->bus, devnr | func); |
| 13874 | if (peer && peer != tp->pdev) |
| 13875 | break; |
| 13876 | pci_dev_put(peer); |
| 13877 | } |
| 13878 | /* 5704 can be configured in single-port mode, set peer to |
| 13879 | * tp->pdev in that case. |
| 13880 | */ |
| 13881 | if (!peer) { |
| 13882 | peer = tp->pdev; |
| 13883 | return peer; |
| 13884 | } |
| 13885 | |
| 13886 | /* |
| 13887 | * We don't need to keep the refcount elevated; there's no way |
| 13888 | * to remove one half of this device without removing the other |
| 13889 | */ |
| 13890 | pci_dev_put(peer); |
| 13891 | |
| 13892 | return peer; |
| 13893 | } |
| 13894 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13895 | static int __devinit tg3_get_invariants(struct tg3 *tp) |
| 13896 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13897 | u32 misc_ctrl_reg; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13898 | u32 pci_state_reg, grc_misc_cfg; |
| 13899 | u32 val; |
| 13900 | u16 pci_cmd; |
Matt Carlson | 5e7dfd0 | 2008-11-21 17:18:16 -0800 | [diff] [blame] | 13901 | int err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13902 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13903 | /* Force memory write invalidate off. If we leave it on, |
| 13904 | * then on 5700_BX chips we have to enable a workaround. |
| 13905 | * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary |
| 13906 | * to match the cacheline size. The Broadcom driver have this |
| 13907 | * workaround but turns MWI off all the times so never uses |
| 13908 | * it. This seems to suggest that the workaround is insufficient. |
| 13909 | */ |
| 13910 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); |
| 13911 | pci_cmd &= ~PCI_COMMAND_INVALIDATE; |
| 13912 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); |
| 13913 | |
Matt Carlson | 1682128 | 2011-07-13 09:27:28 +0000 | [diff] [blame] | 13914 | /* Important! -- Make sure register accesses are byteswapped |
| 13915 | * correctly. Also, for those chips that require it, make |
| 13916 | * sure that indirect register accesses are enabled before |
| 13917 | * the first operation. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13918 | */ |
| 13919 | pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, |
| 13920 | &misc_ctrl_reg); |
Matt Carlson | 1682128 | 2011-07-13 09:27:28 +0000 | [diff] [blame] | 13921 | tp->misc_host_ctrl |= (misc_ctrl_reg & |
| 13922 | MISC_HOST_CTRL_CHIPREV); |
| 13923 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, |
| 13924 | tp->misc_host_ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13925 | |
| 13926 | tp->pci_chip_rev_id = (misc_ctrl_reg >> |
| 13927 | MISC_HOST_CTRL_CHIPREV_SHIFT); |
Matt Carlson | 795d01c | 2007-10-07 23:28:17 -0700 | [diff] [blame] | 13928 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) { |
| 13929 | u32 prod_id_asic_rev; |
| 13930 | |
Matt Carlson | 5001e2f | 2009-11-13 13:03:51 +0000 | [diff] [blame] | 13931 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || |
| 13932 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || |
Matt Carlson | d78b59f | 2011-04-05 14:22:46 +0000 | [diff] [blame] | 13933 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || |
| 13934 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) |
Matt Carlson | f6eb9b1 | 2009-09-01 13:19:53 +0000 | [diff] [blame] | 13935 | pci_read_config_dword(tp->pdev, |
| 13936 | TG3PCI_GEN2_PRODID_ASICREV, |
| 13937 | &prod_id_asic_rev); |
Matt Carlson | b703df6 | 2009-12-03 08:36:21 +0000 | [diff] [blame] | 13938 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || |
| 13939 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || |
| 13940 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || |
| 13941 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || |
| 13942 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || |
Matt Carlson | 55086ad | 2011-12-14 11:09:59 +0000 | [diff] [blame] | 13943 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || |
| 13944 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 || |
| 13945 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 || |
| 13946 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 || |
| 13947 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) |
Matt Carlson | b703df6 | 2009-12-03 08:36:21 +0000 | [diff] [blame] | 13948 | pci_read_config_dword(tp->pdev, |
| 13949 | TG3PCI_GEN15_PRODID_ASICREV, |
| 13950 | &prod_id_asic_rev); |
Matt Carlson | f6eb9b1 | 2009-09-01 13:19:53 +0000 | [diff] [blame] | 13951 | else |
| 13952 | pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV, |
| 13953 | &prod_id_asic_rev); |
| 13954 | |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 13955 | tp->pci_chip_rev_id = prod_id_asic_rev; |
Matt Carlson | 795d01c | 2007-10-07 23:28:17 -0700 | [diff] [blame] | 13956 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13957 | |
Michael Chan | ff645be | 2005-04-21 17:09:53 -0700 | [diff] [blame] | 13958 | /* Wrong chip ID in 5752 A0. This code can be removed later |
| 13959 | * as A0 is not in production. |
| 13960 | */ |
| 13961 | if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) |
| 13962 | tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; |
| 13963 | |
Michael Chan | 6892914 | 2005-08-09 20:17:14 -0700 | [diff] [blame] | 13964 | /* If we have 5702/03 A1 or A2 on certain ICH chipsets, |
| 13965 | * we need to disable memory and use config. cycles |
| 13966 | * only to access all registers. The 5702/03 chips |
| 13967 | * can mistakenly decode the special cycles from the |
| 13968 | * ICH chipsets as memory write cycles, causing corruption |
| 13969 | * of register and memory space. Only certain ICH bridges |
| 13970 | * will drive special cycles with non-zero data during the |
| 13971 | * address phase which can fall within the 5703's address |
| 13972 | * range. This is not an ICH bug as the PCI spec allows |
| 13973 | * non-zero address during special cycles. However, only |
| 13974 | * these ICH bridges are known to drive non-zero addresses |
| 13975 | * during special cycles. |
| 13976 | * |
| 13977 | * Since special cycles do not cross PCI bridges, we only |
| 13978 | * enable this workaround if the 5703 is on the secondary |
| 13979 | * bus of these ICH bridges. |
| 13980 | */ |
| 13981 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) || |
| 13982 | (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) { |
| 13983 | static struct tg3_dev_id { |
| 13984 | u32 vendor; |
| 13985 | u32 device; |
| 13986 | u32 rev; |
| 13987 | } ich_chipsets[] = { |
| 13988 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8, |
| 13989 | PCI_ANY_ID }, |
| 13990 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8, |
| 13991 | PCI_ANY_ID }, |
| 13992 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11, |
| 13993 | 0xa }, |
| 13994 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6, |
| 13995 | PCI_ANY_ID }, |
| 13996 | { }, |
| 13997 | }; |
| 13998 | struct tg3_dev_id *pci_id = &ich_chipsets[0]; |
| 13999 | struct pci_dev *bridge = NULL; |
| 14000 | |
| 14001 | while (pci_id->vendor != 0) { |
| 14002 | bridge = pci_get_device(pci_id->vendor, pci_id->device, |
| 14003 | bridge); |
| 14004 | if (!bridge) { |
| 14005 | pci_id++; |
| 14006 | continue; |
| 14007 | } |
| 14008 | if (pci_id->rev != PCI_ANY_ID) { |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 14009 | if (bridge->revision > pci_id->rev) |
Michael Chan | 6892914 | 2005-08-09 20:17:14 -0700 | [diff] [blame] | 14010 | continue; |
| 14011 | } |
| 14012 | if (bridge->subordinate && |
| 14013 | (bridge->subordinate->number == |
| 14014 | tp->pdev->bus->number)) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14015 | tg3_flag_set(tp, ICH_WORKAROUND); |
Michael Chan | 6892914 | 2005-08-09 20:17:14 -0700 | [diff] [blame] | 14016 | pci_dev_put(bridge); |
| 14017 | break; |
| 14018 | } |
| 14019 | } |
| 14020 | } |
| 14021 | |
Matt Carlson | 6ff6f81 | 2011-05-19 12:12:54 +0000 | [diff] [blame] | 14022 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { |
Matt Carlson | 41588ba | 2008-04-19 18:12:33 -0700 | [diff] [blame] | 14023 | static struct tg3_dev_id { |
| 14024 | u32 vendor; |
| 14025 | u32 device; |
| 14026 | } bridge_chipsets[] = { |
| 14027 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 }, |
| 14028 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 }, |
| 14029 | { }, |
| 14030 | }; |
| 14031 | struct tg3_dev_id *pci_id = &bridge_chipsets[0]; |
| 14032 | struct pci_dev *bridge = NULL; |
| 14033 | |
| 14034 | while (pci_id->vendor != 0) { |
| 14035 | bridge = pci_get_device(pci_id->vendor, |
| 14036 | pci_id->device, |
| 14037 | bridge); |
| 14038 | if (!bridge) { |
| 14039 | pci_id++; |
| 14040 | continue; |
| 14041 | } |
| 14042 | if (bridge->subordinate && |
| 14043 | (bridge->subordinate->number <= |
| 14044 | tp->pdev->bus->number) && |
| 14045 | (bridge->subordinate->subordinate >= |
| 14046 | tp->pdev->bus->number)) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14047 | tg3_flag_set(tp, 5701_DMA_BUG); |
Matt Carlson | 41588ba | 2008-04-19 18:12:33 -0700 | [diff] [blame] | 14048 | pci_dev_put(bridge); |
| 14049 | break; |
| 14050 | } |
| 14051 | } |
| 14052 | } |
| 14053 | |
Michael Chan | 4a29cc2 | 2006-03-19 13:21:12 -0800 | [diff] [blame] | 14054 | /* The EPB bridge inside 5714, 5715, and 5780 cannot support |
| 14055 | * DMA addresses > 40-bit. This bridge may have other additional |
| 14056 | * 57xx devices behind it in some 4-port NIC designs for example. |
| 14057 | * Any tg3 device found behind the bridge will also need the 40-bit |
| 14058 | * DMA workaround. |
| 14059 | */ |
Michael Chan | a4e2b34 | 2005-10-26 15:46:52 -0700 | [diff] [blame] | 14060 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || |
| 14061 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14062 | tg3_flag_set(tp, 5780_CLASS); |
| 14063 | tg3_flag_set(tp, 40BIT_DMA_BUG); |
Michael Chan | 4cf78e4 | 2005-07-25 12:29:19 -0700 | [diff] [blame] | 14064 | tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); |
Matt Carlson | 859a58879 | 2010-04-05 10:19:28 +0000 | [diff] [blame] | 14065 | } else { |
Michael Chan | 4a29cc2 | 2006-03-19 13:21:12 -0800 | [diff] [blame] | 14066 | struct pci_dev *bridge = NULL; |
| 14067 | |
| 14068 | do { |
| 14069 | bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, |
| 14070 | PCI_DEVICE_ID_SERVERWORKS_EPB, |
| 14071 | bridge); |
| 14072 | if (bridge && bridge->subordinate && |
| 14073 | (bridge->subordinate->number <= |
| 14074 | tp->pdev->bus->number) && |
| 14075 | (bridge->subordinate->subordinate >= |
| 14076 | tp->pdev->bus->number)) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14077 | tg3_flag_set(tp, 40BIT_DMA_BUG); |
Michael Chan | 4a29cc2 | 2006-03-19 13:21:12 -0800 | [diff] [blame] | 14078 | pci_dev_put(bridge); |
| 14079 | break; |
| 14080 | } |
| 14081 | } while (bridge); |
| 14082 | } |
Michael Chan | 4cf78e4 | 2005-07-25 12:29:19 -0700 | [diff] [blame] | 14083 | |
Matt Carlson | f6eb9b1 | 2009-09-01 13:19:53 +0000 | [diff] [blame] | 14084 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
Matt Carlson | 3a1e19d | 2011-07-13 09:27:32 +0000 | [diff] [blame] | 14085 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) |
Michael Chan | 7544b09 | 2007-05-05 13:08:32 -0700 | [diff] [blame] | 14086 | tp->pdev_peer = tg3_find_peer(tp); |
| 14087 | |
Matt Carlson | c885e82 | 2010-08-02 11:25:57 +0000 | [diff] [blame] | 14088 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
Matt Carlson | d78b59f | 2011-04-05 14:22:46 +0000 | [diff] [blame] | 14089 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
| 14090 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14091 | tg3_flag_set(tp, 5717_PLUS); |
Matt Carlson | 0a58d66 | 2011-04-05 14:22:45 +0000 | [diff] [blame] | 14092 | |
| 14093 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 || |
Matt Carlson | 55086ad | 2011-12-14 11:09:59 +0000 | [diff] [blame] | 14094 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) |
| 14095 | tg3_flag_set(tp, 57765_CLASS); |
| 14096 | |
| 14097 | if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS)) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14098 | tg3_flag_set(tp, 57765_PLUS); |
Matt Carlson | c885e82 | 2010-08-02 11:25:57 +0000 | [diff] [blame] | 14099 | |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 14100 | /* Intentionally exclude ASIC_REV_5906 */ |
| 14101 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
Michael Chan | d9ab5ad | 2006-03-20 22:27:35 -0800 | [diff] [blame] | 14102 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
Matt Carlson | d30cdd2 | 2007-10-07 23:28:35 -0700 | [diff] [blame] | 14103 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
Matt Carlson | 9936bcf | 2007-10-10 18:03:07 -0700 | [diff] [blame] | 14104 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
Matt Carlson | 57e6983 | 2008-05-25 23:48:31 -0700 | [diff] [blame] | 14105 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
Matt Carlson | f6eb9b1 | 2009-09-01 13:19:53 +0000 | [diff] [blame] | 14106 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14107 | tg3_flag(tp, 57765_PLUS)) |
| 14108 | tg3_flag_set(tp, 5755_PLUS); |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 14109 | |
| 14110 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || |
| 14111 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
Michael Chan | b5d3772 | 2006-09-27 16:06:21 -0700 | [diff] [blame] | 14112 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14113 | tg3_flag(tp, 5755_PLUS) || |
| 14114 | tg3_flag(tp, 5780_CLASS)) |
| 14115 | tg3_flag_set(tp, 5750_PLUS); |
John W. Linville | 6708e5c | 2005-04-21 17:00:52 -0700 | [diff] [blame] | 14116 | |
Matt Carlson | 6ff6f81 | 2011-05-19 12:12:54 +0000 | [diff] [blame] | 14117 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14118 | tg3_flag(tp, 5750_PLUS)) |
| 14119 | tg3_flag_set(tp, 5705_PLUS); |
John W. Linville | 1b440c56 | 2005-04-21 17:03:18 -0700 | [diff] [blame] | 14120 | |
Matt Carlson | 507399f | 2009-11-13 13:03:37 +0000 | [diff] [blame] | 14121 | /* Determine TSO capabilities */ |
Matt Carlson | a051294 | 2011-07-27 14:20:54 +0000 | [diff] [blame] | 14122 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) |
Matt Carlson | 4d163b7 | 2011-01-25 15:58:48 +0000 | [diff] [blame] | 14123 | ; /* Do nothing. HW bug. */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14124 | else if (tg3_flag(tp, 57765_PLUS)) |
| 14125 | tg3_flag_set(tp, HW_TSO_3); |
| 14126 | else if (tg3_flag(tp, 5755_PLUS) || |
Matt Carlson | e849cdc | 2009-11-13 13:03:38 +0000 | [diff] [blame] | 14127 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14128 | tg3_flag_set(tp, HW_TSO_2); |
| 14129 | else if (tg3_flag(tp, 5750_PLUS)) { |
| 14130 | tg3_flag_set(tp, HW_TSO_1); |
| 14131 | tg3_flag_set(tp, TSO_BUG); |
Matt Carlson | 507399f | 2009-11-13 13:03:37 +0000 | [diff] [blame] | 14132 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 && |
| 14133 | tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14134 | tg3_flag_clear(tp, TSO_BUG); |
Matt Carlson | 507399f | 2009-11-13 13:03:37 +0000 | [diff] [blame] | 14135 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
| 14136 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && |
| 14137 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14138 | tg3_flag_set(tp, TSO_BUG); |
Matt Carlson | 507399f | 2009-11-13 13:03:37 +0000 | [diff] [blame] | 14139 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) |
| 14140 | tp->fw_needed = FIRMWARE_TG3TSO5; |
| 14141 | else |
| 14142 | tp->fw_needed = FIRMWARE_TG3TSO; |
| 14143 | } |
| 14144 | |
Matt Carlson | dabc5c6 | 2011-05-19 12:12:52 +0000 | [diff] [blame] | 14145 | /* Selectively allow TSO based on operating conditions */ |
Matt Carlson | 6ff6f81 | 2011-05-19 12:12:54 +0000 | [diff] [blame] | 14146 | if (tg3_flag(tp, HW_TSO_1) || |
| 14147 | tg3_flag(tp, HW_TSO_2) || |
| 14148 | tg3_flag(tp, HW_TSO_3) || |
Matt Carlson | cf9ecf4 | 2011-11-28 09:41:03 +0000 | [diff] [blame] | 14149 | tp->fw_needed) { |
| 14150 | /* For firmware TSO, assume ASF is disabled. |
| 14151 | * We'll disable TSO later if we discover ASF |
| 14152 | * is enabled in tg3_get_eeprom_hw_cfg(). |
| 14153 | */ |
Matt Carlson | dabc5c6 | 2011-05-19 12:12:52 +0000 | [diff] [blame] | 14154 | tg3_flag_set(tp, TSO_CAPABLE); |
Matt Carlson | cf9ecf4 | 2011-11-28 09:41:03 +0000 | [diff] [blame] | 14155 | } else { |
Matt Carlson | dabc5c6 | 2011-05-19 12:12:52 +0000 | [diff] [blame] | 14156 | tg3_flag_clear(tp, TSO_CAPABLE); |
| 14157 | tg3_flag_clear(tp, TSO_BUG); |
| 14158 | tp->fw_needed = NULL; |
| 14159 | } |
| 14160 | |
| 14161 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) |
| 14162 | tp->fw_needed = FIRMWARE_TG3; |
| 14163 | |
Matt Carlson | 507399f | 2009-11-13 13:03:37 +0000 | [diff] [blame] | 14164 | tp->irq_max = 1; |
| 14165 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14166 | if (tg3_flag(tp, 5750_PLUS)) { |
| 14167 | tg3_flag_set(tp, SUPPORT_MSI); |
Michael Chan | 7544b09 | 2007-05-05 13:08:32 -0700 | [diff] [blame] | 14168 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || |
| 14169 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || |
| 14170 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && |
| 14171 | tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && |
| 14172 | tp->pdev_peer == tp->pdev)) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14173 | tg3_flag_clear(tp, SUPPORT_MSI); |
Michael Chan | 7544b09 | 2007-05-05 13:08:32 -0700 | [diff] [blame] | 14174 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14175 | if (tg3_flag(tp, 5755_PLUS) || |
Michael Chan | b5d3772 | 2006-09-27 16:06:21 -0700 | [diff] [blame] | 14176 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14177 | tg3_flag_set(tp, 1SHOT_MSI); |
Michael Chan | 52c0fd8 | 2006-06-29 20:15:54 -0700 | [diff] [blame] | 14178 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14179 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14180 | if (tg3_flag(tp, 57765_PLUS)) { |
| 14181 | tg3_flag_set(tp, SUPPORT_MSIX); |
Matt Carlson | 507399f | 2009-11-13 13:03:37 +0000 | [diff] [blame] | 14182 | tp->irq_max = TG3_IRQ_MAX_VECS; |
Matt Carlson | 9041547 | 2011-12-16 13:33:23 +0000 | [diff] [blame] | 14183 | tg3_rss_init_dflt_indir_tbl(tp); |
Matt Carlson | 507399f | 2009-11-13 13:03:37 +0000 | [diff] [blame] | 14184 | } |
Matt Carlson | f6eb9b1 | 2009-09-01 13:19:53 +0000 | [diff] [blame] | 14185 | } |
Matt Carlson | 0e1406d | 2009-11-02 12:33:33 +0000 | [diff] [blame] | 14186 | |
Matt Carlson | 2ffcc98 | 2011-05-19 12:12:44 +0000 | [diff] [blame] | 14187 | if (tg3_flag(tp, 5755_PLUS)) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14188 | tg3_flag_set(tp, SHORT_DMA_BUG); |
Matt Carlson | f6eb9b1 | 2009-09-01 13:19:53 +0000 | [diff] [blame] | 14189 | |
Matt Carlson | e31aa98 | 2011-07-27 14:20:53 +0000 | [diff] [blame] | 14190 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) |
Matt Carlson | a4cb428 | 2011-12-14 11:09:58 +0000 | [diff] [blame] | 14191 | tp->dma_limit = TG3_TX_BD_DMA_MAX_4K; |
Matt Carlson | 55086ad | 2011-12-14 11:09:59 +0000 | [diff] [blame] | 14192 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) |
| 14193 | tp->dma_limit = TG3_TX_BD_DMA_MAX_2K; |
Matt Carlson | e31aa98 | 2011-07-27 14:20:53 +0000 | [diff] [blame] | 14194 | |
Matt Carlson | fa6b2aa | 2011-11-21 15:01:19 +0000 | [diff] [blame] | 14195 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
| 14196 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
| 14197 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14198 | tg3_flag_set(tp, LRG_PROD_RING_CAP); |
Matt Carlson | de9f523 | 2011-04-05 14:22:43 +0000 | [diff] [blame] | 14199 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14200 | if (tg3_flag(tp, 57765_PLUS) && |
Matt Carlson | a051294 | 2011-07-27 14:20:54 +0000 | [diff] [blame] | 14201 | tp->pci_chip_rev_id != CHIPREV_ID_5719_A0) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14202 | tg3_flag_set(tp, USE_JUMBO_BDFLAG); |
Matt Carlson | b703df6 | 2009-12-03 08:36:21 +0000 | [diff] [blame] | 14203 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14204 | if (!tg3_flag(tp, 5705_PLUS) || |
| 14205 | tg3_flag(tp, 5780_CLASS) || |
| 14206 | tg3_flag(tp, USE_JUMBO_BDFLAG)) |
| 14207 | tg3_flag_set(tp, JUMBO_CAPABLE); |
Michael Chan | 0f893dc | 2005-07-25 12:30:38 -0700 | [diff] [blame] | 14208 | |
Matt Carlson | 52f4490 | 2008-11-21 17:17:04 -0800 | [diff] [blame] | 14209 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, |
| 14210 | &pci_state_reg); |
| 14211 | |
Jon Mason | 708ebb3 | 2011-06-27 12:56:50 +0000 | [diff] [blame] | 14212 | if (pci_is_pcie(tp->pdev)) { |
Matt Carlson | 5e7dfd0 | 2008-11-21 17:18:16 -0800 | [diff] [blame] | 14213 | u16 lnkctl; |
| 14214 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14215 | tg3_flag_set(tp, PCI_EXPRESS); |
Matt Carlson | 5f5c51e | 2007-11-12 21:19:37 -0800 | [diff] [blame] | 14216 | |
Matt Carlson | 2c55a3d | 2011-11-28 09:41:04 +0000 | [diff] [blame] | 14217 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) { |
| 14218 | int readrq = pcie_get_readrq(tp->pdev); |
| 14219 | if (readrq > 2048) |
| 14220 | pcie_set_readrq(tp->pdev, 2048); |
| 14221 | } |
Matt Carlson | 5f5c51e | 2007-11-12 21:19:37 -0800 | [diff] [blame] | 14222 | |
Matt Carlson | 5e7dfd0 | 2008-11-21 17:18:16 -0800 | [diff] [blame] | 14223 | pci_read_config_word(tp->pdev, |
Jon Mason | 708ebb3 | 2011-06-27 12:56:50 +0000 | [diff] [blame] | 14224 | pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL, |
Matt Carlson | 5e7dfd0 | 2008-11-21 17:18:16 -0800 | [diff] [blame] | 14225 | &lnkctl); |
| 14226 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { |
Matt Carlson | 7196cd6 | 2011-05-19 16:02:44 +0000 | [diff] [blame] | 14227 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
| 14228 | ASIC_REV_5906) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14229 | tg3_flag_clear(tp, HW_TSO_2); |
Matt Carlson | dabc5c6 | 2011-05-19 12:12:52 +0000 | [diff] [blame] | 14230 | tg3_flag_clear(tp, TSO_CAPABLE); |
Matt Carlson | 7196cd6 | 2011-05-19 16:02:44 +0000 | [diff] [blame] | 14231 | } |
Matt Carlson | 5e7dfd0 | 2008-11-21 17:18:16 -0800 | [diff] [blame] | 14232 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 14233 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
Matt Carlson | 9cf74eb | 2009-04-20 06:58:27 +0000 | [diff] [blame] | 14234 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || |
| 14235 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14236 | tg3_flag_set(tp, CLKREQ_BUG); |
Matt Carlson | 614b059 | 2010-01-20 16:58:02 +0000 | [diff] [blame] | 14237 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14238 | tg3_flag_set(tp, L1PLLPD_EN); |
Michael Chan | c7835a7 | 2006-11-15 21:14:42 -0800 | [diff] [blame] | 14239 | } |
Matt Carlson | 52f4490 | 2008-11-21 17:17:04 -0800 | [diff] [blame] | 14240 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
Jon Mason | 708ebb3 | 2011-06-27 12:56:50 +0000 | [diff] [blame] | 14241 | /* BCM5785 devices are effectively PCIe devices, and should |
| 14242 | * follow PCIe codepaths, but do not have a PCIe capabilities |
| 14243 | * section. |
Matt Carlson | 93a700a | 2011-08-31 11:44:54 +0000 | [diff] [blame] | 14244 | */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14245 | tg3_flag_set(tp, PCI_EXPRESS); |
| 14246 | } else if (!tg3_flag(tp, 5705_PLUS) || |
| 14247 | tg3_flag(tp, 5780_CLASS)) { |
Matt Carlson | 52f4490 | 2008-11-21 17:17:04 -0800 | [diff] [blame] | 14248 | tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); |
| 14249 | if (!tp->pcix_cap) { |
Matt Carlson | 2445e46 | 2010-04-05 10:19:21 +0000 | [diff] [blame] | 14250 | dev_err(&tp->pdev->dev, |
| 14251 | "Cannot find PCI-X capability, aborting\n"); |
Matt Carlson | 52f4490 | 2008-11-21 17:17:04 -0800 | [diff] [blame] | 14252 | return -EIO; |
| 14253 | } |
| 14254 | |
| 14255 | if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE)) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14256 | tg3_flag_set(tp, PCIX_MODE); |
Matt Carlson | 52f4490 | 2008-11-21 17:17:04 -0800 | [diff] [blame] | 14257 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14258 | |
Michael Chan | 399de50 | 2005-10-03 14:02:39 -0700 | [diff] [blame] | 14259 | /* If we have an AMD 762 or VIA K8T800 chipset, write |
| 14260 | * reordering to the mailbox registers done by the host |
| 14261 | * controller can cause major troubles. We read back from |
| 14262 | * every mailbox register write to force the writes to be |
| 14263 | * posted to the chip in order. |
| 14264 | */ |
Matt Carlson | 4143470 | 2011-03-09 16:58:22 +0000 | [diff] [blame] | 14265 | if (pci_dev_present(tg3_write_reorder_chipsets) && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14266 | !tg3_flag(tp, PCI_EXPRESS)) |
| 14267 | tg3_flag_set(tp, MBOX_WRITE_REORDER); |
Michael Chan | 399de50 | 2005-10-03 14:02:39 -0700 | [diff] [blame] | 14268 | |
Matt Carlson | 69fc405 | 2008-12-21 20:19:57 -0800 | [diff] [blame] | 14269 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, |
| 14270 | &tp->pci_cacheline_sz); |
| 14271 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, |
| 14272 | &tp->pci_lat_timer); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14273 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && |
| 14274 | tp->pci_lat_timer < 64) { |
| 14275 | tp->pci_lat_timer = 64; |
Matt Carlson | 69fc405 | 2008-12-21 20:19:57 -0800 | [diff] [blame] | 14276 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, |
| 14277 | tp->pci_lat_timer); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14278 | } |
| 14279 | |
Matt Carlson | 1682128 | 2011-07-13 09:27:28 +0000 | [diff] [blame] | 14280 | /* Important! -- It is critical that the PCI-X hw workaround |
| 14281 | * situation is decided before the first MMIO register access. |
| 14282 | */ |
Matt Carlson | 52f4490 | 2008-11-21 17:17:04 -0800 | [diff] [blame] | 14283 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { |
| 14284 | /* 5700 BX chips need to have their TX producer index |
| 14285 | * mailboxes written twice to workaround a bug. |
| 14286 | */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14287 | tg3_flag_set(tp, TXD_MBOX_HWBUG); |
Matt Carlson | 9974a35 | 2007-10-07 23:27:28 -0700 | [diff] [blame] | 14288 | |
Matt Carlson | 52f4490 | 2008-11-21 17:17:04 -0800 | [diff] [blame] | 14289 | /* If we are in PCI-X mode, enable register write workaround. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14290 | * |
| 14291 | * The workaround is to use indirect register accesses |
| 14292 | * for all chip writes not to mailbox registers. |
| 14293 | */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14294 | if (tg3_flag(tp, PCIX_MODE)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14295 | u32 pm_reg; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14296 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14297 | tg3_flag_set(tp, PCIX_TARGET_HWBUG); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14298 | |
| 14299 | /* The chip can have it's power management PCI config |
| 14300 | * space registers clobbered due to this bug. |
| 14301 | * So explicitly force the chip into D0 here. |
| 14302 | */ |
Matt Carlson | 9974a35 | 2007-10-07 23:27:28 -0700 | [diff] [blame] | 14303 | pci_read_config_dword(tp->pdev, |
| 14304 | tp->pm_cap + PCI_PM_CTRL, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14305 | &pm_reg); |
| 14306 | pm_reg &= ~PCI_PM_CTRL_STATE_MASK; |
| 14307 | pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; |
Matt Carlson | 9974a35 | 2007-10-07 23:27:28 -0700 | [diff] [blame] | 14308 | pci_write_config_dword(tp->pdev, |
| 14309 | tp->pm_cap + PCI_PM_CTRL, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14310 | pm_reg); |
| 14311 | |
| 14312 | /* Also, force SERR#/PERR# in PCI command. */ |
| 14313 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); |
| 14314 | pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; |
| 14315 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); |
| 14316 | } |
| 14317 | } |
| 14318 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14319 | if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14320 | tg3_flag_set(tp, PCI_HIGH_SPEED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14321 | if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14322 | tg3_flag_set(tp, PCI_32BIT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14323 | |
| 14324 | /* Chip-specific fixup from Broadcom driver */ |
| 14325 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && |
| 14326 | (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { |
| 14327 | pci_state_reg |= PCISTATE_RETRY_SAME_DMA; |
| 14328 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); |
| 14329 | } |
| 14330 | |
Michael Chan | 1ee582d | 2005-08-09 20:16:46 -0700 | [diff] [blame] | 14331 | /* Default fast path register access methods */ |
Michael Chan | 2009493 | 2005-08-09 20:16:32 -0700 | [diff] [blame] | 14332 | tp->read32 = tg3_read32; |
Michael Chan | 1ee582d | 2005-08-09 20:16:46 -0700 | [diff] [blame] | 14333 | tp->write32 = tg3_write32; |
Michael Chan | 09ee929 | 2005-08-09 20:17:00 -0700 | [diff] [blame] | 14334 | tp->read32_mbox = tg3_read32; |
Michael Chan | 2009493 | 2005-08-09 20:16:32 -0700 | [diff] [blame] | 14335 | tp->write32_mbox = tg3_write32; |
Michael Chan | 1ee582d | 2005-08-09 20:16:46 -0700 | [diff] [blame] | 14336 | tp->write32_tx_mbox = tg3_write32; |
| 14337 | tp->write32_rx_mbox = tg3_write32; |
| 14338 | |
| 14339 | /* Various workaround register access methods */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14340 | if (tg3_flag(tp, PCIX_TARGET_HWBUG)) |
Michael Chan | 1ee582d | 2005-08-09 20:16:46 -0700 | [diff] [blame] | 14341 | tp->write32 = tg3_write_indirect_reg32; |
Matt Carlson | 98efd8a | 2007-05-05 12:47:25 -0700 | [diff] [blame] | 14342 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14343 | (tg3_flag(tp, PCI_EXPRESS) && |
Matt Carlson | 98efd8a | 2007-05-05 12:47:25 -0700 | [diff] [blame] | 14344 | tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { |
| 14345 | /* |
| 14346 | * Back to back register writes can cause problems on these |
| 14347 | * chips, the workaround is to read back all reg writes |
| 14348 | * except those to mailbox regs. |
| 14349 | * |
| 14350 | * See tg3_write_indirect_reg32(). |
| 14351 | */ |
Michael Chan | 1ee582d | 2005-08-09 20:16:46 -0700 | [diff] [blame] | 14352 | tp->write32 = tg3_write_flush_reg32; |
Matt Carlson | 98efd8a | 2007-05-05 12:47:25 -0700 | [diff] [blame] | 14353 | } |
| 14354 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14355 | if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) { |
Michael Chan | 1ee582d | 2005-08-09 20:16:46 -0700 | [diff] [blame] | 14356 | tp->write32_tx_mbox = tg3_write32_tx_mbox; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14357 | if (tg3_flag(tp, MBOX_WRITE_REORDER)) |
Michael Chan | 1ee582d | 2005-08-09 20:16:46 -0700 | [diff] [blame] | 14358 | tp->write32_rx_mbox = tg3_write_flush_reg32; |
| 14359 | } |
Michael Chan | 2009493 | 2005-08-09 20:16:32 -0700 | [diff] [blame] | 14360 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14361 | if (tg3_flag(tp, ICH_WORKAROUND)) { |
Michael Chan | 6892914 | 2005-08-09 20:17:14 -0700 | [diff] [blame] | 14362 | tp->read32 = tg3_read_indirect_reg32; |
| 14363 | tp->write32 = tg3_write_indirect_reg32; |
| 14364 | tp->read32_mbox = tg3_read_indirect_mbox; |
| 14365 | tp->write32_mbox = tg3_write_indirect_mbox; |
| 14366 | tp->write32_tx_mbox = tg3_write_indirect_mbox; |
| 14367 | tp->write32_rx_mbox = tg3_write_indirect_mbox; |
| 14368 | |
| 14369 | iounmap(tp->regs); |
Peter Hagervall | 22abe31 | 2005-09-16 17:01:03 -0700 | [diff] [blame] | 14370 | tp->regs = NULL; |
Michael Chan | 6892914 | 2005-08-09 20:17:14 -0700 | [diff] [blame] | 14371 | |
| 14372 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); |
| 14373 | pci_cmd &= ~PCI_COMMAND_MEMORY; |
| 14374 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); |
| 14375 | } |
Michael Chan | b5d3772 | 2006-09-27 16:06:21 -0700 | [diff] [blame] | 14376 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
| 14377 | tp->read32_mbox = tg3_read32_mbox_5906; |
| 14378 | tp->write32_mbox = tg3_write32_mbox_5906; |
| 14379 | tp->write32_tx_mbox = tg3_write32_mbox_5906; |
| 14380 | tp->write32_rx_mbox = tg3_write32_mbox_5906; |
| 14381 | } |
Michael Chan | 6892914 | 2005-08-09 20:17:14 -0700 | [diff] [blame] | 14382 | |
Michael Chan | bbadf50 | 2006-04-06 21:46:34 -0700 | [diff] [blame] | 14383 | if (tp->write32 == tg3_write_indirect_reg32 || |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14384 | (tg3_flag(tp, PCIX_MODE) && |
Michael Chan | bbadf50 | 2006-04-06 21:46:34 -0700 | [diff] [blame] | 14385 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
David S. Miller | f49639e | 2006-06-09 11:58:36 -0700 | [diff] [blame] | 14386 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14387 | tg3_flag_set(tp, SRAM_USE_CONFIG); |
Michael Chan | bbadf50 | 2006-04-06 21:46:34 -0700 | [diff] [blame] | 14388 | |
Matt Carlson | 1682128 | 2011-07-13 09:27:28 +0000 | [diff] [blame] | 14389 | /* The memory arbiter has to be enabled in order for SRAM accesses |
| 14390 | * to succeed. Normally on powerup the tg3 chip firmware will make |
| 14391 | * sure it is enabled, but other entities such as system netboot |
| 14392 | * code might disable it. |
| 14393 | */ |
| 14394 | val = tr32(MEMARB_MODE); |
| 14395 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); |
| 14396 | |
Matt Carlson | 9dc5e34 | 2011-11-04 09:15:02 +0000 | [diff] [blame] | 14397 | tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; |
| 14398 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
| 14399 | tg3_flag(tp, 5780_CLASS)) { |
| 14400 | if (tg3_flag(tp, PCIX_MODE)) { |
| 14401 | pci_read_config_dword(tp->pdev, |
| 14402 | tp->pcix_cap + PCI_X_STATUS, |
| 14403 | &val); |
| 14404 | tp->pci_fn = val & 0x7; |
| 14405 | } |
| 14406 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { |
| 14407 | tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val); |
| 14408 | if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) == |
| 14409 | NIC_SRAM_CPMUSTAT_SIG) { |
| 14410 | tp->pci_fn = val & TG3_CPMU_STATUS_FMSK_5717; |
| 14411 | tp->pci_fn = tp->pci_fn ? 1 : 0; |
| 14412 | } |
| 14413 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
| 14414 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { |
| 14415 | tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val); |
| 14416 | if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) == |
| 14417 | NIC_SRAM_CPMUSTAT_SIG) { |
| 14418 | tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> |
| 14419 | TG3_CPMU_STATUS_FSHFT_5719; |
| 14420 | } |
Matt Carlson | 69f11c9 | 2011-07-13 09:27:30 +0000 | [diff] [blame] | 14421 | } |
| 14422 | |
Michael Chan | 7d0c41e | 2005-04-21 17:06:20 -0700 | [diff] [blame] | 14423 | /* Get eeprom hw config before calling tg3_set_power_state(). |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14424 | * In particular, the TG3_FLAG_IS_NIC flag must be |
Michael Chan | 7d0c41e | 2005-04-21 17:06:20 -0700 | [diff] [blame] | 14425 | * determined before calling tg3_set_power_state() so that |
| 14426 | * we know whether or not to switch out of Vaux power. |
| 14427 | * When the flag is set, it means that GPIO1 is used for eeprom |
| 14428 | * write protect and also implies that it is a LOM where GPIOs |
| 14429 | * are not used to switch power. |
Jeff Garzik | 6aa20a2 | 2006-09-13 13:24:59 -0400 | [diff] [blame] | 14430 | */ |
Michael Chan | 7d0c41e | 2005-04-21 17:06:20 -0700 | [diff] [blame] | 14431 | tg3_get_eeprom_hw_cfg(tp); |
| 14432 | |
Matt Carlson | cf9ecf4 | 2011-11-28 09:41:03 +0000 | [diff] [blame] | 14433 | if (tp->fw_needed && tg3_flag(tp, ENABLE_ASF)) { |
| 14434 | tg3_flag_clear(tp, TSO_CAPABLE); |
| 14435 | tg3_flag_clear(tp, TSO_BUG); |
| 14436 | tp->fw_needed = NULL; |
| 14437 | } |
| 14438 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14439 | if (tg3_flag(tp, ENABLE_APE)) { |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 14440 | /* Allow reads and writes to the |
| 14441 | * APE register and memory space. |
| 14442 | */ |
| 14443 | pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR | |
Matt Carlson | f92d9dc1 | 2010-06-05 17:24:30 +0000 | [diff] [blame] | 14444 | PCISTATE_ALLOW_APE_SHMEM_WR | |
| 14445 | PCISTATE_ALLOW_APE_PSPACE_WR; |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 14446 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, |
| 14447 | pci_state_reg); |
Matt Carlson | c9cab24 | 2011-07-13 09:27:27 +0000 | [diff] [blame] | 14448 | |
| 14449 | tg3_ape_lock_init(tp); |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 14450 | } |
| 14451 | |
Matt Carlson | 9936bcf | 2007-10-10 18:03:07 -0700 | [diff] [blame] | 14452 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
Matt Carlson | 57e6983 | 2008-05-25 23:48:31 -0700 | [diff] [blame] | 14453 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 14454 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
Matt Carlson | f6eb9b1 | 2009-09-01 13:19:53 +0000 | [diff] [blame] | 14455 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14456 | tg3_flag(tp, 57765_PLUS)) |
| 14457 | tg3_flag_set(tp, CPMU_PRESENT); |
Matt Carlson | d30cdd2 | 2007-10-07 23:28:35 -0700 | [diff] [blame] | 14458 | |
Matt Carlson | 1682128 | 2011-07-13 09:27:28 +0000 | [diff] [blame] | 14459 | /* Set up tp->grc_local_ctrl before calling |
| 14460 | * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high |
| 14461 | * will bring 5700's external PHY out of reset. |
Michael Chan | 314fba3 | 2005-04-21 17:07:04 -0700 | [diff] [blame] | 14462 | * It is also used as eeprom write protect on LOMs. |
| 14463 | */ |
| 14464 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; |
Matt Carlson | 6ff6f81 | 2011-05-19 12:12:54 +0000 | [diff] [blame] | 14465 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14466 | tg3_flag(tp, EEPROM_WRITE_PROT)) |
Michael Chan | 314fba3 | 2005-04-21 17:07:04 -0700 | [diff] [blame] | 14467 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | |
| 14468 | GRC_LCLCTRL_GPIO_OUTPUT1); |
Michael Chan | 3e7d83b | 2005-04-21 17:10:36 -0700 | [diff] [blame] | 14469 | /* Unused GPIO3 must be driven as output on 5752 because there |
| 14470 | * are no pull-up resistors on unused GPIO pins. |
| 14471 | */ |
| 14472 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) |
| 14473 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; |
Michael Chan | 314fba3 | 2005-04-21 17:07:04 -0700 | [diff] [blame] | 14474 | |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 14475 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
Matt Carlson | cb4ed1f | 2010-01-20 16:58:09 +0000 | [diff] [blame] | 14476 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
Matt Carlson | 55086ad | 2011-12-14 11:09:59 +0000 | [diff] [blame] | 14477 | tg3_flag(tp, 57765_CLASS)) |
Michael Chan | af36e6b | 2006-03-23 01:28:06 -0800 | [diff] [blame] | 14478 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; |
| 14479 | |
Matt Carlson | 8d519ab | 2009-04-20 06:58:01 +0000 | [diff] [blame] | 14480 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
| 14481 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { |
Matt Carlson | 5f0c4a3 | 2008-06-09 15:41:12 -0700 | [diff] [blame] | 14482 | /* Turn off the debug UART. */ |
| 14483 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14484 | if (tg3_flag(tp, IS_NIC)) |
Matt Carlson | 5f0c4a3 | 2008-06-09 15:41:12 -0700 | [diff] [blame] | 14485 | /* Keep VMain power. */ |
| 14486 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | |
| 14487 | GRC_LCLCTRL_GPIO_OUTPUT0; |
| 14488 | } |
| 14489 | |
Matt Carlson | 1682128 | 2011-07-13 09:27:28 +0000 | [diff] [blame] | 14490 | /* Switch out of Vaux if it is a NIC */ |
| 14491 | tg3_pwrsrc_switch_to_vmain(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14492 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14493 | /* Derive initial jumbo mode from MTU assigned in |
| 14494 | * ether_setup() via the alloc_etherdev() call |
| 14495 | */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14496 | if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) |
| 14497 | tg3_flag_set(tp, JUMBO_RING_ENABLE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14498 | |
| 14499 | /* Determine WakeOnLan speed to use. */ |
| 14500 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
| 14501 | tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || |
| 14502 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || |
| 14503 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14504 | tg3_flag_clear(tp, WOL_SPEED_100MB); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14505 | } else { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14506 | tg3_flag_set(tp, WOL_SPEED_100MB); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14507 | } |
| 14508 | |
Matt Carlson | 7f97a4b | 2009-08-25 10:10:03 +0000 | [diff] [blame] | 14509 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 14510 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
Matt Carlson | 7f97a4b | 2009-08-25 10:10:03 +0000 | [diff] [blame] | 14511 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14512 | /* A few boards don't want Ethernet@WireSpeed phy feature */ |
Matt Carlson | 6ff6f81 | 2011-05-19 12:12:54 +0000 | [diff] [blame] | 14513 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
| 14514 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14515 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && |
Michael Chan | 747e8f8 | 2005-07-25 12:33:22 -0700 | [diff] [blame] | 14516 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 14517 | (tp->phy_flags & TG3_PHYFLG_IS_FET) || |
| 14518 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
| 14519 | tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14520 | |
| 14521 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || |
| 14522 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX) |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 14523 | tp->phy_flags |= TG3_PHYFLG_ADC_BUG; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14524 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 14525 | tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14526 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14527 | if (tg3_flag(tp, 5705_PLUS) && |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 14528 | !(tp->phy_flags & TG3_PHYFLG_IS_FET) && |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 14529 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
Matt Carlson | f6eb9b1 | 2009-09-01 13:19:53 +0000 | [diff] [blame] | 14530 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14531 | !tg3_flag(tp, 57765_PLUS)) { |
Michael Chan | c424cb2 | 2006-04-29 18:56:34 -0700 | [diff] [blame] | 14532 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
Matt Carlson | d30cdd2 | 2007-10-07 23:28:35 -0700 | [diff] [blame] | 14533 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
Matt Carlson | 9936bcf | 2007-10-10 18:03:07 -0700 | [diff] [blame] | 14534 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
| 14535 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { |
Michael Chan | d4011ad | 2007-02-13 12:17:25 -0800 | [diff] [blame] | 14536 | if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && |
| 14537 | tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 14538 | tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; |
Michael Chan | c1d2a19 | 2007-01-08 19:57:20 -0800 | [diff] [blame] | 14539 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 14540 | tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 14541 | } else |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 14542 | tp->phy_flags |= TG3_PHYFLG_BER_BUG; |
Michael Chan | c424cb2 | 2006-04-29 18:56:34 -0700 | [diff] [blame] | 14543 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14544 | |
Matt Carlson | b2a5c19 | 2008-04-03 21:44:44 -0700 | [diff] [blame] | 14545 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
| 14546 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { |
| 14547 | tp->phy_otp = tg3_read_otp_phycfg(tp); |
| 14548 | if (tp->phy_otp == 0) |
| 14549 | tp->phy_otp = TG3_OTP_DEFAULT; |
| 14550 | } |
| 14551 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14552 | if (tg3_flag(tp, CPMU_PRESENT)) |
Matt Carlson | 8ef2142 | 2008-05-02 16:47:53 -0700 | [diff] [blame] | 14553 | tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; |
| 14554 | else |
| 14555 | tp->mi_mode = MAC_MI_MODE_BASE; |
| 14556 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14557 | tp->coalesce_mode = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14558 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && |
| 14559 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) |
| 14560 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; |
| 14561 | |
Matt Carlson | 4d95847 | 2011-04-20 07:57:35 +0000 | [diff] [blame] | 14562 | /* Set these bits to enable statistics workaround. */ |
| 14563 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
| 14564 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || |
| 14565 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) { |
| 14566 | tp->coalesce_mode |= HOSTCC_MODE_ATTN; |
| 14567 | tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; |
| 14568 | } |
| 14569 | |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 14570 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
| 14571 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14572 | tg3_flag_set(tp, USE_PHYLIB); |
Matt Carlson | 57e6983 | 2008-05-25 23:48:31 -0700 | [diff] [blame] | 14573 | |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 14574 | err = tg3_mdio_init(tp); |
| 14575 | if (err) |
| 14576 | return err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14577 | |
| 14578 | /* Initialize data/descriptor byte/word swapping. */ |
| 14579 | val = tr32(GRC_MODE); |
Matt Carlson | f2096f9 | 2011-04-05 14:22:48 +0000 | [diff] [blame] | 14580 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) |
| 14581 | val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA | |
| 14582 | GRC_MODE_WORD_SWAP_B2HRX_DATA | |
| 14583 | GRC_MODE_B2HRX_ENABLE | |
| 14584 | GRC_MODE_HTX2B_ENABLE | |
| 14585 | GRC_MODE_HOST_STACKUP); |
| 14586 | else |
| 14587 | val &= GRC_MODE_HOST_STACKUP; |
| 14588 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14589 | tw32(GRC_MODE, val | tp->grc_mode); |
| 14590 | |
| 14591 | tg3_switch_clocks(tp); |
| 14592 | |
| 14593 | /* Clear this out for sanity. */ |
| 14594 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); |
| 14595 | |
| 14596 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, |
| 14597 | &pci_state_reg); |
| 14598 | if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14599 | !tg3_flag(tp, PCIX_TARGET_HWBUG)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14600 | u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl); |
| 14601 | |
| 14602 | if (chiprevid == CHIPREV_ID_5701_A0 || |
| 14603 | chiprevid == CHIPREV_ID_5701_B0 || |
| 14604 | chiprevid == CHIPREV_ID_5701_B2 || |
| 14605 | chiprevid == CHIPREV_ID_5701_B5) { |
| 14606 | void __iomem *sram_base; |
| 14607 | |
| 14608 | /* Write some dummy words into the SRAM status block |
| 14609 | * area, see if it reads back correctly. If the return |
| 14610 | * value is bad, force enable the PCIX workaround. |
| 14611 | */ |
| 14612 | sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; |
| 14613 | |
| 14614 | writel(0x00000000, sram_base); |
| 14615 | writel(0x00000000, sram_base + 4); |
| 14616 | writel(0xffffffff, sram_base + 4); |
| 14617 | if (readl(sram_base) != 0x00000000) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14618 | tg3_flag_set(tp, PCIX_TARGET_HWBUG); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14619 | } |
| 14620 | } |
| 14621 | |
| 14622 | udelay(50); |
| 14623 | tg3_nvram_init(tp); |
| 14624 | |
| 14625 | grc_misc_cfg = tr32(GRC_MISC_CFG); |
| 14626 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; |
| 14627 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14628 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
| 14629 | (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || |
| 14630 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14631 | tg3_flag_set(tp, IS_5788); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14632 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14633 | if (!tg3_flag(tp, IS_5788) && |
Matt Carlson | 6ff6f81 | 2011-05-19 12:12:54 +0000 | [diff] [blame] | 14634 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14635 | tg3_flag_set(tp, TAGGED_STATUS); |
| 14636 | if (tg3_flag(tp, TAGGED_STATUS)) { |
David S. Miller | fac9b83 | 2005-05-18 22:46:34 -0700 | [diff] [blame] | 14637 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | |
| 14638 | HOSTCC_MODE_CLRTICK_TXBD); |
| 14639 | |
| 14640 | tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; |
| 14641 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, |
| 14642 | tp->misc_host_ctrl); |
| 14643 | } |
| 14644 | |
Matt Carlson | 3bda125 | 2008-08-15 14:08:22 -0700 | [diff] [blame] | 14645 | /* Preserve the APE MAC_MODE bits */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14646 | if (tg3_flag(tp, ENABLE_APE)) |
Matt Carlson | d2394e6b | 2010-11-24 08:31:47 +0000 | [diff] [blame] | 14647 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; |
Matt Carlson | 3bda125 | 2008-08-15 14:08:22 -0700 | [diff] [blame] | 14648 | else |
Matt Carlson | 6e01b20 | 2011-08-19 13:58:20 +0000 | [diff] [blame] | 14649 | tp->mac_mode = 0; |
Matt Carlson | 3bda125 | 2008-08-15 14:08:22 -0700 | [diff] [blame] | 14650 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14651 | /* these are limited to 10/100 only */ |
| 14652 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && |
| 14653 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || |
| 14654 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
| 14655 | tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && |
| 14656 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 || |
| 14657 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 || |
| 14658 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) || |
| 14659 | (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && |
| 14660 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F || |
Michael Chan | 676917d | 2006-12-07 00:20:22 -0800 | [diff] [blame] | 14661 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F || |
| 14662 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) || |
Matt Carlson | 321d32a | 2008-11-21 17:22:19 -0800 | [diff] [blame] | 14663 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 || |
Matt Carlson | d110114 | 2010-02-17 15:16:55 +0000 | [diff] [blame] | 14664 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || |
| 14665 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 14666 | (tp->phy_flags & TG3_PHYFLG_IS_FET)) |
| 14667 | tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14668 | |
| 14669 | err = tg3_phy_probe(tp); |
| 14670 | if (err) { |
Matt Carlson | 2445e46 | 2010-04-05 10:19:21 +0000 | [diff] [blame] | 14671 | dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14672 | /* ... but do not return immediately ... */ |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 14673 | tg3_mdio_fini(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14674 | } |
| 14675 | |
Matt Carlson | 184b890 | 2010-04-05 10:19:25 +0000 | [diff] [blame] | 14676 | tg3_read_vpd(tp); |
Michael Chan | c4e6575 | 2006-03-20 22:29:32 -0800 | [diff] [blame] | 14677 | tg3_read_fw_ver(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14678 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 14679 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
| 14680 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14681 | } else { |
| 14682 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 14683 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14684 | else |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 14685 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14686 | } |
| 14687 | |
| 14688 | /* 5700 {AX,BX} chips have a broken status block link |
| 14689 | * change bit implementation, so we must use the |
| 14690 | * status register in those cases. |
| 14691 | */ |
| 14692 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14693 | tg3_flag_set(tp, USE_LINKCHG_REG); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14694 | else |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14695 | tg3_flag_clear(tp, USE_LINKCHG_REG); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14696 | |
| 14697 | /* The led_ctrl is set during tg3_phy_probe, here we might |
| 14698 | * have to force the link status polling mechanism based |
| 14699 | * upon subsystem IDs. |
| 14700 | */ |
| 14701 | if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && |
Michael Chan | 007a880d | 2007-05-31 14:49:51 -0700 | [diff] [blame] | 14702 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 14703 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
| 14704 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14705 | tg3_flag_set(tp, USE_LINKCHG_REG); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14706 | } |
| 14707 | |
| 14708 | /* For all SERDES we poll the MAC status register. */ |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 14709 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14710 | tg3_flag_set(tp, POLL_SERDES); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14711 | else |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14712 | tg3_flag_clear(tp, POLL_SERDES); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14713 | |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 14714 | tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN; |
Matt Carlson | d2757fc | 2010-04-12 06:58:27 +0000 | [diff] [blame] | 14715 | tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14716 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14717 | tg3_flag(tp, PCIX_MODE)) { |
Eric Dumazet | 9205fd9 | 2011-11-18 06:47:01 +0000 | [diff] [blame] | 14718 | tp->rx_offset = NET_SKB_PAD; |
Matt Carlson | d2757fc | 2010-04-12 06:58:27 +0000 | [diff] [blame] | 14719 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
Matt Carlson | 9dc7a11 | 2010-04-12 06:58:28 +0000 | [diff] [blame] | 14720 | tp->rx_copy_thresh = ~(u16)0; |
Matt Carlson | d2757fc | 2010-04-12 06:58:27 +0000 | [diff] [blame] | 14721 | #endif |
| 14722 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14723 | |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 14724 | tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; |
| 14725 | tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; |
Matt Carlson | 7cb32cf | 2010-09-30 10:34:36 +0000 | [diff] [blame] | 14726 | tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; |
| 14727 | |
Matt Carlson | 2c49a44 | 2010-09-30 10:34:35 +0000 | [diff] [blame] | 14728 | tp->rx_std_max_post = tp->rx_std_ring_mask + 1; |
Michael Chan | f92905d | 2006-06-29 20:14:29 -0700 | [diff] [blame] | 14729 | |
| 14730 | /* Increment the rx prod index on the rx std ring by at most |
| 14731 | * 8 for these chips to workaround hw errata. |
| 14732 | */ |
| 14733 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || |
| 14734 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
| 14735 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
| 14736 | tp->rx_std_max_post = 8; |
| 14737 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14738 | if (tg3_flag(tp, ASPM_WORKAROUND)) |
Matt Carlson | 8ed5d97 | 2007-05-07 00:25:49 -0700 | [diff] [blame] | 14739 | tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & |
| 14740 | PCIE_PWR_MGMT_L1_THRESH_MSK; |
| 14741 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14742 | return err; |
| 14743 | } |
| 14744 | |
David S. Miller | 49b6e95f | 2007-03-29 01:38:42 -0700 | [diff] [blame] | 14745 | #ifdef CONFIG_SPARC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14746 | static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp) |
| 14747 | { |
| 14748 | struct net_device *dev = tp->dev; |
| 14749 | struct pci_dev *pdev = tp->pdev; |
David S. Miller | 49b6e95f | 2007-03-29 01:38:42 -0700 | [diff] [blame] | 14750 | struct device_node *dp = pci_device_to_OF_node(pdev); |
David S. Miller | 374d4ca | 2007-03-29 01:57:57 -0700 | [diff] [blame] | 14751 | const unsigned char *addr; |
David S. Miller | 49b6e95f | 2007-03-29 01:38:42 -0700 | [diff] [blame] | 14752 | int len; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14753 | |
David S. Miller | 49b6e95f | 2007-03-29 01:38:42 -0700 | [diff] [blame] | 14754 | addr = of_get_property(dp, "local-mac-address", &len); |
| 14755 | if (addr && len == 6) { |
| 14756 | memcpy(dev->dev_addr, addr, 6); |
| 14757 | memcpy(dev->perm_addr, dev->dev_addr, 6); |
| 14758 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14759 | } |
| 14760 | return -ENODEV; |
| 14761 | } |
| 14762 | |
| 14763 | static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp) |
| 14764 | { |
| 14765 | struct net_device *dev = tp->dev; |
| 14766 | |
| 14767 | memcpy(dev->dev_addr, idprom->id_ethaddr, 6); |
John W. Linville | 2ff4369 | 2005-09-12 14:44:20 -0700 | [diff] [blame] | 14768 | memcpy(dev->perm_addr, idprom->id_ethaddr, 6); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14769 | return 0; |
| 14770 | } |
| 14771 | #endif |
| 14772 | |
| 14773 | static int __devinit tg3_get_device_address(struct tg3 *tp) |
| 14774 | { |
| 14775 | struct net_device *dev = tp->dev; |
| 14776 | u32 hi, lo, mac_offset; |
Michael Chan | 008652b | 2006-03-27 23:14:53 -0800 | [diff] [blame] | 14777 | int addr_ok = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14778 | |
David S. Miller | 49b6e95f | 2007-03-29 01:38:42 -0700 | [diff] [blame] | 14779 | #ifdef CONFIG_SPARC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14780 | if (!tg3_get_macaddr_sparc(tp)) |
| 14781 | return 0; |
| 14782 | #endif |
| 14783 | |
| 14784 | mac_offset = 0x7c; |
Matt Carlson | 6ff6f81 | 2011-05-19 12:12:54 +0000 | [diff] [blame] | 14785 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14786 | tg3_flag(tp, 5780_CLASS)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14787 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) |
| 14788 | mac_offset = 0xcc; |
| 14789 | if (tg3_nvram_lock(tp)) |
| 14790 | tw32_f(NVRAM_CMD, NVRAM_CMD_RESET); |
| 14791 | else |
| 14792 | tg3_nvram_unlock(tp); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14793 | } else if (tg3_flag(tp, 5717_PLUS)) { |
Matt Carlson | 69f11c9 | 2011-07-13 09:27:30 +0000 | [diff] [blame] | 14794 | if (tp->pci_fn & 1) |
Matt Carlson | a1b950d | 2009-09-01 13:20:17 +0000 | [diff] [blame] | 14795 | mac_offset = 0xcc; |
Matt Carlson | 69f11c9 | 2011-07-13 09:27:30 +0000 | [diff] [blame] | 14796 | if (tp->pci_fn > 1) |
Matt Carlson | a50d079 | 2010-06-05 17:24:37 +0000 | [diff] [blame] | 14797 | mac_offset += 0x18c; |
Matt Carlson | a1b950d | 2009-09-01 13:20:17 +0000 | [diff] [blame] | 14798 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
Michael Chan | b5d3772 | 2006-09-27 16:06:21 -0700 | [diff] [blame] | 14799 | mac_offset = 0x10; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14800 | |
| 14801 | /* First try to get it from MAC address mailbox. */ |
| 14802 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); |
| 14803 | if ((hi >> 16) == 0x484b) { |
| 14804 | dev->dev_addr[0] = (hi >> 8) & 0xff; |
| 14805 | dev->dev_addr[1] = (hi >> 0) & 0xff; |
| 14806 | |
| 14807 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); |
| 14808 | dev->dev_addr[2] = (lo >> 24) & 0xff; |
| 14809 | dev->dev_addr[3] = (lo >> 16) & 0xff; |
| 14810 | dev->dev_addr[4] = (lo >> 8) & 0xff; |
| 14811 | dev->dev_addr[5] = (lo >> 0) & 0xff; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14812 | |
Michael Chan | 008652b | 2006-03-27 23:14:53 -0800 | [diff] [blame] | 14813 | /* Some old bootcode may report a 0 MAC address in SRAM */ |
| 14814 | addr_ok = is_valid_ether_addr(&dev->dev_addr[0]); |
| 14815 | } |
| 14816 | if (!addr_ok) { |
| 14817 | /* Next, try NVRAM. */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14818 | if (!tg3_flag(tp, NO_NVRAM) && |
Matt Carlson | df259d8 | 2009-04-20 06:57:14 +0000 | [diff] [blame] | 14819 | !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && |
Matt Carlson | 6d348f2 | 2009-02-25 14:25:52 +0000 | [diff] [blame] | 14820 | !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { |
Matt Carlson | 62cedd1 | 2009-04-20 14:52:29 -0700 | [diff] [blame] | 14821 | memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); |
| 14822 | memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo)); |
Michael Chan | 008652b | 2006-03-27 23:14:53 -0800 | [diff] [blame] | 14823 | } |
| 14824 | /* Finally just fetch it out of the MAC control regs. */ |
| 14825 | else { |
| 14826 | hi = tr32(MAC_ADDR_0_HIGH); |
| 14827 | lo = tr32(MAC_ADDR_0_LOW); |
| 14828 | |
| 14829 | dev->dev_addr[5] = lo & 0xff; |
| 14830 | dev->dev_addr[4] = (lo >> 8) & 0xff; |
| 14831 | dev->dev_addr[3] = (lo >> 16) & 0xff; |
| 14832 | dev->dev_addr[2] = (lo >> 24) & 0xff; |
| 14833 | dev->dev_addr[1] = hi & 0xff; |
| 14834 | dev->dev_addr[0] = (hi >> 8) & 0xff; |
| 14835 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14836 | } |
| 14837 | |
| 14838 | if (!is_valid_ether_addr(&dev->dev_addr[0])) { |
David S. Miller | 7582a33 | 2008-03-20 15:53:15 -0700 | [diff] [blame] | 14839 | #ifdef CONFIG_SPARC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14840 | if (!tg3_get_default_macaddr_sparc(tp)) |
| 14841 | return 0; |
| 14842 | #endif |
| 14843 | return -EINVAL; |
| 14844 | } |
John W. Linville | 2ff4369 | 2005-09-12 14:44:20 -0700 | [diff] [blame] | 14845 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14846 | return 0; |
| 14847 | } |
| 14848 | |
David S. Miller | 59e6b43 | 2005-05-18 22:50:10 -0700 | [diff] [blame] | 14849 | #define BOUNDARY_SINGLE_CACHELINE 1 |
| 14850 | #define BOUNDARY_MULTI_CACHELINE 2 |
| 14851 | |
| 14852 | static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) |
| 14853 | { |
| 14854 | int cacheline_size; |
| 14855 | u8 byte; |
| 14856 | int goal; |
| 14857 | |
| 14858 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); |
| 14859 | if (byte == 0) |
| 14860 | cacheline_size = 1024; |
| 14861 | else |
| 14862 | cacheline_size = (int) byte * 4; |
| 14863 | |
| 14864 | /* On 5703 and later chips, the boundary bits have no |
| 14865 | * effect. |
| 14866 | */ |
| 14867 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
| 14868 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14869 | !tg3_flag(tp, PCI_EXPRESS)) |
David S. Miller | 59e6b43 | 2005-05-18 22:50:10 -0700 | [diff] [blame] | 14870 | goto out; |
| 14871 | |
| 14872 | #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) |
| 14873 | goal = BOUNDARY_MULTI_CACHELINE; |
| 14874 | #else |
| 14875 | #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA) |
| 14876 | goal = BOUNDARY_SINGLE_CACHELINE; |
| 14877 | #else |
| 14878 | goal = 0; |
| 14879 | #endif |
| 14880 | #endif |
| 14881 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14882 | if (tg3_flag(tp, 57765_PLUS)) { |
Matt Carlson | cbf9ca6 | 2009-11-13 13:03:40 +0000 | [diff] [blame] | 14883 | val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; |
| 14884 | goto out; |
| 14885 | } |
| 14886 | |
David S. Miller | 59e6b43 | 2005-05-18 22:50:10 -0700 | [diff] [blame] | 14887 | if (!goal) |
| 14888 | goto out; |
| 14889 | |
| 14890 | /* PCI controllers on most RISC systems tend to disconnect |
| 14891 | * when a device tries to burst across a cache-line boundary. |
| 14892 | * Therefore, letting tg3 do so just wastes PCI bandwidth. |
| 14893 | * |
| 14894 | * Unfortunately, for PCI-E there are only limited |
| 14895 | * write-side controls for this, and thus for reads |
| 14896 | * we will still get the disconnects. We'll also waste |
| 14897 | * these PCI cycles for both read and write for chips |
| 14898 | * other than 5700 and 5701 which do not implement the |
| 14899 | * boundary bits. |
| 14900 | */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14901 | if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) { |
David S. Miller | 59e6b43 | 2005-05-18 22:50:10 -0700 | [diff] [blame] | 14902 | switch (cacheline_size) { |
| 14903 | case 16: |
| 14904 | case 32: |
| 14905 | case 64: |
| 14906 | case 128: |
| 14907 | if (goal == BOUNDARY_SINGLE_CACHELINE) { |
| 14908 | val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX | |
| 14909 | DMA_RWCTRL_WRITE_BNDRY_128_PCIX); |
| 14910 | } else { |
| 14911 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | |
| 14912 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); |
| 14913 | } |
| 14914 | break; |
| 14915 | |
| 14916 | case 256: |
| 14917 | val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX | |
| 14918 | DMA_RWCTRL_WRITE_BNDRY_256_PCIX); |
| 14919 | break; |
| 14920 | |
| 14921 | default: |
| 14922 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | |
| 14923 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); |
| 14924 | break; |
Stephen Hemminger | 855e111 | 2008-04-16 16:37:28 -0700 | [diff] [blame] | 14925 | } |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 14926 | } else if (tg3_flag(tp, PCI_EXPRESS)) { |
David S. Miller | 59e6b43 | 2005-05-18 22:50:10 -0700 | [diff] [blame] | 14927 | switch (cacheline_size) { |
| 14928 | case 16: |
| 14929 | case 32: |
| 14930 | case 64: |
| 14931 | if (goal == BOUNDARY_SINGLE_CACHELINE) { |
| 14932 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; |
| 14933 | val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; |
| 14934 | break; |
| 14935 | } |
| 14936 | /* fallthrough */ |
| 14937 | case 128: |
| 14938 | default: |
| 14939 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; |
| 14940 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; |
| 14941 | break; |
Stephen Hemminger | 855e111 | 2008-04-16 16:37:28 -0700 | [diff] [blame] | 14942 | } |
David S. Miller | 59e6b43 | 2005-05-18 22:50:10 -0700 | [diff] [blame] | 14943 | } else { |
| 14944 | switch (cacheline_size) { |
| 14945 | case 16: |
| 14946 | if (goal == BOUNDARY_SINGLE_CACHELINE) { |
| 14947 | val |= (DMA_RWCTRL_READ_BNDRY_16 | |
| 14948 | DMA_RWCTRL_WRITE_BNDRY_16); |
| 14949 | break; |
| 14950 | } |
| 14951 | /* fallthrough */ |
| 14952 | case 32: |
| 14953 | if (goal == BOUNDARY_SINGLE_CACHELINE) { |
| 14954 | val |= (DMA_RWCTRL_READ_BNDRY_32 | |
| 14955 | DMA_RWCTRL_WRITE_BNDRY_32); |
| 14956 | break; |
| 14957 | } |
| 14958 | /* fallthrough */ |
| 14959 | case 64: |
| 14960 | if (goal == BOUNDARY_SINGLE_CACHELINE) { |
| 14961 | val |= (DMA_RWCTRL_READ_BNDRY_64 | |
| 14962 | DMA_RWCTRL_WRITE_BNDRY_64); |
| 14963 | break; |
| 14964 | } |
| 14965 | /* fallthrough */ |
| 14966 | case 128: |
| 14967 | if (goal == BOUNDARY_SINGLE_CACHELINE) { |
| 14968 | val |= (DMA_RWCTRL_READ_BNDRY_128 | |
| 14969 | DMA_RWCTRL_WRITE_BNDRY_128); |
| 14970 | break; |
| 14971 | } |
| 14972 | /* fallthrough */ |
| 14973 | case 256: |
| 14974 | val |= (DMA_RWCTRL_READ_BNDRY_256 | |
| 14975 | DMA_RWCTRL_WRITE_BNDRY_256); |
| 14976 | break; |
| 14977 | case 512: |
| 14978 | val |= (DMA_RWCTRL_READ_BNDRY_512 | |
| 14979 | DMA_RWCTRL_WRITE_BNDRY_512); |
| 14980 | break; |
| 14981 | case 1024: |
| 14982 | default: |
| 14983 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | |
| 14984 | DMA_RWCTRL_WRITE_BNDRY_1024); |
| 14985 | break; |
Stephen Hemminger | 855e111 | 2008-04-16 16:37:28 -0700 | [diff] [blame] | 14986 | } |
David S. Miller | 59e6b43 | 2005-05-18 22:50:10 -0700 | [diff] [blame] | 14987 | } |
| 14988 | |
| 14989 | out: |
| 14990 | return val; |
| 14991 | } |
| 14992 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14993 | static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device) |
| 14994 | { |
| 14995 | struct tg3_internal_buffer_desc test_desc; |
| 14996 | u32 sram_dma_descs; |
| 14997 | int i, ret; |
| 14998 | |
| 14999 | sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE; |
| 15000 | |
| 15001 | tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0); |
| 15002 | tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0); |
| 15003 | tw32(RDMAC_STATUS, 0); |
| 15004 | tw32(WDMAC_STATUS, 0); |
| 15005 | |
| 15006 | tw32(BUFMGR_MODE, 0); |
| 15007 | tw32(FTQ_RESET, 0); |
| 15008 | |
| 15009 | test_desc.addr_hi = ((u64) buf_dma) >> 32; |
| 15010 | test_desc.addr_lo = buf_dma & 0xffffffff; |
| 15011 | test_desc.nic_mbuf = 0x00002100; |
| 15012 | test_desc.len = size; |
| 15013 | |
| 15014 | /* |
| 15015 | * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz |
| 15016 | * the *second* time the tg3 driver was getting loaded after an |
| 15017 | * initial scan. |
| 15018 | * |
| 15019 | * Broadcom tells me: |
| 15020 | * ...the DMA engine is connected to the GRC block and a DMA |
| 15021 | * reset may affect the GRC block in some unpredictable way... |
| 15022 | * The behavior of resets to individual blocks has not been tested. |
| 15023 | * |
| 15024 | * Broadcom noted the GRC reset will also reset all sub-components. |
| 15025 | */ |
| 15026 | if (to_device) { |
| 15027 | test_desc.cqid_sqid = (13 << 8) | 2; |
| 15028 | |
| 15029 | tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE); |
| 15030 | udelay(40); |
| 15031 | } else { |
| 15032 | test_desc.cqid_sqid = (16 << 8) | 7; |
| 15033 | |
| 15034 | tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE); |
| 15035 | udelay(40); |
| 15036 | } |
| 15037 | test_desc.flags = 0x00000005; |
| 15038 | |
| 15039 | for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) { |
| 15040 | u32 val; |
| 15041 | |
| 15042 | val = *(((u32 *)&test_desc) + i); |
| 15043 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, |
| 15044 | sram_dma_descs + (i * sizeof(u32))); |
| 15045 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); |
| 15046 | } |
| 15047 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); |
| 15048 | |
Matt Carlson | 859a58879 | 2010-04-05 10:19:28 +0000 | [diff] [blame] | 15049 | if (to_device) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15050 | tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); |
Matt Carlson | 859a58879 | 2010-04-05 10:19:28 +0000 | [diff] [blame] | 15051 | else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15052 | tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15053 | |
| 15054 | ret = -ENODEV; |
| 15055 | for (i = 0; i < 40; i++) { |
| 15056 | u32 val; |
| 15057 | |
| 15058 | if (to_device) |
| 15059 | val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); |
| 15060 | else |
| 15061 | val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); |
| 15062 | if ((val & 0xffff) == sram_dma_descs) { |
| 15063 | ret = 0; |
| 15064 | break; |
| 15065 | } |
| 15066 | |
| 15067 | udelay(100); |
| 15068 | } |
| 15069 | |
| 15070 | return ret; |
| 15071 | } |
| 15072 | |
David S. Miller | ded7340 | 2005-05-23 13:59:47 -0700 | [diff] [blame] | 15073 | #define TEST_BUFFER_SIZE 0x2000 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15074 | |
Matt Carlson | 4143470 | 2011-03-09 16:58:22 +0000 | [diff] [blame] | 15075 | static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = { |
Joe Perches | 895950c | 2010-12-21 02:16:08 -0800 | [diff] [blame] | 15076 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) }, |
| 15077 | { }, |
| 15078 | }; |
| 15079 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15080 | static int __devinit tg3_test_dma(struct tg3 *tp) |
| 15081 | { |
| 15082 | dma_addr_t buf_dma; |
David S. Miller | 59e6b43 | 2005-05-18 22:50:10 -0700 | [diff] [blame] | 15083 | u32 *buf, saved_dma_rwctrl; |
Matt Carlson | cbf9ca6 | 2009-11-13 13:03:40 +0000 | [diff] [blame] | 15084 | int ret = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15085 | |
Matt Carlson | 4bae65c | 2010-11-24 08:31:52 +0000 | [diff] [blame] | 15086 | buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, |
| 15087 | &buf_dma, GFP_KERNEL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15088 | if (!buf) { |
| 15089 | ret = -ENOMEM; |
| 15090 | goto out_nofree; |
| 15091 | } |
| 15092 | |
| 15093 | tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | |
| 15094 | (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); |
| 15095 | |
David S. Miller | 59e6b43 | 2005-05-18 22:50:10 -0700 | [diff] [blame] | 15096 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15097 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15098 | if (tg3_flag(tp, 57765_PLUS)) |
Matt Carlson | cbf9ca6 | 2009-11-13 13:03:40 +0000 | [diff] [blame] | 15099 | goto out; |
| 15100 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15101 | if (tg3_flag(tp, PCI_EXPRESS)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15102 | /* DMA read watermark not used on PCIE */ |
| 15103 | tp->dma_rwctrl |= 0x00180000; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15104 | } else if (!tg3_flag(tp, PCIX_MODE)) { |
Michael Chan | 85e94ce | 2005-04-21 17:05:28 -0700 | [diff] [blame] | 15105 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
| 15106 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15107 | tp->dma_rwctrl |= 0x003f0000; |
| 15108 | else |
| 15109 | tp->dma_rwctrl |= 0x003f000f; |
| 15110 | } else { |
| 15111 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || |
| 15112 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
| 15113 | u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); |
Michael Chan | 49afdeb | 2007-02-13 12:17:03 -0800 | [diff] [blame] | 15114 | u32 read_water = 0x7; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15115 | |
Michael Chan | 4a29cc2 | 2006-03-19 13:21:12 -0800 | [diff] [blame] | 15116 | /* If the 5704 is behind the EPB bridge, we can |
| 15117 | * do the less restrictive ONE_DMA workaround for |
| 15118 | * better performance. |
| 15119 | */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15120 | if (tg3_flag(tp, 40BIT_DMA_BUG) && |
Michael Chan | 4a29cc2 | 2006-03-19 13:21:12 -0800 | [diff] [blame] | 15121 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) |
| 15122 | tp->dma_rwctrl |= 0x8000; |
| 15123 | else if (ccval == 0x6 || ccval == 0x7) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15124 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; |
| 15125 | |
Michael Chan | 49afdeb | 2007-02-13 12:17:03 -0800 | [diff] [blame] | 15126 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) |
| 15127 | read_water = 4; |
David S. Miller | 59e6b43 | 2005-05-18 22:50:10 -0700 | [diff] [blame] | 15128 | /* Set bit 23 to enable PCIX hw bug fix */ |
Michael Chan | 49afdeb | 2007-02-13 12:17:03 -0800 | [diff] [blame] | 15129 | tp->dma_rwctrl |= |
| 15130 | (read_water << DMA_RWCTRL_READ_WATER_SHIFT) | |
| 15131 | (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | |
| 15132 | (1 << 23); |
Michael Chan | 4cf78e4 | 2005-07-25 12:29:19 -0700 | [diff] [blame] | 15133 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { |
| 15134 | /* 5780 always in PCIX mode */ |
| 15135 | tp->dma_rwctrl |= 0x00144000; |
Michael Chan | a4e2b34 | 2005-10-26 15:46:52 -0700 | [diff] [blame] | 15136 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
| 15137 | /* 5714 always in PCIX mode */ |
| 15138 | tp->dma_rwctrl |= 0x00148000; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15139 | } else { |
| 15140 | tp->dma_rwctrl |= 0x001b000f; |
| 15141 | } |
| 15142 | } |
| 15143 | |
| 15144 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || |
| 15145 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) |
| 15146 | tp->dma_rwctrl &= 0xfffffff0; |
| 15147 | |
| 15148 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
| 15149 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { |
| 15150 | /* Remove this if it causes problems for some boards. */ |
| 15151 | tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; |
| 15152 | |
| 15153 | /* On 5700/5701 chips, we need to set this bit. |
| 15154 | * Otherwise the chip will issue cacheline transactions |
| 15155 | * to streamable DMA memory with not all the byte |
| 15156 | * enables turned on. This is an error on several |
| 15157 | * RISC PCI controllers, in particular sparc64. |
| 15158 | * |
| 15159 | * On 5703/5704 chips, this bit has been reassigned |
| 15160 | * a different meaning. In particular, it is used |
| 15161 | * on those chips to enable a PCI-X workaround. |
| 15162 | */ |
| 15163 | tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; |
| 15164 | } |
| 15165 | |
| 15166 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); |
| 15167 | |
| 15168 | #if 0 |
| 15169 | /* Unneeded, already done by tg3_get_invariants. */ |
| 15170 | tg3_switch_clocks(tp); |
| 15171 | #endif |
| 15172 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15173 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
| 15174 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) |
| 15175 | goto out; |
| 15176 | |
David S. Miller | 59e6b43 | 2005-05-18 22:50:10 -0700 | [diff] [blame] | 15177 | /* It is best to perform DMA test with maximum write burst size |
| 15178 | * to expose the 5700/5701 write DMA bug. |
| 15179 | */ |
| 15180 | saved_dma_rwctrl = tp->dma_rwctrl; |
| 15181 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; |
| 15182 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); |
| 15183 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15184 | while (1) { |
| 15185 | u32 *p = buf, i; |
| 15186 | |
| 15187 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) |
| 15188 | p[i] = i; |
| 15189 | |
| 15190 | /* Send the buffer to the chip. */ |
| 15191 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); |
| 15192 | if (ret) { |
Matt Carlson | 2445e46 | 2010-04-05 10:19:21 +0000 | [diff] [blame] | 15193 | dev_err(&tp->pdev->dev, |
| 15194 | "%s: Buffer write failed. err = %d\n", |
| 15195 | __func__, ret); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15196 | break; |
| 15197 | } |
| 15198 | |
| 15199 | #if 0 |
| 15200 | /* validate data reached card RAM correctly. */ |
| 15201 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { |
| 15202 | u32 val; |
| 15203 | tg3_read_mem(tp, 0x2100 + (i*4), &val); |
| 15204 | if (le32_to_cpu(val) != p[i]) { |
Matt Carlson | 2445e46 | 2010-04-05 10:19:21 +0000 | [diff] [blame] | 15205 | dev_err(&tp->pdev->dev, |
| 15206 | "%s: Buffer corrupted on device! " |
| 15207 | "(%d != %d)\n", __func__, val, i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15208 | /* ret = -ENODEV here? */ |
| 15209 | } |
| 15210 | p[i] = 0; |
| 15211 | } |
| 15212 | #endif |
| 15213 | /* Now read it back. */ |
| 15214 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); |
| 15215 | if (ret) { |
Matt Carlson | 5129c3a | 2010-04-05 10:19:23 +0000 | [diff] [blame] | 15216 | dev_err(&tp->pdev->dev, "%s: Buffer read failed. " |
| 15217 | "err = %d\n", __func__, ret); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15218 | break; |
| 15219 | } |
| 15220 | |
| 15221 | /* Verify it. */ |
| 15222 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { |
| 15223 | if (p[i] == i) |
| 15224 | continue; |
| 15225 | |
David S. Miller | 59e6b43 | 2005-05-18 22:50:10 -0700 | [diff] [blame] | 15226 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
| 15227 | DMA_RWCTRL_WRITE_BNDRY_16) { |
| 15228 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15229 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; |
| 15230 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); |
| 15231 | break; |
| 15232 | } else { |
Matt Carlson | 2445e46 | 2010-04-05 10:19:21 +0000 | [diff] [blame] | 15233 | dev_err(&tp->pdev->dev, |
| 15234 | "%s: Buffer corrupted on read back! " |
| 15235 | "(%d != %d)\n", __func__, p[i], i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15236 | ret = -ENODEV; |
| 15237 | goto out; |
| 15238 | } |
| 15239 | } |
| 15240 | |
| 15241 | if (i == (TEST_BUFFER_SIZE / sizeof(u32))) { |
| 15242 | /* Success. */ |
| 15243 | ret = 0; |
| 15244 | break; |
| 15245 | } |
| 15246 | } |
David S. Miller | 59e6b43 | 2005-05-18 22:50:10 -0700 | [diff] [blame] | 15247 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
| 15248 | DMA_RWCTRL_WRITE_BNDRY_16) { |
| 15249 | /* DMA test passed without adjusting DMA boundary, |
Michael Chan | 6d1cfba | 2005-06-08 14:13:14 -0700 | [diff] [blame] | 15250 | * now look for chipsets that are known to expose the |
| 15251 | * DMA bug without failing the test. |
David S. Miller | 59e6b43 | 2005-05-18 22:50:10 -0700 | [diff] [blame] | 15252 | */ |
Matt Carlson | 4143470 | 2011-03-09 16:58:22 +0000 | [diff] [blame] | 15253 | if (pci_dev_present(tg3_dma_wait_state_chipsets)) { |
Michael Chan | 6d1cfba | 2005-06-08 14:13:14 -0700 | [diff] [blame] | 15254 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; |
| 15255 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; |
Matt Carlson | 859a58879 | 2010-04-05 10:19:28 +0000 | [diff] [blame] | 15256 | } else { |
Michael Chan | 6d1cfba | 2005-06-08 14:13:14 -0700 | [diff] [blame] | 15257 | /* Safe to use the calculated DMA boundary. */ |
| 15258 | tp->dma_rwctrl = saved_dma_rwctrl; |
Matt Carlson | 859a58879 | 2010-04-05 10:19:28 +0000 | [diff] [blame] | 15259 | } |
Michael Chan | 6d1cfba | 2005-06-08 14:13:14 -0700 | [diff] [blame] | 15260 | |
David S. Miller | 59e6b43 | 2005-05-18 22:50:10 -0700 | [diff] [blame] | 15261 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); |
| 15262 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15263 | |
| 15264 | out: |
Matt Carlson | 4bae65c | 2010-11-24 08:31:52 +0000 | [diff] [blame] | 15265 | dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15266 | out_nofree: |
| 15267 | return ret; |
| 15268 | } |
| 15269 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15270 | static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) |
| 15271 | { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15272 | if (tg3_flag(tp, 57765_PLUS)) { |
Matt Carlson | 666bc83 | 2010-01-20 16:58:03 +0000 | [diff] [blame] | 15273 | tp->bufmgr_config.mbuf_read_dma_low_water = |
| 15274 | DEFAULT_MB_RDMA_LOW_WATER_5705; |
| 15275 | tp->bufmgr_config.mbuf_mac_rx_low_water = |
| 15276 | DEFAULT_MB_MACRX_LOW_WATER_57765; |
| 15277 | tp->bufmgr_config.mbuf_high_water = |
| 15278 | DEFAULT_MB_HIGH_WATER_57765; |
| 15279 | |
| 15280 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = |
| 15281 | DEFAULT_MB_RDMA_LOW_WATER_5705; |
| 15282 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = |
| 15283 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765; |
| 15284 | tp->bufmgr_config.mbuf_high_water_jumbo = |
| 15285 | DEFAULT_MB_HIGH_WATER_JUMBO_57765; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15286 | } else if (tg3_flag(tp, 5705_PLUS)) { |
Michael Chan | fdfec172 | 2005-07-25 12:31:48 -0700 | [diff] [blame] | 15287 | tp->bufmgr_config.mbuf_read_dma_low_water = |
| 15288 | DEFAULT_MB_RDMA_LOW_WATER_5705; |
| 15289 | tp->bufmgr_config.mbuf_mac_rx_low_water = |
| 15290 | DEFAULT_MB_MACRX_LOW_WATER_5705; |
| 15291 | tp->bufmgr_config.mbuf_high_water = |
| 15292 | DEFAULT_MB_HIGH_WATER_5705; |
Michael Chan | b5d3772 | 2006-09-27 16:06:21 -0700 | [diff] [blame] | 15293 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
| 15294 | tp->bufmgr_config.mbuf_mac_rx_low_water = |
| 15295 | DEFAULT_MB_MACRX_LOW_WATER_5906; |
| 15296 | tp->bufmgr_config.mbuf_high_water = |
| 15297 | DEFAULT_MB_HIGH_WATER_5906; |
| 15298 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15299 | |
Michael Chan | fdfec172 | 2005-07-25 12:31:48 -0700 | [diff] [blame] | 15300 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = |
| 15301 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780; |
| 15302 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = |
| 15303 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780; |
| 15304 | tp->bufmgr_config.mbuf_high_water_jumbo = |
| 15305 | DEFAULT_MB_HIGH_WATER_JUMBO_5780; |
| 15306 | } else { |
| 15307 | tp->bufmgr_config.mbuf_read_dma_low_water = |
| 15308 | DEFAULT_MB_RDMA_LOW_WATER; |
| 15309 | tp->bufmgr_config.mbuf_mac_rx_low_water = |
| 15310 | DEFAULT_MB_MACRX_LOW_WATER; |
| 15311 | tp->bufmgr_config.mbuf_high_water = |
| 15312 | DEFAULT_MB_HIGH_WATER; |
| 15313 | |
| 15314 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = |
| 15315 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO; |
| 15316 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = |
| 15317 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO; |
| 15318 | tp->bufmgr_config.mbuf_high_water_jumbo = |
| 15319 | DEFAULT_MB_HIGH_WATER_JUMBO; |
| 15320 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15321 | |
| 15322 | tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; |
| 15323 | tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; |
| 15324 | } |
| 15325 | |
| 15326 | static char * __devinit tg3_phy_string(struct tg3 *tp) |
| 15327 | { |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 15328 | switch (tp->phy_id & TG3_PHY_ID_MASK) { |
| 15329 | case TG3_PHY_ID_BCM5400: return "5400"; |
| 15330 | case TG3_PHY_ID_BCM5401: return "5401"; |
| 15331 | case TG3_PHY_ID_BCM5411: return "5411"; |
| 15332 | case TG3_PHY_ID_BCM5701: return "5701"; |
| 15333 | case TG3_PHY_ID_BCM5703: return "5703"; |
| 15334 | case TG3_PHY_ID_BCM5704: return "5704"; |
| 15335 | case TG3_PHY_ID_BCM5705: return "5705"; |
| 15336 | case TG3_PHY_ID_BCM5750: return "5750"; |
| 15337 | case TG3_PHY_ID_BCM5752: return "5752"; |
| 15338 | case TG3_PHY_ID_BCM5714: return "5714"; |
| 15339 | case TG3_PHY_ID_BCM5780: return "5780"; |
| 15340 | case TG3_PHY_ID_BCM5755: return "5755"; |
| 15341 | case TG3_PHY_ID_BCM5787: return "5787"; |
| 15342 | case TG3_PHY_ID_BCM5784: return "5784"; |
| 15343 | case TG3_PHY_ID_BCM5756: return "5722/5756"; |
| 15344 | case TG3_PHY_ID_BCM5906: return "5906"; |
| 15345 | case TG3_PHY_ID_BCM5761: return "5761"; |
| 15346 | case TG3_PHY_ID_BCM5718C: return "5718C"; |
| 15347 | case TG3_PHY_ID_BCM5718S: return "5718S"; |
| 15348 | case TG3_PHY_ID_BCM57765: return "57765"; |
Matt Carlson | 302b500 | 2010-06-05 17:24:38 +0000 | [diff] [blame] | 15349 | case TG3_PHY_ID_BCM5719C: return "5719C"; |
Matt Carlson | 6418f2c | 2011-04-05 14:22:49 +0000 | [diff] [blame] | 15350 | case TG3_PHY_ID_BCM5720C: return "5720C"; |
Matt Carlson | 79eb690 | 2010-02-17 15:17:03 +0000 | [diff] [blame] | 15351 | case TG3_PHY_ID_BCM8002: return "8002/serdes"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15352 | case 0: return "serdes"; |
| 15353 | default: return "unknown"; |
Stephen Hemminger | 855e111 | 2008-04-16 16:37:28 -0700 | [diff] [blame] | 15354 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15355 | } |
| 15356 | |
Michael Chan | f9804dd | 2005-09-27 12:13:10 -0700 | [diff] [blame] | 15357 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) |
| 15358 | { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15359 | if (tg3_flag(tp, PCI_EXPRESS)) { |
Michael Chan | f9804dd | 2005-09-27 12:13:10 -0700 | [diff] [blame] | 15360 | strcpy(str, "PCI Express"); |
| 15361 | return str; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15362 | } else if (tg3_flag(tp, PCIX_MODE)) { |
Michael Chan | f9804dd | 2005-09-27 12:13:10 -0700 | [diff] [blame] | 15363 | u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; |
| 15364 | |
| 15365 | strcpy(str, "PCIX:"); |
| 15366 | |
| 15367 | if ((clock_ctrl == 7) || |
| 15368 | ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == |
| 15369 | GRC_MISC_CFG_BOARD_ID_5704CIOBE)) |
| 15370 | strcat(str, "133MHz"); |
| 15371 | else if (clock_ctrl == 0) |
| 15372 | strcat(str, "33MHz"); |
| 15373 | else if (clock_ctrl == 2) |
| 15374 | strcat(str, "50MHz"); |
| 15375 | else if (clock_ctrl == 4) |
| 15376 | strcat(str, "66MHz"); |
| 15377 | else if (clock_ctrl == 6) |
| 15378 | strcat(str, "100MHz"); |
Michael Chan | f9804dd | 2005-09-27 12:13:10 -0700 | [diff] [blame] | 15379 | } else { |
| 15380 | strcpy(str, "PCI:"); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15381 | if (tg3_flag(tp, PCI_HIGH_SPEED)) |
Michael Chan | f9804dd | 2005-09-27 12:13:10 -0700 | [diff] [blame] | 15382 | strcat(str, "66MHz"); |
| 15383 | else |
| 15384 | strcat(str, "33MHz"); |
| 15385 | } |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15386 | if (tg3_flag(tp, PCI_32BIT)) |
Michael Chan | f9804dd | 2005-09-27 12:13:10 -0700 | [diff] [blame] | 15387 | strcat(str, ":32-bit"); |
| 15388 | else |
| 15389 | strcat(str, ":64-bit"); |
| 15390 | return str; |
| 15391 | } |
| 15392 | |
David S. Miller | 15f9850 | 2005-05-18 22:49:26 -0700 | [diff] [blame] | 15393 | static void __devinit tg3_init_coal(struct tg3 *tp) |
| 15394 | { |
| 15395 | struct ethtool_coalesce *ec = &tp->coal; |
| 15396 | |
| 15397 | memset(ec, 0, sizeof(*ec)); |
| 15398 | ec->cmd = ETHTOOL_GCOALESCE; |
| 15399 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; |
| 15400 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; |
| 15401 | ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; |
| 15402 | ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; |
| 15403 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; |
| 15404 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; |
| 15405 | ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; |
| 15406 | ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; |
| 15407 | ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; |
| 15408 | |
| 15409 | if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | |
| 15410 | HOSTCC_MODE_CLRTICK_TXBD)) { |
| 15411 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; |
| 15412 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; |
| 15413 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; |
| 15414 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; |
| 15415 | } |
Michael Chan | d244c89 | 2005-07-05 14:42:33 -0700 | [diff] [blame] | 15416 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15417 | if (tg3_flag(tp, 5705_PLUS)) { |
Michael Chan | d244c89 | 2005-07-05 14:42:33 -0700 | [diff] [blame] | 15418 | ec->rx_coalesce_usecs_irq = 0; |
| 15419 | ec->tx_coalesce_usecs_irq = 0; |
| 15420 | ec->stats_block_coalesce_usecs = 0; |
| 15421 | } |
David S. Miller | 15f9850 | 2005-05-18 22:49:26 -0700 | [diff] [blame] | 15422 | } |
| 15423 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15424 | static int __devinit tg3_init_one(struct pci_dev *pdev, |
| 15425 | const struct pci_device_id *ent) |
| 15426 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15427 | struct net_device *dev; |
| 15428 | struct tg3 *tp; |
Matt Carlson | 646c9ed | 2009-09-01 12:58:41 +0000 | [diff] [blame] | 15429 | int i, err, pm_cap; |
| 15430 | u32 sndmbx, rcvmbx, intmbx; |
Michael Chan | f9804dd | 2005-09-27 12:13:10 -0700 | [diff] [blame] | 15431 | char str[40]; |
Michael Chan | 72f2afb | 2006-03-06 19:28:35 -0800 | [diff] [blame] | 15432 | u64 dma_mask, persist_dma_mask; |
Michał Mirosław | c8f44af | 2011-11-15 15:29:55 +0000 | [diff] [blame] | 15433 | netdev_features_t features = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15434 | |
Joe Perches | 05dbe00 | 2010-02-17 19:44:19 +0000 | [diff] [blame] | 15435 | printk_once(KERN_INFO "%s\n", version); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15436 | |
| 15437 | err = pci_enable_device(pdev); |
| 15438 | if (err) { |
Matt Carlson | 2445e46 | 2010-04-05 10:19:21 +0000 | [diff] [blame] | 15439 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15440 | return err; |
| 15441 | } |
| 15442 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15443 | err = pci_request_regions(pdev, DRV_MODULE_NAME); |
| 15444 | if (err) { |
Matt Carlson | 2445e46 | 2010-04-05 10:19:21 +0000 | [diff] [blame] | 15445 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15446 | goto err_out_disable_pdev; |
| 15447 | } |
| 15448 | |
| 15449 | pci_set_master(pdev); |
| 15450 | |
| 15451 | /* Find power-management capability. */ |
| 15452 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); |
| 15453 | if (pm_cap == 0) { |
Matt Carlson | 2445e46 | 2010-04-05 10:19:21 +0000 | [diff] [blame] | 15454 | dev_err(&pdev->dev, |
| 15455 | "Cannot find Power Management capability, aborting\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15456 | err = -EIO; |
| 15457 | goto err_out_free_res; |
| 15458 | } |
| 15459 | |
Matt Carlson | 1682128 | 2011-07-13 09:27:28 +0000 | [diff] [blame] | 15460 | err = pci_set_power_state(pdev, PCI_D0); |
| 15461 | if (err) { |
| 15462 | dev_err(&pdev->dev, "Transition to D0 failed, aborting\n"); |
| 15463 | goto err_out_free_res; |
| 15464 | } |
| 15465 | |
Matt Carlson | fe5f578 | 2009-09-01 13:09:39 +0000 | [diff] [blame] | 15466 | dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15467 | if (!dev) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15468 | err = -ENOMEM; |
Matt Carlson | 1682128 | 2011-07-13 09:27:28 +0000 | [diff] [blame] | 15469 | goto err_out_power_down; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15470 | } |
| 15471 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15472 | SET_NETDEV_DEV(dev, &pdev->dev); |
| 15473 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15474 | tp = netdev_priv(dev); |
| 15475 | tp->pdev = pdev; |
| 15476 | tp->dev = dev; |
| 15477 | tp->pm_cap = pm_cap; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15478 | tp->rx_mode = TG3_DEF_RX_MODE; |
| 15479 | tp->tx_mode = TG3_DEF_TX_MODE; |
Matt Carlson | 8ef2142 | 2008-05-02 16:47:53 -0700 | [diff] [blame] | 15480 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15481 | if (tg3_debug > 0) |
| 15482 | tp->msg_enable = tg3_debug; |
| 15483 | else |
| 15484 | tp->msg_enable = TG3_DEF_MSG_ENABLE; |
| 15485 | |
| 15486 | /* The word/byte swap controls here control register access byte |
| 15487 | * swapping. DMA data byte swapping is controlled in the GRC_MODE |
| 15488 | * setting below. |
| 15489 | */ |
| 15490 | tp->misc_host_ctrl = |
| 15491 | MISC_HOST_CTRL_MASK_PCI_INT | |
| 15492 | MISC_HOST_CTRL_WORD_SWAP | |
| 15493 | MISC_HOST_CTRL_INDIR_ACCESS | |
| 15494 | MISC_HOST_CTRL_PCISTATE_RW; |
| 15495 | |
| 15496 | /* The NONFRM (non-frame) byte/word swap controls take effect |
| 15497 | * on descriptor entries, anything which isn't packet data. |
| 15498 | * |
| 15499 | * The StrongARM chips on the board (one for tx, one for rx) |
| 15500 | * are running in big-endian mode. |
| 15501 | */ |
| 15502 | tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | |
| 15503 | GRC_MODE_WSWAP_NONFRM_DATA); |
| 15504 | #ifdef __BIG_ENDIAN |
| 15505 | tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; |
| 15506 | #endif |
| 15507 | spin_lock_init(&tp->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15508 | spin_lock_init(&tp->indirect_lock); |
David Howells | c402895 | 2006-11-22 14:57:56 +0000 | [diff] [blame] | 15509 | INIT_WORK(&tp->reset_task, tg3_reset_task); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15510 | |
Matt Carlson | d5fe488 | 2008-11-21 17:20:32 -0800 | [diff] [blame] | 15511 | tp->regs = pci_ioremap_bar(pdev, BAR_0); |
Andy Gospodarek | ab0049b | 2007-09-06 20:42:14 +0100 | [diff] [blame] | 15512 | if (!tp->regs) { |
Matt Carlson | ab96b24 | 2010-04-05 10:19:22 +0000 | [diff] [blame] | 15513 | dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15514 | err = -ENOMEM; |
| 15515 | goto err_out_free_dev; |
| 15516 | } |
| 15517 | |
Matt Carlson | c9cab24 | 2011-07-13 09:27:27 +0000 | [diff] [blame] | 15518 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
| 15519 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || |
| 15520 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || |
| 15521 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || |
| 15522 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || |
| 15523 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || |
| 15524 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || |
| 15525 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) { |
| 15526 | tg3_flag_set(tp, ENABLE_APE); |
| 15527 | tp->aperegs = pci_ioremap_bar(pdev, BAR_2); |
| 15528 | if (!tp->aperegs) { |
| 15529 | dev_err(&pdev->dev, |
| 15530 | "Cannot map APE registers, aborting\n"); |
| 15531 | err = -ENOMEM; |
| 15532 | goto err_out_iounmap; |
| 15533 | } |
| 15534 | } |
| 15535 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15536 | tp->rx_pending = TG3_DEF_RX_RING_PENDING; |
| 15537 | tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15538 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15539 | dev->ethtool_ops = &tg3_ethtool_ops; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15540 | dev->watchdog_timeo = TG3_TX_TIMEOUT; |
Matt Carlson | 2ffcc98 | 2011-05-19 12:12:44 +0000 | [diff] [blame] | 15541 | dev->netdev_ops = &tg3_netdev_ops; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15542 | dev->irq = pdev->irq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15543 | |
| 15544 | err = tg3_get_invariants(tp); |
| 15545 | if (err) { |
Matt Carlson | ab96b24 | 2010-04-05 10:19:22 +0000 | [diff] [blame] | 15546 | dev_err(&pdev->dev, |
| 15547 | "Problem fetching invariants of chip, aborting\n"); |
Matt Carlson | c9cab24 | 2011-07-13 09:27:27 +0000 | [diff] [blame] | 15548 | goto err_out_apeunmap; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15549 | } |
| 15550 | |
Michael Chan | 4a29cc2 | 2006-03-19 13:21:12 -0800 | [diff] [blame] | 15551 | /* The EPB bridge inside 5714, 5715, and 5780 and any |
| 15552 | * device behind the EPB cannot support DMA addresses > 40-bit. |
Michael Chan | 72f2afb | 2006-03-06 19:28:35 -0800 | [diff] [blame] | 15553 | * On 64-bit systems with IOMMU, use 40-bit dma_mask. |
| 15554 | * On 64-bit systems without IOMMU, use 64-bit dma_mask and |
| 15555 | * do DMA address check in tg3_start_xmit(). |
| 15556 | */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15557 | if (tg3_flag(tp, IS_5788)) |
Yang Hongyang | 284901a | 2009-04-06 19:01:15 -0700 | [diff] [blame] | 15558 | persist_dma_mask = dma_mask = DMA_BIT_MASK(32); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15559 | else if (tg3_flag(tp, 40BIT_DMA_BUG)) { |
Yang Hongyang | 50cf156 | 2009-04-06 19:01:14 -0700 | [diff] [blame] | 15560 | persist_dma_mask = dma_mask = DMA_BIT_MASK(40); |
Michael Chan | 72f2afb | 2006-03-06 19:28:35 -0800 | [diff] [blame] | 15561 | #ifdef CONFIG_HIGHMEM |
Yang Hongyang | 6a35528 | 2009-04-06 19:01:13 -0700 | [diff] [blame] | 15562 | dma_mask = DMA_BIT_MASK(64); |
Michael Chan | 72f2afb | 2006-03-06 19:28:35 -0800 | [diff] [blame] | 15563 | #endif |
Michael Chan | 4a29cc2 | 2006-03-19 13:21:12 -0800 | [diff] [blame] | 15564 | } else |
Yang Hongyang | 6a35528 | 2009-04-06 19:01:13 -0700 | [diff] [blame] | 15565 | persist_dma_mask = dma_mask = DMA_BIT_MASK(64); |
Michael Chan | 72f2afb | 2006-03-06 19:28:35 -0800 | [diff] [blame] | 15566 | |
| 15567 | /* Configure DMA attributes. */ |
Yang Hongyang | 284901a | 2009-04-06 19:01:15 -0700 | [diff] [blame] | 15568 | if (dma_mask > DMA_BIT_MASK(32)) { |
Michael Chan | 72f2afb | 2006-03-06 19:28:35 -0800 | [diff] [blame] | 15569 | err = pci_set_dma_mask(pdev, dma_mask); |
| 15570 | if (!err) { |
Matt Carlson | 0da0606 | 2011-05-19 12:12:53 +0000 | [diff] [blame] | 15571 | features |= NETIF_F_HIGHDMA; |
Michael Chan | 72f2afb | 2006-03-06 19:28:35 -0800 | [diff] [blame] | 15572 | err = pci_set_consistent_dma_mask(pdev, |
| 15573 | persist_dma_mask); |
| 15574 | if (err < 0) { |
Matt Carlson | ab96b24 | 2010-04-05 10:19:22 +0000 | [diff] [blame] | 15575 | dev_err(&pdev->dev, "Unable to obtain 64 bit " |
| 15576 | "DMA for consistent allocations\n"); |
Matt Carlson | c9cab24 | 2011-07-13 09:27:27 +0000 | [diff] [blame] | 15577 | goto err_out_apeunmap; |
Michael Chan | 72f2afb | 2006-03-06 19:28:35 -0800 | [diff] [blame] | 15578 | } |
| 15579 | } |
| 15580 | } |
Yang Hongyang | 284901a | 2009-04-06 19:01:15 -0700 | [diff] [blame] | 15581 | if (err || dma_mask == DMA_BIT_MASK(32)) { |
| 15582 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
Michael Chan | 72f2afb | 2006-03-06 19:28:35 -0800 | [diff] [blame] | 15583 | if (err) { |
Matt Carlson | ab96b24 | 2010-04-05 10:19:22 +0000 | [diff] [blame] | 15584 | dev_err(&pdev->dev, |
| 15585 | "No usable DMA configuration, aborting\n"); |
Matt Carlson | c9cab24 | 2011-07-13 09:27:27 +0000 | [diff] [blame] | 15586 | goto err_out_apeunmap; |
Michael Chan | 72f2afb | 2006-03-06 19:28:35 -0800 | [diff] [blame] | 15587 | } |
| 15588 | } |
| 15589 | |
Michael Chan | fdfec172 | 2005-07-25 12:31:48 -0700 | [diff] [blame] | 15590 | tg3_init_bufmgr_config(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15591 | |
Matt Carlson | 0da0606 | 2011-05-19 12:12:53 +0000 | [diff] [blame] | 15592 | features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
| 15593 | |
| 15594 | /* 5700 B0 chips do not support checksumming correctly due |
| 15595 | * to hardware bugs. |
| 15596 | */ |
| 15597 | if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) { |
| 15598 | features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM; |
| 15599 | |
| 15600 | if (tg3_flag(tp, 5755_PLUS)) |
| 15601 | features |= NETIF_F_IPV6_CSUM; |
| 15602 | } |
| 15603 | |
Michael Chan | 4e3a7aa | 2006-03-20 17:47:44 -0800 | [diff] [blame] | 15604 | /* TSO is on by default on chips that support hardware TSO. |
| 15605 | * Firmware TSO on older chips gives lower performance, so it |
| 15606 | * is off by default, but can be enabled using ethtool. |
| 15607 | */ |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15608 | if ((tg3_flag(tp, HW_TSO_1) || |
| 15609 | tg3_flag(tp, HW_TSO_2) || |
| 15610 | tg3_flag(tp, HW_TSO_3)) && |
Matt Carlson | 0da0606 | 2011-05-19 12:12:53 +0000 | [diff] [blame] | 15611 | (features & NETIF_F_IP_CSUM)) |
| 15612 | features |= NETIF_F_TSO; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15613 | if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) { |
Matt Carlson | 0da0606 | 2011-05-19 12:12:53 +0000 | [diff] [blame] | 15614 | if (features & NETIF_F_IPV6_CSUM) |
| 15615 | features |= NETIF_F_TSO6; |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15616 | if (tg3_flag(tp, HW_TSO_3) || |
Matt Carlson | e849cdc | 2009-11-13 13:03:38 +0000 | [diff] [blame] | 15617 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
Matt Carlson | 57e6983 | 2008-05-25 23:48:31 -0700 | [diff] [blame] | 15618 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
| 15619 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15620 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
Michał Mirosław | dc66891 | 2011-04-07 03:35:07 +0000 | [diff] [blame] | 15621 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
Matt Carlson | 0da0606 | 2011-05-19 12:12:53 +0000 | [diff] [blame] | 15622 | features |= NETIF_F_TSO_ECN; |
Michael Chan | b002662 | 2006-07-03 19:42:14 -0700 | [diff] [blame] | 15623 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15624 | |
Matt Carlson | d542fe2 | 2011-05-19 16:02:43 +0000 | [diff] [blame] | 15625 | dev->features |= features; |
| 15626 | dev->vlan_features |= features; |
| 15627 | |
Mahesh Bandewar | 06c03c0 | 2011-05-08 06:51:48 +0000 | [diff] [blame] | 15628 | /* |
| 15629 | * Add loopback capability only for a subset of devices that support |
| 15630 | * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY |
| 15631 | * loopback for the remaining devices. |
| 15632 | */ |
| 15633 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 && |
| 15634 | !tg3_flag(tp, CPMU_PRESENT)) |
| 15635 | /* Add the loopback capability */ |
Matt Carlson | 0da0606 | 2011-05-19 12:12:53 +0000 | [diff] [blame] | 15636 | features |= NETIF_F_LOOPBACK; |
| 15637 | |
Matt Carlson | 0da0606 | 2011-05-19 12:12:53 +0000 | [diff] [blame] | 15638 | dev->hw_features |= features; |
Mahesh Bandewar | 06c03c0 | 2011-05-08 06:51:48 +0000 | [diff] [blame] | 15639 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15640 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15641 | !tg3_flag(tp, TSO_CAPABLE) && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15642 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15643 | tg3_flag_set(tp, MAX_RXPEND_64); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15644 | tp->rx_pending = 63; |
| 15645 | } |
| 15646 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15647 | err = tg3_get_device_address(tp); |
| 15648 | if (err) { |
Matt Carlson | ab96b24 | 2010-04-05 10:19:22 +0000 | [diff] [blame] | 15649 | dev_err(&pdev->dev, |
| 15650 | "Could not obtain valid ethernet address, aborting\n"); |
Matt Carlson | c9cab24 | 2011-07-13 09:27:27 +0000 | [diff] [blame] | 15651 | goto err_out_apeunmap; |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 15652 | } |
| 15653 | |
Matt Carlson | c88864d | 2007-11-12 21:07:01 -0800 | [diff] [blame] | 15654 | /* |
| 15655 | * Reset chip in case UNDI or EFI driver did not shutdown |
| 15656 | * DMA self test will enable WDMAC and we'll see (spurious) |
| 15657 | * pending DMA on the PCI bus at that point. |
| 15658 | */ |
| 15659 | if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || |
| 15660 | (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { |
| 15661 | tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); |
| 15662 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
| 15663 | } |
| 15664 | |
| 15665 | err = tg3_test_dma(tp); |
| 15666 | if (err) { |
Matt Carlson | ab96b24 | 2010-04-05 10:19:22 +0000 | [diff] [blame] | 15667 | dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); |
Matt Carlson | c88864d | 2007-11-12 21:07:01 -0800 | [diff] [blame] | 15668 | goto err_out_apeunmap; |
| 15669 | } |
| 15670 | |
Matt Carlson | 78f90dc | 2009-11-13 13:03:42 +0000 | [diff] [blame] | 15671 | intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; |
| 15672 | rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; |
| 15673 | sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; |
Matt Carlson | 6fd45cb | 2010-09-15 08:59:57 +0000 | [diff] [blame] | 15674 | for (i = 0; i < tp->irq_max; i++) { |
Matt Carlson | 78f90dc | 2009-11-13 13:03:42 +0000 | [diff] [blame] | 15675 | struct tg3_napi *tnapi = &tp->napi[i]; |
| 15676 | |
| 15677 | tnapi->tp = tp; |
| 15678 | tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; |
| 15679 | |
| 15680 | tnapi->int_mbox = intmbx; |
Matt Carlson | 93a700a | 2011-08-31 11:44:54 +0000 | [diff] [blame] | 15681 | if (i <= 4) |
Matt Carlson | 78f90dc | 2009-11-13 13:03:42 +0000 | [diff] [blame] | 15682 | intmbx += 0x8; |
| 15683 | else |
| 15684 | intmbx += 0x4; |
| 15685 | |
| 15686 | tnapi->consmbox = rcvmbx; |
| 15687 | tnapi->prodmbox = sndmbx; |
| 15688 | |
Matt Carlson | 66cfd1b | 2010-09-30 10:34:30 +0000 | [diff] [blame] | 15689 | if (i) |
Matt Carlson | 78f90dc | 2009-11-13 13:03:42 +0000 | [diff] [blame] | 15690 | tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); |
Matt Carlson | 66cfd1b | 2010-09-30 10:34:30 +0000 | [diff] [blame] | 15691 | else |
Matt Carlson | 78f90dc | 2009-11-13 13:03:42 +0000 | [diff] [blame] | 15692 | tnapi->coal_now = HOSTCC_MODE_NOW; |
Matt Carlson | 78f90dc | 2009-11-13 13:03:42 +0000 | [diff] [blame] | 15693 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15694 | if (!tg3_flag(tp, SUPPORT_MSIX)) |
Matt Carlson | 78f90dc | 2009-11-13 13:03:42 +0000 | [diff] [blame] | 15695 | break; |
| 15696 | |
| 15697 | /* |
| 15698 | * If we support MSIX, we'll be using RSS. If we're using |
| 15699 | * RSS, the first vector only handles link interrupts and the |
| 15700 | * remaining vectors handle rx and tx interrupts. Reuse the |
| 15701 | * mailbox values for the next iteration. The values we setup |
| 15702 | * above are still useful for the single vectored mode. |
| 15703 | */ |
| 15704 | if (!i) |
| 15705 | continue; |
| 15706 | |
| 15707 | rcvmbx += 0x8; |
| 15708 | |
| 15709 | if (sndmbx & 0x4) |
| 15710 | sndmbx -= 0x4; |
| 15711 | else |
| 15712 | sndmbx += 0xc; |
| 15713 | } |
| 15714 | |
Matt Carlson | c88864d | 2007-11-12 21:07:01 -0800 | [diff] [blame] | 15715 | tg3_init_coal(tp); |
| 15716 | |
Michael Chan | c49a156 | 2006-12-17 17:07:29 -0800 | [diff] [blame] | 15717 | pci_set_drvdata(pdev, dev); |
| 15718 | |
Matt Carlson | cd0d722 | 2011-07-13 09:27:33 +0000 | [diff] [blame] | 15719 | if (tg3_flag(tp, 5717_PLUS)) { |
| 15720 | /* Resume a low-power mode */ |
| 15721 | tg3_frob_aux_power(tp, false); |
| 15722 | } |
| 15723 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15724 | err = register_netdev(dev); |
| 15725 | if (err) { |
Matt Carlson | ab96b24 | 2010-04-05 10:19:22 +0000 | [diff] [blame] | 15726 | dev_err(&pdev->dev, "Cannot register net device, aborting\n"); |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 15727 | goto err_out_apeunmap; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15728 | } |
| 15729 | |
Joe Perches | 05dbe00 | 2010-02-17 19:44:19 +0000 | [diff] [blame] | 15730 | netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n", |
| 15731 | tp->board_part_number, |
| 15732 | tp->pci_chip_rev_id, |
| 15733 | tg3_bus_string(tp, str), |
| 15734 | dev->dev_addr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15735 | |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 15736 | if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { |
Matt Carlson | 3f0e3ad | 2009-11-02 14:24:36 +0000 | [diff] [blame] | 15737 | struct phy_device *phydev; |
| 15738 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
Matt Carlson | 5129c3a | 2010-04-05 10:19:23 +0000 | [diff] [blame] | 15739 | netdev_info(dev, |
| 15740 | "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", |
Joe Perches | 05dbe00 | 2010-02-17 19:44:19 +0000 | [diff] [blame] | 15741 | phydev->drv->name, dev_name(&phydev->dev)); |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 15742 | } else { |
| 15743 | char *ethtype; |
| 15744 | |
| 15745 | if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) |
| 15746 | ethtype = "10/100Base-TX"; |
| 15747 | else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) |
| 15748 | ethtype = "1000Base-SX"; |
| 15749 | else |
| 15750 | ethtype = "10/100/1000Base-T"; |
| 15751 | |
Matt Carlson | 5129c3a | 2010-04-05 10:19:23 +0000 | [diff] [blame] | 15752 | netdev_info(dev, "attached PHY is %s (%s Ethernet) " |
Matt Carlson | 4700783 | 2011-04-20 07:57:43 +0000 | [diff] [blame] | 15753 | "(WireSpeed[%d], EEE[%d])\n", |
| 15754 | tg3_phy_string(tp), ethtype, |
| 15755 | (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, |
| 15756 | (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 15757 | } |
Matt Carlson | df59c94 | 2008-11-03 16:52:56 -0800 | [diff] [blame] | 15758 | |
Joe Perches | 05dbe00 | 2010-02-17 19:44:19 +0000 | [diff] [blame] | 15759 | netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n", |
Michał Mirosław | dc66891 | 2011-04-07 03:35:07 +0000 | [diff] [blame] | 15760 | (dev->features & NETIF_F_RXCSUM) != 0, |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15761 | tg3_flag(tp, USE_LINKCHG_REG) != 0, |
Matt Carlson | f07e9af | 2010-08-02 11:26:07 +0000 | [diff] [blame] | 15762 | (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15763 | tg3_flag(tp, ENABLE_ASF) != 0, |
| 15764 | tg3_flag(tp, TSO_CAPABLE) != 0); |
Joe Perches | 05dbe00 | 2010-02-17 19:44:19 +0000 | [diff] [blame] | 15765 | netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", |
| 15766 | tp->dma_rwctrl, |
| 15767 | pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : |
| 15768 | ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15769 | |
Matt Carlson | b45aa2f | 2011-04-25 12:42:48 +0000 | [diff] [blame] | 15770 | pci_save_state(pdev); |
| 15771 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15772 | return 0; |
| 15773 | |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 15774 | err_out_apeunmap: |
| 15775 | if (tp->aperegs) { |
| 15776 | iounmap(tp->aperegs); |
| 15777 | tp->aperegs = NULL; |
| 15778 | } |
| 15779 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15780 | err_out_iounmap: |
Michael Chan | 6892914 | 2005-08-09 20:17:14 -0700 | [diff] [blame] | 15781 | if (tp->regs) { |
| 15782 | iounmap(tp->regs); |
Peter Hagervall | 22abe31 | 2005-09-16 17:01:03 -0700 | [diff] [blame] | 15783 | tp->regs = NULL; |
Michael Chan | 6892914 | 2005-08-09 20:17:14 -0700 | [diff] [blame] | 15784 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15785 | |
| 15786 | err_out_free_dev: |
| 15787 | free_netdev(dev); |
| 15788 | |
Matt Carlson | 1682128 | 2011-07-13 09:27:28 +0000 | [diff] [blame] | 15789 | err_out_power_down: |
| 15790 | pci_set_power_state(pdev, PCI_D3hot); |
| 15791 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15792 | err_out_free_res: |
| 15793 | pci_release_regions(pdev); |
| 15794 | |
| 15795 | err_out_disable_pdev: |
| 15796 | pci_disable_device(pdev); |
| 15797 | pci_set_drvdata(pdev, NULL); |
| 15798 | return err; |
| 15799 | } |
| 15800 | |
| 15801 | static void __devexit tg3_remove_one(struct pci_dev *pdev) |
| 15802 | { |
| 15803 | struct net_device *dev = pci_get_drvdata(pdev); |
| 15804 | |
| 15805 | if (dev) { |
| 15806 | struct tg3 *tp = netdev_priv(dev); |
| 15807 | |
Jaswinder Singh Rajput | 077f849 | 2009-01-04 16:11:25 -0800 | [diff] [blame] | 15808 | if (tp->fw) |
| 15809 | release_firmware(tp->fw); |
| 15810 | |
Matt Carlson | db21997 | 2011-11-04 09:15:03 +0000 | [diff] [blame] | 15811 | tg3_reset_task_cancel(tp); |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 15812 | |
David S. Miller | 1805b2f | 2011-10-24 18:18:09 -0400 | [diff] [blame] | 15813 | if (tg3_flag(tp, USE_PHYLIB)) { |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 15814 | tg3_phy_fini(tp); |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 15815 | tg3_mdio_fini(tp); |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 15816 | } |
Matt Carlson | 158d7ab | 2008-05-29 01:37:54 -0700 | [diff] [blame] | 15817 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15818 | unregister_netdev(dev); |
Matt Carlson | 0d3031d | 2007-10-10 18:02:43 -0700 | [diff] [blame] | 15819 | if (tp->aperegs) { |
| 15820 | iounmap(tp->aperegs); |
| 15821 | tp->aperegs = NULL; |
| 15822 | } |
Michael Chan | 6892914 | 2005-08-09 20:17:14 -0700 | [diff] [blame] | 15823 | if (tp->regs) { |
| 15824 | iounmap(tp->regs); |
Peter Hagervall | 22abe31 | 2005-09-16 17:01:03 -0700 | [diff] [blame] | 15825 | tp->regs = NULL; |
Michael Chan | 6892914 | 2005-08-09 20:17:14 -0700 | [diff] [blame] | 15826 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15827 | free_netdev(dev); |
| 15828 | pci_release_regions(pdev); |
| 15829 | pci_disable_device(pdev); |
| 15830 | pci_set_drvdata(pdev, NULL); |
| 15831 | } |
| 15832 | } |
| 15833 | |
Eric Dumazet | aa6027c | 2011-01-01 05:22:46 +0000 | [diff] [blame] | 15834 | #ifdef CONFIG_PM_SLEEP |
Rafael J. Wysocki | c866b7e | 2010-12-25 12:56:23 +0000 | [diff] [blame] | 15835 | static int tg3_suspend(struct device *device) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15836 | { |
Rafael J. Wysocki | c866b7e | 2010-12-25 12:56:23 +0000 | [diff] [blame] | 15837 | struct pci_dev *pdev = to_pci_dev(device); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15838 | struct net_device *dev = pci_get_drvdata(pdev); |
| 15839 | struct tg3 *tp = netdev_priv(dev); |
| 15840 | int err; |
| 15841 | |
| 15842 | if (!netif_running(dev)) |
| 15843 | return 0; |
| 15844 | |
Matt Carlson | db21997 | 2011-11-04 09:15:03 +0000 | [diff] [blame] | 15845 | tg3_reset_task_cancel(tp); |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 15846 | tg3_phy_stop(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15847 | tg3_netif_stop(tp); |
| 15848 | |
| 15849 | del_timer_sync(&tp->timer); |
| 15850 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 15851 | tg3_full_lock(tp, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15852 | tg3_disable_ints(tp); |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 15853 | tg3_full_unlock(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15854 | |
| 15855 | netif_device_detach(dev); |
| 15856 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 15857 | tg3_full_lock(tp, 0); |
Michael Chan | 944d980 | 2005-05-29 14:57:48 -0700 | [diff] [blame] | 15858 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15859 | tg3_flag_clear(tp, INIT_COMPLETE); |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 15860 | tg3_full_unlock(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15861 | |
Rafael J. Wysocki | c866b7e | 2010-12-25 12:56:23 +0000 | [diff] [blame] | 15862 | err = tg3_power_down_prepare(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15863 | if (err) { |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 15864 | int err2; |
| 15865 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 15866 | tg3_full_lock(tp, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15867 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15868 | tg3_flag_set(tp, INIT_COMPLETE); |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 15869 | err2 = tg3_restart_hw(tp, 1); |
| 15870 | if (err2) |
Michael Chan | b9ec6c1 | 2006-07-25 16:37:27 -0700 | [diff] [blame] | 15871 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15872 | |
| 15873 | tp->timer.expires = jiffies + tp->timer_offset; |
| 15874 | add_timer(&tp->timer); |
| 15875 | |
| 15876 | netif_device_attach(dev); |
| 15877 | tg3_netif_start(tp); |
| 15878 | |
Michael Chan | b9ec6c1 | 2006-07-25 16:37:27 -0700 | [diff] [blame] | 15879 | out: |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 15880 | tg3_full_unlock(tp); |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 15881 | |
| 15882 | if (!err2) |
| 15883 | tg3_phy_start(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15884 | } |
| 15885 | |
| 15886 | return err; |
| 15887 | } |
| 15888 | |
Rafael J. Wysocki | c866b7e | 2010-12-25 12:56:23 +0000 | [diff] [blame] | 15889 | static int tg3_resume(struct device *device) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15890 | { |
Rafael J. Wysocki | c866b7e | 2010-12-25 12:56:23 +0000 | [diff] [blame] | 15891 | struct pci_dev *pdev = to_pci_dev(device); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15892 | struct net_device *dev = pci_get_drvdata(pdev); |
| 15893 | struct tg3 *tp = netdev_priv(dev); |
| 15894 | int err; |
| 15895 | |
| 15896 | if (!netif_running(dev)) |
| 15897 | return 0; |
| 15898 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15899 | netif_device_attach(dev); |
| 15900 | |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 15901 | tg3_full_lock(tp, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15902 | |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15903 | tg3_flag_set(tp, INIT_COMPLETE); |
Michael Chan | b9ec6c1 | 2006-07-25 16:37:27 -0700 | [diff] [blame] | 15904 | err = tg3_restart_hw(tp, 1); |
| 15905 | if (err) |
| 15906 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15907 | |
| 15908 | tp->timer.expires = jiffies + tp->timer_offset; |
| 15909 | add_timer(&tp->timer); |
| 15910 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15911 | tg3_netif_start(tp); |
| 15912 | |
Michael Chan | b9ec6c1 | 2006-07-25 16:37:27 -0700 | [diff] [blame] | 15913 | out: |
David S. Miller | f47c11e | 2005-06-24 20:18:35 -0700 | [diff] [blame] | 15914 | tg3_full_unlock(tp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15915 | |
Matt Carlson | b02fd9e | 2008-05-25 23:47:41 -0700 | [diff] [blame] | 15916 | if (!err) |
| 15917 | tg3_phy_start(tp); |
| 15918 | |
Michael Chan | b9ec6c1 | 2006-07-25 16:37:27 -0700 | [diff] [blame] | 15919 | return err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15920 | } |
| 15921 | |
Rafael J. Wysocki | c866b7e | 2010-12-25 12:56:23 +0000 | [diff] [blame] | 15922 | static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume); |
Eric Dumazet | aa6027c | 2011-01-01 05:22:46 +0000 | [diff] [blame] | 15923 | #define TG3_PM_OPS (&tg3_pm_ops) |
| 15924 | |
| 15925 | #else |
| 15926 | |
| 15927 | #define TG3_PM_OPS NULL |
| 15928 | |
| 15929 | #endif /* CONFIG_PM_SLEEP */ |
Rafael J. Wysocki | c866b7e | 2010-12-25 12:56:23 +0000 | [diff] [blame] | 15930 | |
Matt Carlson | b45aa2f | 2011-04-25 12:42:48 +0000 | [diff] [blame] | 15931 | /** |
| 15932 | * tg3_io_error_detected - called when PCI error is detected |
| 15933 | * @pdev: Pointer to PCI device |
| 15934 | * @state: The current pci connection state |
| 15935 | * |
| 15936 | * This function is called after a PCI bus error affecting |
| 15937 | * this device has been detected. |
| 15938 | */ |
| 15939 | static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev, |
| 15940 | pci_channel_state_t state) |
| 15941 | { |
| 15942 | struct net_device *netdev = pci_get_drvdata(pdev); |
| 15943 | struct tg3 *tp = netdev_priv(netdev); |
| 15944 | pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET; |
| 15945 | |
| 15946 | netdev_info(netdev, "PCI I/O error detected\n"); |
| 15947 | |
| 15948 | rtnl_lock(); |
| 15949 | |
| 15950 | if (!netif_running(netdev)) |
| 15951 | goto done; |
| 15952 | |
| 15953 | tg3_phy_stop(tp); |
| 15954 | |
| 15955 | tg3_netif_stop(tp); |
| 15956 | |
| 15957 | del_timer_sync(&tp->timer); |
Matt Carlson | b45aa2f | 2011-04-25 12:42:48 +0000 | [diff] [blame] | 15958 | |
| 15959 | /* Want to make sure that the reset task doesn't run */ |
Matt Carlson | db21997 | 2011-11-04 09:15:03 +0000 | [diff] [blame] | 15960 | tg3_reset_task_cancel(tp); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 15961 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); |
Matt Carlson | b45aa2f | 2011-04-25 12:42:48 +0000 | [diff] [blame] | 15962 | |
| 15963 | netif_device_detach(netdev); |
| 15964 | |
| 15965 | /* Clean up software state, even if MMIO is blocked */ |
| 15966 | tg3_full_lock(tp, 0); |
| 15967 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); |
| 15968 | tg3_full_unlock(tp); |
| 15969 | |
| 15970 | done: |
| 15971 | if (state == pci_channel_io_perm_failure) |
| 15972 | err = PCI_ERS_RESULT_DISCONNECT; |
| 15973 | else |
| 15974 | pci_disable_device(pdev); |
| 15975 | |
| 15976 | rtnl_unlock(); |
| 15977 | |
| 15978 | return err; |
| 15979 | } |
| 15980 | |
| 15981 | /** |
| 15982 | * tg3_io_slot_reset - called after the pci bus has been reset. |
| 15983 | * @pdev: Pointer to PCI device |
| 15984 | * |
| 15985 | * Restart the card from scratch, as if from a cold-boot. |
| 15986 | * At this point, the card has exprienced a hard reset, |
| 15987 | * followed by fixups by BIOS, and has its config space |
| 15988 | * set up identically to what it was at cold boot. |
| 15989 | */ |
| 15990 | static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev) |
| 15991 | { |
| 15992 | struct net_device *netdev = pci_get_drvdata(pdev); |
| 15993 | struct tg3 *tp = netdev_priv(netdev); |
| 15994 | pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT; |
| 15995 | int err; |
| 15996 | |
| 15997 | rtnl_lock(); |
| 15998 | |
| 15999 | if (pci_enable_device(pdev)) { |
| 16000 | netdev_err(netdev, "Cannot re-enable PCI device after reset.\n"); |
| 16001 | goto done; |
| 16002 | } |
| 16003 | |
| 16004 | pci_set_master(pdev); |
| 16005 | pci_restore_state(pdev); |
| 16006 | pci_save_state(pdev); |
| 16007 | |
| 16008 | if (!netif_running(netdev)) { |
| 16009 | rc = PCI_ERS_RESULT_RECOVERED; |
| 16010 | goto done; |
| 16011 | } |
| 16012 | |
| 16013 | err = tg3_power_up(tp); |
Matt Carlson | bed9829 | 2011-07-13 09:27:29 +0000 | [diff] [blame] | 16014 | if (err) |
Matt Carlson | b45aa2f | 2011-04-25 12:42:48 +0000 | [diff] [blame] | 16015 | goto done; |
Matt Carlson | b45aa2f | 2011-04-25 12:42:48 +0000 | [diff] [blame] | 16016 | |
| 16017 | rc = PCI_ERS_RESULT_RECOVERED; |
| 16018 | |
| 16019 | done: |
| 16020 | rtnl_unlock(); |
| 16021 | |
| 16022 | return rc; |
| 16023 | } |
| 16024 | |
| 16025 | /** |
| 16026 | * tg3_io_resume - called when traffic can start flowing again. |
| 16027 | * @pdev: Pointer to PCI device |
| 16028 | * |
| 16029 | * This callback is called when the error recovery driver tells |
| 16030 | * us that its OK to resume normal operation. |
| 16031 | */ |
| 16032 | static void tg3_io_resume(struct pci_dev *pdev) |
| 16033 | { |
| 16034 | struct net_device *netdev = pci_get_drvdata(pdev); |
| 16035 | struct tg3 *tp = netdev_priv(netdev); |
| 16036 | int err; |
| 16037 | |
| 16038 | rtnl_lock(); |
| 16039 | |
| 16040 | if (!netif_running(netdev)) |
| 16041 | goto done; |
| 16042 | |
| 16043 | tg3_full_lock(tp, 0); |
Joe Perches | 63c3a66 | 2011-04-26 08:12:10 +0000 | [diff] [blame] | 16044 | tg3_flag_set(tp, INIT_COMPLETE); |
Matt Carlson | b45aa2f | 2011-04-25 12:42:48 +0000 | [diff] [blame] | 16045 | err = tg3_restart_hw(tp, 1); |
| 16046 | tg3_full_unlock(tp); |
| 16047 | if (err) { |
| 16048 | netdev_err(netdev, "Cannot restart hardware after reset.\n"); |
| 16049 | goto done; |
| 16050 | } |
| 16051 | |
| 16052 | netif_device_attach(netdev); |
| 16053 | |
| 16054 | tp->timer.expires = jiffies + tp->timer_offset; |
| 16055 | add_timer(&tp->timer); |
| 16056 | |
| 16057 | tg3_netif_start(tp); |
| 16058 | |
| 16059 | tg3_phy_start(tp); |
| 16060 | |
| 16061 | done: |
| 16062 | rtnl_unlock(); |
| 16063 | } |
| 16064 | |
| 16065 | static struct pci_error_handlers tg3_err_handler = { |
| 16066 | .error_detected = tg3_io_error_detected, |
| 16067 | .slot_reset = tg3_io_slot_reset, |
| 16068 | .resume = tg3_io_resume |
| 16069 | }; |
| 16070 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16071 | static struct pci_driver tg3_driver = { |
| 16072 | .name = DRV_MODULE_NAME, |
| 16073 | .id_table = tg3_pci_tbl, |
| 16074 | .probe = tg3_init_one, |
| 16075 | .remove = __devexit_p(tg3_remove_one), |
Matt Carlson | b45aa2f | 2011-04-25 12:42:48 +0000 | [diff] [blame] | 16076 | .err_handler = &tg3_err_handler, |
Eric Dumazet | aa6027c | 2011-01-01 05:22:46 +0000 | [diff] [blame] | 16077 | .driver.pm = TG3_PM_OPS, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16078 | }; |
| 16079 | |
| 16080 | static int __init tg3_init(void) |
| 16081 | { |
Jeff Garzik | 2991762 | 2006-08-19 17:48:59 -0400 | [diff] [blame] | 16082 | return pci_register_driver(&tg3_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16083 | } |
| 16084 | |
| 16085 | static void __exit tg3_cleanup(void) |
| 16086 | { |
| 16087 | pci_unregister_driver(&tg3_driver); |
| 16088 | } |
| 16089 | |
| 16090 | module_init(tg3_init); |
| 16091 | module_exit(tg3_cleanup); |