Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
| 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 5 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 8 | * copy of this software and associated documentation files (the |
| 9 | * "Software"), to deal in the Software without restriction, including |
| 10 | * without limitation the rights to use, copy, modify, merge, publish, |
| 11 | * distribute, sub license, and/or sell copies of the Software, and to |
| 12 | * permit persons to whom the Software is furnished to do so, subject to |
| 13 | * the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the |
| 16 | * next paragraph) shall be included in all copies or substantial portions |
| 17 | * of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 26 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 27 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 30 | |
Jesse Barnes | d1d7067 | 2014-05-28 14:39:03 -0700 | [diff] [blame] | 31 | #include <linux/async.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 32 | #include <drm/drmP.h> |
| 33 | #include <drm/drm_crtc_helper.h> |
| 34 | #include <drm/drm_fb_helper.h> |
Daniel Vetter | 4f03b1f | 2014-09-10 12:43:49 +0200 | [diff] [blame] | 35 | #include <drm/drm_legacy.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include "intel_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 37 | #include <drm/i915_drm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | #include "i915_drv.h" |
Yu Zhang | e21fd55 | 2015-02-10 19:05:51 +0800 | [diff] [blame] | 39 | #include "i915_vgpu.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 40 | #include "i915_trace.h" |
Jordan Crouse | dcdb167 | 2010-05-27 13:40:25 -0600 | [diff] [blame] | 41 | #include <linux/pci.h> |
Daniel Vetter | a4de052 | 2014-06-05 16:20:46 +0200 | [diff] [blame] | 42 | #include <linux/console.h> |
| 43 | #include <linux/vt.h> |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 44 | #include <linux/vgaarb.h> |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 45 | #include <linux/acpi.h> |
| 46 | #include <linux/pnp.h> |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 47 | #include <linux/vga_switcheroo.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 48 | #include <linux/slab.h> |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 49 | #include <acpi/video.h> |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 50 | #include <linux/pm.h> |
| 51 | #include <linux/pm_runtime.h> |
Imre Deak | 4bdc729 | 2014-05-20 19:47:20 +0300 | [diff] [blame] | 52 | #include <linux/oom.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 53 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 55 | static int i915_getparam(struct drm_device *dev, void *data, |
| 56 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 57 | { |
Jani Nikula | 4c8a4be | 2014-03-31 14:27:15 +0300 | [diff] [blame] | 58 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 59 | drm_i915_getparam_t *param = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 60 | int value; |
| 61 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 62 | switch (param->param) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 63 | case I915_PARAM_IRQ_ACTIVE: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 64 | case I915_PARAM_ALLOW_BATCHBUFFER: |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 65 | case I915_PARAM_LAST_DISPATCH: |
Daniel Vetter | ac883c8 | 2014-11-19 21:24:54 +0100 | [diff] [blame] | 66 | /* Reject all old ums/dri params. */ |
Chris Wilson | 5c6c600 | 2014-09-06 10:28:27 +0100 | [diff] [blame] | 67 | return -ENODEV; |
Kristian Høgsberg | ed4c9c4 | 2008-08-20 11:08:52 -0400 | [diff] [blame] | 68 | case I915_PARAM_CHIPSET_ID: |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 69 | value = dev->pdev->device; |
Kristian Høgsberg | ed4c9c4 | 2008-08-20 11:08:52 -0400 | [diff] [blame] | 70 | break; |
Neil Roberts | 27cd446 | 2015-03-04 14:41:16 +0000 | [diff] [blame] | 71 | case I915_PARAM_REVISION: |
| 72 | value = dev->pdev->revision; |
| 73 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 74 | case I915_PARAM_HAS_GEM: |
Daniel Vetter | 2e895b1 | 2012-04-23 16:50:51 +0200 | [diff] [blame] | 75 | value = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 76 | break; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 77 | case I915_PARAM_NUM_FENCES_AVAIL: |
| 78 | value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; |
| 79 | break; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 80 | case I915_PARAM_HAS_OVERLAY: |
| 81 | value = dev_priv->overlay ? 1 : 0; |
| 82 | break; |
Jesse Barnes | e9560f7 | 2009-11-19 10:49:07 -0800 | [diff] [blame] | 83 | case I915_PARAM_HAS_PAGEFLIPPING: |
| 84 | value = 1; |
| 85 | break; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 86 | case I915_PARAM_HAS_EXECBUF2: |
| 87 | /* depends on GEM */ |
Daniel Vetter | 2e895b1 | 2012-04-23 16:50:51 +0200 | [diff] [blame] | 88 | value = 1; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 89 | break; |
Zou Nan hai | e3a815f | 2010-05-31 13:58:47 +0800 | [diff] [blame] | 90 | case I915_PARAM_HAS_BSD: |
Chris Wilson | edc912f | 2012-05-11 14:29:32 +0100 | [diff] [blame] | 91 | value = intel_ring_initialized(&dev_priv->ring[VCS]); |
Zou Nan hai | e3a815f | 2010-05-31 13:58:47 +0800 | [diff] [blame] | 92 | break; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 93 | case I915_PARAM_HAS_BLT: |
Chris Wilson | edc912f | 2012-05-11 14:29:32 +0100 | [diff] [blame] | 94 | value = intel_ring_initialized(&dev_priv->ring[BCS]); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 95 | break; |
Xiang, Haihao | a1f2cc7 | 2013-05-28 19:22:34 -0700 | [diff] [blame] | 96 | case I915_PARAM_HAS_VEBOX: |
| 97 | value = intel_ring_initialized(&dev_priv->ring[VECS]); |
| 98 | break; |
Zhipeng Gong | 08e16dc | 2015-01-13 08:48:25 +0800 | [diff] [blame] | 99 | case I915_PARAM_HAS_BSD2: |
| 100 | value = intel_ring_initialized(&dev_priv->ring[VCS2]); |
| 101 | break; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 102 | case I915_PARAM_HAS_RELAXED_FENCING: |
| 103 | value = 1; |
| 104 | break; |
Daniel Vetter | bbf0c6b | 2010-12-05 11:30:40 +0100 | [diff] [blame] | 105 | case I915_PARAM_HAS_COHERENT_RINGS: |
| 106 | value = 1; |
| 107 | break; |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 108 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
| 109 | value = INTEL_INFO(dev)->gen >= 4; |
| 110 | break; |
Chris Wilson | 271d81b | 2011-03-01 15:24:41 +0000 | [diff] [blame] | 111 | case I915_PARAM_HAS_RELAXED_DELTA: |
| 112 | value = 1; |
| 113 | break; |
Eric Anholt | ae662d3 | 2012-01-03 09:23:29 -0800 | [diff] [blame] | 114 | case I915_PARAM_HAS_GEN7_SOL_RESET: |
| 115 | value = 1; |
| 116 | break; |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 117 | case I915_PARAM_HAS_LLC: |
| 118 | value = HAS_LLC(dev); |
| 119 | break; |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 120 | case I915_PARAM_HAS_WT: |
| 121 | value = HAS_WT(dev); |
| 122 | break; |
Daniel Vetter | 777ee96 | 2012-02-15 23:50:25 +0100 | [diff] [blame] | 123 | case I915_PARAM_HAS_ALIASING_PPGTT: |
Daniel Vetter | 896ab1a | 2014-08-06 15:04:51 +0200 | [diff] [blame] | 124 | value = USES_PPGTT(dev); |
Daniel Vetter | 777ee96 | 2012-02-15 23:50:25 +0100 | [diff] [blame] | 125 | break; |
Ben Widawsky | 172cf15 | 2012-06-05 15:24:25 -0700 | [diff] [blame] | 126 | case I915_PARAM_HAS_WAIT_TIMEOUT: |
| 127 | value = 1; |
| 128 | break; |
Chris Wilson | 2fedbff | 2012-08-08 10:23:22 +0100 | [diff] [blame] | 129 | case I915_PARAM_HAS_SEMAPHORES: |
| 130 | value = i915_semaphore_is_enabled(dev); |
| 131 | break; |
Dave Airlie | ec6f1bb | 2012-08-16 10:15:34 +1000 | [diff] [blame] | 132 | case I915_PARAM_HAS_PRIME_VMAP_FLUSH: |
| 133 | value = 1; |
| 134 | break; |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 135 | case I915_PARAM_HAS_SECURE_BATCHES: |
| 136 | value = capable(CAP_SYS_ADMIN); |
| 137 | break; |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 138 | case I915_PARAM_HAS_PINNED_BATCHES: |
| 139 | value = 1; |
| 140 | break; |
Daniel Vetter | ed5982e | 2013-01-17 22:23:36 +0100 | [diff] [blame] | 141 | case I915_PARAM_HAS_EXEC_NO_RELOC: |
| 142 | value = 1; |
| 143 | break; |
Chris Wilson | eef90cc | 2013-01-08 10:53:17 +0000 | [diff] [blame] | 144 | case I915_PARAM_HAS_EXEC_HANDLE_LUT: |
| 145 | value = 1; |
| 146 | break; |
Brad Volkin | d728c8e | 2014-02-18 10:15:56 -0800 | [diff] [blame] | 147 | case I915_PARAM_CMD_PARSER_VERSION: |
| 148 | value = i915_cmd_parser_get_version(); |
| 149 | break; |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 150 | case I915_PARAM_HAS_COHERENT_PHYS_GTT: |
| 151 | value = 1; |
| 152 | break; |
Akash Goel | 1816f92 | 2015-01-02 16:29:30 +0530 | [diff] [blame] | 153 | case I915_PARAM_MMAP_VERSION: |
| 154 | value = 1; |
| 155 | break; |
Jeff McGee | a1559ff | 2015-03-09 16:06:54 -0700 | [diff] [blame] | 156 | case I915_PARAM_SUBSLICE_TOTAL: |
| 157 | value = INTEL_INFO(dev)->subslice_total; |
| 158 | if (!value) |
| 159 | return -ENODEV; |
| 160 | break; |
| 161 | case I915_PARAM_EU_TOTAL: |
| 162 | value = INTEL_INFO(dev)->eu_total; |
| 163 | if (!value) |
| 164 | return -ENODEV; |
| 165 | break; |
Chris Wilson | 49e4d84 | 2015-06-15 12:23:48 +0100 | [diff] [blame] | 166 | case I915_PARAM_HAS_GPU_RESET: |
| 167 | value = i915.enable_hangcheck && |
Chris Wilson | 49e4d84 | 2015-06-15 12:23:48 +0100 | [diff] [blame] | 168 | intel_has_gpu_reset(dev); |
| 169 | break; |
Abdiel Janulgue | a9ed33c | 2015-07-01 10:12:23 +0300 | [diff] [blame] | 170 | case I915_PARAM_HAS_RESOURCE_STREAMER: |
| 171 | value = HAS_RESOURCE_STREAMER(dev); |
| 172 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 173 | default: |
Ben Widawsky | e29c32d | 2013-05-31 11:28:45 -0700 | [diff] [blame] | 174 | DRM_DEBUG("Unknown parameter %d\n", param->param); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 175 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 176 | } |
| 177 | |
Daniel Vetter | 1d6ac18 | 2013-12-11 11:34:44 +0100 | [diff] [blame] | 178 | if (copy_to_user(param->value, &value, sizeof(int))) { |
| 179 | DRM_ERROR("copy_to_user failed\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 180 | return -EFAULT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 181 | } |
| 182 | |
| 183 | return 0; |
| 184 | } |
| 185 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 186 | static int i915_setparam(struct drm_device *dev, void *data, |
| 187 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 188 | { |
Jani Nikula | 4c8a4be | 2014-03-31 14:27:15 +0300 | [diff] [blame] | 189 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 190 | drm_i915_setparam_t *param = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 191 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 192 | switch (param->param) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 193 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 194 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 195 | case I915_SETPARAM_ALLOW_BATCHBUFFER: |
Daniel Vetter | ac883c8 | 2014-11-19 21:24:54 +0100 | [diff] [blame] | 196 | /* Reject all old ums/dri params. */ |
Chris Wilson | 5c6c600 | 2014-09-06 10:28:27 +0100 | [diff] [blame] | 197 | return -ENODEV; |
| 198 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 199 | case I915_SETPARAM_NUM_USED_FENCES: |
| 200 | if (param->value > dev_priv->num_fence_regs || |
| 201 | param->value < 0) |
| 202 | return -EINVAL; |
| 203 | /* Userspace can use first N regs */ |
| 204 | dev_priv->fence_reg_start = param->value; |
| 205 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 206 | default: |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 207 | DRM_DEBUG_DRIVER("unknown parameter %d\n", |
yakui_zhao | be25ed9 | 2009-06-02 14:13:55 +0800 | [diff] [blame] | 208 | param->param); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 209 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 210 | } |
| 211 | |
| 212 | return 0; |
| 213 | } |
| 214 | |
Dave Airlie | ec2a4c3 | 2009-08-04 11:43:41 +1000 | [diff] [blame] | 215 | static int i915_get_bridge_dev(struct drm_device *dev) |
| 216 | { |
| 217 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 218 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 219 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
Dave Airlie | ec2a4c3 | 2009-08-04 11:43:41 +1000 | [diff] [blame] | 220 | if (!dev_priv->bridge_dev) { |
| 221 | DRM_ERROR("bridge device not found\n"); |
| 222 | return -1; |
| 223 | } |
| 224 | return 0; |
| 225 | } |
| 226 | |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 227 | #define MCHBAR_I915 0x44 |
| 228 | #define MCHBAR_I965 0x48 |
| 229 | #define MCHBAR_SIZE (4*4096) |
| 230 | |
| 231 | #define DEVEN_REG 0x54 |
| 232 | #define DEVEN_MCHBAR_EN (1 << 28) |
| 233 | |
| 234 | /* Allocate space for the MCH regs if needed, return nonzero on error */ |
| 235 | static int |
| 236 | intel_alloc_mchbar_resource(struct drm_device *dev) |
| 237 | { |
Jani Nikula | 4c8a4be | 2014-03-31 14:27:15 +0300 | [diff] [blame] | 238 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 239 | int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 240 | u32 temp_lo, temp_hi = 0; |
| 241 | u64 mchbar_addr; |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 242 | int ret; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 243 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 244 | if (INTEL_INFO(dev)->gen >= 4) |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 245 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
| 246 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); |
| 247 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; |
| 248 | |
| 249 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ |
| 250 | #ifdef CONFIG_PNP |
| 251 | if (mchbar_addr && |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 252 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) |
| 253 | return 0; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 254 | #endif |
| 255 | |
| 256 | /* Get some space for it */ |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 257 | dev_priv->mch_res.name = "i915 MCHBAR"; |
| 258 | dev_priv->mch_res.flags = IORESOURCE_MEM; |
| 259 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, |
| 260 | &dev_priv->mch_res, |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 261 | MCHBAR_SIZE, MCHBAR_SIZE, |
| 262 | PCIBIOS_MIN_MEM, |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 263 | 0, pcibios_align_resource, |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 264 | dev_priv->bridge_dev); |
| 265 | if (ret) { |
| 266 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); |
| 267 | dev_priv->mch_res.start = 0; |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 268 | return ret; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 269 | } |
| 270 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 271 | if (INTEL_INFO(dev)->gen >= 4) |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 272 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
| 273 | upper_32_bits(dev_priv->mch_res.start)); |
| 274 | |
| 275 | pci_write_config_dword(dev_priv->bridge_dev, reg, |
| 276 | lower_32_bits(dev_priv->mch_res.start)); |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 277 | return 0; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 278 | } |
| 279 | |
| 280 | /* Setup MCHBAR if possible, return true if we should disable it again */ |
| 281 | static void |
| 282 | intel_setup_mchbar(struct drm_device *dev) |
| 283 | { |
Jani Nikula | 4c8a4be | 2014-03-31 14:27:15 +0300 | [diff] [blame] | 284 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 285 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 286 | u32 temp; |
| 287 | bool enabled; |
| 288 | |
Jesse Barnes | 11ea8b7 | 2014-03-03 14:27:57 -0800 | [diff] [blame] | 289 | if (IS_VALLEYVIEW(dev)) |
| 290 | return; |
| 291 | |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 292 | dev_priv->mchbar_need_disable = false; |
| 293 | |
| 294 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
| 295 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); |
| 296 | enabled = !!(temp & DEVEN_MCHBAR_EN); |
| 297 | } else { |
| 298 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); |
| 299 | enabled = temp & 1; |
| 300 | } |
| 301 | |
| 302 | /* If it's already enabled, don't have to do anything */ |
| 303 | if (enabled) |
| 304 | return; |
| 305 | |
| 306 | if (intel_alloc_mchbar_resource(dev)) |
| 307 | return; |
| 308 | |
| 309 | dev_priv->mchbar_need_disable = true; |
| 310 | |
| 311 | /* Space is allocated or reserved, so enable it. */ |
| 312 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
| 313 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, |
| 314 | temp | DEVEN_MCHBAR_EN); |
| 315 | } else { |
| 316 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); |
| 317 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); |
| 318 | } |
| 319 | } |
| 320 | |
| 321 | static void |
| 322 | intel_teardown_mchbar(struct drm_device *dev) |
| 323 | { |
Jani Nikula | 4c8a4be | 2014-03-31 14:27:15 +0300 | [diff] [blame] | 324 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 325 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 326 | u32 temp; |
| 327 | |
| 328 | if (dev_priv->mchbar_need_disable) { |
| 329 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
| 330 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); |
| 331 | temp &= ~DEVEN_MCHBAR_EN; |
| 332 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); |
| 333 | } else { |
| 334 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); |
| 335 | temp &= ~1; |
| 336 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); |
| 337 | } |
| 338 | } |
| 339 | |
| 340 | if (dev_priv->mch_res.start) |
| 341 | release_resource(&dev_priv->mch_res); |
| 342 | } |
| 343 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 344 | /* true = enable decode, false = disable decoder */ |
| 345 | static unsigned int i915_vga_set_decode(void *cookie, bool state) |
| 346 | { |
| 347 | struct drm_device *dev = cookie; |
| 348 | |
| 349 | intel_modeset_vga_set_state(dev, state); |
| 350 | if (state) |
| 351 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | |
| 352 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
| 353 | else |
| 354 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
| 355 | } |
| 356 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 357 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
| 358 | { |
| 359 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 360 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; |
Robin Schroer | 1a5036b | 2014-06-02 16:59:39 +0200 | [diff] [blame] | 361 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 362 | if (state == VGA_SWITCHEROO_ON) { |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 363 | pr_info("switched on\n"); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 364 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 365 | /* i915 resume handler doesn't set to D0 */ |
| 366 | pci_set_power_state(dev->pdev, PCI_D0); |
Maarten Lankhorst | 1751fcf | 2015-08-27 15:15:15 +0200 | [diff] [blame] | 367 | i915_resume_switcheroo(dev); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 368 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 369 | } else { |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 370 | pr_err("switched off\n"); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 371 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
Maarten Lankhorst | 1751fcf | 2015-08-27 15:15:15 +0200 | [diff] [blame] | 372 | i915_suspend_switcheroo(dev, pmm); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 373 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 374 | } |
| 375 | } |
| 376 | |
| 377 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) |
| 378 | { |
| 379 | struct drm_device *dev = pci_get_drvdata(pdev); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 380 | |
Daniel Vetter | fc8fd40 | 2013-11-03 20:46:34 +0100 | [diff] [blame] | 381 | /* |
| 382 | * FIXME: open_count is protected by drm_global_mutex but that would lead to |
| 383 | * locking inversion with the driver load path. And the access here is |
| 384 | * completely racy anyway. So don't bother with locking for now. |
| 385 | */ |
| 386 | return dev->open_count == 0; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 387 | } |
| 388 | |
Takashi Iwai | 26ec685 | 2012-05-11 07:51:17 +0200 | [diff] [blame] | 389 | static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { |
| 390 | .set_gpu_state = i915_switcheroo_set_state, |
| 391 | .reprobe = NULL, |
| 392 | .can_switch = i915_switcheroo_can_switch, |
| 393 | }; |
| 394 | |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 395 | static int i915_load_modeset_init(struct drm_device *dev) |
| 396 | { |
| 397 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 398 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 399 | |
Bryan Freed | 6d139a8 | 2010-10-14 09:14:51 +0100 | [diff] [blame] | 400 | ret = intel_parse_bios(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 401 | if (ret) |
| 402 | DRM_INFO("failed to find VBIOS tables\n"); |
| 403 | |
Chris Wilson | 934f992 | 2011-01-20 13:09:12 +0000 | [diff] [blame] | 404 | /* If we have > 1 VGA cards, then we need to arbitrate access |
| 405 | * to the common VGA resources. |
| 406 | * |
| 407 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), |
| 408 | * then we do not take part in VGA arbitration and the |
| 409 | * vga_client_register() fails with -ENODEV. |
| 410 | */ |
Dave Airlie | ebff5fa9 | 2013-10-11 15:12:04 +1000 | [diff] [blame] | 411 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); |
| 412 | if (ret && ret != -ENODEV) |
| 413 | goto out; |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 414 | |
Jesse Barnes | 723bfd7 | 2010-10-07 16:01:13 -0700 | [diff] [blame] | 415 | intel_register_dsm_handler(); |
| 416 | |
Dave Airlie | 0d69704 | 2012-09-10 12:28:36 +1000 | [diff] [blame] | 417 | ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 418 | if (ret) |
Chris Wilson | 5a79395 | 2010-06-06 10:50:03 +0100 | [diff] [blame] | 419 | goto cleanup_vga_client; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 420 | |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 421 | /* Initialise stolen first so that we may reserve preallocated |
| 422 | * objects for the BIOS to KMS transition. |
| 423 | */ |
| 424 | ret = i915_gem_init_stolen(dev); |
| 425 | if (ret) |
| 426 | goto cleanup_vga_switcheroo; |
| 427 | |
Imre Deak | e13192f | 2014-02-18 00:02:15 +0200 | [diff] [blame] | 428 | intel_power_domains_init_hw(dev_priv); |
| 429 | |
Daniel Vetter | 2aeb7d3 | 2014-09-30 10:56:43 +0200 | [diff] [blame] | 430 | ret = intel_irq_install(dev_priv); |
Daniel Vetter | 52d7ece | 2012-12-01 21:03:22 +0100 | [diff] [blame] | 431 | if (ret) |
| 432 | goto cleanup_gem_stolen; |
| 433 | |
| 434 | /* Important: The output setup functions called by modeset_init need |
| 435 | * working irqs for e.g. gmbus and dp aux transfers. */ |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 436 | intel_modeset_init(dev); |
| 437 | |
Alex Dai | 33a732f | 2015-08-12 15:43:36 +0100 | [diff] [blame] | 438 | /* intel_guc_ucode_init() needs the mutex to allocate GEM objects */ |
| 439 | mutex_lock(&dev->struct_mutex); |
| 440 | intel_guc_ucode_init(dev); |
| 441 | mutex_unlock(&dev->struct_mutex); |
| 442 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 443 | ret = i915_gem_init(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 444 | if (ret) |
Imre Deak | 713028b | 2014-04-25 17:28:00 +0300 | [diff] [blame] | 445 | goto cleanup_irq; |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 446 | |
Daniel Vetter | 52d7ece | 2012-12-01 21:03:22 +0100 | [diff] [blame] | 447 | intel_modeset_gem_init(dev); |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 448 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 449 | /* Always safe in the mode setting case. */ |
| 450 | /* FIXME: do pre/post-mode set stuff in core KMS code */ |
Ville Syrjälä | ba0bf12 | 2013-10-04 14:53:33 +0300 | [diff] [blame] | 451 | dev->vblank_disable_allowed = true; |
Imre Deak | 713028b | 2014-04-25 17:28:00 +0300 | [diff] [blame] | 452 | if (INTEL_INFO(dev)->num_pipes == 0) |
Ben Widawsky | e3c7475 | 2013-04-05 13:12:39 -0700 | [diff] [blame] | 453 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 454 | |
Chris Wilson | 5a79395 | 2010-06-06 10:50:03 +0100 | [diff] [blame] | 455 | ret = intel_fbdev_init(dev); |
| 456 | if (ret) |
Daniel Vetter | 52d7ece | 2012-12-01 21:03:22 +0100 | [diff] [blame] | 457 | goto cleanup_gem; |
| 458 | |
| 459 | /* Only enable hotplug handling once the fbdev is fully set up. */ |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 460 | intel_hpd_init(dev_priv); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 461 | |
| 462 | /* |
| 463 | * Some ports require correctly set-up hpd registers for detection to |
| 464 | * work properly (leading to ghost connected connector status), e.g. VGA |
| 465 | * on gm45. Hence we can only set up the initial fbdev config after hpd |
| 466 | * irqs are fully enabled. Now we should scan for the initial config |
| 467 | * only once hotplug handling is enabled, but due to screwed-up locking |
| 468 | * around kms/fbdev init we can't protect the fdbev initial config |
| 469 | * scanning against hotplug events. Hence do this first and ignore the |
| 470 | * tiny window where we will loose hotplug notifactions. |
| 471 | */ |
Jesse Barnes | d1d7067 | 2014-05-28 14:39:03 -0700 | [diff] [blame] | 472 | async_schedule(intel_fbdev_initial_config, dev_priv); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 473 | |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 474 | drm_kms_helper_poll_init(dev); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 475 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 476 | return 0; |
| 477 | |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 478 | cleanup_gem: |
| 479 | mutex_lock(&dev->struct_mutex); |
| 480 | i915_gem_cleanup_ringbuffer(dev); |
Ben Widawsky | 55d2328 | 2013-05-25 12:26:39 -0700 | [diff] [blame] | 481 | i915_gem_context_fini(dev); |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 482 | mutex_unlock(&dev->struct_mutex); |
Imre Deak | 713028b | 2014-04-25 17:28:00 +0300 | [diff] [blame] | 483 | cleanup_irq: |
Alex Dai | 33a732f | 2015-08-12 15:43:36 +0100 | [diff] [blame] | 484 | mutex_lock(&dev->struct_mutex); |
| 485 | intel_guc_ucode_fini(dev); |
| 486 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | 52d7ece | 2012-12-01 21:03:22 +0100 | [diff] [blame] | 487 | drm_irq_uninstall(dev); |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 488 | cleanup_gem_stolen: |
| 489 | i915_gem_cleanup_stolen(dev); |
Chris Wilson | 5a79395 | 2010-06-06 10:50:03 +0100 | [diff] [blame] | 490 | cleanup_vga_switcheroo: |
| 491 | vga_switcheroo_unregister_client(dev->pdev); |
| 492 | cleanup_vga_client: |
| 493 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 494 | out: |
| 495 | return ret; |
| 496 | } |
| 497 | |
Daniel Vetter | 243eaf3 | 2013-12-17 10:00:54 +0100 | [diff] [blame] | 498 | #if IS_ENABLED(CONFIG_FB) |
Chris Wilson | f96de58 | 2013-12-16 15:57:40 +0000 | [diff] [blame] | 499 | static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
Daniel Vetter | e188719 | 2012-06-12 11:28:17 +0200 | [diff] [blame] | 500 | { |
| 501 | struct apertures_struct *ap; |
| 502 | struct pci_dev *pdev = dev_priv->dev->pdev; |
| 503 | bool primary; |
Chris Wilson | f96de58 | 2013-12-16 15:57:40 +0000 | [diff] [blame] | 504 | int ret; |
Daniel Vetter | e188719 | 2012-06-12 11:28:17 +0200 | [diff] [blame] | 505 | |
| 506 | ap = alloc_apertures(1); |
| 507 | if (!ap) |
Chris Wilson | f96de58 | 2013-12-16 15:57:40 +0000 | [diff] [blame] | 508 | return -ENOMEM; |
Daniel Vetter | e188719 | 2012-06-12 11:28:17 +0200 | [diff] [blame] | 509 | |
Ben Widawsky | dabb7a9 | 2013-01-17 12:45:16 -0800 | [diff] [blame] | 510 | ap->ranges[0].base = dev_priv->gtt.mappable_base; |
Ben Widawsky | f64e292 | 2013-05-25 12:26:36 -0700 | [diff] [blame] | 511 | ap->ranges[0].size = dev_priv->gtt.mappable_end; |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 512 | |
Daniel Vetter | e188719 | 2012-06-12 11:28:17 +0200 | [diff] [blame] | 513 | primary = |
| 514 | pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; |
| 515 | |
Chris Wilson | f96de58 | 2013-12-16 15:57:40 +0000 | [diff] [blame] | 516 | ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary); |
Daniel Vetter | e188719 | 2012-06-12 11:28:17 +0200 | [diff] [blame] | 517 | |
| 518 | kfree(ap); |
Chris Wilson | f96de58 | 2013-12-16 15:57:40 +0000 | [diff] [blame] | 519 | |
| 520 | return ret; |
Daniel Vetter | e188719 | 2012-06-12 11:28:17 +0200 | [diff] [blame] | 521 | } |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 522 | #else |
Chris Wilson | f96de58 | 2013-12-16 15:57:40 +0000 | [diff] [blame] | 523 | static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 524 | { |
Chris Wilson | f96de58 | 2013-12-16 15:57:40 +0000 | [diff] [blame] | 525 | return 0; |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 526 | } |
| 527 | #endif |
Daniel Vetter | e188719 | 2012-06-12 11:28:17 +0200 | [diff] [blame] | 528 | |
Daniel Vetter | a4de052 | 2014-06-05 16:20:46 +0200 | [diff] [blame] | 529 | #if !defined(CONFIG_VGA_CONSOLE) |
| 530 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) |
| 531 | { |
| 532 | return 0; |
| 533 | } |
| 534 | #elif !defined(CONFIG_DUMMY_CONSOLE) |
| 535 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) |
| 536 | { |
| 537 | return -ENODEV; |
| 538 | } |
| 539 | #else |
| 540 | static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) |
| 541 | { |
Daniel Vetter | 1bb9e63 | 2014-07-08 10:02:43 +0200 | [diff] [blame] | 542 | int ret = 0; |
Daniel Vetter | a4de052 | 2014-06-05 16:20:46 +0200 | [diff] [blame] | 543 | |
| 544 | DRM_INFO("Replacing VGA console driver\n"); |
| 545 | |
| 546 | console_lock(); |
Daniel Vetter | 1bb9e63 | 2014-07-08 10:02:43 +0200 | [diff] [blame] | 547 | if (con_is_bound(&vga_con)) |
| 548 | ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1); |
Daniel Vetter | a4de052 | 2014-06-05 16:20:46 +0200 | [diff] [blame] | 549 | if (ret == 0) { |
| 550 | ret = do_unregister_con_driver(&vga_con); |
| 551 | |
| 552 | /* Ignore "already unregistered". */ |
| 553 | if (ret == -ENODEV) |
| 554 | ret = 0; |
| 555 | } |
| 556 | console_unlock(); |
| 557 | |
| 558 | return ret; |
| 559 | } |
| 560 | #endif |
| 561 | |
Daniel Vetter | c96ea64 | 2012-08-08 22:01:51 +0200 | [diff] [blame] | 562 | static void i915_dump_device_info(struct drm_i915_private *dev_priv) |
| 563 | { |
Damien Lespiau | 5c969aa | 2014-02-07 19:12:48 +0000 | [diff] [blame] | 564 | const struct intel_device_info *info = &dev_priv->info; |
Daniel Vetter | c96ea64 | 2012-08-08 22:01:51 +0200 | [diff] [blame] | 565 | |
Damien Lespiau | e2a5800 | 2013-04-23 16:38:34 +0100 | [diff] [blame] | 566 | #define PRINT_S(name) "%s" |
| 567 | #define SEP_EMPTY |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 568 | #define PRINT_FLAG(name) info->name ? #name "," : "" |
| 569 | #define SEP_COMMA , |
Ville Syrjälä | 19c656a | 2014-06-13 15:39:56 +0300 | [diff] [blame] | 570 | DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags=" |
Damien Lespiau | e2a5800 | 2013-04-23 16:38:34 +0100 | [diff] [blame] | 571 | DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY), |
Daniel Vetter | c96ea64 | 2012-08-08 22:01:51 +0200 | [diff] [blame] | 572 | info->gen, |
| 573 | dev_priv->dev->pdev->device, |
Ville Syrjälä | 19c656a | 2014-06-13 15:39:56 +0300 | [diff] [blame] | 574 | dev_priv->dev->pdev->revision, |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 575 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA)); |
Damien Lespiau | e2a5800 | 2013-04-23 16:38:34 +0100 | [diff] [blame] | 576 | #undef PRINT_S |
| 577 | #undef SEP_EMPTY |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 578 | #undef PRINT_FLAG |
| 579 | #undef SEP_COMMA |
Daniel Vetter | c96ea64 | 2012-08-08 22:01:51 +0200 | [diff] [blame] | 580 | } |
| 581 | |
Jeff McGee | 9705ad8 | 2015-04-03 18:13:15 -0700 | [diff] [blame] | 582 | static void cherryview_sseu_info_init(struct drm_device *dev) |
| 583 | { |
| 584 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 585 | struct intel_device_info *info; |
| 586 | u32 fuse, eu_dis; |
| 587 | |
| 588 | info = (struct intel_device_info *)&dev_priv->info; |
| 589 | fuse = I915_READ(CHV_FUSE_GT); |
| 590 | |
| 591 | info->slice_total = 1; |
| 592 | |
| 593 | if (!(fuse & CHV_FGT_DISABLE_SS0)) { |
| 594 | info->subslice_per_slice++; |
| 595 | eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | |
| 596 | CHV_FGT_EU_DIS_SS0_R1_MASK); |
| 597 | info->eu_total += 8 - hweight32(eu_dis); |
| 598 | } |
| 599 | |
| 600 | if (!(fuse & CHV_FGT_DISABLE_SS1)) { |
| 601 | info->subslice_per_slice++; |
| 602 | eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK | |
| 603 | CHV_FGT_EU_DIS_SS1_R1_MASK); |
| 604 | info->eu_total += 8 - hweight32(eu_dis); |
| 605 | } |
| 606 | |
| 607 | info->subslice_total = info->subslice_per_slice; |
| 608 | /* |
| 609 | * CHV expected to always have a uniform distribution of EU |
| 610 | * across subslices. |
| 611 | */ |
| 612 | info->eu_per_subslice = info->subslice_total ? |
| 613 | info->eu_total / info->subslice_total : |
| 614 | 0; |
| 615 | /* |
| 616 | * CHV supports subslice power gating on devices with more than |
| 617 | * one subslice, and supports EU power gating on devices with |
| 618 | * more than one EU pair per subslice. |
| 619 | */ |
| 620 | info->has_slice_pg = 0; |
| 621 | info->has_subslice_pg = (info->subslice_total > 1); |
| 622 | info->has_eu_pg = (info->eu_per_subslice > 2); |
| 623 | } |
| 624 | |
| 625 | static void gen9_sseu_info_init(struct drm_device *dev) |
| 626 | { |
| 627 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 628 | struct intel_device_info *info; |
Jeff McGee | dead16e | 2015-04-03 18:13:16 -0700 | [diff] [blame] | 629 | int s_max = 3, ss_max = 4, eu_max = 8; |
Jeff McGee | 9705ad8 | 2015-04-03 18:13:15 -0700 | [diff] [blame] | 630 | int s, ss; |
Jeff McGee | dead16e | 2015-04-03 18:13:16 -0700 | [diff] [blame] | 631 | u32 fuse2, s_enable, ss_disable, eu_disable; |
| 632 | u8 eu_mask = 0xff; |
| 633 | |
Jeff McGee | 9705ad8 | 2015-04-03 18:13:15 -0700 | [diff] [blame] | 634 | info = (struct intel_device_info *)&dev_priv->info; |
| 635 | fuse2 = I915_READ(GEN8_FUSE2); |
| 636 | s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> |
| 637 | GEN8_F2_S_ENA_SHIFT; |
| 638 | ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >> |
| 639 | GEN9_F2_SS_DIS_SHIFT; |
| 640 | |
Jeff McGee | 9705ad8 | 2015-04-03 18:13:15 -0700 | [diff] [blame] | 641 | info->slice_total = hweight32(s_enable); |
| 642 | /* |
| 643 | * The subslice disable field is global, i.e. it applies |
| 644 | * to each of the enabled slices. |
| 645 | */ |
| 646 | info->subslice_per_slice = ss_max - hweight32(ss_disable); |
| 647 | info->subslice_total = info->slice_total * |
| 648 | info->subslice_per_slice; |
| 649 | |
| 650 | /* |
| 651 | * Iterate through enabled slices and subslices to |
| 652 | * count the total enabled EU. |
| 653 | */ |
| 654 | for (s = 0; s < s_max; s++) { |
| 655 | if (!(s_enable & (0x1 << s))) |
| 656 | /* skip disabled slice */ |
| 657 | continue; |
| 658 | |
Jeff McGee | dead16e | 2015-04-03 18:13:16 -0700 | [diff] [blame] | 659 | eu_disable = I915_READ(GEN9_EU_DISABLE(s)); |
Jeff McGee | 9705ad8 | 2015-04-03 18:13:15 -0700 | [diff] [blame] | 660 | for (ss = 0; ss < ss_max; ss++) { |
Jeff McGee | dead16e | 2015-04-03 18:13:16 -0700 | [diff] [blame] | 661 | int eu_per_ss; |
Jeff McGee | 9705ad8 | 2015-04-03 18:13:15 -0700 | [diff] [blame] | 662 | |
| 663 | if (ss_disable & (0x1 << ss)) |
| 664 | /* skip disabled subslice */ |
| 665 | continue; |
| 666 | |
Jeff McGee | dead16e | 2015-04-03 18:13:16 -0700 | [diff] [blame] | 667 | eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) & |
| 668 | eu_mask); |
Jeff McGee | 9705ad8 | 2015-04-03 18:13:15 -0700 | [diff] [blame] | 669 | |
| 670 | /* |
| 671 | * Record which subslice(s) has(have) 7 EUs. we |
| 672 | * can tune the hash used to spread work among |
| 673 | * subslices if they are unbalanced. |
| 674 | */ |
Jeff McGee | dead16e | 2015-04-03 18:13:16 -0700 | [diff] [blame] | 675 | if (eu_per_ss == 7) |
Jeff McGee | 9705ad8 | 2015-04-03 18:13:15 -0700 | [diff] [blame] | 676 | info->subslice_7eu[s] |= 1 << ss; |
| 677 | |
Jeff McGee | dead16e | 2015-04-03 18:13:16 -0700 | [diff] [blame] | 678 | info->eu_total += eu_per_ss; |
Jeff McGee | 9705ad8 | 2015-04-03 18:13:15 -0700 | [diff] [blame] | 679 | } |
| 680 | } |
| 681 | |
| 682 | /* |
| 683 | * SKL is expected to always have a uniform distribution |
| 684 | * of EU across subslices with the exception that any one |
| 685 | * EU in any one subslice may be fused off for die |
Jeff McGee | dead16e | 2015-04-03 18:13:16 -0700 | [diff] [blame] | 686 | * recovery. BXT is expected to be perfectly uniform in EU |
| 687 | * distribution. |
Jeff McGee | 9705ad8 | 2015-04-03 18:13:15 -0700 | [diff] [blame] | 688 | */ |
| 689 | info->eu_per_subslice = info->subslice_total ? |
| 690 | DIV_ROUND_UP(info->eu_total, |
| 691 | info->subslice_total) : 0; |
| 692 | /* |
| 693 | * SKL supports slice power gating on devices with more than |
| 694 | * one slice, and supports EU power gating on devices with |
Jeff McGee | dead16e | 2015-04-03 18:13:16 -0700 | [diff] [blame] | 695 | * more than one EU pair per subslice. BXT supports subslice |
| 696 | * power gating on devices with more than one subslice, and |
| 697 | * supports EU power gating on devices with more than one EU |
| 698 | * pair per subslice. |
Jeff McGee | 9705ad8 | 2015-04-03 18:13:15 -0700 | [diff] [blame] | 699 | */ |
Jeff McGee | dead16e | 2015-04-03 18:13:16 -0700 | [diff] [blame] | 700 | info->has_slice_pg = (IS_SKYLAKE(dev) && (info->slice_total > 1)); |
| 701 | info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1)); |
| 702 | info->has_eu_pg = (info->eu_per_subslice > 2); |
Jeff McGee | 9705ad8 | 2015-04-03 18:13:15 -0700 | [diff] [blame] | 703 | } |
| 704 | |
Łukasz Daniluk | 91bedd3 | 2015-09-25 11:54:58 +0200 | [diff] [blame] | 705 | static void broadwell_sseu_info_init(struct drm_device *dev) |
| 706 | { |
| 707 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 708 | struct intel_device_info *info; |
| 709 | const int s_max = 3, ss_max = 3, eu_max = 8; |
| 710 | int s, ss; |
| 711 | u32 fuse2, eu_disable[s_max], s_enable, ss_disable; |
| 712 | |
| 713 | fuse2 = I915_READ(GEN8_FUSE2); |
| 714 | s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; |
| 715 | ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT; |
| 716 | |
| 717 | eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK; |
| 718 | eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) | |
| 719 | ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) << |
| 720 | (32 - GEN8_EU_DIS0_S1_SHIFT)); |
| 721 | eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) | |
| 722 | ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) << |
| 723 | (32 - GEN8_EU_DIS1_S2_SHIFT)); |
| 724 | |
| 725 | |
| 726 | info = (struct intel_device_info *)&dev_priv->info; |
| 727 | info->slice_total = hweight32(s_enable); |
| 728 | |
| 729 | /* |
| 730 | * The subslice disable field is global, i.e. it applies |
| 731 | * to each of the enabled slices. |
| 732 | */ |
| 733 | info->subslice_per_slice = ss_max - hweight32(ss_disable); |
| 734 | info->subslice_total = info->slice_total * info->subslice_per_slice; |
| 735 | |
| 736 | /* |
| 737 | * Iterate through enabled slices and subslices to |
| 738 | * count the total enabled EU. |
| 739 | */ |
| 740 | for (s = 0; s < s_max; s++) { |
| 741 | if (!(s_enable & (0x1 << s))) |
| 742 | /* skip disabled slice */ |
| 743 | continue; |
| 744 | |
| 745 | for (ss = 0; ss < ss_max; ss++) { |
| 746 | u32 n_disabled; |
| 747 | |
| 748 | if (ss_disable & (0x1 << ss)) |
| 749 | /* skip disabled subslice */ |
| 750 | continue; |
| 751 | |
| 752 | n_disabled = hweight8(eu_disable[s] >> (ss * eu_max)); |
| 753 | |
| 754 | /* |
| 755 | * Record which subslices have 7 EUs. |
| 756 | */ |
| 757 | if (eu_max - n_disabled == 7) |
| 758 | info->subslice_7eu[s] |= 1 << ss; |
| 759 | |
| 760 | info->eu_total += eu_max - n_disabled; |
| 761 | } |
| 762 | } |
| 763 | |
| 764 | /* |
| 765 | * BDW is expected to always have a uniform distribution of EU across |
| 766 | * subslices with the exception that any one EU in any one subslice may |
| 767 | * be fused off for die recovery. |
| 768 | */ |
| 769 | info->eu_per_subslice = info->subslice_total ? |
| 770 | DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0; |
| 771 | |
| 772 | /* |
| 773 | * BDW supports slice power gating on devices with more than |
| 774 | * one slice. |
| 775 | */ |
| 776 | info->has_slice_pg = (info->slice_total > 1); |
| 777 | info->has_subslice_pg = 0; |
| 778 | info->has_eu_pg = 0; |
| 779 | } |
| 780 | |
Damien Lespiau | 22d3fd46 | 2014-02-07 19:12:49 +0000 | [diff] [blame] | 781 | /* |
| 782 | * Determine various intel_device_info fields at runtime. |
| 783 | * |
| 784 | * Use it when either: |
| 785 | * - it's judged too laborious to fill n static structures with the limit |
| 786 | * when a simple if statement does the job, |
| 787 | * - run-time checks (eg read fuse/strap registers) are needed. |
Damien Lespiau | 658ac4c | 2014-02-10 17:19:45 +0000 | [diff] [blame] | 788 | * |
| 789 | * This function needs to be called: |
| 790 | * - after the MMIO has been setup as we are reading registers, |
| 791 | * - after the PCH has been detected, |
| 792 | * - before the first usage of the fields it can tweak. |
Damien Lespiau | 22d3fd46 | 2014-02-07 19:12:49 +0000 | [diff] [blame] | 793 | */ |
| 794 | static void intel_device_info_runtime_init(struct drm_device *dev) |
| 795 | { |
Damien Lespiau | 658ac4c | 2014-02-10 17:19:45 +0000 | [diff] [blame] | 796 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 22d3fd46 | 2014-02-07 19:12:49 +0000 | [diff] [blame] | 797 | struct intel_device_info *info; |
Damien Lespiau | d615a16 | 2014-03-03 17:31:48 +0000 | [diff] [blame] | 798 | enum pipe pipe; |
Damien Lespiau | 22d3fd46 | 2014-02-07 19:12:49 +0000 | [diff] [blame] | 799 | |
Damien Lespiau | 658ac4c | 2014-02-10 17:19:45 +0000 | [diff] [blame] | 800 | info = (struct intel_device_info *)&dev_priv->info; |
Damien Lespiau | 22d3fd46 | 2014-02-07 19:12:49 +0000 | [diff] [blame] | 801 | |
Damien Lespiau | edd43ed | 2015-07-16 17:08:08 +0100 | [diff] [blame] | 802 | /* |
| 803 | * Skylake and Broxton currently don't expose the topmost plane as its |
| 804 | * use is exclusive with the legacy cursor and we only want to expose |
| 805 | * one of those, not both. Until we can safely expose the topmost plane |
| 806 | * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, |
| 807 | * we don't expose the topmost plane at all to prevent ABI breakage |
| 808 | * down the line. |
| 809 | */ |
Damien Lespiau | 8fb9397 | 2015-03-17 11:39:32 +0200 | [diff] [blame] | 810 | if (IS_BROXTON(dev)) { |
Damien Lespiau | edd43ed | 2015-07-16 17:08:08 +0100 | [diff] [blame] | 811 | info->num_sprites[PIPE_A] = 2; |
| 812 | info->num_sprites[PIPE_B] = 2; |
| 813 | info->num_sprites[PIPE_C] = 1; |
| 814 | } else if (IS_VALLEYVIEW(dev)) |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 815 | for_each_pipe(dev_priv, pipe) |
Damien Lespiau | d615a16 | 2014-03-03 17:31:48 +0000 | [diff] [blame] | 816 | info->num_sprites[pipe] = 2; |
| 817 | else |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 818 | for_each_pipe(dev_priv, pipe) |
Damien Lespiau | d615a16 | 2014-03-03 17:31:48 +0000 | [diff] [blame] | 819 | info->num_sprites[pipe] = 1; |
Damien Lespiau | 658ac4c | 2014-02-10 17:19:45 +0000 | [diff] [blame] | 820 | |
Damien Lespiau | a0bae57 | 2014-02-10 17:20:55 +0000 | [diff] [blame] | 821 | if (i915.disable_display) { |
| 822 | DRM_INFO("Display disabled (module parameter)\n"); |
| 823 | info->num_pipes = 0; |
| 824 | } else if (info->num_pipes > 0 && |
| 825 | (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) && |
| 826 | !IS_VALLEYVIEW(dev)) { |
Damien Lespiau | 658ac4c | 2014-02-10 17:19:45 +0000 | [diff] [blame] | 827 | u32 fuse_strap = I915_READ(FUSE_STRAP); |
| 828 | u32 sfuse_strap = I915_READ(SFUSE_STRAP); |
| 829 | |
| 830 | /* |
| 831 | * SFUSE_STRAP is supposed to have a bit signalling the display |
| 832 | * is fused off. Unfortunately it seems that, at least in |
| 833 | * certain cases, fused off display means that PCH display |
| 834 | * reads don't land anywhere. In that case, we read 0s. |
| 835 | * |
| 836 | * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK |
| 837 | * should be set when taking over after the firmware. |
| 838 | */ |
| 839 | if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || |
| 840 | sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || |
| 841 | (dev_priv->pch_type == PCH_CPT && |
| 842 | !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { |
| 843 | DRM_INFO("Display fused off, disabling\n"); |
| 844 | info->num_pipes = 0; |
| 845 | } |
| 846 | } |
Deepak S | 693d11c | 2015-01-16 20:42:16 +0530 | [diff] [blame] | 847 | |
Jeff McGee | 3873218 | 2015-02-13 10:27:54 -0600 | [diff] [blame] | 848 | /* Initialize slice/subslice/EU info */ |
Jeff McGee | 9705ad8 | 2015-04-03 18:13:15 -0700 | [diff] [blame] | 849 | if (IS_CHERRYVIEW(dev)) |
| 850 | cherryview_sseu_info_init(dev); |
Łukasz Daniluk | 91bedd3 | 2015-09-25 11:54:58 +0200 | [diff] [blame] | 851 | else if (IS_BROADWELL(dev)) |
| 852 | broadwell_sseu_info_init(dev); |
Jeff McGee | dead16e | 2015-04-03 18:13:16 -0700 | [diff] [blame] | 853 | else if (INTEL_INFO(dev)->gen >= 9) |
Jeff McGee | 9705ad8 | 2015-04-03 18:13:15 -0700 | [diff] [blame] | 854 | gen9_sseu_info_init(dev); |
Deepak S | 693d11c | 2015-01-16 20:42:16 +0530 | [diff] [blame] | 855 | |
Jeff McGee | 3873218 | 2015-02-13 10:27:54 -0600 | [diff] [blame] | 856 | DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total); |
| 857 | DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total); |
| 858 | DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice); |
| 859 | DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total); |
| 860 | DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice); |
| 861 | DRM_DEBUG_DRIVER("has slice power gating: %s\n", |
| 862 | info->has_slice_pg ? "y" : "n"); |
| 863 | DRM_DEBUG_DRIVER("has subslice power gating: %s\n", |
| 864 | info->has_subslice_pg ? "y" : "n"); |
| 865 | DRM_DEBUG_DRIVER("has EU power gating: %s\n", |
| 866 | info->has_eu_pg ? "y" : "n"); |
Damien Lespiau | 22d3fd46 | 2014-02-07 19:12:49 +0000 | [diff] [blame] | 867 | } |
| 868 | |
Ville Syrjälä | e27f299 | 2015-07-08 23:45:50 +0300 | [diff] [blame] | 869 | static void intel_init_dpio(struct drm_i915_private *dev_priv) |
| 870 | { |
| 871 | if (!IS_VALLEYVIEW(dev_priv)) |
| 872 | return; |
| 873 | |
| 874 | /* |
| 875 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), |
| 876 | * CHV x1 PHY (DP/HDMI D) |
| 877 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) |
| 878 | */ |
| 879 | if (IS_CHERRYVIEW(dev_priv)) { |
| 880 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; |
| 881 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; |
| 882 | } else { |
| 883 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
| 884 | } |
| 885 | } |
| 886 | |
Eric Anholt | 63ee41d | 2010-12-20 18:40:06 -0800 | [diff] [blame] | 887 | /** |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 888 | * i915_driver_load - setup chip and create an initial config |
| 889 | * @dev: DRM device |
| 890 | * @flags: startup flags |
| 891 | * |
| 892 | * The driver load routine has to do several things: |
| 893 | * - drive output discovery via intel_modeset_init() |
| 894 | * - initialize the memory manager |
| 895 | * - allocate initial config memory |
| 896 | * - setup the DRM framebuffer with the allocated memory |
| 897 | */ |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 898 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 899 | { |
Luca Tettamanti | ea059a1 | 2010-04-08 21:41:59 +0200 | [diff] [blame] | 900 | struct drm_i915_private *dev_priv; |
Damien Lespiau | 5c969aa | 2014-02-07 19:12:48 +0000 | [diff] [blame] | 901 | struct intel_device_info *info, *device_info; |
Chris Wilson | 934d608 | 2012-09-14 11:57:46 +0100 | [diff] [blame] | 902 | int ret = 0, mmio_bar, mmio_size; |
Daniel Vetter | 9021f28 | 2012-03-26 09:45:41 +0200 | [diff] [blame] | 903 | uint32_t aperture_size; |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 904 | |
Daniel Vetter | 26394d9 | 2012-03-26 21:33:18 +0200 | [diff] [blame] | 905 | info = (struct intel_device_info *) flags; |
| 906 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 907 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 908 | if (dev_priv == NULL) |
| 909 | return -ENOMEM; |
| 910 | |
Damien Lespiau | 755f68f | 2014-07-10 14:52:43 +0100 | [diff] [blame] | 911 | dev->dev_private = dev_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 912 | dev_priv->dev = dev; |
Damien Lespiau | 5c969aa | 2014-02-07 19:12:48 +0000 | [diff] [blame] | 913 | |
Chris Wilson | 87f1f46 | 2014-08-09 19:18:42 +0100 | [diff] [blame] | 914 | /* Setup the write-once "constant" device info */ |
Damien Lespiau | 5c969aa | 2014-02-07 19:12:48 +0000 | [diff] [blame] | 915 | device_info = (struct intel_device_info *)&dev_priv->info; |
Chris Wilson | 87f1f46 | 2014-08-09 19:18:42 +0100 | [diff] [blame] | 916 | memcpy(device_info, info, sizeof(dev_priv->info)); |
| 917 | device_info->device_id = dev->pdev->device; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 918 | |
Konstantin Khlebnikov | 7dcd267 | 2013-07-17 10:22:58 +0400 | [diff] [blame] | 919 | spin_lock_init(&dev_priv->irq_lock); |
| 920 | spin_lock_init(&dev_priv->gpu_error.lock); |
Daniel Vetter | 07f11d4 | 2014-09-15 14:35:09 +0200 | [diff] [blame] | 921 | mutex_init(&dev_priv->backlight_lock); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 922 | spin_lock_init(&dev_priv->uncore.lock); |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 923 | spin_lock_init(&dev_priv->mm.object_stat_lock); |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 924 | spin_lock_init(&dev_priv->mmio_flip_lock); |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 925 | mutex_init(&dev_priv->sb_lock); |
Konstantin Khlebnikov | 7dcd267 | 2013-07-17 10:22:58 +0400 | [diff] [blame] | 926 | mutex_init(&dev_priv->modeset_restore_lock); |
Daniel Vetter | eb80562 | 2015-05-04 14:58:44 +0200 | [diff] [blame] | 927 | mutex_init(&dev_priv->csr_lock); |
Konstantin Khlebnikov | 7dcd267 | 2013-07-17 10:22:58 +0400 | [diff] [blame] | 928 | |
Daniel Vetter | f742a55 | 2013-12-06 10:17:53 +0100 | [diff] [blame] | 929 | intel_pm_setup(dev); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 930 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 931 | intel_display_crc_init(dev); |
| 932 | |
Daniel Vetter | c96ea64 | 2012-08-08 22:01:51 +0200 | [diff] [blame] | 933 | i915_dump_device_info(dev_priv); |
| 934 | |
Paulo Zanoni | ed1c9e2 | 2013-08-12 14:34:08 -0300 | [diff] [blame] | 935 | /* Not all pre-production machines fall into this category, only the |
| 936 | * very first ones. Almost everything should work, except for maybe |
| 937 | * suspend/resume. And we don't implement workarounds that affect only |
| 938 | * pre-production machines. */ |
| 939 | if (IS_HSW_EARLY_SDV(dev)) |
| 940 | DRM_INFO("This is an early pre-production Haswell machine. " |
| 941 | "It may not be fully functional.\n"); |
| 942 | |
Dave Airlie | ec2a4c3 | 2009-08-04 11:43:41 +1000 | [diff] [blame] | 943 | if (i915_get_bridge_dev(dev)) { |
| 944 | ret = -EIO; |
| 945 | goto free_priv; |
| 946 | } |
| 947 | |
Ben Widawsky | 1e1bd0f | 2013-04-08 18:43:49 -0700 | [diff] [blame] | 948 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
| 949 | /* Before gen4, the registers and the GTT are behind different BARs. |
| 950 | * However, from gen4 onwards, the registers and the GTT are shared |
| 951 | * in the same BAR, so we want to restrict this ioremap from |
| 952 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, |
| 953 | * the register BAR remains the same size for all the earlier |
| 954 | * generations up to Ironlake. |
| 955 | */ |
| 956 | if (info->gen < 5) |
| 957 | mmio_size = 512*1024; |
| 958 | else |
| 959 | mmio_size = 2*1024*1024; |
| 960 | |
| 961 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size); |
| 962 | if (!dev_priv->regs) { |
| 963 | DRM_ERROR("failed to map registers\n"); |
| 964 | ret = -EIO; |
| 965 | goto put_bridge; |
| 966 | } |
| 967 | |
Ben Widawsky | c3d685a | 2013-10-08 16:31:03 -0700 | [diff] [blame] | 968 | /* This must be called before any calls to HAS_PCH_* */ |
| 969 | intel_detect_pch(dev); |
| 970 | |
| 971 | intel_uncore_init(dev); |
| 972 | |
Daniel Vetter | eb80562 | 2015-05-04 14:58:44 +0200 | [diff] [blame] | 973 | /* Load CSR Firmware for SKL */ |
| 974 | intel_csr_ucode_init(dev); |
| 975 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 976 | ret = i915_gem_gtt_init(dev); |
| 977 | if (ret) |
Daniel Vetter | eb80562 | 2015-05-04 14:58:44 +0200 | [diff] [blame] | 978 | goto out_freecsr; |
Daniel Vetter | e188719 | 2012-06-12 11:28:17 +0200 | [diff] [blame] | 979 | |
Daniel Vetter | 17fa646 | 2015-02-23 12:03:25 +0100 | [diff] [blame] | 980 | /* WARNING: Apparently we must kick fbdev drivers before vgacon, |
| 981 | * otherwise the vga fbdev driver falls over. */ |
| 982 | ret = i915_kick_out_firmware_fb(dev_priv); |
| 983 | if (ret) { |
| 984 | DRM_ERROR("failed to remove conflicting framebuffer drivers\n"); |
| 985 | goto out_gtt; |
| 986 | } |
Daniel Vetter | 0485c9d | 2014-11-14 10:09:49 +0100 | [diff] [blame] | 987 | |
Daniel Vetter | 17fa646 | 2015-02-23 12:03:25 +0100 | [diff] [blame] | 988 | ret = i915_kick_out_vgacon(dev_priv); |
| 989 | if (ret) { |
| 990 | DRM_ERROR("failed to remove conflicting VGA console\n"); |
| 991 | goto out_gtt; |
Daniel Vetter | a4de052 | 2014-06-05 16:20:46 +0200 | [diff] [blame] | 992 | } |
Daniel Vetter | e188719 | 2012-06-12 11:28:17 +0200 | [diff] [blame] | 993 | |
Dave Airlie | 466e69b | 2011-12-19 11:15:29 +0000 | [diff] [blame] | 994 | pci_set_master(dev->pdev); |
| 995 | |
Daniel Vetter | 9f82d23 | 2010-08-30 21:25:23 +0200 | [diff] [blame] | 996 | /* overlay on gen2 is broken and can't address above 1G */ |
| 997 | if (IS_GEN2(dev)) |
| 998 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); |
| 999 | |
Jan Niehusmann | 6927faf | 2011-03-01 23:24:16 +0100 | [diff] [blame] | 1000 | /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
| 1001 | * using 32bit addressing, overwriting memory if HWS is located |
| 1002 | * above 4GB. |
| 1003 | * |
| 1004 | * The documentation also mentions an issue with undefined |
| 1005 | * behaviour if any general state is accessed within a page above 4GB, |
| 1006 | * which also needs to be handled carefully. |
| 1007 | */ |
| 1008 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
| 1009 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); |
| 1010 | |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 1011 | aperture_size = dev_priv->gtt.mappable_end; |
Chris Wilson | 71e9339 | 2010-10-27 18:46:52 +0100 | [diff] [blame] | 1012 | |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 1013 | dev_priv->gtt.mappable = |
| 1014 | io_mapping_create_wc(dev_priv->gtt.mappable_base, |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1015 | aperture_size); |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 1016 | if (dev_priv->gtt.mappable == NULL) { |
Venkatesh Pallipadi | 6644107 | 2009-02-24 17:35:11 -0800 | [diff] [blame] | 1017 | ret = -EIO; |
Chris Wilson | cbb47d1 | 2013-09-23 17:33:20 -0300 | [diff] [blame] | 1018 | goto out_gtt; |
Venkatesh Pallipadi | 6644107 | 2009-02-24 17:35:11 -0800 | [diff] [blame] | 1019 | } |
| 1020 | |
Ben Widawsky | 911bdf0 | 2013-06-27 16:30:23 -0700 | [diff] [blame] | 1021 | dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base, |
| 1022 | aperture_size); |
Eric Anholt | ab657db1 | 2009-01-23 12:57:47 -0800 | [diff] [blame] | 1023 | |
Chris Wilson | e642abb | 2010-09-09 12:46:34 +0100 | [diff] [blame] | 1024 | /* The i915 workqueue is primarily used for batched retirement of |
| 1025 | * requests (and thus managing bo) once the task has been completed |
| 1026 | * by the GPU. i915_gem_retire_requests() is called directly when we |
| 1027 | * need high-priority retirement, such as waiting for an explicit |
| 1028 | * bo. |
| 1029 | * |
| 1030 | * It is also used for periodic low-priority events, such as |
Eric Anholt | df9c204 | 2010-11-18 09:31:12 +0800 | [diff] [blame] | 1031 | * idle-timers and recording error state. |
Chris Wilson | e642abb | 2010-09-09 12:46:34 +0100 | [diff] [blame] | 1032 | * |
| 1033 | * All tasks on the workqueue are expected to acquire the dev mutex |
| 1034 | * so there is no point in running more than one instance of the |
Tejun Heo | 5362186 | 2012-08-22 16:40:57 -0700 | [diff] [blame] | 1035 | * workqueue at any time. Use an ordered one. |
Chris Wilson | e642abb | 2010-09-09 12:46:34 +0100 | [diff] [blame] | 1036 | */ |
Tejun Heo | 5362186 | 2012-08-22 16:40:57 -0700 | [diff] [blame] | 1037 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1038 | if (dev_priv->wq == NULL) { |
| 1039 | DRM_ERROR("Failed to create our workqueue.\n"); |
| 1040 | ret = -ENOMEM; |
Keith Packard | a7b85d2 | 2011-07-10 13:12:17 -0700 | [diff] [blame] | 1041 | goto out_mtrrfree; |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1042 | } |
| 1043 | |
Jani Nikula | 5fcece8 | 2015-05-27 15:03:42 +0300 | [diff] [blame] | 1044 | dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); |
| 1045 | if (dev_priv->hotplug.dp_wq == NULL) { |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 1046 | DRM_ERROR("Failed to create our dp workqueue.\n"); |
| 1047 | ret = -ENOMEM; |
| 1048 | goto out_freewq; |
| 1049 | } |
| 1050 | |
Chris Wilson | 737b150 | 2015-01-26 18:03:03 +0200 | [diff] [blame] | 1051 | dev_priv->gpu_error.hangcheck_wq = |
| 1052 | alloc_ordered_workqueue("i915-hangcheck", 0); |
| 1053 | if (dev_priv->gpu_error.hangcheck_wq == NULL) { |
| 1054 | DRM_ERROR("Failed to create our hangcheck workqueue.\n"); |
| 1055 | ret = -ENOMEM; |
| 1056 | goto out_freedpwq; |
| 1057 | } |
| 1058 | |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 1059 | intel_irq_init(dev_priv); |
Ben Widawsky | 78511f2 | 2013-10-04 21:22:49 -0700 | [diff] [blame] | 1060 | intel_uncore_sanitize(dev); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 1061 | |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1062 | /* Try to make sure MCHBAR is enabled before poking at it */ |
| 1063 | intel_setup_mchbar(dev); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1064 | intel_setup_gmbus(dev); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1065 | intel_opregion_setup(dev); |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1066 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1067 | i915_gem_load(dev); |
| 1068 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1069 | /* On the 945G/GM, the chipset reports the MSI capability on the |
| 1070 | * integrated graphics even though the support isn't actually there |
| 1071 | * according to the published specs. It doesn't appear to function |
| 1072 | * correctly in testing on 945G. |
| 1073 | * This may be a side effect of MSI having been made available for PEG |
| 1074 | * and the registers being closely associated. |
Keith Packard | d1ed629 | 2008-10-17 00:44:42 -0700 | [diff] [blame] | 1075 | * |
| 1076 | * According to chipset errata, on the 965GM, MSI interrupts may |
Keith Packard | b60678a | 2008-12-08 11:12:28 -0800 | [diff] [blame] | 1077 | * be lost or delayed, but we use them anyways to avoid |
| 1078 | * stuck interrupts on some machines. |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1079 | */ |
Keith Packard | b60678a | 2008-12-08 11:12:28 -0800 | [diff] [blame] | 1080 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
Eric Anholt | d3e74d0 | 2008-11-03 14:46:17 -0800 | [diff] [blame] | 1081 | pci_enable_msi(dev->pdev); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1082 | |
Damien Lespiau | 22d3fd46 | 2014-02-07 19:12:49 +0000 | [diff] [blame] | 1083 | intel_device_info_runtime_init(dev); |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 1084 | |
Ville Syrjälä | e27f299 | 2015-07-08 23:45:50 +0300 | [diff] [blame] | 1085 | intel_init_dpio(dev_priv); |
| 1086 | |
Ben Widawsky | e3c7475 | 2013-04-05 13:12:39 -0700 | [diff] [blame] | 1087 | if (INTEL_INFO(dev)->num_pipes) { |
| 1088 | ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes); |
| 1089 | if (ret) |
| 1090 | goto out_gem_unload; |
| 1091 | } |
Keith Packard | 5244021 | 2008-11-18 09:30:25 -0800 | [diff] [blame] | 1092 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 1093 | intel_power_domains_init(dev_priv); |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 1094 | |
Daniel Vetter | 17fa646 | 2015-02-23 12:03:25 +0100 | [diff] [blame] | 1095 | ret = i915_load_modeset_init(dev); |
| 1096 | if (ret < 0) { |
| 1097 | DRM_ERROR("failed to init modeset\n"); |
| 1098 | goto out_power_well; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1099 | } |
| 1100 | |
Yu Zhang | e21fd55 | 2015-02-10 19:05:51 +0800 | [diff] [blame] | 1101 | /* |
| 1102 | * Notify a valid surface after modesetting, |
| 1103 | * when running inside a VM. |
| 1104 | */ |
| 1105 | if (intel_vgpu_active(dev)) |
| 1106 | I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY); |
| 1107 | |
Ben Widawsky | 0136db58 | 2012-04-10 21:17:01 -0700 | [diff] [blame] | 1108 | i915_setup_sysfs(dev); |
| 1109 | |
Ben Widawsky | e3c7475 | 2013-04-05 13:12:39 -0700 | [diff] [blame] | 1110 | if (INTEL_INFO(dev)->num_pipes) { |
| 1111 | /* Must be done after probing outputs */ |
| 1112 | intel_opregion_init(dev); |
Rafael J. Wysocki | 8e5c2b7 | 2013-07-25 21:43:39 +0200 | [diff] [blame] | 1113 | acpi_video_register(); |
Ben Widawsky | e3c7475 | 2013-04-05 13:12:39 -0700 | [diff] [blame] | 1114 | } |
Matthew Garrett | 74a365b | 2009-03-19 21:35:39 +0000 | [diff] [blame] | 1115 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 1116 | if (IS_GEN5(dev)) |
| 1117 | intel_gpu_ips_init(dev_priv); |
Eric Anholt | 63ee41d | 2010-12-20 18:40:06 -0800 | [diff] [blame] | 1118 | |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 1119 | intel_runtime_pm_enable(dev_priv); |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 1120 | |
Imre Deak | 58fddc2 | 2015-01-08 17:54:14 +0200 | [diff] [blame] | 1121 | i915_audio_component_init(dev_priv); |
| 1122 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1123 | return 0; |
| 1124 | |
Chris Wilson | cbb47d1 | 2013-09-23 17:33:20 -0300 | [diff] [blame] | 1125 | out_power_well: |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 1126 | intel_power_domains_fini(dev_priv); |
Chris Wilson | cbb47d1 | 2013-09-23 17:33:20 -0300 | [diff] [blame] | 1127 | drm_vblank_cleanup(dev); |
Chris Wilson | 56e2ea3 | 2010-11-08 17:10:29 +0000 | [diff] [blame] | 1128 | out_gem_unload: |
Imre Deak | 4bdc729 | 2014-05-20 19:47:20 +0300 | [diff] [blame] | 1129 | WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier)); |
| 1130 | unregister_shrinker(&dev_priv->mm.shrinker); |
Keith Packard | a7b85d2 | 2011-07-10 13:12:17 -0700 | [diff] [blame] | 1131 | |
Chris Wilson | 56e2ea3 | 2010-11-08 17:10:29 +0000 | [diff] [blame] | 1132 | if (dev->pdev->msi_enabled) |
| 1133 | pci_disable_msi(dev->pdev); |
| 1134 | |
| 1135 | intel_teardown_gmbus(dev); |
| 1136 | intel_teardown_mchbar(dev); |
Stanislaw Gruszka | 22accca | 2014-01-25 10:13:37 +0100 | [diff] [blame] | 1137 | pm_qos_remove_request(&dev_priv->pm_qos); |
Chris Wilson | 737b150 | 2015-01-26 18:03:03 +0200 | [diff] [blame] | 1138 | destroy_workqueue(dev_priv->gpu_error.hangcheck_wq); |
| 1139 | out_freedpwq: |
Jani Nikula | 5fcece8 | 2015-05-27 15:03:42 +0300 | [diff] [blame] | 1140 | destroy_workqueue(dev_priv->hotplug.dp_wq); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 1141 | out_freewq: |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1142 | destroy_workqueue(dev_priv->wq); |
Keith Packard | a7b85d2 | 2011-07-10 13:12:17 -0700 | [diff] [blame] | 1143 | out_mtrrfree: |
Ben Widawsky | 911bdf0 | 2013-06-27 16:30:23 -0700 | [diff] [blame] | 1144 | arch_phys_wc_del(dev_priv->gtt.mtrr); |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 1145 | io_mapping_free(dev_priv->gtt.mappable); |
Chris Wilson | cbb47d1 | 2013-09-23 17:33:20 -0300 | [diff] [blame] | 1146 | out_gtt: |
Daniel Vetter | 90d0a0e | 2014-08-06 15:04:56 +0200 | [diff] [blame] | 1147 | i915_global_gtt_cleanup(dev); |
Daniel Vetter | eb80562 | 2015-05-04 14:58:44 +0200 | [diff] [blame] | 1148 | out_freecsr: |
| 1149 | intel_csr_ucode_fini(dev); |
Ben Widawsky | c3d685a | 2013-10-08 16:31:03 -0700 | [diff] [blame] | 1150 | intel_uncore_fini(dev); |
Chris Wilson | 6dda569 | 2010-10-29 21:02:18 +0100 | [diff] [blame] | 1151 | pci_iounmap(dev->pdev, dev_priv->regs); |
Dave Airlie | ec2a4c3 | 2009-08-04 11:43:41 +1000 | [diff] [blame] | 1152 | put_bridge: |
| 1153 | pci_dev_put(dev_priv->bridge_dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1154 | free_priv: |
Julia Lawall | 76b1cf2 | 2015-09-13 14:15:25 +0200 | [diff] [blame] | 1155 | kmem_cache_destroy(dev_priv->requests); |
| 1156 | kmem_cache_destroy(dev_priv->vmas); |
| 1157 | kmem_cache_destroy(dev_priv->objects); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1158 | kfree(dev_priv); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1159 | return ret; |
| 1160 | } |
| 1161 | |
| 1162 | int i915_driver_unload(struct drm_device *dev) |
| 1163 | { |
| 1164 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c911fc1 | 2010-08-20 21:23:20 +0200 | [diff] [blame] | 1165 | int ret; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1166 | |
Imre Deak | 58fddc2 | 2015-01-08 17:54:14 +0200 | [diff] [blame] | 1167 | i915_audio_component_cleanup(dev_priv); |
| 1168 | |
Chris Wilson | ce58c32 | 2013-12-02 11:26:07 -0200 | [diff] [blame] | 1169 | ret = i915_gem_suspend(dev); |
| 1170 | if (ret) { |
| 1171 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
| 1172 | return ret; |
| 1173 | } |
| 1174 | |
Daniel Vetter | 41373cd | 2014-09-30 10:56:41 +0200 | [diff] [blame] | 1175 | intel_power_domains_fini(dev_priv); |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 1176 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 1177 | intel_gpu_ips_teardown(); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1178 | |
Ben Widawsky | 0136db58 | 2012-04-10 21:17:01 -0700 | [diff] [blame] | 1179 | i915_teardown_sysfs(dev); |
| 1180 | |
Imre Deak | 4bdc729 | 2014-05-20 19:47:20 +0300 | [diff] [blame] | 1181 | WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier)); |
| 1182 | unregister_shrinker(&dev_priv->mm.shrinker); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 1183 | |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 1184 | io_mapping_free(dev_priv->gtt.mappable); |
Ben Widawsky | 911bdf0 | 2013-06-27 16:30:23 -0700 | [diff] [blame] | 1185 | arch_phys_wc_del(dev_priv->gtt.mtrr); |
Eric Anholt | ab657db1 | 2009-01-23 12:57:47 -0800 | [diff] [blame] | 1186 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1187 | acpi_video_unregister(); |
| 1188 | |
Daniel Vetter | 17fa646 | 2015-02-23 12:03:25 +0100 | [diff] [blame] | 1189 | intel_fbdev_fini(dev); |
Paulo Zanoni | 2ebfaf5 | 2014-10-15 14:15:04 -0300 | [diff] [blame] | 1190 | |
| 1191 | drm_vblank_cleanup(dev); |
| 1192 | |
Daniel Vetter | 17fa646 | 2015-02-23 12:03:25 +0100 | [diff] [blame] | 1193 | intel_modeset_cleanup(dev); |
Jesse Barnes | 3d8620c | 2010-03-26 11:07:21 -0700 | [diff] [blame] | 1194 | |
Daniel Vetter | 17fa646 | 2015-02-23 12:03:25 +0100 | [diff] [blame] | 1195 | /* |
| 1196 | * free the memory space allocated for the child device |
| 1197 | * config parsed from VBT |
| 1198 | */ |
| 1199 | if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) { |
| 1200 | kfree(dev_priv->vbt.child_dev); |
| 1201 | dev_priv->vbt.child_dev = NULL; |
| 1202 | dev_priv->vbt.child_dev_num = 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1203 | } |
Matt Roper | 9aa6114 | 2015-09-14 19:24:18 -0700 | [diff] [blame] | 1204 | kfree(dev_priv->vbt.sdvo_lvds_vbt_mode); |
| 1205 | dev_priv->vbt.sdvo_lvds_vbt_mode = NULL; |
| 1206 | kfree(dev_priv->vbt.lfp_lvds_vbt_mode); |
| 1207 | dev_priv->vbt.lfp_lvds_vbt_mode = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1208 | |
Daniel Vetter | 17fa646 | 2015-02-23 12:03:25 +0100 | [diff] [blame] | 1209 | vga_switcheroo_unregister_client(dev->pdev); |
| 1210 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
| 1211 | |
Daniel Vetter | a8b4899 | 2010-08-20 21:25:11 +0200 | [diff] [blame] | 1212 | /* Free error state after interrupts are fully disabled. */ |
Chris Wilson | 737b150 | 2015-01-26 18:03:03 +0200 | [diff] [blame] | 1213 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
Daniel Vetter | a8b4899 | 2010-08-20 21:25:11 +0200 | [diff] [blame] | 1214 | i915_destroy_error_state(dev); |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 1215 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1216 | if (dev->pdev->msi_enabled) |
| 1217 | pci_disable_msi(dev->pdev); |
| 1218 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1219 | intel_opregion_fini(dev); |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 1220 | |
Daniel Vetter | 17fa646 | 2015-02-23 12:03:25 +0100 | [diff] [blame] | 1221 | /* Flush any outstanding unpin_work. */ |
| 1222 | flush_workqueue(dev_priv->wq); |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 1223 | |
Daniel Vetter | 17fa646 | 2015-02-23 12:03:25 +0100 | [diff] [blame] | 1224 | mutex_lock(&dev->struct_mutex); |
Alex Dai | 33a732f | 2015-08-12 15:43:36 +0100 | [diff] [blame] | 1225 | intel_guc_ucode_fini(dev); |
Daniel Vetter | 17fa646 | 2015-02-23 12:03:25 +0100 | [diff] [blame] | 1226 | i915_gem_cleanup_ringbuffer(dev); |
Daniel Vetter | 17fa646 | 2015-02-23 12:03:25 +0100 | [diff] [blame] | 1227 | i915_gem_context_fini(dev); |
| 1228 | mutex_unlock(&dev->struct_mutex); |
Paulo Zanoni | 7733b49 | 2015-07-07 15:26:04 -0300 | [diff] [blame] | 1229 | intel_fbc_cleanup_cfb(dev_priv); |
Daniel Vetter | 17fa646 | 2015-02-23 12:03:25 +0100 | [diff] [blame] | 1230 | i915_gem_cleanup_stolen(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1231 | |
Daniel Vetter | eb80562 | 2015-05-04 14:58:44 +0200 | [diff] [blame] | 1232 | intel_csr_ucode_fini(dev); |
| 1233 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1234 | intel_teardown_gmbus(dev); |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1235 | intel_teardown_mchbar(dev); |
| 1236 | |
Jani Nikula | 5fcece8 | 2015-05-27 15:03:42 +0300 | [diff] [blame] | 1237 | destroy_workqueue(dev_priv->hotplug.dp_wq); |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 1238 | destroy_workqueue(dev_priv->wq); |
Chris Wilson | 737b150 | 2015-01-26 18:03:03 +0200 | [diff] [blame] | 1239 | destroy_workqueue(dev_priv->gpu_error.hangcheck_wq); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 1240 | pm_qos_remove_request(&dev_priv->pm_qos); |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 1241 | |
Daniel Vetter | 90d0a0e | 2014-08-06 15:04:56 +0200 | [diff] [blame] | 1242 | i915_global_gtt_cleanup(dev); |
Imre Deak | 6640aab | 2013-05-22 17:47:13 +0300 | [diff] [blame] | 1243 | |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 1244 | intel_uncore_fini(dev); |
| 1245 | if (dev_priv->regs != NULL) |
| 1246 | pci_iounmap(dev->pdev, dev_priv->regs); |
| 1247 | |
Julia Lawall | 76b1cf2 | 2015-09-13 14:15:25 +0200 | [diff] [blame] | 1248 | kmem_cache_destroy(dev_priv->requests); |
| 1249 | kmem_cache_destroy(dev_priv->vmas); |
| 1250 | kmem_cache_destroy(dev_priv->objects); |
Dave Airlie | ec2a4c3 | 2009-08-04 11:43:41 +1000 | [diff] [blame] | 1251 | pci_dev_put(dev_priv->bridge_dev); |
Daniel Vetter | 2206e6a | 2014-05-13 22:21:59 +0200 | [diff] [blame] | 1252 | kfree(dev_priv); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1253 | |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 1254 | return 0; |
| 1255 | } |
| 1256 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1257 | int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1258 | { |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1259 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1260 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1261 | ret = i915_gem_open(dev, file); |
| 1262 | if (ret) |
| 1263 | return ret; |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 1264 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1265 | return 0; |
| 1266 | } |
| 1267 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1268 | /** |
| 1269 | * i915_driver_lastclose - clean up after all DRM clients have exited |
| 1270 | * @dev: DRM device |
| 1271 | * |
| 1272 | * Take care of cleaning up after all DRM clients have exited. In the |
| 1273 | * mode setting case, we want to restore the kernel's initial mode (just |
| 1274 | * in case the last client left us in a bad state). |
| 1275 | * |
Daniel Vetter | 9021f28 | 2012-03-26 09:45:41 +0200 | [diff] [blame] | 1276 | * Additionally, in the non-mode setting case, we'll tear down the GTT |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1277 | * and DMA structures, since the kernel won't be using them, and clea |
| 1278 | * up any GEM state. |
| 1279 | */ |
Robin Schroer | 1a5036b | 2014-06-02 16:59:39 +0200 | [diff] [blame] | 1280 | void i915_driver_lastclose(struct drm_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1281 | { |
Daniel Vetter | 377e91b | 2014-11-19 20:36:49 +0100 | [diff] [blame] | 1282 | intel_fbdev_restore_mode(dev); |
| 1283 | vga_switcheroo_process_delayed_switch(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1284 | } |
| 1285 | |
John Harrison | 2885f6a | 2014-06-26 18:23:52 +0100 | [diff] [blame] | 1286 | void i915_driver_preclose(struct drm_device *dev, struct drm_file *file) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1287 | { |
Chris Wilson | 0d1430a | 2013-12-04 14:52:06 +0000 | [diff] [blame] | 1288 | mutex_lock(&dev->struct_mutex); |
John Harrison | 2885f6a | 2014-06-26 18:23:52 +0100 | [diff] [blame] | 1289 | i915_gem_context_close(dev, file); |
| 1290 | i915_gem_release(dev, file); |
Chris Wilson | 0d1430a | 2013-12-04 14:52:06 +0000 | [diff] [blame] | 1291 | mutex_unlock(&dev->struct_mutex); |
Ville Syrjälä | e2fcdaa | 2014-08-06 14:02:51 +0300 | [diff] [blame] | 1292 | |
Daniel Vetter | 17fa646 | 2015-02-23 12:03:25 +0100 | [diff] [blame] | 1293 | intel_modeset_preclose(dev, file); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1294 | } |
| 1295 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1296 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1297 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1298 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1299 | |
Zhao Yakui | a8ebba7 | 2014-04-17 10:37:40 +0800 | [diff] [blame] | 1300 | if (file_priv && file_priv->bsd_ring) |
| 1301 | file_priv->bsd_ring = NULL; |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1302 | kfree(file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1303 | } |
| 1304 | |
Daniel Vetter | 4feb765 | 2014-11-24 11:21:52 +0100 | [diff] [blame] | 1305 | static int |
| 1306 | i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, |
| 1307 | struct drm_file *file) |
| 1308 | { |
| 1309 | return -ENODEV; |
| 1310 | } |
| 1311 | |
Rob Clark | baa7094 | 2013-08-02 13:27:49 -0400 | [diff] [blame] | 1312 | const struct drm_ioctl_desc i915_ioctls[] = { |
Daniel Vetter | 77f3181 | 2014-11-19 21:23:55 +0100 | [diff] [blame] | 1313 | DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 1314 | DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), |
| 1315 | DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), |
| 1316 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), |
| 1317 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), |
| 1318 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), |
Kristian Høgsberg | 10ba501 | 2013-08-25 18:29:01 +0200 | [diff] [blame] | 1319 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW), |
Dave Airlie | 1b2f148 | 2010-08-14 20:20:34 +1000 | [diff] [blame] | 1320 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
Daniel Vetter | b2c606f | 2012-01-17 12:50:12 +0100 | [diff] [blame] | 1321 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), |
| 1322 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), |
| 1323 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
Daniel Vetter | 77f3181 | 2014-11-19 21:23:55 +0100 | [diff] [blame] | 1324 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), |
Daniel Vetter | b2c606f | 2012-01-17 12:50:12 +0100 | [diff] [blame] | 1325 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
Daniel Vetter | d1c1edb | 2012-04-26 23:28:01 +0200 | [diff] [blame] | 1326 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
Daniel Vetter | 77f3181 | 2014-11-19 21:23:55 +0100 | [diff] [blame] | 1327 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), |
| 1328 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), |
| 1329 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
Daniel Vetter | f548c0e | 2014-11-19 21:40:13 +0100 | [diff] [blame] | 1330 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
Dave Airlie | 1b2f148 | 2010-08-14 20:20:34 +1000 | [diff] [blame] | 1331 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), |
Kristian Høgsberg | 10ba501 | 2013-08-25 18:29:01 +0200 | [diff] [blame] | 1332 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
Daniel Vetter | 4feb765 | 2014-11-24 11:21:52 +0100 | [diff] [blame] | 1333 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), |
| 1334 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), |
Kristian Høgsberg | 10ba501 | 2013-08-25 18:29:01 +0200 | [diff] [blame] | 1335 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1336 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1337 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1338 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
Daniel Vetter | 71b14ab | 2014-11-19 20:36:47 +0100 | [diff] [blame] | 1339 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
| 1340 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
Kristian Høgsberg | 10ba501 | 2013-08-25 18:29:01 +0200 | [diff] [blame] | 1341 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1342 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1343 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1344 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1345 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1346 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1347 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1348 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1349 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1350 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
Dave Airlie | 1b2f148 | 2010-08-14 20:20:34 +1000 | [diff] [blame] | 1351 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), |
Kristian Høgsberg | 10ba501 | 2013-08-25 18:29:01 +0200 | [diff] [blame] | 1352 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
Dave Airlie | 1b2f148 | 2010-08-14 20:20:34 +1000 | [diff] [blame] | 1353 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
| 1354 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
Jesse Barnes | 8ea3086 | 2012-01-03 08:05:39 -0800 | [diff] [blame] | 1355 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
Daniel Vetter | a8265c5 | 2015-03-27 09:08:04 +0100 | [diff] [blame] | 1356 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
Kristian Høgsberg | 10ba501 | 2013-08-25 18:29:01 +0200 | [diff] [blame] | 1357 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1358 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1359 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1360 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 1361 | DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
Chris Wilson | 5cc9ed4 | 2014-05-16 14:22:37 +0100 | [diff] [blame] | 1362 | DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
Chris Wilson | c9dc0f3 | 2014-12-24 08:13:40 -0800 | [diff] [blame] | 1363 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
| 1364 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), |
Dave Airlie | c94f702 | 2005-07-07 21:03:38 +1000 | [diff] [blame] | 1365 | }; |
| 1366 | |
Damien Lespiau | f95aeb1 | 2014-06-09 14:39:49 +0100 | [diff] [blame] | 1367 | int i915_max_ioctl = ARRAY_SIZE(i915_ioctls); |