Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 NVIDIA Corporation |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | |
| 9 | #include <linux/clk.h> |
Thierry Reding | a82752e | 2014-01-31 10:02:15 +0100 | [diff] [blame] | 10 | #include <linux/debugfs.h> |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 11 | #include <linux/gpio.h> |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 12 | #include <linux/io.h> |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 13 | #include <linux/of_device.h> |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 14 | #include <linux/platform_device.h> |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 15 | #include <linux/regulator/consumer.h> |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 16 | #include <linux/reset.h> |
Thierry Reding | 306a7f9 | 2014-07-17 13:17:24 +0200 | [diff] [blame] | 17 | |
Thierry Reding | 7232398 | 2014-07-11 13:19:06 +0200 | [diff] [blame] | 18 | #include <soc/tegra/pmc.h> |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 19 | |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 20 | #include <drm/drm_atomic_helper.h> |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 21 | #include <drm/drm_dp_helper.h> |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 22 | #include <drm/drm_panel.h> |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 23 | |
| 24 | #include "dc.h" |
| 25 | #include "drm.h" |
| 26 | #include "sor.h" |
| 27 | |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 28 | #define SOR_REKEY 0x38 |
| 29 | |
| 30 | struct tegra_sor_hdmi_settings { |
| 31 | unsigned long frequency; |
| 32 | |
| 33 | u8 vcocap; |
| 34 | u8 ichpmp; |
| 35 | u8 loadadj; |
| 36 | u8 termadj; |
| 37 | u8 tx_pu; |
| 38 | u8 bg_vref; |
| 39 | |
| 40 | u8 drive_current[4]; |
| 41 | u8 preemphasis[4]; |
| 42 | }; |
| 43 | |
| 44 | #if 1 |
| 45 | static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { |
| 46 | { |
| 47 | .frequency = 54000000, |
| 48 | .vcocap = 0x0, |
| 49 | .ichpmp = 0x1, |
| 50 | .loadadj = 0x3, |
| 51 | .termadj = 0x9, |
| 52 | .tx_pu = 0x10, |
| 53 | .bg_vref = 0x8, |
| 54 | .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, |
| 55 | .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, |
| 56 | }, { |
| 57 | .frequency = 75000000, |
| 58 | .vcocap = 0x3, |
| 59 | .ichpmp = 0x1, |
| 60 | .loadadj = 0x3, |
| 61 | .termadj = 0x9, |
| 62 | .tx_pu = 0x40, |
| 63 | .bg_vref = 0x8, |
| 64 | .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, |
| 65 | .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, |
| 66 | }, { |
| 67 | .frequency = 150000000, |
| 68 | .vcocap = 0x3, |
| 69 | .ichpmp = 0x1, |
| 70 | .loadadj = 0x3, |
| 71 | .termadj = 0x9, |
| 72 | .tx_pu = 0x66, |
| 73 | .bg_vref = 0x8, |
| 74 | .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, |
| 75 | .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, |
| 76 | }, { |
| 77 | .frequency = 300000000, |
| 78 | .vcocap = 0x3, |
| 79 | .ichpmp = 0x1, |
| 80 | .loadadj = 0x3, |
| 81 | .termadj = 0x9, |
| 82 | .tx_pu = 0x66, |
| 83 | .bg_vref = 0xa, |
| 84 | .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, |
| 85 | .preemphasis = { 0x00, 0x17, 0x17, 0x17 }, |
| 86 | }, { |
| 87 | .frequency = 600000000, |
| 88 | .vcocap = 0x3, |
| 89 | .ichpmp = 0x1, |
| 90 | .loadadj = 0x3, |
| 91 | .termadj = 0x9, |
| 92 | .tx_pu = 0x66, |
| 93 | .bg_vref = 0x8, |
| 94 | .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, |
| 95 | .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, |
| 96 | }, |
| 97 | }; |
| 98 | #else |
| 99 | static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { |
| 100 | { |
| 101 | .frequency = 75000000, |
| 102 | .vcocap = 0x3, |
| 103 | .ichpmp = 0x1, |
| 104 | .loadadj = 0x3, |
| 105 | .termadj = 0x9, |
| 106 | .tx_pu = 0x40, |
| 107 | .bg_vref = 0x8, |
| 108 | .drive_current = { 0x29, 0x29, 0x29, 0x29 }, |
| 109 | .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, |
| 110 | }, { |
| 111 | .frequency = 150000000, |
| 112 | .vcocap = 0x3, |
| 113 | .ichpmp = 0x1, |
| 114 | .loadadj = 0x3, |
| 115 | .termadj = 0x9, |
| 116 | .tx_pu = 0x66, |
| 117 | .bg_vref = 0x8, |
| 118 | .drive_current = { 0x30, 0x37, 0x37, 0x37 }, |
| 119 | .preemphasis = { 0x01, 0x02, 0x02, 0x02 }, |
| 120 | }, { |
| 121 | .frequency = 300000000, |
| 122 | .vcocap = 0x3, |
| 123 | .ichpmp = 0x6, |
| 124 | .loadadj = 0x3, |
| 125 | .termadj = 0x9, |
| 126 | .tx_pu = 0x66, |
| 127 | .bg_vref = 0xf, |
| 128 | .drive_current = { 0x30, 0x37, 0x37, 0x37 }, |
| 129 | .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e }, |
| 130 | }, { |
| 131 | .frequency = 600000000, |
| 132 | .vcocap = 0x3, |
| 133 | .ichpmp = 0xa, |
| 134 | .loadadj = 0x3, |
| 135 | .termadj = 0xb, |
| 136 | .tx_pu = 0x66, |
| 137 | .bg_vref = 0xe, |
| 138 | .drive_current = { 0x35, 0x3e, 0x3e, 0x3e }, |
| 139 | .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f }, |
| 140 | }, |
| 141 | }; |
| 142 | #endif |
| 143 | |
| 144 | struct tegra_sor_soc { |
| 145 | bool supports_edp; |
| 146 | bool supports_lvds; |
| 147 | bool supports_hdmi; |
| 148 | bool supports_dp; |
| 149 | |
| 150 | const struct tegra_sor_hdmi_settings *settings; |
| 151 | unsigned int num_settings; |
| 152 | }; |
| 153 | |
| 154 | struct tegra_sor; |
| 155 | |
| 156 | struct tegra_sor_ops { |
| 157 | const char *name; |
| 158 | int (*probe)(struct tegra_sor *sor); |
| 159 | int (*remove)(struct tegra_sor *sor); |
| 160 | }; |
| 161 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 162 | struct tegra_sor { |
| 163 | struct host1x_client client; |
| 164 | struct tegra_output output; |
| 165 | struct device *dev; |
| 166 | |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 167 | const struct tegra_sor_soc *soc; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 168 | void __iomem *regs; |
| 169 | |
| 170 | struct reset_control *rst; |
| 171 | struct clk *clk_parent; |
| 172 | struct clk *clk_safe; |
| 173 | struct clk *clk_dp; |
| 174 | struct clk *clk; |
| 175 | |
Thierry Reding | 9542c23 | 2015-07-08 13:39:09 +0200 | [diff] [blame] | 176 | struct drm_dp_aux *aux; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 177 | |
Thierry Reding | dab1633 | 2015-01-26 16:04:08 +0100 | [diff] [blame] | 178 | struct drm_info_list *debugfs_files; |
| 179 | struct drm_minor *minor; |
Thierry Reding | a82752e | 2014-01-31 10:02:15 +0100 | [diff] [blame] | 180 | struct dentry *debugfs; |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 181 | |
| 182 | const struct tegra_sor_ops *ops; |
| 183 | |
| 184 | /* for HDMI 2.0 */ |
| 185 | struct tegra_sor_hdmi_settings *settings; |
| 186 | unsigned int num_settings; |
| 187 | |
| 188 | struct regulator *avdd_io_supply; |
| 189 | struct regulator *vdd_pll_supply; |
| 190 | struct regulator *hdmi_supply; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 191 | }; |
| 192 | |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 193 | struct tegra_sor_config { |
| 194 | u32 bits_per_pixel; |
| 195 | |
| 196 | u32 active_polarity; |
| 197 | u32 active_count; |
| 198 | u32 tu_size; |
| 199 | u32 active_frac; |
| 200 | u32 watermark; |
Thierry Reding | 7890b57 | 2014-06-05 16:12:46 +0200 | [diff] [blame] | 201 | |
| 202 | u32 hblank_symbols; |
| 203 | u32 vblank_symbols; |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 204 | }; |
| 205 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 206 | static inline struct tegra_sor * |
| 207 | host1x_client_to_sor(struct host1x_client *client) |
| 208 | { |
| 209 | return container_of(client, struct tegra_sor, client); |
| 210 | } |
| 211 | |
| 212 | static inline struct tegra_sor *to_sor(struct tegra_output *output) |
| 213 | { |
| 214 | return container_of(output, struct tegra_sor, output); |
| 215 | } |
| 216 | |
Thierry Reding | 28fe207 | 2015-01-26 16:02:48 +0100 | [diff] [blame] | 217 | static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned long offset) |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 218 | { |
| 219 | return readl(sor->regs + (offset << 2)); |
| 220 | } |
| 221 | |
Thierry Reding | 28fe207 | 2015-01-26 16:02:48 +0100 | [diff] [blame] | 222 | static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 223 | unsigned long offset) |
| 224 | { |
| 225 | writel(value, sor->regs + (offset << 2)); |
| 226 | } |
| 227 | |
Thierry Reding | 25bb2ce | 2015-08-03 14:23:29 +0200 | [diff] [blame^] | 228 | static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) |
| 229 | { |
| 230 | int err; |
| 231 | |
| 232 | clk_disable_unprepare(sor->clk); |
| 233 | |
| 234 | err = clk_set_parent(sor->clk, parent); |
| 235 | if (err < 0) |
| 236 | return err; |
| 237 | |
| 238 | err = clk_prepare_enable(sor->clk); |
| 239 | if (err < 0) |
| 240 | return err; |
| 241 | |
| 242 | return 0; |
| 243 | } |
| 244 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 245 | static int tegra_sor_dp_train_fast(struct tegra_sor *sor, |
| 246 | struct drm_dp_link *link) |
| 247 | { |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 248 | unsigned int i; |
| 249 | u8 pattern; |
Thierry Reding | 28fe207 | 2015-01-26 16:02:48 +0100 | [diff] [blame] | 250 | u32 value; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 251 | int err; |
| 252 | |
| 253 | /* setup lane parameters */ |
| 254 | value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) | |
| 255 | SOR_LANE_DRIVE_CURRENT_LANE2(0x40) | |
| 256 | SOR_LANE_DRIVE_CURRENT_LANE1(0x40) | |
| 257 | SOR_LANE_DRIVE_CURRENT_LANE0(0x40); |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 258 | tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 259 | |
| 260 | value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) | |
| 261 | SOR_LANE_PREEMPHASIS_LANE2(0x0f) | |
| 262 | SOR_LANE_PREEMPHASIS_LANE1(0x0f) | |
| 263 | SOR_LANE_PREEMPHASIS_LANE0(0x0f); |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 264 | tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 265 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 266 | value = SOR_LANE_POSTCURSOR_LANE3(0x00) | |
| 267 | SOR_LANE_POSTCURSOR_LANE2(0x00) | |
| 268 | SOR_LANE_POSTCURSOR_LANE1(0x00) | |
| 269 | SOR_LANE_POSTCURSOR_LANE0(0x00); |
| 270 | tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 271 | |
| 272 | /* disable LVDS mode */ |
| 273 | tegra_sor_writel(sor, 0, SOR_LVDS); |
| 274 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 275 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 276 | value |= SOR_DP_PADCTL_TX_PU_ENABLE; |
| 277 | value &= ~SOR_DP_PADCTL_TX_PU_MASK; |
| 278 | value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */ |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 279 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 280 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 281 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 282 | value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | |
| 283 | SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0; |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 284 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 285 | |
| 286 | usleep_range(10, 100); |
| 287 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 288 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 289 | value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | |
| 290 | SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 291 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 292 | |
Thierry Reding | 9542c23 | 2015-07-08 13:39:09 +0200 | [diff] [blame] | 293 | err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 294 | if (err < 0) |
| 295 | return err; |
| 296 | |
| 297 | for (i = 0, value = 0; i < link->num_lanes; i++) { |
| 298 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | |
| 299 | SOR_DP_TPG_SCRAMBLER_NONE | |
| 300 | SOR_DP_TPG_PATTERN_TRAIN1; |
| 301 | value = (value << 8) | lane; |
| 302 | } |
| 303 | |
| 304 | tegra_sor_writel(sor, value, SOR_DP_TPG); |
| 305 | |
| 306 | pattern = DP_TRAINING_PATTERN_1; |
| 307 | |
Thierry Reding | 9542c23 | 2015-07-08 13:39:09 +0200 | [diff] [blame] | 308 | err = drm_dp_aux_train(sor->aux, link, pattern); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 309 | if (err < 0) |
| 310 | return err; |
| 311 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 312 | value = tegra_sor_readl(sor, SOR_DP_SPARE0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 313 | value |= SOR_DP_SPARE_SEQ_ENABLE; |
| 314 | value &= ~SOR_DP_SPARE_PANEL_INTERNAL; |
| 315 | value |= SOR_DP_SPARE_MACRO_SOR_CLK; |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 316 | tegra_sor_writel(sor, value, SOR_DP_SPARE0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 317 | |
| 318 | for (i = 0, value = 0; i < link->num_lanes; i++) { |
| 319 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | |
| 320 | SOR_DP_TPG_SCRAMBLER_NONE | |
| 321 | SOR_DP_TPG_PATTERN_TRAIN2; |
| 322 | value = (value << 8) | lane; |
| 323 | } |
| 324 | |
| 325 | tegra_sor_writel(sor, value, SOR_DP_TPG); |
| 326 | |
| 327 | pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2; |
| 328 | |
Thierry Reding | 9542c23 | 2015-07-08 13:39:09 +0200 | [diff] [blame] | 329 | err = drm_dp_aux_train(sor->aux, link, pattern); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 330 | if (err < 0) |
| 331 | return err; |
| 332 | |
| 333 | for (i = 0, value = 0; i < link->num_lanes; i++) { |
| 334 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | |
| 335 | SOR_DP_TPG_SCRAMBLER_GALIOS | |
| 336 | SOR_DP_TPG_PATTERN_NONE; |
| 337 | value = (value << 8) | lane; |
| 338 | } |
| 339 | |
| 340 | tegra_sor_writel(sor, value, SOR_DP_TPG); |
| 341 | |
| 342 | pattern = DP_TRAINING_PATTERN_DISABLE; |
| 343 | |
Thierry Reding | 9542c23 | 2015-07-08 13:39:09 +0200 | [diff] [blame] | 344 | err = drm_dp_aux_train(sor->aux, link, pattern); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 345 | if (err < 0) |
| 346 | return err; |
| 347 | |
| 348 | return 0; |
| 349 | } |
| 350 | |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 351 | static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor) |
| 352 | { |
| 353 | u32 mask = 0x08, adj = 0, value; |
| 354 | |
| 355 | /* enable pad calibration logic */ |
| 356 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
| 357 | value &= ~SOR_DP_PADCTL_PAD_CAL_PD; |
| 358 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
| 359 | |
| 360 | value = tegra_sor_readl(sor, SOR_PLL1); |
| 361 | value |= SOR_PLL1_TMDS_TERM; |
| 362 | tegra_sor_writel(sor, value, SOR_PLL1); |
| 363 | |
| 364 | while (mask) { |
| 365 | adj |= mask; |
| 366 | |
| 367 | value = tegra_sor_readl(sor, SOR_PLL1); |
| 368 | value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; |
| 369 | value |= SOR_PLL1_TMDS_TERMADJ(adj); |
| 370 | tegra_sor_writel(sor, value, SOR_PLL1); |
| 371 | |
| 372 | usleep_range(100, 200); |
| 373 | |
| 374 | value = tegra_sor_readl(sor, SOR_PLL1); |
| 375 | if (value & SOR_PLL1_TERM_COMPOUT) |
| 376 | adj &= ~mask; |
| 377 | |
| 378 | mask >>= 1; |
| 379 | } |
| 380 | |
| 381 | value = tegra_sor_readl(sor, SOR_PLL1); |
| 382 | value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; |
| 383 | value |= SOR_PLL1_TMDS_TERMADJ(adj); |
| 384 | tegra_sor_writel(sor, value, SOR_PLL1); |
| 385 | |
| 386 | /* disable pad calibration logic */ |
| 387 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
| 388 | value |= SOR_DP_PADCTL_PAD_CAL_PD; |
| 389 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
| 390 | } |
| 391 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 392 | static void tegra_sor_super_update(struct tegra_sor *sor) |
| 393 | { |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 394 | tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); |
| 395 | tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); |
| 396 | tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 397 | } |
| 398 | |
| 399 | static void tegra_sor_update(struct tegra_sor *sor) |
| 400 | { |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 401 | tegra_sor_writel(sor, 0, SOR_STATE0); |
| 402 | tegra_sor_writel(sor, 1, SOR_STATE0); |
| 403 | tegra_sor_writel(sor, 0, SOR_STATE0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 404 | } |
| 405 | |
| 406 | static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) |
| 407 | { |
Thierry Reding | 28fe207 | 2015-01-26 16:02:48 +0100 | [diff] [blame] | 408 | u32 value; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 409 | |
| 410 | value = tegra_sor_readl(sor, SOR_PWM_DIV); |
| 411 | value &= ~SOR_PWM_DIV_MASK; |
| 412 | value |= 0x400; /* period */ |
| 413 | tegra_sor_writel(sor, value, SOR_PWM_DIV); |
| 414 | |
| 415 | value = tegra_sor_readl(sor, SOR_PWM_CTL); |
| 416 | value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; |
| 417 | value |= 0x400; /* duty cycle */ |
| 418 | value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ |
| 419 | value |= SOR_PWM_CTL_TRIGGER; |
| 420 | tegra_sor_writel(sor, value, SOR_PWM_CTL); |
| 421 | |
| 422 | timeout = jiffies + msecs_to_jiffies(timeout); |
| 423 | |
| 424 | while (time_before(jiffies, timeout)) { |
| 425 | value = tegra_sor_readl(sor, SOR_PWM_CTL); |
| 426 | if ((value & SOR_PWM_CTL_TRIGGER) == 0) |
| 427 | return 0; |
| 428 | |
| 429 | usleep_range(25, 100); |
| 430 | } |
| 431 | |
| 432 | return -ETIMEDOUT; |
| 433 | } |
| 434 | |
| 435 | static int tegra_sor_attach(struct tegra_sor *sor) |
| 436 | { |
| 437 | unsigned long value, timeout; |
| 438 | |
| 439 | /* wake up in normal mode */ |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 440 | value = tegra_sor_readl(sor, SOR_SUPER_STATE1); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 441 | value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; |
| 442 | value |= SOR_SUPER_STATE_MODE_NORMAL; |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 443 | tegra_sor_writel(sor, value, SOR_SUPER_STATE1); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 444 | tegra_sor_super_update(sor); |
| 445 | |
| 446 | /* attach */ |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 447 | value = tegra_sor_readl(sor, SOR_SUPER_STATE1); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 448 | value |= SOR_SUPER_STATE_ATTACHED; |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 449 | tegra_sor_writel(sor, value, SOR_SUPER_STATE1); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 450 | tegra_sor_super_update(sor); |
| 451 | |
| 452 | timeout = jiffies + msecs_to_jiffies(250); |
| 453 | |
| 454 | while (time_before(jiffies, timeout)) { |
| 455 | value = tegra_sor_readl(sor, SOR_TEST); |
| 456 | if ((value & SOR_TEST_ATTACHED) != 0) |
| 457 | return 0; |
| 458 | |
| 459 | usleep_range(25, 100); |
| 460 | } |
| 461 | |
| 462 | return -ETIMEDOUT; |
| 463 | } |
| 464 | |
| 465 | static int tegra_sor_wakeup(struct tegra_sor *sor) |
| 466 | { |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 467 | unsigned long value, timeout; |
| 468 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 469 | timeout = jiffies + msecs_to_jiffies(250); |
| 470 | |
| 471 | /* wait for head to wake up */ |
| 472 | while (time_before(jiffies, timeout)) { |
| 473 | value = tegra_sor_readl(sor, SOR_TEST); |
| 474 | value &= SOR_TEST_HEAD_MODE_MASK; |
| 475 | |
| 476 | if (value == SOR_TEST_HEAD_MODE_AWAKE) |
| 477 | return 0; |
| 478 | |
| 479 | usleep_range(25, 100); |
| 480 | } |
| 481 | |
| 482 | return -ETIMEDOUT; |
| 483 | } |
| 484 | |
| 485 | static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) |
| 486 | { |
Thierry Reding | 28fe207 | 2015-01-26 16:02:48 +0100 | [diff] [blame] | 487 | u32 value; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 488 | |
| 489 | value = tegra_sor_readl(sor, SOR_PWR); |
| 490 | value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; |
| 491 | tegra_sor_writel(sor, value, SOR_PWR); |
| 492 | |
| 493 | timeout = jiffies + msecs_to_jiffies(timeout); |
| 494 | |
| 495 | while (time_before(jiffies, timeout)) { |
| 496 | value = tegra_sor_readl(sor, SOR_PWR); |
| 497 | if ((value & SOR_PWR_TRIGGER) == 0) |
| 498 | return 0; |
| 499 | |
| 500 | usleep_range(25, 100); |
| 501 | } |
| 502 | |
| 503 | return -ETIMEDOUT; |
| 504 | } |
| 505 | |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 506 | struct tegra_sor_params { |
| 507 | /* number of link clocks per line */ |
| 508 | unsigned int num_clocks; |
| 509 | /* ratio between input and output */ |
| 510 | u64 ratio; |
| 511 | /* precision factor */ |
| 512 | u64 precision; |
| 513 | |
| 514 | unsigned int active_polarity; |
| 515 | unsigned int active_count; |
| 516 | unsigned int active_frac; |
| 517 | unsigned int tu_size; |
| 518 | unsigned int error; |
| 519 | }; |
| 520 | |
| 521 | static int tegra_sor_compute_params(struct tegra_sor *sor, |
| 522 | struct tegra_sor_params *params, |
| 523 | unsigned int tu_size) |
| 524 | { |
| 525 | u64 active_sym, active_count, frac, approx; |
| 526 | u32 active_polarity, active_frac = 0; |
| 527 | const u64 f = params->precision; |
| 528 | s64 error; |
| 529 | |
| 530 | active_sym = params->ratio * tu_size; |
| 531 | active_count = div_u64(active_sym, f) * f; |
| 532 | frac = active_sym - active_count; |
| 533 | |
| 534 | /* fraction < 0.5 */ |
| 535 | if (frac >= (f / 2)) { |
| 536 | active_polarity = 1; |
| 537 | frac = f - frac; |
| 538 | } else { |
| 539 | active_polarity = 0; |
| 540 | } |
| 541 | |
| 542 | if (frac != 0) { |
| 543 | frac = div_u64(f * f, frac); /* 1/fraction */ |
| 544 | if (frac <= (15 * f)) { |
| 545 | active_frac = div_u64(frac, f); |
| 546 | |
| 547 | /* round up */ |
| 548 | if (active_polarity) |
| 549 | active_frac++; |
| 550 | } else { |
| 551 | active_frac = active_polarity ? 1 : 15; |
| 552 | } |
| 553 | } |
| 554 | |
| 555 | if (active_frac == 1) |
| 556 | active_polarity = 0; |
| 557 | |
| 558 | if (active_polarity == 1) { |
| 559 | if (active_frac) { |
| 560 | approx = active_count + (active_frac * (f - 1)) * f; |
| 561 | approx = div_u64(approx, active_frac * f); |
| 562 | } else { |
| 563 | approx = active_count + f; |
| 564 | } |
| 565 | } else { |
| 566 | if (active_frac) |
| 567 | approx = active_count + div_u64(f, active_frac); |
| 568 | else |
| 569 | approx = active_count; |
| 570 | } |
| 571 | |
| 572 | error = div_s64(active_sym - approx, tu_size); |
| 573 | error *= params->num_clocks; |
| 574 | |
Andrew Morton | 79211c8 | 2015-11-09 14:58:13 -0800 | [diff] [blame] | 575 | if (error <= 0 && abs(error) < params->error) { |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 576 | params->active_count = div_u64(active_count, f); |
| 577 | params->active_polarity = active_polarity; |
| 578 | params->active_frac = active_frac; |
Andrew Morton | 79211c8 | 2015-11-09 14:58:13 -0800 | [diff] [blame] | 579 | params->error = abs(error); |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 580 | params->tu_size = tu_size; |
| 581 | |
| 582 | if (error == 0) |
| 583 | return true; |
| 584 | } |
| 585 | |
| 586 | return false; |
| 587 | } |
| 588 | |
| 589 | static int tegra_sor_calc_config(struct tegra_sor *sor, |
Thierry Reding | 8044449 | 2015-07-29 18:20:01 +0200 | [diff] [blame] | 590 | const struct drm_display_mode *mode, |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 591 | struct tegra_sor_config *config, |
| 592 | struct drm_dp_link *link) |
| 593 | { |
| 594 | const u64 f = 100000, link_rate = link->rate * 1000; |
| 595 | const u64 pclk = mode->clock * 1000; |
Thierry Reding | 7890b57 | 2014-06-05 16:12:46 +0200 | [diff] [blame] | 596 | u64 input, output, watermark, num; |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 597 | struct tegra_sor_params params; |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 598 | u32 num_syms_per_line; |
| 599 | unsigned int i; |
| 600 | |
| 601 | if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel) |
| 602 | return -EINVAL; |
| 603 | |
| 604 | output = link_rate * 8 * link->num_lanes; |
| 605 | input = pclk * config->bits_per_pixel; |
| 606 | |
| 607 | if (input >= output) |
| 608 | return -ERANGE; |
| 609 | |
| 610 | memset(¶ms, 0, sizeof(params)); |
| 611 | params.ratio = div64_u64(input * f, output); |
| 612 | params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk); |
| 613 | params.precision = f; |
| 614 | params.error = 64 * f; |
| 615 | params.tu_size = 64; |
| 616 | |
| 617 | for (i = params.tu_size; i >= 32; i--) |
| 618 | if (tegra_sor_compute_params(sor, ¶ms, i)) |
| 619 | break; |
| 620 | |
| 621 | if (params.active_frac == 0) { |
| 622 | config->active_polarity = 0; |
| 623 | config->active_count = params.active_count; |
| 624 | |
| 625 | if (!params.active_polarity) |
| 626 | config->active_count--; |
| 627 | |
| 628 | config->tu_size = params.tu_size; |
| 629 | config->active_frac = 1; |
| 630 | } else { |
| 631 | config->active_polarity = params.active_polarity; |
| 632 | config->active_count = params.active_count; |
| 633 | config->active_frac = params.active_frac; |
| 634 | config->tu_size = params.tu_size; |
| 635 | } |
| 636 | |
| 637 | dev_dbg(sor->dev, |
| 638 | "polarity: %d active count: %d tu size: %d active frac: %d\n", |
| 639 | config->active_polarity, config->active_count, |
| 640 | config->tu_size, config->active_frac); |
| 641 | |
| 642 | watermark = params.ratio * config->tu_size * (f - params.ratio); |
| 643 | watermark = div_u64(watermark, f); |
| 644 | |
| 645 | watermark = div_u64(watermark + params.error, f); |
| 646 | config->watermark = watermark + (config->bits_per_pixel / 8) + 2; |
| 647 | num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) * |
| 648 | (link->num_lanes * 8); |
| 649 | |
| 650 | if (config->watermark > 30) { |
| 651 | config->watermark = 30; |
| 652 | dev_err(sor->dev, |
| 653 | "unable to compute TU size, forcing watermark to %u\n", |
| 654 | config->watermark); |
| 655 | } else if (config->watermark > num_syms_per_line) { |
| 656 | config->watermark = num_syms_per_line; |
| 657 | dev_err(sor->dev, "watermark too high, forcing to %u\n", |
| 658 | config->watermark); |
| 659 | } |
| 660 | |
Thierry Reding | 7890b57 | 2014-06-05 16:12:46 +0200 | [diff] [blame] | 661 | /* compute the number of symbols per horizontal blanking interval */ |
| 662 | num = ((mode->htotal - mode->hdisplay) - 7) * link_rate; |
| 663 | config->hblank_symbols = div_u64(num, pclk); |
| 664 | |
| 665 | if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) |
| 666 | config->hblank_symbols -= 3; |
| 667 | |
| 668 | config->hblank_symbols -= 12 / link->num_lanes; |
| 669 | |
| 670 | /* compute the number of symbols per vertical blanking interval */ |
| 671 | num = (mode->hdisplay - 25) * link_rate; |
| 672 | config->vblank_symbols = div_u64(num, pclk); |
| 673 | config->vblank_symbols -= 36 / link->num_lanes + 4; |
| 674 | |
| 675 | dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, |
| 676 | config->vblank_symbols); |
| 677 | |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 678 | return 0; |
| 679 | } |
| 680 | |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 681 | static int tegra_sor_detach(struct tegra_sor *sor) |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 682 | { |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 683 | unsigned long value, timeout; |
| 684 | |
| 685 | /* switch to safe mode */ |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 686 | value = tegra_sor_readl(sor, SOR_SUPER_STATE1); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 687 | value &= ~SOR_SUPER_STATE_MODE_NORMAL; |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 688 | tegra_sor_writel(sor, value, SOR_SUPER_STATE1); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 689 | tegra_sor_super_update(sor); |
| 690 | |
| 691 | timeout = jiffies + msecs_to_jiffies(250); |
| 692 | |
| 693 | while (time_before(jiffies, timeout)) { |
| 694 | value = tegra_sor_readl(sor, SOR_PWR); |
| 695 | if (value & SOR_PWR_MODE_SAFE) |
| 696 | break; |
| 697 | } |
| 698 | |
| 699 | if ((value & SOR_PWR_MODE_SAFE) == 0) |
| 700 | return -ETIMEDOUT; |
| 701 | |
| 702 | /* go to sleep */ |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 703 | value = tegra_sor_readl(sor, SOR_SUPER_STATE1); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 704 | value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 705 | tegra_sor_writel(sor, value, SOR_SUPER_STATE1); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 706 | tegra_sor_super_update(sor); |
| 707 | |
| 708 | /* detach */ |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 709 | value = tegra_sor_readl(sor, SOR_SUPER_STATE1); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 710 | value &= ~SOR_SUPER_STATE_ATTACHED; |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 711 | tegra_sor_writel(sor, value, SOR_SUPER_STATE1); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 712 | tegra_sor_super_update(sor); |
| 713 | |
| 714 | timeout = jiffies + msecs_to_jiffies(250); |
| 715 | |
| 716 | while (time_before(jiffies, timeout)) { |
| 717 | value = tegra_sor_readl(sor, SOR_TEST); |
| 718 | if ((value & SOR_TEST_ATTACHED) == 0) |
| 719 | break; |
| 720 | |
| 721 | usleep_range(25, 100); |
| 722 | } |
| 723 | |
| 724 | if ((value & SOR_TEST_ATTACHED) != 0) |
| 725 | return -ETIMEDOUT; |
| 726 | |
| 727 | return 0; |
| 728 | } |
| 729 | |
| 730 | static int tegra_sor_power_down(struct tegra_sor *sor) |
| 731 | { |
| 732 | unsigned long value, timeout; |
| 733 | int err; |
| 734 | |
| 735 | value = tegra_sor_readl(sor, SOR_PWR); |
| 736 | value &= ~SOR_PWR_NORMAL_STATE_PU; |
| 737 | value |= SOR_PWR_TRIGGER; |
| 738 | tegra_sor_writel(sor, value, SOR_PWR); |
| 739 | |
| 740 | timeout = jiffies + msecs_to_jiffies(250); |
| 741 | |
| 742 | while (time_before(jiffies, timeout)) { |
| 743 | value = tegra_sor_readl(sor, SOR_PWR); |
| 744 | if ((value & SOR_PWR_TRIGGER) == 0) |
| 745 | return 0; |
| 746 | |
| 747 | usleep_range(25, 100); |
| 748 | } |
| 749 | |
| 750 | if ((value & SOR_PWR_TRIGGER) != 0) |
| 751 | return -ETIMEDOUT; |
| 752 | |
Thierry Reding | 25bb2ce | 2015-08-03 14:23:29 +0200 | [diff] [blame^] | 753 | /* switch to safe parent clock */ |
| 754 | err = tegra_sor_set_parent_clock(sor, sor->clk_safe); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 755 | if (err < 0) |
| 756 | dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); |
| 757 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 758 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 759 | value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | |
| 760 | SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 761 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 762 | |
| 763 | /* stop lane sequencer */ |
| 764 | value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | |
| 765 | SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; |
| 766 | tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); |
| 767 | |
| 768 | timeout = jiffies + msecs_to_jiffies(250); |
| 769 | |
| 770 | while (time_before(jiffies, timeout)) { |
| 771 | value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); |
| 772 | if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) |
| 773 | break; |
| 774 | |
| 775 | usleep_range(25, 100); |
| 776 | } |
| 777 | |
| 778 | if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) |
| 779 | return -ETIMEDOUT; |
| 780 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 781 | value = tegra_sor_readl(sor, SOR_PLL2); |
| 782 | value |= SOR_PLL2_PORT_POWERDOWN; |
| 783 | tegra_sor_writel(sor, value, SOR_PLL2); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 784 | |
| 785 | usleep_range(20, 100); |
| 786 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 787 | value = tegra_sor_readl(sor, SOR_PLL0); |
| 788 | value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; |
| 789 | tegra_sor_writel(sor, value, SOR_PLL0); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 790 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 791 | value = tegra_sor_readl(sor, SOR_PLL2); |
| 792 | value |= SOR_PLL2_SEQ_PLLCAPPD; |
| 793 | value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; |
| 794 | tegra_sor_writel(sor, value, SOR_PLL2); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 795 | |
| 796 | usleep_range(20, 100); |
| 797 | |
| 798 | return 0; |
| 799 | } |
| 800 | |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 801 | static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) |
| 802 | { |
| 803 | u32 value; |
| 804 | |
| 805 | timeout = jiffies + msecs_to_jiffies(timeout); |
| 806 | |
| 807 | while (time_before(jiffies, timeout)) { |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 808 | value = tegra_sor_readl(sor, SOR_CRCA); |
| 809 | if (value & SOR_CRCA_VALID) |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 810 | return 0; |
| 811 | |
| 812 | usleep_range(100, 200); |
| 813 | } |
| 814 | |
| 815 | return -ETIMEDOUT; |
| 816 | } |
| 817 | |
Thierry Reding | 530239a | 2015-08-06 11:04:54 +0200 | [diff] [blame] | 818 | static int tegra_sor_show_crc(struct seq_file *s, void *data) |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 819 | { |
Thierry Reding | 530239a | 2015-08-06 11:04:54 +0200 | [diff] [blame] | 820 | struct drm_info_node *node = s->private; |
| 821 | struct tegra_sor *sor = node->info_ent->data; |
Thierry Reding | 850bab4 | 2015-07-29 17:58:41 +0200 | [diff] [blame] | 822 | struct drm_crtc *crtc = sor->output.encoder.crtc; |
| 823 | struct drm_device *drm = node->minor->dev; |
Thierry Reding | 530239a | 2015-08-06 11:04:54 +0200 | [diff] [blame] | 824 | int err = 0; |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 825 | u32 value; |
| 826 | |
Thierry Reding | 850bab4 | 2015-07-29 17:58:41 +0200 | [diff] [blame] | 827 | drm_modeset_lock_all(drm); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 828 | |
Thierry Reding | 850bab4 | 2015-07-29 17:58:41 +0200 | [diff] [blame] | 829 | if (!crtc || !crtc->state->active) { |
| 830 | err = -EBUSY; |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 831 | goto unlock; |
| 832 | } |
| 833 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 834 | value = tegra_sor_readl(sor, SOR_STATE1); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 835 | value &= ~SOR_STATE_ASY_CRC_MODE_MASK; |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 836 | tegra_sor_writel(sor, value, SOR_STATE1); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 837 | |
| 838 | value = tegra_sor_readl(sor, SOR_CRC_CNTRL); |
| 839 | value |= SOR_CRC_CNTRL_ENABLE; |
| 840 | tegra_sor_writel(sor, value, SOR_CRC_CNTRL); |
| 841 | |
| 842 | value = tegra_sor_readl(sor, SOR_TEST); |
| 843 | value &= ~SOR_TEST_CRC_POST_SERIALIZE; |
| 844 | tegra_sor_writel(sor, value, SOR_TEST); |
| 845 | |
| 846 | err = tegra_sor_crc_wait(sor, 100); |
| 847 | if (err < 0) |
| 848 | goto unlock; |
| 849 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 850 | tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); |
| 851 | value = tegra_sor_readl(sor, SOR_CRCB); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 852 | |
Thierry Reding | 530239a | 2015-08-06 11:04:54 +0200 | [diff] [blame] | 853 | seq_printf(s, "%08x\n", value); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 854 | |
| 855 | unlock: |
Thierry Reding | 850bab4 | 2015-07-29 17:58:41 +0200 | [diff] [blame] | 856 | drm_modeset_unlock_all(drm); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 857 | return err; |
| 858 | } |
| 859 | |
Thierry Reding | dab1633 | 2015-01-26 16:04:08 +0100 | [diff] [blame] | 860 | static int tegra_sor_show_regs(struct seq_file *s, void *data) |
| 861 | { |
| 862 | struct drm_info_node *node = s->private; |
| 863 | struct tegra_sor *sor = node->info_ent->data; |
Thierry Reding | 850bab4 | 2015-07-29 17:58:41 +0200 | [diff] [blame] | 864 | struct drm_crtc *crtc = sor->output.encoder.crtc; |
| 865 | struct drm_device *drm = node->minor->dev; |
| 866 | int err = 0; |
| 867 | |
| 868 | drm_modeset_lock_all(drm); |
| 869 | |
| 870 | if (!crtc || !crtc->state->active) { |
| 871 | err = -EBUSY; |
| 872 | goto unlock; |
| 873 | } |
Thierry Reding | dab1633 | 2015-01-26 16:04:08 +0100 | [diff] [blame] | 874 | |
| 875 | #define DUMP_REG(name) \ |
| 876 | seq_printf(s, "%-38s %#05x %08x\n", #name, name, \ |
| 877 | tegra_sor_readl(sor, name)) |
| 878 | |
| 879 | DUMP_REG(SOR_CTXSW); |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 880 | DUMP_REG(SOR_SUPER_STATE0); |
| 881 | DUMP_REG(SOR_SUPER_STATE1); |
| 882 | DUMP_REG(SOR_STATE0); |
| 883 | DUMP_REG(SOR_STATE1); |
| 884 | DUMP_REG(SOR_HEAD_STATE0(0)); |
| 885 | DUMP_REG(SOR_HEAD_STATE0(1)); |
| 886 | DUMP_REG(SOR_HEAD_STATE1(0)); |
| 887 | DUMP_REG(SOR_HEAD_STATE1(1)); |
| 888 | DUMP_REG(SOR_HEAD_STATE2(0)); |
| 889 | DUMP_REG(SOR_HEAD_STATE2(1)); |
| 890 | DUMP_REG(SOR_HEAD_STATE3(0)); |
| 891 | DUMP_REG(SOR_HEAD_STATE3(1)); |
| 892 | DUMP_REG(SOR_HEAD_STATE4(0)); |
| 893 | DUMP_REG(SOR_HEAD_STATE4(1)); |
| 894 | DUMP_REG(SOR_HEAD_STATE5(0)); |
| 895 | DUMP_REG(SOR_HEAD_STATE5(1)); |
Thierry Reding | dab1633 | 2015-01-26 16:04:08 +0100 | [diff] [blame] | 896 | DUMP_REG(SOR_CRC_CNTRL); |
| 897 | DUMP_REG(SOR_DP_DEBUG_MVID); |
| 898 | DUMP_REG(SOR_CLK_CNTRL); |
| 899 | DUMP_REG(SOR_CAP); |
| 900 | DUMP_REG(SOR_PWR); |
| 901 | DUMP_REG(SOR_TEST); |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 902 | DUMP_REG(SOR_PLL0); |
| 903 | DUMP_REG(SOR_PLL1); |
| 904 | DUMP_REG(SOR_PLL2); |
| 905 | DUMP_REG(SOR_PLL3); |
Thierry Reding | dab1633 | 2015-01-26 16:04:08 +0100 | [diff] [blame] | 906 | DUMP_REG(SOR_CSTM); |
| 907 | DUMP_REG(SOR_LVDS); |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 908 | DUMP_REG(SOR_CRCA); |
| 909 | DUMP_REG(SOR_CRCB); |
Thierry Reding | dab1633 | 2015-01-26 16:04:08 +0100 | [diff] [blame] | 910 | DUMP_REG(SOR_BLANK); |
| 911 | DUMP_REG(SOR_SEQ_CTL); |
| 912 | DUMP_REG(SOR_LANE_SEQ_CTL); |
| 913 | DUMP_REG(SOR_SEQ_INST(0)); |
| 914 | DUMP_REG(SOR_SEQ_INST(1)); |
| 915 | DUMP_REG(SOR_SEQ_INST(2)); |
| 916 | DUMP_REG(SOR_SEQ_INST(3)); |
| 917 | DUMP_REG(SOR_SEQ_INST(4)); |
| 918 | DUMP_REG(SOR_SEQ_INST(5)); |
| 919 | DUMP_REG(SOR_SEQ_INST(6)); |
| 920 | DUMP_REG(SOR_SEQ_INST(7)); |
| 921 | DUMP_REG(SOR_SEQ_INST(8)); |
| 922 | DUMP_REG(SOR_SEQ_INST(9)); |
| 923 | DUMP_REG(SOR_SEQ_INST(10)); |
| 924 | DUMP_REG(SOR_SEQ_INST(11)); |
| 925 | DUMP_REG(SOR_SEQ_INST(12)); |
| 926 | DUMP_REG(SOR_SEQ_INST(13)); |
| 927 | DUMP_REG(SOR_SEQ_INST(14)); |
| 928 | DUMP_REG(SOR_SEQ_INST(15)); |
| 929 | DUMP_REG(SOR_PWM_DIV); |
| 930 | DUMP_REG(SOR_PWM_CTL); |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 931 | DUMP_REG(SOR_VCRC_A0); |
| 932 | DUMP_REG(SOR_VCRC_A1); |
| 933 | DUMP_REG(SOR_VCRC_B0); |
| 934 | DUMP_REG(SOR_VCRC_B1); |
| 935 | DUMP_REG(SOR_CCRC_A0); |
| 936 | DUMP_REG(SOR_CCRC_A1); |
| 937 | DUMP_REG(SOR_CCRC_B0); |
| 938 | DUMP_REG(SOR_CCRC_B1); |
| 939 | DUMP_REG(SOR_EDATA_A0); |
| 940 | DUMP_REG(SOR_EDATA_A1); |
| 941 | DUMP_REG(SOR_EDATA_B0); |
| 942 | DUMP_REG(SOR_EDATA_B1); |
| 943 | DUMP_REG(SOR_COUNT_A0); |
| 944 | DUMP_REG(SOR_COUNT_A1); |
| 945 | DUMP_REG(SOR_COUNT_B0); |
| 946 | DUMP_REG(SOR_COUNT_B1); |
| 947 | DUMP_REG(SOR_DEBUG_A0); |
| 948 | DUMP_REG(SOR_DEBUG_A1); |
| 949 | DUMP_REG(SOR_DEBUG_B0); |
| 950 | DUMP_REG(SOR_DEBUG_B1); |
Thierry Reding | dab1633 | 2015-01-26 16:04:08 +0100 | [diff] [blame] | 951 | DUMP_REG(SOR_TRIG); |
| 952 | DUMP_REG(SOR_MSCHECK); |
| 953 | DUMP_REG(SOR_XBAR_CTRL); |
| 954 | DUMP_REG(SOR_XBAR_POL); |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 955 | DUMP_REG(SOR_DP_LINKCTL0); |
| 956 | DUMP_REG(SOR_DP_LINKCTL1); |
| 957 | DUMP_REG(SOR_LANE_DRIVE_CURRENT0); |
| 958 | DUMP_REG(SOR_LANE_DRIVE_CURRENT1); |
| 959 | DUMP_REG(SOR_LANE4_DRIVE_CURRENT0); |
| 960 | DUMP_REG(SOR_LANE4_DRIVE_CURRENT1); |
| 961 | DUMP_REG(SOR_LANE_PREEMPHASIS0); |
| 962 | DUMP_REG(SOR_LANE_PREEMPHASIS1); |
| 963 | DUMP_REG(SOR_LANE4_PREEMPHASIS0); |
| 964 | DUMP_REG(SOR_LANE4_PREEMPHASIS1); |
| 965 | DUMP_REG(SOR_LANE_POSTCURSOR0); |
| 966 | DUMP_REG(SOR_LANE_POSTCURSOR1); |
| 967 | DUMP_REG(SOR_DP_CONFIG0); |
| 968 | DUMP_REG(SOR_DP_CONFIG1); |
| 969 | DUMP_REG(SOR_DP_MN0); |
| 970 | DUMP_REG(SOR_DP_MN1); |
| 971 | DUMP_REG(SOR_DP_PADCTL0); |
| 972 | DUMP_REG(SOR_DP_PADCTL1); |
| 973 | DUMP_REG(SOR_DP_DEBUG0); |
| 974 | DUMP_REG(SOR_DP_DEBUG1); |
| 975 | DUMP_REG(SOR_DP_SPARE0); |
| 976 | DUMP_REG(SOR_DP_SPARE1); |
Thierry Reding | dab1633 | 2015-01-26 16:04:08 +0100 | [diff] [blame] | 977 | DUMP_REG(SOR_DP_AUDIO_CTRL); |
| 978 | DUMP_REG(SOR_DP_AUDIO_HBLANK_SYMBOLS); |
| 979 | DUMP_REG(SOR_DP_AUDIO_VBLANK_SYMBOLS); |
| 980 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_HEADER); |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 981 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK0); |
| 982 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK1); |
| 983 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK2); |
| 984 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK3); |
| 985 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK4); |
| 986 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK5); |
| 987 | DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK6); |
Thierry Reding | dab1633 | 2015-01-26 16:04:08 +0100 | [diff] [blame] | 988 | DUMP_REG(SOR_DP_TPG); |
| 989 | DUMP_REG(SOR_DP_TPG_CONFIG); |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 990 | DUMP_REG(SOR_DP_LQ_CSTM0); |
| 991 | DUMP_REG(SOR_DP_LQ_CSTM1); |
| 992 | DUMP_REG(SOR_DP_LQ_CSTM2); |
Thierry Reding | dab1633 | 2015-01-26 16:04:08 +0100 | [diff] [blame] | 993 | |
| 994 | #undef DUMP_REG |
| 995 | |
Thierry Reding | 850bab4 | 2015-07-29 17:58:41 +0200 | [diff] [blame] | 996 | unlock: |
| 997 | drm_modeset_unlock_all(drm); |
| 998 | return err; |
Thierry Reding | dab1633 | 2015-01-26 16:04:08 +0100 | [diff] [blame] | 999 | } |
| 1000 | |
| 1001 | static const struct drm_info_list debugfs_files[] = { |
Thierry Reding | 530239a | 2015-08-06 11:04:54 +0200 | [diff] [blame] | 1002 | { "crc", tegra_sor_show_crc, 0, NULL }, |
Thierry Reding | dab1633 | 2015-01-26 16:04:08 +0100 | [diff] [blame] | 1003 | { "regs", tegra_sor_show_regs, 0, NULL }, |
| 1004 | }; |
| 1005 | |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1006 | static int tegra_sor_debugfs_init(struct tegra_sor *sor, |
| 1007 | struct drm_minor *minor) |
| 1008 | { |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 1009 | const char *name = sor->soc->supports_dp ? "sor1" : "sor"; |
Thierry Reding | dab1633 | 2015-01-26 16:04:08 +0100 | [diff] [blame] | 1010 | unsigned int i; |
Thierry Reding | 530239a | 2015-08-06 11:04:54 +0200 | [diff] [blame] | 1011 | int err; |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1012 | |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 1013 | sor->debugfs = debugfs_create_dir(name, minor->debugfs_root); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1014 | if (!sor->debugfs) |
| 1015 | return -ENOMEM; |
| 1016 | |
Thierry Reding | dab1633 | 2015-01-26 16:04:08 +0100 | [diff] [blame] | 1017 | sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), |
| 1018 | GFP_KERNEL); |
| 1019 | if (!sor->debugfs_files) { |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1020 | err = -ENOMEM; |
| 1021 | goto remove; |
| 1022 | } |
| 1023 | |
Thierry Reding | dab1633 | 2015-01-26 16:04:08 +0100 | [diff] [blame] | 1024 | for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) |
| 1025 | sor->debugfs_files[i].data = sor; |
| 1026 | |
| 1027 | err = drm_debugfs_create_files(sor->debugfs_files, |
| 1028 | ARRAY_SIZE(debugfs_files), |
| 1029 | sor->debugfs, minor); |
| 1030 | if (err < 0) |
| 1031 | goto free; |
| 1032 | |
Thierry Reding | 3ff1f22 | 2015-07-03 14:14:29 +0200 | [diff] [blame] | 1033 | sor->minor = minor; |
| 1034 | |
Thierry Reding | 530239a | 2015-08-06 11:04:54 +0200 | [diff] [blame] | 1035 | return 0; |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1036 | |
Thierry Reding | dab1633 | 2015-01-26 16:04:08 +0100 | [diff] [blame] | 1037 | free: |
| 1038 | kfree(sor->debugfs_files); |
| 1039 | sor->debugfs_files = NULL; |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1040 | remove: |
Thierry Reding | dab1633 | 2015-01-26 16:04:08 +0100 | [diff] [blame] | 1041 | debugfs_remove_recursive(sor->debugfs); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1042 | sor->debugfs = NULL; |
| 1043 | return err; |
| 1044 | } |
| 1045 | |
Thierry Reding | 4009c22 | 2014-12-19 15:47:30 +0100 | [diff] [blame] | 1046 | static void tegra_sor_debugfs_exit(struct tegra_sor *sor) |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1047 | { |
Thierry Reding | dab1633 | 2015-01-26 16:04:08 +0100 | [diff] [blame] | 1048 | drm_debugfs_remove_files(sor->debugfs_files, ARRAY_SIZE(debugfs_files), |
| 1049 | sor->minor); |
| 1050 | sor->minor = NULL; |
| 1051 | |
| 1052 | kfree(sor->debugfs_files); |
Thierry Reding | 066d30f | 2015-07-03 14:16:30 +0200 | [diff] [blame] | 1053 | sor->debugfs_files = NULL; |
Thierry Reding | dab1633 | 2015-01-26 16:04:08 +0100 | [diff] [blame] | 1054 | |
| 1055 | debugfs_remove_recursive(sor->debugfs); |
Thierry Reding | 066d30f | 2015-07-03 14:16:30 +0200 | [diff] [blame] | 1056 | sor->debugfs = NULL; |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1057 | } |
| 1058 | |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1059 | static enum drm_connector_status |
| 1060 | tegra_sor_connector_detect(struct drm_connector *connector, bool force) |
| 1061 | { |
| 1062 | struct tegra_output *output = connector_to_output(connector); |
| 1063 | struct tegra_sor *sor = to_sor(output); |
| 1064 | |
Thierry Reding | 9542c23 | 2015-07-08 13:39:09 +0200 | [diff] [blame] | 1065 | if (sor->aux) |
| 1066 | return drm_dp_aux_detect(sor->aux); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1067 | |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 1068 | return tegra_output_connector_detect(connector, force); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1069 | } |
| 1070 | |
| 1071 | static const struct drm_connector_funcs tegra_sor_connector_funcs = { |
Thierry Reding | 850bab4 | 2015-07-29 17:58:41 +0200 | [diff] [blame] | 1072 | .dpms = drm_atomic_helper_connector_dpms, |
Thierry Reding | 9d44189 | 2014-11-24 17:02:53 +0100 | [diff] [blame] | 1073 | .reset = drm_atomic_helper_connector_reset, |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1074 | .detect = tegra_sor_connector_detect, |
| 1075 | .fill_modes = drm_helper_probe_single_connector_modes, |
| 1076 | .destroy = tegra_output_connector_destroy, |
Thierry Reding | 9d44189 | 2014-11-24 17:02:53 +0100 | [diff] [blame] | 1077 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 1078 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1079 | }; |
| 1080 | |
| 1081 | static int tegra_sor_connector_get_modes(struct drm_connector *connector) |
| 1082 | { |
| 1083 | struct tegra_output *output = connector_to_output(connector); |
| 1084 | struct tegra_sor *sor = to_sor(output); |
| 1085 | int err; |
| 1086 | |
Thierry Reding | 9542c23 | 2015-07-08 13:39:09 +0200 | [diff] [blame] | 1087 | if (sor->aux) |
| 1088 | drm_dp_aux_enable(sor->aux); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1089 | |
| 1090 | err = tegra_output_connector_get_modes(connector); |
| 1091 | |
Thierry Reding | 9542c23 | 2015-07-08 13:39:09 +0200 | [diff] [blame] | 1092 | if (sor->aux) |
| 1093 | drm_dp_aux_disable(sor->aux); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1094 | |
| 1095 | return err; |
| 1096 | } |
| 1097 | |
| 1098 | static enum drm_mode_status |
| 1099 | tegra_sor_connector_mode_valid(struct drm_connector *connector, |
| 1100 | struct drm_display_mode *mode) |
| 1101 | { |
| 1102 | return MODE_OK; |
| 1103 | } |
| 1104 | |
| 1105 | static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = { |
| 1106 | .get_modes = tegra_sor_connector_get_modes, |
| 1107 | .mode_valid = tegra_sor_connector_mode_valid, |
| 1108 | .best_encoder = tegra_output_connector_best_encoder, |
| 1109 | }; |
| 1110 | |
| 1111 | static const struct drm_encoder_funcs tegra_sor_encoder_funcs = { |
| 1112 | .destroy = tegra_output_encoder_destroy, |
| 1113 | }; |
| 1114 | |
Thierry Reding | 850bab4 | 2015-07-29 17:58:41 +0200 | [diff] [blame] | 1115 | static void tegra_sor_edp_disable(struct drm_encoder *encoder) |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1116 | { |
Thierry Reding | 850bab4 | 2015-07-29 17:58:41 +0200 | [diff] [blame] | 1117 | struct tegra_output *output = encoder_to_output(encoder); |
| 1118 | struct tegra_dc *dc = to_tegra_dc(encoder->crtc); |
| 1119 | struct tegra_sor *sor = to_sor(output); |
| 1120 | u32 value; |
| 1121 | int err; |
| 1122 | |
| 1123 | if (output->panel) |
| 1124 | drm_panel_disable(output->panel); |
| 1125 | |
| 1126 | err = tegra_sor_detach(sor); |
| 1127 | if (err < 0) |
| 1128 | dev_err(sor->dev, "failed to detach SOR: %d\n", err); |
| 1129 | |
| 1130 | tegra_sor_writel(sor, 0, SOR_STATE1); |
| 1131 | tegra_sor_update(sor); |
| 1132 | |
| 1133 | /* |
| 1134 | * The following accesses registers of the display controller, so make |
| 1135 | * sure it's only executed when the output is attached to one. |
| 1136 | */ |
| 1137 | if (dc) { |
| 1138 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); |
| 1139 | value &= ~SOR_ENABLE; |
| 1140 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); |
| 1141 | |
| 1142 | tegra_dc_commit(dc); |
| 1143 | } |
| 1144 | |
| 1145 | err = tegra_sor_power_down(sor); |
| 1146 | if (err < 0) |
| 1147 | dev_err(sor->dev, "failed to power down SOR: %d\n", err); |
| 1148 | |
Thierry Reding | 9542c23 | 2015-07-08 13:39:09 +0200 | [diff] [blame] | 1149 | if (sor->aux) { |
| 1150 | err = drm_dp_aux_disable(sor->aux); |
Thierry Reding | 850bab4 | 2015-07-29 17:58:41 +0200 | [diff] [blame] | 1151 | if (err < 0) |
| 1152 | dev_err(sor->dev, "failed to disable DP: %d\n", err); |
| 1153 | } |
| 1154 | |
| 1155 | err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS); |
| 1156 | if (err < 0) |
| 1157 | dev_err(sor->dev, "failed to power off I/O rail: %d\n", err); |
| 1158 | |
| 1159 | if (output->panel) |
| 1160 | drm_panel_unprepare(output->panel); |
| 1161 | |
| 1162 | reset_control_assert(sor->rst); |
| 1163 | clk_disable_unprepare(sor->clk); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1164 | } |
| 1165 | |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 1166 | #if 0 |
| 1167 | static int calc_h_ref_to_sync(const struct drm_display_mode *mode, |
| 1168 | unsigned int *value) |
| 1169 | { |
| 1170 | unsigned int hfp, hsw, hbp, a = 0, b; |
| 1171 | |
| 1172 | hfp = mode->hsync_start - mode->hdisplay; |
| 1173 | hsw = mode->hsync_end - mode->hsync_start; |
| 1174 | hbp = mode->htotal - mode->hsync_end; |
| 1175 | |
| 1176 | pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp); |
| 1177 | |
| 1178 | b = hfp - 1; |
| 1179 | |
| 1180 | pr_info("a: %u, b: %u\n", a, b); |
| 1181 | pr_info("a + hsw + hbp = %u\n", a + hsw + hbp); |
| 1182 | |
| 1183 | if (a + hsw + hbp <= 11) { |
| 1184 | a = 1 + 11 - hsw - hbp; |
| 1185 | pr_info("a: %u\n", a); |
| 1186 | } |
| 1187 | |
| 1188 | if (a > b) |
| 1189 | return -EINVAL; |
| 1190 | |
| 1191 | if (hsw < 1) |
| 1192 | return -EINVAL; |
| 1193 | |
| 1194 | if (mode->hdisplay < 16) |
| 1195 | return -EINVAL; |
| 1196 | |
| 1197 | if (value) { |
| 1198 | if (b > a && a % 2) |
| 1199 | *value = a + 1; |
| 1200 | else |
| 1201 | *value = a; |
| 1202 | } |
| 1203 | |
| 1204 | return 0; |
| 1205 | } |
| 1206 | #endif |
| 1207 | |
Thierry Reding | 850bab4 | 2015-07-29 17:58:41 +0200 | [diff] [blame] | 1208 | static void tegra_sor_edp_enable(struct drm_encoder *encoder) |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1209 | { |
Thierry Reding | 850bab4 | 2015-07-29 17:58:41 +0200 | [diff] [blame] | 1210 | struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1211 | struct tegra_output *output = encoder_to_output(encoder); |
| 1212 | struct tegra_dc *dc = to_tegra_dc(encoder->crtc); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1213 | unsigned int vbe, vse, hbe, hse, vbs, hbs, i; |
| 1214 | struct tegra_sor *sor = to_sor(output); |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 1215 | struct tegra_sor_config config; |
| 1216 | struct drm_dp_link link; |
Thierry Reding | 01b9bea | 2015-11-11 17:15:29 +0100 | [diff] [blame] | 1217 | u8 rate, lanes; |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 1218 | int err = 0; |
Thierry Reding | 28fe207 | 2015-01-26 16:02:48 +0100 | [diff] [blame] | 1219 | u32 value; |
Thierry Reding | 86f5c52 | 2014-03-26 11:13:16 +0100 | [diff] [blame] | 1220 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1221 | err = clk_prepare_enable(sor->clk); |
| 1222 | if (err < 0) |
Thierry Reding | 850bab4 | 2015-07-29 17:58:41 +0200 | [diff] [blame] | 1223 | dev_err(sor->dev, "failed to enable clock: %d\n", err); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1224 | |
| 1225 | reset_control_deassert(sor->rst); |
| 1226 | |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1227 | if (output->panel) |
| 1228 | drm_panel_prepare(output->panel); |
| 1229 | |
Thierry Reding | 01b9bea | 2015-11-11 17:15:29 +0100 | [diff] [blame] | 1230 | err = drm_dp_aux_enable(sor->aux); |
| 1231 | if (err < 0) |
| 1232 | dev_err(sor->dev, "failed to enable DP: %d\n", err); |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 1233 | |
Thierry Reding | 01b9bea | 2015-11-11 17:15:29 +0100 | [diff] [blame] | 1234 | err = drm_dp_link_probe(sor->aux, &link); |
| 1235 | if (err < 0) { |
| 1236 | dev_err(sor->dev, "failed to probe eDP link: %d\n", err); |
| 1237 | return; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1238 | } |
| 1239 | |
Thierry Reding | 25bb2ce | 2015-08-03 14:23:29 +0200 | [diff] [blame^] | 1240 | /* switch to safe parent clock */ |
| 1241 | err = tegra_sor_set_parent_clock(sor, sor->clk_safe); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1242 | if (err < 0) |
| 1243 | dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); |
| 1244 | |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 1245 | memset(&config, 0, sizeof(config)); |
Stéphane Marchesin | 054b1bd | 2014-06-19 18:18:29 -0700 | [diff] [blame] | 1246 | config.bits_per_pixel = output->connector.display_info.bpc * 3; |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 1247 | |
| 1248 | err = tegra_sor_calc_config(sor, mode, &config, &link); |
| 1249 | if (err < 0) |
| 1250 | dev_err(sor->dev, "failed to compute link configuration: %d\n", |
| 1251 | err); |
| 1252 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1253 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); |
| 1254 | value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; |
| 1255 | value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; |
| 1256 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); |
| 1257 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1258 | value = tegra_sor_readl(sor, SOR_PLL2); |
| 1259 | value &= ~SOR_PLL2_BANDGAP_POWERDOWN; |
| 1260 | tegra_sor_writel(sor, value, SOR_PLL2); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1261 | usleep_range(20, 100); |
| 1262 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1263 | value = tegra_sor_readl(sor, SOR_PLL3); |
| 1264 | value |= SOR_PLL3_PLL_VDD_MODE_3V3; |
| 1265 | tegra_sor_writel(sor, value, SOR_PLL3); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1266 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1267 | value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST | |
| 1268 | SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT; |
| 1269 | tegra_sor_writel(sor, value, SOR_PLL0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1270 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1271 | value = tegra_sor_readl(sor, SOR_PLL2); |
| 1272 | value |= SOR_PLL2_SEQ_PLLCAPPD; |
| 1273 | value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; |
| 1274 | value |= SOR_PLL2_LVDS_ENABLE; |
| 1275 | tegra_sor_writel(sor, value, SOR_PLL2); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1276 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1277 | value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM; |
| 1278 | tegra_sor_writel(sor, value, SOR_PLL1); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1279 | |
| 1280 | while (true) { |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1281 | value = tegra_sor_readl(sor, SOR_PLL2); |
| 1282 | if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0) |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1283 | break; |
| 1284 | |
| 1285 | usleep_range(250, 1000); |
| 1286 | } |
| 1287 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1288 | value = tegra_sor_readl(sor, SOR_PLL2); |
| 1289 | value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; |
| 1290 | value &= ~SOR_PLL2_PORT_POWERDOWN; |
| 1291 | tegra_sor_writel(sor, value, SOR_PLL2); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1292 | |
| 1293 | /* |
| 1294 | * power up |
| 1295 | */ |
| 1296 | |
| 1297 | /* set safe link bandwidth (1.62 Gbps) */ |
| 1298 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); |
| 1299 | value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; |
| 1300 | value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62; |
| 1301 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); |
| 1302 | |
| 1303 | /* step 1 */ |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1304 | value = tegra_sor_readl(sor, SOR_PLL2); |
| 1305 | value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN | |
| 1306 | SOR_PLL2_BANDGAP_POWERDOWN; |
| 1307 | tegra_sor_writel(sor, value, SOR_PLL2); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1308 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1309 | value = tegra_sor_readl(sor, SOR_PLL0); |
| 1310 | value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; |
| 1311 | tegra_sor_writel(sor, value, SOR_PLL0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1312 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1313 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1314 | value &= ~SOR_DP_PADCTL_PAD_CAL_PD; |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1315 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1316 | |
| 1317 | /* step 2 */ |
| 1318 | err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS); |
Thierry Reding | 850bab4 | 2015-07-29 17:58:41 +0200 | [diff] [blame] | 1319 | if (err < 0) |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1320 | dev_err(sor->dev, "failed to power on I/O rail: %d\n", err); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1321 | |
| 1322 | usleep_range(5, 100); |
| 1323 | |
| 1324 | /* step 3 */ |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1325 | value = tegra_sor_readl(sor, SOR_PLL2); |
| 1326 | value &= ~SOR_PLL2_BANDGAP_POWERDOWN; |
| 1327 | tegra_sor_writel(sor, value, SOR_PLL2); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1328 | |
| 1329 | usleep_range(20, 100); |
| 1330 | |
| 1331 | /* step 4 */ |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1332 | value = tegra_sor_readl(sor, SOR_PLL0); |
| 1333 | value &= ~SOR_PLL0_VCOPD; |
| 1334 | value &= ~SOR_PLL0_PWR; |
| 1335 | tegra_sor_writel(sor, value, SOR_PLL0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1336 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1337 | value = tegra_sor_readl(sor, SOR_PLL2); |
| 1338 | value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; |
| 1339 | tegra_sor_writel(sor, value, SOR_PLL2); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1340 | |
| 1341 | usleep_range(200, 1000); |
| 1342 | |
| 1343 | /* step 5 */ |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1344 | value = tegra_sor_readl(sor, SOR_PLL2); |
| 1345 | value &= ~SOR_PLL2_PORT_POWERDOWN; |
| 1346 | tegra_sor_writel(sor, value, SOR_PLL2); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1347 | |
Thierry Reding | 25bb2ce | 2015-08-03 14:23:29 +0200 | [diff] [blame^] | 1348 | /* switch to DP parent clock */ |
| 1349 | err = tegra_sor_set_parent_clock(sor, sor->clk_dp); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1350 | if (err < 0) |
Thierry Reding | 25bb2ce | 2015-08-03 14:23:29 +0200 | [diff] [blame^] | 1351 | dev_err(sor->dev, "failed to set parent clock: %d\n", err); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1352 | |
Thierry Reding | 899451b | 2014-06-05 16:19:48 +0200 | [diff] [blame] | 1353 | /* power DP lanes */ |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1354 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
Thierry Reding | 899451b | 2014-06-05 16:19:48 +0200 | [diff] [blame] | 1355 | |
| 1356 | if (link.num_lanes <= 2) |
| 1357 | value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2); |
| 1358 | else |
| 1359 | value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2; |
| 1360 | |
| 1361 | if (link.num_lanes <= 1) |
| 1362 | value &= ~SOR_DP_PADCTL_PD_TXD_1; |
| 1363 | else |
| 1364 | value |= SOR_DP_PADCTL_PD_TXD_1; |
| 1365 | |
| 1366 | if (link.num_lanes == 0) |
| 1367 | value &= ~SOR_DP_PADCTL_PD_TXD_0; |
| 1368 | else |
| 1369 | value |= SOR_DP_PADCTL_PD_TXD_0; |
| 1370 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1371 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1372 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1373 | value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1374 | value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; |
Thierry Reding | 0c90a18 | 2014-06-05 16:29:46 +0200 | [diff] [blame] | 1375 | value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes); |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1376 | tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1377 | |
| 1378 | /* start lane sequencer */ |
| 1379 | value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | |
| 1380 | SOR_LANE_SEQ_CTL_POWER_STATE_UP; |
| 1381 | tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); |
| 1382 | |
| 1383 | while (true) { |
| 1384 | value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); |
| 1385 | if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) |
| 1386 | break; |
| 1387 | |
| 1388 | usleep_range(250, 1000); |
| 1389 | } |
| 1390 | |
Thierry Reding | a4263fe | 2014-06-05 16:16:23 +0200 | [diff] [blame] | 1391 | /* set link bandwidth */ |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1392 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); |
| 1393 | value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; |
Thierry Reding | a4263fe | 2014-06-05 16:16:23 +0200 | [diff] [blame] | 1394 | value |= drm_dp_link_rate_to_bw_code(link.rate) << 2; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1395 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); |
| 1396 | |
| 1397 | /* set linkctl */ |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1398 | value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1399 | value |= SOR_DP_LINKCTL_ENABLE; |
| 1400 | |
| 1401 | value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 1402 | value |= SOR_DP_LINKCTL_TU_SIZE(config.tu_size); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1403 | |
| 1404 | value |= SOR_DP_LINKCTL_ENHANCED_FRAME; |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1405 | tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1406 | |
| 1407 | for (i = 0, value = 0; i < 4; i++) { |
| 1408 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | |
| 1409 | SOR_DP_TPG_SCRAMBLER_GALIOS | |
| 1410 | SOR_DP_TPG_PATTERN_NONE; |
| 1411 | value = (value << 8) | lane; |
| 1412 | } |
| 1413 | |
| 1414 | tegra_sor_writel(sor, value, SOR_DP_TPG); |
| 1415 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1416 | value = tegra_sor_readl(sor, SOR_DP_CONFIG0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1417 | value &= ~SOR_DP_CONFIG_WATERMARK_MASK; |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 1418 | value |= SOR_DP_CONFIG_WATERMARK(config.watermark); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1419 | |
| 1420 | value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 1421 | value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config.active_count); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1422 | |
| 1423 | value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 1424 | value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config.active_frac); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1425 | |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 1426 | if (config.active_polarity) |
| 1427 | value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; |
| 1428 | else |
| 1429 | value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1430 | |
| 1431 | value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; |
Thierry Reding | 1f64ae7 | 2014-06-05 16:20:27 +0200 | [diff] [blame] | 1432 | value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1433 | tegra_sor_writel(sor, value, SOR_DP_CONFIG0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1434 | |
| 1435 | value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); |
| 1436 | value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; |
Thierry Reding | 7890b57 | 2014-06-05 16:12:46 +0200 | [diff] [blame] | 1437 | value |= config.hblank_symbols & 0xffff; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1438 | tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); |
| 1439 | |
| 1440 | value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); |
| 1441 | value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; |
Thierry Reding | 7890b57 | 2014-06-05 16:12:46 +0200 | [diff] [blame] | 1442 | value |= config.vblank_symbols & 0xffff; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1443 | tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); |
| 1444 | |
| 1445 | /* enable pad calibration logic */ |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1446 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1447 | value |= SOR_DP_PADCTL_PAD_CAL_PD; |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1448 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1449 | |
Thierry Reding | 01b9bea | 2015-11-11 17:15:29 +0100 | [diff] [blame] | 1450 | err = drm_dp_link_probe(sor->aux, &link); |
| 1451 | if (err < 0) |
| 1452 | dev_err(sor->dev, "failed to probe eDP link: %d\n", err); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1453 | |
Thierry Reding | 01b9bea | 2015-11-11 17:15:29 +0100 | [diff] [blame] | 1454 | err = drm_dp_link_power_up(sor->aux, &link); |
| 1455 | if (err < 0) |
| 1456 | dev_err(sor->dev, "failed to power up eDP link: %d\n", err); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1457 | |
Thierry Reding | 01b9bea | 2015-11-11 17:15:29 +0100 | [diff] [blame] | 1458 | err = drm_dp_link_configure(sor->aux, &link); |
| 1459 | if (err < 0) |
| 1460 | dev_err(sor->dev, "failed to configure eDP link: %d\n", err); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1461 | |
Thierry Reding | 01b9bea | 2015-11-11 17:15:29 +0100 | [diff] [blame] | 1462 | rate = drm_dp_link_rate_to_bw_code(link.rate); |
| 1463 | lanes = link.num_lanes; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1464 | |
Thierry Reding | 01b9bea | 2015-11-11 17:15:29 +0100 | [diff] [blame] | 1465 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); |
| 1466 | value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; |
| 1467 | value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); |
| 1468 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1469 | |
Thierry Reding | 01b9bea | 2015-11-11 17:15:29 +0100 | [diff] [blame] | 1470 | value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); |
| 1471 | value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; |
| 1472 | value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1473 | |
Thierry Reding | 01b9bea | 2015-11-11 17:15:29 +0100 | [diff] [blame] | 1474 | if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) |
| 1475 | value |= SOR_DP_LINKCTL_ENHANCED_FRAME; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1476 | |
Thierry Reding | 01b9bea | 2015-11-11 17:15:29 +0100 | [diff] [blame] | 1477 | tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1478 | |
Thierry Reding | 01b9bea | 2015-11-11 17:15:29 +0100 | [diff] [blame] | 1479 | /* disable training pattern generator */ |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1480 | |
Thierry Reding | 01b9bea | 2015-11-11 17:15:29 +0100 | [diff] [blame] | 1481 | for (i = 0; i < link.num_lanes; i++) { |
| 1482 | unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | |
| 1483 | SOR_DP_TPG_SCRAMBLER_GALIOS | |
| 1484 | SOR_DP_TPG_PATTERN_NONE; |
| 1485 | value = (value << 8) | lane; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1486 | } |
| 1487 | |
Thierry Reding | 01b9bea | 2015-11-11 17:15:29 +0100 | [diff] [blame] | 1488 | tegra_sor_writel(sor, value, SOR_DP_TPG); |
| 1489 | |
| 1490 | err = tegra_sor_dp_train_fast(sor, &link); |
| 1491 | if (err < 0) |
| 1492 | dev_err(sor->dev, "DP fast link training failed: %d\n", err); |
| 1493 | |
| 1494 | dev_dbg(sor->dev, "fast link training succeeded\n"); |
| 1495 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1496 | err = tegra_sor_power_up(sor, 250); |
Thierry Reding | 850bab4 | 2015-07-29 17:58:41 +0200 | [diff] [blame] | 1497 | if (err < 0) |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1498 | dev_err(sor->dev, "failed to power up SOR: %d\n", err); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1499 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1500 | /* |
| 1501 | * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete |
| 1502 | * raster, associate with display controller) |
| 1503 | */ |
Thierry Reding | 3f4f3b5 | 2014-07-07 15:35:06 +0200 | [diff] [blame] | 1504 | value = SOR_STATE_ASY_PROTOCOL_DP_A | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1505 | SOR_STATE_ASY_CRC_MODE_COMPLETE | |
| 1506 | SOR_STATE_ASY_OWNER(dc->pipe + 1); |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 1507 | |
Thierry Reding | 3f4f3b5 | 2014-07-07 15:35:06 +0200 | [diff] [blame] | 1508 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 1509 | value &= ~SOR_STATE_ASY_HSYNCPOL; |
| 1510 | |
| 1511 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 1512 | value |= SOR_STATE_ASY_HSYNCPOL; |
| 1513 | |
| 1514 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 1515 | value &= ~SOR_STATE_ASY_VSYNCPOL; |
| 1516 | |
| 1517 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 1518 | value |= SOR_STATE_ASY_VSYNCPOL; |
| 1519 | |
Thierry Reding | 34fa183 | 2014-06-05 16:31:10 +0200 | [diff] [blame] | 1520 | switch (config.bits_per_pixel) { |
| 1521 | case 24: |
| 1522 | value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; |
| 1523 | break; |
| 1524 | |
| 1525 | case 18: |
| 1526 | value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; |
| 1527 | break; |
| 1528 | |
| 1529 | default: |
| 1530 | BUG(); |
| 1531 | break; |
| 1532 | } |
| 1533 | |
Thierry Reding | a9a9e4f | 2015-04-27 15:01:14 +0200 | [diff] [blame] | 1534 | tegra_sor_writel(sor, value, SOR_STATE1); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1535 | |
| 1536 | /* |
| 1537 | * TODO: The video timing programming below doesn't seem to match the |
| 1538 | * register definitions. |
| 1539 | */ |
| 1540 | |
| 1541 | value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); |
Thierry Reding | 51511d0 | 2015-07-30 18:47:07 +0200 | [diff] [blame] | 1542 | tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe)); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1543 | |
| 1544 | vse = mode->vsync_end - mode->vsync_start - 1; |
| 1545 | hse = mode->hsync_end - mode->hsync_start - 1; |
| 1546 | |
| 1547 | value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); |
Thierry Reding | 51511d0 | 2015-07-30 18:47:07 +0200 | [diff] [blame] | 1548 | tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe)); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1549 | |
| 1550 | vbe = vse + (mode->vsync_start - mode->vdisplay); |
| 1551 | hbe = hse + (mode->hsync_start - mode->hdisplay); |
| 1552 | |
| 1553 | value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); |
Thierry Reding | 51511d0 | 2015-07-30 18:47:07 +0200 | [diff] [blame] | 1554 | tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe)); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1555 | |
| 1556 | vbs = vbe + mode->vdisplay; |
| 1557 | hbs = hbe + mode->hdisplay; |
| 1558 | |
| 1559 | value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); |
Thierry Reding | 51511d0 | 2015-07-30 18:47:07 +0200 | [diff] [blame] | 1560 | tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe)); |
| 1561 | |
| 1562 | tegra_sor_writel(sor, 0x1, SOR_HEAD_STATE5(dc->pipe)); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1563 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1564 | /* CSTM (LVDS, link A/B, upper) */ |
Stéphane Marchesin | 143b1df | 2014-05-22 20:32:47 -0700 | [diff] [blame] | 1565 | value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1566 | SOR_CSTM_UPPER; |
| 1567 | tegra_sor_writel(sor, value, SOR_CSTM); |
| 1568 | |
| 1569 | /* PWM setup */ |
| 1570 | err = tegra_sor_setup_pwm(sor, 250); |
Thierry Reding | 850bab4 | 2015-07-29 17:58:41 +0200 | [diff] [blame] | 1571 | if (err < 0) |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1572 | dev_err(sor->dev, "failed to setup PWM: %d\n", err); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1573 | |
Thierry Reding | 666cb87 | 2014-12-08 16:32:47 +0100 | [diff] [blame] | 1574 | tegra_sor_update(sor); |
| 1575 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1576 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); |
| 1577 | value |= SOR_ENABLE; |
| 1578 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); |
| 1579 | |
Thierry Reding | 666cb87 | 2014-12-08 16:32:47 +0100 | [diff] [blame] | 1580 | tegra_dc_commit(dc); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1581 | |
| 1582 | err = tegra_sor_attach(sor); |
Thierry Reding | 850bab4 | 2015-07-29 17:58:41 +0200 | [diff] [blame] | 1583 | if (err < 0) |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1584 | dev_err(sor->dev, "failed to attach SOR: %d\n", err); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1585 | |
| 1586 | err = tegra_sor_wakeup(sor); |
Thierry Reding | 850bab4 | 2015-07-29 17:58:41 +0200 | [diff] [blame] | 1587 | if (err < 0) |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1588 | dev_err(sor->dev, "failed to enable DC: %d\n", err); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1589 | |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 1590 | if (output->panel) |
| 1591 | drm_panel_enable(output->panel); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1592 | } |
| 1593 | |
Thierry Reding | 82f1511 | 2014-12-08 17:26:46 +0100 | [diff] [blame] | 1594 | static int |
| 1595 | tegra_sor_encoder_atomic_check(struct drm_encoder *encoder, |
| 1596 | struct drm_crtc_state *crtc_state, |
| 1597 | struct drm_connector_state *conn_state) |
| 1598 | { |
| 1599 | struct tegra_output *output = encoder_to_output(encoder); |
| 1600 | struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); |
| 1601 | unsigned long pclk = crtc_state->mode.clock * 1000; |
| 1602 | struct tegra_sor *sor = to_sor(output); |
| 1603 | int err; |
| 1604 | |
| 1605 | err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, |
| 1606 | pclk, 0); |
| 1607 | if (err < 0) { |
| 1608 | dev_err(output->dev, "failed to setup CRTC state: %d\n", err); |
| 1609 | return err; |
| 1610 | } |
| 1611 | |
| 1612 | return 0; |
| 1613 | } |
| 1614 | |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 1615 | static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = { |
Thierry Reding | 850bab4 | 2015-07-29 17:58:41 +0200 | [diff] [blame] | 1616 | .disable = tegra_sor_edp_disable, |
| 1617 | .enable = tegra_sor_edp_enable, |
Thierry Reding | 82f1511 | 2014-12-08 17:26:46 +0100 | [diff] [blame] | 1618 | .atomic_check = tegra_sor_encoder_atomic_check, |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1619 | }; |
| 1620 | |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 1621 | static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size) |
| 1622 | { |
| 1623 | u32 value = 0; |
| 1624 | size_t i; |
| 1625 | |
| 1626 | for (i = size; i > 0; i--) |
| 1627 | value = (value << 8) | ptr[i - 1]; |
| 1628 | |
| 1629 | return value; |
| 1630 | } |
| 1631 | |
| 1632 | static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor, |
| 1633 | const void *data, size_t size) |
| 1634 | { |
| 1635 | const u8 *ptr = data; |
| 1636 | unsigned long offset; |
| 1637 | size_t i, j; |
| 1638 | u32 value; |
| 1639 | |
| 1640 | switch (ptr[0]) { |
| 1641 | case HDMI_INFOFRAME_TYPE_AVI: |
| 1642 | offset = SOR_HDMI_AVI_INFOFRAME_HEADER; |
| 1643 | break; |
| 1644 | |
| 1645 | case HDMI_INFOFRAME_TYPE_AUDIO: |
| 1646 | offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER; |
| 1647 | break; |
| 1648 | |
| 1649 | case HDMI_INFOFRAME_TYPE_VENDOR: |
| 1650 | offset = SOR_HDMI_VSI_INFOFRAME_HEADER; |
| 1651 | break; |
| 1652 | |
| 1653 | default: |
| 1654 | dev_err(sor->dev, "unsupported infoframe type: %02x\n", |
| 1655 | ptr[0]); |
| 1656 | return; |
| 1657 | } |
| 1658 | |
| 1659 | value = INFOFRAME_HEADER_TYPE(ptr[0]) | |
| 1660 | INFOFRAME_HEADER_VERSION(ptr[1]) | |
| 1661 | INFOFRAME_HEADER_LEN(ptr[2]); |
| 1662 | tegra_sor_writel(sor, value, offset); |
| 1663 | offset++; |
| 1664 | |
| 1665 | /* |
| 1666 | * Each subpack contains 7 bytes, divided into: |
| 1667 | * - subpack_low: bytes 0 - 3 |
| 1668 | * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) |
| 1669 | */ |
| 1670 | for (i = 3, j = 0; i < size; i += 7, j += 8) { |
| 1671 | size_t rem = size - i, num = min_t(size_t, rem, 4); |
| 1672 | |
| 1673 | value = tegra_sor_hdmi_subpack(&ptr[i], num); |
| 1674 | tegra_sor_writel(sor, value, offset++); |
| 1675 | |
| 1676 | num = min_t(size_t, rem - num, 3); |
| 1677 | |
| 1678 | value = tegra_sor_hdmi_subpack(&ptr[i + 4], num); |
| 1679 | tegra_sor_writel(sor, value, offset++); |
| 1680 | } |
| 1681 | } |
| 1682 | |
| 1683 | static int |
| 1684 | tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor, |
| 1685 | const struct drm_display_mode *mode) |
| 1686 | { |
| 1687 | u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; |
| 1688 | struct hdmi_avi_infoframe frame; |
| 1689 | u32 value; |
| 1690 | int err; |
| 1691 | |
| 1692 | /* disable AVI infoframe */ |
| 1693 | value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); |
| 1694 | value &= ~INFOFRAME_CTRL_SINGLE; |
| 1695 | value &= ~INFOFRAME_CTRL_OTHER; |
| 1696 | value &= ~INFOFRAME_CTRL_ENABLE; |
| 1697 | tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); |
| 1698 | |
| 1699 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
| 1700 | if (err < 0) { |
| 1701 | dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); |
| 1702 | return err; |
| 1703 | } |
| 1704 | |
| 1705 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
| 1706 | if (err < 0) { |
| 1707 | dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); |
| 1708 | return err; |
| 1709 | } |
| 1710 | |
| 1711 | tegra_sor_hdmi_write_infopack(sor, buffer, err); |
| 1712 | |
| 1713 | /* enable AVI infoframe */ |
| 1714 | value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); |
| 1715 | value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; |
| 1716 | value |= INFOFRAME_CTRL_ENABLE; |
| 1717 | tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); |
| 1718 | |
| 1719 | return 0; |
| 1720 | } |
| 1721 | |
| 1722 | static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor) |
| 1723 | { |
| 1724 | u32 value; |
| 1725 | |
| 1726 | value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); |
| 1727 | value &= ~INFOFRAME_CTRL_ENABLE; |
| 1728 | tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); |
| 1729 | } |
| 1730 | |
| 1731 | static struct tegra_sor_hdmi_settings * |
| 1732 | tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency) |
| 1733 | { |
| 1734 | unsigned int i; |
| 1735 | |
| 1736 | for (i = 0; i < sor->num_settings; i++) |
| 1737 | if (frequency <= sor->settings[i].frequency) |
| 1738 | return &sor->settings[i]; |
| 1739 | |
| 1740 | return NULL; |
| 1741 | } |
| 1742 | |
| 1743 | static void tegra_sor_hdmi_disable(struct drm_encoder *encoder) |
| 1744 | { |
| 1745 | struct tegra_output *output = encoder_to_output(encoder); |
| 1746 | struct tegra_dc *dc = to_tegra_dc(encoder->crtc); |
| 1747 | struct tegra_sor *sor = to_sor(output); |
| 1748 | u32 value; |
| 1749 | int err; |
| 1750 | |
| 1751 | err = tegra_sor_detach(sor); |
| 1752 | if (err < 0) |
| 1753 | dev_err(sor->dev, "failed to detach SOR: %d\n", err); |
| 1754 | |
| 1755 | tegra_sor_writel(sor, 0, SOR_STATE1); |
| 1756 | tegra_sor_update(sor); |
| 1757 | |
| 1758 | /* disable display to SOR clock */ |
| 1759 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); |
| 1760 | value &= ~SOR1_TIMING_CYA; |
| 1761 | value &= ~SOR1_ENABLE; |
| 1762 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); |
| 1763 | |
| 1764 | tegra_dc_commit(dc); |
| 1765 | |
| 1766 | err = tegra_sor_power_down(sor); |
| 1767 | if (err < 0) |
| 1768 | dev_err(sor->dev, "failed to power down SOR: %d\n", err); |
| 1769 | |
| 1770 | err = tegra_io_rail_power_off(TEGRA_IO_RAIL_HDMI); |
| 1771 | if (err < 0) |
| 1772 | dev_err(sor->dev, "failed to power off HDMI rail: %d\n", err); |
| 1773 | |
| 1774 | reset_control_assert(sor->rst); |
| 1775 | usleep_range(1000, 2000); |
| 1776 | clk_disable_unprepare(sor->clk); |
| 1777 | } |
| 1778 | |
| 1779 | static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) |
| 1780 | { |
| 1781 | struct tegra_output *output = encoder_to_output(encoder); |
| 1782 | unsigned int h_ref_to_sync = 1, pulse_start, max_ac; |
| 1783 | struct tegra_dc *dc = to_tegra_dc(encoder->crtc); |
| 1784 | unsigned int vbe, vse, hbe, hse, vbs, hbs, div; |
| 1785 | struct tegra_sor_hdmi_settings *settings; |
| 1786 | struct tegra_sor *sor = to_sor(output); |
| 1787 | struct drm_display_mode *mode; |
| 1788 | struct drm_display_info *info; |
| 1789 | u32 value; |
| 1790 | int err; |
| 1791 | |
| 1792 | mode = &encoder->crtc->state->adjusted_mode; |
| 1793 | info = &output->connector.display_info; |
| 1794 | |
| 1795 | err = clk_prepare_enable(sor->clk); |
| 1796 | if (err < 0) |
| 1797 | dev_err(sor->dev, "failed to enable clock: %d\n", err); |
| 1798 | |
| 1799 | usleep_range(1000, 2000); |
| 1800 | |
| 1801 | reset_control_deassert(sor->rst); |
| 1802 | |
Thierry Reding | 25bb2ce | 2015-08-03 14:23:29 +0200 | [diff] [blame^] | 1803 | /* switch to safe parent clock */ |
| 1804 | err = tegra_sor_set_parent_clock(sor, sor->clk_safe); |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 1805 | if (err < 0) |
| 1806 | dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); |
| 1807 | |
| 1808 | div = clk_get_rate(sor->clk) / 1000000 * 4; |
| 1809 | |
| 1810 | err = tegra_io_rail_power_on(TEGRA_IO_RAIL_HDMI); |
| 1811 | if (err < 0) |
| 1812 | dev_err(sor->dev, "failed to power on HDMI rail: %d\n", err); |
| 1813 | |
| 1814 | usleep_range(20, 100); |
| 1815 | |
| 1816 | value = tegra_sor_readl(sor, SOR_PLL2); |
| 1817 | value &= ~SOR_PLL2_BANDGAP_POWERDOWN; |
| 1818 | tegra_sor_writel(sor, value, SOR_PLL2); |
| 1819 | |
| 1820 | usleep_range(20, 100); |
| 1821 | |
| 1822 | value = tegra_sor_readl(sor, SOR_PLL3); |
| 1823 | value &= ~SOR_PLL3_PLL_VDD_MODE_3V3; |
| 1824 | tegra_sor_writel(sor, value, SOR_PLL3); |
| 1825 | |
| 1826 | value = tegra_sor_readl(sor, SOR_PLL0); |
| 1827 | value &= ~SOR_PLL0_VCOPD; |
| 1828 | value &= ~SOR_PLL0_PWR; |
| 1829 | tegra_sor_writel(sor, value, SOR_PLL0); |
| 1830 | |
| 1831 | value = tegra_sor_readl(sor, SOR_PLL2); |
| 1832 | value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; |
| 1833 | tegra_sor_writel(sor, value, SOR_PLL2); |
| 1834 | |
| 1835 | usleep_range(200, 400); |
| 1836 | |
| 1837 | value = tegra_sor_readl(sor, SOR_PLL2); |
| 1838 | value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; |
| 1839 | value &= ~SOR_PLL2_PORT_POWERDOWN; |
| 1840 | tegra_sor_writel(sor, value, SOR_PLL2); |
| 1841 | |
| 1842 | usleep_range(20, 100); |
| 1843 | |
| 1844 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
| 1845 | value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | |
| 1846 | SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2; |
| 1847 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
| 1848 | |
| 1849 | while (true) { |
| 1850 | value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); |
| 1851 | if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0) |
| 1852 | break; |
| 1853 | |
| 1854 | usleep_range(250, 1000); |
| 1855 | } |
| 1856 | |
| 1857 | value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | |
| 1858 | SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5); |
| 1859 | tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); |
| 1860 | |
| 1861 | while (true) { |
| 1862 | value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); |
| 1863 | if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) |
| 1864 | break; |
| 1865 | |
| 1866 | usleep_range(250, 1000); |
| 1867 | } |
| 1868 | |
| 1869 | value = tegra_sor_readl(sor, SOR_CLK_CNTRL); |
| 1870 | value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; |
| 1871 | value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; |
| 1872 | |
| 1873 | if (mode->clock < 340000) |
| 1874 | value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; |
| 1875 | else |
| 1876 | value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40; |
| 1877 | |
| 1878 | value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; |
| 1879 | tegra_sor_writel(sor, value, SOR_CLK_CNTRL); |
| 1880 | |
| 1881 | value = tegra_sor_readl(sor, SOR_DP_SPARE0); |
| 1882 | value |= SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; |
| 1883 | value &= ~SOR_DP_SPARE_PANEL_INTERNAL; |
| 1884 | value |= SOR_DP_SPARE_SEQ_ENABLE; |
| 1885 | tegra_sor_writel(sor, value, SOR_DP_SPARE0); |
| 1886 | |
| 1887 | value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | |
| 1888 | SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8); |
| 1889 | tegra_sor_writel(sor, value, SOR_SEQ_CTL); |
| 1890 | |
| 1891 | value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT | |
| 1892 | SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1); |
| 1893 | tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); |
| 1894 | tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); |
| 1895 | |
| 1896 | /* program the reference clock */ |
| 1897 | value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); |
| 1898 | tegra_sor_writel(sor, value, SOR_REFCLK); |
| 1899 | |
| 1900 | /* XXX don't hardcode */ |
| 1901 | value = SOR_XBAR_CTRL_LINK1_XSEL(4, 4) | |
| 1902 | SOR_XBAR_CTRL_LINK1_XSEL(3, 3) | |
| 1903 | SOR_XBAR_CTRL_LINK1_XSEL(2, 2) | |
| 1904 | SOR_XBAR_CTRL_LINK1_XSEL(1, 1) | |
| 1905 | SOR_XBAR_CTRL_LINK1_XSEL(0, 0) | |
| 1906 | SOR_XBAR_CTRL_LINK0_XSEL(4, 4) | |
| 1907 | SOR_XBAR_CTRL_LINK0_XSEL(3, 3) | |
| 1908 | SOR_XBAR_CTRL_LINK0_XSEL(2, 0) | |
| 1909 | SOR_XBAR_CTRL_LINK0_XSEL(1, 1) | |
| 1910 | SOR_XBAR_CTRL_LINK0_XSEL(0, 2); |
| 1911 | tegra_sor_writel(sor, value, SOR_XBAR_CTRL); |
| 1912 | |
| 1913 | tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); |
| 1914 | |
Thierry Reding | 25bb2ce | 2015-08-03 14:23:29 +0200 | [diff] [blame^] | 1915 | /* switch to parent clock */ |
| 1916 | err = tegra_sor_set_parent_clock(sor, sor->clk_parent); |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 1917 | if (err < 0) |
| 1918 | dev_err(sor->dev, "failed to set parent clock: %d\n", err); |
| 1919 | |
| 1920 | value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); |
| 1921 | |
| 1922 | /* XXX is this the proper check? */ |
| 1923 | if (mode->clock < 75000) |
| 1924 | value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED; |
| 1925 | |
| 1926 | tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); |
| 1927 | |
| 1928 | max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32; |
| 1929 | |
| 1930 | value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) | |
| 1931 | SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY); |
| 1932 | tegra_sor_writel(sor, value, SOR_HDMI_CTRL); |
| 1933 | |
| 1934 | /* H_PULSE2 setup */ |
| 1935 | pulse_start = h_ref_to_sync + (mode->hsync_end - mode->hsync_start) + |
| 1936 | (mode->htotal - mode->hsync_end) - 10; |
| 1937 | |
| 1938 | value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | |
| 1939 | PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL; |
| 1940 | tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); |
| 1941 | |
| 1942 | value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); |
| 1943 | tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); |
| 1944 | |
| 1945 | value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); |
| 1946 | value |= H_PULSE2_ENABLE; |
| 1947 | tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); |
| 1948 | |
| 1949 | /* infoframe setup */ |
| 1950 | err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode); |
| 1951 | if (err < 0) |
| 1952 | dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); |
| 1953 | |
| 1954 | /* XXX HDMI audio support not implemented yet */ |
| 1955 | tegra_sor_hdmi_disable_audio_infoframe(sor); |
| 1956 | |
| 1957 | /* use single TMDS protocol */ |
| 1958 | value = tegra_sor_readl(sor, SOR_STATE1); |
| 1959 | value &= ~SOR_STATE_ASY_PROTOCOL_MASK; |
| 1960 | value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A; |
| 1961 | tegra_sor_writel(sor, value, SOR_STATE1); |
| 1962 | |
| 1963 | /* power up pad calibration */ |
| 1964 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
| 1965 | value &= ~SOR_DP_PADCTL_PAD_CAL_PD; |
| 1966 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
| 1967 | |
| 1968 | /* production settings */ |
| 1969 | settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); |
Dan Carpenter | db8b42f | 2015-08-17 17:37:03 +0300 | [diff] [blame] | 1970 | if (!settings) { |
| 1971 | dev_err(sor->dev, "no settings for pixel clock %d Hz\n", |
| 1972 | mode->clock * 1000); |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 1973 | return; |
| 1974 | } |
| 1975 | |
| 1976 | value = tegra_sor_readl(sor, SOR_PLL0); |
| 1977 | value &= ~SOR_PLL0_ICHPMP_MASK; |
| 1978 | value &= ~SOR_PLL0_VCOCAP_MASK; |
| 1979 | value |= SOR_PLL0_ICHPMP(settings->ichpmp); |
| 1980 | value |= SOR_PLL0_VCOCAP(settings->vcocap); |
| 1981 | tegra_sor_writel(sor, value, SOR_PLL0); |
| 1982 | |
| 1983 | tegra_sor_dp_term_calibrate(sor); |
| 1984 | |
| 1985 | value = tegra_sor_readl(sor, SOR_PLL1); |
| 1986 | value &= ~SOR_PLL1_LOADADJ_MASK; |
| 1987 | value |= SOR_PLL1_LOADADJ(settings->loadadj); |
| 1988 | tegra_sor_writel(sor, value, SOR_PLL1); |
| 1989 | |
| 1990 | value = tegra_sor_readl(sor, SOR_PLL3); |
| 1991 | value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; |
| 1992 | value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref); |
| 1993 | tegra_sor_writel(sor, value, SOR_PLL3); |
| 1994 | |
| 1995 | value = settings->drive_current[0] << 24 | |
| 1996 | settings->drive_current[1] << 16 | |
| 1997 | settings->drive_current[2] << 8 | |
| 1998 | settings->drive_current[3] << 0; |
| 1999 | tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); |
| 2000 | |
| 2001 | value = settings->preemphasis[0] << 24 | |
| 2002 | settings->preemphasis[1] << 16 | |
| 2003 | settings->preemphasis[2] << 8 | |
| 2004 | settings->preemphasis[3] << 0; |
| 2005 | tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); |
| 2006 | |
| 2007 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
| 2008 | value &= ~SOR_DP_PADCTL_TX_PU_MASK; |
| 2009 | value |= SOR_DP_PADCTL_TX_PU_ENABLE; |
| 2010 | value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu); |
| 2011 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
| 2012 | |
| 2013 | /* power down pad calibration */ |
| 2014 | value = tegra_sor_readl(sor, SOR_DP_PADCTL0); |
| 2015 | value |= SOR_DP_PADCTL_PAD_CAL_PD; |
| 2016 | tegra_sor_writel(sor, value, SOR_DP_PADCTL0); |
| 2017 | |
| 2018 | /* miscellaneous display controller settings */ |
| 2019 | value = VSYNC_H_POSITION(1); |
| 2020 | tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); |
| 2021 | |
| 2022 | value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); |
| 2023 | value &= ~DITHER_CONTROL_MASK; |
| 2024 | value &= ~BASE_COLOR_SIZE_MASK; |
| 2025 | |
| 2026 | switch (info->bpc) { |
| 2027 | case 6: |
| 2028 | value |= BASE_COLOR_SIZE_666; |
| 2029 | break; |
| 2030 | |
| 2031 | case 8: |
| 2032 | value |= BASE_COLOR_SIZE_888; |
| 2033 | break; |
| 2034 | |
| 2035 | default: |
| 2036 | WARN(1, "%u bits-per-color not supported\n", info->bpc); |
| 2037 | break; |
| 2038 | } |
| 2039 | |
| 2040 | tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); |
| 2041 | |
| 2042 | err = tegra_sor_power_up(sor, 250); |
| 2043 | if (err < 0) |
| 2044 | dev_err(sor->dev, "failed to power up SOR: %d\n", err); |
| 2045 | |
| 2046 | /* configure mode */ |
| 2047 | value = tegra_sor_readl(sor, SOR_STATE1); |
| 2048 | value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK; |
| 2049 | value &= ~SOR_STATE_ASY_CRC_MODE_MASK; |
| 2050 | value &= ~SOR_STATE_ASY_OWNER_MASK; |
| 2051 | |
| 2052 | value |= SOR_STATE_ASY_CRC_MODE_COMPLETE | |
| 2053 | SOR_STATE_ASY_OWNER(dc->pipe + 1); |
| 2054 | |
| 2055 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 2056 | value &= ~SOR_STATE_ASY_HSYNCPOL; |
| 2057 | |
| 2058 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 2059 | value |= SOR_STATE_ASY_HSYNCPOL; |
| 2060 | |
| 2061 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 2062 | value &= ~SOR_STATE_ASY_VSYNCPOL; |
| 2063 | |
| 2064 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 2065 | value |= SOR_STATE_ASY_VSYNCPOL; |
| 2066 | |
| 2067 | switch (info->bpc) { |
| 2068 | case 8: |
| 2069 | value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; |
| 2070 | break; |
| 2071 | |
| 2072 | case 6: |
| 2073 | value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; |
| 2074 | break; |
| 2075 | |
| 2076 | default: |
| 2077 | BUG(); |
| 2078 | break; |
| 2079 | } |
| 2080 | |
| 2081 | tegra_sor_writel(sor, value, SOR_STATE1); |
| 2082 | |
| 2083 | value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe)); |
| 2084 | value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK; |
| 2085 | value &= ~SOR_HEAD_STATE_DYNRANGE_MASK; |
| 2086 | tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe)); |
| 2087 | |
| 2088 | value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe)); |
| 2089 | value &= ~SOR_HEAD_STATE_COLORSPACE_MASK; |
| 2090 | value |= SOR_HEAD_STATE_COLORSPACE_RGB; |
| 2091 | tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe)); |
| 2092 | |
| 2093 | /* |
| 2094 | * TODO: The video timing programming below doesn't seem to match the |
| 2095 | * register definitions. |
| 2096 | */ |
| 2097 | |
| 2098 | value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); |
| 2099 | tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe)); |
| 2100 | |
| 2101 | /* sync end = sync width - 1 */ |
| 2102 | vse = mode->vsync_end - mode->vsync_start - 1; |
| 2103 | hse = mode->hsync_end - mode->hsync_start - 1; |
| 2104 | |
| 2105 | value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); |
| 2106 | tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe)); |
| 2107 | |
| 2108 | /* blank end = sync end + back porch */ |
| 2109 | vbe = vse + (mode->vtotal - mode->vsync_end); |
| 2110 | hbe = hse + (mode->htotal - mode->hsync_end); |
| 2111 | |
| 2112 | value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); |
| 2113 | tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe)); |
| 2114 | |
| 2115 | /* blank start = blank end + active */ |
| 2116 | vbs = vbe + mode->vdisplay; |
| 2117 | hbs = hbe + mode->hdisplay; |
| 2118 | |
| 2119 | value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); |
| 2120 | tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe)); |
| 2121 | |
| 2122 | tegra_sor_writel(sor, 0x1, SOR_HEAD_STATE5(dc->pipe)); |
| 2123 | |
| 2124 | tegra_sor_update(sor); |
| 2125 | |
| 2126 | err = tegra_sor_attach(sor); |
| 2127 | if (err < 0) |
| 2128 | dev_err(sor->dev, "failed to attach SOR: %d\n", err); |
| 2129 | |
| 2130 | /* enable display to SOR clock and generate HDMI preamble */ |
| 2131 | value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); |
| 2132 | value |= SOR1_ENABLE | SOR1_TIMING_CYA; |
| 2133 | tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); |
| 2134 | |
| 2135 | tegra_dc_commit(dc); |
| 2136 | |
| 2137 | err = tegra_sor_wakeup(sor); |
| 2138 | if (err < 0) |
| 2139 | dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); |
| 2140 | } |
| 2141 | |
| 2142 | static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = { |
| 2143 | .disable = tegra_sor_hdmi_disable, |
| 2144 | .enable = tegra_sor_hdmi_enable, |
| 2145 | .atomic_check = tegra_sor_encoder_atomic_check, |
| 2146 | }; |
| 2147 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2148 | static int tegra_sor_init(struct host1x_client *client) |
| 2149 | { |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 2150 | struct drm_device *drm = dev_get_drvdata(client->parent); |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 2151 | const struct drm_encoder_helper_funcs *helpers = NULL; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2152 | struct tegra_sor *sor = host1x_client_to_sor(client); |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 2153 | int connector = DRM_MODE_CONNECTOR_Unknown; |
| 2154 | int encoder = DRM_MODE_ENCODER_NONE; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2155 | int err; |
| 2156 | |
Thierry Reding | 9542c23 | 2015-07-08 13:39:09 +0200 | [diff] [blame] | 2157 | if (!sor->aux) { |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 2158 | if (sor->soc->supports_hdmi) { |
| 2159 | connector = DRM_MODE_CONNECTOR_HDMIA; |
| 2160 | encoder = DRM_MODE_ENCODER_TMDS; |
| 2161 | helpers = &tegra_sor_hdmi_helpers; |
| 2162 | } else if (sor->soc->supports_lvds) { |
| 2163 | connector = DRM_MODE_CONNECTOR_LVDS; |
| 2164 | encoder = DRM_MODE_ENCODER_LVDS; |
| 2165 | } |
| 2166 | } else { |
| 2167 | if (sor->soc->supports_edp) { |
| 2168 | connector = DRM_MODE_CONNECTOR_eDP; |
| 2169 | encoder = DRM_MODE_ENCODER_TMDS; |
| 2170 | helpers = &tegra_sor_edp_helpers; |
| 2171 | } else if (sor->soc->supports_dp) { |
| 2172 | connector = DRM_MODE_CONNECTOR_DisplayPort; |
| 2173 | encoder = DRM_MODE_ENCODER_TMDS; |
| 2174 | } |
| 2175 | } |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2176 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2177 | sor->output.dev = sor->dev; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2178 | |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 2179 | drm_connector_init(drm, &sor->output.connector, |
| 2180 | &tegra_sor_connector_funcs, |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 2181 | connector); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 2182 | drm_connector_helper_add(&sor->output.connector, |
| 2183 | &tegra_sor_connector_helper_funcs); |
| 2184 | sor->output.connector.dpms = DRM_MODE_DPMS_OFF; |
| 2185 | |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 2186 | drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs, |
Ville Syrjälä | 13a3d91 | 2015-12-09 16:20:18 +0200 | [diff] [blame] | 2187 | encoder, NULL); |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 2188 | drm_encoder_helper_add(&sor->output.encoder, helpers); |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 2189 | |
| 2190 | drm_mode_connector_attach_encoder(&sor->output.connector, |
| 2191 | &sor->output.encoder); |
| 2192 | drm_connector_register(&sor->output.connector); |
| 2193 | |
Thierry Reding | ea130b2 | 2014-12-19 15:51:35 +0100 | [diff] [blame] | 2194 | err = tegra_output_init(drm, &sor->output); |
| 2195 | if (err < 0) { |
| 2196 | dev_err(client->dev, "failed to initialize output: %d\n", err); |
| 2197 | return err; |
| 2198 | } |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 2199 | |
Thierry Reding | ea130b2 | 2014-12-19 15:51:35 +0100 | [diff] [blame] | 2200 | sor->output.encoder.possible_crtcs = 0x3; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2201 | |
Thierry Reding | a82752e | 2014-01-31 10:02:15 +0100 | [diff] [blame] | 2202 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
Thierry Reding | 1b0c7b4 | 2014-05-28 13:46:12 +0200 | [diff] [blame] | 2203 | err = tegra_sor_debugfs_init(sor, drm->primary); |
Thierry Reding | a82752e | 2014-01-31 10:02:15 +0100 | [diff] [blame] | 2204 | if (err < 0) |
| 2205 | dev_err(sor->dev, "debugfs setup failed: %d\n", err); |
| 2206 | } |
| 2207 | |
Thierry Reding | 9542c23 | 2015-07-08 13:39:09 +0200 | [diff] [blame] | 2208 | if (sor->aux) { |
| 2209 | err = drm_dp_aux_attach(sor->aux, &sor->output); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2210 | if (err < 0) { |
| 2211 | dev_err(sor->dev, "failed to attach DP: %d\n", err); |
| 2212 | return err; |
| 2213 | } |
| 2214 | } |
| 2215 | |
Tomeu Vizoso | 535a65d | 2015-03-30 10:33:03 +0200 | [diff] [blame] | 2216 | /* |
| 2217 | * XXX: Remove this reset once proper hand-over from firmware to |
| 2218 | * kernel is possible. |
| 2219 | */ |
| 2220 | err = reset_control_assert(sor->rst); |
| 2221 | if (err < 0) { |
| 2222 | dev_err(sor->dev, "failed to assert SOR reset: %d\n", err); |
| 2223 | return err; |
| 2224 | } |
| 2225 | |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 2226 | err = clk_prepare_enable(sor->clk); |
| 2227 | if (err < 0) { |
| 2228 | dev_err(sor->dev, "failed to enable clock: %d\n", err); |
| 2229 | return err; |
| 2230 | } |
| 2231 | |
Tomeu Vizoso | 535a65d | 2015-03-30 10:33:03 +0200 | [diff] [blame] | 2232 | usleep_range(1000, 3000); |
| 2233 | |
| 2234 | err = reset_control_deassert(sor->rst); |
| 2235 | if (err < 0) { |
| 2236 | dev_err(sor->dev, "failed to deassert SOR reset: %d\n", err); |
| 2237 | return err; |
| 2238 | } |
| 2239 | |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 2240 | err = clk_prepare_enable(sor->clk_safe); |
| 2241 | if (err < 0) |
| 2242 | return err; |
| 2243 | |
| 2244 | err = clk_prepare_enable(sor->clk_dp); |
| 2245 | if (err < 0) |
| 2246 | return err; |
| 2247 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2248 | return 0; |
| 2249 | } |
| 2250 | |
| 2251 | static int tegra_sor_exit(struct host1x_client *client) |
| 2252 | { |
| 2253 | struct tegra_sor *sor = host1x_client_to_sor(client); |
| 2254 | int err; |
| 2255 | |
Thierry Reding | 328ec69 | 2014-12-19 15:55:08 +0100 | [diff] [blame] | 2256 | tegra_output_exit(&sor->output); |
| 2257 | |
Thierry Reding | 9542c23 | 2015-07-08 13:39:09 +0200 | [diff] [blame] | 2258 | if (sor->aux) { |
| 2259 | err = drm_dp_aux_detach(sor->aux); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2260 | if (err < 0) { |
| 2261 | dev_err(sor->dev, "failed to detach DP: %d\n", err); |
| 2262 | return err; |
| 2263 | } |
| 2264 | } |
| 2265 | |
Thierry Reding | 6fad8f6 | 2014-11-28 15:41:34 +0100 | [diff] [blame] | 2266 | clk_disable_unprepare(sor->clk_safe); |
| 2267 | clk_disable_unprepare(sor->clk_dp); |
| 2268 | clk_disable_unprepare(sor->clk); |
| 2269 | |
Thierry Reding | 4009c22 | 2014-12-19 15:47:30 +0100 | [diff] [blame] | 2270 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
| 2271 | tegra_sor_debugfs_exit(sor); |
Thierry Reding | a82752e | 2014-01-31 10:02:15 +0100 | [diff] [blame] | 2272 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2273 | return 0; |
| 2274 | } |
| 2275 | |
| 2276 | static const struct host1x_client_ops sor_client_ops = { |
| 2277 | .init = tegra_sor_init, |
| 2278 | .exit = tegra_sor_exit, |
| 2279 | }; |
| 2280 | |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 2281 | static const struct tegra_sor_ops tegra_sor_edp_ops = { |
| 2282 | .name = "eDP", |
| 2283 | }; |
| 2284 | |
| 2285 | static int tegra_sor_hdmi_probe(struct tegra_sor *sor) |
| 2286 | { |
| 2287 | int err; |
| 2288 | |
| 2289 | sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io"); |
| 2290 | if (IS_ERR(sor->avdd_io_supply)) { |
| 2291 | dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n", |
| 2292 | PTR_ERR(sor->avdd_io_supply)); |
| 2293 | return PTR_ERR(sor->avdd_io_supply); |
| 2294 | } |
| 2295 | |
| 2296 | err = regulator_enable(sor->avdd_io_supply); |
| 2297 | if (err < 0) { |
| 2298 | dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", |
| 2299 | err); |
| 2300 | return err; |
| 2301 | } |
| 2302 | |
| 2303 | sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll"); |
| 2304 | if (IS_ERR(sor->vdd_pll_supply)) { |
| 2305 | dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n", |
| 2306 | PTR_ERR(sor->vdd_pll_supply)); |
| 2307 | return PTR_ERR(sor->vdd_pll_supply); |
| 2308 | } |
| 2309 | |
| 2310 | err = regulator_enable(sor->vdd_pll_supply); |
| 2311 | if (err < 0) { |
| 2312 | dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", |
| 2313 | err); |
| 2314 | return err; |
| 2315 | } |
| 2316 | |
| 2317 | sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); |
| 2318 | if (IS_ERR(sor->hdmi_supply)) { |
| 2319 | dev_err(sor->dev, "cannot get HDMI supply: %ld\n", |
| 2320 | PTR_ERR(sor->hdmi_supply)); |
| 2321 | return PTR_ERR(sor->hdmi_supply); |
| 2322 | } |
| 2323 | |
| 2324 | err = regulator_enable(sor->hdmi_supply); |
| 2325 | if (err < 0) { |
| 2326 | dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); |
| 2327 | return err; |
| 2328 | } |
| 2329 | |
| 2330 | return 0; |
| 2331 | } |
| 2332 | |
| 2333 | static int tegra_sor_hdmi_remove(struct tegra_sor *sor) |
| 2334 | { |
| 2335 | regulator_disable(sor->hdmi_supply); |
| 2336 | regulator_disable(sor->vdd_pll_supply); |
| 2337 | regulator_disable(sor->avdd_io_supply); |
| 2338 | |
| 2339 | return 0; |
| 2340 | } |
| 2341 | |
| 2342 | static const struct tegra_sor_ops tegra_sor_hdmi_ops = { |
| 2343 | .name = "HDMI", |
| 2344 | .probe = tegra_sor_hdmi_probe, |
| 2345 | .remove = tegra_sor_hdmi_remove, |
| 2346 | }; |
| 2347 | |
| 2348 | static const struct tegra_sor_soc tegra124_sor = { |
| 2349 | .supports_edp = true, |
| 2350 | .supports_lvds = true, |
| 2351 | .supports_hdmi = false, |
| 2352 | .supports_dp = false, |
| 2353 | }; |
| 2354 | |
| 2355 | static const struct tegra_sor_soc tegra210_sor = { |
| 2356 | .supports_edp = true, |
| 2357 | .supports_lvds = false, |
| 2358 | .supports_hdmi = false, |
| 2359 | .supports_dp = false, |
| 2360 | }; |
| 2361 | |
| 2362 | static const struct tegra_sor_soc tegra210_sor1 = { |
| 2363 | .supports_edp = false, |
| 2364 | .supports_lvds = false, |
| 2365 | .supports_hdmi = true, |
| 2366 | .supports_dp = true, |
| 2367 | |
| 2368 | .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults), |
| 2369 | .settings = tegra210_sor_hdmi_defaults, |
| 2370 | }; |
| 2371 | |
| 2372 | static const struct of_device_id tegra_sor_of_match[] = { |
| 2373 | { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 }, |
| 2374 | { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor }, |
| 2375 | { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor }, |
| 2376 | { }, |
| 2377 | }; |
| 2378 | MODULE_DEVICE_TABLE(of, tegra_sor_of_match); |
| 2379 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2380 | static int tegra_sor_probe(struct platform_device *pdev) |
| 2381 | { |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 2382 | const struct of_device_id *match; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2383 | struct device_node *np; |
| 2384 | struct tegra_sor *sor; |
| 2385 | struct resource *regs; |
| 2386 | int err; |
| 2387 | |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 2388 | match = of_match_device(tegra_sor_of_match, &pdev->dev); |
| 2389 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2390 | sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); |
| 2391 | if (!sor) |
| 2392 | return -ENOMEM; |
| 2393 | |
| 2394 | sor->output.dev = sor->dev = &pdev->dev; |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 2395 | sor->soc = match->data; |
| 2396 | |
| 2397 | sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, |
| 2398 | sor->soc->num_settings * |
| 2399 | sizeof(*sor->settings), |
| 2400 | GFP_KERNEL); |
| 2401 | if (!sor->settings) |
| 2402 | return -ENOMEM; |
| 2403 | |
| 2404 | sor->num_settings = sor->soc->num_settings; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2405 | |
| 2406 | np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); |
| 2407 | if (np) { |
Thierry Reding | 9542c23 | 2015-07-08 13:39:09 +0200 | [diff] [blame] | 2408 | sor->aux = drm_dp_aux_find_by_of_node(np); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2409 | of_node_put(np); |
| 2410 | |
Thierry Reding | 9542c23 | 2015-07-08 13:39:09 +0200 | [diff] [blame] | 2411 | if (!sor->aux) |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2412 | return -EPROBE_DEFER; |
| 2413 | } |
| 2414 | |
Thierry Reding | 9542c23 | 2015-07-08 13:39:09 +0200 | [diff] [blame] | 2415 | if (!sor->aux) { |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 2416 | if (sor->soc->supports_hdmi) { |
| 2417 | sor->ops = &tegra_sor_hdmi_ops; |
| 2418 | } else if (sor->soc->supports_lvds) { |
| 2419 | dev_err(&pdev->dev, "LVDS not supported yet\n"); |
| 2420 | return -ENODEV; |
| 2421 | } else { |
| 2422 | dev_err(&pdev->dev, "unknown (non-DP) support\n"); |
| 2423 | return -ENODEV; |
| 2424 | } |
| 2425 | } else { |
| 2426 | if (sor->soc->supports_edp) { |
| 2427 | sor->ops = &tegra_sor_edp_ops; |
| 2428 | } else if (sor->soc->supports_dp) { |
| 2429 | dev_err(&pdev->dev, "DisplayPort not supported yet\n"); |
| 2430 | return -ENODEV; |
| 2431 | } else { |
| 2432 | dev_err(&pdev->dev, "unknown (DP) support\n"); |
| 2433 | return -ENODEV; |
| 2434 | } |
| 2435 | } |
| 2436 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2437 | err = tegra_output_probe(&sor->output); |
Thierry Reding | 4dbdc74 | 2015-04-27 15:04:26 +0200 | [diff] [blame] | 2438 | if (err < 0) { |
| 2439 | dev_err(&pdev->dev, "failed to probe output: %d\n", err); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2440 | return err; |
Thierry Reding | 4dbdc74 | 2015-04-27 15:04:26 +0200 | [diff] [blame] | 2441 | } |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2442 | |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 2443 | if (sor->ops && sor->ops->probe) { |
| 2444 | err = sor->ops->probe(sor); |
| 2445 | if (err < 0) { |
| 2446 | dev_err(&pdev->dev, "failed to probe %s: %d\n", |
| 2447 | sor->ops->name, err); |
| 2448 | goto output; |
| 2449 | } |
| 2450 | } |
| 2451 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2452 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 2453 | sor->regs = devm_ioremap_resource(&pdev->dev, regs); |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 2454 | if (IS_ERR(sor->regs)) { |
| 2455 | err = PTR_ERR(sor->regs); |
| 2456 | goto remove; |
| 2457 | } |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2458 | |
| 2459 | sor->rst = devm_reset_control_get(&pdev->dev, "sor"); |
Thierry Reding | 4dbdc74 | 2015-04-27 15:04:26 +0200 | [diff] [blame] | 2460 | if (IS_ERR(sor->rst)) { |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 2461 | err = PTR_ERR(sor->rst); |
| 2462 | dev_err(&pdev->dev, "failed to get reset control: %d\n", err); |
| 2463 | goto remove; |
Thierry Reding | 4dbdc74 | 2015-04-27 15:04:26 +0200 | [diff] [blame] | 2464 | } |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2465 | |
| 2466 | sor->clk = devm_clk_get(&pdev->dev, NULL); |
Thierry Reding | 4dbdc74 | 2015-04-27 15:04:26 +0200 | [diff] [blame] | 2467 | if (IS_ERR(sor->clk)) { |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 2468 | err = PTR_ERR(sor->clk); |
| 2469 | dev_err(&pdev->dev, "failed to get module clock: %d\n", err); |
| 2470 | goto remove; |
Thierry Reding | 4dbdc74 | 2015-04-27 15:04:26 +0200 | [diff] [blame] | 2471 | } |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2472 | |
| 2473 | sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); |
Thierry Reding | 4dbdc74 | 2015-04-27 15:04:26 +0200 | [diff] [blame] | 2474 | if (IS_ERR(sor->clk_parent)) { |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 2475 | err = PTR_ERR(sor->clk_parent); |
| 2476 | dev_err(&pdev->dev, "failed to get parent clock: %d\n", err); |
| 2477 | goto remove; |
Thierry Reding | 4dbdc74 | 2015-04-27 15:04:26 +0200 | [diff] [blame] | 2478 | } |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2479 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2480 | sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); |
Thierry Reding | 4dbdc74 | 2015-04-27 15:04:26 +0200 | [diff] [blame] | 2481 | if (IS_ERR(sor->clk_safe)) { |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 2482 | err = PTR_ERR(sor->clk_safe); |
| 2483 | dev_err(&pdev->dev, "failed to get safe clock: %d\n", err); |
| 2484 | goto remove; |
Thierry Reding | 4dbdc74 | 2015-04-27 15:04:26 +0200 | [diff] [blame] | 2485 | } |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2486 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2487 | sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); |
Thierry Reding | 4dbdc74 | 2015-04-27 15:04:26 +0200 | [diff] [blame] | 2488 | if (IS_ERR(sor->clk_dp)) { |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 2489 | err = PTR_ERR(sor->clk_dp); |
| 2490 | dev_err(&pdev->dev, "failed to get DP clock: %d\n", err); |
| 2491 | goto remove; |
Thierry Reding | 4dbdc74 | 2015-04-27 15:04:26 +0200 | [diff] [blame] | 2492 | } |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2493 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2494 | INIT_LIST_HEAD(&sor->client.list); |
| 2495 | sor->client.ops = &sor_client_ops; |
| 2496 | sor->client.dev = &pdev->dev; |
| 2497 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2498 | err = host1x_client_register(&sor->client); |
| 2499 | if (err < 0) { |
| 2500 | dev_err(&pdev->dev, "failed to register host1x client: %d\n", |
| 2501 | err); |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 2502 | goto remove; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2503 | } |
| 2504 | |
| 2505 | platform_set_drvdata(pdev, sor); |
| 2506 | |
| 2507 | return 0; |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 2508 | |
| 2509 | remove: |
| 2510 | if (sor->ops && sor->ops->remove) |
| 2511 | sor->ops->remove(sor); |
| 2512 | output: |
| 2513 | tegra_output_remove(&sor->output); |
| 2514 | return err; |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2515 | } |
| 2516 | |
| 2517 | static int tegra_sor_remove(struct platform_device *pdev) |
| 2518 | { |
| 2519 | struct tegra_sor *sor = platform_get_drvdata(pdev); |
| 2520 | int err; |
| 2521 | |
| 2522 | err = host1x_client_unregister(&sor->client); |
| 2523 | if (err < 0) { |
| 2524 | dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", |
| 2525 | err); |
| 2526 | return err; |
| 2527 | } |
| 2528 | |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 2529 | if (sor->ops && sor->ops->remove) { |
| 2530 | err = sor->ops->remove(sor); |
| 2531 | if (err < 0) |
| 2532 | dev_err(&pdev->dev, "failed to remove SOR: %d\n", err); |
| 2533 | } |
| 2534 | |
Thierry Reding | 328ec69 | 2014-12-19 15:55:08 +0100 | [diff] [blame] | 2535 | tegra_output_remove(&sor->output); |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2536 | |
| 2537 | return 0; |
| 2538 | } |
| 2539 | |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 2540 | struct platform_driver tegra_sor_driver = { |
| 2541 | .driver = { |
| 2542 | .name = "tegra-sor", |
| 2543 | .of_match_table = tegra_sor_of_match, |
| 2544 | }, |
| 2545 | .probe = tegra_sor_probe, |
| 2546 | .remove = tegra_sor_remove, |
| 2547 | }; |