Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/char/8250_pci.c |
| 3 | * |
| 4 | * Probe module for 8250/16550-type PCI serial ports. |
| 5 | * |
| 6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. |
| 7 | * |
| 8 | * Copyright (C) 2001 Russell King, All Rights Reserved. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | */ |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/pci.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | #include <linux/string.h> |
| 18 | #include <linux/kernel.h> |
| 19 | #include <linux/slab.h> |
| 20 | #include <linux/delay.h> |
| 21 | #include <linux/tty.h> |
| 22 | #include <linux/serial_core.h> |
| 23 | #include <linux/8250_pci.h> |
| 24 | #include <linux/bitops.h> |
| 25 | |
| 26 | #include <asm/byteorder.h> |
| 27 | #include <asm/io.h> |
| 28 | |
| 29 | #include "8250.h" |
| 30 | |
| 31 | #undef SERIAL_DEBUG_PCI |
| 32 | |
| 33 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | * init function returns: |
| 35 | * > 0 - number of ports |
| 36 | * = 0 - use board->num_ports |
| 37 | * < 0 - error |
| 38 | */ |
| 39 | struct pci_serial_quirk { |
| 40 | u32 vendor; |
| 41 | u32 device; |
| 42 | u32 subvendor; |
| 43 | u32 subdevice; |
| 44 | int (*init)(struct pci_dev *dev); |
Russell King | 975a1a7 | 2009-01-02 13:44:27 +0000 | [diff] [blame] | 45 | int (*setup)(struct serial_private *, |
| 46 | const struct pciserial_board *, |
Russell King | 05caac5 | 2005-07-27 11:41:18 +0100 | [diff] [blame] | 47 | struct uart_port *, int); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 48 | void (*exit)(struct pci_dev *dev); |
| 49 | }; |
| 50 | |
| 51 | #define PCI_NUM_BAR_RESOURCES 6 |
| 52 | |
| 53 | struct serial_private { |
Russell King | 70db3d9 | 2005-07-27 11:34:27 +0100 | [diff] [blame] | 54 | struct pci_dev *dev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | unsigned int nr; |
| 56 | void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES]; |
| 57 | struct pci_serial_quirk *quirk; |
| 58 | int line[0]; |
| 59 | }; |
| 60 | |
| 61 | static void moan_device(const char *str, struct pci_dev *dev) |
| 62 | { |
| 63 | printk(KERN_WARNING "%s: %s\n" |
| 64 | KERN_WARNING "Please send the output of lspci -vv, this\n" |
| 65 | KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" |
| 66 | KERN_WARNING "manufacturer and name of serial board or\n" |
| 67 | KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n", |
| 68 | pci_name(dev), str, dev->vendor, dev->device, |
| 69 | dev->subsystem_vendor, dev->subsystem_device); |
| 70 | } |
| 71 | |
| 72 | static int |
Russell King | 70db3d9 | 2005-07-27 11:34:27 +0100 | [diff] [blame] | 73 | setup_port(struct serial_private *priv, struct uart_port *port, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | int bar, int offset, int regshift) |
| 75 | { |
Russell King | 70db3d9 | 2005-07-27 11:34:27 +0100 | [diff] [blame] | 76 | struct pci_dev *dev = priv->dev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 77 | unsigned long base, len; |
| 78 | |
| 79 | if (bar >= PCI_NUM_BAR_RESOURCES) |
| 80 | return -EINVAL; |
| 81 | |
Russell King | 72ce9a8 | 2005-07-27 11:32:04 +0100 | [diff] [blame] | 82 | base = pci_resource_start(dev, bar); |
| 83 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 84 | if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 85 | len = pci_resource_len(dev, bar); |
| 86 | |
| 87 | if (!priv->remapped_bar[bar]) |
Alan Cox | 6f441fe | 2008-05-01 04:34:59 -0700 | [diff] [blame] | 88 | priv->remapped_bar[bar] = ioremap_nocache(base, len); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 89 | if (!priv->remapped_bar[bar]) |
| 90 | return -ENOMEM; |
| 91 | |
| 92 | port->iotype = UPIO_MEM; |
Russell King | 72ce9a8 | 2005-07-27 11:32:04 +0100 | [diff] [blame] | 93 | port->iobase = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 94 | port->mapbase = base + offset; |
| 95 | port->membase = priv->remapped_bar[bar] + offset; |
| 96 | port->regshift = regshift; |
| 97 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 98 | port->iotype = UPIO_PORT; |
Russell King | 72ce9a8 | 2005-07-27 11:32:04 +0100 | [diff] [blame] | 99 | port->iobase = base + offset; |
| 100 | port->mapbase = 0; |
| 101 | port->membase = NULL; |
| 102 | port->regshift = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | } |
| 104 | return 0; |
| 105 | } |
| 106 | |
| 107 | /* |
Krauth.Julien | 02c9b5c | 2008-02-04 22:27:49 -0800 | [diff] [blame] | 108 | * ADDI-DATA GmbH communication cards <info@addi-data.com> |
| 109 | */ |
| 110 | static int addidata_apci7800_setup(struct serial_private *priv, |
Russell King | 975a1a7 | 2009-01-02 13:44:27 +0000 | [diff] [blame] | 111 | const struct pciserial_board *board, |
Krauth.Julien | 02c9b5c | 2008-02-04 22:27:49 -0800 | [diff] [blame] | 112 | struct uart_port *port, int idx) |
| 113 | { |
| 114 | unsigned int bar = 0, offset = board->first_offset; |
| 115 | bar = FL_GET_BASE(board->flags); |
| 116 | |
| 117 | if (idx < 2) { |
| 118 | offset += idx * board->uart_offset; |
| 119 | } else if ((idx >= 2) && (idx < 4)) { |
| 120 | bar += 1; |
| 121 | offset += ((idx - 2) * board->uart_offset); |
| 122 | } else if ((idx >= 4) && (idx < 6)) { |
| 123 | bar += 2; |
| 124 | offset += ((idx - 4) * board->uart_offset); |
| 125 | } else if (idx >= 6) { |
| 126 | bar += 3; |
| 127 | offset += ((idx - 6) * board->uart_offset); |
| 128 | } |
| 129 | |
| 130 | return setup_port(priv, port, bar, offset, board->reg_shift); |
| 131 | } |
| 132 | |
| 133 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 134 | * AFAVLAB uses a different mixture of BARs and offsets |
| 135 | * Not that ugly ;) -- HW |
| 136 | */ |
| 137 | static int |
Russell King | 975a1a7 | 2009-01-02 13:44:27 +0000 | [diff] [blame] | 138 | afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 139 | struct uart_port *port, int idx) |
| 140 | { |
| 141 | unsigned int bar, offset = board->first_offset; |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 142 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 143 | bar = FL_GET_BASE(board->flags); |
| 144 | if (idx < 4) |
| 145 | bar += idx; |
| 146 | else { |
| 147 | bar = 4; |
| 148 | offset += (idx - 4) * board->uart_offset; |
| 149 | } |
| 150 | |
Russell King | 70db3d9 | 2005-07-27 11:34:27 +0100 | [diff] [blame] | 151 | return setup_port(priv, port, bar, offset, board->reg_shift); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 152 | } |
| 153 | |
| 154 | /* |
| 155 | * HP's Remote Management Console. The Diva chip came in several |
| 156 | * different versions. N-class, L2000 and A500 have two Diva chips, each |
| 157 | * with 3 UARTs (the third UART on the second chip is unused). Superdome |
| 158 | * and Keystone have one Diva chip with 3 UARTs. Some later machines have |
| 159 | * one Diva chip, but it has been expanded to 5 UARTs. |
| 160 | */ |
Russell King | 61a116e | 2006-07-03 15:22:35 +0100 | [diff] [blame] | 161 | static int pci_hp_diva_init(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 162 | { |
| 163 | int rc = 0; |
| 164 | |
| 165 | switch (dev->subsystem_device) { |
| 166 | case PCI_DEVICE_ID_HP_DIVA_TOSCA1: |
| 167 | case PCI_DEVICE_ID_HP_DIVA_HALFDOME: |
| 168 | case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: |
| 169 | case PCI_DEVICE_ID_HP_DIVA_EVEREST: |
| 170 | rc = 3; |
| 171 | break; |
| 172 | case PCI_DEVICE_ID_HP_DIVA_TOSCA2: |
| 173 | rc = 2; |
| 174 | break; |
| 175 | case PCI_DEVICE_ID_HP_DIVA_MAESTRO: |
| 176 | rc = 4; |
| 177 | break; |
| 178 | case PCI_DEVICE_ID_HP_DIVA_POWERBAR: |
Justin Chen | 551f8f0 | 2005-10-24 22:16:38 +0100 | [diff] [blame] | 179 | case PCI_DEVICE_ID_HP_DIVA_HURRICANE: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 180 | rc = 1; |
| 181 | break; |
| 182 | } |
| 183 | |
| 184 | return rc; |
| 185 | } |
| 186 | |
| 187 | /* |
| 188 | * HP's Diva chip puts the 4th/5th serial port further out, and |
| 189 | * some serial ports are supposed to be hidden on certain models. |
| 190 | */ |
| 191 | static int |
Russell King | 975a1a7 | 2009-01-02 13:44:27 +0000 | [diff] [blame] | 192 | pci_hp_diva_setup(struct serial_private *priv, |
| 193 | const struct pciserial_board *board, |
| 194 | struct uart_port *port, int idx) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 195 | { |
| 196 | unsigned int offset = board->first_offset; |
| 197 | unsigned int bar = FL_GET_BASE(board->flags); |
| 198 | |
Russell King | 70db3d9 | 2005-07-27 11:34:27 +0100 | [diff] [blame] | 199 | switch (priv->dev->subsystem_device) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 200 | case PCI_DEVICE_ID_HP_DIVA_MAESTRO: |
| 201 | if (idx == 3) |
| 202 | idx++; |
| 203 | break; |
| 204 | case PCI_DEVICE_ID_HP_DIVA_EVEREST: |
| 205 | if (idx > 0) |
| 206 | idx++; |
| 207 | if (idx > 2) |
| 208 | idx++; |
| 209 | break; |
| 210 | } |
| 211 | if (idx > 2) |
| 212 | offset = 0x18; |
| 213 | |
| 214 | offset += idx * board->uart_offset; |
| 215 | |
Russell King | 70db3d9 | 2005-07-27 11:34:27 +0100 | [diff] [blame] | 216 | return setup_port(priv, port, bar, offset, board->reg_shift); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 217 | } |
| 218 | |
| 219 | /* |
| 220 | * Added for EKF Intel i960 serial boards |
| 221 | */ |
Russell King | 61a116e | 2006-07-03 15:22:35 +0100 | [diff] [blame] | 222 | static int pci_inteli960ni_init(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 223 | { |
| 224 | unsigned long oldval; |
| 225 | |
| 226 | if (!(dev->subsystem_device & 0x1000)) |
| 227 | return -ENODEV; |
| 228 | |
| 229 | /* is firmware started? */ |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 230 | pci_read_config_dword(dev, 0x44, (void *)&oldval); |
| 231 | if (oldval == 0x00001000L) { /* RESET value */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 232 | printk(KERN_DEBUG "Local i960 firmware missing"); |
| 233 | return -ENODEV; |
| 234 | } |
| 235 | return 0; |
| 236 | } |
| 237 | |
| 238 | /* |
| 239 | * Some PCI serial cards using the PLX 9050 PCI interface chip require |
| 240 | * that the card interrupt be explicitly enabled or disabled. This |
| 241 | * seems to be mainly needed on card using the PLX which also use I/O |
| 242 | * mapped memory. |
| 243 | */ |
Russell King | 61a116e | 2006-07-03 15:22:35 +0100 | [diff] [blame] | 244 | static int pci_plx9050_init(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 245 | { |
| 246 | u8 irq_config; |
| 247 | void __iomem *p; |
| 248 | |
| 249 | if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { |
| 250 | moan_device("no memory in bar 0", dev); |
| 251 | return 0; |
| 252 | } |
| 253 | |
| 254 | irq_config = 0x41; |
Bjorn Helgaas | add7b58 | 2005-10-24 22:11:57 +0100 | [diff] [blame] | 255 | if (dev->vendor == PCI_VENDOR_ID_PANACOM || |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 256 | dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 257 | irq_config = 0x43; |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 258 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 259 | if ((dev->vendor == PCI_VENDOR_ID_PLX) && |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 260 | (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 261 | /* |
| 262 | * As the megawolf cards have the int pins active |
| 263 | * high, and have 2 UART chips, both ints must be |
| 264 | * enabled on the 9050. Also, the UARTS are set in |
| 265 | * 16450 mode by default, so we have to enable the |
| 266 | * 16C950 'enhanced' mode so that we can use the |
| 267 | * deep FIFOs |
| 268 | */ |
| 269 | irq_config = 0x5b; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 270 | /* |
| 271 | * enable/disable interrupts |
| 272 | */ |
Alan Cox | 6f441fe | 2008-05-01 04:34:59 -0700 | [diff] [blame] | 273 | p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 274 | if (p == NULL) |
| 275 | return -ENOMEM; |
| 276 | writel(irq_config, p + 0x4c); |
| 277 | |
| 278 | /* |
| 279 | * Read the register back to ensure that it took effect. |
| 280 | */ |
| 281 | readl(p + 0x4c); |
| 282 | iounmap(p); |
| 283 | |
| 284 | return 0; |
| 285 | } |
| 286 | |
| 287 | static void __devexit pci_plx9050_exit(struct pci_dev *dev) |
| 288 | { |
| 289 | u8 __iomem *p; |
| 290 | |
| 291 | if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) |
| 292 | return; |
| 293 | |
| 294 | /* |
| 295 | * disable interrupts |
| 296 | */ |
Alan Cox | 6f441fe | 2008-05-01 04:34:59 -0700 | [diff] [blame] | 297 | p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 298 | if (p != NULL) { |
| 299 | writel(0, p + 0x4c); |
| 300 | |
| 301 | /* |
| 302 | * Read the register back to ensure that it took effect. |
| 303 | */ |
| 304 | readl(p + 0x4c); |
| 305 | iounmap(p); |
| 306 | } |
| 307 | } |
| 308 | |
| 309 | /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ |
| 310 | static int |
Russell King | 975a1a7 | 2009-01-02 13:44:27 +0000 | [diff] [blame] | 311 | sbs_setup(struct serial_private *priv, const struct pciserial_board *board, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 312 | struct uart_port *port, int idx) |
| 313 | { |
| 314 | unsigned int bar, offset = board->first_offset; |
| 315 | |
| 316 | bar = 0; |
| 317 | |
| 318 | if (idx < 4) { |
| 319 | /* first four channels map to 0, 0x100, 0x200, 0x300 */ |
| 320 | offset += idx * board->uart_offset; |
| 321 | } else if (idx < 8) { |
| 322 | /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ |
| 323 | offset += idx * board->uart_offset + 0xC00; |
| 324 | } else /* we have only 8 ports on PMC-OCTALPRO */ |
| 325 | return 1; |
| 326 | |
Russell King | 70db3d9 | 2005-07-27 11:34:27 +0100 | [diff] [blame] | 327 | return setup_port(priv, port, bar, offset, board->reg_shift); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 328 | } |
| 329 | |
| 330 | /* |
| 331 | * This does initialization for PMC OCTALPRO cards: |
| 332 | * maps the device memory, resets the UARTs (needed, bc |
| 333 | * if the module is removed and inserted again, the card |
| 334 | * is in the sleep mode) and enables global interrupt. |
| 335 | */ |
| 336 | |
| 337 | /* global control register offset for SBS PMC-OctalPro */ |
| 338 | #define OCT_REG_CR_OFF 0x500 |
| 339 | |
Russell King | 61a116e | 2006-07-03 15:22:35 +0100 | [diff] [blame] | 340 | static int sbs_init(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 341 | { |
| 342 | u8 __iomem *p; |
| 343 | |
Alan Cox | 6f441fe | 2008-05-01 04:34:59 -0700 | [diff] [blame] | 344 | p = ioremap_nocache(pci_resource_start(dev, 0), |
| 345 | pci_resource_len(dev, 0)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 346 | |
| 347 | if (p == NULL) |
| 348 | return -ENOMEM; |
| 349 | /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 350 | writeb(0x10, p + OCT_REG_CR_OFF); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 351 | udelay(50); |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 352 | writeb(0x0, p + OCT_REG_CR_OFF); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 353 | |
| 354 | /* Set bit-2 (INTENABLE) of Control Register */ |
| 355 | writeb(0x4, p + OCT_REG_CR_OFF); |
| 356 | iounmap(p); |
| 357 | |
| 358 | return 0; |
| 359 | } |
| 360 | |
| 361 | /* |
| 362 | * Disables the global interrupt of PMC-OctalPro |
| 363 | */ |
| 364 | |
| 365 | static void __devexit sbs_exit(struct pci_dev *dev) |
| 366 | { |
| 367 | u8 __iomem *p; |
| 368 | |
Alan Cox | 6f441fe | 2008-05-01 04:34:59 -0700 | [diff] [blame] | 369 | p = ioremap_nocache(pci_resource_start(dev, 0), |
| 370 | pci_resource_len(dev, 0)); |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 371 | /* FIXME: What if resource_len < OCT_REG_CR_OFF */ |
| 372 | if (p != NULL) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 373 | writeb(0, p + OCT_REG_CR_OFF); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 374 | iounmap(p); |
| 375 | } |
| 376 | |
| 377 | /* |
| 378 | * SIIG serial cards have an PCI interface chip which also controls |
| 379 | * the UART clocking frequency. Each UART can be clocked independently |
| 380 | * (except cards equiped with 4 UARTs) and initial clocking settings |
| 381 | * are stored in the EEPROM chip. It can cause problems because this |
| 382 | * version of serial driver doesn't support differently clocked UART's |
| 383 | * on single PCI card. To prevent this, initialization functions set |
| 384 | * high frequency clocking for all UART's on given card. It is safe (I |
| 385 | * hope) because it doesn't touch EEPROM settings to prevent conflicts |
| 386 | * with other OSes (like M$ DOS). |
| 387 | * |
| 388 | * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 389 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 390 | * There is two family of SIIG serial cards with different PCI |
| 391 | * interface chip and different configuration methods: |
| 392 | * - 10x cards have control registers in IO and/or memory space; |
| 393 | * - 20x cards have control registers in standard PCI configuration space. |
| 394 | * |
Russell King | 67d74b8 | 2005-07-27 11:33:03 +0100 | [diff] [blame] | 395 | * Note: all 10x cards have PCI device ids 0x10.. |
| 396 | * all 20x cards have PCI device ids 0x20.. |
| 397 | * |
Andrey Panin | fbc0dc0 | 2005-07-18 11:38:09 +0100 | [diff] [blame] | 398 | * There are also Quartet Serial cards which use Oxford Semiconductor |
| 399 | * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. |
| 400 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 401 | * Note: some SIIG cards are probed by the parport_serial object. |
| 402 | */ |
| 403 | |
| 404 | #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) |
| 405 | #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) |
| 406 | |
| 407 | static int pci_siig10x_init(struct pci_dev *dev) |
| 408 | { |
| 409 | u16 data; |
| 410 | void __iomem *p; |
| 411 | |
| 412 | switch (dev->device & 0xfff8) { |
| 413 | case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ |
| 414 | data = 0xffdf; |
| 415 | break; |
| 416 | case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ |
| 417 | data = 0xf7ff; |
| 418 | break; |
| 419 | default: /* 1S1P, 4S */ |
| 420 | data = 0xfffb; |
| 421 | break; |
| 422 | } |
| 423 | |
Alan Cox | 6f441fe | 2008-05-01 04:34:59 -0700 | [diff] [blame] | 424 | p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 425 | if (p == NULL) |
| 426 | return -ENOMEM; |
| 427 | |
| 428 | writew(readw(p + 0x28) & data, p + 0x28); |
| 429 | readw(p + 0x28); |
| 430 | iounmap(p); |
| 431 | return 0; |
| 432 | } |
| 433 | |
| 434 | #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) |
| 435 | #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) |
| 436 | |
| 437 | static int pci_siig20x_init(struct pci_dev *dev) |
| 438 | { |
| 439 | u8 data; |
| 440 | |
| 441 | /* Change clock frequency for the first UART. */ |
| 442 | pci_read_config_byte(dev, 0x6f, &data); |
| 443 | pci_write_config_byte(dev, 0x6f, data & 0xef); |
| 444 | |
| 445 | /* If this card has 2 UART, we have to do the same with second UART. */ |
| 446 | if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || |
| 447 | ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { |
| 448 | pci_read_config_byte(dev, 0x73, &data); |
| 449 | pci_write_config_byte(dev, 0x73, data & 0xef); |
| 450 | } |
| 451 | return 0; |
| 452 | } |
| 453 | |
Russell King | 67d74b8 | 2005-07-27 11:33:03 +0100 | [diff] [blame] | 454 | static int pci_siig_init(struct pci_dev *dev) |
| 455 | { |
| 456 | unsigned int type = dev->device & 0xff00; |
| 457 | |
| 458 | if (type == 0x1000) |
| 459 | return pci_siig10x_init(dev); |
| 460 | else if (type == 0x2000) |
| 461 | return pci_siig20x_init(dev); |
| 462 | |
| 463 | moan_device("Unknown SIIG card", dev); |
| 464 | return -ENODEV; |
| 465 | } |
| 466 | |
Andrey Panin | 3ec9c59 | 2006-02-02 20:15:09 +0000 | [diff] [blame] | 467 | static int pci_siig_setup(struct serial_private *priv, |
Russell King | 975a1a7 | 2009-01-02 13:44:27 +0000 | [diff] [blame] | 468 | const struct pciserial_board *board, |
Andrey Panin | 3ec9c59 | 2006-02-02 20:15:09 +0000 | [diff] [blame] | 469 | struct uart_port *port, int idx) |
| 470 | { |
| 471 | unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; |
| 472 | |
| 473 | if (idx > 3) { |
| 474 | bar = 4; |
| 475 | offset = (idx - 4) * 8; |
| 476 | } |
| 477 | |
| 478 | return setup_port(priv, port, bar, offset, 0); |
| 479 | } |
| 480 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 481 | /* |
| 482 | * Timedia has an explosion of boards, and to avoid the PCI table from |
| 483 | * growing *huge*, we use this function to collapse some 70 entries |
| 484 | * in the PCI table into one, for sanity's and compactness's sake. |
| 485 | */ |
Helge Deller | e9422e0 | 2006-08-29 21:57:29 +0200 | [diff] [blame] | 486 | static const unsigned short timedia_single_port[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 487 | 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 |
| 488 | }; |
| 489 | |
Helge Deller | e9422e0 | 2006-08-29 21:57:29 +0200 | [diff] [blame] | 490 | static const unsigned short timedia_dual_port[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 491 | 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 492 | 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, |
| 493 | 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 494 | 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, |
| 495 | 0xD079, 0 |
| 496 | }; |
| 497 | |
Helge Deller | e9422e0 | 2006-08-29 21:57:29 +0200 | [diff] [blame] | 498 | static const unsigned short timedia_quad_port[] = { |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 499 | 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, |
| 500 | 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 501 | 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, |
| 502 | 0xB157, 0 |
| 503 | }; |
| 504 | |
Helge Deller | e9422e0 | 2006-08-29 21:57:29 +0200 | [diff] [blame] | 505 | static const unsigned short timedia_eight_port[] = { |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 506 | 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 507 | 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 |
| 508 | }; |
| 509 | |
Arjan van de Ven | cb3592b | 2005-11-28 21:04:11 +0000 | [diff] [blame] | 510 | static const struct timedia_struct { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 511 | int num; |
Helge Deller | e9422e0 | 2006-08-29 21:57:29 +0200 | [diff] [blame] | 512 | const unsigned short *ids; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 513 | } timedia_data[] = { |
| 514 | { 1, timedia_single_port }, |
| 515 | { 2, timedia_dual_port }, |
| 516 | { 4, timedia_quad_port }, |
Helge Deller | e9422e0 | 2006-08-29 21:57:29 +0200 | [diff] [blame] | 517 | { 8, timedia_eight_port } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 518 | }; |
| 519 | |
Russell King | 61a116e | 2006-07-03 15:22:35 +0100 | [diff] [blame] | 520 | static int pci_timedia_init(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 521 | { |
Helge Deller | e9422e0 | 2006-08-29 21:57:29 +0200 | [diff] [blame] | 522 | const unsigned short *ids; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 523 | int i, j; |
| 524 | |
Helge Deller | e9422e0 | 2006-08-29 21:57:29 +0200 | [diff] [blame] | 525 | for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 526 | ids = timedia_data[i].ids; |
| 527 | for (j = 0; ids[j]; j++) |
| 528 | if (dev->subsystem_device == ids[j]) |
| 529 | return timedia_data[i].num; |
| 530 | } |
| 531 | return 0; |
| 532 | } |
| 533 | |
| 534 | /* |
| 535 | * Timedia/SUNIX uses a mixture of BARs and offsets |
| 536 | * Ugh, this is ugly as all hell --- TYT |
| 537 | */ |
| 538 | static int |
Russell King | 975a1a7 | 2009-01-02 13:44:27 +0000 | [diff] [blame] | 539 | pci_timedia_setup(struct serial_private *priv, |
| 540 | const struct pciserial_board *board, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 541 | struct uart_port *port, int idx) |
| 542 | { |
| 543 | unsigned int bar = 0, offset = board->first_offset; |
| 544 | |
| 545 | switch (idx) { |
| 546 | case 0: |
| 547 | bar = 0; |
| 548 | break; |
| 549 | case 1: |
| 550 | offset = board->uart_offset; |
| 551 | bar = 0; |
| 552 | break; |
| 553 | case 2: |
| 554 | bar = 1; |
| 555 | break; |
| 556 | case 3: |
| 557 | offset = board->uart_offset; |
Dave Jones | c2cd6d3 | 2005-12-07 18:11:26 +0000 | [diff] [blame] | 558 | /* FALLTHROUGH */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 559 | case 4: /* BAR 2 */ |
| 560 | case 5: /* BAR 3 */ |
| 561 | case 6: /* BAR 4 */ |
| 562 | case 7: /* BAR 5 */ |
| 563 | bar = idx - 2; |
| 564 | } |
| 565 | |
Russell King | 70db3d9 | 2005-07-27 11:34:27 +0100 | [diff] [blame] | 566 | return setup_port(priv, port, bar, offset, board->reg_shift); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 567 | } |
| 568 | |
| 569 | /* |
| 570 | * Some Titan cards are also a little weird |
| 571 | */ |
| 572 | static int |
Russell King | 70db3d9 | 2005-07-27 11:34:27 +0100 | [diff] [blame] | 573 | titan_400l_800l_setup(struct serial_private *priv, |
Russell King | 975a1a7 | 2009-01-02 13:44:27 +0000 | [diff] [blame] | 574 | const struct pciserial_board *board, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 575 | struct uart_port *port, int idx) |
| 576 | { |
| 577 | unsigned int bar, offset = board->first_offset; |
| 578 | |
| 579 | switch (idx) { |
| 580 | case 0: |
| 581 | bar = 1; |
| 582 | break; |
| 583 | case 1: |
| 584 | bar = 2; |
| 585 | break; |
| 586 | default: |
| 587 | bar = 4; |
| 588 | offset = (idx - 2) * board->uart_offset; |
| 589 | } |
| 590 | |
Russell King | 70db3d9 | 2005-07-27 11:34:27 +0100 | [diff] [blame] | 591 | return setup_port(priv, port, bar, offset, board->reg_shift); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 592 | } |
| 593 | |
Russell King | 61a116e | 2006-07-03 15:22:35 +0100 | [diff] [blame] | 594 | static int pci_xircom_init(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 595 | { |
| 596 | msleep(100); |
| 597 | return 0; |
| 598 | } |
| 599 | |
Russell King | 61a116e | 2006-07-03 15:22:35 +0100 | [diff] [blame] | 600 | static int pci_netmos_init(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 601 | { |
| 602 | /* subdevice 0x00PS means <P> parallel, <S> serial */ |
| 603 | unsigned int num_serial = dev->subsystem_device & 0xf; |
| 604 | |
Jiri Slaby | 25cf9bc | 2009-01-15 13:30:34 +0000 | [diff] [blame^] | 605 | if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && |
| 606 | dev->subsystem_device == 0x0299) |
| 607 | return 0; |
| 608 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 609 | if (num_serial == 0) |
| 610 | return -ENODEV; |
| 611 | return num_serial; |
| 612 | } |
| 613 | |
Niels de Vos | 84f8c6f | 2007-08-22 14:01:14 -0700 | [diff] [blame] | 614 | /* |
| 615 | * ITE support by Niels de Vos <niels.devos@wincor-nixdorf.com> |
| 616 | * |
| 617 | * These chips are available with optionally one parallel port and up to |
| 618 | * two serial ports. Unfortunately they all have the same product id. |
| 619 | * |
| 620 | * Basic configuration is done over a region of 32 I/O ports. The base |
| 621 | * ioport is called INTA or INTC, depending on docs/other drivers. |
| 622 | * |
| 623 | * The region of the 32 I/O ports is configured in POSIO0R... |
| 624 | */ |
| 625 | |
| 626 | /* registers */ |
| 627 | #define ITE_887x_MISCR 0x9c |
| 628 | #define ITE_887x_INTCBAR 0x78 |
| 629 | #define ITE_887x_UARTBAR 0x7c |
| 630 | #define ITE_887x_PS0BAR 0x10 |
| 631 | #define ITE_887x_POSIO0 0x60 |
| 632 | |
| 633 | /* I/O space size */ |
| 634 | #define ITE_887x_IOSIZE 32 |
| 635 | /* I/O space size (bits 26-24; 8 bytes = 011b) */ |
| 636 | #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) |
| 637 | /* I/O space size (bits 26-24; 32 bytes = 101b) */ |
| 638 | #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) |
| 639 | /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ |
| 640 | #define ITE_887x_POSIO_SPEED (3 << 29) |
| 641 | /* enable IO_Space bit */ |
| 642 | #define ITE_887x_POSIO_ENABLE (1 << 31) |
| 643 | |
Ralf Baechle | f79abb8 | 2007-08-30 23:56:31 -0700 | [diff] [blame] | 644 | static int pci_ite887x_init(struct pci_dev *dev) |
Niels de Vos | 84f8c6f | 2007-08-22 14:01:14 -0700 | [diff] [blame] | 645 | { |
| 646 | /* inta_addr are the configuration addresses of the ITE */ |
| 647 | static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, |
| 648 | 0x200, 0x280, 0 }; |
| 649 | int ret, i, type; |
| 650 | struct resource *iobase = NULL; |
| 651 | u32 miscr, uartbar, ioport; |
| 652 | |
| 653 | /* search for the base-ioport */ |
| 654 | i = 0; |
| 655 | while (inta_addr[i] && iobase == NULL) { |
| 656 | iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, |
| 657 | "ite887x"); |
| 658 | if (iobase != NULL) { |
| 659 | /* write POSIO0R - speed | size | ioport */ |
| 660 | pci_write_config_dword(dev, ITE_887x_POSIO0, |
| 661 | ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | |
| 662 | ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); |
| 663 | /* write INTCBAR - ioport */ |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 664 | pci_write_config_dword(dev, ITE_887x_INTCBAR, |
| 665 | inta_addr[i]); |
Niels de Vos | 84f8c6f | 2007-08-22 14:01:14 -0700 | [diff] [blame] | 666 | ret = inb(inta_addr[i]); |
| 667 | if (ret != 0xff) { |
| 668 | /* ioport connected */ |
| 669 | break; |
| 670 | } |
| 671 | release_region(iobase->start, ITE_887x_IOSIZE); |
| 672 | iobase = NULL; |
| 673 | } |
| 674 | i++; |
| 675 | } |
| 676 | |
| 677 | if (!inta_addr[i]) { |
| 678 | printk(KERN_ERR "ite887x: could not find iobase\n"); |
| 679 | return -ENODEV; |
| 680 | } |
| 681 | |
| 682 | /* start of undocumented type checking (see parport_pc.c) */ |
| 683 | type = inb(iobase->start + 0x18) & 0x0f; |
| 684 | |
| 685 | switch (type) { |
| 686 | case 0x2: /* ITE8871 (1P) */ |
| 687 | case 0xa: /* ITE8875 (1P) */ |
| 688 | ret = 0; |
| 689 | break; |
| 690 | case 0xe: /* ITE8872 (2S1P) */ |
| 691 | ret = 2; |
| 692 | break; |
| 693 | case 0x6: /* ITE8873 (1S) */ |
| 694 | ret = 1; |
| 695 | break; |
| 696 | case 0x8: /* ITE8874 (2S) */ |
| 697 | ret = 2; |
| 698 | break; |
| 699 | default: |
| 700 | moan_device("Unknown ITE887x", dev); |
| 701 | ret = -ENODEV; |
| 702 | } |
| 703 | |
| 704 | /* configure all serial ports */ |
| 705 | for (i = 0; i < ret; i++) { |
| 706 | /* read the I/O port from the device */ |
| 707 | pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), |
| 708 | &ioport); |
| 709 | ioport &= 0x0000FF00; /* the actual base address */ |
| 710 | pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), |
| 711 | ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | |
| 712 | ITE_887x_POSIO_IOSIZE_8 | ioport); |
| 713 | |
| 714 | /* write the ioport to the UARTBAR */ |
| 715 | pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); |
| 716 | uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ |
| 717 | uartbar |= (ioport << (16 * i)); /* set the ioport */ |
| 718 | pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); |
| 719 | |
| 720 | /* get current config */ |
| 721 | pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); |
| 722 | /* disable interrupts (UARTx_Routing[3:0]) */ |
| 723 | miscr &= ~(0xf << (12 - 4 * i)); |
| 724 | /* activate the UART (UARTx_En) */ |
| 725 | miscr |= 1 << (23 - i); |
| 726 | /* write new config with activated UART */ |
| 727 | pci_write_config_dword(dev, ITE_887x_MISCR, miscr); |
| 728 | } |
| 729 | |
| 730 | if (ret <= 0) { |
| 731 | /* the device has no UARTs if we get here */ |
| 732 | release_region(iobase->start, ITE_887x_IOSIZE); |
| 733 | } |
| 734 | |
| 735 | return ret; |
| 736 | } |
| 737 | |
| 738 | static void __devexit pci_ite887x_exit(struct pci_dev *dev) |
| 739 | { |
| 740 | u32 ioport; |
| 741 | /* the ioport is bit 0-15 in POSIO0R */ |
| 742 | pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); |
| 743 | ioport &= 0xffff; |
| 744 | release_region(ioport, ITE_887x_IOSIZE); |
| 745 | } |
| 746 | |
Russell King | 9f2a036 | 2009-01-02 13:44:20 +0000 | [diff] [blame] | 747 | /* |
| 748 | * Oxford Semiconductor Inc. |
| 749 | * Check that device is part of the Tornado range of devices, then determine |
| 750 | * the number of ports available on the device. |
| 751 | */ |
| 752 | static int pci_oxsemi_tornado_init(struct pci_dev *dev) |
| 753 | { |
| 754 | u8 __iomem *p; |
| 755 | unsigned long deviceID; |
| 756 | unsigned int number_uarts = 0; |
| 757 | |
| 758 | /* OxSemi Tornado devices are all 0xCxxx */ |
| 759 | if (dev->vendor == PCI_VENDOR_ID_OXSEMI && |
| 760 | (dev->device & 0xF000) != 0xC000) |
| 761 | return 0; |
| 762 | |
| 763 | p = pci_iomap(dev, 0, 5); |
| 764 | if (p == NULL) |
| 765 | return -ENOMEM; |
| 766 | |
| 767 | deviceID = ioread32(p); |
| 768 | /* Tornado device */ |
| 769 | if (deviceID == 0x07000200) { |
| 770 | number_uarts = ioread8(p + 4); |
| 771 | printk(KERN_DEBUG |
| 772 | "%d ports detected on Oxford PCI Express device\n", |
| 773 | number_uarts); |
| 774 | } |
| 775 | pci_iounmap(dev, p); |
| 776 | return number_uarts; |
| 777 | } |
| 778 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 779 | static int |
Russell King | 975a1a7 | 2009-01-02 13:44:27 +0000 | [diff] [blame] | 780 | pci_default_setup(struct serial_private *priv, |
| 781 | const struct pciserial_board *board, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 782 | struct uart_port *port, int idx) |
| 783 | { |
| 784 | unsigned int bar, offset = board->first_offset, maxnr; |
| 785 | |
| 786 | bar = FL_GET_BASE(board->flags); |
| 787 | if (board->flags & FL_BASE_BARS) |
| 788 | bar += idx; |
| 789 | else |
| 790 | offset += idx * board->uart_offset; |
| 791 | |
Greg Kroah-Hartman | 2427ddd | 2006-06-12 17:07:52 -0700 | [diff] [blame] | 792 | maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> |
| 793 | (board->reg_shift + 3); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 794 | |
| 795 | if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) |
| 796 | return 1; |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 797 | |
Russell King | 70db3d9 | 2005-07-27 11:34:27 +0100 | [diff] [blame] | 798 | return setup_port(priv, port, bar, offset, board->reg_shift); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 799 | } |
| 800 | |
| 801 | /* This should be in linux/pci_ids.h */ |
| 802 | #define PCI_VENDOR_ID_SBSMODULARIO 0x124B |
| 803 | #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B |
| 804 | #define PCI_DEVICE_ID_OCTPRO 0x0001 |
| 805 | #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 |
| 806 | #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 |
| 807 | #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 |
| 808 | #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 |
| 809 | |
Catalin(ux) M BOIE | b76c5a0 | 2008-07-23 21:29:46 -0700 | [diff] [blame] | 810 | /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ |
| 811 | #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 |
| 812 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 813 | /* |
| 814 | * Master list of serial port init/setup/exit quirks. |
| 815 | * This does not describe the general nature of the port. |
| 816 | * (ie, baud base, number and location of ports, etc) |
| 817 | * |
| 818 | * This list is ordered alphabetically by vendor then device. |
| 819 | * Specific entries must come before more generic entries. |
| 820 | */ |
Sam Ravnborg | 7a63ce5 | 2008-04-28 02:14:02 -0700 | [diff] [blame] | 821 | static struct pci_serial_quirk pci_serial_quirks[] __refdata = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 822 | /* |
Krauth.Julien | 02c9b5c | 2008-02-04 22:27:49 -0800 | [diff] [blame] | 823 | * ADDI-DATA GmbH communication cards <info@addi-data.com> |
| 824 | */ |
| 825 | { |
| 826 | .vendor = PCI_VENDOR_ID_ADDIDATA_OLD, |
| 827 | .device = PCI_DEVICE_ID_ADDIDATA_APCI7800, |
| 828 | .subvendor = PCI_ANY_ID, |
| 829 | .subdevice = PCI_ANY_ID, |
| 830 | .setup = addidata_apci7800_setup, |
| 831 | }, |
| 832 | /* |
Russell King | 61a116e | 2006-07-03 15:22:35 +0100 | [diff] [blame] | 833 | * AFAVLAB cards - these may be called via parport_serial |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 834 | * It is not clear whether this applies to all products. |
| 835 | */ |
| 836 | { |
| 837 | .vendor = PCI_VENDOR_ID_AFAVLAB, |
| 838 | .device = PCI_ANY_ID, |
| 839 | .subvendor = PCI_ANY_ID, |
| 840 | .subdevice = PCI_ANY_ID, |
| 841 | .setup = afavlab_setup, |
| 842 | }, |
| 843 | /* |
| 844 | * HP Diva |
| 845 | */ |
| 846 | { |
| 847 | .vendor = PCI_VENDOR_ID_HP, |
| 848 | .device = PCI_DEVICE_ID_HP_DIVA, |
| 849 | .subvendor = PCI_ANY_ID, |
| 850 | .subdevice = PCI_ANY_ID, |
| 851 | .init = pci_hp_diva_init, |
| 852 | .setup = pci_hp_diva_setup, |
| 853 | }, |
| 854 | /* |
| 855 | * Intel |
| 856 | */ |
| 857 | { |
| 858 | .vendor = PCI_VENDOR_ID_INTEL, |
| 859 | .device = PCI_DEVICE_ID_INTEL_80960_RP, |
| 860 | .subvendor = 0xe4bf, |
| 861 | .subdevice = PCI_ANY_ID, |
| 862 | .init = pci_inteli960ni_init, |
| 863 | .setup = pci_default_setup, |
| 864 | }, |
| 865 | /* |
Niels de Vos | 84f8c6f | 2007-08-22 14:01:14 -0700 | [diff] [blame] | 866 | * ITE |
| 867 | */ |
| 868 | { |
| 869 | .vendor = PCI_VENDOR_ID_ITE, |
| 870 | .device = PCI_DEVICE_ID_ITE_8872, |
| 871 | .subvendor = PCI_ANY_ID, |
| 872 | .subdevice = PCI_ANY_ID, |
| 873 | .init = pci_ite887x_init, |
| 874 | .setup = pci_default_setup, |
| 875 | .exit = __devexit_p(pci_ite887x_exit), |
| 876 | }, |
| 877 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 878 | * Panacom |
| 879 | */ |
| 880 | { |
| 881 | .vendor = PCI_VENDOR_ID_PANACOM, |
| 882 | .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, |
| 883 | .subvendor = PCI_ANY_ID, |
| 884 | .subdevice = PCI_ANY_ID, |
| 885 | .init = pci_plx9050_init, |
| 886 | .setup = pci_default_setup, |
| 887 | .exit = __devexit_p(pci_plx9050_exit), |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 888 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 889 | { |
| 890 | .vendor = PCI_VENDOR_ID_PANACOM, |
| 891 | .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, |
| 892 | .subvendor = PCI_ANY_ID, |
| 893 | .subdevice = PCI_ANY_ID, |
| 894 | .init = pci_plx9050_init, |
| 895 | .setup = pci_default_setup, |
| 896 | .exit = __devexit_p(pci_plx9050_exit), |
| 897 | }, |
| 898 | /* |
| 899 | * PLX |
| 900 | */ |
| 901 | { |
| 902 | .vendor = PCI_VENDOR_ID_PLX, |
Thomas Hoehn | 4821200 | 2007-02-10 01:46:05 -0800 | [diff] [blame] | 903 | .device = PCI_DEVICE_ID_PLX_9030, |
| 904 | .subvendor = PCI_SUBVENDOR_ID_PERLE, |
| 905 | .subdevice = PCI_ANY_ID, |
| 906 | .setup = pci_default_setup, |
| 907 | }, |
| 908 | { |
| 909 | .vendor = PCI_VENDOR_ID_PLX, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 910 | .device = PCI_DEVICE_ID_PLX_9050, |
Bjorn Helgaas | add7b58 | 2005-10-24 22:11:57 +0100 | [diff] [blame] | 911 | .subvendor = PCI_SUBVENDOR_ID_EXSYS, |
| 912 | .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, |
| 913 | .init = pci_plx9050_init, |
| 914 | .setup = pci_default_setup, |
| 915 | .exit = __devexit_p(pci_plx9050_exit), |
| 916 | }, |
| 917 | { |
| 918 | .vendor = PCI_VENDOR_ID_PLX, |
| 919 | .device = PCI_DEVICE_ID_PLX_9050, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 920 | .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, |
| 921 | .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, |
| 922 | .init = pci_plx9050_init, |
| 923 | .setup = pci_default_setup, |
| 924 | .exit = __devexit_p(pci_plx9050_exit), |
| 925 | }, |
| 926 | { |
| 927 | .vendor = PCI_VENDOR_ID_PLX, |
Catalin(ux) M BOIE | b76c5a0 | 2008-07-23 21:29:46 -0700 | [diff] [blame] | 928 | .device = PCI_DEVICE_ID_PLX_9050, |
| 929 | .subvendor = PCI_VENDOR_ID_PLX, |
| 930 | .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584, |
| 931 | .init = pci_plx9050_init, |
| 932 | .setup = pci_default_setup, |
| 933 | .exit = __devexit_p(pci_plx9050_exit), |
| 934 | }, |
| 935 | { |
| 936 | .vendor = PCI_VENDOR_ID_PLX, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 937 | .device = PCI_DEVICE_ID_PLX_ROMULUS, |
| 938 | .subvendor = PCI_VENDOR_ID_PLX, |
| 939 | .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, |
| 940 | .init = pci_plx9050_init, |
| 941 | .setup = pci_default_setup, |
| 942 | .exit = __devexit_p(pci_plx9050_exit), |
| 943 | }, |
| 944 | /* |
| 945 | * SBS Technologies, Inc., PMC-OCTALPRO 232 |
| 946 | */ |
| 947 | { |
| 948 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, |
| 949 | .device = PCI_DEVICE_ID_OCTPRO, |
| 950 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, |
| 951 | .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, |
| 952 | .init = sbs_init, |
| 953 | .setup = sbs_setup, |
| 954 | .exit = __devexit_p(sbs_exit), |
| 955 | }, |
| 956 | /* |
| 957 | * SBS Technologies, Inc., PMC-OCTALPRO 422 |
| 958 | */ |
| 959 | { |
| 960 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, |
| 961 | .device = PCI_DEVICE_ID_OCTPRO, |
| 962 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, |
| 963 | .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, |
| 964 | .init = sbs_init, |
| 965 | .setup = sbs_setup, |
| 966 | .exit = __devexit_p(sbs_exit), |
| 967 | }, |
| 968 | /* |
| 969 | * SBS Technologies, Inc., P-Octal 232 |
| 970 | */ |
| 971 | { |
| 972 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, |
| 973 | .device = PCI_DEVICE_ID_OCTPRO, |
| 974 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, |
| 975 | .subdevice = PCI_SUBDEVICE_ID_POCTAL232, |
| 976 | .init = sbs_init, |
| 977 | .setup = sbs_setup, |
| 978 | .exit = __devexit_p(sbs_exit), |
| 979 | }, |
| 980 | /* |
| 981 | * SBS Technologies, Inc., P-Octal 422 |
| 982 | */ |
| 983 | { |
| 984 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, |
| 985 | .device = PCI_DEVICE_ID_OCTPRO, |
| 986 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, |
| 987 | .subdevice = PCI_SUBDEVICE_ID_POCTAL422, |
| 988 | .init = sbs_init, |
| 989 | .setup = sbs_setup, |
| 990 | .exit = __devexit_p(sbs_exit), |
| 991 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 992 | /* |
Russell King | 61a116e | 2006-07-03 15:22:35 +0100 | [diff] [blame] | 993 | * SIIG cards - these may be called via parport_serial |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 994 | */ |
| 995 | { |
| 996 | .vendor = PCI_VENDOR_ID_SIIG, |
Russell King | 67d74b8 | 2005-07-27 11:33:03 +0100 | [diff] [blame] | 997 | .device = PCI_ANY_ID, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 998 | .subvendor = PCI_ANY_ID, |
| 999 | .subdevice = PCI_ANY_ID, |
Russell King | 67d74b8 | 2005-07-27 11:33:03 +0100 | [diff] [blame] | 1000 | .init = pci_siig_init, |
Andrey Panin | 3ec9c59 | 2006-02-02 20:15:09 +0000 | [diff] [blame] | 1001 | .setup = pci_siig_setup, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1002 | }, |
| 1003 | /* |
| 1004 | * Titan cards |
| 1005 | */ |
| 1006 | { |
| 1007 | .vendor = PCI_VENDOR_ID_TITAN, |
| 1008 | .device = PCI_DEVICE_ID_TITAN_400L, |
| 1009 | .subvendor = PCI_ANY_ID, |
| 1010 | .subdevice = PCI_ANY_ID, |
| 1011 | .setup = titan_400l_800l_setup, |
| 1012 | }, |
| 1013 | { |
| 1014 | .vendor = PCI_VENDOR_ID_TITAN, |
| 1015 | .device = PCI_DEVICE_ID_TITAN_800L, |
| 1016 | .subvendor = PCI_ANY_ID, |
| 1017 | .subdevice = PCI_ANY_ID, |
| 1018 | .setup = titan_400l_800l_setup, |
| 1019 | }, |
| 1020 | /* |
| 1021 | * Timedia cards |
| 1022 | */ |
| 1023 | { |
| 1024 | .vendor = PCI_VENDOR_ID_TIMEDIA, |
| 1025 | .device = PCI_DEVICE_ID_TIMEDIA_1889, |
| 1026 | .subvendor = PCI_VENDOR_ID_TIMEDIA, |
| 1027 | .subdevice = PCI_ANY_ID, |
| 1028 | .init = pci_timedia_init, |
| 1029 | .setup = pci_timedia_setup, |
| 1030 | }, |
| 1031 | { |
| 1032 | .vendor = PCI_VENDOR_ID_TIMEDIA, |
| 1033 | .device = PCI_ANY_ID, |
| 1034 | .subvendor = PCI_ANY_ID, |
| 1035 | .subdevice = PCI_ANY_ID, |
| 1036 | .setup = pci_timedia_setup, |
| 1037 | }, |
| 1038 | /* |
| 1039 | * Xircom cards |
| 1040 | */ |
| 1041 | { |
| 1042 | .vendor = PCI_VENDOR_ID_XIRCOM, |
| 1043 | .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, |
| 1044 | .subvendor = PCI_ANY_ID, |
| 1045 | .subdevice = PCI_ANY_ID, |
| 1046 | .init = pci_xircom_init, |
| 1047 | .setup = pci_default_setup, |
| 1048 | }, |
| 1049 | /* |
Russell King | 61a116e | 2006-07-03 15:22:35 +0100 | [diff] [blame] | 1050 | * Netmos cards - these may be called via parport_serial |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1051 | */ |
| 1052 | { |
| 1053 | .vendor = PCI_VENDOR_ID_NETMOS, |
| 1054 | .device = PCI_ANY_ID, |
| 1055 | .subvendor = PCI_ANY_ID, |
| 1056 | .subdevice = PCI_ANY_ID, |
| 1057 | .init = pci_netmos_init, |
| 1058 | .setup = pci_default_setup, |
| 1059 | }, |
| 1060 | /* |
Russell King | 9f2a036 | 2009-01-02 13:44:20 +0000 | [diff] [blame] | 1061 | * For Oxford Semiconductor and Mainpine |
| 1062 | */ |
| 1063 | { |
| 1064 | .vendor = PCI_VENDOR_ID_OXSEMI, |
| 1065 | .device = PCI_ANY_ID, |
| 1066 | .subvendor = PCI_ANY_ID, |
| 1067 | .subdevice = PCI_ANY_ID, |
| 1068 | .init = pci_oxsemi_tornado_init, |
| 1069 | .setup = pci_default_setup, |
| 1070 | }, |
| 1071 | { |
| 1072 | .vendor = PCI_VENDOR_ID_MAINPINE, |
| 1073 | .device = PCI_ANY_ID, |
| 1074 | .subvendor = PCI_ANY_ID, |
| 1075 | .subdevice = PCI_ANY_ID, |
| 1076 | .init = pci_oxsemi_tornado_init, |
| 1077 | .setup = pci_default_setup, |
| 1078 | }, |
| 1079 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1080 | * Default "match everything" terminator entry |
| 1081 | */ |
| 1082 | { |
| 1083 | .vendor = PCI_ANY_ID, |
| 1084 | .device = PCI_ANY_ID, |
| 1085 | .subvendor = PCI_ANY_ID, |
| 1086 | .subdevice = PCI_ANY_ID, |
| 1087 | .setup = pci_default_setup, |
| 1088 | } |
| 1089 | }; |
| 1090 | |
| 1091 | static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) |
| 1092 | { |
| 1093 | return quirk_id == PCI_ANY_ID || quirk_id == dev_id; |
| 1094 | } |
| 1095 | |
| 1096 | static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) |
| 1097 | { |
| 1098 | struct pci_serial_quirk *quirk; |
| 1099 | |
| 1100 | for (quirk = pci_serial_quirks; ; quirk++) |
| 1101 | if (quirk_id_matches(quirk->vendor, dev->vendor) && |
| 1102 | quirk_id_matches(quirk->device, dev->device) && |
| 1103 | quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && |
| 1104 | quirk_id_matches(quirk->subdevice, dev->subsystem_device)) |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 1105 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1106 | return quirk; |
| 1107 | } |
| 1108 | |
Andrew Morton | dd68e88 | 2006-01-05 10:55:26 +0000 | [diff] [blame] | 1109 | static inline int get_pci_irq(struct pci_dev *dev, |
Russell King | 975a1a7 | 2009-01-02 13:44:27 +0000 | [diff] [blame] | 1110 | const struct pciserial_board *board) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1111 | { |
| 1112 | if (board->flags & FL_NOIRQ) |
| 1113 | return 0; |
| 1114 | else |
| 1115 | return dev->irq; |
| 1116 | } |
| 1117 | |
| 1118 | /* |
| 1119 | * This is the configuration table for all of the PCI serial boards |
| 1120 | * which we support. It is directly indexed by the pci_board_num_t enum |
| 1121 | * value, which is encoded in the pci_device_id PCI probe table's |
| 1122 | * driver_data member. |
| 1123 | * |
| 1124 | * The makeup of these names are: |
Gareth Howlett | 26e9286 | 2006-01-04 17:00:42 +0000 | [diff] [blame] | 1125 | * pbn_bn{_bt}_n_baud{_offsetinhex} |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1126 | * |
Gareth Howlett | 26e9286 | 2006-01-04 17:00:42 +0000 | [diff] [blame] | 1127 | * bn = PCI BAR number |
| 1128 | * bt = Index using PCI BARs |
| 1129 | * n = number of serial ports |
| 1130 | * baud = baud rate |
| 1131 | * offsetinhex = offset for each sequential port (in hex) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1132 | * |
Gareth Howlett | 26e9286 | 2006-01-04 17:00:42 +0000 | [diff] [blame] | 1133 | * This table is sorted by (in order): bn, bt, baud, offsetindex, n. |
Russell King | f1690f3 | 2005-05-06 10:19:09 +0100 | [diff] [blame] | 1134 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1135 | * Please note: in theory if n = 1, _bt infix should make no difference. |
| 1136 | * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 |
| 1137 | */ |
| 1138 | enum pci_board_num_t { |
| 1139 | pbn_default = 0, |
| 1140 | |
| 1141 | pbn_b0_1_115200, |
| 1142 | pbn_b0_2_115200, |
| 1143 | pbn_b0_4_115200, |
| 1144 | pbn_b0_5_115200, |
Alan Cox | bf0df63 | 2007-10-16 01:24:00 -0700 | [diff] [blame] | 1145 | pbn_b0_8_115200, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1146 | |
| 1147 | pbn_b0_1_921600, |
| 1148 | pbn_b0_2_921600, |
| 1149 | pbn_b0_4_921600, |
| 1150 | |
David Ranson | db1de15 | 2005-07-27 11:43:55 -0700 | [diff] [blame] | 1151 | pbn_b0_2_1130000, |
| 1152 | |
Andrey Panin | fbc0dc0 | 2005-07-18 11:38:09 +0100 | [diff] [blame] | 1153 | pbn_b0_4_1152000, |
| 1154 | |
Gareth Howlett | 26e9286 | 2006-01-04 17:00:42 +0000 | [diff] [blame] | 1155 | pbn_b0_2_1843200, |
| 1156 | pbn_b0_4_1843200, |
| 1157 | |
| 1158 | pbn_b0_2_1843200_200, |
| 1159 | pbn_b0_4_1843200_200, |
| 1160 | pbn_b0_8_1843200_200, |
| 1161 | |
Lee Howard | 7106b4e | 2008-10-21 13:48:58 +0100 | [diff] [blame] | 1162 | pbn_b0_1_4000000, |
| 1163 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1164 | pbn_b0_bt_1_115200, |
| 1165 | pbn_b0_bt_2_115200, |
| 1166 | pbn_b0_bt_8_115200, |
| 1167 | |
| 1168 | pbn_b0_bt_1_460800, |
| 1169 | pbn_b0_bt_2_460800, |
| 1170 | pbn_b0_bt_4_460800, |
| 1171 | |
| 1172 | pbn_b0_bt_1_921600, |
| 1173 | pbn_b0_bt_2_921600, |
| 1174 | pbn_b0_bt_4_921600, |
| 1175 | pbn_b0_bt_8_921600, |
| 1176 | |
| 1177 | pbn_b1_1_115200, |
| 1178 | pbn_b1_2_115200, |
| 1179 | pbn_b1_4_115200, |
| 1180 | pbn_b1_8_115200, |
| 1181 | |
| 1182 | pbn_b1_1_921600, |
| 1183 | pbn_b1_2_921600, |
| 1184 | pbn_b1_4_921600, |
| 1185 | pbn_b1_8_921600, |
| 1186 | |
Gareth Howlett | 26e9286 | 2006-01-04 17:00:42 +0000 | [diff] [blame] | 1187 | pbn_b1_2_1250000, |
| 1188 | |
Niels de Vos | 84f8c6f | 2007-08-22 14:01:14 -0700 | [diff] [blame] | 1189 | pbn_b1_bt_1_115200, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1190 | pbn_b1_bt_2_921600, |
| 1191 | |
| 1192 | pbn_b1_1_1382400, |
| 1193 | pbn_b1_2_1382400, |
| 1194 | pbn_b1_4_1382400, |
| 1195 | pbn_b1_8_1382400, |
| 1196 | |
| 1197 | pbn_b2_1_115200, |
Peter Horton | 737c175 | 2006-08-26 09:07:36 +0100 | [diff] [blame] | 1198 | pbn_b2_2_115200, |
Matthias Fuchs | a9cccd3 | 2007-02-10 01:46:05 -0800 | [diff] [blame] | 1199 | pbn_b2_4_115200, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1200 | pbn_b2_8_115200, |
| 1201 | |
| 1202 | pbn_b2_1_460800, |
| 1203 | pbn_b2_4_460800, |
| 1204 | pbn_b2_8_460800, |
| 1205 | pbn_b2_16_460800, |
| 1206 | |
| 1207 | pbn_b2_1_921600, |
| 1208 | pbn_b2_4_921600, |
| 1209 | pbn_b2_8_921600, |
| 1210 | |
| 1211 | pbn_b2_bt_1_115200, |
| 1212 | pbn_b2_bt_2_115200, |
| 1213 | pbn_b2_bt_4_115200, |
| 1214 | |
| 1215 | pbn_b2_bt_2_921600, |
| 1216 | pbn_b2_bt_4_921600, |
| 1217 | |
Alon Bar-Lev | d9004eb | 2006-01-18 11:47:33 +0000 | [diff] [blame] | 1218 | pbn_b3_2_115200, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1219 | pbn_b3_4_115200, |
| 1220 | pbn_b3_8_115200, |
| 1221 | |
| 1222 | /* |
| 1223 | * Board-specific versions. |
| 1224 | */ |
| 1225 | pbn_panacom, |
| 1226 | pbn_panacom2, |
| 1227 | pbn_panacom4, |
Bjorn Helgaas | add7b58 | 2005-10-24 22:11:57 +0100 | [diff] [blame] | 1228 | pbn_exsys_4055, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1229 | pbn_plx_romulus, |
| 1230 | pbn_oxsemi, |
Lee Howard | 7106b4e | 2008-10-21 13:48:58 +0100 | [diff] [blame] | 1231 | pbn_oxsemi_1_4000000, |
| 1232 | pbn_oxsemi_2_4000000, |
| 1233 | pbn_oxsemi_4_4000000, |
| 1234 | pbn_oxsemi_8_4000000, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1235 | pbn_intel_i960, |
| 1236 | pbn_sgi_ioc3, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1237 | pbn_computone_4, |
| 1238 | pbn_computone_6, |
| 1239 | pbn_computone_8, |
| 1240 | pbn_sbsxrsio, |
| 1241 | pbn_exar_XR17C152, |
| 1242 | pbn_exar_XR17C154, |
| 1243 | pbn_exar_XR17C158, |
Olof Johansson | aa79850 | 2007-08-22 14:01:55 -0700 | [diff] [blame] | 1244 | pbn_pasemi_1682M, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1245 | }; |
| 1246 | |
| 1247 | /* |
| 1248 | * uart_offset - the space between channels |
| 1249 | * reg_shift - describes how the UART registers are mapped |
| 1250 | * to PCI memory by the card. |
| 1251 | * For example IER register on SBS, Inc. PMC-OctPro is located at |
| 1252 | * offset 0x10 from the UART base, while UART_IER is defined as 1 |
| 1253 | * in include/linux/serial_reg.h, |
| 1254 | * see first lines of serial_in() and serial_out() in 8250.c |
| 1255 | */ |
| 1256 | |
Russell King | 1c7c1fe | 2005-07-27 11:31:19 +0100 | [diff] [blame] | 1257 | static struct pciserial_board pci_boards[] __devinitdata = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1258 | [pbn_default] = { |
| 1259 | .flags = FL_BASE0, |
| 1260 | .num_ports = 1, |
| 1261 | .base_baud = 115200, |
| 1262 | .uart_offset = 8, |
| 1263 | }, |
| 1264 | [pbn_b0_1_115200] = { |
| 1265 | .flags = FL_BASE0, |
| 1266 | .num_ports = 1, |
| 1267 | .base_baud = 115200, |
| 1268 | .uart_offset = 8, |
| 1269 | }, |
| 1270 | [pbn_b0_2_115200] = { |
| 1271 | .flags = FL_BASE0, |
| 1272 | .num_ports = 2, |
| 1273 | .base_baud = 115200, |
| 1274 | .uart_offset = 8, |
| 1275 | }, |
| 1276 | [pbn_b0_4_115200] = { |
| 1277 | .flags = FL_BASE0, |
| 1278 | .num_ports = 4, |
| 1279 | .base_baud = 115200, |
| 1280 | .uart_offset = 8, |
| 1281 | }, |
| 1282 | [pbn_b0_5_115200] = { |
| 1283 | .flags = FL_BASE0, |
| 1284 | .num_ports = 5, |
| 1285 | .base_baud = 115200, |
| 1286 | .uart_offset = 8, |
| 1287 | }, |
Alan Cox | bf0df63 | 2007-10-16 01:24:00 -0700 | [diff] [blame] | 1288 | [pbn_b0_8_115200] = { |
| 1289 | .flags = FL_BASE0, |
| 1290 | .num_ports = 8, |
| 1291 | .base_baud = 115200, |
| 1292 | .uart_offset = 8, |
| 1293 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1294 | [pbn_b0_1_921600] = { |
| 1295 | .flags = FL_BASE0, |
| 1296 | .num_ports = 1, |
| 1297 | .base_baud = 921600, |
| 1298 | .uart_offset = 8, |
| 1299 | }, |
| 1300 | [pbn_b0_2_921600] = { |
| 1301 | .flags = FL_BASE0, |
| 1302 | .num_ports = 2, |
| 1303 | .base_baud = 921600, |
| 1304 | .uart_offset = 8, |
| 1305 | }, |
| 1306 | [pbn_b0_4_921600] = { |
| 1307 | .flags = FL_BASE0, |
| 1308 | .num_ports = 4, |
| 1309 | .base_baud = 921600, |
| 1310 | .uart_offset = 8, |
| 1311 | }, |
David Ranson | db1de15 | 2005-07-27 11:43:55 -0700 | [diff] [blame] | 1312 | |
| 1313 | [pbn_b0_2_1130000] = { |
| 1314 | .flags = FL_BASE0, |
| 1315 | .num_ports = 2, |
| 1316 | .base_baud = 1130000, |
| 1317 | .uart_offset = 8, |
| 1318 | }, |
| 1319 | |
Andrey Panin | fbc0dc0 | 2005-07-18 11:38:09 +0100 | [diff] [blame] | 1320 | [pbn_b0_4_1152000] = { |
| 1321 | .flags = FL_BASE0, |
| 1322 | .num_ports = 4, |
| 1323 | .base_baud = 1152000, |
| 1324 | .uart_offset = 8, |
| 1325 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1326 | |
Gareth Howlett | 26e9286 | 2006-01-04 17:00:42 +0000 | [diff] [blame] | 1327 | [pbn_b0_2_1843200] = { |
| 1328 | .flags = FL_BASE0, |
| 1329 | .num_ports = 2, |
| 1330 | .base_baud = 1843200, |
| 1331 | .uart_offset = 8, |
| 1332 | }, |
| 1333 | [pbn_b0_4_1843200] = { |
| 1334 | .flags = FL_BASE0, |
| 1335 | .num_ports = 4, |
| 1336 | .base_baud = 1843200, |
| 1337 | .uart_offset = 8, |
| 1338 | }, |
| 1339 | |
| 1340 | [pbn_b0_2_1843200_200] = { |
| 1341 | .flags = FL_BASE0, |
| 1342 | .num_ports = 2, |
| 1343 | .base_baud = 1843200, |
| 1344 | .uart_offset = 0x200, |
| 1345 | }, |
| 1346 | [pbn_b0_4_1843200_200] = { |
| 1347 | .flags = FL_BASE0, |
| 1348 | .num_ports = 4, |
| 1349 | .base_baud = 1843200, |
| 1350 | .uart_offset = 0x200, |
| 1351 | }, |
| 1352 | [pbn_b0_8_1843200_200] = { |
| 1353 | .flags = FL_BASE0, |
| 1354 | .num_ports = 8, |
| 1355 | .base_baud = 1843200, |
| 1356 | .uart_offset = 0x200, |
| 1357 | }, |
Lee Howard | 7106b4e | 2008-10-21 13:48:58 +0100 | [diff] [blame] | 1358 | [pbn_b0_1_4000000] = { |
| 1359 | .flags = FL_BASE0, |
| 1360 | .num_ports = 1, |
| 1361 | .base_baud = 4000000, |
| 1362 | .uart_offset = 8, |
| 1363 | }, |
Gareth Howlett | 26e9286 | 2006-01-04 17:00:42 +0000 | [diff] [blame] | 1364 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1365 | [pbn_b0_bt_1_115200] = { |
| 1366 | .flags = FL_BASE0|FL_BASE_BARS, |
| 1367 | .num_ports = 1, |
| 1368 | .base_baud = 115200, |
| 1369 | .uart_offset = 8, |
| 1370 | }, |
| 1371 | [pbn_b0_bt_2_115200] = { |
| 1372 | .flags = FL_BASE0|FL_BASE_BARS, |
| 1373 | .num_ports = 2, |
| 1374 | .base_baud = 115200, |
| 1375 | .uart_offset = 8, |
| 1376 | }, |
| 1377 | [pbn_b0_bt_8_115200] = { |
| 1378 | .flags = FL_BASE0|FL_BASE_BARS, |
| 1379 | .num_ports = 8, |
| 1380 | .base_baud = 115200, |
| 1381 | .uart_offset = 8, |
| 1382 | }, |
| 1383 | |
| 1384 | [pbn_b0_bt_1_460800] = { |
| 1385 | .flags = FL_BASE0|FL_BASE_BARS, |
| 1386 | .num_ports = 1, |
| 1387 | .base_baud = 460800, |
| 1388 | .uart_offset = 8, |
| 1389 | }, |
| 1390 | [pbn_b0_bt_2_460800] = { |
| 1391 | .flags = FL_BASE0|FL_BASE_BARS, |
| 1392 | .num_ports = 2, |
| 1393 | .base_baud = 460800, |
| 1394 | .uart_offset = 8, |
| 1395 | }, |
| 1396 | [pbn_b0_bt_4_460800] = { |
| 1397 | .flags = FL_BASE0|FL_BASE_BARS, |
| 1398 | .num_ports = 4, |
| 1399 | .base_baud = 460800, |
| 1400 | .uart_offset = 8, |
| 1401 | }, |
| 1402 | |
| 1403 | [pbn_b0_bt_1_921600] = { |
| 1404 | .flags = FL_BASE0|FL_BASE_BARS, |
| 1405 | .num_ports = 1, |
| 1406 | .base_baud = 921600, |
| 1407 | .uart_offset = 8, |
| 1408 | }, |
| 1409 | [pbn_b0_bt_2_921600] = { |
| 1410 | .flags = FL_BASE0|FL_BASE_BARS, |
| 1411 | .num_ports = 2, |
| 1412 | .base_baud = 921600, |
| 1413 | .uart_offset = 8, |
| 1414 | }, |
| 1415 | [pbn_b0_bt_4_921600] = { |
| 1416 | .flags = FL_BASE0|FL_BASE_BARS, |
| 1417 | .num_ports = 4, |
| 1418 | .base_baud = 921600, |
| 1419 | .uart_offset = 8, |
| 1420 | }, |
| 1421 | [pbn_b0_bt_8_921600] = { |
| 1422 | .flags = FL_BASE0|FL_BASE_BARS, |
| 1423 | .num_ports = 8, |
| 1424 | .base_baud = 921600, |
| 1425 | .uart_offset = 8, |
| 1426 | }, |
| 1427 | |
| 1428 | [pbn_b1_1_115200] = { |
| 1429 | .flags = FL_BASE1, |
| 1430 | .num_ports = 1, |
| 1431 | .base_baud = 115200, |
| 1432 | .uart_offset = 8, |
| 1433 | }, |
| 1434 | [pbn_b1_2_115200] = { |
| 1435 | .flags = FL_BASE1, |
| 1436 | .num_ports = 2, |
| 1437 | .base_baud = 115200, |
| 1438 | .uart_offset = 8, |
| 1439 | }, |
| 1440 | [pbn_b1_4_115200] = { |
| 1441 | .flags = FL_BASE1, |
| 1442 | .num_ports = 4, |
| 1443 | .base_baud = 115200, |
| 1444 | .uart_offset = 8, |
| 1445 | }, |
| 1446 | [pbn_b1_8_115200] = { |
| 1447 | .flags = FL_BASE1, |
| 1448 | .num_ports = 8, |
| 1449 | .base_baud = 115200, |
| 1450 | .uart_offset = 8, |
| 1451 | }, |
| 1452 | |
| 1453 | [pbn_b1_1_921600] = { |
| 1454 | .flags = FL_BASE1, |
| 1455 | .num_ports = 1, |
| 1456 | .base_baud = 921600, |
| 1457 | .uart_offset = 8, |
| 1458 | }, |
| 1459 | [pbn_b1_2_921600] = { |
| 1460 | .flags = FL_BASE1, |
| 1461 | .num_ports = 2, |
| 1462 | .base_baud = 921600, |
| 1463 | .uart_offset = 8, |
| 1464 | }, |
| 1465 | [pbn_b1_4_921600] = { |
| 1466 | .flags = FL_BASE1, |
| 1467 | .num_ports = 4, |
| 1468 | .base_baud = 921600, |
| 1469 | .uart_offset = 8, |
| 1470 | }, |
| 1471 | [pbn_b1_8_921600] = { |
| 1472 | .flags = FL_BASE1, |
| 1473 | .num_ports = 8, |
| 1474 | .base_baud = 921600, |
| 1475 | .uart_offset = 8, |
| 1476 | }, |
Gareth Howlett | 26e9286 | 2006-01-04 17:00:42 +0000 | [diff] [blame] | 1477 | [pbn_b1_2_1250000] = { |
| 1478 | .flags = FL_BASE1, |
| 1479 | .num_ports = 2, |
| 1480 | .base_baud = 1250000, |
| 1481 | .uart_offset = 8, |
| 1482 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1483 | |
Niels de Vos | 84f8c6f | 2007-08-22 14:01:14 -0700 | [diff] [blame] | 1484 | [pbn_b1_bt_1_115200] = { |
| 1485 | .flags = FL_BASE1|FL_BASE_BARS, |
| 1486 | .num_ports = 1, |
| 1487 | .base_baud = 115200, |
| 1488 | .uart_offset = 8, |
| 1489 | }, |
| 1490 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1491 | [pbn_b1_bt_2_921600] = { |
| 1492 | .flags = FL_BASE1|FL_BASE_BARS, |
| 1493 | .num_ports = 2, |
| 1494 | .base_baud = 921600, |
| 1495 | .uart_offset = 8, |
| 1496 | }, |
| 1497 | |
| 1498 | [pbn_b1_1_1382400] = { |
| 1499 | .flags = FL_BASE1, |
| 1500 | .num_ports = 1, |
| 1501 | .base_baud = 1382400, |
| 1502 | .uart_offset = 8, |
| 1503 | }, |
| 1504 | [pbn_b1_2_1382400] = { |
| 1505 | .flags = FL_BASE1, |
| 1506 | .num_ports = 2, |
| 1507 | .base_baud = 1382400, |
| 1508 | .uart_offset = 8, |
| 1509 | }, |
| 1510 | [pbn_b1_4_1382400] = { |
| 1511 | .flags = FL_BASE1, |
| 1512 | .num_ports = 4, |
| 1513 | .base_baud = 1382400, |
| 1514 | .uart_offset = 8, |
| 1515 | }, |
| 1516 | [pbn_b1_8_1382400] = { |
| 1517 | .flags = FL_BASE1, |
| 1518 | .num_ports = 8, |
| 1519 | .base_baud = 1382400, |
| 1520 | .uart_offset = 8, |
| 1521 | }, |
| 1522 | |
| 1523 | [pbn_b2_1_115200] = { |
| 1524 | .flags = FL_BASE2, |
| 1525 | .num_ports = 1, |
| 1526 | .base_baud = 115200, |
| 1527 | .uart_offset = 8, |
| 1528 | }, |
Peter Horton | 737c175 | 2006-08-26 09:07:36 +0100 | [diff] [blame] | 1529 | [pbn_b2_2_115200] = { |
| 1530 | .flags = FL_BASE2, |
| 1531 | .num_ports = 2, |
| 1532 | .base_baud = 115200, |
| 1533 | .uart_offset = 8, |
| 1534 | }, |
Matthias Fuchs | a9cccd3 | 2007-02-10 01:46:05 -0800 | [diff] [blame] | 1535 | [pbn_b2_4_115200] = { |
| 1536 | .flags = FL_BASE2, |
| 1537 | .num_ports = 4, |
| 1538 | .base_baud = 115200, |
| 1539 | .uart_offset = 8, |
| 1540 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1541 | [pbn_b2_8_115200] = { |
| 1542 | .flags = FL_BASE2, |
| 1543 | .num_ports = 8, |
| 1544 | .base_baud = 115200, |
| 1545 | .uart_offset = 8, |
| 1546 | }, |
| 1547 | |
| 1548 | [pbn_b2_1_460800] = { |
| 1549 | .flags = FL_BASE2, |
| 1550 | .num_ports = 1, |
| 1551 | .base_baud = 460800, |
| 1552 | .uart_offset = 8, |
| 1553 | }, |
| 1554 | [pbn_b2_4_460800] = { |
| 1555 | .flags = FL_BASE2, |
| 1556 | .num_ports = 4, |
| 1557 | .base_baud = 460800, |
| 1558 | .uart_offset = 8, |
| 1559 | }, |
| 1560 | [pbn_b2_8_460800] = { |
| 1561 | .flags = FL_BASE2, |
| 1562 | .num_ports = 8, |
| 1563 | .base_baud = 460800, |
| 1564 | .uart_offset = 8, |
| 1565 | }, |
| 1566 | [pbn_b2_16_460800] = { |
| 1567 | .flags = FL_BASE2, |
| 1568 | .num_ports = 16, |
| 1569 | .base_baud = 460800, |
| 1570 | .uart_offset = 8, |
| 1571 | }, |
| 1572 | |
| 1573 | [pbn_b2_1_921600] = { |
| 1574 | .flags = FL_BASE2, |
| 1575 | .num_ports = 1, |
| 1576 | .base_baud = 921600, |
| 1577 | .uart_offset = 8, |
| 1578 | }, |
| 1579 | [pbn_b2_4_921600] = { |
| 1580 | .flags = FL_BASE2, |
| 1581 | .num_ports = 4, |
| 1582 | .base_baud = 921600, |
| 1583 | .uart_offset = 8, |
| 1584 | }, |
| 1585 | [pbn_b2_8_921600] = { |
| 1586 | .flags = FL_BASE2, |
| 1587 | .num_ports = 8, |
| 1588 | .base_baud = 921600, |
| 1589 | .uart_offset = 8, |
| 1590 | }, |
| 1591 | |
| 1592 | [pbn_b2_bt_1_115200] = { |
| 1593 | .flags = FL_BASE2|FL_BASE_BARS, |
| 1594 | .num_ports = 1, |
| 1595 | .base_baud = 115200, |
| 1596 | .uart_offset = 8, |
| 1597 | }, |
| 1598 | [pbn_b2_bt_2_115200] = { |
| 1599 | .flags = FL_BASE2|FL_BASE_BARS, |
| 1600 | .num_ports = 2, |
| 1601 | .base_baud = 115200, |
| 1602 | .uart_offset = 8, |
| 1603 | }, |
| 1604 | [pbn_b2_bt_4_115200] = { |
| 1605 | .flags = FL_BASE2|FL_BASE_BARS, |
| 1606 | .num_ports = 4, |
| 1607 | .base_baud = 115200, |
| 1608 | .uart_offset = 8, |
| 1609 | }, |
| 1610 | |
| 1611 | [pbn_b2_bt_2_921600] = { |
| 1612 | .flags = FL_BASE2|FL_BASE_BARS, |
| 1613 | .num_ports = 2, |
| 1614 | .base_baud = 921600, |
| 1615 | .uart_offset = 8, |
| 1616 | }, |
| 1617 | [pbn_b2_bt_4_921600] = { |
| 1618 | .flags = FL_BASE2|FL_BASE_BARS, |
| 1619 | .num_ports = 4, |
| 1620 | .base_baud = 921600, |
| 1621 | .uart_offset = 8, |
| 1622 | }, |
| 1623 | |
Alon Bar-Lev | d9004eb | 2006-01-18 11:47:33 +0000 | [diff] [blame] | 1624 | [pbn_b3_2_115200] = { |
| 1625 | .flags = FL_BASE3, |
| 1626 | .num_ports = 2, |
| 1627 | .base_baud = 115200, |
| 1628 | .uart_offset = 8, |
| 1629 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1630 | [pbn_b3_4_115200] = { |
| 1631 | .flags = FL_BASE3, |
| 1632 | .num_ports = 4, |
| 1633 | .base_baud = 115200, |
| 1634 | .uart_offset = 8, |
| 1635 | }, |
| 1636 | [pbn_b3_8_115200] = { |
| 1637 | .flags = FL_BASE3, |
| 1638 | .num_ports = 8, |
| 1639 | .base_baud = 115200, |
| 1640 | .uart_offset = 8, |
| 1641 | }, |
| 1642 | |
| 1643 | /* |
| 1644 | * Entries following this are board-specific. |
| 1645 | */ |
| 1646 | |
| 1647 | /* |
| 1648 | * Panacom - IOMEM |
| 1649 | */ |
| 1650 | [pbn_panacom] = { |
| 1651 | .flags = FL_BASE2, |
| 1652 | .num_ports = 2, |
| 1653 | .base_baud = 921600, |
| 1654 | .uart_offset = 0x400, |
| 1655 | .reg_shift = 7, |
| 1656 | }, |
| 1657 | [pbn_panacom2] = { |
| 1658 | .flags = FL_BASE2|FL_BASE_BARS, |
| 1659 | .num_ports = 2, |
| 1660 | .base_baud = 921600, |
| 1661 | .uart_offset = 0x400, |
| 1662 | .reg_shift = 7, |
| 1663 | }, |
| 1664 | [pbn_panacom4] = { |
| 1665 | .flags = FL_BASE2|FL_BASE_BARS, |
| 1666 | .num_ports = 4, |
| 1667 | .base_baud = 921600, |
| 1668 | .uart_offset = 0x400, |
| 1669 | .reg_shift = 7, |
| 1670 | }, |
| 1671 | |
Bjorn Helgaas | add7b58 | 2005-10-24 22:11:57 +0100 | [diff] [blame] | 1672 | [pbn_exsys_4055] = { |
| 1673 | .flags = FL_BASE2, |
| 1674 | .num_ports = 4, |
| 1675 | .base_baud = 115200, |
| 1676 | .uart_offset = 8, |
| 1677 | }, |
| 1678 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1679 | /* I think this entry is broken - the first_offset looks wrong --rmk */ |
| 1680 | [pbn_plx_romulus] = { |
| 1681 | .flags = FL_BASE2, |
| 1682 | .num_ports = 4, |
| 1683 | .base_baud = 921600, |
| 1684 | .uart_offset = 8 << 2, |
| 1685 | .reg_shift = 2, |
| 1686 | .first_offset = 0x03, |
| 1687 | }, |
| 1688 | |
| 1689 | /* |
| 1690 | * This board uses the size of PCI Base region 0 to |
| 1691 | * signal now many ports are available |
| 1692 | */ |
| 1693 | [pbn_oxsemi] = { |
| 1694 | .flags = FL_BASE0|FL_REGION_SZ_CAP, |
| 1695 | .num_ports = 32, |
| 1696 | .base_baud = 115200, |
| 1697 | .uart_offset = 8, |
| 1698 | }, |
Lee Howard | 7106b4e | 2008-10-21 13:48:58 +0100 | [diff] [blame] | 1699 | [pbn_oxsemi_1_4000000] = { |
| 1700 | .flags = FL_BASE0, |
| 1701 | .num_ports = 1, |
| 1702 | .base_baud = 4000000, |
| 1703 | .uart_offset = 0x200, |
| 1704 | .first_offset = 0x1000, |
| 1705 | }, |
| 1706 | [pbn_oxsemi_2_4000000] = { |
| 1707 | .flags = FL_BASE0, |
| 1708 | .num_ports = 2, |
| 1709 | .base_baud = 4000000, |
| 1710 | .uart_offset = 0x200, |
| 1711 | .first_offset = 0x1000, |
| 1712 | }, |
| 1713 | [pbn_oxsemi_4_4000000] = { |
| 1714 | .flags = FL_BASE0, |
| 1715 | .num_ports = 4, |
| 1716 | .base_baud = 4000000, |
| 1717 | .uart_offset = 0x200, |
| 1718 | .first_offset = 0x1000, |
| 1719 | }, |
| 1720 | [pbn_oxsemi_8_4000000] = { |
| 1721 | .flags = FL_BASE0, |
| 1722 | .num_ports = 8, |
| 1723 | .base_baud = 4000000, |
| 1724 | .uart_offset = 0x200, |
| 1725 | .first_offset = 0x1000, |
| 1726 | }, |
| 1727 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1728 | |
| 1729 | /* |
| 1730 | * EKF addition for i960 Boards form EKF with serial port. |
| 1731 | * Max 256 ports. |
| 1732 | */ |
| 1733 | [pbn_intel_i960] = { |
| 1734 | .flags = FL_BASE0, |
| 1735 | .num_ports = 32, |
| 1736 | .base_baud = 921600, |
| 1737 | .uart_offset = 8 << 2, |
| 1738 | .reg_shift = 2, |
| 1739 | .first_offset = 0x10000, |
| 1740 | }, |
| 1741 | [pbn_sgi_ioc3] = { |
| 1742 | .flags = FL_BASE0|FL_NOIRQ, |
| 1743 | .num_ports = 1, |
| 1744 | .base_baud = 458333, |
| 1745 | .uart_offset = 8, |
| 1746 | .reg_shift = 0, |
| 1747 | .first_offset = 0x20178, |
| 1748 | }, |
| 1749 | |
| 1750 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1751 | * Computone - uses IOMEM. |
| 1752 | */ |
| 1753 | [pbn_computone_4] = { |
| 1754 | .flags = FL_BASE0, |
| 1755 | .num_ports = 4, |
| 1756 | .base_baud = 921600, |
| 1757 | .uart_offset = 0x40, |
| 1758 | .reg_shift = 2, |
| 1759 | .first_offset = 0x200, |
| 1760 | }, |
| 1761 | [pbn_computone_6] = { |
| 1762 | .flags = FL_BASE0, |
| 1763 | .num_ports = 6, |
| 1764 | .base_baud = 921600, |
| 1765 | .uart_offset = 0x40, |
| 1766 | .reg_shift = 2, |
| 1767 | .first_offset = 0x200, |
| 1768 | }, |
| 1769 | [pbn_computone_8] = { |
| 1770 | .flags = FL_BASE0, |
| 1771 | .num_ports = 8, |
| 1772 | .base_baud = 921600, |
| 1773 | .uart_offset = 0x40, |
| 1774 | .reg_shift = 2, |
| 1775 | .first_offset = 0x200, |
| 1776 | }, |
| 1777 | [pbn_sbsxrsio] = { |
| 1778 | .flags = FL_BASE0, |
| 1779 | .num_ports = 8, |
| 1780 | .base_baud = 460800, |
| 1781 | .uart_offset = 256, |
| 1782 | .reg_shift = 4, |
| 1783 | }, |
| 1784 | /* |
| 1785 | * Exar Corp. XR17C15[248] Dual/Quad/Octal UART |
| 1786 | * Only basic 16550A support. |
| 1787 | * XR17C15[24] are not tested, but they should work. |
| 1788 | */ |
| 1789 | [pbn_exar_XR17C152] = { |
| 1790 | .flags = FL_BASE0, |
| 1791 | .num_ports = 2, |
| 1792 | .base_baud = 921600, |
| 1793 | .uart_offset = 0x200, |
| 1794 | }, |
| 1795 | [pbn_exar_XR17C154] = { |
| 1796 | .flags = FL_BASE0, |
| 1797 | .num_ports = 4, |
| 1798 | .base_baud = 921600, |
| 1799 | .uart_offset = 0x200, |
| 1800 | }, |
| 1801 | [pbn_exar_XR17C158] = { |
| 1802 | .flags = FL_BASE0, |
| 1803 | .num_ports = 8, |
| 1804 | .base_baud = 921600, |
| 1805 | .uart_offset = 0x200, |
| 1806 | }, |
Olof Johansson | aa79850 | 2007-08-22 14:01:55 -0700 | [diff] [blame] | 1807 | /* |
| 1808 | * PA Semi PWRficient PA6T-1682M on-chip UART |
| 1809 | */ |
| 1810 | [pbn_pasemi_1682M] = { |
| 1811 | .flags = FL_BASE0, |
| 1812 | .num_ports = 1, |
| 1813 | .base_baud = 8333333, |
| 1814 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1815 | }; |
| 1816 | |
Christian Schmidt | 436bbd4 | 2007-08-22 14:01:19 -0700 | [diff] [blame] | 1817 | static const struct pci_device_id softmodem_blacklist[] = { |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 1818 | { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ |
Christian Schmidt | 436bbd4 | 2007-08-22 14:01:19 -0700 | [diff] [blame] | 1819 | }; |
| 1820 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1821 | /* |
| 1822 | * Given a complete unknown PCI device, try to use some heuristics to |
| 1823 | * guess what the configuration might be, based on the pitiful PCI |
| 1824 | * serial specs. Returns 0 on success, 1 on failure. |
| 1825 | */ |
| 1826 | static int __devinit |
Russell King | 1c7c1fe | 2005-07-27 11:31:19 +0100 | [diff] [blame] | 1827 | serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1828 | { |
Christian Schmidt | 436bbd4 | 2007-08-22 14:01:19 -0700 | [diff] [blame] | 1829 | const struct pci_device_id *blacklist; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1830 | int num_iomem, num_port, first_port = -1, i; |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 1831 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1832 | /* |
| 1833 | * If it is not a communications device or the programming |
| 1834 | * interface is greater than 6, give up. |
| 1835 | * |
| 1836 | * (Should we try to make guesses for multiport serial devices |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 1837 | * later?) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1838 | */ |
| 1839 | if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && |
| 1840 | ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || |
| 1841 | (dev->class & 0xff) > 6) |
| 1842 | return -ENODEV; |
| 1843 | |
Christian Schmidt | 436bbd4 | 2007-08-22 14:01:19 -0700 | [diff] [blame] | 1844 | /* |
| 1845 | * Do not access blacklisted devices that are known not to |
| 1846 | * feature serial ports. |
| 1847 | */ |
| 1848 | for (blacklist = softmodem_blacklist; |
| 1849 | blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist); |
| 1850 | blacklist++) { |
| 1851 | if (dev->vendor == blacklist->vendor && |
| 1852 | dev->device == blacklist->device) |
| 1853 | return -ENODEV; |
| 1854 | } |
| 1855 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1856 | num_iomem = num_port = 0; |
| 1857 | for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { |
| 1858 | if (pci_resource_flags(dev, i) & IORESOURCE_IO) { |
| 1859 | num_port++; |
| 1860 | if (first_port == -1) |
| 1861 | first_port = i; |
| 1862 | } |
| 1863 | if (pci_resource_flags(dev, i) & IORESOURCE_MEM) |
| 1864 | num_iomem++; |
| 1865 | } |
| 1866 | |
| 1867 | /* |
| 1868 | * If there is 1 or 0 iomem regions, and exactly one port, |
| 1869 | * use it. We guess the number of ports based on the IO |
| 1870 | * region size. |
| 1871 | */ |
| 1872 | if (num_iomem <= 1 && num_port == 1) { |
| 1873 | board->flags = first_port; |
| 1874 | board->num_ports = pci_resource_len(dev, first_port) / 8; |
| 1875 | return 0; |
| 1876 | } |
| 1877 | |
| 1878 | /* |
| 1879 | * Now guess if we've got a board which indexes by BARs. |
| 1880 | * Each IO BAR should be 8 bytes, and they should follow |
| 1881 | * consecutively. |
| 1882 | */ |
| 1883 | first_port = -1; |
| 1884 | num_port = 0; |
| 1885 | for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { |
| 1886 | if (pci_resource_flags(dev, i) & IORESOURCE_IO && |
| 1887 | pci_resource_len(dev, i) == 8 && |
| 1888 | (first_port == -1 || (first_port + num_port) == i)) { |
| 1889 | num_port++; |
| 1890 | if (first_port == -1) |
| 1891 | first_port = i; |
| 1892 | } |
| 1893 | } |
| 1894 | |
| 1895 | if (num_port > 1) { |
| 1896 | board->flags = first_port | FL_BASE_BARS; |
| 1897 | board->num_ports = num_port; |
| 1898 | return 0; |
| 1899 | } |
| 1900 | |
| 1901 | return -ENODEV; |
| 1902 | } |
| 1903 | |
| 1904 | static inline int |
Russell King | 975a1a7 | 2009-01-02 13:44:27 +0000 | [diff] [blame] | 1905 | serial_pci_matches(const struct pciserial_board *board, |
| 1906 | const struct pciserial_board *guessed) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1907 | { |
| 1908 | return |
| 1909 | board->num_ports == guessed->num_ports && |
| 1910 | board->base_baud == guessed->base_baud && |
| 1911 | board->uart_offset == guessed->uart_offset && |
| 1912 | board->reg_shift == guessed->reg_shift && |
| 1913 | board->first_offset == guessed->first_offset; |
| 1914 | } |
| 1915 | |
Russell King | 241fc43 | 2005-07-27 11:35:54 +0100 | [diff] [blame] | 1916 | struct serial_private * |
Russell King | 975a1a7 | 2009-01-02 13:44:27 +0000 | [diff] [blame] | 1917 | pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) |
Russell King | 241fc43 | 2005-07-27 11:35:54 +0100 | [diff] [blame] | 1918 | { |
| 1919 | struct uart_port serial_port; |
| 1920 | struct serial_private *priv; |
| 1921 | struct pci_serial_quirk *quirk; |
| 1922 | int rc, nr_ports, i; |
| 1923 | |
| 1924 | nr_ports = board->num_ports; |
| 1925 | |
| 1926 | /* |
| 1927 | * Find an init and setup quirks. |
| 1928 | */ |
| 1929 | quirk = find_quirk(dev); |
| 1930 | |
| 1931 | /* |
| 1932 | * Run the new-style initialization function. |
| 1933 | * The initialization function returns: |
| 1934 | * <0 - error |
| 1935 | * 0 - use board->num_ports |
| 1936 | * >0 - number of ports |
| 1937 | */ |
| 1938 | if (quirk->init) { |
| 1939 | rc = quirk->init(dev); |
| 1940 | if (rc < 0) { |
| 1941 | priv = ERR_PTR(rc); |
| 1942 | goto err_out; |
| 1943 | } |
| 1944 | if (rc) |
| 1945 | nr_ports = rc; |
| 1946 | } |
| 1947 | |
Burman Yan | 8f31bb3 | 2007-02-14 00:33:07 -0800 | [diff] [blame] | 1948 | priv = kzalloc(sizeof(struct serial_private) + |
Russell King | 241fc43 | 2005-07-27 11:35:54 +0100 | [diff] [blame] | 1949 | sizeof(unsigned int) * nr_ports, |
| 1950 | GFP_KERNEL); |
| 1951 | if (!priv) { |
| 1952 | priv = ERR_PTR(-ENOMEM); |
| 1953 | goto err_deinit; |
| 1954 | } |
| 1955 | |
Russell King | 241fc43 | 2005-07-27 11:35:54 +0100 | [diff] [blame] | 1956 | priv->dev = dev; |
| 1957 | priv->quirk = quirk; |
| 1958 | |
| 1959 | memset(&serial_port, 0, sizeof(struct uart_port)); |
| 1960 | serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; |
| 1961 | serial_port.uartclk = board->base_baud * 16; |
| 1962 | serial_port.irq = get_pci_irq(dev, board); |
| 1963 | serial_port.dev = &dev->dev; |
| 1964 | |
| 1965 | for (i = 0; i < nr_ports; i++) { |
| 1966 | if (quirk->setup(priv, board, &serial_port, i)) |
| 1967 | break; |
| 1968 | |
| 1969 | #ifdef SERIAL_DEBUG_PCI |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 1970 | printk(KERN_DEBUG "Setup PCI port: port %x, irq %d, type %d\n", |
Russell King | 241fc43 | 2005-07-27 11:35:54 +0100 | [diff] [blame] | 1971 | serial_port.iobase, serial_port.irq, serial_port.iotype); |
| 1972 | #endif |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 1973 | |
Russell King | 241fc43 | 2005-07-27 11:35:54 +0100 | [diff] [blame] | 1974 | priv->line[i] = serial8250_register_port(&serial_port); |
| 1975 | if (priv->line[i] < 0) { |
| 1976 | printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]); |
| 1977 | break; |
| 1978 | } |
| 1979 | } |
Russell King | 241fc43 | 2005-07-27 11:35:54 +0100 | [diff] [blame] | 1980 | priv->nr = i; |
Russell King | 241fc43 | 2005-07-27 11:35:54 +0100 | [diff] [blame] | 1981 | return priv; |
| 1982 | |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 1983 | err_deinit: |
Russell King | 241fc43 | 2005-07-27 11:35:54 +0100 | [diff] [blame] | 1984 | if (quirk->exit) |
| 1985 | quirk->exit(dev); |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 1986 | err_out: |
Russell King | 241fc43 | 2005-07-27 11:35:54 +0100 | [diff] [blame] | 1987 | return priv; |
| 1988 | } |
| 1989 | EXPORT_SYMBOL_GPL(pciserial_init_ports); |
| 1990 | |
| 1991 | void pciserial_remove_ports(struct serial_private *priv) |
| 1992 | { |
| 1993 | struct pci_serial_quirk *quirk; |
| 1994 | int i; |
| 1995 | |
| 1996 | for (i = 0; i < priv->nr; i++) |
| 1997 | serial8250_unregister_port(priv->line[i]); |
| 1998 | |
| 1999 | for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { |
| 2000 | if (priv->remapped_bar[i]) |
| 2001 | iounmap(priv->remapped_bar[i]); |
| 2002 | priv->remapped_bar[i] = NULL; |
| 2003 | } |
| 2004 | |
| 2005 | /* |
| 2006 | * Find the exit quirks. |
| 2007 | */ |
| 2008 | quirk = find_quirk(priv->dev); |
| 2009 | if (quirk->exit) |
| 2010 | quirk->exit(priv->dev); |
| 2011 | |
| 2012 | kfree(priv); |
| 2013 | } |
| 2014 | EXPORT_SYMBOL_GPL(pciserial_remove_ports); |
| 2015 | |
| 2016 | void pciserial_suspend_ports(struct serial_private *priv) |
| 2017 | { |
| 2018 | int i; |
| 2019 | |
| 2020 | for (i = 0; i < priv->nr; i++) |
| 2021 | if (priv->line[i] >= 0) |
| 2022 | serial8250_suspend_port(priv->line[i]); |
| 2023 | } |
| 2024 | EXPORT_SYMBOL_GPL(pciserial_suspend_ports); |
| 2025 | |
| 2026 | void pciserial_resume_ports(struct serial_private *priv) |
| 2027 | { |
| 2028 | int i; |
| 2029 | |
| 2030 | /* |
| 2031 | * Ensure that the board is correctly configured. |
| 2032 | */ |
| 2033 | if (priv->quirk->init) |
| 2034 | priv->quirk->init(priv->dev); |
| 2035 | |
| 2036 | for (i = 0; i < priv->nr; i++) |
| 2037 | if (priv->line[i] >= 0) |
| 2038 | serial8250_resume_port(priv->line[i]); |
| 2039 | } |
| 2040 | EXPORT_SYMBOL_GPL(pciserial_resume_ports); |
| 2041 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2042 | /* |
| 2043 | * Probe one serial board. Unfortunately, there is no rhyme nor reason |
| 2044 | * to the arrangement of serial ports on a PCI card. |
| 2045 | */ |
| 2046 | static int __devinit |
| 2047 | pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) |
| 2048 | { |
| 2049 | struct serial_private *priv; |
Russell King | 975a1a7 | 2009-01-02 13:44:27 +0000 | [diff] [blame] | 2050 | const struct pciserial_board *board; |
| 2051 | struct pciserial_board tmp; |
Russell King | 241fc43 | 2005-07-27 11:35:54 +0100 | [diff] [blame] | 2052 | int rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2053 | |
| 2054 | if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { |
| 2055 | printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n", |
| 2056 | ent->driver_data); |
| 2057 | return -EINVAL; |
| 2058 | } |
| 2059 | |
| 2060 | board = &pci_boards[ent->driver_data]; |
| 2061 | |
| 2062 | rc = pci_enable_device(dev); |
| 2063 | if (rc) |
| 2064 | return rc; |
| 2065 | |
| 2066 | if (ent->driver_data == pbn_default) { |
| 2067 | /* |
| 2068 | * Use a copy of the pci_board entry for this; |
| 2069 | * avoid changing entries in the table. |
| 2070 | */ |
Russell King | 1c7c1fe | 2005-07-27 11:31:19 +0100 | [diff] [blame] | 2071 | memcpy(&tmp, board, sizeof(struct pciserial_board)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2072 | board = &tmp; |
| 2073 | |
| 2074 | /* |
| 2075 | * We matched one of our class entries. Try to |
| 2076 | * determine the parameters of this board. |
| 2077 | */ |
Russell King | 975a1a7 | 2009-01-02 13:44:27 +0000 | [diff] [blame] | 2078 | rc = serial_pci_guess_board(dev, &tmp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2079 | if (rc) |
| 2080 | goto disable; |
| 2081 | } else { |
| 2082 | /* |
| 2083 | * We matched an explicit entry. If we are able to |
| 2084 | * detect this boards settings with our heuristic, |
| 2085 | * then we no longer need this entry. |
| 2086 | */ |
Russell King | 1c7c1fe | 2005-07-27 11:31:19 +0100 | [diff] [blame] | 2087 | memcpy(&tmp, &pci_boards[pbn_default], |
| 2088 | sizeof(struct pciserial_board)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2089 | rc = serial_pci_guess_board(dev, &tmp); |
| 2090 | if (rc == 0 && serial_pci_matches(board, &tmp)) |
| 2091 | moan_device("Redundant entry in serial pci_table.", |
| 2092 | dev); |
| 2093 | } |
| 2094 | |
Russell King | 241fc43 | 2005-07-27 11:35:54 +0100 | [diff] [blame] | 2095 | priv = pciserial_init_ports(dev, board); |
| 2096 | if (!IS_ERR(priv)) { |
| 2097 | pci_set_drvdata(dev, priv); |
| 2098 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2099 | } |
| 2100 | |
Russell King | 241fc43 | 2005-07-27 11:35:54 +0100 | [diff] [blame] | 2101 | rc = PTR_ERR(priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2102 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2103 | disable: |
| 2104 | pci_disable_device(dev); |
| 2105 | return rc; |
| 2106 | } |
| 2107 | |
| 2108 | static void __devexit pciserial_remove_one(struct pci_dev *dev) |
| 2109 | { |
| 2110 | struct serial_private *priv = pci_get_drvdata(dev); |
| 2111 | |
| 2112 | pci_set_drvdata(dev, NULL); |
| 2113 | |
Russell King | 241fc43 | 2005-07-27 11:35:54 +0100 | [diff] [blame] | 2114 | pciserial_remove_ports(priv); |
Russell King | 056a876 | 2005-07-22 10:15:04 +0100 | [diff] [blame] | 2115 | |
| 2116 | pci_disable_device(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2117 | } |
| 2118 | |
Alexey Dobriyan | 1d5e799 | 2006-09-25 16:51:27 -0700 | [diff] [blame] | 2119 | #ifdef CONFIG_PM |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2120 | static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state) |
| 2121 | { |
| 2122 | struct serial_private *priv = pci_get_drvdata(dev); |
| 2123 | |
Russell King | 241fc43 | 2005-07-27 11:35:54 +0100 | [diff] [blame] | 2124 | if (priv) |
| 2125 | pciserial_suspend_ports(priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2126 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2127 | pci_save_state(dev); |
| 2128 | pci_set_power_state(dev, pci_choose_state(dev, state)); |
| 2129 | return 0; |
| 2130 | } |
| 2131 | |
| 2132 | static int pciserial_resume_one(struct pci_dev *dev) |
| 2133 | { |
Dirk Hohndel | ccb9d59 | 2007-10-29 06:28:17 -0700 | [diff] [blame] | 2134 | int err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2135 | struct serial_private *priv = pci_get_drvdata(dev); |
| 2136 | |
| 2137 | pci_set_power_state(dev, PCI_D0); |
| 2138 | pci_restore_state(dev); |
| 2139 | |
| 2140 | if (priv) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2141 | /* |
| 2142 | * The device may have been disabled. Re-enable it. |
| 2143 | */ |
Dirk Hohndel | ccb9d59 | 2007-10-29 06:28:17 -0700 | [diff] [blame] | 2144 | err = pci_enable_device(dev); |
Alan Cox | 40836c4 | 2008-10-13 10:36:11 +0100 | [diff] [blame] | 2145 | /* FIXME: We cannot simply error out here */ |
Dirk Hohndel | ccb9d59 | 2007-10-29 06:28:17 -0700 | [diff] [blame] | 2146 | if (err) |
Alan Cox | 40836c4 | 2008-10-13 10:36:11 +0100 | [diff] [blame] | 2147 | printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n"); |
Russell King | 241fc43 | 2005-07-27 11:35:54 +0100 | [diff] [blame] | 2148 | pciserial_resume_ports(priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2149 | } |
| 2150 | return 0; |
| 2151 | } |
Alexey Dobriyan | 1d5e799 | 2006-09-25 16:51:27 -0700 | [diff] [blame] | 2152 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2153 | |
| 2154 | static struct pci_device_id serial_pci_tbl[] = { |
| 2155 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, |
| 2156 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2157 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, |
| 2158 | pbn_b1_8_1382400 }, |
| 2159 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, |
| 2160 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2161 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, |
| 2162 | pbn_b1_4_1382400 }, |
| 2163 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, |
| 2164 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2165 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, |
| 2166 | pbn_b1_2_1382400 }, |
| 2167 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
| 2168 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2169 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, |
| 2170 | pbn_b1_8_1382400 }, |
| 2171 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
| 2172 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2173 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, |
| 2174 | pbn_b1_4_1382400 }, |
| 2175 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
| 2176 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2177 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, |
| 2178 | pbn_b1_2_1382400 }, |
| 2179 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
| 2180 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2181 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, |
| 2182 | pbn_b1_8_921600 }, |
| 2183 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
| 2184 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2185 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, |
| 2186 | pbn_b1_8_921600 }, |
| 2187 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
| 2188 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2189 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, |
| 2190 | pbn_b1_4_921600 }, |
| 2191 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
| 2192 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2193 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, |
| 2194 | pbn_b1_4_921600 }, |
| 2195 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
| 2196 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2197 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, |
| 2198 | pbn_b1_2_921600 }, |
| 2199 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
| 2200 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2201 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, |
| 2202 | pbn_b1_8_921600 }, |
| 2203 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
| 2204 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2205 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, |
| 2206 | pbn_b1_8_921600 }, |
| 2207 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
| 2208 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2209 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, |
| 2210 | pbn_b1_4_921600 }, |
Gareth Howlett | 26e9286 | 2006-01-04 17:00:42 +0000 | [diff] [blame] | 2211 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
| 2212 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2213 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, |
| 2214 | pbn_b1_2_1250000 }, |
| 2215 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, |
| 2216 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2217 | PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, |
| 2218 | pbn_b0_2_1843200 }, |
| 2219 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, |
| 2220 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2221 | PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, |
| 2222 | pbn_b0_4_1843200 }, |
Yoichi Yuasa | 85d1494 | 2006-02-08 21:46:24 +0000 | [diff] [blame] | 2223 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, |
| 2224 | PCI_VENDOR_ID_AFAVLAB, |
| 2225 | PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, |
| 2226 | pbn_b0_4_1152000 }, |
Gareth Howlett | 26e9286 | 2006-01-04 17:00:42 +0000 | [diff] [blame] | 2227 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, |
| 2228 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2229 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0, |
| 2230 | pbn_b0_2_1843200_200 }, |
| 2231 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, |
| 2232 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2233 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0, |
| 2234 | pbn_b0_4_1843200_200 }, |
| 2235 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, |
| 2236 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2237 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0, |
| 2238 | pbn_b0_8_1843200_200 }, |
| 2239 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, |
| 2240 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2241 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0, |
| 2242 | pbn_b0_2_1843200_200 }, |
| 2243 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, |
| 2244 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2245 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0, |
| 2246 | pbn_b0_4_1843200_200 }, |
| 2247 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, |
| 2248 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2249 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0, |
| 2250 | pbn_b0_8_1843200_200 }, |
| 2251 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, |
| 2252 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2253 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0, |
| 2254 | pbn_b0_2_1843200_200 }, |
| 2255 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, |
| 2256 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2257 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0, |
| 2258 | pbn_b0_4_1843200_200 }, |
| 2259 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, |
| 2260 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2261 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0, |
| 2262 | pbn_b0_8_1843200_200 }, |
| 2263 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, |
| 2264 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2265 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0, |
| 2266 | pbn_b0_2_1843200_200 }, |
| 2267 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, |
| 2268 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2269 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0, |
| 2270 | pbn_b0_4_1843200_200 }, |
| 2271 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, |
| 2272 | PCI_SUBVENDOR_ID_CONNECT_TECH, |
| 2273 | PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0, |
| 2274 | pbn_b0_8_1843200_200 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2275 | |
| 2276 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 2277 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2278 | pbn_b2_bt_1_115200 }, |
| 2279 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 2280 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2281 | pbn_b2_bt_2_115200 }, |
| 2282 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 2283 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2284 | pbn_b2_bt_4_115200 }, |
| 2285 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 2286 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2287 | pbn_b2_bt_2_115200 }, |
| 2288 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 2289 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2290 | pbn_b2_bt_4_115200 }, |
| 2291 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 2292 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2293 | pbn_b2_8_115200 }, |
Flavio Leitner | e65f0f8 | 2009-01-02 13:50:43 +0000 | [diff] [blame] | 2294 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, |
| 2295 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2296 | pbn_b2_8_460800 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2297 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, |
| 2298 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2299 | pbn_b2_8_115200 }, |
| 2300 | |
| 2301 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, |
| 2302 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2303 | pbn_b2_bt_2_115200 }, |
| 2304 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, |
| 2305 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2306 | pbn_b2_bt_2_921600 }, |
| 2307 | /* |
| 2308 | * VScom SPCOM800, from sl@s.pl |
| 2309 | */ |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 2310 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, |
| 2311 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2312 | pbn_b2_8_921600 }, |
| 2313 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 2314 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2315 | pbn_b2_4_921600 }, |
Catalin(ux) M BOIE | b76c5a0 | 2008-07-23 21:29:46 -0700 | [diff] [blame] | 2316 | /* Unknown card - subdevice 0x1584 */ |
| 2317 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
| 2318 | PCI_VENDOR_ID_PLX, |
| 2319 | PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, |
| 2320 | pbn_b0_4_115200 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2321 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
| 2322 | PCI_SUBVENDOR_ID_KEYSPAN, |
| 2323 | PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, |
| 2324 | pbn_panacom }, |
| 2325 | { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, |
| 2326 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2327 | pbn_panacom4 }, |
| 2328 | { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, |
| 2329 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2330 | pbn_panacom2 }, |
Matthias Fuchs | a9cccd3 | 2007-02-10 01:46:05 -0800 | [diff] [blame] | 2331 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, |
| 2332 | PCI_VENDOR_ID_ESDGMBH, |
| 2333 | PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, |
| 2334 | pbn_b2_4_115200 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2335 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
| 2336 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 2337 | PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2338 | pbn_b2_4_460800 }, |
| 2339 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
| 2340 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 2341 | PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2342 | pbn_b2_8_460800 }, |
| 2343 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
| 2344 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 2345 | PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2346 | pbn_b2_16_460800 }, |
| 2347 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
| 2348 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 2349 | PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2350 | pbn_b2_16_460800 }, |
| 2351 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
| 2352 | PCI_SUBVENDOR_ID_CHASE_PCIRAS, |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 2353 | PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2354 | pbn_b2_4_460800 }, |
| 2355 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
| 2356 | PCI_SUBVENDOR_ID_CHASE_PCIRAS, |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 2357 | PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2358 | pbn_b2_8_460800 }, |
Bjorn Helgaas | add7b58 | 2005-10-24 22:11:57 +0100 | [diff] [blame] | 2359 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
| 2360 | PCI_SUBVENDOR_ID_EXSYS, |
| 2361 | PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, |
| 2362 | pbn_exsys_4055 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2363 | /* |
| 2364 | * Megawolf Romulus PCI Serial Card, from Mike Hudson |
| 2365 | * (Exoray@isys.ca) |
| 2366 | */ |
| 2367 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, |
| 2368 | 0x10b5, 0x106a, 0, 0, |
| 2369 | pbn_plx_romulus }, |
| 2370 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, |
| 2371 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2372 | pbn_b1_4_115200 }, |
| 2373 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, |
| 2374 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2375 | pbn_b1_2_115200 }, |
| 2376 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, |
| 2377 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2378 | pbn_b1_8_115200 }, |
| 2379 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, |
| 2380 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2381 | pbn_b1_8_115200 }, |
| 2382 | { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 2383 | PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, |
| 2384 | 0, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2385 | pbn_b0_4_921600 }, |
| 2386 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 2387 | PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, |
| 2388 | 0, 0, |
Andrey Panin | fbc0dc0 | 2005-07-18 11:38:09 +0100 | [diff] [blame] | 2389 | pbn_b0_4_1152000 }, |
David Ranson | db1de15 | 2005-07-27 11:43:55 -0700 | [diff] [blame] | 2390 | |
| 2391 | /* |
| 2392 | * The below card is a little controversial since it is the |
| 2393 | * subject of a PCI vendor/device ID clash. (See |
| 2394 | * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). |
| 2395 | * For now just used the hex ID 0x950a. |
| 2396 | */ |
| 2397 | { PCI_VENDOR_ID_OXSEMI, 0x950a, |
Niels de Vos | 39aced6 | 2009-01-02 13:46:58 +0000 | [diff] [blame] | 2398 | PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0, |
| 2399 | pbn_b0_2_115200 }, |
| 2400 | { PCI_VENDOR_ID_OXSEMI, 0x950a, |
David Ranson | db1de15 | 2005-07-27 11:43:55 -0700 | [diff] [blame] | 2401 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2402 | pbn_b0_2_1130000 }, |
Andrey Panin | fbc0dc0 | 2005-07-18 11:38:09 +0100 | [diff] [blame] | 2403 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2404 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2405 | pbn_b0_4_115200 }, |
| 2406 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, |
| 2407 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2408 | pbn_b0_bt_2_921600 }, |
| 2409 | |
| 2410 | /* |
Lee Howard | 7106b4e | 2008-10-21 13:48:58 +0100 | [diff] [blame] | 2411 | * Oxford Semiconductor Inc. Tornado PCI express device range. |
| 2412 | */ |
| 2413 | { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ |
| 2414 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2415 | pbn_b0_1_4000000 }, |
| 2416 | { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ |
| 2417 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2418 | pbn_b0_1_4000000 }, |
| 2419 | { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ |
| 2420 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2421 | pbn_oxsemi_1_4000000 }, |
| 2422 | { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ |
| 2423 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2424 | pbn_oxsemi_1_4000000 }, |
| 2425 | { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ |
| 2426 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2427 | pbn_b0_1_4000000 }, |
| 2428 | { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ |
| 2429 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2430 | pbn_b0_1_4000000 }, |
| 2431 | { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ |
| 2432 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2433 | pbn_oxsemi_1_4000000 }, |
| 2434 | { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ |
| 2435 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2436 | pbn_oxsemi_1_4000000 }, |
| 2437 | { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ |
| 2438 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2439 | pbn_b0_1_4000000 }, |
| 2440 | { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ |
| 2441 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2442 | pbn_b0_1_4000000 }, |
| 2443 | { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ |
| 2444 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2445 | pbn_b0_1_4000000 }, |
| 2446 | { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ |
| 2447 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2448 | pbn_b0_1_4000000 }, |
| 2449 | { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ |
| 2450 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2451 | pbn_oxsemi_2_4000000 }, |
| 2452 | { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ |
| 2453 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2454 | pbn_oxsemi_2_4000000 }, |
| 2455 | { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ |
| 2456 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2457 | pbn_oxsemi_4_4000000 }, |
| 2458 | { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ |
| 2459 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2460 | pbn_oxsemi_4_4000000 }, |
| 2461 | { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ |
| 2462 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2463 | pbn_oxsemi_8_4000000 }, |
| 2464 | { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ |
| 2465 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2466 | pbn_oxsemi_8_4000000 }, |
| 2467 | { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ |
| 2468 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2469 | pbn_oxsemi_1_4000000 }, |
| 2470 | { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ |
| 2471 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2472 | pbn_oxsemi_1_4000000 }, |
| 2473 | { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ |
| 2474 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2475 | pbn_oxsemi_1_4000000 }, |
| 2476 | { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ |
| 2477 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2478 | pbn_oxsemi_1_4000000 }, |
| 2479 | { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ |
| 2480 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2481 | pbn_oxsemi_1_4000000 }, |
| 2482 | { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ |
| 2483 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2484 | pbn_oxsemi_1_4000000 }, |
| 2485 | { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ |
| 2486 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2487 | pbn_oxsemi_1_4000000 }, |
| 2488 | { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ |
| 2489 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2490 | pbn_oxsemi_1_4000000 }, |
| 2491 | { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ |
| 2492 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2493 | pbn_oxsemi_1_4000000 }, |
| 2494 | { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ |
| 2495 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2496 | pbn_oxsemi_1_4000000 }, |
| 2497 | { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ |
| 2498 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2499 | pbn_oxsemi_1_4000000 }, |
| 2500 | { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ |
| 2501 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2502 | pbn_oxsemi_1_4000000 }, |
| 2503 | { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ |
| 2504 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2505 | pbn_oxsemi_1_4000000 }, |
| 2506 | { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ |
| 2507 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2508 | pbn_oxsemi_1_4000000 }, |
| 2509 | { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ |
| 2510 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2511 | pbn_oxsemi_1_4000000 }, |
| 2512 | { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ |
| 2513 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2514 | pbn_oxsemi_1_4000000 }, |
| 2515 | { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ |
| 2516 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2517 | pbn_oxsemi_1_4000000 }, |
| 2518 | { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ |
| 2519 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2520 | pbn_oxsemi_1_4000000 }, |
| 2521 | { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ |
| 2522 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2523 | pbn_oxsemi_1_4000000 }, |
| 2524 | { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ |
| 2525 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2526 | pbn_oxsemi_1_4000000 }, |
| 2527 | { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ |
| 2528 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2529 | pbn_oxsemi_1_4000000 }, |
| 2530 | { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ |
| 2531 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2532 | pbn_oxsemi_1_4000000 }, |
| 2533 | { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ |
| 2534 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2535 | pbn_oxsemi_1_4000000 }, |
| 2536 | { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ |
| 2537 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2538 | pbn_oxsemi_1_4000000 }, |
| 2539 | { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ |
| 2540 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2541 | pbn_oxsemi_1_4000000 }, |
| 2542 | { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ |
| 2543 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2544 | pbn_oxsemi_1_4000000 }, |
Lee Howard | b80de36 | 2008-10-21 13:50:14 +0100 | [diff] [blame] | 2545 | /* |
| 2546 | * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado |
| 2547 | */ |
| 2548 | { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ |
| 2549 | PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, |
| 2550 | pbn_oxsemi_1_4000000 }, |
| 2551 | { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ |
| 2552 | PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, |
| 2553 | pbn_oxsemi_2_4000000 }, |
| 2554 | { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ |
| 2555 | PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, |
| 2556 | pbn_oxsemi_4_4000000 }, |
| 2557 | { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ |
| 2558 | PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, |
| 2559 | pbn_oxsemi_8_4000000 }, |
Lee Howard | 7106b4e | 2008-10-21 13:48:58 +0100 | [diff] [blame] | 2560 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2561 | * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, |
| 2562 | * from skokodyn@yahoo.com |
| 2563 | */ |
| 2564 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, |
| 2565 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, |
| 2566 | pbn_sbsxrsio }, |
| 2567 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, |
| 2568 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, |
| 2569 | pbn_sbsxrsio }, |
| 2570 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, |
| 2571 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, |
| 2572 | pbn_sbsxrsio }, |
| 2573 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, |
| 2574 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, |
| 2575 | pbn_sbsxrsio }, |
| 2576 | |
| 2577 | /* |
| 2578 | * Digitan DS560-558, from jimd@esoft.com |
| 2579 | */ |
| 2580 | { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 2581 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2582 | pbn_b1_1_115200 }, |
| 2583 | |
| 2584 | /* |
| 2585 | * Titan Electronic cards |
| 2586 | * The 400L and 800L have a custom setup quirk. |
| 2587 | */ |
| 2588 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 2589 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2590 | pbn_b0_1_921600 }, |
| 2591 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 2592 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2593 | pbn_b0_2_921600 }, |
| 2594 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 2595 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2596 | pbn_b0_4_921600 }, |
| 2597 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, |
Alan Cox | 5756ee9 | 2008-02-08 04:18:51 -0800 | [diff] [blame] | 2598 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2599 | pbn_b0_4_921600 }, |
| 2600 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, |
| 2601 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2602 | pbn_b1_1_921600 }, |
| 2603 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, |
| 2604 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2605 | pbn_b1_bt_2_921600 }, |
| 2606 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, |
| 2607 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2608 | pbn_b0_bt_4_921600 }, |
| 2609 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, |
| 2610 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2611 | pbn_b0_bt_8_921600 }, |
| 2612 | |
| 2613 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, |
| 2614 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2615 | pbn_b2_1_460800 }, |
| 2616 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, |
| 2617 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2618 | pbn_b2_1_460800 }, |
| 2619 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, |
| 2620 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2621 | pbn_b2_1_460800 }, |
| 2622 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, |
| 2623 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2624 | pbn_b2_bt_2_921600 }, |
| 2625 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, |
| 2626 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2627 | pbn_b2_bt_2_921600 }, |
| 2628 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, |
| 2629 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2630 | pbn_b2_bt_2_921600 }, |
| 2631 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, |
| 2632 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2633 | pbn_b2_bt_4_921600 }, |
| 2634 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, |
| 2635 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2636 | pbn_b2_bt_4_921600 }, |
| 2637 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, |
| 2638 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2639 | pbn_b2_bt_4_921600 }, |
| 2640 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, |
| 2641 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2642 | pbn_b0_1_921600 }, |
| 2643 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, |
| 2644 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2645 | pbn_b0_1_921600 }, |
| 2646 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, |
| 2647 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2648 | pbn_b0_1_921600 }, |
| 2649 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, |
| 2650 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2651 | pbn_b0_bt_2_921600 }, |
| 2652 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, |
| 2653 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2654 | pbn_b0_bt_2_921600 }, |
| 2655 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, |
| 2656 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2657 | pbn_b0_bt_2_921600 }, |
| 2658 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, |
| 2659 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2660 | pbn_b0_bt_4_921600 }, |
| 2661 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, |
| 2662 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2663 | pbn_b0_bt_4_921600 }, |
| 2664 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, |
| 2665 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2666 | pbn_b0_bt_4_921600 }, |
Andrey Panin | 3ec9c59 | 2006-02-02 20:15:09 +0000 | [diff] [blame] | 2667 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, |
| 2668 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2669 | pbn_b0_bt_8_921600 }, |
| 2670 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, |
| 2671 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2672 | pbn_b0_bt_8_921600 }, |
| 2673 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, |
| 2674 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2675 | pbn_b0_bt_8_921600 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2676 | |
| 2677 | /* |
| 2678 | * Computone devices submitted by Doug McNash dmcnash@computone.com |
| 2679 | */ |
| 2680 | { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, |
| 2681 | PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, |
| 2682 | 0, 0, pbn_computone_4 }, |
| 2683 | { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, |
| 2684 | PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, |
| 2685 | 0, 0, pbn_computone_8 }, |
| 2686 | { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, |
| 2687 | PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, |
| 2688 | 0, 0, pbn_computone_6 }, |
| 2689 | |
| 2690 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, |
| 2691 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2692 | pbn_oxsemi }, |
| 2693 | { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, |
| 2694 | PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, |
| 2695 | pbn_b0_bt_1_921600 }, |
| 2696 | |
| 2697 | /* |
| 2698 | * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> |
| 2699 | */ |
| 2700 | { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, |
| 2701 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2702 | pbn_b0_bt_8_115200 }, |
| 2703 | { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, |
| 2704 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2705 | pbn_b0_bt_8_115200 }, |
| 2706 | |
| 2707 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, |
| 2708 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2709 | pbn_b0_bt_2_115200 }, |
| 2710 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, |
| 2711 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2712 | pbn_b0_bt_2_115200 }, |
| 2713 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, |
| 2714 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2715 | pbn_b0_bt_2_115200 }, |
| 2716 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, |
| 2717 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2718 | pbn_b0_bt_4_460800 }, |
| 2719 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, |
| 2720 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2721 | pbn_b0_bt_4_460800 }, |
| 2722 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, |
| 2723 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2724 | pbn_b0_bt_2_460800 }, |
| 2725 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, |
| 2726 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2727 | pbn_b0_bt_2_460800 }, |
| 2728 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, |
| 2729 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2730 | pbn_b0_bt_2_460800 }, |
| 2731 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, |
| 2732 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2733 | pbn_b0_bt_1_115200 }, |
| 2734 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, |
| 2735 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2736 | pbn_b0_bt_1_460800 }, |
| 2737 | |
| 2738 | /* |
Russell King | 1fb8cacc | 2006-12-13 14:45:46 +0000 | [diff] [blame] | 2739 | * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). |
| 2740 | * Cards are identified by their subsystem vendor IDs, which |
| 2741 | * (in hex) match the model number. |
| 2742 | * |
| 2743 | * Note that JC140x are RS422/485 cards which require ox950 |
| 2744 | * ACR = 0x10, and as such are not currently fully supported. |
| 2745 | */ |
| 2746 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, |
| 2747 | 0x1204, 0x0004, 0, 0, |
| 2748 | pbn_b0_4_921600 }, |
| 2749 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, |
| 2750 | 0x1208, 0x0004, 0, 0, |
| 2751 | pbn_b0_4_921600 }, |
| 2752 | /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, |
| 2753 | 0x1402, 0x0002, 0, 0, |
| 2754 | pbn_b0_2_921600 }, */ |
| 2755 | /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, |
| 2756 | 0x1404, 0x0004, 0, 0, |
| 2757 | pbn_b0_4_921600 }, */ |
| 2758 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, |
| 2759 | 0x1208, 0x0004, 0, 0, |
| 2760 | pbn_b0_4_921600 }, |
| 2761 | |
| 2762 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2763 | * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com |
| 2764 | */ |
| 2765 | { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, |
| 2766 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2767 | pbn_b1_1_1382400 }, |
| 2768 | |
| 2769 | /* |
| 2770 | * Dell Remote Access Card III - Tim_T_Murphy@Dell.com |
| 2771 | */ |
| 2772 | { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, |
| 2773 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2774 | pbn_b1_1_1382400 }, |
| 2775 | |
| 2776 | /* |
| 2777 | * RAStel 2 port modem, gerg@moreton.com.au |
| 2778 | */ |
| 2779 | { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, |
| 2780 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2781 | pbn_b2_bt_2_115200 }, |
| 2782 | |
| 2783 | /* |
| 2784 | * EKF addition for i960 Boards form EKF with serial port |
| 2785 | */ |
| 2786 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, |
| 2787 | 0xE4BF, PCI_ANY_ID, 0, 0, |
| 2788 | pbn_intel_i960 }, |
| 2789 | |
| 2790 | /* |
| 2791 | * Xircom Cardbus/Ethernet combos |
| 2792 | */ |
| 2793 | { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, |
| 2794 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2795 | pbn_b0_1_115200 }, |
| 2796 | /* |
| 2797 | * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) |
| 2798 | */ |
| 2799 | { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, |
| 2800 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2801 | pbn_b0_1_115200 }, |
| 2802 | |
| 2803 | /* |
| 2804 | * Untested PCI modems, sent in from various folks... |
| 2805 | */ |
| 2806 | |
| 2807 | /* |
| 2808 | * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> |
| 2809 | */ |
| 2810 | { PCI_VENDOR_ID_ROCKWELL, 0x1004, |
| 2811 | 0x1048, 0x1500, 0, 0, |
| 2812 | pbn_b1_1_115200 }, |
| 2813 | |
| 2814 | { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, |
| 2815 | 0xFF00, 0, 0, 0, |
| 2816 | pbn_sgi_ioc3 }, |
| 2817 | |
| 2818 | /* |
| 2819 | * HP Diva card |
| 2820 | */ |
| 2821 | { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, |
| 2822 | PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, |
| 2823 | pbn_b1_1_115200 }, |
| 2824 | { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, |
| 2825 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2826 | pbn_b0_5_115200 }, |
| 2827 | { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, |
| 2828 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2829 | pbn_b2_1_115200 }, |
| 2830 | |
Alon Bar-Lev | d9004eb | 2006-01-18 11:47:33 +0000 | [diff] [blame] | 2831 | { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, |
| 2832 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2833 | pbn_b3_2_115200 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2834 | { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, |
| 2835 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2836 | pbn_b3_4_115200 }, |
| 2837 | { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, |
| 2838 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2839 | pbn_b3_8_115200 }, |
| 2840 | |
| 2841 | /* |
| 2842 | * Exar Corp. XR17C15[248] Dual/Quad/Octal UART |
| 2843 | */ |
| 2844 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, |
| 2845 | PCI_ANY_ID, PCI_ANY_ID, |
| 2846 | 0, |
| 2847 | 0, pbn_exar_XR17C152 }, |
| 2848 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, |
| 2849 | PCI_ANY_ID, PCI_ANY_ID, |
| 2850 | 0, |
| 2851 | 0, pbn_exar_XR17C154 }, |
| 2852 | { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, |
| 2853 | PCI_ANY_ID, PCI_ANY_ID, |
| 2854 | 0, |
| 2855 | 0, pbn_exar_XR17C158 }, |
| 2856 | |
| 2857 | /* |
| 2858 | * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) |
| 2859 | */ |
| 2860 | { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, |
| 2861 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 2862 | pbn_b0_1_115200 }, |
Niels de Vos | 84f8c6f | 2007-08-22 14:01:14 -0700 | [diff] [blame] | 2863 | /* |
| 2864 | * ITE |
| 2865 | */ |
| 2866 | { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, |
| 2867 | PCI_ANY_ID, PCI_ANY_ID, |
| 2868 | 0, 0, |
| 2869 | pbn_b1_bt_1_115200 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2870 | |
| 2871 | /* |
Peter Horton | 737c175 | 2006-08-26 09:07:36 +0100 | [diff] [blame] | 2872 | * IntaShield IS-200 |
| 2873 | */ |
| 2874 | { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, |
| 2875 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ |
| 2876 | pbn_b2_2_115200 }, |
Ignacio GarcÃa Pérez | 4b6f6ce | 2008-05-23 13:04:28 -0700 | [diff] [blame] | 2877 | /* |
| 2878 | * IntaShield IS-400 |
| 2879 | */ |
| 2880 | { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, |
| 2881 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ |
| 2882 | pbn_b2_4_115200 }, |
Peter Horton | 737c175 | 2006-08-26 09:07:36 +0100 | [diff] [blame] | 2883 | /* |
Thomas Hoehn | 4821200 | 2007-02-10 01:46:05 -0800 | [diff] [blame] | 2884 | * Perle PCI-RAS cards |
| 2885 | */ |
| 2886 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, |
| 2887 | PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, |
| 2888 | 0, 0, pbn_b2_4_921600 }, |
| 2889 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, |
| 2890 | PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, |
| 2891 | 0, 0, pbn_b2_8_921600 }, |
Alan Cox | bf0df63 | 2007-10-16 01:24:00 -0700 | [diff] [blame] | 2892 | |
| 2893 | /* |
| 2894 | * Mainpine series cards: Fairly standard layout but fools |
| 2895 | * parts of the autodetect in some cases and uses otherwise |
| 2896 | * unmatched communications subclasses in the PCI Express case |
| 2897 | */ |
| 2898 | |
| 2899 | { /* RockForceDUO */ |
| 2900 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2901 | PCI_VENDOR_ID_MAINPINE, 0x0200, |
| 2902 | 0, 0, pbn_b0_2_115200 }, |
| 2903 | { /* RockForceQUATRO */ |
| 2904 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2905 | PCI_VENDOR_ID_MAINPINE, 0x0300, |
| 2906 | 0, 0, pbn_b0_4_115200 }, |
| 2907 | { /* RockForceDUO+ */ |
| 2908 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2909 | PCI_VENDOR_ID_MAINPINE, 0x0400, |
| 2910 | 0, 0, pbn_b0_2_115200 }, |
| 2911 | { /* RockForceQUATRO+ */ |
| 2912 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2913 | PCI_VENDOR_ID_MAINPINE, 0x0500, |
| 2914 | 0, 0, pbn_b0_4_115200 }, |
| 2915 | { /* RockForce+ */ |
| 2916 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2917 | PCI_VENDOR_ID_MAINPINE, 0x0600, |
| 2918 | 0, 0, pbn_b0_2_115200 }, |
| 2919 | { /* RockForce+ */ |
| 2920 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2921 | PCI_VENDOR_ID_MAINPINE, 0x0700, |
| 2922 | 0, 0, pbn_b0_4_115200 }, |
| 2923 | { /* RockForceOCTO+ */ |
| 2924 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2925 | PCI_VENDOR_ID_MAINPINE, 0x0800, |
| 2926 | 0, 0, pbn_b0_8_115200 }, |
| 2927 | { /* RockForceDUO+ */ |
| 2928 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2929 | PCI_VENDOR_ID_MAINPINE, 0x0C00, |
| 2930 | 0, 0, pbn_b0_2_115200 }, |
| 2931 | { /* RockForceQUARTRO+ */ |
| 2932 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2933 | PCI_VENDOR_ID_MAINPINE, 0x0D00, |
| 2934 | 0, 0, pbn_b0_4_115200 }, |
| 2935 | { /* RockForceOCTO+ */ |
| 2936 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2937 | PCI_VENDOR_ID_MAINPINE, 0x1D00, |
| 2938 | 0, 0, pbn_b0_8_115200 }, |
| 2939 | { /* RockForceD1 */ |
| 2940 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2941 | PCI_VENDOR_ID_MAINPINE, 0x2000, |
| 2942 | 0, 0, pbn_b0_1_115200 }, |
| 2943 | { /* RockForceF1 */ |
| 2944 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2945 | PCI_VENDOR_ID_MAINPINE, 0x2100, |
| 2946 | 0, 0, pbn_b0_1_115200 }, |
| 2947 | { /* RockForceD2 */ |
| 2948 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2949 | PCI_VENDOR_ID_MAINPINE, 0x2200, |
| 2950 | 0, 0, pbn_b0_2_115200 }, |
| 2951 | { /* RockForceF2 */ |
| 2952 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2953 | PCI_VENDOR_ID_MAINPINE, 0x2300, |
| 2954 | 0, 0, pbn_b0_2_115200 }, |
| 2955 | { /* RockForceD4 */ |
| 2956 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2957 | PCI_VENDOR_ID_MAINPINE, 0x2400, |
| 2958 | 0, 0, pbn_b0_4_115200 }, |
| 2959 | { /* RockForceF4 */ |
| 2960 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2961 | PCI_VENDOR_ID_MAINPINE, 0x2500, |
| 2962 | 0, 0, pbn_b0_4_115200 }, |
| 2963 | { /* RockForceD8 */ |
| 2964 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2965 | PCI_VENDOR_ID_MAINPINE, 0x2600, |
| 2966 | 0, 0, pbn_b0_8_115200 }, |
| 2967 | { /* RockForceF8 */ |
| 2968 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2969 | PCI_VENDOR_ID_MAINPINE, 0x2700, |
| 2970 | 0, 0, pbn_b0_8_115200 }, |
| 2971 | { /* IQ Express D1 */ |
| 2972 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2973 | PCI_VENDOR_ID_MAINPINE, 0x3000, |
| 2974 | 0, 0, pbn_b0_1_115200 }, |
| 2975 | { /* IQ Express F1 */ |
| 2976 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2977 | PCI_VENDOR_ID_MAINPINE, 0x3100, |
| 2978 | 0, 0, pbn_b0_1_115200 }, |
| 2979 | { /* IQ Express D2 */ |
| 2980 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2981 | PCI_VENDOR_ID_MAINPINE, 0x3200, |
| 2982 | 0, 0, pbn_b0_2_115200 }, |
| 2983 | { /* IQ Express F2 */ |
| 2984 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2985 | PCI_VENDOR_ID_MAINPINE, 0x3300, |
| 2986 | 0, 0, pbn_b0_2_115200 }, |
| 2987 | { /* IQ Express D4 */ |
| 2988 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2989 | PCI_VENDOR_ID_MAINPINE, 0x3400, |
| 2990 | 0, 0, pbn_b0_4_115200 }, |
| 2991 | { /* IQ Express F4 */ |
| 2992 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2993 | PCI_VENDOR_ID_MAINPINE, 0x3500, |
| 2994 | 0, 0, pbn_b0_4_115200 }, |
| 2995 | { /* IQ Express D8 */ |
| 2996 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 2997 | PCI_VENDOR_ID_MAINPINE, 0x3C00, |
| 2998 | 0, 0, pbn_b0_8_115200 }, |
| 2999 | { /* IQ Express F8 */ |
| 3000 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, |
| 3001 | PCI_VENDOR_ID_MAINPINE, 0x3D00, |
| 3002 | 0, 0, pbn_b0_8_115200 }, |
| 3003 | |
| 3004 | |
Thomas Hoehn | 4821200 | 2007-02-10 01:46:05 -0800 | [diff] [blame] | 3005 | /* |
Olof Johansson | aa79850 | 2007-08-22 14:01:55 -0700 | [diff] [blame] | 3006 | * PA Semi PA6T-1682M on-chip UART |
| 3007 | */ |
| 3008 | { PCI_VENDOR_ID_PASEMI, 0xa004, |
| 3009 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 3010 | pbn_pasemi_1682M }, |
| 3011 | |
| 3012 | /* |
Krauth.Julien | 02c9b5c | 2008-02-04 22:27:49 -0800 | [diff] [blame] | 3013 | * ADDI-DATA GmbH communication cards <info@addi-data.com> |
| 3014 | */ |
| 3015 | { PCI_VENDOR_ID_ADDIDATA, |
| 3016 | PCI_DEVICE_ID_ADDIDATA_APCI7500, |
| 3017 | PCI_ANY_ID, |
| 3018 | PCI_ANY_ID, |
| 3019 | 0, |
| 3020 | 0, |
| 3021 | pbn_b0_4_115200 }, |
| 3022 | |
| 3023 | { PCI_VENDOR_ID_ADDIDATA, |
| 3024 | PCI_DEVICE_ID_ADDIDATA_APCI7420, |
| 3025 | PCI_ANY_ID, |
| 3026 | PCI_ANY_ID, |
| 3027 | 0, |
| 3028 | 0, |
| 3029 | pbn_b0_2_115200 }, |
| 3030 | |
| 3031 | { PCI_VENDOR_ID_ADDIDATA, |
| 3032 | PCI_DEVICE_ID_ADDIDATA_APCI7300, |
| 3033 | PCI_ANY_ID, |
| 3034 | PCI_ANY_ID, |
| 3035 | 0, |
| 3036 | 0, |
| 3037 | pbn_b0_1_115200 }, |
| 3038 | |
| 3039 | { PCI_VENDOR_ID_ADDIDATA_OLD, |
| 3040 | PCI_DEVICE_ID_ADDIDATA_APCI7800, |
| 3041 | PCI_ANY_ID, |
| 3042 | PCI_ANY_ID, |
| 3043 | 0, |
| 3044 | 0, |
| 3045 | pbn_b1_8_115200 }, |
| 3046 | |
| 3047 | { PCI_VENDOR_ID_ADDIDATA, |
| 3048 | PCI_DEVICE_ID_ADDIDATA_APCI7500_2, |
| 3049 | PCI_ANY_ID, |
| 3050 | PCI_ANY_ID, |
| 3051 | 0, |
| 3052 | 0, |
| 3053 | pbn_b0_4_115200 }, |
| 3054 | |
| 3055 | { PCI_VENDOR_ID_ADDIDATA, |
| 3056 | PCI_DEVICE_ID_ADDIDATA_APCI7420_2, |
| 3057 | PCI_ANY_ID, |
| 3058 | PCI_ANY_ID, |
| 3059 | 0, |
| 3060 | 0, |
| 3061 | pbn_b0_2_115200 }, |
| 3062 | |
| 3063 | { PCI_VENDOR_ID_ADDIDATA, |
| 3064 | PCI_DEVICE_ID_ADDIDATA_APCI7300_2, |
| 3065 | PCI_ANY_ID, |
| 3066 | PCI_ANY_ID, |
| 3067 | 0, |
| 3068 | 0, |
| 3069 | pbn_b0_1_115200 }, |
| 3070 | |
| 3071 | { PCI_VENDOR_ID_ADDIDATA, |
| 3072 | PCI_DEVICE_ID_ADDIDATA_APCI7500_3, |
| 3073 | PCI_ANY_ID, |
| 3074 | PCI_ANY_ID, |
| 3075 | 0, |
| 3076 | 0, |
| 3077 | pbn_b0_4_115200 }, |
| 3078 | |
| 3079 | { PCI_VENDOR_ID_ADDIDATA, |
| 3080 | PCI_DEVICE_ID_ADDIDATA_APCI7420_3, |
| 3081 | PCI_ANY_ID, |
| 3082 | PCI_ANY_ID, |
| 3083 | 0, |
| 3084 | 0, |
| 3085 | pbn_b0_2_115200 }, |
| 3086 | |
| 3087 | { PCI_VENDOR_ID_ADDIDATA, |
| 3088 | PCI_DEVICE_ID_ADDIDATA_APCI7300_3, |
| 3089 | PCI_ANY_ID, |
| 3090 | PCI_ANY_ID, |
| 3091 | 0, |
| 3092 | 0, |
| 3093 | pbn_b0_1_115200 }, |
| 3094 | |
| 3095 | { PCI_VENDOR_ID_ADDIDATA, |
| 3096 | PCI_DEVICE_ID_ADDIDATA_APCI7800_3, |
| 3097 | PCI_ANY_ID, |
| 3098 | PCI_ANY_ID, |
| 3099 | 0, |
| 3100 | 0, |
| 3101 | pbn_b0_8_115200 }, |
| 3102 | |
Jiri Slaby | 25cf9bc | 2009-01-15 13:30:34 +0000 | [diff] [blame^] | 3103 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, |
| 3104 | PCI_VENDOR_ID_IBM, 0x0299, |
| 3105 | 0, 0, pbn_b0_bt_2_115200 }, |
| 3106 | |
Krauth.Julien | 02c9b5c | 2008-02-04 22:27:49 -0800 | [diff] [blame] | 3107 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3108 | * These entries match devices with class COMMUNICATION_SERIAL, |
| 3109 | * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL |
| 3110 | */ |
| 3111 | { PCI_ANY_ID, PCI_ANY_ID, |
| 3112 | PCI_ANY_ID, PCI_ANY_ID, |
| 3113 | PCI_CLASS_COMMUNICATION_SERIAL << 8, |
| 3114 | 0xffff00, pbn_default }, |
| 3115 | { PCI_ANY_ID, PCI_ANY_ID, |
| 3116 | PCI_ANY_ID, PCI_ANY_ID, |
| 3117 | PCI_CLASS_COMMUNICATION_MODEM << 8, |
| 3118 | 0xffff00, pbn_default }, |
| 3119 | { PCI_ANY_ID, PCI_ANY_ID, |
| 3120 | PCI_ANY_ID, PCI_ANY_ID, |
| 3121 | PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, |
| 3122 | 0xffff00, pbn_default }, |
| 3123 | { 0, } |
| 3124 | }; |
| 3125 | |
| 3126 | static struct pci_driver serial_pci_driver = { |
| 3127 | .name = "serial", |
| 3128 | .probe = pciserial_init_one, |
| 3129 | .remove = __devexit_p(pciserial_remove_one), |
Alexey Dobriyan | 1d5e799 | 2006-09-25 16:51:27 -0700 | [diff] [blame] | 3130 | #ifdef CONFIG_PM |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3131 | .suspend = pciserial_suspend_one, |
| 3132 | .resume = pciserial_resume_one, |
Alexey Dobriyan | 1d5e799 | 2006-09-25 16:51:27 -0700 | [diff] [blame] | 3133 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3134 | .id_table = serial_pci_tbl, |
| 3135 | }; |
| 3136 | |
| 3137 | static int __init serial8250_pci_init(void) |
| 3138 | { |
| 3139 | return pci_register_driver(&serial_pci_driver); |
| 3140 | } |
| 3141 | |
| 3142 | static void __exit serial8250_pci_exit(void) |
| 3143 | { |
| 3144 | pci_unregister_driver(&serial_pci_driver); |
| 3145 | } |
| 3146 | |
| 3147 | module_init(serial8250_pci_init); |
| 3148 | module_exit(serial8250_pci_exit); |
| 3149 | |
| 3150 | MODULE_LICENSE("GPL"); |
| 3151 | MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); |
| 3152 | MODULE_DEVICE_TABLE(pci, serial_pci_tbl); |