blob: 32501f6ec991169917af2446db4acbd37f8fbba0 [file] [log] [blame]
Dave Airlie746c1aa2009-12-08 07:07:28 +10001/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
Jerome Glisse8d1c7022012-07-17 17:17:16 -040025 * Jerome Glisse
Dave Airlie746c1aa2009-12-08 07:07:28 +100026 */
David Howells760285e2012-10-02 18:01:07 +010027#include <drm/drmP.h>
28#include <drm/radeon_drm.h>
Dave Airlie746c1aa2009-12-08 07:07:28 +100029#include "radeon.h"
30
31#include "atom.h"
32#include "atom-bits.h"
David Howells760285e2012-10-02 18:01:07 +010033#include <drm/drm_dp_helper.h>
Dave Airlie746c1aa2009-12-08 07:07:28 +100034
Alex Deucherf92a8b62009-11-23 18:40:40 -050035/* move these to drm_dp_helper.c/h */
Alex Deucher5801ead2009-11-24 13:32:59 -050036#define DP_LINK_CONFIGURATION_SIZE 9
Daniel Vetter1a644cd2012-10-18 15:32:40 +020037#define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
Alex Deucher5801ead2009-11-24 13:32:59 -050038
39static char *voltage_names[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
41};
42static char *pre_emph_names[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
44};
Alex Deucherf92a8b62009-11-23 18:40:40 -050045
Alex Deucher224d94b2011-05-20 04:34:28 -040046/***** radeon AUX functions *****/
Alex Deucher34be8c92013-07-18 11:13:53 -040047
48/* Atom needs data in little endian format
49 * so swap as appropriate when copying data to
50 * or from atom. Note that atom operates on
51 * dw units.
52 */
53static void radeon_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
54{
55#ifdef __BIG_ENDIAN
56 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
57 u32 *dst32, *src32;
58 int i;
59
60 memcpy(src_tmp, src, num_bytes);
61 src32 = (u32 *)src_tmp;
62 dst32 = (u32 *)dst_tmp;
63 if (to_le) {
64 for (i = 0; i < ((num_bytes + 3) / 4); i++)
65 dst32[i] = cpu_to_le32(src32[i]);
66 memcpy(dst, dst_tmp, num_bytes);
67 } else {
68 u8 dws = num_bytes & ~3;
69 for (i = 0; i < ((num_bytes + 3) / 4); i++)
70 dst32[i] = le32_to_cpu(src32[i]);
71 memcpy(dst, dst_tmp, dws);
72 if (num_bytes % 4) {
73 for (i = 0; i < (num_bytes % 4); i++)
74 dst[dws+i] = dst_tmp[dws+i];
75 }
76 }
77#else
78 memcpy(dst, src, num_bytes);
79#endif
80}
81
Alex Deucherbcc1c2a2010-01-12 17:54:34 -050082union aux_channel_transaction {
83 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
84 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
85};
Alex Deucher5801ead2009-11-24 13:32:59 -050086
Alex Deucher834b2902011-05-20 04:34:24 -040087static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
88 u8 *send, int send_bytes,
89 u8 *recv, int recv_size,
90 u8 delay, u8 *ack)
Dave Airlie746c1aa2009-12-08 07:07:28 +100091{
92 struct drm_device *dev = chan->dev;
93 struct radeon_device *rdev = dev->dev_private;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -050094 union aux_channel_transaction args;
Dave Airlie746c1aa2009-12-08 07:07:28 +100095 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
96 unsigned char *base;
Alex Deucher834b2902011-05-20 04:34:24 -040097 int recv_bytes;
Alex Deucher1a66c952009-11-20 19:40:13 -050098
Dave Airlie746c1aa2009-12-08 07:07:28 +100099 memset(&args, 0, sizeof(args));
Alex Deucher1a66c952009-11-20 19:40:13 -0500100
Alex Deucher97412a72012-03-20 17:18:06 -0400101 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
Dave Airlie746c1aa2009-12-08 07:07:28 +1000102
Alex Deucher34be8c92013-07-18 11:13:53 -0400103 radeon_copy_swap(base, send, send_bytes, true);
Dave Airlie746c1aa2009-12-08 07:07:28 +1000104
Alex Deucher34be8c92013-07-18 11:13:53 -0400105 args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
106 args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500107 args.v1.ucDataOutLen = 0;
108 args.v1.ucChannelID = chan->rec.i2c_id;
109 args.v1.ucDelay = delay / 10;
110 if (ASIC_IS_DCE4(rdev))
Alex Deucher8e36ed02010-05-18 19:26:47 -0400111 args.v2.ucHPD_ID = chan->rec.hpd;
Dave Airlie746c1aa2009-12-08 07:07:28 +1000112
113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
114
Alex Deucher834b2902011-05-20 04:34:24 -0400115 *ack = args.v1.ucReplyStatus;
116
117 /* timeout */
118 if (args.v1.ucReplyStatus == 1) {
119 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
120 return -ETIMEDOUT;
Dave Airlie746c1aa2009-12-08 07:07:28 +1000121 }
122
Alex Deucher834b2902011-05-20 04:34:24 -0400123 /* flags not zero */
124 if (args.v1.ucReplyStatus == 2) {
125 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
126 return -EBUSY;
Dave Airlie746c1aa2009-12-08 07:07:28 +1000127 }
Alex Deucher834b2902011-05-20 04:34:24 -0400128
129 /* error */
130 if (args.v1.ucReplyStatus == 3) {
131 DRM_DEBUG_KMS("dp_aux_ch error\n");
132 return -EIO;
133 }
134
135 recv_bytes = args.v1.ucDataOutLen;
136 if (recv_bytes > recv_size)
137 recv_bytes = recv_size;
138
139 if (recv && recv_size)
Alex Deucher34be8c92013-07-18 11:13:53 -0400140 radeon_copy_swap(recv, base + 16, recv_bytes, false);
Alex Deucher834b2902011-05-20 04:34:24 -0400141
142 return recv_bytes;
Dave Airlie746c1aa2009-12-08 07:07:28 +1000143}
144
Alex Deucher834b2902011-05-20 04:34:24 -0400145static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
146 u16 address, u8 *send, u8 send_bytes, u8 delay)
Alex Deucher5801ead2009-11-24 13:32:59 -0500147{
148 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
Alex Deucher834b2902011-05-20 04:34:24 -0400149 int ret;
Alex Deucher5801ead2009-11-24 13:32:59 -0500150 u8 msg[20];
Alex Deucher834b2902011-05-20 04:34:24 -0400151 int msg_bytes = send_bytes + 4;
152 u8 ack;
Alex Deucher6375bda2011-10-03 09:13:46 -0400153 unsigned retry;
Alex Deucher5801ead2009-11-24 13:32:59 -0500154
Alex Deucher834b2902011-05-20 04:34:24 -0400155 if (send_bytes > 16)
156 return -1;
157
Alex Deucher5801ead2009-11-24 13:32:59 -0500158 msg[0] = address;
159 msg[1] = address >> 8;
160 msg[2] = AUX_NATIVE_WRITE << 4;
Alex Deucher834b2902011-05-20 04:34:24 -0400161 msg[3] = (msg_bytes << 4) | (send_bytes - 1);
Alex Deucher5801ead2009-11-24 13:32:59 -0500162 memcpy(&msg[4], send, send_bytes);
Alex Deucher834b2902011-05-20 04:34:24 -0400163
Alex Deucher6375bda2011-10-03 09:13:46 -0400164 for (retry = 0; retry < 4; retry++) {
Alex Deucher834b2902011-05-20 04:34:24 -0400165 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
166 msg, msg_bytes, NULL, 0, delay, &ack);
Alex Deucher4f332842011-10-04 17:23:15 -0400167 if (ret == -EBUSY)
168 continue;
169 else if (ret < 0)
Alex Deucher834b2902011-05-20 04:34:24 -0400170 return ret;
171 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
Alex Deucher6375bda2011-10-03 09:13:46 -0400172 return send_bytes;
Alex Deucher834b2902011-05-20 04:34:24 -0400173 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
174 udelay(400);
175 else
176 return -EIO;
177 }
178
Alex Deucher6375bda2011-10-03 09:13:46 -0400179 return -EIO;
Alex Deucher5801ead2009-11-24 13:32:59 -0500180}
181
Alex Deucher834b2902011-05-20 04:34:24 -0400182static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
183 u16 address, u8 *recv, int recv_bytes, u8 delay)
Alex Deucher5801ead2009-11-24 13:32:59 -0500184{
185 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
Alex Deucher834b2902011-05-20 04:34:24 -0400186 u8 msg[4];
187 int msg_bytes = 4;
188 u8 ack;
189 int ret;
Alex Deucher6375bda2011-10-03 09:13:46 -0400190 unsigned retry;
Alex Deucher834b2902011-05-20 04:34:24 -0400191
Alex Deucher5801ead2009-11-24 13:32:59 -0500192 msg[0] = address;
193 msg[1] = address >> 8;
194 msg[2] = AUX_NATIVE_READ << 4;
Alex Deucher834b2902011-05-20 04:34:24 -0400195 msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
Alex Deucher5801ead2009-11-24 13:32:59 -0500196
Alex Deucher6375bda2011-10-03 09:13:46 -0400197 for (retry = 0; retry < 4; retry++) {
Alex Deucher834b2902011-05-20 04:34:24 -0400198 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
199 msg, msg_bytes, recv, recv_bytes, delay, &ack);
Alex Deucher4f332842011-10-04 17:23:15 -0400200 if (ret == -EBUSY)
201 continue;
202 else if (ret < 0)
Alex Deucher834b2902011-05-20 04:34:24 -0400203 return ret;
204 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
205 return ret;
206 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
207 udelay(400);
Alex Deucher109bc102011-10-03 09:13:45 -0400208 else if (ret == 0)
209 return -EPROTO;
Alex Deucher834b2902011-05-20 04:34:24 -0400210 else
211 return -EIO;
212 }
Alex Deucher6375bda2011-10-03 09:13:46 -0400213
214 return -EIO;
Alex Deucher5801ead2009-11-24 13:32:59 -0500215}
216
Alex Deucher224d94b2011-05-20 04:34:28 -0400217static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
218 u16 reg, u8 val)
Dave Airlie746c1aa2009-12-08 07:07:28 +1000219{
Alex Deucher224d94b2011-05-20 04:34:28 -0400220 radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0);
Dave Airlie746c1aa2009-12-08 07:07:28 +1000221}
222
Alex Deucher224d94b2011-05-20 04:34:28 -0400223static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector,
224 u16 reg)
Dave Airlie746c1aa2009-12-08 07:07:28 +1000225{
Alex Deucher224d94b2011-05-20 04:34:28 -0400226 u8 val = 0;
Dave Airlie746c1aa2009-12-08 07:07:28 +1000227
Alex Deucher224d94b2011-05-20 04:34:28 -0400228 radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0);
Dave Airlie746c1aa2009-12-08 07:07:28 +1000229
Alex Deucher224d94b2011-05-20 04:34:28 -0400230 return val;
Alex Deucher5801ead2009-11-24 13:32:59 -0500231}
232
Dave Airlie746c1aa2009-12-08 07:07:28 +1000233int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
Alex Deucher834b2902011-05-20 04:34:24 -0400234 u8 write_byte, u8 *read_byte)
Dave Airlie746c1aa2009-12-08 07:07:28 +1000235{
236 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
237 struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
Alex Deucher834b2902011-05-20 04:34:24 -0400238 u16 address = algo_data->address;
239 u8 msg[5];
240 u8 reply[2];
241 unsigned retry;
242 int msg_bytes;
243 int reply_bytes = 1;
244 int ret;
245 u8 ack;
Dave Airlie746c1aa2009-12-08 07:07:28 +1000246
247 /* Set up the command byte */
248 if (mode & MODE_I2C_READ)
249 msg[2] = AUX_I2C_READ << 4;
250 else
251 msg[2] = AUX_I2C_WRITE << 4;
252
253 if (!(mode & MODE_I2C_STOP))
254 msg[2] |= AUX_I2C_MOT << 4;
255
256 msg[0] = address;
257 msg[1] = address >> 8;
258
Dave Airlie746c1aa2009-12-08 07:07:28 +1000259 switch (mode) {
260 case MODE_I2C_WRITE:
Alex Deucher834b2902011-05-20 04:34:24 -0400261 msg_bytes = 5;
262 msg[3] = msg_bytes << 4;
Dave Airlie746c1aa2009-12-08 07:07:28 +1000263 msg[4] = write_byte;
Dave Airlie746c1aa2009-12-08 07:07:28 +1000264 break;
265 case MODE_I2C_READ:
Alex Deucher834b2902011-05-20 04:34:24 -0400266 msg_bytes = 4;
267 msg[3] = msg_bytes << 4;
Dave Airlie746c1aa2009-12-08 07:07:28 +1000268 break;
269 default:
Alex Deucher834b2902011-05-20 04:34:24 -0400270 msg_bytes = 4;
271 msg[3] = 3 << 4;
Dave Airlie746c1aa2009-12-08 07:07:28 +1000272 break;
273 }
274
Alex Deucher834b2902011-05-20 04:34:24 -0400275 for (retry = 0; retry < 4; retry++) {
276 ret = radeon_process_aux_ch(auxch,
277 msg, msg_bytes, reply, reply_bytes, 0, &ack);
Alex Deucher4f332842011-10-04 17:23:15 -0400278 if (ret == -EBUSY)
279 continue;
280 else if (ret < 0) {
Alex Deucher834b2902011-05-20 04:34:24 -0400281 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
282 return ret;
283 }
Dave Airlie746c1aa2009-12-08 07:07:28 +1000284
Alex Deucher834b2902011-05-20 04:34:24 -0400285 switch (ack & AUX_NATIVE_REPLY_MASK) {
286 case AUX_NATIVE_REPLY_ACK:
287 /* I2C-over-AUX Reply field is only valid
288 * when paired with AUX ACK.
289 */
290 break;
291 case AUX_NATIVE_REPLY_NACK:
292 DRM_DEBUG_KMS("aux_ch native nack\n");
293 return -EREMOTEIO;
294 case AUX_NATIVE_REPLY_DEFER:
295 DRM_DEBUG_KMS("aux_ch native defer\n");
296 udelay(400);
297 continue;
298 default:
299 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
300 return -EREMOTEIO;
301 }
302
303 switch (ack & AUX_I2C_REPLY_MASK) {
304 case AUX_I2C_REPLY_ACK:
305 if (mode == MODE_I2C_READ)
306 *read_byte = reply[0];
307 return ret;
308 case AUX_I2C_REPLY_NACK:
309 DRM_DEBUG_KMS("aux_i2c nack\n");
310 return -EREMOTEIO;
311 case AUX_I2C_REPLY_DEFER:
312 DRM_DEBUG_KMS("aux_i2c defer\n");
313 udelay(400);
314 break;
315 default:
316 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
317 return -EREMOTEIO;
318 }
Dave Airlie746c1aa2009-12-08 07:07:28 +1000319 }
Alex Deucher834b2902011-05-20 04:34:24 -0400320
Alex Deucher091264f2011-11-08 10:09:58 -0500321 DRM_DEBUG_KMS("aux i2c too many retries, giving up\n");
Dave Airlie746c1aa2009-12-08 07:07:28 +1000322 return -EREMOTEIO;
323}
Alex Deucher5801ead2009-11-24 13:32:59 -0500324
Alex Deucher224d94b2011-05-20 04:34:28 -0400325/***** general DP utility functions *****/
326
Alex Deucher224d94b2011-05-20 04:34:28 -0400327#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
328#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
329
330static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
331 int lane_count,
332 u8 train_set[4])
333{
334 u8 v = 0;
335 u8 p = 0;
336 int lane;
337
338 for (lane = 0; lane < lane_count; lane++) {
Daniel Vetter0f037bd2012-10-18 10:15:27 +0200339 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
340 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
Alex Deucher224d94b2011-05-20 04:34:28 -0400341
342 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
343 lane,
344 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
345 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
346
347 if (this_v > v)
348 v = this_v;
349 if (this_p > p)
350 p = this_p;
351 }
352
353 if (v >= DP_VOLTAGE_MAX)
354 v |= DP_TRAIN_MAX_SWING_REACHED;
355
356 if (p >= DP_PRE_EMPHASIS_MAX)
357 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
358
359 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
360 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
361 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
362
363 for (lane = 0; lane < 4; lane++)
364 train_set[lane] = v | p;
365}
366
367/* convert bits per color to bits per pixel */
368/* get bpc from the EDID */
369static int convert_bpc_to_bpp(int bpc)
370{
371 if (bpc == 0)
372 return 24;
373 else
374 return bpc * 3;
375}
376
377/* get the max pix clock supported by the link rate and lane num */
378static int dp_get_max_dp_pix_clock(int link_rate,
379 int lane_num,
380 int bpp)
381{
382 return (link_rate * lane_num * 8) / bpp;
383}
384
Alex Deucher224d94b2011-05-20 04:34:28 -0400385/***** radeon specific DP functions *****/
386
387/* First get the min lane# when low rate is used according to pixel clock
388 * (prefer low rate), second check max lane# supported by DP panel,
389 * if the max lane# < low rate lane# then use max lane# instead.
390 */
391static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
392 u8 dpcd[DP_DPCD_SIZE],
393 int pix_clock)
394{
Alex Deuchereccea792012-03-26 15:12:54 -0400395 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
Daniel Vetter3b5c6622012-10-18 10:15:31 +0200396 int max_link_rate = drm_dp_max_link_rate(dpcd);
Daniel Vetter397fe152012-10-22 22:56:43 +0200397 int max_lane_num = drm_dp_max_lane_count(dpcd);
Alex Deucher224d94b2011-05-20 04:34:28 -0400398 int lane_num;
399 int max_dp_pix_clock;
400
401 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
402 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
403 if (pix_clock <= max_dp_pix_clock)
404 break;
405 }
406
407 return lane_num;
408}
409
410static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
411 u8 dpcd[DP_DPCD_SIZE],
412 int pix_clock)
413{
Alex Deuchereccea792012-03-26 15:12:54 -0400414 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
Alex Deucher224d94b2011-05-20 04:34:28 -0400415 int lane_num, max_pix_clock;
416
Alex Deucherfdca78c2011-10-25 11:54:52 -0400417 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
418 ENCODER_OBJECT_ID_NUTMEG)
Alex Deucher224d94b2011-05-20 04:34:28 -0400419 return 270000;
420
421 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
422 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
423 if (pix_clock <= max_pix_clock)
424 return 162000;
425 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
426 if (pix_clock <= max_pix_clock)
427 return 270000;
428 if (radeon_connector_is_dp12_capable(connector)) {
429 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
430 if (pix_clock <= max_pix_clock)
431 return 540000;
432 }
433
Daniel Vetter3b5c6622012-10-18 10:15:31 +0200434 return drm_dp_max_link_rate(dpcd);
Alex Deucher224d94b2011-05-20 04:34:28 -0400435}
436
437static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
438 int action, int dp_clock,
439 u8 ucconfig, u8 lane_num)
440{
441 DP_ENCODER_SERVICE_PARAMETERS args;
442 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
443
444 memset(&args, 0, sizeof(args));
445 args.ucLinkClock = dp_clock / 10;
446 args.ucConfig = ucconfig;
447 args.ucAction = action;
448 args.ucLaneNum = lane_num;
449 args.ucStatus = 0;
450
451 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
452 return args.ucStatus;
453}
454
455u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
456{
457 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
458 struct drm_device *dev = radeon_connector->base.dev;
459 struct radeon_device *rdev = dev->dev_private;
460
461 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
462 dig_connector->dp_i2c_bus->rec.i2c_id, 0);
463}
464
Adam Jackson40c5d872012-05-14 16:05:48 -0400465static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
466{
467 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
468 u8 buf[3];
469
470 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
471 return;
472
473 if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0))
474 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
475 buf[0], buf[1], buf[2]);
476
477 if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0))
478 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
479 buf[0], buf[1], buf[2]);
480}
481
Alex Deucher224d94b2011-05-20 04:34:28 -0400482bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
483{
484 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
Daniel Vetter1a644cd2012-10-18 15:32:40 +0200485 u8 msg[DP_DPCD_SIZE];
Alex Deucher224d94b2011-05-20 04:34:28 -0400486 int ret, i;
487
Daniel Vetter1a644cd2012-10-18 15:32:40 +0200488 ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg,
489 DP_DPCD_SIZE, 0);
Alex Deucher224d94b2011-05-20 04:34:28 -0400490 if (ret > 0) {
Daniel Vetter1a644cd2012-10-18 15:32:40 +0200491 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
Alex Deucher224d94b2011-05-20 04:34:28 -0400492 DRM_DEBUG_KMS("DPCD: ");
Daniel Vetter1a644cd2012-10-18 15:32:40 +0200493 for (i = 0; i < DP_DPCD_SIZE; i++)
Alex Deucher224d94b2011-05-20 04:34:28 -0400494 DRM_DEBUG_KMS("%02x ", msg[i]);
495 DRM_DEBUG_KMS("\n");
Adam Jackson40c5d872012-05-14 16:05:48 -0400496
497 radeon_dp_probe_oui(radeon_connector);
498
Alex Deucher224d94b2011-05-20 04:34:28 -0400499 return true;
500 }
501 dig_connector->dpcd[0] = 0;
502 return false;
503}
504
Alex Deucher386d4d72012-01-20 15:01:29 -0500505int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
506 struct drm_connector *connector)
Alex Deucher224d94b2011-05-20 04:34:28 -0400507{
508 struct drm_device *dev = encoder->dev;
509 struct radeon_device *rdev = dev->dev_private;
Alex Deucher00dfb8d2011-10-31 08:54:41 -0400510 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
Alex Deucher224d94b2011-05-20 04:34:28 -0400511 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
Alex Deucher0ceb9962012-08-27 17:48:18 -0400512 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
513 u8 tmp;
Alex Deucher224d94b2011-05-20 04:34:28 -0400514
515 if (!ASIC_IS_DCE4(rdev))
Alex Deucher386d4d72012-01-20 15:01:29 -0500516 return panel_mode;
Alex Deucher224d94b2011-05-20 04:34:28 -0400517
Alex Deucher0ceb9962012-08-27 17:48:18 -0400518 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
519 /* DP bridge chips */
520 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
521 if (tmp & 1)
522 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
523 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
524 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
Alex Deucher304a4842012-02-02 10:18:00 -0500525 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
526 else
Alex Deucher0ceb9962012-08-27 17:48:18 -0400527 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
Alex Deucher304a4842012-02-02 10:18:00 -0500528 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
Alex Deucher0ceb9962012-08-27 17:48:18 -0400529 /* eDP */
530 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
Alex Deucher00dfb8d2011-10-31 08:54:41 -0400531 if (tmp & 1)
532 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
533 }
Alex Deucher224d94b2011-05-20 04:34:28 -0400534
Alex Deucher386d4d72012-01-20 15:01:29 -0500535 return panel_mode;
Alex Deucher224d94b2011-05-20 04:34:28 -0400536}
537
538void radeon_dp_set_link_config(struct drm_connector *connector,
Laurent Pincharte811f5a2012-07-17 17:56:50 +0200539 const struct drm_display_mode *mode)
Alex Deucher224d94b2011-05-20 04:34:28 -0400540{
541 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
542 struct radeon_connector_atom_dig *dig_connector;
543
544 if (!radeon_connector->con_priv)
545 return;
546 dig_connector = radeon_connector->con_priv;
547
548 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
549 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
550 dig_connector->dp_clock =
551 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
552 dig_connector->dp_lane_count =
553 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
554 }
555}
556
557int radeon_dp_mode_valid_helper(struct drm_connector *connector,
558 struct drm_display_mode *mode)
559{
560 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
561 struct radeon_connector_atom_dig *dig_connector;
562 int dp_clock;
563
564 if (!radeon_connector->con_priv)
565 return MODE_CLOCK_HIGH;
566 dig_connector = radeon_connector->con_priv;
567
568 dp_clock =
569 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
570
571 if ((dp_clock == 540000) &&
572 (!radeon_connector_is_dp12_capable(connector)))
573 return MODE_CLOCK_HIGH;
574
575 return MODE_OK;
576}
577
578static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector,
579 u8 link_status[DP_LINK_STATUS_SIZE])
580{
581 int ret;
582 ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS,
583 link_status, DP_LINK_STATUS_SIZE, 100);
584 if (ret <= 0) {
Alex Deucher224d94b2011-05-20 04:34:28 -0400585 return false;
586 }
587
Andy Shevchenko9a6a4b42012-09-05 12:04:19 +0000588 DRM_DEBUG_KMS("link status %*ph\n", 6, link_status);
Alex Deucher224d94b2011-05-20 04:34:28 -0400589 return true;
590}
591
Alex Deucherd5811e82011-08-13 13:36:13 -0400592bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
593{
594 u8 link_status[DP_LINK_STATUS_SIZE];
595 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
596
597 if (!radeon_dp_get_link_status(radeon_connector, link_status))
598 return false;
Daniel Vetter1ffdff12012-10-18 10:15:24 +0200599 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
Alex Deucherd5811e82011-08-13 13:36:13 -0400600 return false;
601 return true;
602}
603
Alex Deucher224d94b2011-05-20 04:34:28 -0400604struct radeon_dp_link_train_info {
605 struct radeon_device *rdev;
606 struct drm_encoder *encoder;
607 struct drm_connector *connector;
608 struct radeon_connector *radeon_connector;
609 int enc_id;
610 int dp_clock;
611 int dp_lane_count;
Alex Deucher224d94b2011-05-20 04:34:28 -0400612 bool tp3_supported;
Daniel Vetter1a644cd2012-10-18 15:32:40 +0200613 u8 dpcd[DP_RECEIVER_CAP_SIZE];
Alex Deucher224d94b2011-05-20 04:34:28 -0400614 u8 train_set[4];
615 u8 link_status[DP_LINK_STATUS_SIZE];
616 u8 tries;
Jerome Glisse5a96a892011-07-25 11:57:43 -0400617 bool use_dpencoder;
Alex Deucher224d94b2011-05-20 04:34:28 -0400618};
619
620static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
621{
622 /* set the initial vs/emph on the source */
623 atombios_dig_transmitter_setup(dp_info->encoder,
624 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
625 0, dp_info->train_set[0]); /* sets all lanes at once */
626
627 /* set the vs/emph on the sink */
628 radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET,
629 dp_info->train_set, dp_info->dp_lane_count, 0);
630}
631
632static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
633{
634 int rtp = 0;
635
636 /* set training pattern on the source */
Jerome Glisse5a96a892011-07-25 11:57:43 -0400637 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
Alex Deucher224d94b2011-05-20 04:34:28 -0400638 switch (tp) {
639 case DP_TRAINING_PATTERN_1:
640 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
641 break;
642 case DP_TRAINING_PATTERN_2:
643 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
644 break;
645 case DP_TRAINING_PATTERN_3:
646 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
647 break;
648 }
649 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
650 } else {
651 switch (tp) {
652 case DP_TRAINING_PATTERN_1:
653 rtp = 0;
654 break;
655 case DP_TRAINING_PATTERN_2:
656 rtp = 1;
657 break;
658 }
659 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
660 dp_info->dp_clock, dp_info->enc_id, rtp);
661 }
662
663 /* enable training pattern on the sink */
664 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp);
665}
666
667static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
668{
Alex Deucher386d4d72012-01-20 15:01:29 -0500669 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
670 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
Alex Deucher224d94b2011-05-20 04:34:28 -0400671 u8 tmp;
672
673 /* power up the sink */
674 if (dp_info->dpcd[0] >= 0x11)
675 radeon_write_dpcd_reg(dp_info->radeon_connector,
676 DP_SET_POWER, DP_SET_POWER_D0);
677
678 /* possibly enable downspread on the sink */
679 if (dp_info->dpcd[3] & 0x1)
680 radeon_write_dpcd_reg(dp_info->radeon_connector,
681 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
682 else
683 radeon_write_dpcd_reg(dp_info->radeon_connector,
684 DP_DOWNSPREAD_CTRL, 0);
685
Alex Deucher386d4d72012-01-20 15:01:29 -0500686 if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
687 (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
688 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1);
689 }
Alex Deucher224d94b2011-05-20 04:34:28 -0400690
691 /* set the lane count on the sink */
692 tmp = dp_info->dp_lane_count;
Dave Airlieabc81132012-03-18 10:10:50 +0000693 if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 &&
694 dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)
Alex Deucher224d94b2011-05-20 04:34:28 -0400695 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
696 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);
697
698 /* set the link rate on the sink */
Daniel Vetter3b5c6622012-10-18 10:15:31 +0200699 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
Alex Deucher224d94b2011-05-20 04:34:28 -0400700 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);
701
702 /* start training on the source */
Jerome Glisse5a96a892011-07-25 11:57:43 -0400703 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
Alex Deucher224d94b2011-05-20 04:34:28 -0400704 atombios_dig_encoder_setup(dp_info->encoder,
705 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
706 else
707 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
708 dp_info->dp_clock, dp_info->enc_id, 0);
709
710 /* disable the training pattern on the sink */
711 radeon_write_dpcd_reg(dp_info->radeon_connector,
712 DP_TRAINING_PATTERN_SET,
713 DP_TRAINING_PATTERN_DISABLE);
714
715 return 0;
716}
717
718static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
719{
720 udelay(400);
721
722 /* disable the training pattern on the sink */
723 radeon_write_dpcd_reg(dp_info->radeon_connector,
724 DP_TRAINING_PATTERN_SET,
725 DP_TRAINING_PATTERN_DISABLE);
726
727 /* disable the training pattern on the source */
Jerome Glisse5a96a892011-07-25 11:57:43 -0400728 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
Alex Deucher224d94b2011-05-20 04:34:28 -0400729 atombios_dig_encoder_setup(dp_info->encoder,
730 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
731 else
732 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
733 dp_info->dp_clock, dp_info->enc_id, 0);
734
735 return 0;
736}
737
738static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
739{
740 bool clock_recovery;
741 u8 voltage;
742 int i;
743
744 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
745 memset(dp_info->train_set, 0, 4);
746 radeon_dp_update_vs_emph(dp_info);
747
748 udelay(400);
749
750 /* clock recovery loop */
751 clock_recovery = false;
752 dp_info->tries = 0;
753 voltage = 0xff;
754 while (1) {
Daniel Vetter1a644cd2012-10-18 15:32:40 +0200755 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
Alex Deucher224d94b2011-05-20 04:34:28 -0400756
Jerome Glisse8d1c7022012-07-17 17:17:16 -0400757 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
758 DRM_ERROR("displayport link status failed\n");
Alex Deucher224d94b2011-05-20 04:34:28 -0400759 break;
Jerome Glisse8d1c7022012-07-17 17:17:16 -0400760 }
Alex Deucher224d94b2011-05-20 04:34:28 -0400761
Daniel Vetter01916272012-10-18 10:15:25 +0200762 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
Alex Deucher224d94b2011-05-20 04:34:28 -0400763 clock_recovery = true;
764 break;
765 }
766
767 for (i = 0; i < dp_info->dp_lane_count; i++) {
768 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
769 break;
770 }
771 if (i == dp_info->dp_lane_count) {
772 DRM_ERROR("clock recovery reached max voltage\n");
773 break;
774 }
775
776 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
777 ++dp_info->tries;
778 if (dp_info->tries == 5) {
779 DRM_ERROR("clock recovery tried 5 times\n");
780 break;
781 }
782 } else
783 dp_info->tries = 0;
784
785 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
786
787 /* Compute new train_set as requested by sink */
788 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
789
790 radeon_dp_update_vs_emph(dp_info);
791 }
792 if (!clock_recovery) {
793 DRM_ERROR("clock recovery failed\n");
794 return -1;
795 } else {
796 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
797 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
798 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
799 DP_TRAIN_PRE_EMPHASIS_SHIFT);
800 return 0;
801 }
802}
803
804static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
805{
806 bool channel_eq;
807
808 if (dp_info->tp3_supported)
809 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
810 else
811 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
812
813 /* channel equalization loop */
814 dp_info->tries = 0;
815 channel_eq = false;
816 while (1) {
Daniel Vetter1a644cd2012-10-18 15:32:40 +0200817 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
Alex Deucher224d94b2011-05-20 04:34:28 -0400818
Jerome Glisse8d1c7022012-07-17 17:17:16 -0400819 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
820 DRM_ERROR("displayport link status failed\n");
Alex Deucher224d94b2011-05-20 04:34:28 -0400821 break;
Jerome Glisse8d1c7022012-07-17 17:17:16 -0400822 }
Alex Deucher224d94b2011-05-20 04:34:28 -0400823
Daniel Vetter1ffdff12012-10-18 10:15:24 +0200824 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
Alex Deucher224d94b2011-05-20 04:34:28 -0400825 channel_eq = true;
826 break;
827 }
828
829 /* Try 5 times */
830 if (dp_info->tries > 5) {
831 DRM_ERROR("channel eq failed: 5 tries\n");
832 break;
833 }
834
835 /* Compute new train_set as requested by sink */
836 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
837
838 radeon_dp_update_vs_emph(dp_info);
839 dp_info->tries++;
840 }
841
842 if (!channel_eq) {
843 DRM_ERROR("channel eq failed\n");
844 return -1;
845 } else {
846 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
847 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
848 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
849 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
850 return 0;
851 }
852}
853
854void radeon_dp_link_train(struct drm_encoder *encoder,
855 struct drm_connector *connector)
856{
857 struct drm_device *dev = encoder->dev;
858 struct radeon_device *rdev = dev->dev_private;
859 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
860 struct radeon_encoder_atom_dig *dig;
861 struct radeon_connector *radeon_connector;
862 struct radeon_connector_atom_dig *dig_connector;
863 struct radeon_dp_link_train_info dp_info;
Jerome Glisse5a96a892011-07-25 11:57:43 -0400864 int index;
865 u8 tmp, frev, crev;
Alex Deucher224d94b2011-05-20 04:34:28 -0400866
867 if (!radeon_encoder->enc_priv)
868 return;
869 dig = radeon_encoder->enc_priv;
870
871 radeon_connector = to_radeon_connector(connector);
872 if (!radeon_connector->con_priv)
873 return;
874 dig_connector = radeon_connector->con_priv;
875
876 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
877 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
878 return;
879
Jerome Glisse5a96a892011-07-25 11:57:43 -0400880 /* DPEncoderService newer than 1.1 can't program properly the
881 * training pattern. When facing such version use the
882 * DIGXEncoderControl (X== 1 | 2)
883 */
884 dp_info.use_dpencoder = true;
885 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
886 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
887 if (crev > 1) {
888 dp_info.use_dpencoder = false;
889 }
890 }
891
Alex Deucher224d94b2011-05-20 04:34:28 -0400892 dp_info.enc_id = 0;
893 if (dig->dig_encoder)
894 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
895 else
896 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
897 if (dig->linkb)
898 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
899 else
900 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
901
Alex Deucher224d94b2011-05-20 04:34:28 -0400902 tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT);
903 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
904 dp_info.tp3_supported = true;
905 else
906 dp_info.tp3_supported = false;
907
Daniel Vetter1a644cd2012-10-18 15:32:40 +0200908 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
Alex Deucher224d94b2011-05-20 04:34:28 -0400909 dp_info.rdev = rdev;
910 dp_info.encoder = encoder;
911 dp_info.connector = connector;
912 dp_info.radeon_connector = radeon_connector;
913 dp_info.dp_lane_count = dig_connector->dp_lane_count;
914 dp_info.dp_clock = dig_connector->dp_clock;
915
916 if (radeon_dp_link_train_init(&dp_info))
917 goto done;
918 if (radeon_dp_link_train_cr(&dp_info))
919 goto done;
920 if (radeon_dp_link_train_ce(&dp_info))
921 goto done;
922done:
923 if (radeon_dp_link_train_finish(&dp_info))
924 return;
925}