blob: d6c4ebf91547209b720c013c5760e7e99e650342 [file] [log] [blame]
Stephen M. Cameronedd16362009-12-08 14:09:11 -08001/*
2 * Disk Array driver for HP Smart Array SAS controllers
Don Brace1358f6d2015-07-18 11:12:38 -05003 * Copyright 2014-2015 PMC-Sierra, Inc.
4 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
Stephen M. Cameronedd16362009-12-08 14:09:11 -08005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
Don Brace1358f6d2015-07-18 11:12:38 -050015 * Questions/Comments/Bugfixes to storagedev@pmcs.com
Stephen M. Cameronedd16362009-12-08 14:09:11 -080016 *
17 */
18#ifndef HPSA_H
19#define HPSA_H
20
21#include <scsi/scsicam.h>
22
23#define IO_OK 0
24#define IO_ERROR 1
25
26struct ctlr_info;
27
28struct access_method {
29 void (*submit_command)(struct ctlr_info *h,
30 struct CommandList *c);
31 void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
Stephen M. Cameron900c5442010-02-04 08:42:35 -060032 bool (*intr_pending)(struct ctlr_info *h);
Matt Gates254f7962012-05-01 11:43:06 -050033 unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
Stephen M. Cameronedd16362009-12-08 14:09:11 -080034};
35
36struct hpsa_scsi_dev_t {
Don Brace3ad7de62015-11-04 15:50:19 -060037 unsigned int devtype;
Stephen M. Cameronedd16362009-12-08 14:09:11 -080038 int bus, target, lun; /* as presented to the OS */
39 unsigned char scsi3addr[8]; /* as presented to the HW */
40#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
41 unsigned char device_id[16]; /* from inquiry pg. 0x83 */
42 unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
43 unsigned char model[16]; /* bytes 16-31 of inquiry data */
Stephen M. Cameronedd16362009-12-08 14:09:11 -080044 unsigned char raid_level; /* from inquiry page 0xC1 */
Stephen M. Cameron98465902014-02-21 16:25:00 -060045 unsigned char volume_offline; /* discovered via TUR or VPD */
Don Brace03383732015-01-23 16:43:30 -060046 u16 queue_depth; /* max queue_depth for this device */
Webb Scalesd604f532015-04-23 09:35:22 -050047 atomic_t reset_cmds_out; /* Count of commands to-be affected */
Don Brace03383732015-01-23 16:43:30 -060048 atomic_t ioaccel_cmds_out; /* Only used for physical devices
49 * counts commands sent to physical
50 * device via "ioaccel" path.
51 */
Matt Gatese1f7de02014-02-18 13:55:17 -060052 u32 ioaccel_handle;
Joe Handzik8270b862015-07-18 11:12:43 -050053 u8 active_path_index;
54 u8 path_map;
55 u8 bay;
56 u8 box[8];
57 u16 phys_connector[8];
Stephen M. Cameron283b4a92014-02-18 13:55:33 -060058 int offload_config; /* I/O accel RAID offload configured */
59 int offload_enabled; /* I/O accel RAID offload enabled */
Stephen Cameron41ce4c32015-04-23 09:31:47 -050060 int offload_to_be_enabled;
Joe Handzika3144e02015-04-23 09:32:59 -050061 int hba_ioaccel_enabled;
Stephen M. Cameron283b4a92014-02-18 13:55:33 -060062 int offload_to_mirror; /* Send next I/O accelerator RAID
63 * offload request to mirror drive
64 */
65 struct raid_map_data raid_map; /* I/O accelerator RAID map */
66
Don Brace03383732015-01-23 16:43:30 -060067 /*
68 * Pointers from logical drive map indices to the phys drives that
69 * make those logical drives. Note, multiple logical drives may
70 * share physical drives. You can have for instance 5 physical
71 * drives with 3 logical drives each using those same 5 physical
72 * disks. We need these pointers for counting i/o's out to physical
73 * devices in order to honor physical device queue depth limits.
74 */
75 struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES];
Webb Scalesd604f532015-04-23 09:35:22 -050076 int nphysical_disks;
Stephen Cameron9b5c48c2015-04-23 09:32:06 -050077 int supports_aborts;
Stephen Cameron41ce4c32015-04-23 09:31:47 -050078#define HPSA_DO_NOT_EXPOSE 0x0
79#define HPSA_SG_ATTACH 0x1
80#define HPSA_ULD_ATTACH 0x2
81#define HPSA_SCSI_ADD (HPSA_SG_ATTACH | HPSA_ULD_ATTACH)
82 u8 expose_state;
Stephen M. Cameronedd16362009-12-08 14:09:11 -080083};
84
Stephen M. Cameron072b0512014-05-29 10:53:07 -050085struct reply_queue_buffer {
Matt Gates254f7962012-05-01 11:43:06 -050086 u64 *head;
87 size_t size;
88 u8 wraparound;
89 u32 current_entry;
Stephen M. Cameron072b0512014-05-29 10:53:07 -050090 dma_addr_t busaddr;
Matt Gates254f7962012-05-01 11:43:06 -050091};
92
Stephen M. Cameron316b2212014-02-21 16:25:15 -060093#pragma pack(1)
94struct bmic_controller_parameters {
95 u8 led_flags;
96 u8 enable_command_list_verification;
97 u8 backed_out_write_drives;
98 u16 stripes_for_parity;
99 u8 parity_distribution_mode_flags;
100 u16 max_driver_requests;
101 u16 elevator_trend_count;
102 u8 disable_elevator;
103 u8 force_scan_complete;
104 u8 scsi_transfer_mode;
105 u8 force_narrow;
106 u8 rebuild_priority;
107 u8 expand_priority;
108 u8 host_sdb_asic_fix;
109 u8 pdpi_burst_from_host_disabled;
110 char software_name[64];
111 char hardware_name[32];
112 u8 bridge_revision;
113 u8 snapshot_priority;
114 u32 os_specific;
115 u8 post_prompt_timeout;
116 u8 automatic_drive_slamming;
117 u8 reserved1;
118 u8 nvram_flags;
119 u8 cache_nvram_flags;
120 u8 drive_config_flags;
121 u16 reserved2;
122 u8 temp_warning_level;
123 u8 temp_shutdown_level;
124 u8 temp_condition_reset;
125 u8 max_coalesce_commands;
126 u32 max_coalesce_delay;
127 u8 orca_password[4];
128 u8 access_id[16];
129 u8 reserved[356];
130};
131#pragma pack()
132
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800133struct ctlr_info {
134 int ctlr;
135 char devname[8];
136 char *product_name;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800137 struct pci_dev *pdev;
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600138 u32 board_id;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800139 void __iomem *vaddr;
140 unsigned long paddr;
141 int nr_cmds; /* Number of commands allowed on this controller */
Stephen Camerond54c5c22015-01-23 16:42:59 -0600142#define HPSA_CMDS_RESERVED_FOR_ABORTS 2
143#define HPSA_CMDS_RESERVED_FOR_DRIVER 1
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800144 struct CfgTable __iomem *cfgtable;
145 int interrupts_enabled;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800146 int max_commands;
Stephen M. Cameron0cbf7682014-11-14 17:27:09 -0600147 atomic_t commands_outstanding;
Don Brace303932f2010-02-04 08:42:40 -0600148# define PERF_MODE_INT 0
149# define DOORBELL_INT 1
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800150# define SIMPLE_MODE_INT 2
151# define MEMQ_MODE_INT 3
Matt Gates254f7962012-05-01 11:43:06 -0500152 unsigned int intr[MAX_REPLY_QUEUES];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800153 unsigned int msix_vector;
154 unsigned int msi_vector;
Stephen M. Camerona9a3a272011-02-15 15:32:53 -0600155 int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800156 struct access_method access;
157
158 /* queue and queue Info */
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800159 unsigned int Qdepth;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800160 unsigned int maxSG;
161 spinlock_t lock;
Stephen M. Cameron33a2ffc2010-02-25 14:03:27 -0600162 int maxsgentries;
163 u8 max_cmd_sg_entries;
164 int chainsize;
165 struct SGDescriptor **cmd_sg_list;
Webb Scalesd9a729f2015-04-23 09:33:27 -0500166 struct ioaccel2_sg_element **ioaccel2_cmd_sg_list;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800167
168 /* pointers to command and error info pool */
169 struct CommandList *cmd_pool;
170 dma_addr_t cmd_pool_dhandle;
Matt Gatese1f7de02014-02-18 13:55:17 -0600171 struct io_accel1_cmd *ioaccel_cmd_pool;
172 dma_addr_t ioaccel_cmd_pool_dhandle;
Stephen M. Cameronaca90122014-02-18 13:56:14 -0600173 struct io_accel2_cmd *ioaccel2_cmd_pool;
174 dma_addr_t ioaccel2_cmd_pool_dhandle;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800175 struct ErrorInfo *errinfo_pool;
176 dma_addr_t errinfo_pool_dhandle;
177 unsigned long *cmd_pool_bits;
Stephen M. Camerona08a8472010-02-04 08:43:16 -0600178 int scan_finished;
179 spinlock_t scan_lock;
180 wait_queue_head_t scan_wait_queue;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800181
182 struct Scsi_Host *scsi_host;
183 spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
184 int ndevices; /* number of used elements in .dev[] array. */
Scott Teelcfe5bad2011-10-26 16:21:07 -0500185 struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
Don Brace303932f2010-02-04 08:42:40 -0600186 /*
187 * Performant mode tables.
188 */
189 u32 trans_support;
190 u32 trans_offset;
Don Brace42a91642014-11-14 17:26:27 -0600191 struct TransTable_struct __iomem *transtable;
Don Brace303932f2010-02-04 08:42:40 -0600192 unsigned long transMethod;
193
Stephen M. Cameron0390f0c2013-09-23 13:34:12 -0500194 /* cap concurrent passthrus at some reasonable maximum */
Stephen Cameron45fcb862015-01-23 16:43:04 -0600195#define HPSA_MAX_CONCURRENT_PASSTHRUS (10)
Don Brace34f0c622015-01-23 16:43:46 -0600196 atomic_t passthru_cmds_avail;
Stephen M. Cameron0390f0c2013-09-23 13:34:12 -0500197
Don Brace303932f2010-02-04 08:42:40 -0600198 /*
Matt Gates254f7962012-05-01 11:43:06 -0500199 * Performant mode completion buffers
Don Brace303932f2010-02-04 08:42:40 -0600200 */
Stephen M. Cameron072b0512014-05-29 10:53:07 -0500201 size_t reply_queue_size;
202 struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES];
Matt Gates254f7962012-05-01 11:43:06 -0500203 u8 nreply_queues;
Don Brace303932f2010-02-04 08:42:40 -0600204 u32 *blockFetchTable;
Matt Gatese1f7de02014-02-18 13:55:17 -0600205 u32 *ioaccel1_blockFetchTable;
Stephen M. Cameronaca90122014-02-18 13:56:14 -0600206 u32 *ioaccel2_blockFetchTable;
Don Brace42a91642014-11-14 17:26:27 -0600207 u32 __iomem *ioaccel2_bft2_regs;
Stephen M. Cameron339b2b12010-02-04 08:42:50 -0600208 unsigned char *hba_inquiry_data;
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600209 u32 driver_support;
210 u32 fw_support;
211 int ioaccel_support;
212 int ioaccel_maxsg;
Stephen M. Camerona0c12412011-10-26 16:22:04 -0500213 u64 last_intr_timestamp;
214 u32 last_heartbeat;
215 u64 last_heartbeat_timestamp;
Stephen M. Camerone85c5972012-05-01 11:43:42 -0500216 u32 heartbeat_sample_interval;
217 atomic_t firmware_flash_in_progress;
Don Brace42a91642014-11-14 17:26:27 -0600218 u32 __percpu *lockup_detected;
Stephen M. Cameron8a98db732013-12-04 17:10:07 -0600219 struct delayed_work monitor_ctlr_work;
Don Brace6636e7f2015-01-23 16:45:17 -0600220 struct delayed_work rescan_ctlr_work;
Stephen M. Cameron8a98db732013-12-04 17:10:07 -0600221 int remove_in_progress;
Matt Gates254f7962012-05-01 11:43:06 -0500222 /* Address of h->q[x] is passed to intr handler to know which queue */
223 u8 q[MAX_REPLY_QUEUES];
Robert Elliott8b470042015-04-23 09:34:58 -0500224 char intrname[MAX_REPLY_QUEUES][16]; /* "hpsa0-msix00" names */
Stephen M. Cameron75167d22012-05-01 11:42:51 -0500225 u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
226#define HPSATMF_BITS_SUPPORTED (1 << 0)
227#define HPSATMF_PHYS_LUN_RESET (1 << 1)
228#define HPSATMF_PHYS_NEX_RESET (1 << 2)
229#define HPSATMF_PHYS_TASK_ABORT (1 << 3)
230#define HPSATMF_PHYS_TSET_ABORT (1 << 4)
231#define HPSATMF_PHYS_CLEAR_ACA (1 << 5)
232#define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
233#define HPSATMF_PHYS_QRY_TASK (1 << 7)
234#define HPSATMF_PHYS_QRY_TSET (1 << 8)
235#define HPSATMF_PHYS_QRY_ASYNC (1 << 9)
Stephen Cameron8be986c2015-04-23 09:34:06 -0500236#define HPSATMF_IOACCEL_ENABLED (1 << 15)
Stephen M. Cameron75167d22012-05-01 11:42:51 -0500237#define HPSATMF_MASK_SUPPORTED (1 << 16)
238#define HPSATMF_LOG_LUN_RESET (1 << 17)
239#define HPSATMF_LOG_NEX_RESET (1 << 18)
240#define HPSATMF_LOG_TASK_ABORT (1 << 19)
241#define HPSATMF_LOG_TSET_ABORT (1 << 20)
242#define HPSATMF_LOG_CLEAR_ACA (1 << 21)
243#define HPSATMF_LOG_CLEAR_TSET (1 << 22)
244#define HPSATMF_LOG_QRY_TASK (1 << 23)
245#define HPSATMF_LOG_QRY_TSET (1 << 24)
246#define HPSATMF_LOG_QRY_ASYNC (1 << 25)
Stephen M. Cameron76438d02014-02-18 13:55:43 -0600247 u32 events;
Stephen M. Cameronfaff6ee2014-02-18 13:57:42 -0600248#define CTLR_STATE_CHANGE_EVENT (1 << 0)
249#define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1)
250#define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4)
251#define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5)
252#define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6)
253#define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30)
254#define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31)
255
256#define RESCAN_REQUIRED_EVENT_BITS \
Stephen M. Cameron7b2c46e2014-05-29 10:53:44 -0500257 (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \
Stephen M. Cameronfaff6ee2014-02-18 13:57:42 -0600258 CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \
259 CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \
Stephen M. Cameronfaff6ee2014-02-18 13:57:42 -0600260 CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \
261 CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE)
Stephen M. Cameron98465902014-02-21 16:25:00 -0600262 spinlock_t offline_device_lock;
263 struct list_head offline_device_list;
Scott Teelda0697b2014-02-18 13:57:00 -0600264 int acciopath_status;
Stephen M. Cameron2ba8bfc2014-02-18 13:57:52 -0600265 int raid_offload_debug;
Stephen Cameron9b5c48c2015-04-23 09:32:06 -0500266 int needs_abort_tags_swizzled;
Don Brace080ef1c2015-01-23 16:43:25 -0600267 struct workqueue_struct *resubmit_wq;
Don Brace6636e7f2015-01-23 16:45:17 -0600268 struct workqueue_struct *rescan_ctlr_wq;
Stephen Cameron9b5c48c2015-04-23 09:32:06 -0500269 atomic_t abort_cmds_available;
270 wait_queue_head_t abort_cmd_wait_queue;
Webb Scalesd604f532015-04-23 09:35:22 -0500271 wait_queue_head_t event_sync_wait_queue;
272 struct mutex reset_mutex;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800273};
Stephen M. Cameron98465902014-02-21 16:25:00 -0600274
275struct offline_device_entry {
276 unsigned char scsi3addr[8];
277 struct list_head offline_list;
278};
279
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800280#define HPSA_ABORT_MSG 0
281#define HPSA_DEVICE_RESET_MSG 1
Stephen M. Cameron64670ac2011-05-03 14:59:51 -0500282#define HPSA_RESET_TYPE_CONTROLLER 0x00
283#define HPSA_RESET_TYPE_BUS 0x01
284#define HPSA_RESET_TYPE_TARGET 0x03
285#define HPSA_RESET_TYPE_LUN 0x04
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800286#define HPSA_MSG_SEND_RETRY_LIMIT 10
Stephen M. Cameron516fda42011-05-03 14:59:15 -0500287#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800288
289/* Maximum time in seconds driver will wait for command completions
290 * when polling before giving up.
291 */
292#define HPSA_MAX_POLL_TIME_SECS (20)
293
294/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
295 * how many times to retry TEST UNIT READY on a device
296 * while waiting for it to become ready before giving up.
297 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
298 * between sending TURs while waiting for a device
299 * to become ready.
300 */
301#define HPSA_TUR_RETRY_LIMIT (20)
302#define HPSA_MAX_WAIT_INTERVAL_SECS (30)
303
304/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
305 * to become ready, in seconds, before giving up on it.
306 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
307 * between polling the board to see if it is ready, in
308 * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
309 * HPSA_BOARD_READY_ITERATIONS are derived from those.
310 */
311#define HPSA_BOARD_READY_WAIT_SECS (120)
Stephen M. Cameron2ed71272011-05-03 14:59:31 -0500312#define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800313#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
314#define HPSA_BOARD_READY_POLL_INTERVAL \
315 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
316#define HPSA_BOARD_READY_ITERATIONS \
317 ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
318 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
Stephen M. Cameronfe5389c2011-01-06 14:48:03 -0600319#define HPSA_BOARD_NOT_READY_ITERATIONS \
320 ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
321 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800322#define HPSA_POST_RESET_PAUSE_MSECS (3000)
323#define HPSA_POST_RESET_NOOP_RETRIES (12)
324
325/* Defining the diffent access_menthods */
326/*
327 * Memory mapped FIFO interface (SMART 53xx cards)
328 */
329#define SA5_DOORBELL 0x20
330#define SA5_REQUEST_PORT_OFFSET 0x40
Webb Scales281a7fd2015-01-23 16:43:35 -0600331#define SA5_REQUEST_PORT64_LO_OFFSET 0xC0
332#define SA5_REQUEST_PORT64_HI_OFFSET 0xC4
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800333#define SA5_REPLY_INTR_MASK_OFFSET 0x34
334#define SA5_REPLY_PORT_OFFSET 0x44
335#define SA5_INTR_STATUS 0x30
336#define SA5_SCRATCHPAD_OFFSET 0xB0
337
338#define SA5_CTCFG_OFFSET 0xB4
339#define SA5_CTMEM_OFFSET 0xB8
340
341#define SA5_INTR_OFF 0x08
342#define SA5B_INTR_OFF 0x04
343#define SA5_INTR_PENDING 0x08
344#define SA5B_INTR_PENDING 0x04
345#define FIFO_EMPTY 0xffffffff
346#define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
347
348#define HPSA_ERROR_BIT 0x02
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800349
Don Brace303932f2010-02-04 08:42:40 -0600350/* Performant mode flags */
351#define SA5_PERF_INTR_PENDING 0x04
352#define SA5_PERF_INTR_OFF 0x05
353#define SA5_OUTDB_STATUS_PERF_BIT 0x01
354#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
355#define SA5_OUTDB_CLEAR 0xA0
356#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
357#define SA5_OUTDB_STATUS 0x9C
358
359
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800360#define HPSA_INTR_ON 1
361#define HPSA_INTR_OFF 0
Mike Millerb66cc252014-02-18 13:56:04 -0600362
363/*
364 * Inbound Post Queue offsets for IO Accelerator Mode 2
365 */
366#define IOACCEL2_INBOUND_POSTQ_32 0x48
367#define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0
368#define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4
369
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800370/*
371 Send the command to the hardware
372*/
373static void SA5_submit_command(struct ctlr_info *h,
374 struct CommandList *c)
375{
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800376 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
Stephen M. Cameronfec62c32011-07-21 13:16:05 -0500377 (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800378}
379
Stephen M. Cameronb3a52e72014-05-29 10:53:23 -0500380static void SA5_submit_command_no_read(struct ctlr_info *h,
381 struct CommandList *c)
382{
383 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
384}
385
Scott Teelc3497752014-02-18 13:56:34 -0600386static void SA5_submit_command_ioaccel2(struct ctlr_info *h,
387 struct CommandList *c)
388{
Stephen Cameronc05e8862015-01-23 16:44:40 -0600389 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
Scott Teelc3497752014-02-18 13:56:34 -0600390}
391
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800392/*
393 * This card is the opposite of the other cards.
394 * 0 turns interrupts on...
395 * 0x08 turns them off...
396 */
397static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
398{
399 if (val) { /* Turn interrupts on */
400 h->interrupts_enabled = 1;
401 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Stephen M. Cameron8cd21da2011-05-03 14:58:55 -0500402 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800403 } else { /* Turn them off */
404 h->interrupts_enabled = 0;
405 writel(SA5_INTR_OFF,
406 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Stephen M. Cameron8cd21da2011-05-03 14:58:55 -0500407 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800408 }
409}
Don Brace303932f2010-02-04 08:42:40 -0600410
411static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
412{
413 if (val) { /* turn on interrupts */
414 h->interrupts_enabled = 1;
415 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Stephen M. Cameron8cd21da2011-05-03 14:58:55 -0500416 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Don Brace303932f2010-02-04 08:42:40 -0600417 } else {
418 h->interrupts_enabled = 0;
419 writel(SA5_PERF_INTR_OFF,
420 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Stephen M. Cameron8cd21da2011-05-03 14:58:55 -0500421 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Don Brace303932f2010-02-04 08:42:40 -0600422 }
423}
424
Matt Gates254f7962012-05-01 11:43:06 -0500425static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
Don Brace303932f2010-02-04 08:42:40 -0600426{
Stephen M. Cameron072b0512014-05-29 10:53:07 -0500427 struct reply_queue_buffer *rq = &h->reply_queue[q];
Stephen M. Cameron0cbf7682014-11-14 17:27:09 -0600428 unsigned long register_value = FIFO_EMPTY;
Don Brace303932f2010-02-04 08:42:40 -0600429
Don Brace303932f2010-02-04 08:42:40 -0600430 /* msi auto clears the interrupt pending bit. */
Don Bracebee266a2015-01-23 16:43:51 -0600431 if (unlikely(!(h->msi_vector || h->msix_vector))) {
Stephen M. Cameron2c17d2d2012-05-01 11:42:30 -0500432 /* flush the controller write of the reply queue by reading
433 * outbound doorbell status register.
434 */
Don Bracebee266a2015-01-23 16:43:51 -0600435 (void) readl(h->vaddr + SA5_OUTDB_STATUS);
Don Brace303932f2010-02-04 08:42:40 -0600436 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
437 /* Do a read in order to flush the write to the controller
438 * (as per spec.)
439 */
Don Bracebee266a2015-01-23 16:43:51 -0600440 (void) readl(h->vaddr + SA5_OUTDB_STATUS);
Don Brace303932f2010-02-04 08:42:40 -0600441 }
442
Don Bracebee266a2015-01-23 16:43:51 -0600443 if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) {
Matt Gates254f7962012-05-01 11:43:06 -0500444 register_value = rq->head[rq->current_entry];
445 rq->current_entry++;
Stephen M. Cameron0cbf7682014-11-14 17:27:09 -0600446 atomic_dec(&h->commands_outstanding);
Don Brace303932f2010-02-04 08:42:40 -0600447 } else {
448 register_value = FIFO_EMPTY;
449 }
450 /* Check for wraparound */
Matt Gates254f7962012-05-01 11:43:06 -0500451 if (rq->current_entry == h->max_commands) {
452 rq->current_entry = 0;
453 rq->wraparound ^= 1;
Don Brace303932f2010-02-04 08:42:40 -0600454 }
Don Brace303932f2010-02-04 08:42:40 -0600455 return register_value;
456}
457
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800458/*
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800459 * returns value read from hardware.
460 * returns FIFO_EMPTY if there is nothing to read
461 */
Matt Gates254f7962012-05-01 11:43:06 -0500462static unsigned long SA5_completed(struct ctlr_info *h,
463 __attribute__((unused)) u8 q)
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800464{
465 unsigned long register_value
466 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
467
Stephen M. Cameron0cbf7682014-11-14 17:27:09 -0600468 if (register_value != FIFO_EMPTY)
469 atomic_dec(&h->commands_outstanding);
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800470
471#ifdef HPSA_DEBUG
472 if (register_value != FIFO_EMPTY)
Stephen M. Cameron84ca0be2010-02-04 08:42:30 -0600473 dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800474 register_value);
475 else
Stephen M. Cameronf79cfec2012-01-19 14:00:59 -0600476 dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800477#endif
478
479 return register_value;
480}
481/*
482 * Returns true if an interrupt is pending..
483 */
Stephen M. Cameron900c5442010-02-04 08:42:35 -0600484static bool SA5_intr_pending(struct ctlr_info *h)
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800485{
486 unsigned long register_value =
487 readl(h->vaddr + SA5_INTR_STATUS);
Stephen M. Cameron900c5442010-02-04 08:42:35 -0600488 return register_value & SA5_INTR_PENDING;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800489}
490
Don Brace303932f2010-02-04 08:42:40 -0600491static bool SA5_performant_intr_pending(struct ctlr_info *h)
492{
493 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
494
495 if (!register_value)
496 return false;
497
Don Brace303932f2010-02-04 08:42:40 -0600498 /* Read outbound doorbell to flush */
499 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
500 return register_value & SA5_OUTDB_STATUS_PERF_BIT;
501}
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800502
Matt Gatese1f7de02014-02-18 13:55:17 -0600503#define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100
504
505static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
506{
507 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
508
509 return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ?
510 true : false;
511}
512
513#define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0
514#define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8
515#define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC
516#define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL
517
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600518static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
Matt Gatese1f7de02014-02-18 13:55:17 -0600519{
520 u64 register_value;
Stephen M. Cameron072b0512014-05-29 10:53:07 -0500521 struct reply_queue_buffer *rq = &h->reply_queue[q];
Matt Gatese1f7de02014-02-18 13:55:17 -0600522
523 BUG_ON(q >= h->nreply_queues);
524
525 register_value = rq->head[rq->current_entry];
526 if (register_value != IOACCEL_MODE1_REPLY_UNUSED) {
527 rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED;
528 if (++rq->current_entry == rq->size)
529 rq->current_entry = 0;
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600530 /*
531 * @todo
532 *
533 * Don't really need to write the new index after each command,
534 * but with current driver design this is easiest.
535 */
536 wmb();
537 writel((q << 24) | rq->current_entry, h->vaddr +
538 IOACCEL_MODE1_CONSUMER_INDEX);
Stephen M. Cameron0cbf7682014-11-14 17:27:09 -0600539 atomic_dec(&h->commands_outstanding);
Matt Gatese1f7de02014-02-18 13:55:17 -0600540 }
541 return (unsigned long) register_value;
542}
543
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800544static struct access_method SA5_access = {
545 SA5_submit_command,
546 SA5_intr_mask,
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800547 SA5_intr_pending,
548 SA5_completed,
549};
550
Matt Gatese1f7de02014-02-18 13:55:17 -0600551static struct access_method SA5_ioaccel_mode1_access = {
552 SA5_submit_command,
553 SA5_performant_intr_mask,
Matt Gatese1f7de02014-02-18 13:55:17 -0600554 SA5_ioaccel_mode1_intr_pending,
555 SA5_ioaccel_mode1_completed,
556};
557
Scott Teelc3497752014-02-18 13:56:34 -0600558static struct access_method SA5_ioaccel_mode2_access = {
559 SA5_submit_command_ioaccel2,
560 SA5_performant_intr_mask,
Scott Teelc3497752014-02-18 13:56:34 -0600561 SA5_performant_intr_pending,
562 SA5_performant_completed,
563};
564
Don Brace303932f2010-02-04 08:42:40 -0600565static struct access_method SA5_performant_access = {
566 SA5_submit_command,
567 SA5_performant_intr_mask,
Don Brace303932f2010-02-04 08:42:40 -0600568 SA5_performant_intr_pending,
569 SA5_performant_completed,
570};
571
Stephen M. Cameronb3a52e72014-05-29 10:53:23 -0500572static struct access_method SA5_performant_access_no_read = {
573 SA5_submit_command_no_read,
574 SA5_performant_intr_mask,
Stephen M. Cameronb3a52e72014-05-29 10:53:23 -0500575 SA5_performant_intr_pending,
576 SA5_performant_completed,
577};
578
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800579struct board_type {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600580 u32 board_id;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800581 char *product_name;
582 struct access_method *access;
583};
584
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800585#endif /* HPSA_H */
586