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gerrit-public.fairphone.software / kernel / msm-4.9 / 3f120bbac14d87bd76e43e14f8823ee80b71a6ee / . / arch / arm64 / boot / dts / qcom / sdm845-v2.dtsi
blob: 761efea39b2eccb1bc84a7139ebace3acc069514 [file] [log] [blame]
Channagoud Kadabi459f0112017-03-20 12:42:15 -0700[diff] [blame]1/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include "sdm845.dtsi"
14
15/ {
16 model = "Qualcomm Technologies, Inc. SDM845 V2";
17 qcom,msm-id = <321 0x20000>;
18};
David Collins36050182017-04-26 11:41:22 -0700[diff] [blame]19
Subhash Jadavani0842b272017-07-19 17:05:13 -0700[diff] [blame]20&sdhc_2 {
Subhash Jadavani3497a962017-07-31 13:57:47 -0700[diff] [blame]21 /delete-property/ qcom,sdr104-wa;
Subhash Jadavani0842b272017-07-19 17:05:13 -0700[diff] [blame]22};
23
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]24/delete-node/ &apc0_cpr;
25/delete-node/ &apc1_cpr;
26
27&soc {
28 /* CPR controller regulators */
29 apc0_cpr: cprh-ctrl@17dc0000 {
30 compatible = "qcom,cprh-sdm845-v2-kbss-regulator";
31 reg = <0x17dc0000 0x4000>,
32 <0x00784000 0x1000>,
33 <0x17840000 0x1000>;
34 reg-names = "cpr_ctrl", "fuse_base", "saw";
35 clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>;
36 clock-names = "core_clk";
37 qcom,cpr-ctrl-name = "apc0";
38 qcom,cpr-controller-id = <0>;
39
40 qcom,cpr-sensor-time = <1000>;
41 qcom,cpr-loop-time = <5000000>;
42 qcom,cpr-idle-cycles = <15>;
43 qcom,cpr-up-down-delay-time = <3000>;
44 qcom,cpr-step-quot-init-min = <11>;
45 qcom,cpr-step-quot-init-max = <12>;
46 qcom,cpr-count-mode = <0>; /* All at once */
47 qcom,cpr-count-repeat = <20>;
48 qcom,cpr-down-error-step-limit = <1>;
49 qcom,cpr-up-error-step-limit = <1>;
50 qcom,cpr-corner-switch-delay-time = <1042>;
51 qcom,cpr-voltage-settling-time = <1760>;
52 qcom,cpr-reset-step-quot-loop-en;
53
54 qcom,voltage-step = <4000>;
55 qcom,voltage-base = <352000>;
56 qcom,cpr-saw-use-unit-mV;
57
58 qcom,saw-avs-ctrl = <0x101C031>;
59 qcom,saw-avs-limit = <0x3B803B8>;
60
61 qcom,cpr-enable;
62 qcom,cpr-hw-closed-loop;
63
64 qcom,cpr-panic-reg-addr-list =
65 <0x17dc3a84 0x17dc3a88 0x17840c18>;
66 qcom,cpr-panic-reg-name-list =
67 "APSS_SILVER_CPRH_STATUS_0",
68 "APSS_SILVER_CPRH_STATUS_1",
69 "SILVER_SAW4_PMIC_STS";
70
71 qcom,cpr-aging-ref-voltage = <952000>;
72 vdd-supply = <&pm8998_s13>;
73
74 thread@0 {
75 qcom,cpr-thread-id = <0>;
76 qcom,cpr-consecutive-up = <0>;
77 qcom,cpr-consecutive-down = <0>;
78 qcom,cpr-up-threshold = <2>;
79 qcom,cpr-down-threshold = <2>;
80
81 apc0_pwrcl_vreg: regulator {
82 regulator-name = "apc0_pwrcl_corner";
83 regulator-min-microvolt = <1>;
84 regulator-max-microvolt = <18>;
85
86 qcom,cpr-fuse-corners = <4>;
87 qcom,cpr-fuse-combos = <16>;
88 qcom,cpr-speed-bins = <2>;
89 qcom,cpr-speed-bin-corners = <18 18>;
90 qcom,cpr-corners = <18>;
91
92 qcom,cpr-corner-fmax-map = <6 12 15 18>;
93
94 qcom,cpr-voltage-ceiling =
95 <828000 828000 828000 828000 828000
96 828000 828000 828000 828000 828000
97 828000 828000 828000 828000 828000
98 884000 952000 952000>;
99
100 qcom,cpr-voltage-floor =
101 <568000 568000 568000 568000 568000
102 568000 568000 568000 568000 568000
103 568000 568000 568000 568000 568000
104 568000 568000 568000>;
105
106 qcom,cpr-floor-to-ceiling-max-range =
107 <32000 32000 32000 32000 32000
108 32000 32000 32000 32000 32000
109 32000 32000 32000 32000 32000
110 32000 40000 40000>;
111
112 qcom,corner-frequencies =
113 <300000000 403200000 480000000
114 576000000 652800000 748800000
115 825600000 902400000 979200000
116 1056000000 1132800000 1228800000
117 1324800000 1420800000 1516800000
118 1612800000 1689600000 1766400000>;
119
120 qcom,cpr-ro-scaling-factor =
121 <2594 2795 2576 2761 2469 2673 2198
122 2553 3188 3255 3191 2962 3055 2984
123 2043 2947>,
124 <2594 2795 2576 2761 2469 2673 2198
125 2553 3188 3255 3191 2962 3055 2984
126 2043 2947>,
127 <2259 2389 2387 2531 2294 2464 2218
128 2476 2525 2855 2817 2836 2740 2490
129 1950 2632>,
130 <2259 2389 2387 2531 2294 2464 2218
131 2476 2525 2855 2817 2836 2740 2490
132 1950 2632>;
133
134 qcom,cpr-open-loop-voltage-fuse-adjustment =
135 <100000 100000 100000 100000>;
136
137 qcom,cpr-closed-loop-voltage-fuse-adjustment =
138 <100000 100000 100000 100000>;
139
140 qcom,allow-voltage-interpolation;
141 qcom,allow-quotient-interpolation;
142 qcom,cpr-scaled-open-loop-voltage-as-ceiling;
143
144 qcom,cpr-aging-max-voltage-adjustment = <15000>;
145 qcom,cpr-aging-ref-corner = <18>;
146 qcom,cpr-aging-ro-scaling-factor = <1620>;
147 qcom,allow-aging-voltage-adjustment =
148 /* Speed bin 0 */
149 <0 1 1 1 1 1 1 1>,
150 /* Speed bin 1 */
151 <0 1 1 1 1 1 1 1>;
152 qcom,allow-aging-open-loop-voltage-adjustment =
153 <1>;
154 };
155 };
156
157 thread@1 {
158 qcom,cpr-thread-id = <1>;
159 qcom,cpr-consecutive-up = <0>;
160 qcom,cpr-consecutive-down = <0>;
161 qcom,cpr-up-threshold = <2>;
162 qcom,cpr-down-threshold = <2>;
163
164 apc0_l3_vreg: regulator {
165 regulator-name = "apc0_l3_corner";
166 regulator-min-microvolt = <1>;
167 regulator-max-microvolt = <14>;
168
169 qcom,cpr-fuse-corners = <4>;
170 qcom,cpr-fuse-combos = <16>;
171 qcom,cpr-speed-bins = <2>;
172 qcom,cpr-speed-bin-corners = <14 14>;
173 qcom,cpr-corners = <14>;
174
175 qcom,cpr-corner-fmax-map = <4 8 11 14>;
176
177 qcom,cpr-voltage-ceiling =
178 <828000 828000 828000 828000 828000
179 828000 828000 828000 828000 828000
180 828000 884000 884000 952000>;
181
182 qcom,cpr-voltage-floor =
183 <568000 568000 568000 568000 568000
184 568000 568000 568000 568000 568000
185 568000 568000 568000 568000>;
186
187 qcom,cpr-floor-to-ceiling-max-range =
188 <32000 32000 32000 32000 32000
189 32000 32000 32000 32000 32000
190 32000 32000 32000 40000>;
191
192 qcom,corner-frequencies =
193 <300000000 403200000 480000000
194 576000000 652800000 748800000
195 844800000 940800000 1036800000
196 1132800000 1209600000 1305600000
197 1401600000 1478400000>;
198
199 qcom,cpr-ro-scaling-factor =
200 <2857 3056 2828 2952 2699 2796 2447
201 2631 2630 2579 2244 3343 3287 3137
202 3164 2656>,
203 <2857 3056 2828 2952 2699 2796 2447
204 2631 2630 2579 2244 3343 3287 3137
205 3164 2656>,
206 <2439 2577 2552 2667 2461 2577 2394
207 2536 2132 2307 2191 2903 2838 2912
208 2501 2095>,
209 <2439 2577 2552 2667 2461 2577 2394
210 2536 2132 2307 2191 2903 2838 2912
211 2501 2095>;
212
213 qcom,cpr-open-loop-voltage-fuse-adjustment =
214 <100000 100000 100000 100000>;
215
216 qcom,cpr-closed-loop-voltage-fuse-adjustment =
217 <100000 100000 100000 100000>;
218
219 qcom,allow-voltage-interpolation;
220 qcom,allow-quotient-interpolation;
221 qcom,cpr-scaled-open-loop-voltage-as-ceiling;
222
223 qcom,cpr-aging-max-voltage-adjustment = <15000>;
224 qcom,cpr-aging-ref-corner = <14>;
225 qcom,cpr-aging-ro-scaling-factor = <1620>;
226 qcom,allow-aging-voltage-adjustment =
227 /* Speed bin 0 */
228 <0 1 1 1 1 1 1 1>,
229 /* Speed bin 1 */
230 <0 1 1 1 1 1 1 1>;
231 qcom,allow-aging-open-loop-voltage-adjustment =
232 <1>;
233 };
234 };
235 };
236
237 apc1_cpr: cprh-ctrl@17db0000 {
238 compatible = "qcom,cprh-sdm845-v2-kbss-regulator";
239 reg = <0x17db0000 0x4000>,
240 <0x00784000 0x1000>,
241 <0x17830000 0x1000>;
242 reg-names = "cpr_ctrl", "fuse_base", "saw";
243 clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>;
244 clock-names = "core_clk";
245 qcom,cpr-ctrl-name = "apc1";
246 qcom,cpr-controller-id = <1>;
247
248 qcom,cpr-sensor-time = <1000>;
249 qcom,cpr-loop-time = <5000000>;
250 qcom,cpr-idle-cycles = <15>;
251 qcom,cpr-up-down-delay-time = <3000>;
252 qcom,cpr-step-quot-init-min = <9>;
253 qcom,cpr-step-quot-init-max = <14>;
254 qcom,cpr-count-mode = <0>; /* All at once */
255 qcom,cpr-count-repeat = <20>;
256 qcom,cpr-down-error-step-limit = <1>;
257 qcom,cpr-up-error-step-limit = <1>;
258 qcom,cpr-corner-switch-delay-time = <1042>;
259 qcom,cpr-voltage-settling-time = <1760>;
260 qcom,cpr-reset-step-quot-loop-en;
261
262 qcom,apm-threshold-voltage = <800000>;
263 qcom,apm-crossover-voltage = <880000>;
264 qcom,mem-acc-threshold-voltage = <852000>;
265 qcom,mem-acc-crossover-voltage = <852000>;
266
267 qcom,voltage-step = <4000>;
268 qcom,voltage-base = <352000>;
269 qcom,cpr-saw-use-unit-mV;
270
271 qcom,saw-avs-ctrl = <0x101C031>;
272 qcom,saw-avs-limit = <0x4700470>;
273
274 qcom,cpr-enable;
275 qcom,cpr-hw-closed-loop;
276
277 qcom,cpr-panic-reg-addr-list =
278 <0x17db3a84 0x17830c18>;
279 qcom,cpr-panic-reg-name-list =
280 "APSS_GOLD_CPRH_STATUS_0", "GOLD_SAW4_PMIC_STS";
281
282 qcom,cpr-aging-ref-voltage = <1136000>;
283 vdd-supply = <&pm8998_s12>;
284
285 thread@0 {
286 qcom,cpr-thread-id = <0>;
287 qcom,cpr-consecutive-up = <0>;
288 qcom,cpr-consecutive-down = <0>;
289 qcom,cpr-up-threshold = <2>;
290 qcom,cpr-down-threshold = <2>;
291
292 apc1_perfcl_vreg: regulator {
293 regulator-name = "apc1_perfcl_corner";
294 regulator-min-microvolt = <1>;
295 regulator-max-microvolt = <33>;
296
297 qcom,cpr-fuse-corners = <5>;
298 qcom,cpr-fuse-combos = <16>;
299 qcom,cpr-speed-bins = <2>;
300 qcom,cpr-speed-bin-corners = <28 31>;
301 qcom,cpr-corners =
302 /* Speed bin 0 */
303 <28 28 28 28 28 28 28 28>,
304 /* Speed bin 1 */
305 <31 31 31 31 31 31 31 31>;
306
307 qcom,cpr-corner-fmax-map =
308 /* Speed bin 0 */
309 <7 14 22 27 28>,
310 /* Speed bin 1 */
311 <7 14 22 27 31>;
312
313 qcom,cpr-voltage-ceiling =
314 /* Speed bin 0 */
315 <828000 828000 828000 828000 828000
316 828000 828000 828000 828000 828000
317 828000 828000 828000 828000 828000
318 828000 828000 828000 884000 884000
319 884000 884000 1104000 1104000 1104000
320 1104000 1136000 1136000>,
321 /* Speed bin 1 */
322 <828000 828000 828000 828000 828000
323 828000 828000 828000 828000 828000
324 828000 828000 828000 828000 828000
325 828000 828000 828000 884000 884000
326 884000 884000 1104000 1104000 1104000
327 1104000 1136000 1136000 1136000 1136000
328 1136000>;
329
330 qcom,cpr-voltage-floor =
331 /* Speed bin 0 */
332 <568000 568000 568000 568000 568000
333 568000 568000 568000 568000 568000
334 568000 568000 568000 568000 568000
335 568000 568000 568000 568000 568000
336 568000 568000 568000 568000 568000
337 568000 568000 568000>,
338 /* Speed bin 1 */
339 <568000 568000 568000 568000 568000
340 568000 568000 568000 568000 568000
341 568000 568000 568000 568000 568000
342 568000 568000 568000 568000 568000
343 568000 568000 568000 568000 568000
344 568000 568000 568000 568000 568000
345 568000>;
346
347 qcom,cpr-floor-to-ceiling-max-range =
348 /* Speed bin 0 */
349 <32000 32000 32000 32000 32000
350 32000 32000 32000 32000 32000
351 32000 32000 32000 32000 32000
352 32000 32000 32000 32000 32000
353 32000 32000 32000 32000 32000
354 32000 32000 32000>,
355 /* Speed bin 1 */
356 <32000 32000 32000 32000 32000
357 32000 32000 32000 32000 32000
358 32000 32000 32000 32000 32000
359 32000 32000 32000 32000 32000
360 32000 32000 32000 32000 32000
361 32000 32000 40000 40000 40000
362 40000>;
363
364 qcom,corner-frequencies =
365 /* Speed bin 0 */
366 <300000000 403200000 480000000
367 576000000 652800000 748800000
368 825600000 902400000 979200000
369 1056000000 1132800000 1209600000
370 1286400000 1363200000 1459200000
371 1536000000 1612800000 1689600000
372 1766400000 1843200000 1920000000
373 1996800000 2092800000 2169600000
374 2246400000 2323200000 2400000000
375 2400000000>,
376 /* Speed bin 1 */
377 <300000000 403200000 480000000
378 576000000 652800000 748800000
379 825600000 902400000 979200000
380 1056000000 1132800000 1209600000
381 1286400000 1363200000 1459200000
382 1536000000 1612800000 1689600000
383 1766400000 1843200000 1920000000
384 1996800000 2092800000 2169600000
385 2246400000 2323200000 2400000000
386 2476800000 2553600000 2630400000
387 2707200000>;
388
389 qcom,cpr-ro-scaling-factor =
390 <2857 3056 2828 2952 2699 2796 2447
391 2631 2630 2579 2244 3343 3287 3137
392 3164 2656>,
393 <2857 3056 2828 2952 2699 2796 2447
394 2631 2630 2579 2244 3343 3287 3137
395 3164 2656>,
396 <2086 2208 2273 2408 2203 2327 2213
397 2340 1755 2039 2049 2474 2437 2618
398 2003 1675>,
399 <2086 2208 2273 2408 2203 2327 2213
400 2340 1755 2039 2049 2474 2437 2618
401 2003 1675>,
402 <2086 2208 2273 2408 2203 2327 2213
403 2340 1755 2039 2049 2474 2437 2618
404 2003 1675>;
405
406 qcom,cpr-open-loop-voltage-fuse-adjustment =
407 <100000 100000 100000 100000 100000>;
408
409 qcom,cpr-closed-loop-voltage-fuse-adjustment =
410 <100000 100000 100000 100000 100000>;
411
412 qcom,allow-voltage-interpolation;
413 qcom,allow-quotient-interpolation;
414 qcom,cpr-scaled-open-loop-voltage-as-ceiling;
415
416 qcom,cpr-aging-max-voltage-adjustment = <15000>;
417 qcom,cpr-aging-ref-corner = <27 31>;
418 qcom,cpr-aging-ro-scaling-factor = <1700>;
419 qcom,allow-aging-voltage-adjustment =
420 /* Speed bin 0 */
421 <0 1 1 1 1 1 1 1>,
422 /* Speed bin 1 */
423 <0 1 1 1 1 1 1 1>;
424 qcom,allow-aging-open-loop-voltage-adjustment =
425 <1>;
426 };
427 };
428 };
429};
430
431&clock_cpucc {
Deepak Katragaddaa442baa2017-07-11 12:27:06 -0700[diff] [blame]432 compatible = "qcom,clk-cpu-osm-v2";
433
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]434 vdd-l3-supply = <&apc0_l3_vreg>;
435 vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
Deepak Katragaddaa442baa2017-07-11 12:27:06 -0700[diff] [blame]436 vdd-perfcl-supply = <&apc1_perfcl_vreg>;
437
438 qcom,l3-speedbin0-v0 =
439 < 300000000 0x000c000f 0x00002020 0x1 1 >,
440 < 403200000 0x500c0115 0x00002020 0x1 2 >,
441 < 480000000 0x50140219 0x00002020 0x1 3 >,
442 < 576000000 0x5014031e 0x00002020 0x1 4 >,
443 < 652800000 0x401c0422 0x00002020 0x1 5 >,
444 < 748800000 0x401c0527 0x00002020 0x1 6 >,
445 < 844800000 0x4024062c 0x00002323 0x2 7 >,
446 < 940800000 0x40240731 0x00002727 0x2 8 >,
447 < 1036800000 0x40240836 0x00002b2b 0x2 9 >,
448 < 1132800000 0x402c093b 0x00002f2f 0x2 10 >,
449 < 1209600000 0x402c0a3f 0x00003232 0x2 11 >,
450 < 1305600000 0x40340b44 0x00003636 0x2 12 >,
451 < 1401600000 0x40340c49 0x00003a3a 0x2 13 >,
452 < 1478400000 0x403c0d4d 0x00003e3e 0x2 14 >;
453
454 qcom,pwrcl-speedbin0-v0 =
455 < 300000000 0x000c000f 0x00002020 0x1 1 >,
456 < 403200000 0x500c0115 0x00002020 0x1 2 >,
457 < 480000000 0x50140219 0x00002020 0x1 3 >,
458 < 576000000 0x5014031e 0x00002020 0x1 4 >,
459 < 652800000 0x401c0422 0x00002020 0x1 5 >,
460 < 748800000 0x401c0527 0x00002020 0x1 6 >,
461 < 825600000 0x401c062b 0x00002222 0x1 7 >,
462 < 902400000 0x4024072f 0x00002626 0x1 8 >,
463 < 979200000 0x40240833 0x00002929 0x1 9 >,
464 < 1056000000 0x402c0937 0x00002c2c 0x2 10 >,
465 < 1132800000 0x402c0a3b 0x00002f2f 0x2 11 >,
466 < 1228800000 0x402c0b40 0x00003333 0x2 12 >,
467 < 1324800000 0x40340c45 0x00003737 0x2 13 >,
468 < 1420800000 0x40340d4a 0x00003b3b 0x2 14 >,
469 < 1516800000 0x403c0e4f 0x00003f3f 0x2 15 >,
470 < 1612800000 0x403c0f54 0x00004343 0x2 16 >,
471 < 1689600000 0x40441058 0x00004646 0x2 17 >,
472 < 1766400000 0x4044115c 0x00004a4a 0x2 18 >;
473
474 qcom,perfcl-speedbin0-v0 =
475 < 300000000 0x000c000f 0x00002020 0x1 1 >,
476 < 403200000 0x500c0115 0x00002020 0x1 2 >,
477 < 480000000 0x50140219 0x00002020 0x1 3 >,
478 < 576000000 0x5014031e 0x00002020 0x1 4 >,
479 < 652800000 0x401c0422 0x00002020 0x1 5 >,
480 < 748800000 0x401c0527 0x00002020 0x1 6 >,
481 < 825600000 0x401c062b 0x00002222 0x1 7 >,
482 < 902400000 0x4024072f 0x00002626 0x1 8 >,
483 < 979200000 0x40240833 0x00002929 0x1 9 >,
484 < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
485 < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
486 < 1209600000 0x402c0b3f 0x00003232 0x2 12 >,
487 < 1286400000 0x40340c43 0x00003636 0x2 13 >,
488 < 1363200000 0x40340d47 0x00003939 0x2 14 >,
489 < 1459200000 0x403c0e4c 0x00003d3d 0x2 15 >,
490 < 1536000000 0x403c0f50 0x00004040 0x2 16 >,
491 < 1612800000 0x403c1054 0x00004343 0x2 17 >,
492 < 1689600000 0x40441158 0x00004646 0x2 18 >,
493 < 1766400000 0x4044125c 0x00004a4a 0x2 19 >,
494 < 1843200000 0x40441360 0x00004d4d 0x2 20 >,
495 < 1920000000 0x404c1464 0x00005050 0x2 21 >,
496 < 1996800000 0x404c1568 0x00005353 0x2 22 >,
497 < 2092800000 0x4054166d 0x00005757 0x2 23 >,
498 < 2169600000 0x40541771 0x00005a5a 0x2 24 >,
499 < 2246400000 0x40541875 0x00005e5e 0x2 25 >,
500 < 2323200000 0x40541979 0x00006161 0x2 26 >,
501 < 2400000000 0x40541a7d 0x00006464 0x2 27 >;
502
503 qcom,perfcl-speedbin1-v0 =
504 < 300000000 0x000c000f 0x00002020 0x1 1 >,
505 < 403200000 0x500c0115 0x00002020 0x1 2 >,
506 < 480000000 0x50140219 0x00002020 0x1 3 >,
507 < 576000000 0x5014031e 0x00002020 0x1 4 >,
508 < 652800000 0x401c0422 0x00002020 0x1 5 >,
509 < 748800000 0x401c0527 0x00002020 0x1 6 >,
510 < 825600000 0x401c062b 0x00002222 0x1 7 >,
511 < 902400000 0x4024072f 0x00002626 0x1 8 >,
512 < 979200000 0x40240833 0x00002929 0x1 9 >,
513 < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
514 < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
515 < 1209600000 0x402c0b3f 0x00003232 0x2 12 >,
516 < 1286400000 0x40340c43 0x00003636 0x2 13 >,
517 < 1363200000 0x40340d47 0x00003939 0x2 14 >,
518 < 1459200000 0x403c0e4c 0x00003d3d 0x2 15 >,
519 < 1536000000 0x403c0f50 0x00004040 0x2 16 >,
520 < 1612800000 0x403c1054 0x00004343 0x2 17 >,
521 < 1689600000 0x40441158 0x00004646 0x2 18 >,
522 < 1766400000 0x4044125c 0x00004a4a 0x2 19 >,
523 < 1843200000 0x40441360 0x00004d4d 0x2 20 >,
524 < 1920000000 0x404c1464 0x00005050 0x2 21 >,
525 < 1996800000 0x404c1568 0x00005353 0x2 22 >,
526 < 2092800000 0x4054166d 0x00005757 0x2 23 >,
527 < 2169600000 0x40541771 0x00005a5a 0x2 24 >,
528 < 2246400000 0x40541875 0x00005e5e 0x2 25 >,
529 < 2323200000 0x40541979 0x00006161 0x2 26 >,
530 < 2400000000 0x40541a7d 0x00006464 0x2 27 >,
531 < 2476800000 0x40541b81 0x00006767 0x2 28 >,
532 < 2553600000 0x40541c85 0x00006a6a 0x2 29 >,
533 < 2630400000 0x40541d89 0x00006e6e 0x2 30 >,
534 < 2707200000 0x40541e8d 0x00007171 0x2 31 >;
Deepak Katragadda30d72dd2017-08-01 13:56:00 -0700[diff] [blame]535
536 qcom,l3-memacc-level-vc-bin0 = <8 13>;
537
538 qcom,pwrcl-memacc-level-vc-bin0 = <12 16>;
539
540 qcom,perfcl-memacc-level-vc-bin0 = <14 22>;
541 qcom,perfcl-memacc-level-vc-bin1 = <14 22>;
David Collinsf5764762017-07-20 16:42:42 -0700[diff] [blame]542};
543
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]544&clock_gcc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame^]545 compatible = "qcom,gcc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]546};
547
548&clock_camcc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame^]549 compatible = "qcom,cam_cc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]550};
551
552&clock_dispcc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame^]553 compatible = "qcom,dispcc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]554};
555
Vicky Wallace1762ab32017-07-12 19:00:04 -0700[diff] [blame]556&clock_gpucc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame^]557 compatible = "qcom,gpucc-sdm845-v2", "syscon";
Vicky Wallace1762ab32017-07-12 19:00:04 -0700[diff] [blame]558};
559
560&clock_gfx {
561 compatible = "qcom,gfxcc-sdm845-v2";
562};
563
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]564&clock_videocc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700[diff] [blame^]565 compatible = "qcom,video_cc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700[diff] [blame]566};
Praneeth Paladugu55381212017-07-05 15:02:44 -0700[diff] [blame]567
Deepak Katragadda0836d182017-07-27 14:23:02 -0700[diff] [blame]568&clock_aop {
569 compatible = "qcom,aop-qmp-clk-v2";
570};
571
Praneeth Paladugu55381212017-07-05 15:02:44 -0700[diff] [blame]572&msm_vidc {
573 qcom,allowed-clock-rates = <100000000 200000000 330000000
574 404000000 444000000 533000000>;
575};
Reut Zysman861fd6c2017-07-30 15:39:13 +0300[diff] [blame]576
577&spss_utils {
578 qcom,spss-dev-firmware-name = "spss2d"; /* 8 chars max */
579 qcom,spss-test-firmware-name = "spss2t"; /* 8 chars max */
580 qcom,spss-prod-firmware-name = "spss2p"; /* 8 chars max */
581};
Narendra Muppalla4efd3442017-07-24 17:36:15 -0700[diff] [blame]582
583&mdss_mdp {
584 clock-max-rate = <0 0 0 0 430000000 19200000 0>;
585};