Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2005-2011 Atheros Communications Inc. |
| 3 | * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. |
| 4 | * |
| 5 | * Permission to use, copy, modify, and/or distribute this software for any |
| 6 | * purpose with or without fee is hereby granted, provided that the above |
| 7 | * copyright notice and this permission notice appear in all copies. |
| 8 | * |
| 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 16 | */ |
| 17 | |
| 18 | #ifndef _HW_H_ |
| 19 | #define _HW_H_ |
| 20 | |
| 21 | #include "targaddrs.h" |
| 22 | |
Kalle Valo | a58227e | 2014-10-13 09:40:59 +0300 | [diff] [blame] | 23 | #define ATH10K_FW_DIR "ath10k" |
| 24 | |
Bartosz Markowski | 079a049 | 2015-11-05 09:50:42 +0100 | [diff] [blame] | 25 | #define QCA988X_2_0_DEVICE_ID (0x003c) |
| 26 | #define QCA6164_2_1_DEVICE_ID (0x0041) |
| 27 | #define QCA6174_2_1_DEVICE_ID (0x003e) |
| 28 | #define QCA99X0_2_0_DEVICE_ID (0x0040) |
Anilkumar Kolli | e565c31 | 2016-06-30 15:24:00 +0300 | [diff] [blame] | 29 | #define QCA9888_2_0_DEVICE_ID (0x0056) |
Vasanthakumar Thiagarajan | 651b4cd | 2016-05-23 23:12:45 +0300 | [diff] [blame] | 30 | #define QCA9984_1_0_DEVICE_ID (0x0046) |
Bartosz Markowski | 079a049 | 2015-11-05 09:50:42 +0100 | [diff] [blame] | 31 | #define QCA9377_1_0_DEVICE_ID (0x0042) |
Sven Eckelmann | 6fd3dd7 | 2016-06-02 17:59:49 +0300 | [diff] [blame] | 32 | #define QCA9887_1_0_DEVICE_ID (0x0050) |
Bartosz Markowski | 079a049 | 2015-11-05 09:50:42 +0100 | [diff] [blame] | 33 | |
Kalle Valo | e01ae68 | 2013-09-01 11:22:14 +0300 | [diff] [blame] | 34 | /* QCA988X 1.0 definitions (unsupported) */ |
| 35 | #define QCA988X_HW_1_0_CHIP_ID_REV 0x0 |
| 36 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 37 | /* QCA988X 2.0 definitions */ |
| 38 | #define QCA988X_HW_2_0_VERSION 0x4100016c |
Kalle Valo | e01ae68 | 2013-09-01 11:22:14 +0300 | [diff] [blame] | 39 | #define QCA988X_HW_2_0_CHIP_ID_REV 0x2 |
Kalle Valo | a58227e | 2014-10-13 09:40:59 +0300 | [diff] [blame] | 40 | #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0" |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 41 | #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" |
| 42 | #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 |
| 43 | |
Sven Eckelmann | 6fd3dd7 | 2016-06-02 17:59:49 +0300 | [diff] [blame] | 44 | /* QCA9887 1.0 definitions */ |
| 45 | #define QCA9887_HW_1_0_VERSION 0x4100016d |
| 46 | #define QCA9887_HW_1_0_CHIP_ID_REV 0 |
| 47 | #define QCA9887_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9887/hw1.0" |
| 48 | #define QCA9887_HW_1_0_BOARD_DATA_FILE "board.bin" |
| 49 | #define QCA9887_HW_1_0_PATCH_LOAD_ADDR 0x1234 |
| 50 | |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 51 | /* QCA6174 target BMI version signatures */ |
| 52 | #define QCA6174_HW_1_0_VERSION 0x05000000 |
| 53 | #define QCA6174_HW_1_1_VERSION 0x05000001 |
| 54 | #define QCA6174_HW_1_3_VERSION 0x05000003 |
| 55 | #define QCA6174_HW_2_1_VERSION 0x05010000 |
| 56 | #define QCA6174_HW_3_0_VERSION 0x05020000 |
Michal Kazior | 608b8f7 | 2015-01-29 13:24:33 +0100 | [diff] [blame] | 57 | #define QCA6174_HW_3_2_VERSION 0x05030000 |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 58 | |
Bartosz Markowski | 034074f | 2015-11-05 09:50:43 +0100 | [diff] [blame] | 59 | /* QCA9377 target BMI version signatures */ |
| 60 | #define QCA9377_HW_1_0_DEV_VERSION 0x05020000 |
Bartosz Markowski | 12551ce | 2015-11-05 09:50:40 +0100 | [diff] [blame] | 61 | #define QCA9377_HW_1_1_DEV_VERSION 0x05020001 |
| 62 | |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 63 | enum qca6174_pci_rev { |
| 64 | QCA6174_PCI_REV_1_1 = 0x11, |
| 65 | QCA6174_PCI_REV_1_3 = 0x13, |
| 66 | QCA6174_PCI_REV_2_0 = 0x20, |
| 67 | QCA6174_PCI_REV_3_0 = 0x30, |
| 68 | }; |
| 69 | |
| 70 | enum qca6174_chip_id_rev { |
| 71 | QCA6174_HW_1_0_CHIP_ID_REV = 0, |
| 72 | QCA6174_HW_1_1_CHIP_ID_REV = 1, |
| 73 | QCA6174_HW_1_3_CHIP_ID_REV = 2, |
| 74 | QCA6174_HW_2_1_CHIP_ID_REV = 4, |
| 75 | QCA6174_HW_2_2_CHIP_ID_REV = 5, |
| 76 | QCA6174_HW_3_0_CHIP_ID_REV = 8, |
| 77 | QCA6174_HW_3_1_CHIP_ID_REV = 9, |
| 78 | QCA6174_HW_3_2_CHIP_ID_REV = 10, |
| 79 | }; |
| 80 | |
Bartosz Markowski | 12551ce | 2015-11-05 09:50:40 +0100 | [diff] [blame] | 81 | enum qca9377_chip_id_rev { |
Bartosz Markowski | 034074f | 2015-11-05 09:50:43 +0100 | [diff] [blame] | 82 | QCA9377_HW_1_0_CHIP_ID_REV = 0x0, |
Bartosz Markowski | 12551ce | 2015-11-05 09:50:40 +0100 | [diff] [blame] | 83 | QCA9377_HW_1_1_CHIP_ID_REV = 0x1, |
| 84 | }; |
| 85 | |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 86 | #define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1" |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 87 | #define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin" |
| 88 | #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234 |
| 89 | |
| 90 | #define QCA6174_HW_3_0_FW_DIR "ath10k/QCA6174/hw3.0" |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 91 | #define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin" |
| 92 | #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234 |
| 93 | |
Vasanthakumar Thiagarajan | 8bd4702 | 2015-06-18 12:31:03 +0530 | [diff] [blame] | 94 | /* QCA99X0 1.0 definitions (unsupported) */ |
| 95 | #define QCA99X0_HW_1_0_CHIP_ID_REV 0x0 |
| 96 | |
| 97 | /* QCA99X0 2.0 definitions */ |
| 98 | #define QCA99X0_HW_2_0_DEV_VERSION 0x01000000 |
| 99 | #define QCA99X0_HW_2_0_CHIP_ID_REV 0x1 |
| 100 | #define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0" |
Vasanthakumar Thiagarajan | 8bd4702 | 2015-06-18 12:31:03 +0530 | [diff] [blame] | 101 | #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin" |
| 102 | #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234 |
| 103 | |
Vasanthakumar Thiagarajan | 651b4cd | 2016-05-23 23:12:45 +0300 | [diff] [blame] | 104 | /* QCA9984 1.0 defines */ |
| 105 | #define QCA9984_HW_1_0_DEV_VERSION 0x1000000 |
| 106 | #define QCA9984_HW_DEV_TYPE 0xa |
| 107 | #define QCA9984_HW_1_0_CHIP_ID_REV 0x0 |
| 108 | #define QCA9984_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9984/hw1.0" |
| 109 | #define QCA9984_HW_1_0_BOARD_DATA_FILE "board.bin" |
| 110 | #define QCA9984_HW_1_0_PATCH_LOAD_ADDR 0x1234 |
| 111 | |
Anilkumar Kolli | e565c31 | 2016-06-30 15:24:00 +0300 | [diff] [blame] | 112 | /* QCA9888 2.0 defines */ |
| 113 | #define QCA9888_HW_2_0_DEV_VERSION 0x1000000 |
| 114 | #define QCA9888_HW_DEV_TYPE 0xc |
| 115 | #define QCA9888_HW_2_0_CHIP_ID_REV 0x0 |
| 116 | #define QCA9888_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA9888/hw2.0" |
| 117 | #define QCA9888_HW_2_0_BOARD_DATA_FILE "board.bin" |
| 118 | #define QCA9888_HW_2_0_PATCH_LOAD_ADDR 0x1234 |
| 119 | |
Bartosz Markowski | a226b51 | 2015-10-28 15:09:53 +0100 | [diff] [blame] | 120 | /* QCA9377 1.0 definitions */ |
Bartosz Markowski | a226b51 | 2015-10-28 15:09:53 +0100 | [diff] [blame] | 121 | #define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0" |
Bartosz Markowski | a226b51 | 2015-10-28 15:09:53 +0100 | [diff] [blame] | 122 | #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin" |
| 123 | #define QCA9377_HW_1_0_PATCH_LOAD_ADDR 0x1234 |
| 124 | |
Raja Mani | b1a958c | 2016-01-29 16:35:11 +0530 | [diff] [blame] | 125 | /* QCA4019 1.0 definitions */ |
| 126 | #define QCA4019_HW_1_0_DEV_VERSION 0x01000000 |
| 127 | #define QCA4019_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA4019/hw1.0" |
Raja Mani | b1a958c | 2016-01-29 16:35:11 +0530 | [diff] [blame] | 128 | #define QCA4019_HW_1_0_BOARD_DATA_FILE "board.bin" |
| 129 | #define QCA4019_HW_1_0_PATCH_LOAD_ADDR 0x1234 |
| 130 | |
Kalle Valo | 1a22243 | 2013-09-27 19:55:07 +0300 | [diff] [blame] | 131 | #define ATH10K_FW_API2_FILE "firmware-2.bin" |
Michal Kazior | 24c88f7 | 2014-07-25 13:32:17 +0200 | [diff] [blame] | 132 | #define ATH10K_FW_API3_FILE "firmware-3.bin" |
Kalle Valo | 1a22243 | 2013-09-27 19:55:07 +0300 | [diff] [blame] | 133 | |
Rajkumar Manoharan | 4a16fbe | 2014-12-17 12:21:12 +0200 | [diff] [blame] | 134 | /* added support for ATH10K_FW_IE_WMI_OP_VERSION */ |
| 135 | #define ATH10K_FW_API4_FILE "firmware-4.bin" |
| 136 | |
Kalle Valo | 53513c3 | 2015-03-25 13:12:42 +0200 | [diff] [blame] | 137 | /* HTT id conflict fix for management frames over HTT */ |
| 138 | #define ATH10K_FW_API5_FILE "firmware-5.bin" |
| 139 | |
Kalle Valo | 43d2a30 | 2014-09-10 18:23:30 +0300 | [diff] [blame] | 140 | #define ATH10K_FW_UTF_FILE "utf.bin" |
Alan Liu | a81a98c | 2015-10-28 21:38:32 +0200 | [diff] [blame] | 141 | #define ATH10K_FW_UTF_API2_FILE "utf-2.bin" |
Kalle Valo | 43d2a30 | 2014-09-10 18:23:30 +0300 | [diff] [blame] | 142 | |
Kalle Valo | 1a22243 | 2013-09-27 19:55:07 +0300 | [diff] [blame] | 143 | /* includes also the null byte */ |
| 144 | #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" |
Manikanta Pubbisetty | 0a51b34 | 2015-10-09 11:55:58 +0300 | [diff] [blame] | 145 | #define ATH10K_BOARD_MAGIC "QCA-ATH10K-BOARD" |
| 146 | |
| 147 | #define ATH10K_BOARD_API2_FILE "board-2.bin" |
Kalle Valo | 1a22243 | 2013-09-27 19:55:07 +0300 | [diff] [blame] | 148 | |
Ben Greear | 384914b | 2014-08-25 08:37:32 +0300 | [diff] [blame] | 149 | #define REG_DUMP_COUNT_QCA988X 60 |
| 150 | |
Kalle Valo | 1a22243 | 2013-09-27 19:55:07 +0300 | [diff] [blame] | 151 | struct ath10k_fw_ie { |
| 152 | __le32 id; |
| 153 | __le32 len; |
| 154 | u8 data[0]; |
| 155 | }; |
| 156 | |
| 157 | enum ath10k_fw_ie_type { |
| 158 | ATH10K_FW_IE_FW_VERSION = 0, |
| 159 | ATH10K_FW_IE_TIMESTAMP = 1, |
| 160 | ATH10K_FW_IE_FEATURES = 2, |
| 161 | ATH10K_FW_IE_FW_IMAGE = 3, |
| 162 | ATH10K_FW_IE_OTP_IMAGE = 4, |
Kalle Valo | 202e86e | 2014-12-03 10:10:08 +0200 | [diff] [blame] | 163 | |
| 164 | /* WMI "operations" interface version, 32 bit value. Supported from |
| 165 | * FW API 4 and above. |
| 166 | */ |
| 167 | ATH10K_FW_IE_WMI_OP_VERSION = 5, |
Rajkumar Manoharan | 8348db2 | 2015-03-25 13:12:27 +0200 | [diff] [blame] | 168 | |
| 169 | /* HTT "operations" interface version, 32 bit value. Supported from |
| 170 | * FW API 5 and above. |
| 171 | */ |
| 172 | ATH10K_FW_IE_HTT_OP_VERSION = 6, |
Vasanthakumar Thiagarajan | dcb02db | 2015-06-18 12:31:09 +0530 | [diff] [blame] | 173 | |
| 174 | /* Code swap image for firmware binary */ |
| 175 | ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7, |
Kalle Valo | 202e86e | 2014-12-03 10:10:08 +0200 | [diff] [blame] | 176 | }; |
| 177 | |
| 178 | enum ath10k_fw_wmi_op_version { |
| 179 | ATH10K_FW_WMI_OP_VERSION_UNSET = 0, |
| 180 | |
| 181 | ATH10K_FW_WMI_OP_VERSION_MAIN = 1, |
| 182 | ATH10K_FW_WMI_OP_VERSION_10_1 = 2, |
| 183 | ATH10K_FW_WMI_OP_VERSION_10_2 = 3, |
Michal Kazior | ca996ec | 2014-12-03 10:11:32 +0200 | [diff] [blame] | 184 | ATH10K_FW_WMI_OP_VERSION_TLV = 4, |
Rajkumar Manoharan | 4a16fbe | 2014-12-17 12:21:12 +0200 | [diff] [blame] | 185 | ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5, |
Raja Mani | 9bd2132 | 2015-06-22 20:10:09 +0530 | [diff] [blame] | 186 | ATH10K_FW_WMI_OP_VERSION_10_4 = 6, |
Kalle Valo | 202e86e | 2014-12-03 10:10:08 +0200 | [diff] [blame] | 187 | |
| 188 | /* keep last */ |
| 189 | ATH10K_FW_WMI_OP_VERSION_MAX, |
Kalle Valo | 1a22243 | 2013-09-27 19:55:07 +0300 | [diff] [blame] | 190 | }; |
| 191 | |
Rajkumar Manoharan | 8348db2 | 2015-03-25 13:12:27 +0200 | [diff] [blame] | 192 | enum ath10k_fw_htt_op_version { |
| 193 | ATH10K_FW_HTT_OP_VERSION_UNSET = 0, |
| 194 | |
| 195 | ATH10K_FW_HTT_OP_VERSION_MAIN = 1, |
| 196 | |
| 197 | /* also used in 10.2 and 10.2.4 branches */ |
| 198 | ATH10K_FW_HTT_OP_VERSION_10_1 = 2, |
| 199 | |
| 200 | ATH10K_FW_HTT_OP_VERSION_TLV = 3, |
| 201 | |
Raja Mani | 721ad3c | 2015-06-22 20:22:24 +0530 | [diff] [blame] | 202 | ATH10K_FW_HTT_OP_VERSION_10_4 = 4, |
| 203 | |
Rajkumar Manoharan | 8348db2 | 2015-03-25 13:12:27 +0200 | [diff] [blame] | 204 | /* keep last */ |
| 205 | ATH10K_FW_HTT_OP_VERSION_MAX, |
| 206 | }; |
| 207 | |
Manikanta Pubbisetty | 0a51b34 | 2015-10-09 11:55:58 +0300 | [diff] [blame] | 208 | enum ath10k_bd_ie_type { |
| 209 | /* contains sub IEs of enum ath10k_bd_ie_board_type */ |
| 210 | ATH10K_BD_IE_BOARD = 0, |
| 211 | }; |
| 212 | |
| 213 | enum ath10k_bd_ie_board_type { |
| 214 | ATH10K_BD_IE_BOARD_NAME = 0, |
| 215 | ATH10K_BD_IE_BOARD_DATA = 1, |
| 216 | }; |
| 217 | |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 218 | enum ath10k_hw_rev { |
| 219 | ATH10K_HW_QCA988X, |
| 220 | ATH10K_HW_QCA6174, |
Vasanthakumar Thiagarajan | 8bd4702 | 2015-06-18 12:31:03 +0530 | [diff] [blame] | 221 | ATH10K_HW_QCA99X0, |
Anilkumar Kolli | e565c31 | 2016-06-30 15:24:00 +0300 | [diff] [blame] | 222 | ATH10K_HW_QCA9888, |
Vasanthakumar Thiagarajan | 651b4cd | 2016-05-23 23:12:45 +0300 | [diff] [blame] | 223 | ATH10K_HW_QCA9984, |
Bartosz Markowski | a226b51 | 2015-10-28 15:09:53 +0100 | [diff] [blame] | 224 | ATH10K_HW_QCA9377, |
Raja Mani | 0b523ce | 2016-01-27 15:24:25 +0530 | [diff] [blame] | 225 | ATH10K_HW_QCA4019, |
Sven Eckelmann | 6fd3dd7 | 2016-06-02 17:59:49 +0300 | [diff] [blame] | 226 | ATH10K_HW_QCA9887, |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 227 | }; |
| 228 | |
| 229 | struct ath10k_hw_regs { |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 230 | u32 rtc_soc_base_address; |
| 231 | u32 rtc_wmac_base_address; |
| 232 | u32 soc_core_base_address; |
| 233 | u32 ce_wrapper_base_address; |
| 234 | u32 ce0_base_address; |
| 235 | u32 ce1_base_address; |
| 236 | u32 ce2_base_address; |
| 237 | u32 ce3_base_address; |
| 238 | u32 ce4_base_address; |
| 239 | u32 ce5_base_address; |
| 240 | u32 ce6_base_address; |
| 241 | u32 ce7_base_address; |
| 242 | u32 soc_reset_control_si0_rst_mask; |
| 243 | u32 soc_reset_control_ce_rst_mask; |
| 244 | u32 soc_chip_id_address; |
| 245 | u32 scratch_3_address; |
Vasanthakumar Thiagarajan | a521ee9 | 2015-06-18 12:31:02 +0530 | [diff] [blame] | 246 | u32 fw_indicator_address; |
| 247 | u32 pcie_local_base_address; |
| 248 | u32 ce_wrap_intr_sum_host_msi_lsb; |
| 249 | u32 ce_wrap_intr_sum_host_msi_mask; |
| 250 | u32 pcie_intr_fw_mask; |
| 251 | u32 pcie_intr_ce_mask_all; |
| 252 | u32 pcie_intr_clr_address; |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 253 | }; |
| 254 | |
| 255 | extern const struct ath10k_hw_regs qca988x_regs; |
| 256 | extern const struct ath10k_hw_regs qca6174_regs; |
Vasanthakumar Thiagarajan | 8bd4702 | 2015-06-18 12:31:03 +0530 | [diff] [blame] | 257 | extern const struct ath10k_hw_regs qca99x0_regs; |
Raja Mani | 37a219a | 2016-01-27 15:24:26 +0530 | [diff] [blame] | 258 | extern const struct ath10k_hw_regs qca4019_regs; |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 259 | |
Vasanthakumar Thiagarajan | 2f2cfc4 | 2015-06-18 12:31:01 +0530 | [diff] [blame] | 260 | struct ath10k_hw_values { |
| 261 | u32 rtc_state_val_on; |
| 262 | u8 ce_count; |
| 263 | u8 msi_assign_ce_max; |
| 264 | u8 num_target_ce_config_wlan; |
Vasanthakumar Thiagarajan | 2adf99c | 2015-06-18 12:31:07 +0530 | [diff] [blame] | 265 | u16 ce_desc_meta_data_mask; |
| 266 | u8 ce_desc_meta_data_lsb; |
Vasanthakumar Thiagarajan | 2f2cfc4 | 2015-06-18 12:31:01 +0530 | [diff] [blame] | 267 | }; |
| 268 | |
| 269 | extern const struct ath10k_hw_values qca988x_values; |
| 270 | extern const struct ath10k_hw_values qca6174_values; |
Vasanthakumar Thiagarajan | 8bd4702 | 2015-06-18 12:31:03 +0530 | [diff] [blame] | 271 | extern const struct ath10k_hw_values qca99x0_values; |
Anilkumar Kolli | e565c31 | 2016-06-30 15:24:00 +0300 | [diff] [blame] | 272 | extern const struct ath10k_hw_values qca9888_values; |
Raja Mani | 37a219a | 2016-01-27 15:24:26 +0530 | [diff] [blame] | 273 | extern const struct ath10k_hw_values qca4019_values; |
Vasanthakumar Thiagarajan | 2f2cfc4 | 2015-06-18 12:31:01 +0530 | [diff] [blame] | 274 | |
Michal Kazior | 587f703 | 2015-05-25 14:06:18 +0200 | [diff] [blame] | 275 | void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, |
| 276 | u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev); |
| 277 | |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 278 | #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X) |
Sven Eckelmann | 6fd3dd7 | 2016-06-02 17:59:49 +0300 | [diff] [blame] | 279 | #define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887) |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 280 | #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174) |
Vasanthakumar Thiagarajan | 8bd4702 | 2015-06-18 12:31:03 +0530 | [diff] [blame] | 281 | #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0) |
Anilkumar Kolli | e565c31 | 2016-06-30 15:24:00 +0300 | [diff] [blame] | 282 | #define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888) |
Vasanthakumar Thiagarajan | 651b4cd | 2016-05-23 23:12:45 +0300 | [diff] [blame] | 283 | #define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984) |
Bartosz Markowski | a226b51 | 2015-10-28 15:09:53 +0100 | [diff] [blame] | 284 | #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377) |
Raja Mani | 0b523ce | 2016-01-27 15:24:25 +0530 | [diff] [blame] | 285 | #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019) |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 286 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 287 | /* Known pecularities: |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 288 | * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap |
| 289 | * - raw have FCS, nwifi doesn't |
| 290 | * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher |
| 291 | * param, llc/snap) are aligned to 4byte boundaries each */ |
| 292 | enum ath10k_hw_txrx_mode { |
| 293 | ATH10K_HW_TXRX_RAW = 0, |
David Liu | ccec903 | 2015-07-24 20:25:32 +0300 | [diff] [blame] | 294 | |
| 295 | /* Native Wifi decap mode is used to align IP frames to 4-byte |
| 296 | * boundaries and avoid a very expensive re-alignment in mac80211. |
| 297 | */ |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 298 | ATH10K_HW_TXRX_NATIVE_WIFI = 1, |
| 299 | ATH10K_HW_TXRX_ETHERNET = 2, |
Michal Kazior | 961d4c3 | 2013-08-09 10:13:34 +0200 | [diff] [blame] | 300 | |
| 301 | /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ |
| 302 | ATH10K_HW_TXRX_MGMT = 3, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 303 | }; |
| 304 | |
| 305 | enum ath10k_mcast2ucast_mode { |
| 306 | ATH10K_MCAST2UCAST_DISABLED = 0, |
| 307 | ATH10K_MCAST2UCAST_ENABLED = 1, |
| 308 | }; |
| 309 | |
Michal Kazior | 6aa4cf1 | 2015-03-30 09:51:55 +0300 | [diff] [blame] | 310 | enum ath10k_hw_rate_ofdm { |
| 311 | ATH10K_HW_RATE_OFDM_48M = 0, |
| 312 | ATH10K_HW_RATE_OFDM_24M, |
| 313 | ATH10K_HW_RATE_OFDM_12M, |
| 314 | ATH10K_HW_RATE_OFDM_6M, |
| 315 | ATH10K_HW_RATE_OFDM_54M, |
| 316 | ATH10K_HW_RATE_OFDM_36M, |
| 317 | ATH10K_HW_RATE_OFDM_18M, |
| 318 | ATH10K_HW_RATE_OFDM_9M, |
| 319 | }; |
| 320 | |
| 321 | enum ath10k_hw_rate_cck { |
| 322 | ATH10K_HW_RATE_CCK_LP_11M = 0, |
| 323 | ATH10K_HW_RATE_CCK_LP_5_5M, |
| 324 | ATH10K_HW_RATE_CCK_LP_2M, |
| 325 | ATH10K_HW_RATE_CCK_LP_1M, |
| 326 | ATH10K_HW_RATE_CCK_SP_11M, |
| 327 | ATH10K_HW_RATE_CCK_SP_5_5M, |
| 328 | ATH10K_HW_RATE_CCK_SP_2M, |
| 329 | }; |
| 330 | |
Mohammed Shafi Shajakhan | 5269c65 | 2016-06-07 15:47:04 +0300 | [diff] [blame] | 331 | enum ath10k_hw_rate_rev2_cck { |
| 332 | ATH10K_HW_RATE_REV2_CCK_LP_1M = 1, |
| 333 | ATH10K_HW_RATE_REV2_CCK_LP_2M, |
| 334 | ATH10K_HW_RATE_REV2_CCK_LP_5_5M, |
| 335 | ATH10K_HW_RATE_REV2_CCK_LP_11M, |
| 336 | ATH10K_HW_RATE_REV2_CCK_SP_2M, |
| 337 | ATH10K_HW_RATE_REV2_CCK_SP_5_5M, |
| 338 | ATH10K_HW_RATE_REV2_CCK_SP_11M, |
| 339 | }; |
| 340 | |
Yanbo Li | b8d55fc | 2015-11-16 22:22:02 +0200 | [diff] [blame] | 341 | enum ath10k_hw_4addr_pad { |
| 342 | ATH10K_HW_4ADDR_PAD_AFTER, |
| 343 | ATH10K_HW_4ADDR_PAD_BEFORE, |
| 344 | }; |
| 345 | |
Vasanthakumar Thiagarajan | 26c1976 | 2016-06-07 15:47:05 +0300 | [diff] [blame] | 346 | enum ath10k_hw_cc_wraparound_type { |
| 347 | ATH10K_HW_CC_WRAP_DISABLED = 0, |
| 348 | |
| 349 | /* This type is when the HW chip has a quirky Cycle Counter |
| 350 | * wraparound which resets to 0x7fffffff instead of 0. All |
| 351 | * other CC related counters (e.g. Rx Clear Count) are divided |
| 352 | * by 2 so they never wraparound themselves. |
| 353 | */ |
| 354 | ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1, |
Vasanthakumar Thiagarajan | 8e10035 | 2016-06-07 15:47:06 +0300 | [diff] [blame] | 355 | |
| 356 | /* Each hw counter wrapsaround independently. When the |
| 357 | * counter overflows the repestive counter is right shifted |
| 358 | * by 1, i.e reset to 0x7fffffff, and other counters will be |
| 359 | * running unaffected. In this type of wraparound, it should |
| 360 | * be possible to report accurate Rx busy time unlike the |
| 361 | * first type. |
| 362 | */ |
| 363 | ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2, |
Vasanthakumar Thiagarajan | 26c1976 | 2016-06-07 15:47:05 +0300 | [diff] [blame] | 364 | }; |
| 365 | |
Vasanthakumar Thiagarajan | 43d923e | 2016-09-09 17:25:13 +0300 | [diff] [blame^] | 366 | struct ath10k_hw_params { |
| 367 | u32 id; |
| 368 | u16 dev_id; |
| 369 | const char *name; |
| 370 | u32 patch_load_addr; |
| 371 | int uart_pin; |
| 372 | u32 otp_exe_param; |
| 373 | |
| 374 | /* Type of hw cycle counter wraparound logic, for more info |
| 375 | * refer enum ath10k_hw_cc_wraparound_type. |
| 376 | */ |
| 377 | enum ath10k_hw_cc_wraparound_type cc_wraparound_type; |
| 378 | |
| 379 | /* Some of chip expects fragment descriptor to be continuous |
| 380 | * memory for any TX operation. Set continuous_frag_desc flag |
| 381 | * for the hardware which have such requirement. |
| 382 | */ |
| 383 | bool continuous_frag_desc; |
| 384 | |
| 385 | /* CCK hardware rate table mapping for the newer chipsets |
| 386 | * like QCA99X0, QCA4019 got revised. The CCK h/w rate values |
| 387 | * are in a proper order with respect to the rate/preamble |
| 388 | */ |
| 389 | bool cck_rate_map_rev2; |
| 390 | |
| 391 | u32 channel_counters_freq_hz; |
| 392 | |
| 393 | /* Mgmt tx descriptors threshold for limiting probe response |
| 394 | * frames. |
| 395 | */ |
| 396 | u32 max_probe_resp_desc_thres; |
| 397 | |
| 398 | /* The padding bytes's location is different on various chips */ |
| 399 | enum ath10k_hw_4addr_pad hw_4addr_pad; |
| 400 | |
| 401 | u32 tx_chain_mask; |
| 402 | u32 rx_chain_mask; |
| 403 | u32 max_spatial_stream; |
| 404 | u32 cal_data_len; |
| 405 | |
| 406 | struct ath10k_hw_params_fw { |
| 407 | const char *dir; |
| 408 | const char *board; |
| 409 | size_t board_size; |
| 410 | size_t board_ext_size; |
| 411 | } fw; |
| 412 | |
| 413 | /* qca99x0 family chips deliver broadcast/multicast management |
| 414 | * frames encrypted and expect software do decryption. |
| 415 | */ |
| 416 | bool sw_decrypt_mcast_mgmt; |
| 417 | }; |
| 418 | |
Bartosz Markowski | ec6a73f | 2013-09-26 17:47:14 +0200 | [diff] [blame] | 419 | /* Target specific defines for MAIN firmware */ |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 420 | #define TARGET_NUM_VDEVS 8 |
| 421 | #define TARGET_NUM_PEER_AST 2 |
| 422 | #define TARGET_NUM_WDS_ENTRIES 32 |
| 423 | #define TARGET_DMA_BURST_SIZE 0 |
| 424 | #define TARGET_MAC_AGGR_DELIM 0 |
| 425 | #define TARGET_AST_SKID_LIMIT 16 |
Michal Kazior | cfd1061 | 2014-11-25 15:16:05 +0100 | [diff] [blame] | 426 | #define TARGET_NUM_STATIONS 16 |
| 427 | #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \ |
| 428 | (TARGET_NUM_VDEVS)) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 429 | #define TARGET_NUM_OFFLOAD_PEERS 0 |
| 430 | #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 |
| 431 | #define TARGET_NUM_PEER_KEYS 2 |
Michal Kazior | cfd1061 | 2014-11-25 15:16:05 +0100 | [diff] [blame] | 432 | #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 433 | #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) |
| 434 | #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) |
| 435 | #define TARGET_RX_TIMEOUT_LO_PRI 100 |
| 436 | #define TARGET_RX_TIMEOUT_HI_PRI 40 |
Michal Kazior | 4d316c7 | 2013-09-26 10:12:24 +0300 | [diff] [blame] | 437 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 438 | #define TARGET_SCAN_MAX_PENDING_REQS 4 |
| 439 | #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 |
| 440 | #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 |
| 441 | #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 |
| 442 | #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 |
| 443 | #define TARGET_NUM_MCAST_GROUPS 0 |
| 444 | #define TARGET_NUM_MCAST_TABLE_ELEMS 0 |
| 445 | #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED |
| 446 | #define TARGET_TX_DBG_LOG_SIZE 1024 |
| 447 | #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 |
| 448 | #define TARGET_VOW_CONFIG 0 |
| 449 | #define TARGET_NUM_MSDU_DESC (1024 + 400) |
| 450 | #define TARGET_MAX_FRAG_ENTRIES 0 |
| 451 | |
Bartosz Markowski | ec6a73f | 2013-09-26 17:47:14 +0200 | [diff] [blame] | 452 | /* Target specific defines for 10.X firmware */ |
| 453 | #define TARGET_10X_NUM_VDEVS 16 |
| 454 | #define TARGET_10X_NUM_PEER_AST 2 |
| 455 | #define TARGET_10X_NUM_WDS_ENTRIES 32 |
| 456 | #define TARGET_10X_DMA_BURST_SIZE 0 |
| 457 | #define TARGET_10X_MAC_AGGR_DELIM 0 |
SenthilKumar Jegadeesan | b24af14 | 2015-03-04 15:43:45 +0200 | [diff] [blame] | 458 | #define TARGET_10X_AST_SKID_LIMIT 128 |
Michal Kazior | cfd1061 | 2014-11-25 15:16:05 +0100 | [diff] [blame] | 459 | #define TARGET_10X_NUM_STATIONS 128 |
Anilkumar Kolli | af9a6a3 | 2016-02-23 12:19:57 +0530 | [diff] [blame] | 460 | #define TARGET_10X_TX_STATS_NUM_STATIONS 118 |
Michal Kazior | cfd1061 | 2014-11-25 15:16:05 +0100 | [diff] [blame] | 461 | #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \ |
| 462 | (TARGET_10X_NUM_VDEVS)) |
Anilkumar Kolli | af9a6a3 | 2016-02-23 12:19:57 +0530 | [diff] [blame] | 463 | #define TARGET_10X_TX_STATS_NUM_PEERS ((TARGET_10X_TX_STATS_NUM_STATIONS) + \ |
| 464 | (TARGET_10X_NUM_VDEVS)) |
Bartosz Markowski | ec6a73f | 2013-09-26 17:47:14 +0200 | [diff] [blame] | 465 | #define TARGET_10X_NUM_OFFLOAD_PEERS 0 |
| 466 | #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 |
| 467 | #define TARGET_10X_NUM_PEER_KEYS 2 |
Michal Kazior | cfd1061 | 2014-11-25 15:16:05 +0100 | [diff] [blame] | 468 | #define TARGET_10X_NUM_TIDS_MAX 256 |
| 469 | #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ |
| 470 | (TARGET_10X_NUM_PEERS) * 2) |
Anilkumar Kolli | af9a6a3 | 2016-02-23 12:19:57 +0530 | [diff] [blame] | 471 | #define TARGET_10X_TX_STATS_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ |
| 472 | (TARGET_10X_TX_STATS_NUM_PEERS) * 2) |
Bartosz Markowski | ec6a73f | 2013-09-26 17:47:14 +0200 | [diff] [blame] | 473 | #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) |
| 474 | #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) |
| 475 | #define TARGET_10X_RX_TIMEOUT_LO_PRI 100 |
| 476 | #define TARGET_10X_RX_TIMEOUT_HI_PRI 40 |
Bartosz Markowski | ec6a73f | 2013-09-26 17:47:14 +0200 | [diff] [blame] | 477 | #define TARGET_10X_SCAN_MAX_PENDING_REQS 4 |
| 478 | #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 |
| 479 | #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 |
| 480 | #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 |
| 481 | #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 |
| 482 | #define TARGET_10X_NUM_MCAST_GROUPS 0 |
| 483 | #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 |
| 484 | #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED |
| 485 | #define TARGET_10X_TX_DBG_LOG_SIZE 1024 |
| 486 | #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 |
| 487 | #define TARGET_10X_VOW_CONFIG 0 |
| 488 | #define TARGET_10X_NUM_MSDU_DESC (1024 + 400) |
| 489 | #define TARGET_10X_MAX_FRAG_ENTRIES 0 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 490 | |
Sujith Manoharan | f6603ff | 2015-01-12 12:30:02 +0200 | [diff] [blame] | 491 | /* 10.2 parameters */ |
Felix Fietkau | 76d164f | 2015-09-17 14:29:07 +0300 | [diff] [blame] | 492 | #define TARGET_10_2_DMA_BURST_SIZE 0 |
Sujith Manoharan | f6603ff | 2015-01-12 12:30:02 +0200 | [diff] [blame] | 493 | |
Michal Kazior | ca996ec | 2014-12-03 10:11:32 +0200 | [diff] [blame] | 494 | /* Target specific defines for WMI-TLV firmware */ |
Michal Kazior | 039a005 | 2015-03-31 10:26:26 +0000 | [diff] [blame] | 495 | #define TARGET_TLV_NUM_VDEVS 4 |
Michal Kazior | ca996ec | 2014-12-03 10:11:32 +0200 | [diff] [blame] | 496 | #define TARGET_TLV_NUM_STATIONS 32 |
Michal Kazior | 039a005 | 2015-03-31 10:26:26 +0000 | [diff] [blame] | 497 | #define TARGET_TLV_NUM_PEERS 35 |
Marek Puzyniak | 8cca3d6 | 2015-03-30 09:51:52 +0300 | [diff] [blame] | 498 | #define TARGET_TLV_NUM_TDLS_VDEVS 1 |
Michal Kazior | ca996ec | 2014-12-03 10:11:32 +0200 | [diff] [blame] | 499 | #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2) |
| 500 | #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32) |
Janusz Dziedzic | 25c8661 | 2015-03-23 17:32:54 +0200 | [diff] [blame] | 501 | #define TARGET_TLV_NUM_WOW_PATTERNS 22 |
Michal Kazior | ca996ec | 2014-12-03 10:11:32 +0200 | [diff] [blame] | 502 | |
Vasanthakumar Thiagarajan | 050af06 | 2015-06-18 12:31:04 +0530 | [diff] [blame] | 503 | /* Diagnostic Window */ |
| 504 | #define CE_DIAG_PIPE 7 |
| 505 | |
Vasanthakumar Thiagarajan | 2f2cfc4 | 2015-06-18 12:31:01 +0530 | [diff] [blame] | 506 | #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan |
| 507 | |
Raja Mani | d1e52a8 | 2015-06-22 20:10:15 +0530 | [diff] [blame] | 508 | /* Target specific defines for 10.4 firmware */ |
| 509 | #define TARGET_10_4_NUM_VDEVS 16 |
| 510 | #define TARGET_10_4_NUM_STATIONS 32 |
| 511 | #define TARGET_10_4_NUM_PEERS ((TARGET_10_4_NUM_STATIONS) + \ |
| 512 | (TARGET_10_4_NUM_VDEVS)) |
| 513 | #define TARGET_10_4_ACTIVE_PEERS 0 |
Raja Mani | b039941 | 2015-06-22 20:10:17 +0530 | [diff] [blame] | 514 | |
Raja Mani | 1201844 | 2015-07-29 11:40:38 +0300 | [diff] [blame] | 515 | #define TARGET_10_4_NUM_QCACHE_PEERS_MAX 512 |
Michal Kazior | 99ad1cb | 2016-03-01 13:16:11 +0100 | [diff] [blame] | 516 | #define TARGET_10_4_QCACHE_ACTIVE_PEERS 50 |
| 517 | #define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC 35 |
Raja Mani | d1e52a8 | 2015-06-22 20:10:15 +0530 | [diff] [blame] | 518 | #define TARGET_10_4_NUM_OFFLOAD_PEERS 0 |
| 519 | #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS 0 |
| 520 | #define TARGET_10_4_NUM_PEER_KEYS 2 |
| 521 | #define TARGET_10_4_TGT_NUM_TIDS ((TARGET_10_4_NUM_PEERS) * 2) |
Michal Kazior | 99ad1cb | 2016-03-01 13:16:11 +0100 | [diff] [blame] | 522 | #define TARGET_10_4_NUM_MSDU_DESC (1024 + 400) |
| 523 | #define TARGET_10_4_NUM_MSDU_DESC_PFC 2500 |
Raja Mani | d1e52a8 | 2015-06-22 20:10:15 +0530 | [diff] [blame] | 524 | #define TARGET_10_4_AST_SKID_LIMIT 32 |
Raja Mani | d1e52a8 | 2015-06-22 20:10:15 +0530 | [diff] [blame] | 525 | |
| 526 | /* 100 ms for video, best-effort, and background */ |
| 527 | #define TARGET_10_4_RX_TIMEOUT_LO_PRI 100 |
| 528 | |
| 529 | /* 40 ms for voice */ |
| 530 | #define TARGET_10_4_RX_TIMEOUT_HI_PRI 40 |
| 531 | |
| 532 | #define TARGET_10_4_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI |
| 533 | #define TARGET_10_4_SCAN_MAX_REQS 4 |
| 534 | #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV 3 |
| 535 | #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV 3 |
| 536 | #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES 8 |
| 537 | |
| 538 | /* Note: mcast to ucast is disabled by default */ |
| 539 | #define TARGET_10_4_NUM_MCAST_GROUPS 0 |
| 540 | #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS 0 |
| 541 | #define TARGET_10_4_MCAST2UCAST_MODE 0 |
| 542 | |
| 543 | #define TARGET_10_4_TX_DBG_LOG_SIZE 1024 |
| 544 | #define TARGET_10_4_NUM_WDS_ENTRIES 32 |
Felix Fietkau | 76d164f | 2015-09-17 14:29:07 +0300 | [diff] [blame] | 545 | #define TARGET_10_4_DMA_BURST_SIZE 0 |
Raja Mani | d1e52a8 | 2015-06-22 20:10:15 +0530 | [diff] [blame] | 546 | #define TARGET_10_4_MAC_AGGR_DELIM 0 |
| 547 | #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 |
| 548 | #define TARGET_10_4_VOW_CONFIG 0 |
| 549 | #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV 3 |
Raja Mani | d1e52a8 | 2015-06-22 20:10:15 +0530 | [diff] [blame] | 550 | #define TARGET_10_4_11AC_TX_MAX_FRAGS 2 |
| 551 | #define TARGET_10_4_MAX_PEER_EXT_STATS 16 |
| 552 | #define TARGET_10_4_SMART_ANT_CAP 0 |
| 553 | #define TARGET_10_4_BK_MIN_FREE 0 |
| 554 | #define TARGET_10_4_BE_MIN_FREE 0 |
| 555 | #define TARGET_10_4_VI_MIN_FREE 0 |
| 556 | #define TARGET_10_4_VO_MIN_FREE 0 |
| 557 | #define TARGET_10_4_RX_BATCH_MODE 1 |
| 558 | #define TARGET_10_4_THERMAL_THROTTLING_CONFIG 0 |
| 559 | #define TARGET_10_4_ATF_CONFIG 0 |
| 560 | #define TARGET_10_4_IPHDR_PAD_CONFIG 1 |
| 561 | #define TARGET_10_4_QWRAP_CONFIG 0 |
| 562 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 563 | /* Number of Copy Engines supported */ |
Vasanthakumar Thiagarajan | 2f2cfc4 | 2015-06-18 12:31:01 +0530 | [diff] [blame] | 564 | #define CE_COUNT ar->hw_values->ce_count |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 565 | |
| 566 | /* |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 567 | * Granted MSIs are assigned as follows: |
| 568 | * Firmware uses the first |
| 569 | * Remaining MSIs, if any, are used by Copy Engines |
| 570 | * This mapping is known to both Target firmware and Host software. |
| 571 | * It may be changed as long as Host and Target are kept in sync. |
| 572 | */ |
| 573 | /* MSI for firmware (errors, etc.) */ |
| 574 | #define MSI_ASSIGN_FW 0 |
| 575 | |
| 576 | /* MSIs for Copy Engines */ |
| 577 | #define MSI_ASSIGN_CE_INITIAL 1 |
Vasanthakumar Thiagarajan | 2f2cfc4 | 2015-06-18 12:31:01 +0530 | [diff] [blame] | 578 | #define MSI_ASSIGN_CE_MAX ar->hw_values->msi_assign_ce_max |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 579 | |
| 580 | /* as of IP3.7.1 */ |
Vasanthakumar Thiagarajan | 2f2cfc4 | 2015-06-18 12:31:01 +0530 | [diff] [blame] | 581 | #define RTC_STATE_V_ON ar->hw_values->rtc_state_val_on |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 582 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 583 | #define RTC_STATE_V_LSB 0 |
| 584 | #define RTC_STATE_V_MASK 0x00000007 |
| 585 | #define RTC_STATE_ADDRESS 0x0000 |
| 586 | #define PCIE_SOC_WAKE_V_MASK 0x00000001 |
| 587 | #define PCIE_SOC_WAKE_ADDRESS 0x0004 |
| 588 | #define PCIE_SOC_WAKE_RESET 0x00000000 |
| 589 | #define SOC_GLOBAL_RESET_ADDRESS 0x0008 |
| 590 | |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 591 | #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address |
| 592 | #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 593 | #define MAC_COEX_BASE_ADDRESS 0x00006000 |
| 594 | #define BT_COEX_BASE_ADDRESS 0x00007000 |
| 595 | #define SOC_PCIE_BASE_ADDRESS 0x00008000 |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 596 | #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 597 | #define WLAN_UART_BASE_ADDRESS 0x0000c000 |
| 598 | #define WLAN_SI_BASE_ADDRESS 0x00010000 |
| 599 | #define WLAN_GPIO_BASE_ADDRESS 0x00014000 |
| 600 | #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 |
| 601 | #define WLAN_MAC_BASE_ADDRESS 0x00020000 |
| 602 | #define EFUSE_BASE_ADDRESS 0x00030000 |
| 603 | #define FPGA_REG_BASE_ADDRESS 0x00039000 |
| 604 | #define WLAN_UART2_BASE_ADDRESS 0x00054c00 |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 605 | #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address |
| 606 | #define CE0_BASE_ADDRESS ar->regs->ce0_base_address |
| 607 | #define CE1_BASE_ADDRESS ar->regs->ce1_base_address |
| 608 | #define CE2_BASE_ADDRESS ar->regs->ce2_base_address |
| 609 | #define CE3_BASE_ADDRESS ar->regs->ce3_base_address |
| 610 | #define CE4_BASE_ADDRESS ar->regs->ce4_base_address |
| 611 | #define CE5_BASE_ADDRESS ar->regs->ce5_base_address |
| 612 | #define CE6_BASE_ADDRESS ar->regs->ce6_base_address |
| 613 | #define CE7_BASE_ADDRESS ar->regs->ce7_base_address |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 614 | #define DBI_BASE_ADDRESS 0x00060000 |
| 615 | #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 |
Vasanthakumar Thiagarajan | a521ee9 | 2015-06-18 12:31:02 +0530 | [diff] [blame] | 616 | #define PCIE_LOCAL_BASE_ADDRESS ar->regs->pcie_local_base_address |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 617 | |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 618 | #define SOC_RESET_CONTROL_ADDRESS 0x00000000 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 619 | #define SOC_RESET_CONTROL_OFFSET 0x00000000 |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 620 | #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask |
| 621 | #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 622 | #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 623 | #define SOC_CPU_CLOCK_OFFSET 0x00000020 |
| 624 | #define SOC_CPU_CLOCK_STANDARD_LSB 0 |
| 625 | #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 |
| 626 | #define SOC_CLOCK_CONTROL_OFFSET 0x00000028 |
| 627 | #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 |
| 628 | #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 |
| 629 | #define SOC_LPO_CAL_OFFSET 0x000000e0 |
| 630 | #define SOC_LPO_CAL_ENABLE_LSB 20 |
| 631 | #define SOC_LPO_CAL_ENABLE_MASK 0x00100000 |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 632 | #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 |
| 633 | #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 634 | |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 635 | #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address |
Kalle Valo | e01ae68 | 2013-09-01 11:22:14 +0300 | [diff] [blame] | 636 | #define SOC_CHIP_ID_REV_LSB 8 |
| 637 | #define SOC_CHIP_ID_REV_MASK 0x00000f00 |
| 638 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 639 | #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 |
| 640 | #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 |
| 641 | #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 |
| 642 | #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 |
| 643 | |
| 644 | #define WLAN_GPIO_PIN0_ADDRESS 0x00000028 |
Sven Eckelmann | 6847f96 | 2016-06-02 17:59:50 +0300 | [diff] [blame] | 645 | #define WLAN_GPIO_PIN0_CONFIG_LSB 11 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 646 | #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 |
Sven Eckelmann | 6847f96 | 2016-06-02 17:59:50 +0300 | [diff] [blame] | 647 | #define WLAN_GPIO_PIN0_PAD_PULL_LSB 5 |
| 648 | #define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 649 | #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c |
| 650 | #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 |
| 651 | #define WLAN_GPIO_PIN10_ADDRESS 0x00000050 |
| 652 | #define WLAN_GPIO_PIN11_ADDRESS 0x00000054 |
| 653 | #define WLAN_GPIO_PIN12_ADDRESS 0x00000058 |
| 654 | #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c |
| 655 | |
| 656 | #define CLOCK_GPIO_OFFSET 0xffffffff |
| 657 | #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 |
| 658 | #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 |
| 659 | |
| 660 | #define SI_CONFIG_OFFSET 0x00000000 |
Sven Eckelmann | 6847f96 | 2016-06-02 17:59:50 +0300 | [diff] [blame] | 661 | #define SI_CONFIG_ERR_INT_LSB 19 |
| 662 | #define SI_CONFIG_ERR_INT_MASK 0x00080000 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 663 | #define SI_CONFIG_BIDIR_OD_DATA_LSB 18 |
| 664 | #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 |
| 665 | #define SI_CONFIG_I2C_LSB 16 |
| 666 | #define SI_CONFIG_I2C_MASK 0x00010000 |
| 667 | #define SI_CONFIG_POS_SAMPLE_LSB 7 |
| 668 | #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 |
| 669 | #define SI_CONFIG_INACTIVE_DATA_LSB 5 |
| 670 | #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 |
| 671 | #define SI_CONFIG_INACTIVE_CLK_LSB 4 |
| 672 | #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 |
| 673 | #define SI_CONFIG_DIVIDER_LSB 0 |
| 674 | #define SI_CONFIG_DIVIDER_MASK 0x0000000f |
| 675 | #define SI_CS_OFFSET 0x00000004 |
Sven Eckelmann | 6847f96 | 2016-06-02 17:59:50 +0300 | [diff] [blame] | 676 | #define SI_CS_DONE_ERR_LSB 10 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 677 | #define SI_CS_DONE_ERR_MASK 0x00000400 |
Sven Eckelmann | 6847f96 | 2016-06-02 17:59:50 +0300 | [diff] [blame] | 678 | #define SI_CS_DONE_INT_LSB 9 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 679 | #define SI_CS_DONE_INT_MASK 0x00000200 |
| 680 | #define SI_CS_START_LSB 8 |
| 681 | #define SI_CS_START_MASK 0x00000100 |
| 682 | #define SI_CS_RX_CNT_LSB 4 |
| 683 | #define SI_CS_RX_CNT_MASK 0x000000f0 |
| 684 | #define SI_CS_TX_CNT_LSB 0 |
| 685 | #define SI_CS_TX_CNT_MASK 0x0000000f |
| 686 | |
| 687 | #define SI_TX_DATA0_OFFSET 0x00000008 |
| 688 | #define SI_TX_DATA1_OFFSET 0x0000000c |
| 689 | #define SI_RX_DATA0_OFFSET 0x00000010 |
| 690 | #define SI_RX_DATA1_OFFSET 0x00000014 |
| 691 | |
| 692 | #define CORE_CTRL_CPU_INTR_MASK 0x00002000 |
Michal Kazior | 7c0f0e3 | 2014-10-20 14:14:38 +0200 | [diff] [blame] | 693 | #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 694 | #define CORE_CTRL_ADDRESS 0x0000 |
| 695 | #define PCIE_INTR_ENABLE_ADDRESS 0x0008 |
Michal Kazior | e539887 | 2013-11-25 14:06:20 +0100 | [diff] [blame] | 696 | #define PCIE_INTR_CAUSE_ADDRESS 0x000c |
Vasanthakumar Thiagarajan | a521ee9 | 2015-06-18 12:31:02 +0530 | [diff] [blame] | 697 | #define PCIE_INTR_CLR_ADDRESS ar->regs->pcie_intr_clr_address |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 698 | #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 699 | #define CPU_INTR_ADDRESS 0x0010 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 700 | |
Vasanthakumar Thiagarajan | 9c8fb54 | 2015-08-12 16:24:05 +0530 | [diff] [blame] | 701 | #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz) |
Michal Kazior | 0936ea3 | 2015-05-25 14:06:17 +0200 | [diff] [blame] | 702 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 703 | /* Firmware indications to the Host via SCRATCH_3 register. */ |
Vasanthakumar Thiagarajan | a521ee9 | 2015-06-18 12:31:02 +0530 | [diff] [blame] | 704 | #define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 705 | #define FW_IND_EVENT_PENDING 1 |
| 706 | #define FW_IND_INITIALIZED 2 |
Raja Mani | 0d87c92 | 2016-01-27 15:24:33 +0530 | [diff] [blame] | 707 | #define FW_IND_HOST_READY 0x80000000 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 708 | |
| 709 | /* HOST_REG interrupt from firmware */ |
Vasanthakumar Thiagarajan | a521ee9 | 2015-06-18 12:31:02 +0530 | [diff] [blame] | 710 | #define PCIE_INTR_FIRMWARE_MASK ar->regs->pcie_intr_fw_mask |
| 711 | #define PCIE_INTR_CE_MASK_ALL ar->regs->pcie_intr_ce_mask_all |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 712 | |
| 713 | #define DRAM_BASE_ADDRESS 0x00400000 |
| 714 | |
Vasanthakumar Thiagarajan | 8bd4702 | 2015-06-18 12:31:03 +0530 | [diff] [blame] | 715 | #define PCIE_BAR_REG_ADDRESS 0x40030 |
| 716 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 717 | #define MISSING 0 |
| 718 | |
| 719 | #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET |
| 720 | #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET |
| 721 | #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET |
| 722 | #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET |
| 723 | #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK |
| 724 | #define RESET_CONTROL_MBOX_RST_MASK MISSING |
| 725 | #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK |
| 726 | #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS |
| 727 | #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS |
| 728 | #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS |
Sven Eckelmann | 6847f96 | 2016-06-02 17:59:50 +0300 | [diff] [blame] | 729 | #define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 730 | #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK |
Sven Eckelmann | 6847f96 | 2016-06-02 17:59:50 +0300 | [diff] [blame] | 731 | #define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB |
| 732 | #define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 733 | #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK |
| 734 | #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS |
| 735 | #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS |
| 736 | #define LOCAL_SCRATCH_OFFSET 0x18 |
| 737 | #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET |
| 738 | #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET |
| 739 | #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS |
| 740 | #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS |
| 741 | #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS |
| 742 | #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS |
| 743 | #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB |
| 744 | #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK |
| 745 | #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB |
| 746 | #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK |
| 747 | #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS |
| 748 | #define MBOX_BASE_ADDRESS MISSING |
| 749 | #define INT_STATUS_ENABLE_ERROR_LSB MISSING |
| 750 | #define INT_STATUS_ENABLE_ERROR_MASK MISSING |
| 751 | #define INT_STATUS_ENABLE_CPU_LSB MISSING |
| 752 | #define INT_STATUS_ENABLE_CPU_MASK MISSING |
| 753 | #define INT_STATUS_ENABLE_COUNTER_LSB MISSING |
| 754 | #define INT_STATUS_ENABLE_COUNTER_MASK MISSING |
| 755 | #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING |
| 756 | #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING |
| 757 | #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING |
| 758 | #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING |
| 759 | #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING |
| 760 | #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING |
| 761 | #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING |
| 762 | #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING |
| 763 | #define INT_STATUS_ENABLE_ADDRESS MISSING |
| 764 | #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING |
| 765 | #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING |
| 766 | #define HOST_INT_STATUS_ADDRESS MISSING |
| 767 | #define CPU_INT_STATUS_ADDRESS MISSING |
| 768 | #define ERROR_INT_STATUS_ADDRESS MISSING |
| 769 | #define ERROR_INT_STATUS_WAKEUP_MASK MISSING |
| 770 | #define ERROR_INT_STATUS_WAKEUP_LSB MISSING |
| 771 | #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING |
| 772 | #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING |
| 773 | #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING |
| 774 | #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING |
| 775 | #define COUNT_DEC_ADDRESS MISSING |
| 776 | #define HOST_INT_STATUS_CPU_MASK MISSING |
| 777 | #define HOST_INT_STATUS_CPU_LSB MISSING |
| 778 | #define HOST_INT_STATUS_ERROR_MASK MISSING |
| 779 | #define HOST_INT_STATUS_ERROR_LSB MISSING |
| 780 | #define HOST_INT_STATUS_COUNTER_MASK MISSING |
| 781 | #define HOST_INT_STATUS_COUNTER_LSB MISSING |
| 782 | #define RX_LOOKAHEAD_VALID_ADDRESS MISSING |
| 783 | #define WINDOW_DATA_ADDRESS MISSING |
| 784 | #define WINDOW_READ_ADDR_ADDRESS MISSING |
| 785 | #define WINDOW_WRITE_ADDR_ADDRESS MISSING |
| 786 | |
Sven Eckelmann | 6847f96 | 2016-06-02 17:59:50 +0300 | [diff] [blame] | 787 | #define QCA9887_1_0_I2C_SDA_GPIO_PIN 5 |
| 788 | #define QCA9887_1_0_I2C_SDA_PIN_CONFIG 3 |
| 789 | #define QCA9887_1_0_SI_CLK_GPIO_PIN 17 |
| 790 | #define QCA9887_1_0_SI_CLK_PIN_CONFIG 3 |
| 791 | #define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010 |
| 792 | |
| 793 | #define QCA9887_EEPROM_SELECT_READ 0xa10000a0 |
| 794 | #define QCA9887_EEPROM_ADDR_HI_MASK 0x0000ff00 |
| 795 | #define QCA9887_EEPROM_ADDR_HI_LSB 8 |
| 796 | #define QCA9887_EEPROM_ADDR_LO_MASK 0x00ff0000 |
| 797 | #define QCA9887_EEPROM_ADDR_LO_LSB 16 |
| 798 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 799 | #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) |
| 800 | |
| 801 | #endif /* _HW_H_ */ |