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gerrit-public.fairphone.software / kernel / msm-4.9 / 4959444165523e68118035bebb727b9431746765 / . / drivers / net / wireless / realtek / rtl8xxxu / rtl8xxxu.c
blob: fcae9f020f5c821c9fc29cb74614e822ae511892 [file] [log] [blame]
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1/*
2 * RTL8XXXU mac80211 USB driver
3 *
4 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
5 *
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
8 *
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 */
23
24#include <linux/init.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/errno.h>
28#include <linux/slab.h>
29#include <linux/module.h>
30#include <linux/spinlock.h>
31#include <linux/list.h>
32#include <linux/usb.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
38#include <linux/moduleparam.h>
39#include <net/mac80211.h>
40#include "rtl8xxxu.h"
41#include "rtl8xxxu_regs.h"
42
43#define DRIVER_NAME "rtl8xxxu"
44
Jes Sorensen3307d842016-02-29 17:03:59 -0500[diff] [blame]45static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]46static bool rtl8xxxu_ht40_2g;
47
48MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50MODULE_LICENSE("GPL");
51MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
Jes Sorensenb001e082016-02-29 17:04:02 -0500[diff] [blame]57MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]58MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
59MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]60
61module_param_named(debug, rtl8xxxu_debug, int, 0600);
62MODULE_PARM_DESC(debug, "Set debug mask");
63module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
64MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
65
66#define USB_VENDOR_ID_REALTEK 0x0bda
67/* Minimum IEEE80211_MAX_FRAME_LEN */
68#define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
69#define RTL8XXXU_RX_URBS 32
70#define RTL8XXXU_RX_URB_PENDING_WATER 8
71#define RTL8XXXU_TX_URBS 64
72#define RTL8XXXU_TX_URB_LOW_WATER 25
73#define RTL8XXXU_TX_URB_HIGH_WATER 32
74
75static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
76 struct rtl8xxxu_rx_urb *rx_urb);
77
78static struct ieee80211_rate rtl8xxxu_rates[] = {
79 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
80 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
81 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
82 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
83 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
84 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
85 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
86 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
87 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
88 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
89 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
90 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
91};
92
93static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
94 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
95 .hw_value = 1, .max_power = 30 },
96 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
97 .hw_value = 2, .max_power = 30 },
98 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
99 .hw_value = 3, .max_power = 30 },
100 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
101 .hw_value = 4, .max_power = 30 },
102 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
103 .hw_value = 5, .max_power = 30 },
104 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
105 .hw_value = 6, .max_power = 30 },
106 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
107 .hw_value = 7, .max_power = 30 },
108 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
109 .hw_value = 8, .max_power = 30 },
110 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
111 .hw_value = 9, .max_power = 30 },
112 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
113 .hw_value = 10, .max_power = 30 },
114 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
115 .hw_value = 11, .max_power = 30 },
116 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
117 .hw_value = 12, .max_power = 30 },
118 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
119 .hw_value = 13, .max_power = 30 },
120 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
121 .hw_value = 14, .max_power = 30 }
122};
123
124static struct ieee80211_supported_band rtl8xxxu_supported_band = {
125 .channels = rtl8xxxu_channels_2g,
126 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
127 .bitrates = rtl8xxxu_rates,
128 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
129};
130
131static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
132 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
133 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
134 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
135 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
136 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
137 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
138 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
139 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
140 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
141 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
142 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
143 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
144 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
145 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
146 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
147 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
148 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
149 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
150 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
151 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
152 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
153 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
154};
155
Jes Sorensenb7dd8ff2016-02-29 17:04:17 -0500[diff] [blame]156static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
157 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
158 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
159 {0x430, 0x00}, {0x431, 0x00},
160 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
161 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
162 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
163 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
164 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
165 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
166 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
167 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
168 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
169 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
170 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
171 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
172 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
173 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
174 {0x516, 0x0a}, {0x525, 0x4f},
175 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
176 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
177 {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
178 {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
179 {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
180 {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
181 {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
182 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
183 {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
184 {0xffff, 0xff},
185};
186
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]187static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
188 {0x800, 0x80040000}, {0x804, 0x00000003},
189 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
190 {0x810, 0x10001331}, {0x814, 0x020c3d10},
191 {0x818, 0x02200385}, {0x81c, 0x00000000},
192 {0x820, 0x01000100}, {0x824, 0x00390004},
193 {0x828, 0x00000000}, {0x82c, 0x00000000},
194 {0x830, 0x00000000}, {0x834, 0x00000000},
195 {0x838, 0x00000000}, {0x83c, 0x00000000},
196 {0x840, 0x00010000}, {0x844, 0x00000000},
197 {0x848, 0x00000000}, {0x84c, 0x00000000},
198 {0x850, 0x00000000}, {0x854, 0x00000000},
199 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
200 {0x860, 0x66f60110}, {0x864, 0x061f0130},
201 {0x868, 0x00000000}, {0x86c, 0x32323200},
202 {0x870, 0x07000760}, {0x874, 0x22004000},
203 {0x878, 0x00000808}, {0x87c, 0x00000000},
204 {0x880, 0xc0083070}, {0x884, 0x000004d5},
205 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
206 {0x890, 0x00000800}, {0x894, 0xfffffffe},
207 {0x898, 0x40302010}, {0x89c, 0x00706050},
208 {0x900, 0x00000000}, {0x904, 0x00000023},
209 {0x908, 0x00000000}, {0x90c, 0x81121111},
210 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
211 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
212 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
213 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
214 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
215 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
216 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
217 {0xa78, 0x00000900},
218 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
219 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
220 {0xc10, 0x08800000}, {0xc14, 0x40000100},
221 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
222 {0xc20, 0x00000000}, {0xc24, 0x00000000},
223 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
224 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
225 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
226 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
227 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
228 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
229 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
230 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
231 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
232 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
233 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
234 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
235 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
236 {0xc90, 0x00121820}, {0xc94, 0x00000000},
237 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
238 {0xca0, 0x00000000}, {0xca4, 0x00000080},
239 {0xca8, 0x00000000}, {0xcac, 0x00000000},
240 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
241 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
242 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
243 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
244 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
245 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
246 {0xce0, 0x00222222}, {0xce4, 0x00000000},
247 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
248 {0xd00, 0x00080740}, {0xd04, 0x00020401},
249 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
250 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
251 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
252 {0xd30, 0x00000000}, {0xd34, 0x80608000},
253 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
254 {0xd40, 0x00000000}, {0xd44, 0x00000000},
255 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
256 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
257 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
258 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
259 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
260 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
261 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
262 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
263 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
264 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
265 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
266 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
267 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
268 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
269 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
270 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
271 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
272 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
273 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
274 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
275 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
276 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
277 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
278 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
279 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
280 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
281 {0xf00, 0x00000300},
282 {0xffff, 0xffffffff},
283};
284
Jes Sorensen36c32582016-02-29 17:04:14 -0500[diff] [blame]285static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
286 {0x800, 0x80040000}, {0x804, 0x00000003},
287 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
288 {0x810, 0x10001331}, {0x814, 0x020c3d10},
289 {0x818, 0x02200385}, {0x81c, 0x00000000},
290 {0x820, 0x01000100}, {0x824, 0x00190204},
291 {0x828, 0x00000000}, {0x82c, 0x00000000},
292 {0x830, 0x00000000}, {0x834, 0x00000000},
293 {0x838, 0x00000000}, {0x83c, 0x00000000},
294 {0x840, 0x00010000}, {0x844, 0x00000000},
295 {0x848, 0x00000000}, {0x84c, 0x00000000},
296 {0x850, 0x00000000}, {0x854, 0x00000000},
297 {0x858, 0x569a11a9}, {0x85c, 0x01000014},
298 {0x860, 0x66f60110}, {0x864, 0x061f0649},
299 {0x868, 0x00000000}, {0x86c, 0x27272700},
300 {0x870, 0x07000760}, {0x874, 0x25004000},
301 {0x878, 0x00000808}, {0x87c, 0x00000000},
302 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
303 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
304 {0x890, 0x00000800}, {0x894, 0xfffffffe},
305 {0x898, 0x40302010}, {0x89c, 0x00706050},
306 {0x900, 0x00000000}, {0x904, 0x00000023},
307 {0x908, 0x00000000}, {0x90c, 0x81121111},
308 {0x910, 0x00000002}, {0x914, 0x00000201},
309 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
310 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
311 {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
312 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
313 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
314 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
315 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
316 {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
317 {0xa80, 0x21806490}, {0xb2c, 0x00000000},
318 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
319 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
320 {0xc10, 0x08800000}, {0xc14, 0x40000100},
321 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
322 {0xc20, 0x00000000}, {0xc24, 0x00000000},
323 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
324 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
325 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
326 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
327 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
328 {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
329 {0xc58, 0x00013149}, {0xc5c, 0x00250492},
330 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
331 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
332 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
333 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
334 {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
335 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
336 {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
337 {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
338 {0xca0, 0x00000000}, {0xca4, 0x000300a0},
339 {0xca8, 0x00000000}, {0xcac, 0x00000000},
340 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
341 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
342 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
343 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
344 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
345 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
346 {0xce0, 0x00222222}, {0xce4, 0x00000000},
347 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
348 {0xd00, 0x00000740}, {0xd04, 0x40020401},
349 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
350 {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
351 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
352 {0xd30, 0x00000000}, {0xd34, 0x80608000},
353 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
354 {0xd40, 0x00000000}, {0xd44, 0x00000000},
355 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
356 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
357 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
358 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
359 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
360 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
361 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
362 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
363 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
364 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
365 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
366 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
367 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
368 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
369 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
370 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
371 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
372 {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
373 {0xe70, 0x00c00096}, {0xe74, 0x01000056},
374 {0xe78, 0x01000014}, {0xe7c, 0x01000056},
375 {0xe80, 0x01000014}, {0xe84, 0x00c00096},
376 {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
377 {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
378 {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
379 {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
380 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
381 {0xf00, 0x00000300},
382 {0x820, 0x01000100}, {0x800, 0x83040000},
383 {0xffff, 0xffffffff},
384};
385
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]386static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
387 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
388 {0x800, 0x80040002}, {0x804, 0x00000003},
389 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
390 {0x810, 0x10000330}, {0x814, 0x020c3d10},
391 {0x818, 0x02200385}, {0x81c, 0x00000000},
392 {0x820, 0x01000100}, {0x824, 0x00390004},
393 {0x828, 0x01000100}, {0x82c, 0x00390004},
394 {0x830, 0x27272727}, {0x834, 0x27272727},
395 {0x838, 0x27272727}, {0x83c, 0x27272727},
396 {0x840, 0x00010000}, {0x844, 0x00010000},
397 {0x848, 0x27272727}, {0x84c, 0x27272727},
398 {0x850, 0x00000000}, {0x854, 0x00000000},
399 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
400 {0x860, 0x66e60230}, {0x864, 0x061f0130},
401 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
402 {0x870, 0x07000700}, {0x874, 0x22184000},
403 {0x878, 0x08080808}, {0x87c, 0x00000000},
404 {0x880, 0xc0083070}, {0x884, 0x000004d5},
405 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
406 {0x890, 0x00000800}, {0x894, 0xfffffffe},
407 {0x898, 0x40302010}, {0x89c, 0x00706050},
408 {0x900, 0x00000000}, {0x904, 0x00000023},
409 {0x908, 0x00000000}, {0x90c, 0x81121313},
410 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
411 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
412 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
413 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
414 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
415 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
416 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
417 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
418 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
419 {0xc10, 0x08800000}, {0xc14, 0x40000100},
420 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
421 {0xc20, 0x00000000}, {0xc24, 0x00000000},
422 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
423 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
424 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
425 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
426 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
427 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
428 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
429 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
430 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
431 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
432 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
433 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
434 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
435 {0xc90, 0x00121820}, {0xc94, 0x00000000},
436 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
437 {0xca0, 0x00000000}, {0xca4, 0x00000080},
438 {0xca8, 0x00000000}, {0xcac, 0x00000000},
439 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
440 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
441 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
442 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
443 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
444 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
445 {0xce0, 0x00222222}, {0xce4, 0x00000000},
446 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
447 {0xd00, 0x00080740}, {0xd04, 0x00020403},
448 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
449 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
450 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
451 {0xd30, 0x00000000}, {0xd34, 0x80608000},
452 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
453 {0xd40, 0x00000000}, {0xd44, 0x00000000},
454 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
455 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
456 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
457 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
458 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
459 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
460 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
461 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
462 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
463 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
464 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
465 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
466 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
467 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
468 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
469 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
470 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
471 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
472 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
473 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
474 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
475 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
476 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
477 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
478 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
479 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
480 {0xf00, 0x00000300},
481 {0xffff, 0xffffffff},
482};
483
484static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
485 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
486 {0x040, 0x000c0004}, {0x800, 0x80040000},
487 {0x804, 0x00000001}, {0x808, 0x0000fc00},
488 {0x80c, 0x0000000a}, {0x810, 0x10005388},
489 {0x814, 0x020c3d10}, {0x818, 0x02200385},
490 {0x81c, 0x00000000}, {0x820, 0x01000100},
491 {0x824, 0x00390204}, {0x828, 0x00000000},
492 {0x82c, 0x00000000}, {0x830, 0x00000000},
493 {0x834, 0x00000000}, {0x838, 0x00000000},
494 {0x83c, 0x00000000}, {0x840, 0x00010000},
495 {0x844, 0x00000000}, {0x848, 0x00000000},
496 {0x84c, 0x00000000}, {0x850, 0x00000000},
497 {0x854, 0x00000000}, {0x858, 0x569a569a},
498 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
499 {0x864, 0x061f0130}, {0x868, 0x00000000},
500 {0x86c, 0x20202000}, {0x870, 0x03000300},
501 {0x874, 0x22004000}, {0x878, 0x00000808},
502 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
503 {0x884, 0x000004d5}, {0x888, 0x00000000},
504 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
505 {0x894, 0xfffffffe}, {0x898, 0x40302010},
506 {0x89c, 0x00706050}, {0x900, 0x00000000},
507 {0x904, 0x00000023}, {0x908, 0x00000000},
508 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
509 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
510 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
511 {0xa14, 0x11144028}, {0xa18, 0x00881117},
512 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
513 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
514 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
515 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
516 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
517 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
518 {0xc14, 0x40000100}, {0xc18, 0x08800000},
519 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
520 {0xc24, 0x00000000}, {0xc28, 0x00000000},
521 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
522 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
523 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
524 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
525 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
526 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
527 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
528 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
529 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
530 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
531 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
532 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
533 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
534 {0xc94, 0x00000000}, {0xc98, 0x00121820},
535 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
536 {0xca4, 0x00000080}, {0xca8, 0x00000000},
537 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
538 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
539 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
540 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
541 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
542 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
543 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
544 {0xce4, 0x00000000}, {0xce8, 0x37644302},
545 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
546 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
547 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
548 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
549 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
550 {0xd34, 0x80608000}, {0xd38, 0x00000000},
551 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
552 {0xd44, 0x00000000}, {0xd48, 0x00000000},
553 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
554 {0xd54, 0x00000000}, {0xd58, 0x00000000},
555 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
556 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
557 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
558 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
559 {0xe00, 0x24242424}, {0xe04, 0x24242424},
560 {0xe08, 0x03902024}, {0xe10, 0x24242424},
561 {0xe14, 0x24242424}, {0xe18, 0x24242424},
562 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
563 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
564 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
565 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
566 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
567 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
568 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
569 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
570 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
571 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
572 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
573 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
574 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
575 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
576 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
577 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
578 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
579 {0xf00, 0x00000300},
580 {0xffff, 0xffffffff},
581};
582
583static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
584 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
585 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
586 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
587 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
588 {0xc78, 0x78080001}, {0xc78, 0x77090001},
589 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
590 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
591 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
592 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
593 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
594 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
595 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
596 {0xc78, 0x68180001}, {0xc78, 0x67190001},
597 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
598 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
599 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
600 {0xc78, 0x60200001}, {0xc78, 0x49210001},
601 {0xc78, 0x48220001}, {0xc78, 0x47230001},
602 {0xc78, 0x46240001}, {0xc78, 0x45250001},
603 {0xc78, 0x44260001}, {0xc78, 0x43270001},
604 {0xc78, 0x42280001}, {0xc78, 0x41290001},
605 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
606 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
607 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
608 {0xc78, 0x21300001}, {0xc78, 0x20310001},
609 {0xc78, 0x06320001}, {0xc78, 0x05330001},
610 {0xc78, 0x04340001}, {0xc78, 0x03350001},
611 {0xc78, 0x02360001}, {0xc78, 0x01370001},
612 {0xc78, 0x00380001}, {0xc78, 0x00390001},
613 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
614 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
615 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
616 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
617 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
618 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
619 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
620 {0xc78, 0x78480001}, {0xc78, 0x77490001},
621 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
622 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
623 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
624 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
625 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
626 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
627 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
628 {0xc78, 0x68580001}, {0xc78, 0x67590001},
629 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
630 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
631 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
632 {0xc78, 0x60600001}, {0xc78, 0x49610001},
633 {0xc78, 0x48620001}, {0xc78, 0x47630001},
634 {0xc78, 0x46640001}, {0xc78, 0x45650001},
635 {0xc78, 0x44660001}, {0xc78, 0x43670001},
636 {0xc78, 0x42680001}, {0xc78, 0x41690001},
637 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
638 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
639 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
640 {0xc78, 0x21700001}, {0xc78, 0x20710001},
641 {0xc78, 0x06720001}, {0xc78, 0x05730001},
642 {0xc78, 0x04740001}, {0xc78, 0x03750001},
643 {0xc78, 0x02760001}, {0xc78, 0x01770001},
644 {0xc78, 0x00780001}, {0xc78, 0x00790001},
645 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
646 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
647 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
648 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
649 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
650 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
651 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
652 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
653 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
654 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
655 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
656 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
657 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
658 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
659 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
660 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
661 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
662 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
663 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
664 {0xffff, 0xffffffff}
665};
666
667static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
668 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
669 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
670 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
671 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
672 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
673 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
674 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
675 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
676 {0xc78, 0x73100001}, {0xc78, 0x72110001},
677 {0xc78, 0x71120001}, {0xc78, 0x70130001},
678 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
679 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
680 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
681 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
682 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
683 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
684 {0xc78, 0x63200001}, {0xc78, 0x62210001},
685 {0xc78, 0x61220001}, {0xc78, 0x60230001},
686 {0xc78, 0x46240001}, {0xc78, 0x45250001},
687 {0xc78, 0x44260001}, {0xc78, 0x43270001},
688 {0xc78, 0x42280001}, {0xc78, 0x41290001},
689 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
690 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
691 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
692 {0xc78, 0x21300001}, {0xc78, 0x20310001},
693 {0xc78, 0x06320001}, {0xc78, 0x05330001},
694 {0xc78, 0x04340001}, {0xc78, 0x03350001},
695 {0xc78, 0x02360001}, {0xc78, 0x01370001},
696 {0xc78, 0x00380001}, {0xc78, 0x00390001},
697 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
698 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
699 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
700 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
701 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
702 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
703 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
704 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
705 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
706 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
707 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
708 {0xc78, 0x73500001}, {0xc78, 0x72510001},
709 {0xc78, 0x71520001}, {0xc78, 0x70530001},
710 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
711 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
712 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
713 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
714 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
715 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
716 {0xc78, 0x63600001}, {0xc78, 0x62610001},
717 {0xc78, 0x61620001}, {0xc78, 0x60630001},
718 {0xc78, 0x46640001}, {0xc78, 0x45650001},
719 {0xc78, 0x44660001}, {0xc78, 0x43670001},
720 {0xc78, 0x42680001}, {0xc78, 0x41690001},
721 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
722 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
723 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
724 {0xc78, 0x21700001}, {0xc78, 0x20710001},
725 {0xc78, 0x06720001}, {0xc78, 0x05730001},
726 {0xc78, 0x04740001}, {0xc78, 0x03750001},
727 {0xc78, 0x02760001}, {0xc78, 0x01770001},
728 {0xc78, 0x00780001}, {0xc78, 0x00790001},
729 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
730 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
731 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
732 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
733 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
734 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
735 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
736 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
737 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
738 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
739 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
740 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
741 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
742 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
743 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
744 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
745 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
746 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
747 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
748 {0xffff, 0xffffffff}
749};
750
Jes Sorensenb9f498e2016-02-29 17:04:18 -0500[diff] [blame]751static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
752 {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
753 {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
754 {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
755 {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
756 {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
757 {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
758 {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
759 {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
760 {0xc78, 0xed100001}, {0xc78, 0xec110001},
761 {0xc78, 0xeb120001}, {0xc78, 0xea130001},
762 {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
763 {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
764 {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
765 {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
766 {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
767 {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
768 {0xc78, 0x65200001}, {0xc78, 0x64210001},
769 {0xc78, 0x63220001}, {0xc78, 0x4a230001},
770 {0xc78, 0x49240001}, {0xc78, 0x48250001},
771 {0xc78, 0x47260001}, {0xc78, 0x46270001},
772 {0xc78, 0x45280001}, {0xc78, 0x44290001},
773 {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
774 {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
775 {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
776 {0xc78, 0x0a300001}, {0xc78, 0x09310001},
777 {0xc78, 0x08320001}, {0xc78, 0x07330001},
778 {0xc78, 0x06340001}, {0xc78, 0x05350001},
779 {0xc78, 0x04360001}, {0xc78, 0x03370001},
780 {0xc78, 0x02380001}, {0xc78, 0x01390001},
781 {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
782 {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
783 {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
784 {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
785 {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
786 {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
787 {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
788 {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
789 {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
790 {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
791 {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
792 {0xc78, 0xec500001}, {0xc78, 0xeb510001},
793 {0xc78, 0xea520001}, {0xc78, 0xe9530001},
794 {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
795 {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
796 {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
797 {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
798 {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
799 {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
800 {0xc78, 0x65600001}, {0xc78, 0x64610001},
801 {0xc78, 0x63620001}, {0xc78, 0x62630001},
802 {0xc78, 0x61640001}, {0xc78, 0x48650001},
803 {0xc78, 0x47660001}, {0xc78, 0x46670001},
804 {0xc78, 0x45680001}, {0xc78, 0x44690001},
805 {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
806 {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
807 {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
808 {0xc78, 0x24700001}, {0xc78, 0x09710001},
809 {0xc78, 0x08720001}, {0xc78, 0x07730001},
810 {0xc78, 0x06740001}, {0xc78, 0x05750001},
811 {0xc78, 0x04760001}, {0xc78, 0x03770001},
812 {0xc78, 0x02780001}, {0xc78, 0x01790001},
813 {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
814 {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
815 {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
816 {0xc50, 0x69553422},
817 {0xc50, 0x69553420},
818 {0x824, 0x00390204},
819 {0xffff, 0xffffffff}
820};
821
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]822static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
823 {0x00, 0x00030159}, {0x01, 0x00031284},
824 {0x02, 0x00098000}, {0x03, 0x00039c63},
825 {0x04, 0x000210e7}, {0x09, 0x0002044f},
826 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
827 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
828 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
829 {0x19, 0x00000000}, {0x1a, 0x00030355},
830 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
831 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
832 {0x1f, 0x00000000}, {0x20, 0x0000b614},
833 {0x21, 0x0006c000}, {0x22, 0x00000000},
834 {0x23, 0x00001558}, {0x24, 0x00000060},
835 {0x25, 0x00000483}, {0x26, 0x0004f000},
836 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
837 {0x29, 0x00004783}, {0x2a, 0x00000001},
838 {0x2b, 0x00021334}, {0x2a, 0x00000000},
839 {0x2b, 0x00000054}, {0x2a, 0x00000001},
840 {0x2b, 0x00000808}, {0x2b, 0x00053333},
841 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
842 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
843 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
844 {0x2b, 0x00000808}, {0x2b, 0x00063333},
845 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
846 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
847 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
848 {0x2b, 0x00000808}, {0x2b, 0x00073333},
849 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
850 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
851 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
852 {0x2b, 0x00000709}, {0x2b, 0x00063333},
853 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
854 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
855 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
856 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
857 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
858 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
859 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
860 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
861 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
862 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
863 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
864 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
865 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
866 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
867 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
868 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
869 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
870 {0x10, 0x0002000f}, {0x11, 0x000203f9},
871 {0x10, 0x0003000f}, {0x11, 0x000ff500},
872 {0x10, 0x00000000}, {0x11, 0x00000000},
873 {0x10, 0x0008000f}, {0x11, 0x0003f100},
874 {0x10, 0x0009000f}, {0x11, 0x00023100},
875 {0x12, 0x00032000}, {0x12, 0x00071000},
876 {0x12, 0x000b0000}, {0x12, 0x000fc000},
877 {0x13, 0x000287b3}, {0x13, 0x000244b7},
878 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
879 {0x13, 0x00018493}, {0x13, 0x0001429b},
880 {0x13, 0x00010299}, {0x13, 0x0000c29c},
881 {0x13, 0x000081a0}, {0x13, 0x000040ac},
882 {0x13, 0x00000020}, {0x14, 0x0001944c},
883 {0x14, 0x00059444}, {0x14, 0x0009944c},
884 {0x14, 0x000d9444}, {0x15, 0x0000f474},
885 {0x15, 0x0004f477}, {0x15, 0x0008f455},
886 {0x15, 0x000cf455}, {0x16, 0x00000339},
887 {0x16, 0x00040339}, {0x16, 0x00080339},
888 {0x16, 0x000c0366}, {0x00, 0x00010159},
889 {0x18, 0x0000f401}, {0xfe, 0x00000000},
890 {0xfe, 0x00000000}, {0x1f, 0x00000003},
891 {0xfe, 0x00000000}, {0xfe, 0x00000000},
892 {0x1e, 0x00000247}, {0x1f, 0x00000000},
893 {0x00, 0x00030159},
894 {0xff, 0xffffffff}
895};
896
Jes Sorensen22a31d42016-02-29 17:04:15 -0500[diff] [blame]897static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
898 {0x00, 0x00010000}, {0xb0, 0x000dffe0},
899 {0xfe, 0x00000000}, {0xfe, 0x00000000},
900 {0xfe, 0x00000000}, {0xb1, 0x00000018},
901 {0xfe, 0x00000000}, {0xfe, 0x00000000},
902 {0xfe, 0x00000000}, {0xb2, 0x00084c00},
903 {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
904 {0xb7, 0x00000010}, {0xb8, 0x0000907f},
905 {0x5c, 0x00000002}, {0x7c, 0x00000002},
906 {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
907 {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
908 {0x1e, 0x00000000}, {0xdf, 0x00000780},
909 {0x50, 0x00067435},
910 /*
911 * The 8723bu vendor driver indicates that bit 8 should be set in
912 * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
913 * they never actually check the package type - and just default
914 * to not setting it.
915 */
916 {0x51, 0x0006b04e},
917 {0x52, 0x000007d2}, {0x53, 0x00000000},
918 {0x54, 0x00050400}, {0x55, 0x0004026e},
919 {0xdd, 0x0000004c}, {0x70, 0x00067435},
920 /*
921 * 0x71 has same package type condition as for register 0x51
922 */
923 {0x71, 0x0006b04e},
924 {0x72, 0x000007d2}, {0x73, 0x00000000},
925 {0x74, 0x00050400}, {0x75, 0x0004026e},
926 {0xef, 0x00000100}, {0x34, 0x0000add7},
927 {0x35, 0x00005c00}, {0x34, 0x00009dd4},
928 {0x35, 0x00005000}, {0x34, 0x00008dd1},
929 {0x35, 0x00004400}, {0x34, 0x00007dce},
930 {0x35, 0x00003800}, {0x34, 0x00006cd1},
931 {0x35, 0x00004400}, {0x34, 0x00005cce},
932 {0x35, 0x00003800}, {0x34, 0x000048ce},
933 {0x35, 0x00004400}, {0x34, 0x000034ce},
934 {0x35, 0x00003800}, {0x34, 0x00002451},
935 {0x35, 0x00004400}, {0x34, 0x0000144e},
936 {0x35, 0x00003800}, {0x34, 0x00000051},
937 {0x35, 0x00004400}, {0xef, 0x00000000},
938 {0xef, 0x00000100}, {0xed, 0x00000010},
939 {0x44, 0x0000add7}, {0x44, 0x00009dd4},
940 {0x44, 0x00008dd1}, {0x44, 0x00007dce},
941 {0x44, 0x00006cc1}, {0x44, 0x00005cce},
942 {0x44, 0x000044d1}, {0x44, 0x000034ce},
943 {0x44, 0x00002451}, {0x44, 0x0000144e},
944 {0x44, 0x00000051}, {0xef, 0x00000000},
945 {0xed, 0x00000000}, {0x7f, 0x00020080},
946 {0xef, 0x00002000}, {0x3b, 0x000380ef},
947 {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
948 {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
949 {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
950 {0x3b, 0x00000900}, {0xef, 0x00000000},
951 {0xed, 0x00000001}, {0x40, 0x000380ef},
952 {0x40, 0x000302fe}, {0x40, 0x00028ce6},
953 {0x40, 0x000200bc}, {0x40, 0x000188a5},
954 {0x40, 0x00010fbc}, {0x40, 0x00008f71},
955 {0x40, 0x00000900}, {0xed, 0x00000000},
956 {0x82, 0x00080000}, {0x83, 0x00008000},
957 {0x84, 0x00048d80}, {0x85, 0x00068000},
958 {0xa2, 0x00080000}, {0xa3, 0x00008000},
959 {0xa4, 0x00048d80}, {0xa5, 0x00068000},
960 {0xed, 0x00000002}, {0xef, 0x00000002},
961 {0x56, 0x00000032}, {0x76, 0x00000032},
962 {0x01, 0x00000780},
963 {0xff, 0xffffffff}
964};
965
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]966static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
967 {0x00, 0x00030159}, {0x01, 0x00031284},
968 {0x02, 0x00098000}, {0x03, 0x00018c63},
969 {0x04, 0x000210e7}, {0x09, 0x0002044f},
970 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
971 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
972 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
973 {0x19, 0x00000000}, {0x1a, 0x00010255},
974 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
975 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
976 {0x1f, 0x00080001}, {0x20, 0x0000b614},
977 {0x21, 0x0006c000}, {0x22, 0x00000000},
978 {0x23, 0x00001558}, {0x24, 0x00000060},
979 {0x25, 0x00000483}, {0x26, 0x0004f000},
980 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
981 {0x29, 0x00004783}, {0x2a, 0x00000001},
982 {0x2b, 0x00021334}, {0x2a, 0x00000000},
983 {0x2b, 0x00000054}, {0x2a, 0x00000001},
984 {0x2b, 0x00000808}, {0x2b, 0x00053333},
985 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
986 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
987 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
988 {0x2b, 0x00000808}, {0x2b, 0x00063333},
989 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
990 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
991 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
992 {0x2b, 0x00000808}, {0x2b, 0x00073333},
993 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
994 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
995 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
996 {0x2b, 0x00000709}, {0x2b, 0x00063333},
997 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
998 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
999 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1000 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1001 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1002 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1003 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1004 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1005 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1006 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1007 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1008 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1009 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1010 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1011 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1012 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1013 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1014 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1015 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1016 {0x10, 0x00000000}, {0x11, 0x00000000},
1017 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1018 {0x10, 0x0009000f}, {0x11, 0x00023100},
1019 {0x12, 0x00032000}, {0x12, 0x00071000},
1020 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1021 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1022 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1023 {0x13, 0x00018493}, {0x13, 0x0001429b},
1024 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1025 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1026 {0x13, 0x00000020}, {0x14, 0x0001944c},
1027 {0x14, 0x00059444}, {0x14, 0x0009944c},
1028 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1029 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1030 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1031 {0x16, 0x000a0330}, {0x16, 0x00060330},
1032 {0x16, 0x00020330}, {0x00, 0x00010159},
1033 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1034 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1035 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1036 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1037 {0x00, 0x00030159},
1038 {0xff, 0xffffffff}
1039};
1040
1041static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
1042 {0x00, 0x00030159}, {0x01, 0x00031284},
1043 {0x02, 0x00098000}, {0x03, 0x00018c63},
1044 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1045 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1046 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1047 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1048 {0x12, 0x00032000}, {0x12, 0x00071000},
1049 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1050 {0x13, 0x000287af}, {0x13, 0x000244b7},
1051 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1052 {0x13, 0x00018493}, {0x13, 0x00014297},
1053 {0x13, 0x00010295}, {0x13, 0x0000c298},
1054 {0x13, 0x0000819c}, {0x13, 0x000040a8},
1055 {0x13, 0x0000001c}, {0x14, 0x0001944c},
1056 {0x14, 0x00059444}, {0x14, 0x0009944c},
1057 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1058 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1059 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1060 {0x16, 0x000a0330}, {0x16, 0x00060330},
1061 {0x16, 0x00020330},
1062 {0xff, 0xffffffff}
1063};
1064
1065static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
1066 {0x00, 0x00030159}, {0x01, 0x00031284},
1067 {0x02, 0x00098000}, {0x03, 0x00018c63},
1068 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1069 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1070 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1071 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1072 {0x19, 0x00000000}, {0x1a, 0x00010255},
1073 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1074 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1075 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1076 {0x21, 0x0006c000}, {0x22, 0x00000000},
1077 {0x23, 0x00001558}, {0x24, 0x00000060},
1078 {0x25, 0x00000483}, {0x26, 0x0004f000},
1079 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1080 {0x29, 0x00004783}, {0x2a, 0x00000001},
1081 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1082 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1083 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1084 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1085 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1086 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1087 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1088 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1089 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1090 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1091 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1092 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1093 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1094 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1095 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1096 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1097 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1098 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1099 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1100 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1101 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1102 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1103 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1104 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1105 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1106 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1107 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1108 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1109 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1110 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1111 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1112 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1113 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1114 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1115 {0x10, 0x00000000}, {0x11, 0x00000000},
1116 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1117 {0x10, 0x0009000f}, {0x11, 0x00023100},
1118 {0x12, 0x00032000}, {0x12, 0x00071000},
1119 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1120 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1121 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1122 {0x13, 0x00018493}, {0x13, 0x0001429b},
1123 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1124 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1125 {0x13, 0x00000020}, {0x14, 0x0001944c},
1126 {0x14, 0x00059444}, {0x14, 0x0009944c},
1127 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1128 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1129 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1130 {0x16, 0x000a0330}, {0x16, 0x00060330},
1131 {0x16, 0x00020330}, {0x00, 0x00010159},
1132 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1133 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1134 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1135 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1136 {0x00, 0x00030159},
1137 {0xff, 0xffffffff}
1138};
1139
1140static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
1141 {0x00, 0x00030159}, {0x01, 0x00031284},
1142 {0x02, 0x00098000}, {0x03, 0x00018c63},
1143 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1144 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1145 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1146 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1147 {0x19, 0x00000000}, {0x1a, 0x00000255},
1148 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1149 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1150 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1151 {0x21, 0x0006c000}, {0x22, 0x0000083c},
1152 {0x23, 0x00001558}, {0x24, 0x00000060},
1153 {0x25, 0x00000483}, {0x26, 0x0004f000},
1154 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1155 {0x29, 0x00004783}, {0x2a, 0x00000001},
1156 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1157 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1158 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1159 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1160 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1161 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1162 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1163 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1164 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1165 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1166 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1167 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1168 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1169 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1170 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1171 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1172 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1173 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1174 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1175 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1176 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1177 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1178 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1179 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1180 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1181 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1182 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1183 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1184 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1185 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1186 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1187 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1188 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1189 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1190 {0x10, 0x00000000}, {0x11, 0x00000000},
1191 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1192 {0x10, 0x0009000f}, {0x11, 0x00023100},
1193 {0x12, 0x000d8000}, {0x12, 0x00090000},
1194 {0x12, 0x00051000}, {0x12, 0x00012000},
1195 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1196 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1197 {0x13, 0x000183a4}, {0x13, 0x00014398},
1198 {0x13, 0x000101a4}, {0x13, 0x0000c198},
1199 {0x13, 0x000080a4}, {0x13, 0x00004098},
1200 {0x13, 0x00000000}, {0x14, 0x0001944c},
1201 {0x14, 0x00059444}, {0x14, 0x0009944c},
1202 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1203 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1204 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1205 {0x16, 0x000a0330}, {0x16, 0x00060330},
1206 {0x16, 0x00020330}, {0x00, 0x00010159},
1207 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1208 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1209 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1210 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1211 {0x00, 0x00030159},
1212 {0xff, 0xffffffff}
1213};
1214
1215static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
1216 { /* RF_A */
1217 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
1218 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
1219 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
1220 .hspiread = REG_HSPI_XA_READBACK,
1221 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
1222 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
1223 },
1224 { /* RF_B */
1225 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
1226 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
1227 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
1228 .hspiread = REG_HSPI_XB_READBACK,
1229 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
1230 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
1231 },
1232};
1233
1234static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
1235 REG_OFDM0_XA_RX_IQ_IMBALANCE,
1236 REG_OFDM0_XB_RX_IQ_IMBALANCE,
1237 REG_OFDM0_ENERGY_CCA_THRES,
1238 REG_OFDM0_AGCR_SSI_TABLE,
1239 REG_OFDM0_XA_TX_IQ_IMBALANCE,
1240 REG_OFDM0_XB_TX_IQ_IMBALANCE,
1241 REG_OFDM0_XC_TX_AFE,
1242 REG_OFDM0_XD_TX_AFE,
1243 REG_OFDM0_RX_IQ_EXT_ANTA
1244};
1245
1246static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
1247{
1248 struct usb_device *udev = priv->udev;
1249 int len;
1250 u8 data;
1251
1252 mutex_lock(&priv->usb_buf_mutex);
1253 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1254 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1255 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1256 RTW_USB_CONTROL_MSG_TIMEOUT);
1257 data = priv->usb_buf.val8;
1258 mutex_unlock(&priv->usb_buf_mutex);
1259
1260 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1261 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
1262 __func__, addr, data, len);
1263 return data;
1264}
1265
1266static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
1267{
1268 struct usb_device *udev = priv->udev;
1269 int len;
1270 u16 data;
1271
1272 mutex_lock(&priv->usb_buf_mutex);
1273 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1274 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1275 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1276 RTW_USB_CONTROL_MSG_TIMEOUT);
1277 data = le16_to_cpu(priv->usb_buf.val16);
1278 mutex_unlock(&priv->usb_buf_mutex);
1279
1280 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1281 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
1282 __func__, addr, data, len);
1283 return data;
1284}
1285
1286static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1287{
1288 struct usb_device *udev = priv->udev;
1289 int len;
1290 u32 data;
1291
1292 mutex_lock(&priv->usb_buf_mutex);
1293 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1294 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1295 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1296 RTW_USB_CONTROL_MSG_TIMEOUT);
1297 data = le32_to_cpu(priv->usb_buf.val32);
1298 mutex_unlock(&priv->usb_buf_mutex);
1299
1300 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1301 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
1302 __func__, addr, data, len);
1303 return data;
1304}
1305
1306static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1307{
1308 struct usb_device *udev = priv->udev;
1309 int ret;
1310
1311 mutex_lock(&priv->usb_buf_mutex);
1312 priv->usb_buf.val8 = val;
1313 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1314 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1315 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1316 RTW_USB_CONTROL_MSG_TIMEOUT);
1317
1318 mutex_unlock(&priv->usb_buf_mutex);
1319
1320 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1321 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1322 __func__, addr, val);
1323 return ret;
1324}
1325
1326static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1327{
1328 struct usb_device *udev = priv->udev;
1329 int ret;
1330
1331 mutex_lock(&priv->usb_buf_mutex);
1332 priv->usb_buf.val16 = cpu_to_le16(val);
1333 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1334 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1335 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1336 RTW_USB_CONTROL_MSG_TIMEOUT);
1337 mutex_unlock(&priv->usb_buf_mutex);
1338
1339 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1340 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1341 __func__, addr, val);
1342 return ret;
1343}
1344
1345static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1346{
1347 struct usb_device *udev = priv->udev;
1348 int ret;
1349
1350 mutex_lock(&priv->usb_buf_mutex);
1351 priv->usb_buf.val32 = cpu_to_le32(val);
1352 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1353 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1354 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1355 RTW_USB_CONTROL_MSG_TIMEOUT);
1356 mutex_unlock(&priv->usb_buf_mutex);
1357
1358 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1359 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1360 __func__, addr, val);
1361 return ret;
1362}
1363
1364static int
1365rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1366{
1367 struct usb_device *udev = priv->udev;
1368 int blocksize = priv->fops->writeN_block_size;
1369 int ret, i, count, remainder;
1370
1371 count = len / blocksize;
1372 remainder = len % blocksize;
1373
1374 for (i = 0; i < count; i++) {
1375 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1376 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1377 addr, 0, buf, blocksize,
1378 RTW_USB_CONTROL_MSG_TIMEOUT);
1379 if (ret != blocksize)
1380 goto write_error;
1381
1382 addr += blocksize;
1383 buf += blocksize;
1384 }
1385
1386 if (remainder) {
1387 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1388 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1389 addr, 0, buf, remainder,
1390 RTW_USB_CONTROL_MSG_TIMEOUT);
1391 if (ret != remainder)
1392 goto write_error;
1393 }
1394
1395 return len;
1396
1397write_error:
1398 dev_info(&udev->dev,
1399 "%s: Failed to write block at addr: %04x size: %04x\n",
1400 __func__, addr, blocksize);
1401 return -EAGAIN;
1402}
1403
1404static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1405 enum rtl8xxxu_rfpath path, u8 reg)
1406{
1407 u32 hssia, val32, retval;
1408
1409 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1410 if (path != RF_A)
1411 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1412 else
1413 val32 = hssia;
1414
1415 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1416 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1417 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1418 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1419 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1420
1421 udelay(10);
1422
1423 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1424 udelay(100);
1425
1426 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1427 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1428 udelay(10);
1429
1430 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1431 if (val32 & FPGA0_HSSI_PARM1_PI)
1432 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1433 else
1434 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1435
1436 retval &= 0xfffff;
1437
1438 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1439 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1440 __func__, reg, retval);
1441 return retval;
1442}
1443
Jes Sorensen22a31d42016-02-29 17:04:15 -0500[diff] [blame]1444/*
1445 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1446 * have write issues in high temperature conditions. We may have to
1447 * retry writing them.
1448 */
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1449static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1450 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1451{
1452 int ret, retval;
1453 u32 dataaddr;
1454
1455 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1456 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1457 __func__, reg, data);
1458
1459 data &= FPGA0_LSSI_PARM_DATA_MASK;
1460 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1461
1462 /* Use XB for path B */
1463 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1464 if (ret != sizeof(dataaddr))
1465 retval = -EIO;
1466 else
1467 retval = 0;
1468
1469 udelay(1);
1470
1471 return retval;
1472}
1473
1474static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c)
1475{
1476 struct device *dev = &priv->udev->dev;
1477 int mbox_nr, retry, retval = 0;
1478 int mbox_reg, mbox_ext_reg;
1479 u8 val8;
1480
1481 mutex_lock(&priv->h2c_mutex);
1482
1483 mbox_nr = priv->next_mbox;
1484 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
Jes Sorensened35d092016-02-29 17:04:19 -0500[diff] [blame]1485 mbox_ext_reg = priv->fops->mbox_ext_reg +
1486 (mbox_nr * priv->fops->mbox_ext_width);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1487
1488 /*
1489 * MBOX ready?
1490 */
1491 retry = 100;
1492 do {
1493 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1494 if (!(val8 & BIT(mbox_nr)))
1495 break;
1496 } while (retry--);
1497
1498 if (!retry) {
1499 dev_dbg(dev, "%s: Mailbox busy\n", __func__);
1500 retval = -EBUSY;
1501 goto error;
1502 }
1503
1504 /*
1505 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1506 */
1507 if (h2c->cmd.cmd & H2C_EXT) {
Jes Sorensened35d092016-02-29 17:04:19 -0500[diff] [blame]1508 if (priv->fops->mbox_ext_width == 4) {
1509 rtl8xxxu_write32(priv, mbox_ext_reg,
1510 le32_to_cpu(h2c->raw_wide.ext));
1511 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1512 dev_info(dev, "H2C_EXT %08x\n",
1513 le32_to_cpu(h2c->raw_wide.ext));
1514 } else {
1515 rtl8xxxu_write16(priv, mbox_ext_reg,
1516 le16_to_cpu(h2c->raw.ext));
1517 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1518 dev_info(dev, "H2C_EXT %04x\n",
1519 le16_to_cpu(h2c->raw.ext));
1520 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1521 }
1522 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1523 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1524 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1525
1526 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1527
1528error:
1529 mutex_unlock(&priv->h2c_mutex);
1530 return retval;
1531}
1532
1533static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1534{
1535 u8 val8;
1536 u32 val32;
1537
1538 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1539 val8 |= BIT(0) | BIT(3);
1540 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1541
1542 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1543 val32 &= ~(BIT(4) | BIT(5));
1544 val32 |= BIT(3);
1545 if (priv->rf_paths == 2) {
1546 val32 &= ~(BIT(20) | BIT(21));
1547 val32 |= BIT(19);
1548 }
1549 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1550
1551 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1552 val32 &= ~OFDM_RF_PATH_TX_MASK;
1553 if (priv->tx_paths == 2)
1554 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1555 else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1556 val32 |= OFDM_RF_PATH_TX_B;
1557 else
1558 val32 |= OFDM_RF_PATH_TX_A;
1559 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1560
1561 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1562 val32 &= ~FPGA_RF_MODE_JAPAN;
1563 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1564
1565 if (priv->rf_paths == 2)
1566 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1567 else
1568 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1569
1570 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1571 if (priv->rf_paths == 2)
1572 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1573
1574 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1575}
1576
1577static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1578{
1579 u8 sps0;
1580 u32 val32;
1581
1582 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1583
1584 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1585
1586 /* RF RX code for preamble power saving */
1587 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1588 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1589 if (priv->rf_paths == 2)
1590 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1591 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1592
1593 /* Disable TX for four paths */
1594 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1595 val32 &= ~OFDM_RF_PATH_TX_MASK;
1596 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1597
1598 /* Enable power saving */
1599 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1600 val32 |= FPGA_RF_MODE_JAPAN;
1601 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1602
1603 /* AFE control register to power down bits [30:22] */
1604 if (priv->rf_paths == 2)
1605 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1606 else
1607 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1608
1609 /* Power down RF module */
1610 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1611 if (priv->rf_paths == 2)
1612 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1613
1614 sps0 &= ~(BIT(0) | BIT(3));
1615 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1616}
1617
1618
1619static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1620{
1621 u8 val8;
1622
1623 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1624 val8 &= ~BIT(6);
1625 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1626
1627 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1628 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1629 val8 &= ~BIT(0);
1630 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1631}
1632
1633
1634/*
1635 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1636 * supports the 2.4GHz band, so channels 1 - 14:
1637 * group 0: channels 1 - 3
1638 * group 1: channels 4 - 9
1639 * group 2: channels 10 - 14
1640 *
1641 * Note: We index from 0 in the code
1642 */
1643static int rtl8723a_channel_to_group(int channel)
1644{
1645 int group;
1646
1647 if (channel < 4)
1648 group = 0;
1649 else if (channel < 10)
1650 group = 1;
1651 else
1652 group = 2;
1653
1654 return group;
1655}
1656
1657static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1658{
1659 struct rtl8xxxu_priv *priv = hw->priv;
1660 u32 val32, rsr;
1661 u8 val8, opmode;
1662 bool ht = true;
1663 int sec_ch_above, channel;
1664 int i;
1665
1666 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1667 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1668 channel = hw->conf.chandef.chan->hw_value;
1669
1670 switch (hw->conf.chandef.width) {
1671 case NL80211_CHAN_WIDTH_20_NOHT:
1672 ht = false;
1673 case NL80211_CHAN_WIDTH_20:
1674 opmode |= BW_OPMODE_20MHZ;
1675 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1676
1677 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1678 val32 &= ~FPGA_RF_MODE;
1679 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1680
1681 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1682 val32 &= ~FPGA_RF_MODE;
1683 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1684
1685 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1686 val32 |= FPGA0_ANALOG2_20MHZ;
1687 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1688 break;
1689 case NL80211_CHAN_WIDTH_40:
1690 if (hw->conf.chandef.center_freq1 >
1691 hw->conf.chandef.chan->center_freq) {
1692 sec_ch_above = 1;
1693 channel += 2;
1694 } else {
1695 sec_ch_above = 0;
1696 channel -= 2;
1697 }
1698
1699 opmode &= ~BW_OPMODE_20MHZ;
1700 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1701 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1702 if (sec_ch_above)
1703 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1704 else
1705 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1706 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1707
1708 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1709 val32 |= FPGA_RF_MODE;
1710 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1711
1712 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1713 val32 |= FPGA_RF_MODE;
1714 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1715
1716 /*
1717 * Set Control channel to upper or lower. These settings
1718 * are required only for 40MHz
1719 */
1720 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1721 val32 &= ~CCK0_SIDEBAND;
1722 if (!sec_ch_above)
1723 val32 |= CCK0_SIDEBAND;
1724 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1725
1726 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1727 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1728 if (sec_ch_above)
1729 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1730 else
1731 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1732 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1733
1734 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1735 val32 &= ~FPGA0_ANALOG2_20MHZ;
1736 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1737
1738 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1739 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1740 if (sec_ch_above)
1741 val32 |= FPGA0_PS_UPPER_CHANNEL;
1742 else
1743 val32 |= FPGA0_PS_LOWER_CHANNEL;
1744 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1745 break;
1746
1747 default:
1748 break;
1749 }
1750
1751 for (i = RF_A; i < priv->rf_paths; i++) {
1752 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1753 val32 &= ~MODE_AG_CHANNEL_MASK;
1754 val32 |= channel;
1755 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1756 }
1757
1758 if (ht)
1759 val8 = 0x0e;
1760 else
1761 val8 = 0x0a;
1762
1763 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1764 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1765
1766 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1767 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1768
1769 for (i = RF_A; i < priv->rf_paths; i++) {
1770 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1771 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1772 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1773 else
1774 val32 |= MODE_AG_CHANNEL_20MHZ;
1775 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1776 }
1777}
1778
1779static void
1780rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1781{
1782 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1783 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1784 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1785 u8 val8;
1786 int group, i;
1787
1788 group = rtl8723a_channel_to_group(channel);
1789
1790 cck[0] = priv->cck_tx_power_index_A[group];
1791 cck[1] = priv->cck_tx_power_index_B[group];
1792
1793 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1794 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1795
1796 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1797 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1798
1799 mcsbase[0] = ofdm[0];
1800 mcsbase[1] = ofdm[1];
1801 if (!ht40) {
1802 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1803 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1804 }
1805
1806 if (priv->tx_paths > 1) {
1807 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1808 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
1809 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1810 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
1811 }
1812
1813 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1814 dev_info(&priv->udev->dev,
1815 "%s: Setting TX power CCK A: %02x, "
1816 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1817 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1818
1819 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1820 if (cck[i] > RF6052_MAX_TX_PWR)
1821 cck[i] = RF6052_MAX_TX_PWR;
1822 if (ofdm[i] > RF6052_MAX_TX_PWR)
1823 ofdm[i] = RF6052_MAX_TX_PWR;
1824 }
1825
1826 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1827 val32 &= 0xffff00ff;
1828 val32 |= (cck[0] << 8);
1829 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1830
1831 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1832 val32 &= 0xff;
1833 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1834 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1835
1836 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1837 val32 &= 0xffffff00;
1838 val32 |= cck[1];
1839 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1840
1841 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1842 val32 &= 0xff;
1843 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1844 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1845
1846 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1847 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1848 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1849 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1850 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
1851 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
1852
1853 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
1854 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
1855
1856 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1857 mcsbase[0] << 16 | mcsbase[0] << 24;
1858 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1859 mcsbase[1] << 16 | mcsbase[1] << 24;
1860
1861 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
1862 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
1863
1864 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
1865 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
1866
1867 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
1868 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
1869
1870 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
1871 for (i = 0; i < 3; i++) {
1872 if (i != 2)
1873 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1874 else
1875 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1876 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1877 }
1878 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
1879 for (i = 0; i < 3; i++) {
1880 if (i != 2)
1881 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1882 else
1883 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1884 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1885 }
1886}
1887
1888static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1889 enum nl80211_iftype linktype)
1890{
Jes Sorensena26703f2016-02-03 13:39:56 -0500[diff] [blame]1891 u8 val8;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1892
Jes Sorensena26703f2016-02-03 13:39:56 -0500[diff] [blame]1893 val8 = rtl8xxxu_read8(priv, REG_MSR);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1894 val8 &= ~MSR_LINKTYPE_MASK;
1895
1896 switch (linktype) {
1897 case NL80211_IFTYPE_UNSPECIFIED:
1898 val8 |= MSR_LINKTYPE_NONE;
1899 break;
1900 case NL80211_IFTYPE_ADHOC:
1901 val8 |= MSR_LINKTYPE_ADHOC;
1902 break;
1903 case NL80211_IFTYPE_STATION:
1904 val8 |= MSR_LINKTYPE_STATION;
1905 break;
1906 case NL80211_IFTYPE_AP:
1907 val8 |= MSR_LINKTYPE_AP;
1908 break;
1909 default:
1910 goto out;
1911 }
1912
1913 rtl8xxxu_write8(priv, REG_MSR, val8);
1914out:
1915 return;
1916}
1917
1918static void
1919rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1920{
1921 u16 val16;
1922
1923 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1924 RETRY_LIMIT_SHORT_MASK) |
1925 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1926 RETRY_LIMIT_LONG_MASK);
1927
1928 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1929}
1930
1931static void
1932rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1933{
1934 u16 val16;
1935
1936 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1937 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1938
1939 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1940}
1941
1942static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1943{
1944 struct device *dev = &priv->udev->dev;
1945 char *cut;
1946
1947 switch (priv->chip_cut) {
1948 case 0:
1949 cut = "A";
1950 break;
1951 case 1:
1952 cut = "B";
1953 break;
Jes Sorensen0e5d4352016-02-29 17:04:00 -0500[diff] [blame]1954 case 2:
1955 cut = "C";
1956 break;
1957 case 3:
1958 cut = "D";
1959 break;
1960 case 4:
1961 cut = "E";
1962 break;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1963 default:
1964 cut = "unknown";
1965 }
1966
1967 dev_info(dev,
1968 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
Jes Sorensen0e5d4352016-02-29 17:04:00 -0500[diff] [blame]1969 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
1970 priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
1971 priv->has_bluetooth, priv->has_gps, priv->hi_pa);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1972
1973 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1974}
1975
1976static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
1977{
1978 struct device *dev = &priv->udev->dev;
1979 u32 val32, bonding;
1980 u16 val16;
1981
1982 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1983 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
1984 SYS_CFG_CHIP_VERSION_SHIFT;
1985 if (val32 & SYS_CFG_TRP_VAUX_EN) {
1986 dev_info(dev, "Unsupported test chip\n");
1987 return -ENOTSUPP;
1988 }
1989
1990 if (val32 & SYS_CFG_BT_FUNC) {
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]1991 if (priv->chip_cut >= 3) {
1992 sprintf(priv->chip_name, "8723BU");
1993 priv->rtlchip = 0x8723b;
1994 } else {
1995 sprintf(priv->chip_name, "8723AU");
Jes Sorensen0e28b972016-02-29 17:04:13 -0500[diff] [blame]1996 priv->usb_interrupts = 1;
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]1997 priv->rtlchip = 0x8723a;
1998 }
1999
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2000 priv->rf_paths = 1;
2001 priv->rx_paths = 1;
2002 priv->tx_paths = 1;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2003
2004 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
2005 if (val32 & MULTI_WIFI_FUNC_EN)
2006 priv->has_wifi = 1;
2007 if (val32 & MULTI_BT_FUNC_EN)
2008 priv->has_bluetooth = 1;
2009 if (val32 & MULTI_GPS_FUNC_EN)
2010 priv->has_gps = 1;
Jakub Sitnicki38451992016-02-03 13:39:49 -0500[diff] [blame]2011 priv->is_multi_func = 1;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2012 } else if (val32 & SYS_CFG_TYPE_ID) {
2013 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
2014 bonding &= HPON_FSM_BONDING_MASK;
Jes Sorensen0e5d4352016-02-29 17:04:00 -0500[diff] [blame]2015 if (priv->chip_cut >= 3) {
2016 if (bonding == HPON_FSM_BONDING_1T2R) {
2017 sprintf(priv->chip_name, "8191EU");
2018 priv->rf_paths = 2;
2019 priv->rx_paths = 2;
2020 priv->tx_paths = 1;
2021 priv->rtlchip = 0x8191e;
2022 } else {
2023 sprintf(priv->chip_name, "8192EU");
2024 priv->rf_paths = 2;
2025 priv->rx_paths = 2;
2026 priv->tx_paths = 2;
2027 priv->rtlchip = 0x8192e;
2028 }
2029 } else if (bonding == HPON_FSM_BONDING_1T2R) {
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2030 sprintf(priv->chip_name, "8191CU");
2031 priv->rf_paths = 2;
2032 priv->rx_paths = 2;
2033 priv->tx_paths = 1;
Jes Sorensen0e28b972016-02-29 17:04:13 -0500[diff] [blame]2034 priv->usb_interrupts = 1;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2035 priv->rtlchip = 0x8191c;
2036 } else {
2037 sprintf(priv->chip_name, "8192CU");
2038 priv->rf_paths = 2;
2039 priv->rx_paths = 2;
2040 priv->tx_paths = 2;
Jes Sorensen0e28b972016-02-29 17:04:13 -0500[diff] [blame]2041 priv->usb_interrupts = 1;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2042 priv->rtlchip = 0x8192c;
2043 }
2044 priv->has_wifi = 1;
2045 } else {
2046 sprintf(priv->chip_name, "8188CU");
2047 priv->rf_paths = 1;
2048 priv->rx_paths = 1;
2049 priv->tx_paths = 1;
2050 priv->rtlchip = 0x8188c;
Jes Sorensen0e28b972016-02-29 17:04:13 -0500[diff] [blame]2051 priv->usb_interrupts = 1;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2052 priv->has_wifi = 1;
2053 }
2054
Jes Sorensen0e5d4352016-02-29 17:04:00 -0500[diff] [blame]2055 switch (priv->rtlchip) {
2056 case 0x8188e:
2057 case 0x8192e:
2058 case 0x8723b:
2059 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
2060 case SYS_CFG_VENDOR_ID_TSMC:
2061 sprintf(priv->chip_vendor, "TSMC");
2062 break;
2063 case SYS_CFG_VENDOR_ID_SMIC:
2064 sprintf(priv->chip_vendor, "SMIC");
2065 priv->vendor_smic = 1;
2066 break;
2067 case SYS_CFG_VENDOR_ID_UMC:
2068 sprintf(priv->chip_vendor, "UMC");
2069 priv->vendor_umc = 1;
2070 break;
2071 default:
2072 sprintf(priv->chip_vendor, "unknown");
2073 }
2074 break;
2075 default:
2076 if (val32 & SYS_CFG_VENDOR_ID) {
2077 sprintf(priv->chip_vendor, "UMC");
2078 priv->vendor_umc = 1;
2079 } else {
2080 sprintf(priv->chip_vendor, "TSMC");
2081 }
2082 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2083
2084 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
2085 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
2086
2087 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
2088 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
2089 priv->ep_tx_high_queue = 1;
2090 priv->ep_tx_count++;
2091 }
2092
2093 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
2094 priv->ep_tx_normal_queue = 1;
2095 priv->ep_tx_count++;
2096 }
2097
2098 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
2099 priv->ep_tx_low_queue = 1;
2100 priv->ep_tx_count++;
2101 }
2102
2103 /*
2104 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2105 */
2106 if (!priv->ep_tx_count) {
2107 switch (priv->nr_out_eps) {
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]2108 case 4:
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2109 case 3:
2110 priv->ep_tx_low_queue = 1;
2111 priv->ep_tx_count++;
2112 case 2:
2113 priv->ep_tx_normal_queue = 1;
2114 priv->ep_tx_count++;
2115 case 1:
2116 priv->ep_tx_high_queue = 1;
2117 priv->ep_tx_count++;
2118 break;
2119 default:
2120 dev_info(dev, "Unsupported USB TX end-points\n");
2121 return -ENOTSUPP;
2122 }
2123 }
2124
2125 return 0;
2126}
2127
2128static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
2129{
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2130 struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
2131
2132 if (efuse->rtl_id != cpu_to_le16(0x8129))
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2133 return -EINVAL;
2134
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2135 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2136
2137 memcpy(priv->cck_tx_power_index_A,
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2138 efuse->cck_tx_power_index_A,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2139 sizeof(priv->cck_tx_power_index_A));
2140 memcpy(priv->cck_tx_power_index_B,
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2141 efuse->cck_tx_power_index_B,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2142 sizeof(priv->cck_tx_power_index_B));
2143
2144 memcpy(priv->ht40_1s_tx_power_index_A,
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2145 efuse->ht40_1s_tx_power_index_A,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2146 sizeof(priv->ht40_1s_tx_power_index_A));
2147 memcpy(priv->ht40_1s_tx_power_index_B,
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2148 efuse->ht40_1s_tx_power_index_B,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2149 sizeof(priv->ht40_1s_tx_power_index_B));
2150
2151 memcpy(priv->ht20_tx_power_index_diff,
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2152 efuse->ht20_tx_power_index_diff,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2153 sizeof(priv->ht20_tx_power_index_diff));
2154 memcpy(priv->ofdm_tx_power_index_diff,
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2155 efuse->ofdm_tx_power_index_diff,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2156 sizeof(priv->ofdm_tx_power_index_diff));
2157
2158 memcpy(priv->ht40_max_power_offset,
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2159 efuse->ht40_max_power_offset,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2160 sizeof(priv->ht40_max_power_offset));
2161 memcpy(priv->ht20_max_power_offset,
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2162 efuse->ht20_max_power_offset,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2163 sizeof(priv->ht20_max_power_offset));
2164
2165 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2166 efuse->vendor_name);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2167 dev_info(&priv->udev->dev, "Product: %.41s\n",
Jakub Sitnickid38f1c32016-02-29 17:04:25 -0500[diff] [blame]2168 efuse->device_name);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2169 return 0;
2170}
2171
Jes Sorensen3c836d62016-02-29 17:04:11 -0500[diff] [blame]2172static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
2173{
2174 if (priv->efuse_wifi.efuse8723bu.rtl_id != cpu_to_le16(0x8129))
2175 return -EINVAL;
2176
2177 ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8723bu.mac_addr);
2178
2179 memcpy(priv->cck_tx_power_index_A,
2180 priv->efuse_wifi.efuse8723bu.cck_tx_power_index_A,
2181 sizeof(priv->cck_tx_power_index_A));
2182 memcpy(priv->cck_tx_power_index_B,
2183 priv->efuse_wifi.efuse8723bu.cck_tx_power_index_B,
2184 sizeof(priv->cck_tx_power_index_B));
2185
2186 memcpy(priv->ht40_1s_tx_power_index_A,
2187 priv->efuse_wifi.efuse8723bu.ht40_1s_tx_power_index_A,
2188 sizeof(priv->ht40_1s_tx_power_index_A));
2189 memcpy(priv->ht40_1s_tx_power_index_B,
2190 priv->efuse_wifi.efuse8723bu.ht40_1s_tx_power_index_B,
2191 sizeof(priv->ht40_1s_tx_power_index_B));
2192
2193 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2194 priv->efuse_wifi.efuse8723bu.vendor_name);
2195 dev_info(&priv->udev->dev, "Product: %.41s\n",
2196 priv->efuse_wifi.efuse8723bu.device_name);
2197
2198 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2199 int i;
2200 unsigned char *raw = priv->efuse_wifi.raw;
2201
2202 dev_info(&priv->udev->dev,
2203 "%s: dumping efuse (0x%02zx bytes):\n",
2204 __func__, sizeof(struct rtl8723bu_efuse));
2205 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) {
2206 dev_info(&priv->udev->dev, "%02x: "
2207 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2208 raw[i], raw[i + 1], raw[i + 2],
2209 raw[i + 3], raw[i + 4], raw[i + 5],
2210 raw[i + 6], raw[i + 7]);
2211 }
2212 }
2213
2214 return 0;
2215}
2216
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]2217#ifdef CONFIG_RTL8XXXU_UNTESTED
2218
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2219static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
2220{
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame^]2221 struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2222 int i;
2223
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame^]2224 if (efuse->rtl_id != cpu_to_le16(0x8129))
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2225 return -EINVAL;
2226
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame^]2227 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2228
2229 memcpy(priv->cck_tx_power_index_A,
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame^]2230 efuse->cck_tx_power_index_A,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2231 sizeof(priv->cck_tx_power_index_A));
2232 memcpy(priv->cck_tx_power_index_B,
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame^]2233 efuse->cck_tx_power_index_B,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2234 sizeof(priv->cck_tx_power_index_B));
2235
2236 memcpy(priv->ht40_1s_tx_power_index_A,
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame^]2237 efuse->ht40_1s_tx_power_index_A,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2238 sizeof(priv->ht40_1s_tx_power_index_A));
2239 memcpy(priv->ht40_1s_tx_power_index_B,
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame^]2240 efuse->ht40_1s_tx_power_index_B,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2241 sizeof(priv->ht40_1s_tx_power_index_B));
2242 memcpy(priv->ht40_2s_tx_power_index_diff,
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame^]2243 efuse->ht40_2s_tx_power_index_diff,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2244 sizeof(priv->ht40_2s_tx_power_index_diff));
2245
2246 memcpy(priv->ht20_tx_power_index_diff,
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame^]2247 efuse->ht20_tx_power_index_diff,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2248 sizeof(priv->ht20_tx_power_index_diff));
2249 memcpy(priv->ofdm_tx_power_index_diff,
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame^]2250 efuse->ofdm_tx_power_index_diff,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2251 sizeof(priv->ofdm_tx_power_index_diff));
2252
2253 memcpy(priv->ht40_max_power_offset,
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame^]2254 efuse->ht40_max_power_offset,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2255 sizeof(priv->ht40_max_power_offset));
2256 memcpy(priv->ht20_max_power_offset,
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame^]2257 efuse->ht20_max_power_offset,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2258 sizeof(priv->ht20_max_power_offset));
2259
2260 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame^]2261 efuse->vendor_name);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2262 dev_info(&priv->udev->dev, "Product: %.20s\n",
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame^]2263 efuse->device_name);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2264
Jakub Sitnicki49594442016-02-29 17:04:26 -0500[diff] [blame^]2265 if (efuse->rf_regulatory & 0x20) {
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2266 sprintf(priv->chip_name, "8188RU");
2267 priv->hi_pa = 1;
2268 }
2269
2270 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2271 unsigned char *raw = priv->efuse_wifi.raw;
2272
2273 dev_info(&priv->udev->dev,
2274 "%s: dumping efuse (0x%02zx bytes):\n",
2275 __func__, sizeof(struct rtl8192cu_efuse));
2276 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
2277 dev_info(&priv->udev->dev, "%02x: "
2278 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2279 raw[i], raw[i + 1], raw[i + 2],
2280 raw[i + 3], raw[i + 4], raw[i + 5],
2281 raw[i + 6], raw[i + 7]);
2282 }
2283 }
2284 return 0;
2285}
2286
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]2287#endif
2288
Jes Sorensen3307d842016-02-29 17:03:59 -0500[diff] [blame]2289static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
2290{
2291 int i;
2292
2293 if (priv->efuse_wifi.efuse8192eu.rtl_id != cpu_to_le16(0x8129))
2294 return -EINVAL;
2295
2296 ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8192eu.mac_addr);
2297
2298 memcpy(priv->cck_tx_power_index_A,
2299 priv->efuse_wifi.efuse8192eu.cck_tx_power_index_A,
2300 sizeof(priv->cck_tx_power_index_A));
2301 memcpy(priv->cck_tx_power_index_B,
2302 priv->efuse_wifi.efuse8192eu.cck_tx_power_index_B,
2303 sizeof(priv->cck_tx_power_index_B));
2304
2305 memcpy(priv->ht40_1s_tx_power_index_A,
2306 priv->efuse_wifi.efuse8192eu.ht40_1s_tx_power_index_A,
2307 sizeof(priv->ht40_1s_tx_power_index_A));
2308 memcpy(priv->ht40_1s_tx_power_index_B,
2309 priv->efuse_wifi.efuse8192eu.ht40_1s_tx_power_index_B,
2310 sizeof(priv->ht40_1s_tx_power_index_B));
2311
2312 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2313 priv->efuse_wifi.efuse8192eu.vendor_name);
2314 dev_info(&priv->udev->dev, "Product: %.11s\n",
2315 priv->efuse_wifi.efuse8192eu.device_name);
2316 dev_info(&priv->udev->dev, "Serial: %.11s\n",
2317 priv->efuse_wifi.efuse8192eu.serial);
2318
2319 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2320 unsigned char *raw = priv->efuse_wifi.raw;
2321
2322 dev_info(&priv->udev->dev,
2323 "%s: dumping efuse (0x%02zx bytes):\n",
2324 __func__, sizeof(struct rtl8192eu_efuse));
2325 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) {
2326 dev_info(&priv->udev->dev, "%02x: "
2327 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2328 raw[i], raw[i + 1], raw[i + 2],
2329 raw[i + 3], raw[i + 4], raw[i + 5],
2330 raw[i + 6], raw[i + 7]);
2331 }
2332 }
Jes Sorensen0e5d4352016-02-29 17:04:00 -0500[diff] [blame]2333 return 0;
Jes Sorensen3307d842016-02-29 17:03:59 -0500[diff] [blame]2334}
2335
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2336static int
2337rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
2338{
2339 int i;
2340 u8 val8;
2341 u32 val32;
2342
2343 /* Write Address */
2344 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
2345 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
2346 val8 &= 0xfc;
2347 val8 |= (offset >> 8) & 0x03;
2348 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
2349
2350 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
2351 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
2352
2353 /* Poll for data read */
2354 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2355 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
2356 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2357 if (val32 & BIT(31))
2358 break;
2359 }
2360
2361 if (i == RTL8XXXU_MAX_REG_POLL)
2362 return -EIO;
2363
2364 udelay(50);
2365 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2366
2367 *data = val32 & 0xff;
2368 return 0;
2369}
2370
2371static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
2372{
2373 struct device *dev = &priv->udev->dev;
2374 int i, ret = 0;
2375 u8 val8, word_mask, header, extheader;
2376 u16 val16, efuse_addr, offset;
2377 u32 val32;
2378
2379 val16 = rtl8xxxu_read16(priv, REG_9346CR);
2380 if (val16 & EEPROM_ENABLE)
2381 priv->has_eeprom = 1;
2382 if (val16 & EEPROM_BOOT)
2383 priv->boot_eeprom = 1;
2384
Jakub Sitnicki38451992016-02-03 13:39:49 -0500[diff] [blame]2385 if (priv->is_multi_func) {
2386 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
2387 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
2388 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
2389 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2390
2391 dev_dbg(dev, "Booting from %s\n",
2392 priv->boot_eeprom ? "EEPROM" : "EFUSE");
2393
2394 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
2395
2396 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2397 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
2398 if (!(val16 & SYS_ISO_PWC_EV12V)) {
2399 val16 |= SYS_ISO_PWC_EV12V;
2400 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
2401 }
2402 /* Reset: 0x0000[28], default valid */
2403 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2404 if (!(val16 & SYS_FUNC_ELDR)) {
2405 val16 |= SYS_FUNC_ELDR;
2406 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2407 }
2408
2409 /*
2410 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2411 */
2412 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
2413 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
2414 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
2415 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
2416 }
2417
2418 /* Default value is 0xff */
Jes Sorensen3307d842016-02-29 17:03:59 -0500[diff] [blame]2419 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2420
2421 efuse_addr = 0;
2422 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
Jakub Sitnickif6c47702016-02-29 17:04:23 -0500[diff] [blame]2423 u16 map_addr;
2424
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2425 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
2426 if (ret || header == 0xff)
2427 goto exit;
2428
2429 if ((header & 0x1f) == 0x0f) { /* extended header */
2430 offset = (header & 0xe0) >> 5;
2431
2432 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
2433 &extheader);
2434 if (ret)
2435 goto exit;
2436 /* All words disabled */
2437 if ((extheader & 0x0f) == 0x0f)
2438 continue;
2439
2440 offset |= ((extheader & 0xf0) >> 1);
2441 word_mask = extheader & 0x0f;
2442 } else {
2443 offset = (header >> 4) & 0x0f;
2444 word_mask = header & 0x0f;
2445 }
2446
Jakub Sitnickif6c47702016-02-29 17:04:23 -0500[diff] [blame]2447 /* Get word enable value from PG header */
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2448
Jakub Sitnickif6c47702016-02-29 17:04:23 -0500[diff] [blame]2449 /* We have 8 bits to indicate validity */
2450 map_addr = offset * 8;
2451 if (map_addr >= EFUSE_MAP_LEN) {
2452 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2453 "efuse corrupt!\n",
2454 __func__, map_addr);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2455 ret = -EINVAL;
2456 goto exit;
2457 }
Jakub Sitnickif6c47702016-02-29 17:04:23 -0500[diff] [blame]2458 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2459 /* Check word enable condition in the section */
Jakub Sitnicki32a39dd2016-02-29 17:04:24 -0500[diff] [blame]2460 if (word_mask & BIT(i)) {
Jakub Sitnickif6c47702016-02-29 17:04:23 -0500[diff] [blame]2461 map_addr += 2;
Jakub Sitnicki32a39dd2016-02-29 17:04:24 -0500[diff] [blame]2462 continue;
2463 }
2464
2465 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2466 if (ret)
2467 goto exit;
2468 priv->efuse_wifi.raw[map_addr++] = val8;
2469
2470 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2471 if (ret)
2472 goto exit;
2473 priv->efuse_wifi.raw[map_addr++] = val8;
Jakub Sitnickif6c47702016-02-29 17:04:23 -0500[diff] [blame]2474 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2475 }
2476
2477exit:
2478 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2479
2480 return ret;
2481}
2482
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2483static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
2484{
2485 u8 val8;
2486 u16 sys_func;
2487
2488 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
Jes Sorensen53b381c2016-02-03 13:39:57 -0500[diff] [blame]2489 val8 &= ~BIT(0);
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2490 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2491 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2492 sys_func &= ~SYS_FUNC_CPU_ENABLE;
2493 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2494 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
Jes Sorensen53b381c2016-02-03 13:39:57 -0500[diff] [blame]2495 val8 |= BIT(0);
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2496 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2497 sys_func |= SYS_FUNC_CPU_ENABLE;
2498 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2499}
2500
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2501static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2502{
2503 struct device *dev = &priv->udev->dev;
2504 int ret = 0, i;
2505 u32 val32;
2506
2507 /* Poll checksum report */
2508 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2509 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2510 if (val32 & MCU_FW_DL_CSUM_REPORT)
2511 break;
2512 }
2513
2514 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2515 dev_warn(dev, "Firmware checksum poll timed out\n");
2516 ret = -EAGAIN;
2517 goto exit;
2518 }
2519
2520 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2521 val32 |= MCU_FW_DL_READY;
2522 val32 &= ~MCU_WINT_INIT_READY;
2523 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2524
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2525 /*
2526 * Reset the 8051 in order for the firmware to start running,
2527 * otherwise it won't come up on the 8192eu
2528 */
2529 rtl8xxxu_reset_8051(priv);
2530
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2531 /* Wait for firmware to become ready */
2532 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2533 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2534 if (val32 & MCU_WINT_INIT_READY)
2535 break;
2536
2537 udelay(100);
2538 }
2539
2540 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2541 dev_warn(dev, "Firmware failed to start\n");
2542 ret = -EAGAIN;
2543 goto exit;
2544 }
2545
2546exit:
2547 return ret;
2548}
2549
2550static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2551{
2552 int pages, remainder, i, ret;
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2553 u8 val8;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2554 u16 val16;
2555 u32 val32;
2556 u8 *fwptr;
2557
2558 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2559 val8 |= 4;
2560 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2561
2562 /* 8051 enable */
2563 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
Jes Sorensen43154f62016-02-03 13:39:35 -0500[diff] [blame]2564 val16 |= SYS_FUNC_CPU_ENABLE;
2565 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2566
Jes Sorensen216202a2016-02-03 13:39:37 -0500[diff] [blame]2567 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2568 if (val8 & MCU_FW_RAM_SEL) {
2569 pr_info("do the RAM reset\n");
2570 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2571 rtl8xxxu_reset_8051(priv);
Jes Sorensen216202a2016-02-03 13:39:37 -0500[diff] [blame]2572 }
2573
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2574 /* MCU firmware download enable */
2575 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2576 val8 |= MCU_FW_DL_ENABLE;
2577 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2578
2579 /* 8051 reset */
2580 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2581 val32 &= ~BIT(19);
2582 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2583
2584 /* Reset firmware download checksum */
2585 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2586 val8 |= MCU_FW_DL_CSUM_REPORT;
2587 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2588
2589 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2590 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2591
2592 fwptr = priv->fw_data->data;
2593
2594 for (i = 0; i < pages; i++) {
2595 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2596 val8 |= i;
2597 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2598
2599 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2600 fwptr, RTL_FW_PAGE_SIZE);
2601 if (ret != RTL_FW_PAGE_SIZE) {
2602 ret = -EAGAIN;
2603 goto fw_abort;
2604 }
2605
2606 fwptr += RTL_FW_PAGE_SIZE;
2607 }
2608
2609 if (remainder) {
2610 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2611 val8 |= i;
2612 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2613 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2614 fwptr, remainder);
2615 if (ret != remainder) {
2616 ret = -EAGAIN;
2617 goto fw_abort;
2618 }
2619 }
2620
2621 ret = 0;
2622fw_abort:
2623 /* MCU firmware download disable */
2624 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2625 val16 &= ~MCU_FW_DL_ENABLE;
2626 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2627
2628 return ret;
2629}
2630
2631static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2632{
2633 struct device *dev = &priv->udev->dev;
2634 const struct firmware *fw;
2635 int ret = 0;
2636 u16 signature;
2637
2638 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2639 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2640 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2641 ret = -EAGAIN;
2642 goto exit;
2643 }
2644 if (!fw) {
2645 dev_warn(dev, "Firmware data not available\n");
2646 ret = -EINVAL;
2647 goto exit;
2648 }
2649
2650 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
Tobias Klauser98e27cb2016-02-03 13:39:43 -0500[diff] [blame]2651 if (!priv->fw_data) {
2652 ret = -ENOMEM;
2653 goto exit;
2654 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2655 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2656
2657 signature = le16_to_cpu(priv->fw_data->signature);
2658 switch (signature & 0xfff0) {
Jes Sorensen0e5d4352016-02-29 17:04:00 -0500[diff] [blame]2659 case 0x92e0:
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2660 case 0x92c0:
2661 case 0x88c0:
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]2662 case 0x5300:
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2663 case 0x2300:
2664 break;
2665 default:
2666 ret = -EINVAL;
2667 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2668 __func__, signature);
2669 }
2670
2671 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2672 le16_to_cpu(priv->fw_data->major_version),
2673 priv->fw_data->minor_version, signature);
2674
2675exit:
2676 release_firmware(fw);
2677 return ret;
2678}
2679
2680static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2681{
2682 char *fw_name;
2683 int ret;
2684
2685 switch (priv->chip_cut) {
2686 case 0:
2687 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2688 break;
2689 case 1:
2690 if (priv->enable_bluetooth)
2691 fw_name = "rtlwifi/rtl8723aufw_B.bin";
2692 else
2693 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2694
2695 break;
2696 default:
2697 return -EINVAL;
2698 }
2699
2700 ret = rtl8xxxu_load_firmware(priv, fw_name);
2701 return ret;
2702}
2703
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]2704static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
2705{
2706 char *fw_name;
2707 int ret;
2708
2709 if (priv->enable_bluetooth)
2710 fw_name = "rtlwifi/rtl8723bu_bt.bin";
2711 else
2712 fw_name = "rtlwifi/rtl8723bu_nic.bin";
2713
2714 ret = rtl8xxxu_load_firmware(priv, fw_name);
2715 return ret;
2716}
2717
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]2718#ifdef CONFIG_RTL8XXXU_UNTESTED
2719
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2720static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2721{
2722 char *fw_name;
2723 int ret;
2724
2725 if (!priv->vendor_umc)
2726 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2727 else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2728 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2729 else
2730 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2731
2732 ret = rtl8xxxu_load_firmware(priv, fw_name);
2733
2734 return ret;
2735}
2736
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]2737#endif
2738
Jes Sorensen3307d842016-02-29 17:03:59 -0500[diff] [blame]2739static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
2740{
2741 char *fw_name;
2742 int ret;
2743
Jes Sorensen0e5d4352016-02-29 17:04:00 -0500[diff] [blame]2744 fw_name = "rtlwifi/rtl8192eu_nic.bin";
Jes Sorensen3307d842016-02-29 17:03:59 -0500[diff] [blame]2745
2746 ret = rtl8xxxu_load_firmware(priv, fw_name);
2747
2748 return ret;
2749}
2750
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2751static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2752{
2753 u16 val16;
2754 int i = 100;
2755
2756 /* Inform 8051 to perform reset */
2757 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2758
2759 for (i = 100; i > 0; i--) {
2760 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2761
2762 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2763 dev_dbg(&priv->udev->dev,
2764 "%s: Firmware self reset success!\n", __func__);
2765 break;
2766 }
2767 udelay(50);
2768 }
2769
2770 if (!i) {
2771 /* Force firmware reset */
2772 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2773 val16 &= ~SYS_FUNC_CPU_ENABLE;
2774 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2775 }
2776}
2777
Jes Sorensenf0d9f5e2016-02-29 17:04:16 -0500[diff] [blame]2778static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
2779{
2780 u32 val32;
2781
2782 val32 = rtl8xxxu_read32(priv, 0x64);
2783 val32 &= ~(BIT(20) | BIT(24));
2784 rtl8xxxu_write32(priv, 0x64, val32);
2785
2786 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
2787 val32 &= ~BIT(4);
2788 val32 |= BIT(3);
2789 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
2790
2791 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
2792 val32 &= ~BIT(23);
2793 val32 |= BIT(24);
2794 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
2795
2796 val32 = rtl8xxxu_read32(priv, 0x0944);
2797 val32 |= (BIT(0) | BIT(1));
2798 rtl8xxxu_write32(priv, 0x0944, val32);
2799
2800 val32 = rtl8xxxu_read32(priv, 0x0930);
2801 val32 &= 0xffffff00;
2802 val32 |= 0x77;
2803 rtl8xxxu_write32(priv, 0x0930, val32);
2804
2805 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
2806 val32 |= BIT(11);
2807 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
2808}
2809
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2810static int
2811rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
2812{
2813 int i, ret;
2814 u16 reg;
2815 u8 val;
2816
2817 for (i = 0; ; i++) {
2818 reg = array[i].reg;
2819 val = array[i].val;
2820
2821 if (reg == 0xffff && val == 0xff)
2822 break;
2823
2824 ret = rtl8xxxu_write8(priv, reg, val);
2825 if (ret != 1) {
2826 dev_warn(&priv->udev->dev,
2827 "Failed to initialize MAC\n");
2828 return -EAGAIN;
2829 }
2830 }
2831
2832 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2833
2834 return 0;
2835}
2836
2837static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2838 struct rtl8xxxu_reg32val *array)
2839{
2840 int i, ret;
2841 u16 reg;
2842 u32 val;
2843
2844 for (i = 0; ; i++) {
2845 reg = array[i].reg;
2846 val = array[i].val;
2847
2848 if (reg == 0xffff && val == 0xffffffff)
2849 break;
2850
2851 ret = rtl8xxxu_write32(priv, reg, val);
2852 if (ret != sizeof(val)) {
2853 dev_warn(&priv->udev->dev,
2854 "Failed to initialize PHY\n");
2855 return -EAGAIN;
2856 }
2857 udelay(1);
2858 }
2859
2860 return 0;
2861}
2862
2863/*
2864 * Most of this is black magic retrieved from the old rtl8723au driver
2865 */
2866static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2867{
2868 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2869 u32 val32;
2870
2871 /*
2872 * Todo: The vendor driver maintains a table of PHY register
2873 * addresses, which is initialized here. Do we need this?
2874 */
2875
2876 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2877 udelay(2);
2878 val8 |= AFE_PLL_320_ENABLE;
2879 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2880 udelay(2);
2881
2882 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2883 udelay(2);
2884
2885 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
2886 val8 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2887 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
2888
2889 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
2890 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2891 val32 &= ~AFE_XTAL_RF_GATE;
2892 if (priv->has_bluetooth)
2893 val32 &= ~AFE_XTAL_BT_GATE;
2894 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2895
2896 /* 6. 0x1f[7:0] = 0x07 */
2897 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2898 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2899
2900 if (priv->hi_pa)
2901 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2902 else if (priv->tx_paths == 2)
2903 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
Jes Sorensen36c32582016-02-29 17:04:14 -0500[diff] [blame]2904 else if (priv->rtlchip == 0x8723b)
2905 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2906 else
2907 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2908
2909
2910 if (priv->rtlchip == 0x8188c && priv->hi_pa &&
2911 priv->vendor_umc && priv->chip_cut == 1)
2912 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2913
2914 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2915 /*
2916 * For 1T2R boards, patch the registers.
2917 *
2918 * It looks like 8191/2 1T2R boards use path B for TX
2919 */
2920 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2921 val32 &= ~(BIT(0) | BIT(1));
2922 val32 |= BIT(1);
2923 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2924
2925 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2926 val32 &= ~0x300033;
2927 val32 |= 0x200022;
2928 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2929
2930 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2931 val32 &= 0xff000000;
2932 val32 |= 0x45000000;
2933 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2934
2935 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2936 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2937 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2938 OFDM_RF_PATH_TX_B);
2939 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2940
2941 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2942 val32 &= ~(BIT(4) | BIT(5));
2943 val32 |= BIT(4);
2944 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2945
2946 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2947 val32 &= ~(BIT(27) | BIT(26));
2948 val32 |= BIT(27);
2949 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2950
2951 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2952 val32 &= ~(BIT(27) | BIT(26));
2953 val32 |= BIT(27);
2954 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2955
2956 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2957 val32 &= ~(BIT(27) | BIT(26));
2958 val32 |= BIT(27);
2959 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2960
2961 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2962 val32 &= ~(BIT(27) | BIT(26));
2963 val32 |= BIT(27);
2964 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2965
2966 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2967 val32 &= ~(BIT(27) | BIT(26));
2968 val32 |= BIT(27);
2969 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2970 }
2971
Jes Sorensenb9f498e2016-02-29 17:04:18 -0500[diff] [blame]2972 if (priv->rtlchip == 0x8723b)
2973 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
2974 else if (priv->hi_pa)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2975 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2976 else
2977 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2978
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]2979 if ((priv->rtlchip == 0x8723a || priv->rtlchip == 0x8723b) &&
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2980 priv->efuse_wifi.efuse8723.version >= 0x01) {
2981 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
2982
2983 val8 = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2984 val32 &= 0xff000fff;
2985 val32 |= ((val8 | (val8 << 6)) << 12);
2986
2987 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
2988 }
2989
2990 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2991 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2992 ldohci12 = 0x57;
2993 lpldo = 1;
2994 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2995
2996 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2997
2998 return 0;
2999}
3000
3001static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
3002 struct rtl8xxxu_rfregval *array,
3003 enum rtl8xxxu_rfpath path)
3004{
3005 int i, ret;
3006 u8 reg;
3007 u32 val;
3008
3009 for (i = 0; ; i++) {
3010 reg = array[i].reg;
3011 val = array[i].val;
3012
3013 if (reg == 0xff && val == 0xffffffff)
3014 break;
3015
3016 switch (reg) {
3017 case 0xfe:
3018 msleep(50);
3019 continue;
3020 case 0xfd:
3021 mdelay(5);
3022 continue;
3023 case 0xfc:
3024 mdelay(1);
3025 continue;
3026 case 0xfb:
3027 udelay(50);
3028 continue;
3029 case 0xfa:
3030 udelay(5);
3031 continue;
3032 case 0xf9:
3033 udelay(1);
3034 continue;
3035 }
3036
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3037 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
3038 if (ret) {
3039 dev_warn(&priv->udev->dev,
3040 "Failed to initialize RF\n");
3041 return -EAGAIN;
3042 }
3043 udelay(1);
3044 }
3045
3046 return 0;
3047}
3048
3049static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
3050 struct rtl8xxxu_rfregval *table,
3051 enum rtl8xxxu_rfpath path)
3052{
3053 u32 val32;
3054 u16 val16, rfsi_rfenv;
3055 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
3056
3057 switch (path) {
3058 case RF_A:
3059 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
3060 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
3061 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
3062 break;
3063 case RF_B:
3064 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
3065 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
3066 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
3067 break;
3068 default:
3069 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
3070 __func__, path + 'A');
3071 return -EINVAL;
3072 }
3073 /* For path B, use XB */
3074 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
3075 rfsi_rfenv &= FPGA0_RF_RFENV;
3076
3077 /*
3078 * These two we might be able to optimize into one
3079 */
3080 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3081 val32 |= BIT(20); /* 0x10 << 16 */
3082 rtl8xxxu_write32(priv, reg_int_oe, val32);
3083 udelay(1);
3084
3085 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3086 val32 |= BIT(4);
3087 rtl8xxxu_write32(priv, reg_int_oe, val32);
3088 udelay(1);
3089
3090 /*
3091 * These two we might be able to optimize into one
3092 */
3093 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3094 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
3095 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3096 udelay(1);
3097
3098 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3099 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
3100 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3101 udelay(1);
3102
3103 rtl8xxxu_init_rf_regs(priv, table, path);
3104
3105 /* For path B, use XB */
3106 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
3107 val16 &= ~FPGA0_RF_RFENV;
3108 val16 |= rfsi_rfenv;
3109 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
3110
3111 return 0;
3112}
3113
3114static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
3115{
3116 int ret = -EBUSY;
3117 int count = 0;
3118 u32 value;
3119
3120 value = LLT_OP_WRITE | address << 8 | data;
3121
3122 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
3123
3124 do {
3125 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
3126 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
3127 ret = 0;
3128 break;
3129 }
3130 } while (count++ < 20);
3131
3132 return ret;
3133}
3134
3135static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3136{
3137 int ret;
3138 int i;
3139
3140 for (i = 0; i < last_tx_page; i++) {
3141 ret = rtl8xxxu_llt_write(priv, i, i + 1);
3142 if (ret)
3143 goto exit;
3144 }
3145
3146 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
3147 if (ret)
3148 goto exit;
3149
3150 /* Mark remaining pages as a ring buffer */
3151 for (i = last_tx_page + 1; i < 0xff; i++) {
3152 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
3153 if (ret)
3154 goto exit;
3155 }
3156
3157 /* Let last entry point to the start entry of ring buffer */
3158 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
3159 if (ret)
3160 goto exit;
3161
3162exit:
3163 return ret;
3164}
3165
Jes Sorensen74b99be2016-02-29 17:04:04 -0500[diff] [blame]3166static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3167{
3168 u32 val32;
3169 int ret = 0;
3170 int i;
3171
3172 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
Jes Sorensen74b99be2016-02-29 17:04:04 -0500[diff] [blame]3173 val32 |= AUTO_LLT_INIT_LLT;
3174 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
3175
3176 for (i = 500; i; i--) {
3177 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3178 if (!(val32 & AUTO_LLT_INIT_LLT))
3179 break;
3180 usleep_range(2, 4);
3181 }
3182
Jes Sorensen4de24812016-02-29 17:04:07 -0500[diff] [blame]3183 if (!i) {
Jes Sorensen74b99be2016-02-29 17:04:04 -0500[diff] [blame]3184 ret = -EBUSY;
3185 dev_warn(&priv->udev->dev, "LLT table init failed\n");
3186 }
Jes Sorensen74b99be2016-02-29 17:04:04 -0500[diff] [blame]3187
3188 return ret;
3189}
3190
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3191static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
3192{
3193 u16 val16, hi, lo;
3194 u16 hiq, mgq, bkq, beq, viq, voq;
3195 int hip, mgp, bkp, bep, vip, vop;
3196 int ret = 0;
3197
3198 switch (priv->ep_tx_count) {
3199 case 1:
3200 if (priv->ep_tx_high_queue) {
3201 hi = TRXDMA_QUEUE_HIGH;
3202 } else if (priv->ep_tx_low_queue) {
3203 hi = TRXDMA_QUEUE_LOW;
3204 } else if (priv->ep_tx_normal_queue) {
3205 hi = TRXDMA_QUEUE_NORMAL;
3206 } else {
3207 hi = 0;
3208 ret = -EINVAL;
3209 }
3210
3211 hiq = hi;
3212 mgq = hi;
3213 bkq = hi;
3214 beq = hi;
3215 viq = hi;
3216 voq = hi;
3217
3218 hip = 0;
3219 mgp = 0;
3220 bkp = 0;
3221 bep = 0;
3222 vip = 0;
3223 vop = 0;
3224 break;
3225 case 2:
3226 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
3227 hi = TRXDMA_QUEUE_HIGH;
3228 lo = TRXDMA_QUEUE_LOW;
3229 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
3230 hi = TRXDMA_QUEUE_NORMAL;
3231 lo = TRXDMA_QUEUE_LOW;
3232 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
3233 hi = TRXDMA_QUEUE_HIGH;
3234 lo = TRXDMA_QUEUE_NORMAL;
3235 } else {
3236 ret = -EINVAL;
3237 hi = 0;
3238 lo = 0;
3239 }
3240
3241 hiq = hi;
3242 mgq = hi;
3243 bkq = lo;
3244 beq = lo;
3245 viq = hi;
3246 voq = hi;
3247
3248 hip = 0;
3249 mgp = 0;
3250 bkp = 1;
3251 bep = 1;
3252 vip = 0;
3253 vop = 0;
3254 break;
3255 case 3:
3256 beq = TRXDMA_QUEUE_LOW;
3257 bkq = TRXDMA_QUEUE_LOW;
3258 viq = TRXDMA_QUEUE_NORMAL;
3259 voq = TRXDMA_QUEUE_HIGH;
3260 mgq = TRXDMA_QUEUE_HIGH;
3261 hiq = TRXDMA_QUEUE_HIGH;
3262
3263 hip = hiq ^ 3;
3264 mgp = mgq ^ 3;
3265 bkp = bkq ^ 3;
3266 bep = beq ^ 3;
3267 vip = viq ^ 3;
3268 vop = viq ^ 3;
3269 break;
3270 default:
3271 ret = -EINVAL;
3272 }
3273
3274 /*
3275 * None of the vendor drivers are configuring the beacon
3276 * queue here .... why?
3277 */
3278 if (!ret) {
3279 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
3280 val16 &= 0x7;
3281 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
3282 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
3283 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
3284 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
3285 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
3286 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
3287 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
3288
3289 priv->pipe_out[TXDESC_QUEUE_VO] =
3290 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
3291 priv->pipe_out[TXDESC_QUEUE_VI] =
3292 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
3293 priv->pipe_out[TXDESC_QUEUE_BE] =
3294 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
3295 priv->pipe_out[TXDESC_QUEUE_BK] =
3296 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
3297 priv->pipe_out[TXDESC_QUEUE_BEACON] =
3298 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3299 priv->pipe_out[TXDESC_QUEUE_MGNT] =
3300 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
3301 priv->pipe_out[TXDESC_QUEUE_HIGH] =
3302 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
3303 priv->pipe_out[TXDESC_QUEUE_CMD] =
3304 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3305 }
3306
3307 return ret;
3308}
3309
3310static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
3311 bool iqk_ok, int result[][8],
3312 int candidate, bool tx_only)
3313{
3314 u32 oldval, x, tx0_a, reg;
3315 int y, tx0_c;
3316 u32 val32;
3317
3318 if (!iqk_ok)
3319 return;
3320
3321 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3322 oldval = val32 >> 22;
3323
3324 x = result[candidate][0];
3325 if ((x & 0x00000200) != 0)
3326 x = x | 0xfffffc00;
3327 tx0_a = (x * oldval) >> 8;
3328
3329 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3330 val32 &= ~0x3ff;
3331 val32 |= tx0_a;
3332 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3333
3334 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3335 val32 &= ~BIT(31);
3336 if ((x * oldval >> 7) & 0x1)
3337 val32 |= BIT(31);
3338 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3339
3340 y = result[candidate][1];
3341 if ((y & 0x00000200) != 0)
3342 y = y | 0xfffffc00;
3343 tx0_c = (y * oldval) >> 8;
3344
3345 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
3346 val32 &= ~0xf0000000;
3347 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
3348 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
3349
3350 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3351 val32 &= ~0x003f0000;
3352 val32 |= ((tx0_c & 0x3f) << 16);
3353 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3354
3355 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3356 val32 &= ~BIT(29);
3357 if ((y * oldval >> 7) & 0x1)
3358 val32 |= BIT(29);
3359 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3360
3361 if (tx_only) {
3362 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3363 return;
3364 }
3365
3366 reg = result[candidate][2];
3367
3368 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3369 val32 &= ~0x3ff;
3370 val32 |= (reg & 0x3ff);
3371 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3372
3373 reg = result[candidate][3] & 0x3F;
3374
3375 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3376 val32 &= ~0xfc00;
3377 val32 |= ((reg << 10) & 0xfc00);
3378 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3379
3380 reg = (result[candidate][3] >> 6) & 0xF;
3381
3382 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
3383 val32 &= ~0xf0000000;
3384 val32 |= (reg << 28);
3385 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
3386}
3387
3388static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
3389 bool iqk_ok, int result[][8],
3390 int candidate, bool tx_only)
3391{
3392 u32 oldval, x, tx1_a, reg;
3393 int y, tx1_c;
3394 u32 val32;
3395
3396 if (!iqk_ok)
3397 return;
3398
3399 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3400 oldval = val32 >> 22;
3401
3402 x = result[candidate][4];
3403 if ((x & 0x00000200) != 0)
3404 x = x | 0xfffffc00;
3405 tx1_a = (x * oldval) >> 8;
3406
3407 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3408 val32 &= ~0x3ff;
3409 val32 |= tx1_a;
3410 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3411
3412 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3413 val32 &= ~BIT(27);
3414 if ((x * oldval >> 7) & 0x1)
3415 val32 |= BIT(27);
3416 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3417
3418 y = result[candidate][5];
3419 if ((y & 0x00000200) != 0)
3420 y = y | 0xfffffc00;
3421 tx1_c = (y * oldval) >> 8;
3422
3423 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
3424 val32 &= ~0xf0000000;
3425 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
3426 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
3427
3428 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3429 val32 &= ~0x003f0000;
3430 val32 |= ((tx1_c & 0x3f) << 16);
3431 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3432
3433 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3434 val32 &= ~BIT(25);
3435 if ((y * oldval >> 7) & 0x1)
3436 val32 |= BIT(25);
3437 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3438
3439 if (tx_only) {
3440 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3441 return;
3442 }
3443
3444 reg = result[candidate][6];
3445
3446 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3447 val32 &= ~0x3ff;
3448 val32 |= (reg & 0x3ff);
3449 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3450
3451 reg = result[candidate][7] & 0x3f;
3452
3453 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3454 val32 &= ~0xfc00;
3455 val32 |= ((reg << 10) & 0xfc00);
3456 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3457
3458 reg = (result[candidate][7] >> 6) & 0xf;
3459
3460 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
3461 val32 &= ~0x0000f000;
3462 val32 |= (reg << 12);
3463 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
3464}
3465
3466#define MAX_TOLERANCE 5
3467
3468static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
3469 int result[][8], int c1, int c2)
3470{
3471 u32 i, j, diff, simubitmap, bound = 0;
3472 int candidate[2] = {-1, -1}; /* for path A and path B */
3473 bool retval = true;
3474
3475 if (priv->tx_paths > 1)
3476 bound = 8;
3477 else
3478 bound = 4;
3479
3480 simubitmap = 0;
3481
3482 for (i = 0; i < bound; i++) {
3483 diff = (result[c1][i] > result[c2][i]) ?
3484 (result[c1][i] - result[c2][i]) :
3485 (result[c2][i] - result[c1][i]);
3486 if (diff > MAX_TOLERANCE) {
3487 if ((i == 2 || i == 6) && !simubitmap) {
3488 if (result[c1][i] + result[c1][i + 1] == 0)
3489 candidate[(i / 4)] = c2;
3490 else if (result[c2][i] + result[c2][i + 1] == 0)
3491 candidate[(i / 4)] = c1;
3492 else
3493 simubitmap = simubitmap | (1 << i);
3494 } else {
3495 simubitmap = simubitmap | (1 << i);
3496 }
3497 }
3498 }
3499
3500 if (simubitmap == 0) {
3501 for (i = 0; i < (bound / 4); i++) {
3502 if (candidate[i] >= 0) {
3503 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3504 result[3][j] = result[candidate[i]][j];
3505 retval = false;
3506 }
3507 }
3508 return retval;
3509 } else if (!(simubitmap & 0x0f)) {
3510 /* path A OK */
3511 for (i = 0; i < 4; i++)
3512 result[3][i] = result[c1][i];
3513 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
3514 /* path B OK */
3515 for (i = 4; i < 8; i++)
3516 result[3][i] = result[c1][i];
3517 }
3518
3519 return false;
3520}
3521
3522static void
3523rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3524{
3525 int i;
3526
3527 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3528 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3529
3530 backup[i] = rtl8xxxu_read32(priv, reg[i]);
3531}
3532
3533static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3534 const u32 *reg, u32 *backup)
3535{
3536 int i;
3537
3538 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3539 rtl8xxxu_write8(priv, reg[i], backup[i]);
3540
3541 rtl8xxxu_write32(priv, reg[i], backup[i]);
3542}
3543
3544static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3545 u32 *backup, int count)
3546{
3547 int i;
3548
3549 for (i = 0; i < count; i++)
3550 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3551}
3552
3553static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3554 u32 *backup, int count)
3555{
3556 int i;
3557
3558 for (i = 0; i < count; i++)
3559 rtl8xxxu_write32(priv, regs[i], backup[i]);
3560}
3561
3562
3563static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3564 bool path_a_on)
3565{
3566 u32 path_on;
3567 int i;
3568
3569 path_on = path_a_on ? 0x04db25a4 : 0x0b1b25a4;
3570 if (priv->tx_paths == 1) {
3571 path_on = 0x0bdb25a0;
3572 rtl8xxxu_write32(priv, regs[0], 0x0b1b25a0);
3573 } else {
3574 rtl8xxxu_write32(priv, regs[0], path_on);
3575 }
3576
3577 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3578 rtl8xxxu_write32(priv, regs[i], path_on);
3579}
3580
3581static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3582 const u32 *regs, u32 *backup)
3583{
3584 int i = 0;
3585
3586 rtl8xxxu_write8(priv, regs[i], 0x3f);
3587
3588 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3589 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3590
3591 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3592}
3593
3594static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3595{
3596 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3597 int result = 0;
3598
3599 /* path-A IQK setting */
3600 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3601 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3602 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3603
3604 val32 = (priv->rf_paths > 1) ? 0x28160202 :
3605 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3606 0x28160502;
3607 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3608
3609 /* path-B IQK setting */
3610 if (priv->rf_paths > 1) {
3611 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3612 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3613 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3614 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3615 }
3616
3617 /* LO calibration setting */
3618 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3619
3620 /* One shot, path A LOK & IQK */
3621 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3622 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3623
3624 mdelay(1);
3625
3626 /* Check failed */
3627 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3628 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3629 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3630 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3631
3632 if (!(reg_eac & BIT(28)) &&
3633 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3634 ((reg_e9c & 0x03ff0000) != 0x00420000))
3635 result |= 0x01;
3636 else /* If TX not OK, ignore RX */
3637 goto out;
3638
3639 /* If TX is OK, check whether RX is OK */
3640 if (!(reg_eac & BIT(27)) &&
3641 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3642 ((reg_eac & 0x03ff0000) != 0x00360000))
3643 result |= 0x02;
3644 else
3645 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3646 __func__);
3647out:
3648 return result;
3649}
3650
3651static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3652{
3653 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3654 int result = 0;
3655
3656 /* One shot, path B LOK & IQK */
3657 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3658 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3659
3660 mdelay(1);
3661
3662 /* Check failed */
3663 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3664 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3665 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3666 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3667 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3668
3669 if (!(reg_eac & BIT(31)) &&
3670 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3671 ((reg_ebc & 0x03ff0000) != 0x00420000))
3672 result |= 0x01;
3673 else
3674 goto out;
3675
3676 if (!(reg_eac & BIT(30)) &&
3677 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3678 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3679 result |= 0x02;
3680 else
3681 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3682 __func__);
3683out:
3684 return result;
3685}
3686
3687static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3688 int result[][8], int t)
3689{
3690 struct device *dev = &priv->udev->dev;
3691 u32 i, val32;
3692 int path_a_ok, path_b_ok;
3693 int retry = 2;
3694 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3695 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3696 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3697 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3698 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3699 REG_TX_TO_TX, REG_RX_CCK,
3700 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3701 REG_RX_TO_RX, REG_STANDBY,
3702 REG_SLEEP, REG_PMPD_ANAEN
3703 };
3704 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3705 REG_TXPAUSE, REG_BEACON_CTRL,
3706 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3707 };
3708 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3709 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3710 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3711 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3712 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3713 };
3714
3715 /*
3716 * Note: IQ calibration must be performed after loading
3717 * PHY_REG.txt , and radio_a, radio_b.txt
3718 */
3719
3720 if (t == 0) {
3721 /* Save ADDA parameters, turn Path A ADDA on */
3722 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3723 RTL8XXXU_ADDA_REGS);
3724 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3725 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3726 priv->bb_backup, RTL8XXXU_BB_REGS);
3727 }
3728
3729 rtl8xxxu_path_adda_on(priv, adda_regs, true);
3730
3731 if (t == 0) {
3732 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3733 if (val32 & FPGA0_HSSI_PARM1_PI)
3734 priv->pi_enabled = 1;
3735 }
3736
3737 if (!priv->pi_enabled) {
3738 /* Switch BB to PI mode to do IQ Calibration. */
3739 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3740 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3741 }
3742
3743 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3744 val32 &= ~FPGA_RF_MODE_CCK;
3745 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3746
3747 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3748 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3749 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3750
3751 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3752 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3753 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3754
3755 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3756 val32 &= ~BIT(10);
3757 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3758 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3759 val32 &= ~BIT(10);
3760 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3761
3762 if (priv->tx_paths > 1) {
3763 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3764 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3765 }
3766
3767 /* MAC settings */
3768 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3769
3770 /* Page B init */
3771 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3772
3773 if (priv->tx_paths > 1)
3774 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3775
3776 /* IQ calibration setting */
3777 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3778 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3779 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3780
3781 for (i = 0; i < retry; i++) {
3782 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3783 if (path_a_ok == 0x03) {
3784 val32 = rtl8xxxu_read32(priv,
3785 REG_TX_POWER_BEFORE_IQK_A);
3786 result[t][0] = (val32 >> 16) & 0x3ff;
3787 val32 = rtl8xxxu_read32(priv,
3788 REG_TX_POWER_AFTER_IQK_A);
3789 result[t][1] = (val32 >> 16) & 0x3ff;
3790 val32 = rtl8xxxu_read32(priv,
3791 REG_RX_POWER_BEFORE_IQK_A_2);
3792 result[t][2] = (val32 >> 16) & 0x3ff;
3793 val32 = rtl8xxxu_read32(priv,
3794 REG_RX_POWER_AFTER_IQK_A_2);
3795 result[t][3] = (val32 >> 16) & 0x3ff;
3796 break;
3797 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3798 /* TX IQK OK */
3799 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3800 __func__);
3801
3802 val32 = rtl8xxxu_read32(priv,
3803 REG_TX_POWER_BEFORE_IQK_A);
3804 result[t][0] = (val32 >> 16) & 0x3ff;
3805 val32 = rtl8xxxu_read32(priv,
3806 REG_TX_POWER_AFTER_IQK_A);
3807 result[t][1] = (val32 >> 16) & 0x3ff;
3808 }
3809 }
3810
3811 if (!path_a_ok)
3812 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3813
3814 if (priv->tx_paths > 1) {
3815 /*
3816 * Path A into standby
3817 */
3818 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3819 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3820 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3821
3822 /* Turn Path B ADDA on */
3823 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3824
3825 for (i = 0; i < retry; i++) {
3826 path_b_ok = rtl8xxxu_iqk_path_b(priv);
3827 if (path_b_ok == 0x03) {
3828 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3829 result[t][4] = (val32 >> 16) & 0x3ff;
3830 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3831 result[t][5] = (val32 >> 16) & 0x3ff;
3832 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3833 result[t][6] = (val32 >> 16) & 0x3ff;
3834 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3835 result[t][7] = (val32 >> 16) & 0x3ff;
3836 break;
3837 } else if (i == (retry - 1) && path_b_ok == 0x01) {
3838 /* TX IQK OK */
3839 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3840 result[t][4] = (val32 >> 16) & 0x3ff;
3841 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3842 result[t][5] = (val32 >> 16) & 0x3ff;
3843 }
3844 }
3845
3846 if (!path_b_ok)
3847 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3848 }
3849
3850 /* Back to BB mode, load original value */
3851 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3852
3853 if (t) {
3854 if (!priv->pi_enabled) {
3855 /*
3856 * Switch back BB to SI mode after finishing
3857 * IQ Calibration
3858 */
3859 val32 = 0x01000000;
3860 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3861 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3862 }
3863
3864 /* Reload ADDA power saving parameters */
3865 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3866 RTL8XXXU_ADDA_REGS);
3867
3868 /* Reload MAC parameters */
3869 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3870
3871 /* Reload BB parameters */
3872 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3873 priv->bb_backup, RTL8XXXU_BB_REGS);
3874
3875 /* Restore RX initial gain */
3876 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3877
3878 if (priv->tx_paths > 1) {
3879 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3880 0x00032ed3);
3881 }
3882
3883 /* Load 0xe30 IQC default value */
3884 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3885 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3886 }
3887}
3888
3889static void rtl8723a_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3890{
3891 struct device *dev = &priv->udev->dev;
3892 int result[4][8]; /* last is final result */
3893 int i, candidate;
3894 bool path_a_ok, path_b_ok;
3895 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3896 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3897 s32 reg_tmp = 0;
3898 bool simu;
3899
3900 memset(result, 0, sizeof(result));
3901 candidate = -1;
3902
3903 path_a_ok = false;
3904 path_b_ok = false;
3905
3906 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3907
3908 for (i = 0; i < 3; i++) {
3909 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3910
3911 if (i == 1) {
3912 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3913 if (simu) {
3914 candidate = 0;
3915 break;
3916 }
3917 }
3918
3919 if (i == 2) {
3920 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3921 if (simu) {
3922 candidate = 0;
3923 break;
3924 }
3925
3926 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3927 if (simu) {
3928 candidate = 1;
3929 } else {
3930 for (i = 0; i < 8; i++)
3931 reg_tmp += result[3][i];
3932
3933 if (reg_tmp)
3934 candidate = 3;
3935 else
3936 candidate = -1;
3937 }
3938 }
3939 }
3940
3941 for (i = 0; i < 4; i++) {
3942 reg_e94 = result[i][0];
3943 reg_e9c = result[i][1];
3944 reg_ea4 = result[i][2];
3945 reg_eac = result[i][3];
3946 reg_eb4 = result[i][4];
3947 reg_ebc = result[i][5];
3948 reg_ec4 = result[i][6];
3949 reg_ecc = result[i][7];
3950 }
3951
3952 if (candidate >= 0) {
3953 reg_e94 = result[candidate][0];
3954 priv->rege94 = reg_e94;
3955 reg_e9c = result[candidate][1];
3956 priv->rege9c = reg_e9c;
3957 reg_ea4 = result[candidate][2];
3958 reg_eac = result[candidate][3];
3959 reg_eb4 = result[candidate][4];
3960 priv->regeb4 = reg_eb4;
3961 reg_ebc = result[candidate][5];
3962 priv->regebc = reg_ebc;
3963 reg_ec4 = result[candidate][6];
3964 reg_ecc = result[candidate][7];
3965 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3966 dev_dbg(dev,
3967 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
3968 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
3969 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3970 path_a_ok = true;
3971 path_b_ok = true;
3972 } else {
3973 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3974 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3975 }
3976
3977 if (reg_e94 && candidate >= 0)
3978 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3979 candidate, (reg_ea4 == 0));
3980
3981 if (priv->tx_paths > 1 && reg_eb4)
3982 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3983 candidate, (reg_ec4 == 0));
3984
3985 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
3986 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3987}
3988
3989static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3990{
3991 u32 val32;
3992 u32 rf_amode, rf_bmode = 0, lstf;
3993
3994 /* Check continuous TX and Packet TX */
3995 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3996
3997 if (lstf & OFDM_LSTF_MASK) {
3998 /* Disable all continuous TX */
3999 val32 = lstf & ~OFDM_LSTF_MASK;
4000 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
4001
4002 /* Read original RF mode Path A */
4003 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
4004
4005 /* Set RF mode to standby Path A */
4006 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
4007 (rf_amode & 0x8ffff) | 0x10000);
4008
4009 /* Path-B */
4010 if (priv->tx_paths > 1) {
4011 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
4012 RF6052_REG_AC);
4013
4014 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
4015 (rf_bmode & 0x8ffff) | 0x10000);
4016 }
4017 } else {
4018 /* Deal with Packet TX case */
4019 /* block all queues */
4020 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
4021 }
4022
4023 /* Start LC calibration */
4024 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
4025 val32 |= 0x08000;
4026 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
4027
4028 msleep(100);
4029
4030 /* Restore original parameters */
4031 if (lstf & OFDM_LSTF_MASK) {
4032 /* Path-A */
4033 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
4034 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
4035
4036 /* Path-B */
4037 if (priv->tx_paths > 1)
4038 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
4039 rf_bmode);
4040 } else /* Deal with Packet TX case */
4041 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
4042}
4043
4044static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
4045{
4046 int i;
4047 u16 reg;
4048
4049 reg = REG_MACID;
4050
4051 for (i = 0; i < ETH_ALEN; i++)
4052 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
4053
4054 return 0;
4055}
4056
4057static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
4058{
4059 int i;
4060 u16 reg;
4061
4062 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
4063
4064 reg = REG_BSSID;
4065
4066 for (i = 0; i < ETH_ALEN; i++)
4067 rtl8xxxu_write8(priv, reg + i, bssid[i]);
4068
4069 return 0;
4070}
4071
4072static void
4073rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
4074{
4075 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
4076 u8 max_agg = 0xf;
4077 int i;
4078
4079 ampdu_factor = 1 << (ampdu_factor + 2);
4080 if (ampdu_factor > max_agg)
4081 ampdu_factor = max_agg;
4082
4083 for (i = 0; i < 4; i++) {
4084 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
4085 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
4086
4087 if ((vals[i] & 0x0f) > ampdu_factor)
4088 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
4089
4090 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
4091 }
4092}
4093
4094static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
4095{
4096 u8 val8;
4097
4098 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
4099 val8 &= 0xf8;
4100 val8 |= density;
4101 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
4102}
4103
4104static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
4105{
4106 u8 val8;
4107 int count, ret;
4108
4109 /* Start of rtl8723AU_card_enable_flow */
4110 /* Act to Cardemu sequence*/
4111 /* Turn off RF */
4112 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
4113
4114 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
4115 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4116 val8 &= ~LEDCFG2_DPDT_SELECT;
4117 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4118
4119 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
4120 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4121 val8 |= BIT(1);
4122 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4123
4124 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4125 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4126 if ((val8 & BIT(1)) == 0)
4127 break;
4128 udelay(10);
4129 }
4130
4131 if (!count) {
4132 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
4133 __func__);
4134 ret = -EBUSY;
4135 goto exit;
4136 }
4137
4138 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
4139 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
4140 val8 |= SYS_ISO_ANALOG_IPS;
4141 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
4142
4143 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
4144 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
4145 val8 &= ~LDOA15_ENABLE;
4146 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
4147
4148exit:
4149 return ret;
4150}
4151
4152static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
4153{
4154 u8 val8;
4155 u8 val32;
4156 int count, ret;
4157
4158 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
4159
4160 /*
4161 * Poll - wait for RX packet to complete
4162 */
4163 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4164 val32 = rtl8xxxu_read32(priv, 0x5f8);
4165 if (!val32)
4166 break;
4167 udelay(10);
4168 }
4169
4170 if (!count) {
4171 dev_warn(&priv->udev->dev,
4172 "%s: RX poll timed out (0x05f8)\n", __func__);
4173 ret = -EBUSY;
4174 goto exit;
4175 }
4176
4177 /* Disable CCK and OFDM, clock gated */
4178 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
4179 val8 &= ~SYS_FUNC_BBRSTB;
4180 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
4181
4182 udelay(2);
4183
4184 /* Reset baseband */
4185 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
4186 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
4187 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
4188
4189 /* Reset MAC TRX */
4190 val8 = rtl8xxxu_read8(priv, REG_CR);
4191 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
4192 rtl8xxxu_write8(priv, REG_CR, val8);
4193
4194 /* Reset MAC TRX */
4195 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
4196 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
4197 rtl8xxxu_write8(priv, REG_CR + 1, val8);
4198
4199 /* Respond TX OK to scheduler */
4200 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
4201 val8 |= DUAL_TSF_TX_OK;
4202 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
4203
4204exit:
4205 return ret;
4206}
4207
Jes Sorensenc05a9db2016-02-29 17:04:03 -0500[diff] [blame]4208static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4209{
4210 u8 val8;
4211
4212 /* Clear suspend enable and power down enable*/
4213 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4214 val8 &= ~(BIT(3) | BIT(7));
4215 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4216
4217 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
4218 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
4219 val8 &= ~BIT(0);
4220 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
4221
4222 /* 0x04[12:11] = 11 enable WL suspend*/
4223 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4224 val8 &= ~(BIT(3) | BIT(4));
4225 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4226}
4227
Jes Sorensenc05a9db2016-02-29 17:04:03 -0500[diff] [blame]4228static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
4229{
4230 u8 val8;
4231
4232 /* Clear suspend enable and power down enable*/
4233 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4234 val8 &= ~(BIT(3) | BIT(4));
4235 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4236}
4237
4238static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
4239{
4240 u8 val8;
4241 u32 val32;
4242 int count, ret = 0;
4243
4244 /* disable HWPDN 0x04[15]=0*/
4245 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4246 val8 &= ~BIT(7);
4247 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4248
4249 /* disable SW LPS 0x04[10]= 0 */
4250 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4251 val8 &= ~BIT(2);
4252 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4253
4254 /* disable WL suspend*/
4255 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4256 val8 &= ~(BIT(3) | BIT(4));
4257 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4258
4259 /* wait till 0x04[17] = 1 power ready*/
4260 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4261 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4262 if (val32 & BIT(17))
4263 break;
4264
4265 udelay(10);
4266 }
4267
4268 if (!count) {
4269 ret = -EBUSY;
4270 goto exit;
4271 }
4272
4273 /* We should be able to optimize the following three entries into one */
4274
4275 /* release WLON reset 0x04[16]= 1*/
4276 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
4277 val8 |= BIT(0);
4278 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
4279
4280 /* set, then poll until 0 */
4281 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4282 val32 |= APS_FSMCO_MAC_ENABLE;
4283 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
4284
4285 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4286 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4287 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
4288 ret = 0;
4289 break;
4290 }
4291 udelay(10);
4292 }
4293
4294 if (!count) {
4295 ret = -EBUSY;
4296 goto exit;
4297 }
4298
4299exit:
4300 return ret;
4301}
4302
4303static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4304{
4305 u8 val8;
4306 u32 val32;
4307 int count, ret = 0;
4308
4309 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
4310 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
4311 val8 |= LDOA15_ENABLE;
4312 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
4313
4314 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
4315 val8 = rtl8xxxu_read8(priv, 0x0067);
4316 val8 &= ~BIT(4);
4317 rtl8xxxu_write8(priv, 0x0067, val8);
4318
4319 mdelay(1);
4320
4321 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
4322 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
4323 val8 &= ~SYS_ISO_ANALOG_IPS;
4324 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
4325
4326 /* disable SW LPS 0x04[10]= 0 */
4327 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4328 val8 &= ~BIT(2);
4329 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4330
4331 /* wait till 0x04[17] = 1 power ready*/
4332 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4333 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4334 if (val32 & BIT(17))
4335 break;
4336
4337 udelay(10);
4338 }
4339
4340 if (!count) {
4341 ret = -EBUSY;
4342 goto exit;
4343 }
4344
4345 /* We should be able to optimize the following three entries into one */
4346
4347 /* release WLON reset 0x04[16]= 1*/
4348 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
4349 val8 |= BIT(0);
4350 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
4351
4352 /* disable HWPDN 0x04[15]= 0*/
4353 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4354 val8 &= ~BIT(7);
4355 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4356
4357 /* disable WL suspend*/
4358 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4359 val8 &= ~(BIT(3) | BIT(4));
4360 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4361
4362 /* set, then poll until 0 */
4363 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4364 val32 |= APS_FSMCO_MAC_ENABLE;
4365 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
4366
4367 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4368 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4369 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
4370 ret = 0;
4371 break;
4372 }
4373 udelay(10);
4374 }
4375
4376 if (!count) {
4377 ret = -EBUSY;
4378 goto exit;
4379 }
4380
4381 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
4382 /*
4383 * Note: Vendor driver actually clears this bit, despite the
4384 * documentation claims it's being set!
4385 */
4386 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4387 val8 |= LEDCFG2_DPDT_SELECT;
4388 val8 &= ~LEDCFG2_DPDT_SELECT;
4389 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4390
4391exit:
4392 return ret;
4393}
4394
4395static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
4396{
4397 u8 val8;
4398
4399 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
4400 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
4401
4402 /* 0x04[12:11] = 01 enable WL suspend */
4403 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4404 val8 &= ~BIT(4);
4405 val8 |= BIT(3);
4406 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4407
4408 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4409 val8 |= BIT(7);
4410 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4411
4412 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
4413 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
4414 val8 |= BIT(0);
4415 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
4416
4417 return 0;
4418}
4419
4420static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
4421{
4422 u8 val8;
4423 u16 val16;
4424 u32 val32;
4425 int ret;
4426
4427 /*
4428 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
4429 */
4430 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
4431
Jes Sorensenc05a9db2016-02-29 17:04:03 -0500[diff] [blame]4432 rtl8723a_disabled_to_emu(priv);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4433
Jes Sorensenc05a9db2016-02-29 17:04:03 -0500[diff] [blame]4434 ret = rtl8723a_emu_to_active(priv);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4435 if (ret)
4436 goto exit;
4437
4438 /*
4439 * 0x0004[19] = 1, reset 8051
4440 */
4441 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
4442 val8 |= BIT(3);
4443 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
4444
4445 /*
4446 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
4447 * Set CR bit10 to enable 32k calibration.
4448 */
4449 val16 = rtl8xxxu_read16(priv, REG_CR);
4450 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
4451 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
4452 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
4453 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
4454 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
4455 rtl8xxxu_write16(priv, REG_CR, val16);
4456
4457 /* For EFuse PG */
4458 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
4459 val32 &= ~(BIT(28) | BIT(29) | BIT(30));
4460 val32 |= (0x06 << 28);
4461 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
4462exit:
4463 return ret;
4464}
4465
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]4466#ifdef CONFIG_RTL8XXXU_UNTESTED
4467
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4468static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
4469{
4470 u8 val8;
4471 u16 val16;
4472 u32 val32;
4473 int i;
4474
4475 for (i = 100; i; i--) {
4476 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
4477 if (val8 & APS_FSMCO_PFM_ALDN)
4478 break;
4479 }
4480
4481 if (!i) {
4482 pr_info("%s: Poll failed\n", __func__);
4483 return -ENODEV;
4484 }
4485
4486 /*
4487 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
4488 */
4489 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
4490 rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
4491 udelay(100);
4492
4493 val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
4494 if (!(val8 & LDOV12D_ENABLE)) {
4495 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
4496 val8 |= LDOV12D_ENABLE;
4497 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
4498
4499 udelay(100);
4500
4501 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
4502 val8 &= ~SYS_ISO_MD2PP;
4503 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
4504 }
4505
4506 /*
4507 * Auto enable WLAN
4508 */
4509 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
4510 val16 |= APS_FSMCO_MAC_ENABLE;
4511 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
4512
4513 for (i = 1000; i; i--) {
4514 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
4515 if (!(val16 & APS_FSMCO_MAC_ENABLE))
4516 break;
4517 }
4518 if (!i) {
4519 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
4520 return -EBUSY;
4521 }
4522
4523 /*
4524 * Enable radio, GPIO, LED
4525 */
4526 val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
4527 APS_FSMCO_PFM_ALDN;
4528 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
4529
4530 /*
4531 * Release RF digital isolation
4532 */
4533 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
4534 val16 &= ~SYS_ISO_DIOR;
4535 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
4536
4537 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
4538 val8 &= ~APSD_CTRL_OFF;
4539 rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
4540 for (i = 200; i; i--) {
4541 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
4542 if (!(val8 & APSD_CTRL_OFF_STATUS))
4543 break;
4544 }
4545
4546 if (!i) {
4547 pr_info("%s: APSD_CTRL poll failed\n", __func__);
4548 return -EBUSY;
4549 }
4550
4551 /*
4552 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
4553 */
4554 val16 = rtl8xxxu_read16(priv, REG_CR);
4555 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
4556 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
4557 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
4558 rtl8xxxu_write16(priv, REG_CR, val16);
4559
4560 /*
4561 * Workaround for 8188RU LNA power leakage problem.
4562 */
4563 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
4564 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
4565 val32 &= ~BIT(1);
4566 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
4567 }
4568 return 0;
4569}
4570
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]4571#endif
4572
Jes Sorensenc05a9db2016-02-29 17:04:03 -0500[diff] [blame]4573static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
4574{
4575 u16 val16;
4576 u32 val32;
4577 int ret;
4578
4579 ret = 0;
4580
4581 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
4582 if (val32 & SYS_CFG_SPS_LDO_SEL) {
4583 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
4584 } else {
4585 /*
4586 * Raise 1.2V voltage
4587 */
4588 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
4589 val32 &= 0xff0fffff;
4590 val32 |= 0x00500000;
4591 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
4592 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
4593 }
4594
4595 rtl8192e_disabled_to_emu(priv);
4596
4597 ret = rtl8192e_emu_to_active(priv);
4598 if (ret)
4599 goto exit;
4600
4601 rtl8xxxu_write16(priv, REG_CR, 0x0000);
4602
4603 /*
4604 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
4605 * Set CR bit10 to enable 32k calibration.
4606 */
4607 val16 = rtl8xxxu_read16(priv, REG_CR);
4608 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
4609 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
4610 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
4611 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
4612 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
4613 rtl8xxxu_write16(priv, REG_CR, val16);
4614
4615exit:
4616 return ret;
4617}
4618
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4619static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
4620{
4621 u8 val8;
4622 u16 val16;
4623 u32 val32;
4624
4625 /*
4626 * Workaround for 8188RU LNA power leakage problem.
4627 */
4628 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
4629 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
4630 val32 |= BIT(1);
4631 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
4632 }
4633
4634 rtl8xxxu_active_to_lps(priv);
4635
4636 /* Turn off RF */
4637 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
4638
4639 /* Reset Firmware if running in RAM */
4640 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
4641 rtl8xxxu_firmware_self_reset(priv);
4642
4643 /* Reset MCU */
4644 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
4645 val16 &= ~SYS_FUNC_CPU_ENABLE;
4646 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
4647
4648 /* Reset MCU ready status */
4649 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
4650
4651 rtl8xxxu_active_to_emu(priv);
4652 rtl8xxxu_emu_to_disabled(priv);
4653
4654 /* Reset MCU IO Wrapper */
4655 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
4656 val8 &= ~BIT(0);
4657 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
4658
4659 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
4660 val8 |= BIT(0);
4661 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
4662
4663 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
4664 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
4665}
4666
4667static void rtl8xxxu_init_bt(struct rtl8xxxu_priv *priv)
4668{
4669 if (!priv->has_bluetooth)
4670 return;
4671}
4672
4673static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
4674{
4675 struct rtl8xxxu_priv *priv = hw->priv;
4676 struct device *dev = &priv->udev->dev;
4677 struct rtl8xxxu_rfregval *rftable;
4678 bool macpower;
4679 int ret;
4680 u8 val8;
4681 u16 val16;
4682 u32 val32;
4683
4684 /* Check if MAC is already powered on */
4685 val8 = rtl8xxxu_read8(priv, REG_CR);
4686
4687 /*
4688 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
4689 * initialized. First MAC returns 0xea, second MAC returns 0x00
4690 */
4691 if (val8 == 0xea)
4692 macpower = false;
4693 else
4694 macpower = true;
4695
4696 ret = priv->fops->power_on(priv);
4697 if (ret < 0) {
4698 dev_warn(dev, "%s: Failed power on\n", __func__);
4699 goto exit;
4700 }
4701
4702 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4703 if (!macpower) {
Jes Sorensen07bb46b2016-02-29 17:04:05 -0500[diff] [blame]4704 if (priv->ep_tx_normal_queue)
4705 val8 = TX_PAGE_NUM_NORM_PQ;
4706 else
4707 val8 = 0;
4708
4709 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
4710
4711 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
4712
4713 if (priv->ep_tx_high_queue)
4714 val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
4715 if (priv->ep_tx_low_queue)
4716 val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
4717
4718 rtl8xxxu_write32(priv, REG_RQPN, val32);
4719
4720 /*
4721 * Set TX buffer boundary
4722 */
4723 val8 = TX_TOTAL_PAGE_NUM + 1;
4724 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
4725 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
4726 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
4727 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
4728 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
4729 }
4730
Jes Sorensena47b9d42016-02-29 17:04:06 -0500[diff] [blame]4731 ret = rtl8xxxu_download_firmware(priv);
4732 dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
4733 if (ret)
4734 goto exit;
4735 ret = rtl8xxxu_start_firmware(priv);
4736 dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
4737 if (ret)
4738 goto exit;
4739
Jes Sorensen07bb46b2016-02-29 17:04:05 -0500[diff] [blame]4740 ret = rtl8xxxu_init_queue_priority(priv);
4741 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
4742 if (ret)
4743 goto exit;
4744
4745 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4746 if (!macpower) {
Jes Sorensen74b99be2016-02-29 17:04:04 -0500[diff] [blame]4747 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4748 if (ret) {
4749 dev_warn(dev, "%s: LLT table init failed\n", __func__);
4750 goto exit;
4751 }
4752 }
4753
Jes Sorensen6431ea02016-02-29 17:04:21 -0500[diff] [blame]4754 /* Fix USB interface interference issue */
4755 if (priv->rtlchip == 0x8723a) {
4756 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4757 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
4758 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4759 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
4760 } else {
Jes Sorensenb63d0aa2016-02-29 17:04:08 -0500[diff] [blame]4761 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
4762 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
4763 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
Jes Sorensen6431ea02016-02-29 17:04:21 -0500[diff] [blame]4764 }
Jes Sorensen99ad16c2016-02-29 17:04:09 -0500[diff] [blame]4765
Jes Sorensen6431ea02016-02-29 17:04:21 -0500[diff] [blame]4766 /* Solve too many protocol error on USB bus */
4767 /* Can't do this for 8188/8192 UMC A cut parts */
4768 if (priv->rtlchip == 0x8723a ||
4769 ((priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c ||
4770 priv->rtlchip == 0x8188c) &&
4771 (priv->chip_cut || !priv->vendor_umc))) {
4772 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
4773 rtl8xxxu_write8(priv, 0xfe41, 0x94);
4774 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4775
4776 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4777 rtl8xxxu_write8(priv, 0xfe41, 0x19);
4778 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4779
4780 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
4781 rtl8xxxu_write8(priv, 0xfe41, 0x91);
4782 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4783
4784 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
4785 rtl8xxxu_write8(priv, 0xfe41, 0x81);
4786 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4787 }
4788
4789 if (priv->rtlchip == 0x8192e || priv->rtlchip == 0x8723b) {
Jes Sorensen99ad16c2016-02-29 17:04:09 -0500[diff] [blame]4790 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
4791 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
Jes Sorensenb63d0aa2016-02-29 17:04:08 -0500[diff] [blame]4792 }
4793
Jes Sorensenf0d9f5e2016-02-29 17:04:16 -0500[diff] [blame]4794 if (priv->fops->phy_init_antenna_selection)
4795 priv->fops->phy_init_antenna_selection(priv);
4796
Jes Sorensenb7dd8ff2016-02-29 17:04:17 -0500[diff] [blame]4797 if (priv->rtlchip == 0x8723b)
4798 ret = rtl8xxxu_init_mac(priv, rtl8723b_mac_init_table);
4799 else
4800 ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
4801
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4802 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
4803 if (ret)
4804 goto exit;
4805
4806 ret = rtl8xxxu_init_phy_bb(priv);
4807 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
4808 if (ret)
4809 goto exit;
4810
4811 switch(priv->rtlchip) {
4812 case 0x8723a:
4813 rftable = rtl8723au_radioa_1t_init_table;
4814 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4815 break;
Jes Sorensen22a31d42016-02-29 17:04:15 -0500[diff] [blame]4816 case 0x8723b:
4817 rftable = rtl8723bu_radioa_1t_init_table;
4818 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4819 break;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4820 case 0x8188c:
4821 if (priv->hi_pa)
4822 rftable = rtl8188ru_radioa_1t_highpa_table;
4823 else
4824 rftable = rtl8192cu_radioa_1t_init_table;
4825 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4826 break;
4827 case 0x8191c:
4828 rftable = rtl8192cu_radioa_1t_init_table;
4829 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4830 break;
4831 case 0x8192c:
4832 rftable = rtl8192cu_radioa_2t_init_table;
4833 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4834 if (ret)
4835 break;
4836 rftable = rtl8192cu_radiob_2t_init_table;
4837 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
4838 break;
4839 default:
4840 ret = -EINVAL;
4841 }
4842
4843 if (ret)
4844 goto exit;
4845
4846 /* Reduce 80M spur */
4847 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
4848 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4849 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
4850 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4851
4852 /* RFSW Control - clear bit 14 ?? */
4853 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
4854 /* 0x07000760 */
4855 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
4856 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
4857 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
4858 FPGA0_RF_BD_CTRL_SHIFT);
4859 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4860 /* 0x860[6:5]= 00 - why? - this sets antenna B */
4861 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
4862
4863 priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
4864 RF6052_REG_MODE_AG);
4865
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4866 /*
4867 * Set RX page boundary
4868 */
4869 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
4870 /*
4871 * Transfer page size is always 128
4872 */
4873 val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
4874 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
4875 rtl8xxxu_write8(priv, REG_PBP, val8);
4876
4877 /*
4878 * Unit in 8 bytes, not obvious what it is used for
4879 */
4880 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4881
4882 /*
4883 * Enable all interrupts - not obvious USB needs to do this
4884 */
4885 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4886 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4887
4888 rtl8xxxu_set_mac(priv);
4889 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4890
4891 /*
4892 * Configure initial WMAC settings
4893 */
4894 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4895 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4896 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4897 rtl8xxxu_write32(priv, REG_RCR, val32);
4898
4899 /*
4900 * Accept all multicast
4901 */
4902 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4903 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4904
4905 /*
4906 * Init adaptive controls
4907 */
4908 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4909 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4910 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4911 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4912
4913 /* CCK = 0x0a, OFDM = 0x10 */
4914 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4915 rtl8xxxu_set_retry(priv, 0x30, 0x30);
4916 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4917
4918 /*
4919 * Init EDCA
4920 */
4921 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4922
4923 /* Set CCK SIFS */
4924 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4925
4926 /* Set OFDM SIFS */
4927 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4928
4929 /* TXOP */
4930 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4931 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4932 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4933 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4934
4935 /* Set data auto rate fallback retry count */
4936 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4937 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4938 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4939 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4940
4941 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4942 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4943 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4944
4945 /* Set ACK timeout */
4946 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4947
4948 /*
4949 * Initialize beacon parameters
4950 */
4951 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4952 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4953 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4954 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4955 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4956 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4957
4958 /*
4959 * Enable CCK and OFDM block
4960 */
4961 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4962 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4963 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4964
4965 /*
4966 * Invalidate all CAM entries - bit 30 is undocumented
4967 */
4968 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4969
4970 /*
4971 * Start out with default power levels for channel 6, 20MHz
4972 */
4973 rtl8723a_set_tx_power(priv, 1, false);
4974
4975 /* Let the 8051 take control of antenna setting */
4976 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4977 val8 |= LEDCFG2_DPDT_SELECT;
4978 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4979
4980 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4981
4982 /* Disable BAR - not sure if this has any effect on USB */
4983 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4984
4985 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4986
Jes Sorensene5c447c2016-02-03 13:39:48 -0500[diff] [blame]4987 rtl8723a_phy_iq_calibrate(priv);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4988
4989 /*
4990 * This should enable thermal meter
4991 */
4992 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4993
4994 rtl8723a_phy_lc_calibrate(priv);
4995
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4996 /* Init BT hw config. */
4997 rtl8xxxu_init_bt(priv);
4998
4999 /*
5000 * Not sure if we really need to save these parameters, but the
5001 * vendor driver does
5002 */
5003 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
5004 if (val32 & FPGA0_HSSI_PARM2_CCK_HIGH_PWR)
5005 priv->path_a_hi_power = 1;
5006
5007 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
5008 priv->path_a_rf_paths = val32 & OFDM_RF_PATH_RX_MASK;
5009
5010 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
5011 priv->path_a_ig_value = val32 & OFDM0_X_AGC_CORE1_IGI_MASK;
5012
5013 /* Set NAV_UPPER to 30000us */
5014 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
5015 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
5016
Jes Sorensen4042e612016-02-03 13:40:01 -0500[diff] [blame]5017 if (priv->rtlchip == 0x8723a) {
5018 /*
5019 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
5020 * but we need to find root cause.
5021 * This is 8723au only.
5022 */
5023 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
5024 if ((val32 & 0xff000000) != 0x83000000) {
5025 val32 |= FPGA_RF_MODE_CCK;
5026 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
5027 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5028 }
5029
5030 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
5031 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
5032 /* ack for xmit mgmt frames. */
5033 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
5034
5035exit:
5036 return ret;
5037}
5038
5039static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
5040{
5041 struct rtl8xxxu_priv *priv = hw->priv;
5042
5043 rtl8xxxu_power_off(priv);
5044}
5045
5046static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
5047 struct ieee80211_key_conf *key, const u8 *mac)
5048{
5049 u32 cmd, val32, addr, ctrl;
5050 int j, i, tmp_debug;
5051
5052 tmp_debug = rtl8xxxu_debug;
5053 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
5054 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
5055
5056 /*
5057 * This is a bit of a hack - the lower bits of the cipher
5058 * suite selector happens to match the cipher index in the CAM
5059 */
5060 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
5061 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
5062
5063 for (j = 5; j >= 0; j--) {
5064 switch (j) {
5065 case 0:
5066 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
5067 break;
5068 case 1:
5069 val32 = mac[2] | (mac[3] << 8) |
5070 (mac[4] << 16) | (mac[5] << 24);
5071 break;
5072 default:
5073 i = (j - 2) << 2;
5074 val32 = key->key[i] | (key->key[i + 1] << 8) |
5075 key->key[i + 2] << 16 | key->key[i + 3] << 24;
5076 break;
5077 }
5078
5079 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
5080 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
5081 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
5082 udelay(100);
5083 }
5084
5085 rtl8xxxu_debug = tmp_debug;
5086}
5087
5088static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
Jes Sorensen56e43742016-02-03 13:39:50 -0500[diff] [blame]5089 struct ieee80211_vif *vif, const u8 *mac)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5090{
5091 struct rtl8xxxu_priv *priv = hw->priv;
5092 u8 val8;
5093
5094 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5095 val8 |= BEACON_DISABLE_TSF_UPDATE;
5096 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5097}
5098
5099static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
5100 struct ieee80211_vif *vif)
5101{
5102 struct rtl8xxxu_priv *priv = hw->priv;
5103 u8 val8;
5104
5105 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5106 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
5107 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5108}
5109
5110static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
5111 u32 ramask, int sgi)
5112{
5113 struct h2c_cmd h2c;
5114
5115 h2c.ramask.cmd = H2C_SET_RATE_MASK;
5116 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
5117 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
5118
5119 h2c.ramask.arg = 0x80;
5120 if (sgi)
5121 h2c.ramask.arg |= 0x20;
5122
5123 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x\n", __func__,
5124 ramask, h2c.ramask.arg);
5125 rtl8723a_h2c_cmd(priv, &h2c);
5126}
5127
5128static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
5129{
5130 u32 val32;
5131 u8 rate_idx = 0;
5132
5133 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
5134
5135 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
5136 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
5137 val32 |= rate_cfg;
5138 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
5139
5140 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
5141
5142 while (rate_cfg) {
5143 rate_cfg = (rate_cfg >> 1);
5144 rate_idx++;
5145 }
5146 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
5147}
5148
5149static void
5150rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5151 struct ieee80211_bss_conf *bss_conf, u32 changed)
5152{
5153 struct rtl8xxxu_priv *priv = hw->priv;
5154 struct device *dev = &priv->udev->dev;
5155 struct ieee80211_sta *sta;
5156 u32 val32;
5157 u8 val8;
5158
5159 if (changed & BSS_CHANGED_ASSOC) {
5160 struct h2c_cmd h2c;
5161
5162 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
5163
5164 memset(&h2c, 0, sizeof(struct h2c_cmd));
5165 rtl8xxxu_set_linktype(priv, vif->type);
5166
5167 if (bss_conf->assoc) {
5168 u32 ramask;
5169 int sgi = 0;
5170
5171 rcu_read_lock();
5172 sta = ieee80211_find_sta(vif, bss_conf->bssid);
5173 if (!sta) {
5174 dev_info(dev, "%s: ASSOC no sta found\n",
5175 __func__);
5176 rcu_read_unlock();
5177 goto error;
5178 }
5179
5180 if (sta->ht_cap.ht_supported)
5181 dev_info(dev, "%s: HT supported\n", __func__);
5182 if (sta->vht_cap.vht_supported)
5183 dev_info(dev, "%s: VHT supported\n", __func__);
5184
5185 /* TODO: Set bits 28-31 for rate adaptive id */
5186 ramask = (sta->supp_rates[0] & 0xfff) |
5187 sta->ht_cap.mcs.rx_mask[0] << 12 |
5188 sta->ht_cap.mcs.rx_mask[1] << 20;
5189 if (sta->ht_cap.cap &
5190 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
5191 sgi = 1;
5192 rcu_read_unlock();
5193
5194 rtl8xxxu_update_rate_mask(priv, ramask, sgi);
5195
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5196 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
5197
5198 rtl8723a_stop_tx_beacon(priv);
5199
5200 /* joinbss sequence */
5201 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
5202 0xc000 | bss_conf->aid);
5203
5204 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
5205 } else {
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5206 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5207 val8 |= BEACON_DISABLE_TSF_UPDATE;
5208 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5209
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5210 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
5211 }
5212 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
5213 rtl8723a_h2c_cmd(priv, &h2c);
5214 }
5215
5216 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
5217 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
5218 bss_conf->use_short_preamble);
5219 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
5220 if (bss_conf->use_short_preamble)
5221 val32 |= RSR_ACK_SHORT_PREAMBLE;
5222 else
5223 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
5224 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
5225 }
5226
5227 if (changed & BSS_CHANGED_ERP_SLOT) {
5228 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
5229 bss_conf->use_short_slot);
5230
5231 if (bss_conf->use_short_slot)
5232 val8 = 9;
5233 else
5234 val8 = 20;
5235 rtl8xxxu_write8(priv, REG_SLOT, val8);
5236 }
5237
5238 if (changed & BSS_CHANGED_BSSID) {
5239 dev_dbg(dev, "Changed BSSID!\n");
5240 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
5241 }
5242
5243 if (changed & BSS_CHANGED_BASIC_RATES) {
5244 dev_dbg(dev, "Changed BASIC_RATES!\n");
5245 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
5246 }
5247error:
5248 return;
5249}
5250
5251static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
5252{
5253 u32 rtlqueue;
5254
5255 switch (queue) {
5256 case IEEE80211_AC_VO:
5257 rtlqueue = TXDESC_QUEUE_VO;
5258 break;
5259 case IEEE80211_AC_VI:
5260 rtlqueue = TXDESC_QUEUE_VI;
5261 break;
5262 case IEEE80211_AC_BE:
5263 rtlqueue = TXDESC_QUEUE_BE;
5264 break;
5265 case IEEE80211_AC_BK:
5266 rtlqueue = TXDESC_QUEUE_BK;
5267 break;
5268 default:
5269 rtlqueue = TXDESC_QUEUE_BE;
5270 }
5271
5272 return rtlqueue;
5273}
5274
5275static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
5276{
5277 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
5278 u32 queue;
5279
5280 if (ieee80211_is_mgmt(hdr->frame_control))
5281 queue = TXDESC_QUEUE_MGNT;
5282 else
5283 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
5284
5285 return queue;
5286}
5287
5288static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc)
5289{
5290 __le16 *ptr = (__le16 *)tx_desc;
5291 u16 csum = 0;
5292 int i;
5293
5294 /*
5295 * Clear csum field before calculation, as the csum field is
5296 * in the middle of the struct.
5297 */
5298 tx_desc->csum = cpu_to_le16(0);
5299
5300 for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++)
5301 csum = csum ^ le16_to_cpu(ptr[i]);
5302
5303 tx_desc->csum |= cpu_to_le16(csum);
5304}
5305
5306static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
5307{
5308 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
5309 unsigned long flags;
5310
5311 spin_lock_irqsave(&priv->tx_urb_lock, flags);
5312 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
5313 list_del(&tx_urb->list);
5314 priv->tx_urb_free_count--;
5315 usb_free_urb(&tx_urb->urb);
5316 }
5317 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5318}
5319
5320static struct rtl8xxxu_tx_urb *
5321rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
5322{
5323 struct rtl8xxxu_tx_urb *tx_urb;
5324 unsigned long flags;
5325
5326 spin_lock_irqsave(&priv->tx_urb_lock, flags);
5327 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
5328 struct rtl8xxxu_tx_urb, list);
5329 if (tx_urb) {
5330 list_del(&tx_urb->list);
5331 priv->tx_urb_free_count--;
5332 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
5333 !priv->tx_stopped) {
5334 priv->tx_stopped = true;
5335 ieee80211_stop_queues(priv->hw);
5336 }
5337 }
5338
5339 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5340
5341 return tx_urb;
5342}
5343
5344static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
5345 struct rtl8xxxu_tx_urb *tx_urb)
5346{
5347 unsigned long flags;
5348
5349 INIT_LIST_HEAD(&tx_urb->list);
5350
5351 spin_lock_irqsave(&priv->tx_urb_lock, flags);
5352
5353 list_add(&tx_urb->list, &priv->tx_urb_free_list);
5354 priv->tx_urb_free_count++;
5355 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
5356 priv->tx_stopped) {
5357 priv->tx_stopped = false;
5358 ieee80211_wake_queues(priv->hw);
5359 }
5360
5361 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5362}
5363
5364static void rtl8xxxu_tx_complete(struct urb *urb)
5365{
5366 struct sk_buff *skb = (struct sk_buff *)urb->context;
5367 struct ieee80211_tx_info *tx_info;
5368 struct ieee80211_hw *hw;
5369 struct rtl8xxxu_tx_urb *tx_urb =
5370 container_of(urb, struct rtl8xxxu_tx_urb, urb);
5371
5372 tx_info = IEEE80211_SKB_CB(skb);
5373 hw = tx_info->rate_driver_data[0];
5374
5375 skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc));
5376
5377 ieee80211_tx_info_clear_status(tx_info);
5378 tx_info->status.rates[0].idx = -1;
5379 tx_info->status.rates[0].count = 0;
5380
5381 if (!urb->status)
5382 tx_info->flags |= IEEE80211_TX_STAT_ACK;
5383
5384 ieee80211_tx_status_irqsafe(hw, skb);
5385
5386 rtl8xxxu_free_tx_urb(hw->priv, tx_urb);
5387}
5388
5389static void rtl8xxxu_dump_action(struct device *dev,
5390 struct ieee80211_hdr *hdr)
5391{
5392 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
5393 u16 cap, timeout;
5394
5395 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
5396 return;
5397
5398 switch (mgmt->u.action.u.addba_resp.action_code) {
5399 case WLAN_ACTION_ADDBA_RESP:
5400 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
5401 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
5402 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
5403 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
5404 "status %02x\n",
5405 timeout,
5406 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
5407 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
5408 (cap >> 1) & 0x1,
5409 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
5410 break;
5411 case WLAN_ACTION_ADDBA_REQ:
5412 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
5413 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
5414 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
5415 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
5416 timeout,
5417 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
5418 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
5419 (cap >> 1) & 0x1);
5420 break;
5421 default:
5422 dev_info(dev, "action frame %02x\n",
5423 mgmt->u.action.u.addba_resp.action_code);
5424 break;
5425 }
5426}
5427
5428static void rtl8xxxu_tx(struct ieee80211_hw *hw,
5429 struct ieee80211_tx_control *control,
5430 struct sk_buff *skb)
5431{
5432 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
5433 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
5434 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
5435 struct rtl8xxxu_priv *priv = hw->priv;
5436 struct rtl8xxxu_tx_desc *tx_desc;
5437 struct rtl8xxxu_tx_urb *tx_urb;
5438 struct ieee80211_sta *sta = NULL;
5439 struct ieee80211_vif *vif = tx_info->control.vif;
5440 struct device *dev = &priv->udev->dev;
5441 u32 queue, rate;
5442 u16 pktlen = skb->len;
5443 u16 seq_number;
5444 u16 rate_flag = tx_info->control.rates[0].flags;
5445 int ret;
5446
5447 if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) {
5448 dev_warn(dev,
5449 "%s: Not enough headroom (%i) for tx descriptor\n",
5450 __func__, skb_headroom(skb));
5451 goto error;
5452 }
5453
5454 if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) {
5455 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
5456 __func__, skb->len);
5457 goto error;
5458 }
5459
5460 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
5461 if (!tx_urb) {
5462 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
5463 goto error;
5464 }
5465
5466 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
5467 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
5468 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
5469
5470 if (ieee80211_is_action(hdr->frame_control))
5471 rtl8xxxu_dump_action(dev, hdr);
5472
5473 tx_info->rate_driver_data[0] = hw;
5474
5475 if (control && control->sta)
5476 sta = control->sta;
5477
5478 tx_desc = (struct rtl8xxxu_tx_desc *)
5479 skb_push(skb, sizeof(struct rtl8xxxu_tx_desc));
5480
5481 memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc));
5482 tx_desc->pkt_size = cpu_to_le16(pktlen);
5483 tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc);
5484
5485 tx_desc->txdw0 =
5486 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
5487 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
5488 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
5489 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
5490
5491 queue = rtl8xxxu_queue_select(hw, skb);
5492 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
5493
5494 if (tx_info->control.hw_key) {
5495 switch (tx_info->control.hw_key->cipher) {
5496 case WLAN_CIPHER_SUITE_WEP40:
5497 case WLAN_CIPHER_SUITE_WEP104:
5498 case WLAN_CIPHER_SUITE_TKIP:
5499 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
5500 break;
5501 case WLAN_CIPHER_SUITE_CCMP:
5502 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
5503 break;
5504 default:
5505 break;
5506 }
5507 }
5508
5509 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
5510 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
5511
5512 if (rate_flag & IEEE80211_TX_RC_MCS)
5513 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
5514 else
5515 rate = tx_rate->hw_value;
5516 tx_desc->txdw5 = cpu_to_le32(rate);
5517
5518 if (ieee80211_is_data(hdr->frame_control))
5519 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
5520
5521 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
5522 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
5523 if (sta->ht_cap.ht_supported) {
5524 u32 ampdu, val32;
5525
5526 ampdu = (u32)sta->ht_cap.ampdu_density;
5527 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
5528 tx_desc->txdw2 |= cpu_to_le32(val32);
5529 tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE);
5530 } else
5531 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
5532 } else
5533 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
5534
5535 if (ieee80211_is_data_qos(hdr->frame_control))
5536 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
5537 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
5538 (sta && vif && vif->bss_conf.use_short_preamble))
5539 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
5540 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
5541 (ieee80211_is_data_qos(hdr->frame_control) &&
5542 sta && sta->ht_cap.cap &
5543 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
5544 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
5545 }
5546 if (ieee80211_is_mgmt(hdr->frame_control)) {
5547 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
5548 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE);
5549 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT);
5550 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE);
5551 }
5552
5553 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
5554 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
5555 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
5556 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE);
5557 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE);
5558 }
5559
5560 rtl8xxxu_calc_tx_desc_csum(tx_desc);
5561
5562 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
5563 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
5564
5565 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
5566 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
5567 if (ret) {
5568 usb_unanchor_urb(&tx_urb->urb);
5569 rtl8xxxu_free_tx_urb(priv, tx_urb);
5570 goto error;
5571 }
5572 return;
5573error:
5574 dev_kfree_skb(skb);
5575}
5576
5577static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
5578 struct ieee80211_rx_status *rx_status,
5579 struct rtl8xxxu_rx_desc *rx_desc,
5580 struct rtl8723au_phy_stats *phy_stats)
5581{
5582 if (phy_stats->sgi_en)
5583 rx_status->flag |= RX_FLAG_SHORT_GI;
5584
5585 if (rx_desc->rxmcs < DESC_RATE_6M) {
5586 /*
5587 * Handle PHY stats for CCK rates
5588 */
5589 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
5590
5591 switch (cck_agc_rpt & 0xc0) {
5592 case 0xc0:
5593 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
5594 break;
5595 case 0x80:
5596 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
5597 break;
5598 case 0x40:
5599 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
5600 break;
5601 case 0x00:
5602 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
5603 break;
5604 }
5605 } else {
5606 rx_status->signal =
5607 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
5608 }
5609}
5610
5611static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
5612{
5613 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5614 unsigned long flags;
5615
5616 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5617
5618 list_for_each_entry_safe(rx_urb, tmp,
5619 &priv->rx_urb_pending_list, list) {
5620 list_del(&rx_urb->list);
5621 priv->rx_urb_pending_count--;
5622 usb_free_urb(&rx_urb->urb);
5623 }
5624
5625 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5626}
5627
5628static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
5629 struct rtl8xxxu_rx_urb *rx_urb)
5630{
5631 struct sk_buff *skb;
5632 unsigned long flags;
5633 int pending = 0;
5634
5635 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5636
5637 if (!priv->shutdown) {
5638 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
5639 priv->rx_urb_pending_count++;
5640 pending = priv->rx_urb_pending_count;
5641 } else {
5642 skb = (struct sk_buff *)rx_urb->urb.context;
5643 dev_kfree_skb(skb);
5644 usb_free_urb(&rx_urb->urb);
5645 }
5646
5647 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5648
5649 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
5650 schedule_work(&priv->rx_urb_wq);
5651}
5652
5653static void rtl8xxxu_rx_urb_work(struct work_struct *work)
5654{
5655 struct rtl8xxxu_priv *priv;
5656 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5657 struct list_head local;
5658 struct sk_buff *skb;
5659 unsigned long flags;
5660 int ret;
5661
5662 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
5663 INIT_LIST_HEAD(&local);
5664
5665 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5666
5667 list_splice_init(&priv->rx_urb_pending_list, &local);
5668 priv->rx_urb_pending_count = 0;
5669
5670 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5671
5672 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
5673 list_del_init(&rx_urb->list);
5674 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5675 /*
5676 * If out of memory or temporary error, put it back on the
5677 * queue and try again. Otherwise the device is dead/gone
5678 * and we should drop it.
5679 */
5680 switch (ret) {
5681 case 0:
5682 break;
5683 case -ENOMEM:
5684 case -EAGAIN:
5685 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5686 break;
5687 default:
5688 pr_info("failed to requeue urb %i\n", ret);
5689 skb = (struct sk_buff *)rx_urb->urb.context;
5690 dev_kfree_skb(skb);
5691 usb_free_urb(&rx_urb->urb);
5692 }
5693 }
5694}
5695
5696static void rtl8xxxu_rx_complete(struct urb *urb)
5697{
5698 struct rtl8xxxu_rx_urb *rx_urb =
5699 container_of(urb, struct rtl8xxxu_rx_urb, urb);
5700 struct ieee80211_hw *hw = rx_urb->hw;
5701 struct rtl8xxxu_priv *priv = hw->priv;
5702 struct sk_buff *skb = (struct sk_buff *)urb->context;
5703 struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
5704 struct rtl8723au_phy_stats *phy_stats;
5705 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5706 struct device *dev = &priv->udev->dev;
5707 __le32 *_rx_desc_le = (__le32 *)skb->data;
5708 u32 *_rx_desc = (u32 *)skb->data;
Jes Sorensena9ffa612016-02-03 13:39:59 -0500[diff] [blame]5709 int drvinfo_sz, desc_shift, i;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5710
5711 for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
5712 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5713
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5714 drvinfo_sz = rx_desc->drvinfo_sz * 8;
5715 desc_shift = rx_desc->shift;
5716 skb_put(skb, urb->actual_length);
5717
5718 if (urb->status == 0) {
5719 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
5720 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5721
5722 skb_pull(skb, drvinfo_sz + desc_shift);
5723
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5724 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5725
5726 if (rx_desc->phy_stats)
5727 rtl8xxxu_rx_parse_phystats(priv, rx_status,
5728 rx_desc, phy_stats);
5729
5730 rx_status->freq = hw->conf.chandef.chan->center_freq;
5731 rx_status->band = hw->conf.chandef.chan->band;
5732
5733 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
5734 rx_status->flag |= RX_FLAG_MACTIME_START;
5735
5736 if (!rx_desc->swdec)
5737 rx_status->flag |= RX_FLAG_DECRYPTED;
5738 if (rx_desc->crc32)
5739 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5740 if (rx_desc->bw)
5741 rx_status->flag |= RX_FLAG_40MHZ;
5742
5743 if (rx_desc->rxht) {
5744 rx_status->flag |= RX_FLAG_HT;
5745 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5746 } else {
5747 rx_status->rate_idx = rx_desc->rxmcs;
5748 }
5749
5750 ieee80211_rx_irqsafe(hw, skb);
5751 skb = NULL;
5752 rx_urb->urb.context = NULL;
5753 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5754 } else {
5755 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5756 goto cleanup;
5757 }
5758 return;
5759
5760cleanup:
5761 usb_free_urb(urb);
5762 dev_kfree_skb(skb);
5763 return;
5764}
5765
5766static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
5767 struct rtl8xxxu_rx_urb *rx_urb)
5768{
5769 struct sk_buff *skb;
5770 int skb_size;
5771 int ret;
5772
5773 skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
5774 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
5775 if (!skb)
5776 return -ENOMEM;
5777
5778 memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
5779 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
5780 skb_size, rtl8xxxu_rx_complete, skb);
5781 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
5782 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
5783 if (ret)
5784 usb_unanchor_urb(&rx_urb->urb);
5785 return ret;
5786}
5787
5788static void rtl8xxxu_int_complete(struct urb *urb)
5789{
5790 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
5791 struct device *dev = &priv->udev->dev;
5792 int ret;
5793
5794 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5795 if (urb->status == 0) {
5796 usb_anchor_urb(urb, &priv->int_anchor);
5797 ret = usb_submit_urb(urb, GFP_ATOMIC);
5798 if (ret)
5799 usb_unanchor_urb(urb);
5800 } else {
5801 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
5802 }
5803}
5804
5805
5806static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
5807{
5808 struct rtl8xxxu_priv *priv = hw->priv;
5809 struct urb *urb;
5810 u32 val32;
5811 int ret;
5812
5813 urb = usb_alloc_urb(0, GFP_KERNEL);
5814 if (!urb)
5815 return -ENOMEM;
5816
5817 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
5818 priv->int_buf, USB_INTR_CONTENT_LENGTH,
5819 rtl8xxxu_int_complete, priv, 1);
5820 usb_anchor_urb(urb, &priv->int_anchor);
5821 ret = usb_submit_urb(urb, GFP_KERNEL);
5822 if (ret) {
5823 usb_unanchor_urb(urb);
5824 goto error;
5825 }
5826
5827 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
5828 val32 |= USB_HIMR_CPWM;
5829 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
5830
5831error:
5832 return ret;
5833}
5834
5835static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
5836 struct ieee80211_vif *vif)
5837{
5838 struct rtl8xxxu_priv *priv = hw->priv;
5839 int ret;
5840 u8 val8;
5841
5842 switch (vif->type) {
5843 case NL80211_IFTYPE_STATION:
5844 rtl8723a_stop_tx_beacon(priv);
5845
5846 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5847 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
5848 BEACON_DISABLE_TSF_UPDATE;
5849 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5850 ret = 0;
5851 break;
5852 default:
5853 ret = -EOPNOTSUPP;
5854 }
5855
5856 rtl8xxxu_set_linktype(priv, vif->type);
5857
5858 return ret;
5859}
5860
5861static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
5862 struct ieee80211_vif *vif)
5863{
5864 struct rtl8xxxu_priv *priv = hw->priv;
5865
5866 dev_dbg(&priv->udev->dev, "%s\n", __func__);
5867}
5868
5869static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
5870{
5871 struct rtl8xxxu_priv *priv = hw->priv;
5872 struct device *dev = &priv->udev->dev;
5873 u16 val16;
5874 int ret = 0, channel;
5875 bool ht40;
5876
5877 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
5878 dev_info(dev,
5879 "%s: channel: %i (changed %08x chandef.width %02x)\n",
5880 __func__, hw->conf.chandef.chan->hw_value,
5881 changed, hw->conf.chandef.width);
5882
5883 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
5884 val16 = ((hw->conf.long_frame_max_tx_count <<
5885 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
5886 ((hw->conf.short_frame_max_tx_count <<
5887 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
5888 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
5889 }
5890
5891 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
5892 switch (hw->conf.chandef.width) {
5893 case NL80211_CHAN_WIDTH_20_NOHT:
5894 case NL80211_CHAN_WIDTH_20:
5895 ht40 = false;
5896 break;
5897 case NL80211_CHAN_WIDTH_40:
5898 ht40 = true;
5899 break;
5900 default:
5901 ret = -ENOTSUPP;
5902 goto exit;
5903 }
5904
5905 channel = hw->conf.chandef.chan->hw_value;
5906
5907 rtl8723a_set_tx_power(priv, channel, ht40);
5908
5909 rtl8723au_config_channel(hw);
5910 }
5911
5912exit:
5913 return ret;
5914}
5915
5916static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
5917 struct ieee80211_vif *vif, u16 queue,
5918 const struct ieee80211_tx_queue_params *param)
5919{
5920 struct rtl8xxxu_priv *priv = hw->priv;
5921 struct device *dev = &priv->udev->dev;
5922 u32 val32;
5923 u8 aifs, acm_ctrl, acm_bit;
5924
5925 aifs = param->aifs;
5926
5927 val32 = aifs |
5928 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
5929 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
5930 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
5931
5932 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
5933 dev_dbg(dev,
5934 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
5935 __func__, queue, val32, param->acm, acm_ctrl);
5936
5937 switch (queue) {
5938 case IEEE80211_AC_VO:
5939 acm_bit = ACM_HW_CTRL_VO;
5940 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
5941 break;
5942 case IEEE80211_AC_VI:
5943 acm_bit = ACM_HW_CTRL_VI;
5944 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
5945 break;
5946 case IEEE80211_AC_BE:
5947 acm_bit = ACM_HW_CTRL_BE;
5948 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
5949 break;
5950 case IEEE80211_AC_BK:
5951 acm_bit = ACM_HW_CTRL_BK;
5952 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
5953 break;
5954 default:
5955 acm_bit = 0;
5956 break;
5957 }
5958
5959 if (param->acm)
5960 acm_ctrl |= acm_bit;
5961 else
5962 acm_ctrl &= ~acm_bit;
5963 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
5964
5965 return 0;
5966}
5967
5968static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
5969 unsigned int changed_flags,
5970 unsigned int *total_flags, u64 multicast)
5971{
5972 struct rtl8xxxu_priv *priv = hw->priv;
Bruno Randolf3bed4bf2016-02-03 13:39:51 -0500[diff] [blame]5973 u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5974
5975 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
5976 __func__, changed_flags, *total_flags);
5977
Bruno Randolf3bed4bf2016-02-03 13:39:51 -0500[diff] [blame]5978 /*
5979 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
5980 */
5981
5982 if (*total_flags & FIF_FCSFAIL)
5983 rcr |= RCR_ACCEPT_CRC32;
5984 else
5985 rcr &= ~RCR_ACCEPT_CRC32;
5986
5987 /*
5988 * FIF_PLCPFAIL not supported?
5989 */
5990
5991 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
5992 rcr &= ~RCR_CHECK_BSSID_BEACON;
5993 else
5994 rcr |= RCR_CHECK_BSSID_BEACON;
5995
5996 if (*total_flags & FIF_CONTROL)
5997 rcr |= RCR_ACCEPT_CTRL_FRAME;
5998 else
5999 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
6000
6001 if (*total_flags & FIF_OTHER_BSS) {
6002 rcr |= RCR_ACCEPT_AP;
6003 rcr &= ~RCR_CHECK_BSSID_MATCH;
6004 } else {
6005 rcr &= ~RCR_ACCEPT_AP;
6006 rcr |= RCR_CHECK_BSSID_MATCH;
6007 }
6008
6009 if (*total_flags & FIF_PSPOLL)
6010 rcr |= RCR_ACCEPT_PM;
6011 else
6012 rcr &= ~RCR_ACCEPT_PM;
6013
6014 /*
6015 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
6016 */
6017
6018 rtl8xxxu_write32(priv, REG_RCR, rcr);
6019
Jes Sorensen755bda12016-02-03 13:39:54 -0500[diff] [blame]6020 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
6021 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
6022 FIF_PROBE_REQ);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6023}
6024
6025static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
6026{
6027 if (rts > 2347)
6028 return -EINVAL;
6029
6030 return 0;
6031}
6032
6033static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
6034 struct ieee80211_vif *vif,
6035 struct ieee80211_sta *sta,
6036 struct ieee80211_key_conf *key)
6037{
6038 struct rtl8xxxu_priv *priv = hw->priv;
6039 struct device *dev = &priv->udev->dev;
6040 u8 mac_addr[ETH_ALEN];
6041 u8 val8;
6042 u16 val16;
6043 u32 val32;
6044 int retval = -EOPNOTSUPP;
6045
6046 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
6047 __func__, cmd, key->cipher, key->keyidx);
6048
6049 if (vif->type != NL80211_IFTYPE_STATION)
6050 return -EOPNOTSUPP;
6051
6052 if (key->keyidx > 3)
6053 return -EOPNOTSUPP;
6054
6055 switch (key->cipher) {
6056 case WLAN_CIPHER_SUITE_WEP40:
6057 case WLAN_CIPHER_SUITE_WEP104:
6058
6059 break;
6060 case WLAN_CIPHER_SUITE_CCMP:
6061 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
6062 break;
6063 case WLAN_CIPHER_SUITE_TKIP:
6064 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
6065 default:
6066 return -EOPNOTSUPP;
6067 }
6068
6069 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
6070 dev_dbg(dev, "%s: pairwise key\n", __func__);
6071 ether_addr_copy(mac_addr, sta->addr);
6072 } else {
6073 dev_dbg(dev, "%s: group key\n", __func__);
6074 eth_broadcast_addr(mac_addr);
6075 }
6076
6077 val16 = rtl8xxxu_read16(priv, REG_CR);
6078 val16 |= CR_SECURITY_ENABLE;
6079 rtl8xxxu_write16(priv, REG_CR, val16);
6080
6081 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
6082 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
6083 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
6084 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
6085
6086 switch (cmd) {
6087 case SET_KEY:
6088 key->hw_key_idx = key->keyidx;
6089 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
6090 rtl8xxxu_cam_write(priv, key, mac_addr);
6091 retval = 0;
6092 break;
6093 case DISABLE_KEY:
6094 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
6095 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
6096 key->keyidx << CAM_CMD_KEY_SHIFT;
6097 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
6098 retval = 0;
6099 break;
6100 default:
6101 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
6102 }
6103
6104 return retval;
6105}
6106
6107static int
6108rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
Sara Sharon50ea05e2015-12-30 16:06:04 +0200[diff] [blame]6109 struct ieee80211_ampdu_params *params)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6110{
6111 struct rtl8xxxu_priv *priv = hw->priv;
6112 struct device *dev = &priv->udev->dev;
6113 u8 ampdu_factor, ampdu_density;
Sara Sharon50ea05e2015-12-30 16:06:04 +0200[diff] [blame]6114 struct ieee80211_sta *sta = params->sta;
6115 enum ieee80211_ampdu_mlme_action action = params->action;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6116
6117 switch (action) {
6118 case IEEE80211_AMPDU_TX_START:
6119 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
6120 ampdu_factor = sta->ht_cap.ampdu_factor;
6121 ampdu_density = sta->ht_cap.ampdu_density;
6122 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
6123 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
6124 dev_dbg(dev,
6125 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
6126 ampdu_factor, ampdu_density);
6127 break;
6128 case IEEE80211_AMPDU_TX_STOP_FLUSH:
6129 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
6130 rtl8xxxu_set_ampdu_factor(priv, 0);
6131 rtl8xxxu_set_ampdu_min_space(priv, 0);
6132 break;
6133 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
6134 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
6135 __func__);
6136 rtl8xxxu_set_ampdu_factor(priv, 0);
6137 rtl8xxxu_set_ampdu_min_space(priv, 0);
6138 break;
6139 case IEEE80211_AMPDU_RX_START:
6140 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
6141 break;
6142 case IEEE80211_AMPDU_RX_STOP:
6143 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
6144 break;
6145 default:
6146 break;
6147 }
6148 return 0;
6149}
6150
6151static int rtl8xxxu_start(struct ieee80211_hw *hw)
6152{
6153 struct rtl8xxxu_priv *priv = hw->priv;
6154 struct rtl8xxxu_rx_urb *rx_urb;
6155 struct rtl8xxxu_tx_urb *tx_urb;
6156 unsigned long flags;
6157 int ret, i;
6158
6159 ret = 0;
6160
6161 init_usb_anchor(&priv->rx_anchor);
6162 init_usb_anchor(&priv->tx_anchor);
6163 init_usb_anchor(&priv->int_anchor);
6164
6165 rtl8723a_enable_rf(priv);
Jes Sorensen0e28b972016-02-29 17:04:13 -0500[diff] [blame]6166 if (priv->usb_interrupts) {
6167 ret = rtl8xxxu_submit_int_urb(hw);
6168 if (ret)
6169 goto exit;
6170 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6171
6172 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
6173 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
6174 if (!tx_urb) {
6175 if (!i)
6176 ret = -ENOMEM;
6177
6178 goto error_out;
6179 }
6180 usb_init_urb(&tx_urb->urb);
6181 INIT_LIST_HEAD(&tx_urb->list);
6182 tx_urb->hw = hw;
6183 list_add(&tx_urb->list, &priv->tx_urb_free_list);
6184 priv->tx_urb_free_count++;
6185 }
6186
6187 priv->tx_stopped = false;
6188
6189 spin_lock_irqsave(&priv->rx_urb_lock, flags);
6190 priv->shutdown = false;
6191 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
6192
6193 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
6194 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
6195 if (!rx_urb) {
6196 if (!i)
6197 ret = -ENOMEM;
6198
6199 goto error_out;
6200 }
6201 usb_init_urb(&rx_urb->urb);
6202 INIT_LIST_HEAD(&rx_urb->list);
6203 rx_urb->hw = hw;
6204
6205 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
6206 }
6207exit:
6208 /*
Bruno Randolfc85ea112016-02-03 13:39:55 -0500[diff] [blame]6209 * Accept all data and mgmt frames
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6210 */
Bruno Randolfc85ea112016-02-03 13:39:55 -0500[diff] [blame]6211 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6212 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
6213
6214 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
6215
6216 return ret;
6217
6218error_out:
6219 rtl8xxxu_free_tx_resources(priv);
6220 /*
6221 * Disable all data and mgmt frames
6222 */
6223 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
6224 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
6225
6226 return ret;
6227}
6228
6229static void rtl8xxxu_stop(struct ieee80211_hw *hw)
6230{
6231 struct rtl8xxxu_priv *priv = hw->priv;
6232 unsigned long flags;
6233
6234 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
6235
6236 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
6237 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
6238
6239 spin_lock_irqsave(&priv->rx_urb_lock, flags);
6240 priv->shutdown = true;
6241 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
6242
6243 usb_kill_anchored_urbs(&priv->rx_anchor);
6244 usb_kill_anchored_urbs(&priv->tx_anchor);
Jes Sorensen0e28b972016-02-29 17:04:13 -0500[diff] [blame]6245 if (priv->usb_interrupts)
6246 usb_kill_anchored_urbs(&priv->int_anchor);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6247
6248 rtl8723a_disable_rf(priv);
6249
6250 /*
6251 * Disable interrupts
6252 */
Jes Sorensen0e28b972016-02-29 17:04:13 -0500[diff] [blame]6253 if (priv->usb_interrupts)
6254 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6255
6256 rtl8xxxu_free_rx_resources(priv);
6257 rtl8xxxu_free_tx_resources(priv);
6258}
6259
6260static const struct ieee80211_ops rtl8xxxu_ops = {
6261 .tx = rtl8xxxu_tx,
6262 .add_interface = rtl8xxxu_add_interface,
6263 .remove_interface = rtl8xxxu_remove_interface,
6264 .config = rtl8xxxu_config,
6265 .conf_tx = rtl8xxxu_conf_tx,
6266 .bss_info_changed = rtl8xxxu_bss_info_changed,
6267 .configure_filter = rtl8xxxu_configure_filter,
6268 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
6269 .start = rtl8xxxu_start,
6270 .stop = rtl8xxxu_stop,
6271 .sw_scan_start = rtl8xxxu_sw_scan_start,
6272 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
6273 .set_key = rtl8xxxu_set_key,
6274 .ampdu_action = rtl8xxxu_ampdu_action,
6275};
6276
6277static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
6278 struct usb_interface *interface)
6279{
6280 struct usb_interface_descriptor *interface_desc;
6281 struct usb_host_interface *host_interface;
6282 struct usb_endpoint_descriptor *endpoint;
6283 struct device *dev = &priv->udev->dev;
6284 int i, j = 0, endpoints;
6285 u8 dir, xtype, num;
6286 int ret = 0;
6287
6288 host_interface = &interface->altsetting[0];
6289 interface_desc = &host_interface->desc;
6290 endpoints = interface_desc->bNumEndpoints;
6291
6292 for (i = 0; i < endpoints; i++) {
6293 endpoint = &host_interface->endpoint[i].desc;
6294
6295 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
6296 num = usb_endpoint_num(endpoint);
6297 xtype = usb_endpoint_type(endpoint);
6298 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6299 dev_dbg(dev,
6300 "%s: endpoint: dir %02x, # %02x, type %02x\n",
6301 __func__, dir, num, xtype);
6302 if (usb_endpoint_dir_in(endpoint) &&
6303 usb_endpoint_xfer_bulk(endpoint)) {
6304 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6305 dev_dbg(dev, "%s: in endpoint num %i\n",
6306 __func__, num);
6307
6308 if (priv->pipe_in) {
6309 dev_warn(dev,
6310 "%s: Too many IN pipes\n", __func__);
6311 ret = -EINVAL;
6312 goto exit;
6313 }
6314
6315 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
6316 }
6317
6318 if (usb_endpoint_dir_in(endpoint) &&
6319 usb_endpoint_xfer_int(endpoint)) {
6320 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6321 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
6322 __func__, num);
6323
6324 if (priv->pipe_interrupt) {
6325 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
6326 __func__);
6327 ret = -EINVAL;
6328 goto exit;
6329 }
6330
6331 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
6332 }
6333
6334 if (usb_endpoint_dir_out(endpoint) &&
6335 usb_endpoint_xfer_bulk(endpoint)) {
6336 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6337 dev_dbg(dev, "%s: out endpoint num %i\n",
6338 __func__, num);
6339 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
6340 dev_warn(dev,
6341 "%s: Too many OUT pipes\n", __func__);
6342 ret = -EINVAL;
6343 goto exit;
6344 }
6345 priv->out_ep[j++] = num;
6346 }
6347 }
6348exit:
6349 priv->nr_out_eps = j;
6350 return ret;
6351}
6352
6353static int rtl8xxxu_probe(struct usb_interface *interface,
6354 const struct usb_device_id *id)
6355{
6356 struct rtl8xxxu_priv *priv;
6357 struct ieee80211_hw *hw;
6358 struct usb_device *udev;
6359 struct ieee80211_supported_band *sband;
6360 int ret = 0;
6361 int untested = 1;
6362
6363 udev = usb_get_dev(interface_to_usbdev(interface));
6364
6365 switch (id->idVendor) {
6366 case USB_VENDOR_ID_REALTEK:
6367 switch(id->idProduct) {
6368 case 0x1724:
6369 case 0x8176:
6370 case 0x8178:
6371 case 0x817f:
6372 untested = 0;
6373 break;
6374 }
6375 break;
6376 case 0x7392:
6377 if (id->idProduct == 0x7811)
6378 untested = 0;
6379 break;
6380 default:
6381 break;
6382 }
6383
6384 if (untested) {
6385 rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
6386 dev_info(&udev->dev,
6387 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
6388 id->idVendor, id->idProduct);
6389 dev_info(&udev->dev,
6390 "Please report results to Jes.Sorensen@gmail.com\n");
6391 }
6392
6393 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
6394 if (!hw) {
6395 ret = -ENOMEM;
6396 goto exit;
6397 }
6398
6399 priv = hw->priv;
6400 priv->hw = hw;
6401 priv->udev = udev;
6402 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
6403 mutex_init(&priv->usb_buf_mutex);
6404 mutex_init(&priv->h2c_mutex);
6405 INIT_LIST_HEAD(&priv->tx_urb_free_list);
6406 spin_lock_init(&priv->tx_urb_lock);
6407 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
6408 spin_lock_init(&priv->rx_urb_lock);
6409 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
6410
6411 usb_set_intfdata(interface, hw);
6412
6413 ret = rtl8xxxu_parse_usb(priv, interface);
6414 if (ret)
6415 goto exit;
6416
6417 ret = rtl8xxxu_identify_chip(priv);
6418 if (ret) {
6419 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
6420 goto exit;
6421 }
6422
6423 ret = rtl8xxxu_read_efuse(priv);
6424 if (ret) {
6425 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
6426 goto exit;
6427 }
6428
6429 ret = priv->fops->parse_efuse(priv);
6430 if (ret) {
6431 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
6432 goto exit;
6433 }
6434
6435 rtl8xxxu_print_chipinfo(priv);
6436
6437 ret = priv->fops->load_firmware(priv);
6438 if (ret) {
6439 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
6440 goto exit;
6441 }
6442
6443 ret = rtl8xxxu_init_device(hw);
6444
6445 hw->wiphy->max_scan_ssids = 1;
6446 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
6447 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
6448 hw->queues = 4;
6449
6450 sband = &rtl8xxxu_supported_band;
6451 sband->ht_cap.ht_supported = true;
6452 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
6453 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
6454 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
6455 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
6456 sband->ht_cap.mcs.rx_mask[0] = 0xff;
6457 sband->ht_cap.mcs.rx_mask[4] = 0x01;
6458 if (priv->rf_paths > 1) {
6459 sband->ht_cap.mcs.rx_mask[1] = 0xff;
6460 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
6461 }
6462 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
6463 /*
6464 * Some APs will negotiate HT20_40 in a noisy environment leading
6465 * to miserable performance. Rather than defaulting to this, only
6466 * enable it if explicitly requested at module load time.
6467 */
6468 if (rtl8xxxu_ht40_2g) {
6469 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
6470 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
6471 }
6472 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
6473
6474 hw->wiphy->rts_threshold = 2347;
6475
6476 SET_IEEE80211_DEV(priv->hw, &interface->dev);
6477 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
6478
6479 hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc);
6480 ieee80211_hw_set(hw, SIGNAL_DBM);
6481 /*
6482 * The firmware handles rate control
6483 */
6484 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
6485 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
6486
6487 ret = ieee80211_register_hw(priv->hw);
6488 if (ret) {
6489 dev_err(&udev->dev, "%s: Failed to register: %i\n",
6490 __func__, ret);
6491 goto exit;
6492 }
6493
6494exit:
6495 if (ret < 0)
6496 usb_put_dev(udev);
6497 return ret;
6498}
6499
6500static void rtl8xxxu_disconnect(struct usb_interface *interface)
6501{
6502 struct rtl8xxxu_priv *priv;
6503 struct ieee80211_hw *hw;
6504
6505 hw = usb_get_intfdata(interface);
6506 priv = hw->priv;
6507
6508 rtl8xxxu_disable_device(hw);
6509 usb_set_intfdata(interface, NULL);
6510
6511 dev_info(&priv->udev->dev, "disconnecting\n");
6512
6513 ieee80211_unregister_hw(hw);
6514
6515 kfree(priv->fw_data);
6516 mutex_destroy(&priv->usb_buf_mutex);
6517 mutex_destroy(&priv->h2c_mutex);
6518
6519 usb_put_dev(priv->udev);
6520 ieee80211_free_hw(hw);
6521}
6522
6523static struct rtl8xxxu_fileops rtl8723au_fops = {
6524 .parse_efuse = rtl8723au_parse_efuse,
6525 .load_firmware = rtl8723au_load_firmware,
6526 .power_on = rtl8723au_power_on,
Jes Sorensen74b99be2016-02-29 17:04:04 -0500[diff] [blame]6527 .llt_init = rtl8xxxu_init_llt_table,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6528 .writeN_block_size = 1024,
Jes Sorensened35d092016-02-29 17:04:19 -0500[diff] [blame]6529 .mbox_ext_reg = REG_HMBOX_EXT_0,
6530 .mbox_ext_width = 2,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6531};
6532
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]6533static struct rtl8xxxu_fileops rtl8723bu_fops = {
Jes Sorensen3c836d62016-02-29 17:04:11 -0500[diff] [blame]6534 .parse_efuse = rtl8723bu_parse_efuse,
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]6535 .load_firmware = rtl8723bu_load_firmware,
6536 .power_on = rtl8723au_power_on,
6537 .llt_init = rtl8xxxu_auto_llt_table,
Jes Sorensenf0d9f5e2016-02-29 17:04:16 -0500[diff] [blame]6538 .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
Jes Sorensenadfc0122016-02-29 17:04:12 -0500[diff] [blame]6539 .writeN_block_size = 1024,
Jes Sorensened35d092016-02-29 17:04:19 -0500[diff] [blame]6540 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
6541 .mbox_ext_width = 4,
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]6542};
6543
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]6544#ifdef CONFIG_RTL8XXXU_UNTESTED
6545
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6546static struct rtl8xxxu_fileops rtl8192cu_fops = {
6547 .parse_efuse = rtl8192cu_parse_efuse,
6548 .load_firmware = rtl8192cu_load_firmware,
6549 .power_on = rtl8192cu_power_on,
Jes Sorensen74b99be2016-02-29 17:04:04 -0500[diff] [blame]6550 .llt_init = rtl8xxxu_init_llt_table,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6551 .writeN_block_size = 128,
Jes Sorensened35d092016-02-29 17:04:19 -0500[diff] [blame]6552 .mbox_ext_reg = REG_HMBOX_EXT_0,
6553 .mbox_ext_width = 2,
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6554};
6555
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]6556#endif
6557
Jes Sorensen3307d842016-02-29 17:03:59 -0500[diff] [blame]6558static struct rtl8xxxu_fileops rtl8192eu_fops = {
6559 .parse_efuse = rtl8192eu_parse_efuse,
6560 .load_firmware = rtl8192eu_load_firmware,
Jes Sorensenc05a9db2016-02-29 17:04:03 -0500[diff] [blame]6561 .power_on = rtl8192eu_power_on,
Jes Sorensen74b99be2016-02-29 17:04:04 -0500[diff] [blame]6562 .llt_init = rtl8xxxu_auto_llt_table,
Jes Sorensenc05a9db2016-02-29 17:04:03 -0500[diff] [blame]6563 .writeN_block_size = 128,
Jes Sorensened35d092016-02-29 17:04:19 -0500[diff] [blame]6564 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
6565 .mbox_ext_width = 4,
Jes Sorensen3307d842016-02-29 17:03:59 -0500[diff] [blame]6566};
6567
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6568static struct usb_device_id dev_table[] = {
6569{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
6570 .driver_info = (unsigned long)&rtl8723au_fops},
6571{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
6572 .driver_info = (unsigned long)&rtl8723au_fops},
6573{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
6574 .driver_info = (unsigned long)&rtl8723au_fops},
Jes Sorensen3307d842016-02-29 17:03:59 -0500[diff] [blame]6575{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
6576 .driver_info = (unsigned long)&rtl8192eu_fops},
Jes Sorensen35a741f2016-02-29 17:04:10 -0500[diff] [blame]6577{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
6578 .driver_info = (unsigned long)&rtl8723bu_fops},
Kalle Valo033695b2015-10-23 20:27:58 +0300[diff] [blame]6579#ifdef CONFIG_RTL8XXXU_UNTESTED
6580/* Still supported by rtlwifi */
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6581{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
6582 .driver_info = (unsigned long)&rtl8192cu_fops},
6583{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
6584 .driver_info = (unsigned long)&rtl8192cu_fops},
6585{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
6586 .driver_info = (unsigned long)&rtl8192cu_fops},
6587/* Tested by Larry Finger */
6588{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
6589 .driver_info = (unsigned long)&rtl8192cu_fops},
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6590/* Currently untested 8188 series devices */
6591{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
6592 .driver_info = (unsigned long)&rtl8192cu_fops},
6593{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
6594 .driver_info = (unsigned long)&rtl8192cu_fops},
6595{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
6596 .driver_info = (unsigned long)&rtl8192cu_fops},
6597{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
6598 .driver_info = (unsigned long)&rtl8192cu_fops},
6599{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
6600 .driver_info = (unsigned long)&rtl8192cu_fops},
6601{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
6602 .driver_info = (unsigned long)&rtl8192cu_fops},
6603{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
6604 .driver_info = (unsigned long)&rtl8192cu_fops},
6605{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
6606 .driver_info = (unsigned long)&rtl8192cu_fops},
6607{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
6608 .driver_info = (unsigned long)&rtl8192cu_fops},
6609{USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
6610 .driver_info = (unsigned long)&rtl8192cu_fops},
6611{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
6612 .driver_info = (unsigned long)&rtl8192cu_fops},
6613{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
6614 .driver_info = (unsigned long)&rtl8192cu_fops},
6615{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
6616 .driver_info = (unsigned long)&rtl8192cu_fops},
6617{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
6618 .driver_info = (unsigned long)&rtl8192cu_fops},
6619{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
6620 .driver_info = (unsigned long)&rtl8192cu_fops},
6621{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
6622 .driver_info = (unsigned long)&rtl8192cu_fops},
6623{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
6624 .driver_info = (unsigned long)&rtl8192cu_fops},
6625{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
6626 .driver_info = (unsigned long)&rtl8192cu_fops},
6627{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
6628 .driver_info = (unsigned long)&rtl8192cu_fops},
6629{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
6630 .driver_info = (unsigned long)&rtl8192cu_fops},
6631{USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
6632 .driver_info = (unsigned long)&rtl8192cu_fops},
6633{USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
6634 .driver_info = (unsigned long)&rtl8192cu_fops},
6635{USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
6636 .driver_info = (unsigned long)&rtl8192cu_fops},
6637{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
6638 .driver_info = (unsigned long)&rtl8192cu_fops},
6639{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
6640 .driver_info = (unsigned long)&rtl8192cu_fops},
6641{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
6642 .driver_info = (unsigned long)&rtl8192cu_fops},
6643{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
6644 .driver_info = (unsigned long)&rtl8192cu_fops},
6645{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
6646 .driver_info = (unsigned long)&rtl8192cu_fops},
6647{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
6648 .driver_info = (unsigned long)&rtl8192cu_fops},
6649{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
6650 .driver_info = (unsigned long)&rtl8192cu_fops},
6651{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
6652 .driver_info = (unsigned long)&rtl8192cu_fops},
6653{USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
6654 .driver_info = (unsigned long)&rtl8192cu_fops},
6655{USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
6656 .driver_info = (unsigned long)&rtl8192cu_fops},
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6657{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
6658 .driver_info = (unsigned long)&rtl8192cu_fops},
6659{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
6660 .driver_info = (unsigned long)&rtl8192cu_fops},
6661{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
6662 .driver_info = (unsigned long)&rtl8192cu_fops},
6663{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
6664 .driver_info = (unsigned long)&rtl8192cu_fops},
6665{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
6666 .driver_info = (unsigned long)&rtl8192cu_fops},
6667{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
6668 .driver_info = (unsigned long)&rtl8192cu_fops},
6669{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
6670 .driver_info = (unsigned long)&rtl8192cu_fops},
6671/* Currently untested 8192 series devices */
6672{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
6673 .driver_info = (unsigned long)&rtl8192cu_fops},
6674{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
6675 .driver_info = (unsigned long)&rtl8192cu_fops},
6676{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
6677 .driver_info = (unsigned long)&rtl8192cu_fops},
6678{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
6679 .driver_info = (unsigned long)&rtl8192cu_fops},
6680{USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
6681 .driver_info = (unsigned long)&rtl8192cu_fops},
6682{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
6683 .driver_info = (unsigned long)&rtl8192cu_fops},
6684{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
6685 .driver_info = (unsigned long)&rtl8192cu_fops},
6686{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
6687 .driver_info = (unsigned long)&rtl8192cu_fops},
6688{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
6689 .driver_info = (unsigned long)&rtl8192cu_fops},
6690{USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
6691 .driver_info = (unsigned long)&rtl8192cu_fops},
6692{USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
6693 .driver_info = (unsigned long)&rtl8192cu_fops},
6694{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
6695 .driver_info = (unsigned long)&rtl8192cu_fops},
6696{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
6697 .driver_info = (unsigned long)&rtl8192cu_fops},
6698{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
6699 .driver_info = (unsigned long)&rtl8192cu_fops},
6700{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
6701 .driver_info = (unsigned long)&rtl8192cu_fops},
6702{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
6703 .driver_info = (unsigned long)&rtl8192cu_fops},
6704{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
6705 .driver_info = (unsigned long)&rtl8192cu_fops},
6706{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
6707 .driver_info = (unsigned long)&rtl8192cu_fops},
6708{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
6709 .driver_info = (unsigned long)&rtl8192cu_fops},
6710{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
6711 .driver_info = (unsigned long)&rtl8192cu_fops},
6712{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
6713 .driver_info = (unsigned long)&rtl8192cu_fops},
6714{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
6715 .driver_info = (unsigned long)&rtl8192cu_fops},
6716{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
6717 .driver_info = (unsigned long)&rtl8192cu_fops},
6718{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
6719 .driver_info = (unsigned long)&rtl8192cu_fops},
6720{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
6721 .driver_info = (unsigned long)&rtl8192cu_fops},
6722#endif
6723{ }
6724};
6725
6726static struct usb_driver rtl8xxxu_driver = {
6727 .name = DRIVER_NAME,
6728 .probe = rtl8xxxu_probe,
6729 .disconnect = rtl8xxxu_disconnect,
6730 .id_table = dev_table,
6731 .disable_hub_initiated_lpm = 1,
6732};
6733
6734static int __init rtl8xxxu_module_init(void)
6735{
6736 int res;
6737
6738 res = usb_register(&rtl8xxxu_driver);
6739 if (res < 0)
6740 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
6741
6742 return res;
6743}
6744
6745static void __exit rtl8xxxu_module_exit(void)
6746{
6747 usb_deregister(&rtl8xxxu_driver);
6748}
6749
6750
6751MODULE_DEVICE_TABLE(usb, dev_table);
6752
6753module_init(rtl8xxxu_module_init);
6754module_exit(rtl8xxxu_module_exit);