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Paul Walmsley543d9372008-03-18 10:22:06 +02001/*
2 * linux/arch/arm/mach-omap2/clock.h
3 *
Paul Walmsleyd8a94452009-12-08 16:21:29 -07004 * Copyright (C) 2005-2009 Texas Instruments, Inc.
Paul Walmsley530e5442011-02-25 15:39:28 -07005 * Copyright (C) 2004-2011 Nokia Corporation
Tony Lindgrena16e9702008-03-18 11:56:39 +02006 *
7 * Contacts:
Paul Walmsley543d9372008-03-18 10:22:06 +02008 * Richard Woodruff <r-woodruff2@ti.com>
Paul Walmsley543d9372008-03-18 10:22:06 +02009 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
17#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
18
Paul Walmsley12706c52011-07-10 05:57:06 -060019#include <linux/kernel.h>
Paul Walmsleya135eaa2012-09-27 10:33:34 -060020#include <linux/list.h>
Paul Walmsley12706c52011-07-10 05:57:06 -060021
Paul Walmsleye10dd622012-09-27 10:33:35 -060022#include <linux/clkdev.h>
Mike Turquettef9ae32a2012-11-07 13:14:47 -080023#include <linux/clk-provider.h>
Tero Kristof38b0dd2013-06-12 16:04:34 +030024#include <linux/clk/ti.h>
Paul Walmsleye10dd622012-09-27 10:33:35 -060025
26struct omap_clk {
27 u16 cpu;
28 struct clk_lookup lk;
29};
30
J Keerthy78e52e02013-03-18 09:57:39 -060031#define CLK(dev, con, ck) \
Paul Walmsleye10dd622012-09-27 10:33:35 -060032 { \
Paul Walmsleye10dd622012-09-27 10:33:35 -060033 .lk = { \
34 .dev_id = dev, \
35 .con_id = con, \
36 .clk = ck, \
37 }, \
38 }
39
Rajendra Nayakb5a23662012-11-10 16:58:40 -070040struct clockdomain;
Rajendra Nayakb5a23662012-11-10 16:58:40 -070041
Paul Walmsley8c725dc2012-09-16 10:45:54 -060042#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
Tomeu Vizoso035a61c2015-01-23 12:03:30 +010043 static struct clk_core _name##_core = { \
Paul Walmsley8c725dc2012-09-16 10:45:54 -060044 .name = #_name, \
45 .hw = &_name##_hw.hw, \
46 .parent_names = _parent_array_name, \
47 .num_parents = ARRAY_SIZE(_parent_array_name), \
48 .ops = &_clkops_name, \
Tomeu Vizoso035a61c2015-01-23 12:03:30 +010049 }; \
50 static struct clk _name = { \
51 .core = &_name##_core, \
Paul Walmsley8c725dc2012-09-16 10:45:54 -060052 };
53
Afzal Mohammed601155b2013-01-23 17:12:05 +053054#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \
55 _clkops_name, _flags) \
Tomeu Vizoso035a61c2015-01-23 12:03:30 +010056 static struct clk_core _name##_core = { \
Afzal Mohammed601155b2013-01-23 17:12:05 +053057 .name = #_name, \
58 .hw = &_name##_hw.hw, \
59 .parent_names = _parent_array_name, \
60 .num_parents = ARRAY_SIZE(_parent_array_name), \
61 .ops = &_clkops_name, \
62 .flags = _flags, \
Tomeu Vizoso035a61c2015-01-23 12:03:30 +010063 }; \
64 static struct clk _name = { \
65 .core = &_name##_core, \
Afzal Mohammed601155b2013-01-23 17:12:05 +053066 };
67
Paul Walmsley8c725dc2012-09-16 10:45:54 -060068#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \
69 static struct clk_hw_omap _name##_hw = { \
70 .hw = { \
71 .clk = &_name, \
72 }, \
73 .clkdm_name = _clkdm_name, \
74 };
75
76#define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \
77 _clksel_reg, _clksel_mask, \
78 _parent_names, _ops) \
79 static struct clk _name; \
80 static struct clk_hw_omap _name##_hw = { \
81 .hw = { \
82 .clk = &_name, \
83 }, \
84 .clksel = _clksel, \
85 .clksel_reg = _clksel_reg, \
86 .clksel_mask = _clksel_mask, \
87 .clkdm_name = _clkdm_name, \
88 }; \
89 DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
90
91#define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel, \
92 _clksel_reg, _clksel_mask, \
93 _enable_reg, _enable_bit, \
94 _hwops, _parent_names, _ops) \
95 static struct clk _name; \
96 static struct clk_hw_omap _name##_hw = { \
97 .hw = { \
98 .clk = &_name, \
99 }, \
100 .ops = _hwops, \
101 .enable_reg = _enable_reg, \
102 .enable_bit = _enable_bit, \
103 .clksel = _clksel, \
104 .clksel_reg = _clksel_reg, \
105 .clksel_mask = _clksel_mask, \
106 .clkdm_name = _clkdm_name, \
107 }; \
108 DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
109
Paul Walmsleya135eaa2012-09-27 10:33:34 -0600110/* struct clksel_rate.flags possibilities */
111#define RATE_IN_242X (1 << 0)
112#define RATE_IN_243X (1 << 1)
113#define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */
114#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
115#define RATE_IN_36XX (1 << 4)
116#define RATE_IN_4430 (1 << 5)
117#define RATE_IN_TI816X (1 << 6)
118#define RATE_IN_4460 (1 << 7)
119#define RATE_IN_AM33XX (1 << 8)
120#define RATE_IN_TI814X (1 << 9)
121
122#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
123#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
124#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
125#define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460)
126
127/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
128#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
129
130
131/**
132 * struct clksel_rate - register bitfield values corresponding to clk divisors
133 * @val: register bitfield value (shifted to bit 0)
134 * @div: clock divisor corresponding to @val
135 * @flags: (see "struct clksel_rate.flags possibilities" above)
136 *
137 * @val should match the value of a read from struct clk.clksel_reg
138 * AND'ed with struct clk.clksel_mask, shifted right to bit 0.
139 *
140 * @div is the divisor that should be applied to the parent clock's rate
141 * to produce the current clock's rate.
142 */
143struct clksel_rate {
144 u32 val;
145 u8 div;
146 u16 flags;
147};
148
149/**
150 * struct clksel - available parent clocks, and a pointer to their divisors
151 * @parent: struct clk * to a possible parent clock
152 * @rates: available divisors for this parent clock
153 *
154 * A struct clksel is always associated with one or more struct clks
155 * and one or more struct clksel_rates.
156 */
157struct clksel {
158 struct clk *parent;
159 const struct clksel_rate *rates;
160};
161
Russell Kingc0bf3132009-02-19 13:29:22 +0000162/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
163#define CORE_CLK_SRC_32K 0x0
164#define CORE_CLK_SRC_DPLL 0x1
165#define CORE_CLK_SRC_DPLL_X2 0x2
166
167/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
168#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
169#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
170#define OMAP2XXX_EN_DPLL_LOCKED 0x3
171
172/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
173#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
174#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
175#define OMAP3XXX_EN_DPLL_LOCKED 0x7
176
Rajendra Nayak16975a72009-12-08 18:47:16 -0700177/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
178#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
179#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
180#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
181#define OMAP4XXX_EN_DPLL_LOCKED 0x7
182
Mike Turquette32cc0022012-11-10 16:58:41 -0700183u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
184void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
185void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
Mike Turquette32cc0022012-11-10 16:58:41 -0700186void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
187void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
Paul Walmsley543d9372008-03-18 10:22:06 +0200188
Paul Walmsley12706c52011-07-10 05:57:06 -0600189void __init omap2_clk_disable_clkdm_control(void);
Paul Walmsley435699d2010-05-18 18:40:24 -0600190
191/* clkt_clksel.c public functions */
Mike Turquette32cc0022012-11-10 16:58:41 -0700192u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
193 unsigned long target_rate,
194 u32 *new_div);
195u8 omap2_clksel_find_parent_index(struct clk_hw *hw);
196unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate);
197long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
198 unsigned long *parent_rate);
199int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
200 unsigned long parent_rate);
201int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
Paul Walmsley435699d2010-05-18 18:40:24 -0600202
Paul Walmsley530e5442011-02-25 15:39:28 -0700203/* clkt_iclk.c public functions */
Rajendra Nayakb4777a22012-04-27 15:53:48 +0530204extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
205extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
Paul Walmsley530e5442011-02-25 15:39:28 -0700206
Mike Turquette32cc0022012-11-10 16:58:41 -0700207unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
Paul Walmsley435699d2010-05-18 18:40:24 -0600208
Mike Turquette32cc0022012-11-10 16:58:41 -0700209void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
210 void __iomem **other_reg,
211 u8 *other_bit);
212void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
213 void __iomem **idlest_reg,
214 u8 *idlest_bit, u8 *idlest_val);
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530215int omap2_clk_enable_autoidle_all(void);
Tero Kristo818b40e2013-10-11 19:15:32 +0300216int omap2_clk_allow_idle(struct clk *clk);
217int omap2_clk_deny_idle(struct clk *clk);
Paul Walmsley4d30e822010-02-22 22:09:36 -0700218int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
219void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
220 const char *core_ck_name,
221 const char *mpu_ck_name);
Paul Walmsley543d9372008-03-18 10:22:06 +0200222
Tero Kristo3ada6b102013-10-22 11:47:08 +0300223u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg);
224void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg);
225
Afzal Mohammed99541192011-12-13 10:46:43 -0800226extern u16 cpu_mask;
Paul Walmsleyd8a94452009-12-08 16:21:29 -0700227
Tero Kristo8111e012014-07-02 11:47:39 +0300228/*
229 * Clock features setup. Used instead of CPU type checks.
230 */
231struct ti_clk_features {
232 u32 flags;
Tero Kristoa24886e2014-07-02 11:47:40 +0300233 long fint_min;
234 long fint_max;
235 long fint_band1_max;
236 long fint_band2_min;
Tero Kristo512d91c2014-07-02 11:47:42 +0300237 u8 dpll_bypass_vals;
Tero Kristo066edb22014-07-02 11:47:44 +0300238 u8 cm_idlest_val;
Tero Kristo8111e012014-07-02 11:47:39 +0300239};
Tero Kristo2337c5b2014-07-02 11:47:43 +0300240
241#define TI_CLK_DPLL_HAS_FREQSEL (1 << 0)
Tero Kristof0d2f682014-10-03 16:57:10 +0300242#define TI_CLK_DPLL4_DENY_REPROGRAM (1 << 1)
Tero Kristo2337c5b2014-07-02 11:47:43 +0300243
Tero Kristo8111e012014-07-02 11:47:39 +0300244extern struct ti_clk_features ti_clk_features;
245
Russell Kingb36ee722008-11-04 17:59:52 +0000246extern const struct clkops clkops_omap2_dflt_wait;
Russell Kingbc51da42008-11-04 18:59:32 +0000247extern const struct clkops clkops_omap2_dflt;
Russell Kingb36ee722008-11-04 17:59:52 +0000248
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700249extern struct clk_functions omap2_clk_functions;
250
Paul Walmsleyd8a94452009-12-08 16:21:29 -0700251extern const struct clksel_rate gpt_32k_rates[];
252extern const struct clksel_rate gpt_sys_rates[];
253extern const struct clksel_rate gfx_l3_rates[];
Paul Walmsley22411392011-02-25 15:52:04 -0700254extern const struct clksel_rate dsp_ick_rates[];
Paul Walmsley543d9372008-03-18 10:22:06 +0200255
Mike Turquette32cc0022012-11-10 16:58:41 -0700256extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
257extern const struct clk_hw_omap_ops clkhwops_wait;
Rajendra Nayakb4777a22012-04-27 15:53:48 +0530258extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
Rajendra Nayakb4777a22012-04-27 15:53:48 +0530259extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
Rajendra Nayakb4777a22012-04-27 15:53:48 +0530260extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
261extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
Rajendra Nayakb4777a22012-04-27 15:53:48 +0530262extern const struct clk_hw_omap_ops clkhwops_apll54;
263extern const struct clk_hw_omap_ops clkhwops_apll96;
Paul Walmsley657ebfa2010-02-22 22:09:20 -0700264
Paul Walmsley571efa02012-05-29 15:26:40 +0530265/* clksel_rate blocks shared between OMAP44xx and AM33xx */
266extern const struct clksel_rate div_1_0_rates[];
Rajendra Nayakcb268672012-11-06 15:41:08 -0700267extern const struct clksel_rate div3_1to4_rates[];
Paul Walmsley571efa02012-05-29 15:26:40 +0530268extern const struct clksel_rate div_1_1_rates[];
269extern const struct clksel_rate div_1_2_rates[];
270extern const struct clksel_rate div_1_3_rates[];
271extern const struct clksel_rate div_1_4_rates[];
272extern const struct clksel_rate div31_1to31_rates[];
273
Mike Turquette32cc0022012-11-10 16:58:41 -0700274extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
275extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
Mike Turquette32cc0022012-11-10 16:58:41 -0700276
Tero Kristo80cbb222015-02-06 16:00:32 +0200277struct regmap;
278
Tero Kristo9f029b12014-10-22 15:15:36 +0300279int __init omap2_clk_provider_init(struct device_node *np, int index,
Tero Kristo80cbb222015-02-06 16:00:32 +0200280 struct regmap *syscon, void __iomem *mem);
Tero Kristo9f029b12014-10-22 15:15:36 +0300281void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem);
282
Tero Kristo8111e012014-07-02 11:47:39 +0300283void __init ti_clk_init_features(void);
Paul Walmsley543d9372008-03-18 10:22:06 +0200284#endif