Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1 | #ifndef _INTEL_RINGBUFFER_H_ |
| 2 | #define _INTEL_RINGBUFFER_H_ |
| 3 | |
Brad Volkin | 44e895a | 2014-05-10 14:10:43 -0700 | [diff] [blame] | 4 | #include <linux/hashtable.h> |
Chris Wilson | 06fbca7 | 2015-04-07 16:20:36 +0100 | [diff] [blame] | 5 | #include "i915_gem_batch_pool.h" |
Brad Volkin | 44e895a | 2014-05-10 14:10:43 -0700 | [diff] [blame] | 6 | |
| 7 | #define I915_CMD_HASH_ORDER 9 |
| 8 | |
Oscar Mateo | 4712274 | 2014-07-24 17:04:28 +0100 | [diff] [blame] | 9 | /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill, |
| 10 | * but keeps the logic simple. Indeed, the whole purpose of this macro is just |
| 11 | * to give some inclination as to some of the magic values used in the various |
| 12 | * workarounds! |
| 13 | */ |
| 14 | #define CACHELINE_BYTES 64 |
Arun Siluvery | 17ee950 | 2015-06-19 19:07:01 +0100 | [diff] [blame] | 15 | #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t)) |
Oscar Mateo | 4712274 | 2014-07-24 17:04:28 +0100 | [diff] [blame] | 16 | |
Ville Syrjälä | 633cf8f | 2012-12-03 18:43:32 +0200 | [diff] [blame] | 17 | /* |
| 18 | * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" |
| 19 | * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use" |
| 20 | * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use" |
| 21 | * |
| 22 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same |
| 23 | * cacheline, the Head Pointer must not be greater than the Tail |
| 24 | * Pointer." |
| 25 | */ |
| 26 | #define I915_RING_FREE_SPACE 64 |
| 27 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 28 | struct intel_hw_status_page { |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 29 | u32 *page_addr; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 30 | unsigned int gfx_addr; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 31 | struct drm_i915_gem_object *obj; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 32 | }; |
| 33 | |
Ben Widawsky | b7287d8 | 2011-04-25 11:22:22 -0700 | [diff] [blame] | 34 | #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) |
| 35 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 36 | |
Ben Widawsky | b7287d8 | 2011-04-25 11:22:22 -0700 | [diff] [blame] | 37 | #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) |
| 38 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 39 | |
Ben Widawsky | b7287d8 | 2011-04-25 11:22:22 -0700 | [diff] [blame] | 40 | #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) |
| 41 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 42 | |
Ben Widawsky | b7287d8 | 2011-04-25 11:22:22 -0700 | [diff] [blame] | 43 | #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) |
| 44 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 45 | |
Ben Widawsky | b7287d8 | 2011-04-25 11:22:22 -0700 | [diff] [blame] | 46 | #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) |
| 47 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) |
Daniel Vetter | 870e86d | 2010-08-02 16:29:44 +0200 | [diff] [blame] | 48 | |
Naresh Kumar Kachhi | e9fea57 | 2014-03-12 16:39:41 +0530 | [diff] [blame] | 49 | #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base)) |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 50 | #define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val) |
Naresh Kumar Kachhi | e9fea57 | 2014-03-12 16:39:41 +0530 | [diff] [blame] | 51 | |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 52 | /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to |
| 53 | * do the writes, and that must have qw aligned offsets, simply pretend it's 8b. |
| 54 | */ |
| 55 | #define i915_semaphore_seqno_size sizeof(uint64_t) |
| 56 | #define GEN8_SIGNAL_OFFSET(__ring, to) \ |
| 57 | (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ |
| 58 | ((__ring)->id * I915_NUM_RINGS * i915_semaphore_seqno_size) + \ |
| 59 | (i915_semaphore_seqno_size * (to))) |
| 60 | |
| 61 | #define GEN8_WAIT_OFFSET(__ring, from) \ |
| 62 | (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ |
| 63 | ((from) * I915_NUM_RINGS * i915_semaphore_seqno_size) + \ |
| 64 | (i915_semaphore_seqno_size * (__ring)->id)) |
| 65 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 66 | #define GEN8_RING_SEMAPHORE_INIT(e) do { \ |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 67 | if (!dev_priv->semaphore_obj) { \ |
| 68 | break; \ |
| 69 | } \ |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 70 | (e)->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET((e), RCS); \ |
| 71 | (e)->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET((e), VCS); \ |
| 72 | (e)->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET((e), BCS); \ |
| 73 | (e)->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET((e), VECS); \ |
| 74 | (e)->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET((e), VCS2); \ |
| 75 | (e)->semaphore.signal_ggtt[(e)->id] = MI_SEMAPHORE_SYNC_INVALID; \ |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 76 | } while(0) |
| 77 | |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 78 | enum intel_ring_hangcheck_action { |
Mika Kuoppala | da66146 | 2013-09-06 16:03:28 +0300 | [diff] [blame] | 79 | HANGCHECK_IDLE = 0, |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 80 | HANGCHECK_WAIT, |
| 81 | HANGCHECK_ACTIVE, |
| 82 | HANGCHECK_KICK, |
| 83 | HANGCHECK_HUNG, |
| 84 | }; |
Mika Kuoppala | ad8beae | 2013-06-12 12:35:32 +0300 | [diff] [blame] | 85 | |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 86 | #define HANGCHECK_SCORE_RING_HUNG 31 |
| 87 | |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 88 | struct intel_ring_hangcheck { |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 89 | u64 acthd; |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 90 | u32 seqno; |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 91 | int score; |
Mika Kuoppala | ad8beae | 2013-06-12 12:35:32 +0300 | [diff] [blame] | 92 | enum intel_ring_hangcheck_action action; |
Chris Wilson | 4be1738 | 2014-06-06 10:22:29 +0100 | [diff] [blame] | 93 | int deadlock; |
Mika Kuoppala | 61642ff | 2015-12-01 17:56:12 +0200 | [diff] [blame] | 94 | u32 instdone[I915_NUM_INSTDONE_REG]; |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 95 | }; |
| 96 | |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 97 | struct intel_ringbuffer { |
| 98 | struct drm_i915_gem_object *obj; |
| 99 | void __iomem *virtual_start; |
Tvrtko Ursulin | 0eb973d | 2016-01-15 15:10:28 +0000 | [diff] [blame] | 100 | struct i915_vma *vma; |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 101 | |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame^] | 102 | struct intel_engine_cs *engine; |
Chris Wilson | 608c1a5 | 2015-09-03 13:01:40 +0100 | [diff] [blame] | 103 | struct list_head link; |
Daniel Vetter | 0c7dd53 | 2014-08-11 16:17:44 +0200 | [diff] [blame] | 104 | |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 105 | u32 head; |
| 106 | u32 tail; |
| 107 | int space; |
| 108 | int size; |
| 109 | int effective_size; |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 110 | int reserved_size; |
| 111 | int reserved_tail; |
| 112 | bool reserved_in_use; |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 113 | |
| 114 | /** We track the position of the requests in the ring buffer, and |
| 115 | * when each is retired we increment last_retired_head as the GPU |
| 116 | * must have finished processing the request and so we know we |
| 117 | * can advance the ringbuffer up to that position. |
| 118 | * |
| 119 | * last_retired_head is set to -1 after the value is consumed so |
| 120 | * we can detect new retirements. |
| 121 | */ |
| 122 | u32 last_retired_head; |
| 123 | }; |
| 124 | |
Nick Hoath | 2107637 | 2015-01-15 13:10:38 +0000 | [diff] [blame] | 125 | struct intel_context; |
Francisco Jerez | 4e86f72 | 2015-05-29 16:44:14 +0300 | [diff] [blame] | 126 | struct drm_i915_reg_descriptor; |
Nick Hoath | 2107637 | 2015-01-15 13:10:38 +0000 | [diff] [blame] | 127 | |
Arun Siluvery | 17ee950 | 2015-06-19 19:07:01 +0100 | [diff] [blame] | 128 | /* |
| 129 | * we use a single page to load ctx workarounds so all of these |
| 130 | * values are referred in terms of dwords |
| 131 | * |
| 132 | * struct i915_wa_ctx_bb: |
| 133 | * offset: specifies batch starting position, also helpful in case |
| 134 | * if we want to have multiple batches at different offsets based on |
| 135 | * some criteria. It is not a requirement at the moment but provides |
| 136 | * an option for future use. |
| 137 | * size: size of the batch in DWORDS |
| 138 | */ |
| 139 | struct i915_ctx_workarounds { |
| 140 | struct i915_wa_ctx_bb { |
| 141 | u32 offset; |
| 142 | u32 size; |
| 143 | } indirect_ctx, per_ctx; |
| 144 | struct drm_i915_gem_object *obj; |
| 145 | }; |
| 146 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 147 | struct intel_engine_cs { |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 148 | const char *name; |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 149 | enum intel_ring_id { |
Tvrtko Ursulin | de1add3 | 2016-01-15 15:12:50 +0000 | [diff] [blame] | 150 | RCS = 0, |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 151 | BCS, |
Tvrtko Ursulin | de1add3 | 2016-01-15 15:12:50 +0000 | [diff] [blame] | 152 | VCS, |
| 153 | VCS2, /* Keep instances of the same type engine together. */ |
| 154 | VECS |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 155 | } id; |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 156 | #define I915_NUM_RINGS 5 |
Tvrtko Ursulin | de1add3 | 2016-01-15 15:12:50 +0000 | [diff] [blame] | 157 | #define _VCS(n) (VCS + (n)) |
Chris Wilson | 426960b | 2016-01-15 16:51:46 +0000 | [diff] [blame] | 158 | unsigned int exec_id; |
Alex Dai | 397097b | 2016-01-23 11:58:14 -0800 | [diff] [blame] | 159 | unsigned int guc_id; |
Daniel Vetter | 333e9fe | 2010-08-02 16:24:01 +0200 | [diff] [blame] | 160 | u32 mmio_base; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 161 | struct drm_device *dev; |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 162 | struct intel_ringbuffer *buffer; |
Chris Wilson | 608c1a5 | 2015-09-03 13:01:40 +0100 | [diff] [blame] | 163 | struct list_head buffers; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 164 | |
Chris Wilson | 06fbca7 | 2015-04-07 16:20:36 +0100 | [diff] [blame] | 165 | /* |
| 166 | * A pool of objects to use as shadow copies of client batch buffers |
| 167 | * when the command parser is enabled. Prevents the client from |
| 168 | * modifying the batch contents after software parsing. |
| 169 | */ |
| 170 | struct i915_gem_batch_pool batch_pool; |
| 171 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 172 | struct intel_hw_status_page status_page; |
Arun Siluvery | 17ee950 | 2015-06-19 19:07:01 +0100 | [diff] [blame] | 173 | struct i915_ctx_workarounds wa_ctx; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 174 | |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 175 | unsigned irq_refcount; /* protected by dev_priv->irq_lock */ |
Daniel Vetter | 6a848cc | 2012-04-11 22:12:46 +0200 | [diff] [blame] | 176 | u32 irq_enable_mask; /* bitmask to enable ring interrupt */ |
John Harrison | 581c26e8 | 2014-11-24 18:49:39 +0000 | [diff] [blame] | 177 | struct drm_i915_gem_request *trace_irq_req; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 178 | bool __must_check (*irq_get)(struct intel_engine_cs *ring); |
| 179 | void (*irq_put)(struct intel_engine_cs *ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 180 | |
Daniel Vetter | ecfe00d | 2014-11-20 00:33:04 +0100 | [diff] [blame] | 181 | int (*init_hw)(struct intel_engine_cs *ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 182 | |
John Harrison | 8753181 | 2015-05-29 17:43:44 +0100 | [diff] [blame] | 183 | int (*init_context)(struct drm_i915_gem_request *req); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 184 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 185 | void (*write_tail)(struct intel_engine_cs *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 186 | u32 value); |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 187 | int __must_check (*flush)(struct drm_i915_gem_request *req, |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 188 | u32 invalidate_domains, |
| 189 | u32 flush_domains); |
John Harrison | ee044a8 | 2015-05-29 17:44:00 +0100 | [diff] [blame] | 190 | int (*add_request)(struct drm_i915_gem_request *req); |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 191 | /* Some chipsets are not quite as coherent as advertised and need |
| 192 | * an expensive kick to force a true read of the up-to-date seqno. |
| 193 | * However, the up-to-date seqno is not always required and the last |
| 194 | * seen value is good enough. Note that the seqno will always be |
| 195 | * monotonic, even if not coherent. |
| 196 | */ |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 197 | u32 (*get_seqno)(struct intel_engine_cs *ring, |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 198 | bool lazy_coherency); |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 199 | void (*set_seqno)(struct intel_engine_cs *ring, |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 200 | u32 seqno); |
John Harrison | 53fddaf | 2015-05-29 17:44:02 +0100 | [diff] [blame] | 201 | int (*dispatch_execbuffer)(struct drm_i915_gem_request *req, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 202 | u64 offset, u32 length, |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 203 | unsigned dispatch_flags); |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 204 | #define I915_DISPATCH_SECURE 0x1 |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 205 | #define I915_DISPATCH_PINNED 0x2 |
Abdiel Janulgue | 919032e | 2015-06-16 13:39:40 +0300 | [diff] [blame] | 206 | #define I915_DISPATCH_RS 0x4 |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 207 | void (*cleanup)(struct intel_engine_cs *ring); |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 208 | |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 209 | /* GEN8 signal/wait table - never trust comments! |
| 210 | * signal to signal to signal to signal to signal to |
| 211 | * RCS VCS BCS VECS VCS2 |
| 212 | * -------------------------------------------------------------------- |
| 213 | * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) | |
| 214 | * |------------------------------------------------------------------- |
| 215 | * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) | |
| 216 | * |------------------------------------------------------------------- |
| 217 | * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) | |
| 218 | * |------------------------------------------------------------------- |
| 219 | * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) | |
| 220 | * |------------------------------------------------------------------- |
| 221 | * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) | |
| 222 | * |------------------------------------------------------------------- |
| 223 | * |
| 224 | * Generalization: |
| 225 | * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id) |
| 226 | * ie. transpose of g(x, y) |
| 227 | * |
| 228 | * sync from sync from sync from sync from sync from |
| 229 | * RCS VCS BCS VECS VCS2 |
| 230 | * -------------------------------------------------------------------- |
| 231 | * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) | |
| 232 | * |------------------------------------------------------------------- |
| 233 | * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) | |
| 234 | * |------------------------------------------------------------------- |
| 235 | * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) | |
| 236 | * |------------------------------------------------------------------- |
| 237 | * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) | |
| 238 | * |------------------------------------------------------------------- |
| 239 | * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) | |
| 240 | * |------------------------------------------------------------------- |
| 241 | * |
| 242 | * Generalization: |
| 243 | * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id) |
| 244 | * ie. transpose of f(x, y) |
| 245 | */ |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 246 | struct { |
| 247 | u32 sync_seqno[I915_NUM_RINGS-1]; |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 248 | |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 249 | union { |
| 250 | struct { |
| 251 | /* our mbox written by others */ |
| 252 | u32 wait[I915_NUM_RINGS]; |
| 253 | /* mboxes this ring signals to */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 254 | i915_reg_t signal[I915_NUM_RINGS]; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 255 | } mbox; |
| 256 | u64 signal_ggtt[I915_NUM_RINGS]; |
| 257 | }; |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 258 | |
| 259 | /* AKA wait() */ |
John Harrison | 599d924 | 2015-05-29 17:44:04 +0100 | [diff] [blame] | 260 | int (*sync_to)(struct drm_i915_gem_request *to_req, |
| 261 | struct intel_engine_cs *from, |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 262 | u32 seqno); |
John Harrison | f716968 | 2015-05-29 17:44:05 +0100 | [diff] [blame] | 263 | int (*signal)(struct drm_i915_gem_request *signaller_req, |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 264 | /* num_dwords needed by caller */ |
| 265 | unsigned int num_dwords); |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 266 | } semaphore; |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 267 | |
Oscar Mateo | 4da46e1 | 2014-07-24 17:04:27 +0100 | [diff] [blame] | 268 | /* Execlists */ |
Michel Thierry | acdd884 | 2014-07-24 17:04:38 +0100 | [diff] [blame] | 269 | spinlock_t execlist_lock; |
| 270 | struct list_head execlist_queue; |
Thomas Daniel | c86ee3a9 | 2014-11-13 10:27:05 +0000 | [diff] [blame] | 271 | struct list_head execlist_retired_req_list; |
Tvrtko Ursulin | c6a2ac7 | 2016-02-26 16:58:32 +0000 | [diff] [blame] | 272 | unsigned int next_context_status_buffer; |
| 273 | unsigned int idle_lite_restore_wa; |
Tvrtko Ursulin | ca82580c | 2016-01-15 15:10:27 +0000 | [diff] [blame] | 274 | bool disable_lite_restore_wa; |
| 275 | u32 ctx_desc_template; |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 276 | u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */ |
John Harrison | c4e7663 | 2015-05-29 17:44:01 +0100 | [diff] [blame] | 277 | int (*emit_request)(struct drm_i915_gem_request *request); |
John Harrison | 7deb4d398 | 2015-05-29 17:43:59 +0100 | [diff] [blame] | 278 | int (*emit_flush)(struct drm_i915_gem_request *request, |
Oscar Mateo | 4712274 | 2014-07-24 17:04:28 +0100 | [diff] [blame] | 279 | u32 invalidate_domains, |
| 280 | u32 flush_domains); |
John Harrison | be795fc | 2015-05-29 17:44:03 +0100 | [diff] [blame] | 281 | int (*emit_bb_start)(struct drm_i915_gem_request *req, |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 282 | u64 offset, unsigned dispatch_flags); |
Oscar Mateo | 4da46e1 | 2014-07-24 17:04:27 +0100 | [diff] [blame] | 283 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 284 | /** |
| 285 | * List of objects currently involved in rendering from the |
| 286 | * ringbuffer. |
| 287 | * |
| 288 | * Includes buffers having the contents of their GPU caches |
John Harrison | 97b2a6a | 2014-11-24 18:49:26 +0000 | [diff] [blame] | 289 | * flushed, not necessarily primitives. last_read_req |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 290 | * represents when the rendering involved will be completed. |
| 291 | * |
| 292 | * A reference is held on the buffer while on this list. |
| 293 | */ |
| 294 | struct list_head active_list; |
| 295 | |
| 296 | /** |
| 297 | * List of breadcrumbs associated with GPU requests currently |
| 298 | * outstanding. |
| 299 | */ |
| 300 | struct list_head request_list; |
| 301 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 302 | /** |
Tomas Elf | 94f7bbe | 2015-07-09 15:30:57 +0100 | [diff] [blame] | 303 | * Seqno of request most recently submitted to request_list. |
| 304 | * Used exclusively by hang checker to avoid grabbing lock while |
| 305 | * inspecting request list. |
| 306 | */ |
| 307 | u32 last_submitted_seqno; |
| 308 | |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 309 | bool gpu_caches_dirty; |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 310 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 311 | wait_queue_head_t irq_queue; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 312 | |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 313 | struct intel_context *last_context; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 314 | |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 315 | struct intel_ring_hangcheck hangcheck; |
| 316 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 317 | struct { |
| 318 | struct drm_i915_gem_object *obj; |
| 319 | u32 gtt_offset; |
| 320 | volatile u32 *cpu_page; |
| 321 | } scratch; |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 322 | |
Brad Volkin | 44e895a | 2014-05-10 14:10:43 -0700 | [diff] [blame] | 323 | bool needs_cmd_parser; |
| 324 | |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 325 | /* |
Brad Volkin | 44e895a | 2014-05-10 14:10:43 -0700 | [diff] [blame] | 326 | * Table of commands the command parser needs to know about |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 327 | * for this ring. |
| 328 | */ |
Brad Volkin | 44e895a | 2014-05-10 14:10:43 -0700 | [diff] [blame] | 329 | DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER); |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 330 | |
| 331 | /* |
| 332 | * Table of registers allowed in commands that read/write registers. |
| 333 | */ |
Francisco Jerez | 4e86f72 | 2015-05-29 16:44:14 +0300 | [diff] [blame] | 334 | const struct drm_i915_reg_descriptor *reg_table; |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 335 | int reg_count; |
| 336 | |
| 337 | /* |
| 338 | * Table of registers allowed in commands that read/write registers, but |
| 339 | * only from the DRM master. |
| 340 | */ |
Francisco Jerez | 4e86f72 | 2015-05-29 16:44:14 +0300 | [diff] [blame] | 341 | const struct drm_i915_reg_descriptor *master_reg_table; |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 342 | int master_reg_count; |
| 343 | |
| 344 | /* |
| 345 | * Returns the bitmask for the length field of the specified command. |
| 346 | * Return 0 for an unrecognized/invalid command. |
| 347 | * |
| 348 | * If the command parser finds an entry for a command in the ring's |
| 349 | * cmd_tables, it gets the command's length based on the table entry. |
| 350 | * If not, it calls this function to determine the per-ring length field |
| 351 | * encoding for the command (i.e. certain opcode ranges use certain bits |
| 352 | * to encode the command length in the header). |
| 353 | */ |
| 354 | u32 (*get_cmd_length_mask)(u32 cmd_header); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 355 | }; |
| 356 | |
Dave Gordon | b0366a5 | 2015-12-08 15:02:36 +0000 | [diff] [blame] | 357 | static inline bool |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 358 | intel_ring_initialized(struct intel_engine_cs *engine) |
Dave Gordon | b0366a5 | 2015-12-08 15:02:36 +0000 | [diff] [blame] | 359 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 360 | return engine->dev != NULL; |
Dave Gordon | b0366a5 | 2015-12-08 15:02:36 +0000 | [diff] [blame] | 361 | } |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 362 | |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 363 | static inline unsigned |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 364 | intel_ring_flag(struct intel_engine_cs *engine) |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 365 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 366 | return 1 << engine->id; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 367 | } |
| 368 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 369 | static inline u32 |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 370 | intel_ring_sync_index(struct intel_engine_cs *engine, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 371 | struct intel_engine_cs *other) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 372 | { |
| 373 | int idx; |
| 374 | |
| 375 | /* |
Rodrigo Vivi | ddd4dbc | 2014-06-30 09:51:11 -0700 | [diff] [blame] | 376 | * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2; |
| 377 | * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs; |
| 378 | * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs; |
| 379 | * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs; |
| 380 | * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 381 | */ |
| 382 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 383 | idx = (other - engine) - 1; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 384 | if (idx < 0) |
| 385 | idx += I915_NUM_RINGS; |
| 386 | |
| 387 | return idx; |
| 388 | } |
| 389 | |
Imre Deak | 319404d | 2015-08-14 18:35:27 +0300 | [diff] [blame] | 390 | static inline void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 391 | intel_flush_status_page(struct intel_engine_cs *engine, int reg) |
Imre Deak | 319404d | 2015-08-14 18:35:27 +0300 | [diff] [blame] | 392 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 393 | drm_clflush_virt_range(&engine->status_page.page_addr[reg], |
Imre Deak | 319404d | 2015-08-14 18:35:27 +0300 | [diff] [blame] | 394 | sizeof(uint32_t)); |
| 395 | } |
| 396 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 397 | static inline u32 |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 398 | intel_read_status_page(struct intel_engine_cs *engine, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 399 | int reg) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 400 | { |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 401 | /* Ensure that the compiler doesn't optimize away the load. */ |
| 402 | barrier(); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 403 | return engine->status_page.page_addr[reg]; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 404 | } |
| 405 | |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 406 | static inline void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 407 | intel_write_status_page(struct intel_engine_cs *engine, |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 408 | int reg, u32 value) |
| 409 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 410 | engine->status_page.page_addr[reg] = value; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 411 | } |
| 412 | |
Jani Nikula | e282891 | 2016-01-18 09:19:47 +0200 | [diff] [blame] | 413 | /* |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 414 | * Reads a dword out of the status page, which is written to from the command |
| 415 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or |
| 416 | * MI_STORE_DATA_IMM. |
| 417 | * |
| 418 | * The following dwords have a reserved meaning: |
| 419 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. |
| 420 | * 0x04: ring 0 head pointer |
| 421 | * 0x05: ring 1 head pointer (915-class) |
| 422 | * 0x06: ring 2 head pointer (915-class) |
| 423 | * 0x10-0x1b: Context status DWords (GM45) |
| 424 | * 0x1f: Last written status offset. (GM45) |
Thomas Daniel | b07da53 | 2015-02-18 11:48:21 +0000 | [diff] [blame] | 425 | * 0x20-0x2f: Reserved (Gen6+) |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 426 | * |
Thomas Daniel | b07da53 | 2015-02-18 11:48:21 +0000 | [diff] [blame] | 427 | * The area from dword 0x30 to 0x3ff is available for driver usage. |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 428 | */ |
Thomas Daniel | b07da53 | 2015-02-18 11:48:21 +0000 | [diff] [blame] | 429 | #define I915_GEM_HWS_INDEX 0x30 |
Chris Wilson | 7c17d37 | 2016-01-20 15:43:35 +0200 | [diff] [blame] | 430 | #define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
Thomas Daniel | b07da53 | 2015-02-18 11:48:21 +0000 | [diff] [blame] | 431 | #define I915_GEM_HWS_SCRATCH_INDEX 0x40 |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 432 | #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 433 | |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 434 | struct intel_ringbuffer * |
| 435 | intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size); |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 436 | int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, |
| 437 | struct intel_ringbuffer *ringbuf); |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 438 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf); |
| 439 | void intel_ringbuffer_free(struct intel_ringbuffer *ring); |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 440 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 441 | void intel_stop_ring_buffer(struct intel_engine_cs *engine); |
| 442 | void intel_cleanup_ring_buffer(struct intel_engine_cs *engine); |
Ben Widawsky | 96f298a | 2011-03-19 18:14:27 -0700 | [diff] [blame] | 443 | |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 444 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request); |
| 445 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 446 | int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n); |
John Harrison | bba09b1 | 2015-05-29 17:44:06 +0100 | [diff] [blame] | 447 | int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 448 | static inline void intel_ring_emit(struct intel_engine_cs *engine, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 449 | u32 data) |
Chris Wilson | e898cd2 | 2010-08-04 15:18:14 +0100 | [diff] [blame] | 450 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 451 | struct intel_ringbuffer *ringbuf = engine->buffer; |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 452 | iowrite32(data, ringbuf->virtual_start + ringbuf->tail); |
| 453 | ringbuf->tail += 4; |
Chris Wilson | e898cd2 | 2010-08-04 15:18:14 +0100 | [diff] [blame] | 454 | } |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 455 | static inline void intel_ring_emit_reg(struct intel_engine_cs *engine, |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 456 | i915_reg_t reg) |
Ville Syrjälä | f92a916 | 2015-11-04 23:20:07 +0200 | [diff] [blame] | 457 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 458 | intel_ring_emit(engine, i915_mmio_reg_offset(reg)); |
Ville Syrjälä | f92a916 | 2015-11-04 23:20:07 +0200 | [diff] [blame] | 459 | } |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 460 | static inline void intel_ring_advance(struct intel_engine_cs *engine) |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 461 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 462 | struct intel_ringbuffer *ringbuf = engine->buffer; |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 463 | ringbuf->tail &= ringbuf->size - 1; |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 464 | } |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 465 | int __intel_ring_space(int head, int tail, int size); |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 466 | void intel_ring_update_space(struct intel_ringbuffer *ringbuf); |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 467 | int intel_ring_space(struct intel_ringbuffer *ringbuf); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 468 | bool intel_ring_stopped(struct intel_engine_cs *engine); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 469 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 470 | int __must_check intel_ring_idle(struct intel_engine_cs *engine); |
| 471 | void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno); |
John Harrison | 4866d72 | 2015-05-29 17:43:55 +0100 | [diff] [blame] | 472 | int intel_ring_flush_all_caches(struct drm_i915_gem_request *req); |
John Harrison | 2f20055 | 2015-05-29 17:43:53 +0100 | [diff] [blame] | 473 | int intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 474 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 475 | void intel_fini_pipe_control(struct intel_engine_cs *engine); |
| 476 | int intel_init_pipe_control(struct intel_engine_cs *engine); |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 477 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 478 | int intel_init_render_ring_buffer(struct drm_device *dev); |
| 479 | int intel_init_bsd_ring_buffer(struct drm_device *dev); |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 480 | int intel_init_bsd2_ring_buffer(struct drm_device *dev); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 481 | int intel_init_blt_ring_buffer(struct drm_device *dev); |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 482 | int intel_init_vebox_ring_buffer(struct drm_device *dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 483 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 484 | u64 intel_ring_get_active_head(struct intel_engine_cs *engine); |
Daniel Vetter | 79f321b | 2010-09-24 21:20:10 +0200 | [diff] [blame] | 485 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 486 | int init_workarounds_ring(struct intel_engine_cs *engine); |
Michel Thierry | 771b9a5 | 2014-11-11 16:47:33 +0000 | [diff] [blame] | 487 | |
Oscar Mateo | 1b5d063 | 2014-07-03 16:28:04 +0100 | [diff] [blame] | 488 | static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf) |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 489 | { |
Oscar Mateo | 1b5d063 | 2014-07-03 16:28:04 +0100 | [diff] [blame] | 490 | return ringbuf->tail; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 491 | } |
| 492 | |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 493 | /* |
| 494 | * Arbitrary size for largest possible 'add request' sequence. The code paths |
| 495 | * are complex and variable. Empirical measurement shows that the worst case |
| 496 | * is ILK at 136 words. Reserving too much is better than reserving too little |
| 497 | * as that allows for corner cases that might have been missed. So the figure |
| 498 | * has been rounded up to 160 words. |
| 499 | */ |
| 500 | #define MIN_SPACE_FOR_ADD_REQUEST 160 |
| 501 | |
| 502 | /* |
| 503 | * Reserve space in the ring to guarantee that the i915_add_request() call |
| 504 | * will always have sufficient room to do its stuff. The request creation |
| 505 | * code calls this automatically. |
| 506 | */ |
| 507 | void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size); |
| 508 | /* Cancel the reservation, e.g. because the request is being discarded. */ |
| 509 | void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf); |
| 510 | /* Use the reserved space - for use by i915_add_request() only. */ |
| 511 | void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf); |
| 512 | /* Finish with the reserved space - for use by i915_add_request() only. */ |
| 513 | void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf); |
| 514 | |
John Harrison | 79bbcc2 | 2015-06-30 12:40:55 +0100 | [diff] [blame] | 515 | /* Legacy ringbuffer specific portion of reservation code: */ |
| 516 | int intel_ring_reserve_space(struct drm_i915_gem_request *request); |
| 517 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 518 | #endif /* _INTEL_RINGBUFFER_H_ */ |