Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1 | /* |
Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 2 | * Set up the interrupt priorities |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 3 | * |
Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 4 | * Copyright 2004-2009 Analog Devices Inc. |
| 5 | * 2003 Bas Vermeulen <bas@buyways.nl> |
| 6 | * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca> |
| 7 | * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca> |
| 8 | * 1999 D. Jeff Dionne <jeff@uclinux.org> |
| 9 | * 1996 Roman Zippel |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 10 | * |
Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 11 | * Licensed under the GPL-2 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 12 | */ |
| 13 | |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/kernel_stat.h> |
| 16 | #include <linux/seq_file.h> |
| 17 | #include <linux/irq.h> |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 18 | #ifdef CONFIG_IPIPE |
| 19 | #include <linux/ipipe.h> |
| 20 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 21 | #ifdef CONFIG_KGDB |
| 22 | #include <linux/kgdb.h> |
| 23 | #endif |
| 24 | #include <asm/traps.h> |
| 25 | #include <asm/blackfin.h> |
| 26 | #include <asm/gpio.h> |
| 27 | #include <asm/irq_handler.h> |
Mike Frysinger | 761ec44 | 2009-10-15 17:12:05 +0000 | [diff] [blame] | 28 | #include <asm/dpmc.h> |
Mike Frysinger | 7eb87fd | 2009-11-03 09:29:50 +0000 | [diff] [blame] | 29 | #include <asm/bfin5xx_spi.h> |
| 30 | #include <asm/bfin_sport.h> |
Michael Hennerich | 15435a2 | 2009-12-16 08:39:58 +0000 | [diff] [blame] | 31 | #include <asm/bfin_can.h> |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 32 | |
Mike Frysinger | 7beb743 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 33 | #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) |
| 34 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 35 | #ifdef BF537_FAMILY |
| 36 | # define BF537_GENERIC_ERROR_INT_DEMUX |
Mike Frysinger | 7eb87fd | 2009-11-03 09:29:50 +0000 | [diff] [blame] | 37 | # define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */ |
| 38 | # define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */ |
| 39 | # define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */ |
| 40 | # define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */ |
| 41 | # define UART_ERR_MASK (0x6) /* UART_IIR */ |
| 42 | # define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */ |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 43 | #else |
| 44 | # undef BF537_GENERIC_ERROR_INT_DEMUX |
| 45 | #endif |
| 46 | |
| 47 | /* |
| 48 | * NOTES: |
| 49 | * - we have separated the physical Hardware interrupt from the |
| 50 | * levels that the LINUX kernel sees (see the description in irq.h) |
| 51 | * - |
| 52 | */ |
| 53 | |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 54 | #ifndef CONFIG_SMP |
Mike Frysinger | a99bbcc | 2007-10-22 00:19:31 +0800 | [diff] [blame] | 55 | /* Initialize this to an actual value to force it into the .data |
| 56 | * section so that we know it is properly initialized at entry into |
| 57 | * the kernel but before bss is initialized to zero (which is where |
| 58 | * it would live otherwise). The 0x1f magic represents the IRQs we |
| 59 | * cannot actually mask out in hardware. |
| 60 | */ |
Mike Frysinger | 4005978 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 61 | unsigned long bfin_irq_flags = 0x1f; |
| 62 | EXPORT_SYMBOL(bfin_irq_flags); |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 63 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 64 | |
| 65 | /* The number of spurious interrupts */ |
| 66 | atomic_t num_spurious; |
| 67 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 68 | #ifdef CONFIG_PM |
| 69 | unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */ |
Michael Hennerich | 4a88d0c | 2008-08-05 17:38:41 +0800 | [diff] [blame] | 70 | unsigned vr_wakeup; |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 71 | #endif |
| 72 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 73 | struct ivgx { |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 74 | /* irq number for request_irq, available in mach-bf5xx/irq.h */ |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 75 | unsigned int irqno; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 76 | /* corresponding bit in the SIC_ISR register */ |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 77 | unsigned int isrflag; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 78 | } ivg_table[NR_PERI_INTS]; |
| 79 | |
| 80 | struct ivg_slice { |
| 81 | /* position of first irq in ivg_table for given ivg */ |
| 82 | struct ivgx *ifirst; |
| 83 | struct ivgx *istop; |
| 84 | } ivg7_13[IVG13 - IVG7 + 1]; |
| 85 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 86 | |
| 87 | /* |
| 88 | * Search SIC_IAR and fill tables with the irqvalues |
| 89 | * and their positions in the SIC_ISR register. |
| 90 | */ |
| 91 | static void __init search_IAR(void) |
| 92 | { |
| 93 | unsigned ivg, irq_pos = 0; |
| 94 | for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) { |
Mike Frysinger | 80fcdb9 | 2010-04-22 21:15:00 +0000 | [diff] [blame] | 95 | int irqN; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 96 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 97 | ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos]; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 98 | |
Mike Frysinger | 80fcdb9 | 2010-04-22 21:15:00 +0000 | [diff] [blame] | 99 | for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) { |
| 100 | int irqn; |
| 101 | u32 iar = bfin_read32((unsigned long *)SIC_IAR0 + |
| 102 | #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \ |
| 103 | defined(CONFIG_BF538) || defined(CONFIG_BF539) |
| 104 | ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4)) |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 105 | #else |
Mike Frysinger | 80fcdb9 | 2010-04-22 21:15:00 +0000 | [diff] [blame] | 106 | (irqN >> 3) |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 107 | #endif |
Mike Frysinger | 80fcdb9 | 2010-04-22 21:15:00 +0000 | [diff] [blame] | 108 | ); |
| 109 | |
| 110 | for (irqn = irqN; irqn < irqN + 4; ++irqn) { |
| 111 | int iar_shift = (irqn & 7) * 4; |
| 112 | if (ivg == (0xf & (iar >> iar_shift))) { |
| 113 | ivg_table[irq_pos].irqno = IVG7 + irqn; |
| 114 | ivg_table[irq_pos].isrflag = 1 << (irqn % 32); |
| 115 | ivg7_13[ivg].istop++; |
| 116 | irq_pos++; |
| 117 | } |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 118 | } |
| 119 | } |
| 120 | } |
| 121 | } |
| 122 | |
| 123 | /* |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 124 | * This is for core internal IRQs |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 125 | */ |
| 126 | |
Thomas Gleixner | 4f19ea4 | 2011-02-06 18:23:27 +0000 | [diff] [blame^] | 127 | static void bfin_ack_noop(struct irq_data *d) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 128 | { |
| 129 | /* Dummy function. */ |
| 130 | } |
| 131 | |
Thomas Gleixner | 4f19ea4 | 2011-02-06 18:23:27 +0000 | [diff] [blame^] | 132 | static void bfin_core_mask_irq(struct irq_data *d) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 133 | { |
Thomas Gleixner | 4f19ea4 | 2011-02-06 18:23:27 +0000 | [diff] [blame^] | 134 | bfin_irq_flags &= ~(1 << d->irq); |
David Howells | 3b139cd | 2010-10-07 14:08:52 +0100 | [diff] [blame] | 135 | if (!hard_irqs_disabled()) |
| 136 | hard_local_irq_enable(); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 137 | } |
| 138 | |
Thomas Gleixner | 4f19ea4 | 2011-02-06 18:23:27 +0000 | [diff] [blame^] | 139 | static void bfin_core_unmask_irq(struct irq_data *d) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 140 | { |
Thomas Gleixner | 4f19ea4 | 2011-02-06 18:23:27 +0000 | [diff] [blame^] | 141 | bfin_irq_flags |= 1 << d->irq; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 142 | /* |
| 143 | * If interrupts are enabled, IMASK must contain the same value |
Mike Frysinger | 4005978 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 144 | * as bfin_irq_flags. Make sure that invariant holds. If interrupts |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 145 | * are currently disabled we need not do anything; one of the |
| 146 | * callers will take care of setting IMASK to the proper value |
| 147 | * when reenabling interrupts. |
Mike Frysinger | 4005978 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 148 | * local_irq_enable just does "STI bfin_irq_flags", so it's exactly |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 149 | * what we need. |
| 150 | */ |
David Howells | 3b139cd | 2010-10-07 14:08:52 +0100 | [diff] [blame] | 151 | if (!hard_irqs_disabled()) |
| 152 | hard_local_irq_enable(); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 153 | return; |
| 154 | } |
| 155 | |
| 156 | static void bfin_internal_mask_irq(unsigned int irq) |
| 157 | { |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 158 | unsigned long flags; |
| 159 | |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 160 | #ifdef CONFIG_BF53x |
David Howells | 3b139cd | 2010-10-07 14:08:52 +0100 | [diff] [blame] | 161 | flags = hard_local_irq_save(); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 162 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 163 | ~(1 << SIC_SYSIRQ(irq))); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 164 | #else |
| 165 | unsigned mask_bank, mask_bit; |
David Howells | 3b139cd | 2010-10-07 14:08:52 +0100 | [diff] [blame] | 166 | flags = hard_local_irq_save(); |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 167 | mask_bank = SIC_SYSIRQ(irq) / 32; |
| 168 | mask_bit = SIC_SYSIRQ(irq) % 32; |
Bryan Wu | c04d66b | 2007-07-12 17:26:31 +0800 | [diff] [blame] | 169 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & |
| 170 | ~(1 << mask_bit)); |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 171 | #ifdef CONFIG_SMP |
| 172 | bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) & |
| 173 | ~(1 << mask_bit)); |
| 174 | #endif |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 175 | #endif |
David Howells | 3b139cd | 2010-10-07 14:08:52 +0100 | [diff] [blame] | 176 | hard_local_irq_restore(flags); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 177 | } |
| 178 | |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 179 | #ifdef CONFIG_SMP |
| 180 | static void bfin_internal_unmask_irq_affinity(unsigned int irq, |
| 181 | const struct cpumask *affinity) |
| 182 | #else |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 183 | static void bfin_internal_unmask_irq(unsigned int irq) |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 184 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 185 | { |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 186 | unsigned long flags; |
| 187 | |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 188 | #ifdef CONFIG_BF53x |
David Howells | 3b139cd | 2010-10-07 14:08:52 +0100 | [diff] [blame] | 189 | flags = hard_local_irq_save(); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 190 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 191 | (1 << SIC_SYSIRQ(irq))); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 192 | #else |
| 193 | unsigned mask_bank, mask_bit; |
David Howells | 3b139cd | 2010-10-07 14:08:52 +0100 | [diff] [blame] | 194 | flags = hard_local_irq_save(); |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 195 | mask_bank = SIC_SYSIRQ(irq) / 32; |
| 196 | mask_bit = SIC_SYSIRQ(irq) % 32; |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 197 | #ifdef CONFIG_SMP |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 198 | if (cpumask_test_cpu(0, affinity)) |
| 199 | #endif |
| 200 | bfin_write_SIC_IMASK(mask_bank, |
| 201 | bfin_read_SIC_IMASK(mask_bank) | |
| 202 | (1 << mask_bit)); |
| 203 | #ifdef CONFIG_SMP |
| 204 | if (cpumask_test_cpu(1, affinity)) |
| 205 | bfin_write_SICB_IMASK(mask_bank, |
| 206 | bfin_read_SICB_IMASK(mask_bank) | |
| 207 | (1 << mask_bit)); |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 208 | #endif |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 209 | #endif |
David Howells | 3b139cd | 2010-10-07 14:08:52 +0100 | [diff] [blame] | 210 | hard_local_irq_restore(flags); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 211 | } |
| 212 | |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 213 | #ifdef CONFIG_SMP |
| 214 | static void bfin_internal_unmask_irq(unsigned int irq) |
| 215 | { |
| 216 | struct irq_desc *desc = irq_to_desc(irq); |
| 217 | bfin_internal_unmask_irq_affinity(irq, desc->affinity); |
| 218 | } |
| 219 | |
| 220 | static int bfin_internal_set_affinity(unsigned int irq, const struct cpumask *mask) |
| 221 | { |
| 222 | bfin_internal_mask_irq(irq); |
| 223 | bfin_internal_unmask_irq_affinity(irq, mask); |
| 224 | |
| 225 | return 0; |
| 226 | } |
| 227 | #endif |
| 228 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 229 | #ifdef CONFIG_PM |
| 230 | int bfin_internal_set_wake(unsigned int irq, unsigned int state) |
| 231 | { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 232 | u32 bank, bit, wakeup = 0; |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 233 | unsigned long flags; |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 234 | bank = SIC_SYSIRQ(irq) / 32; |
| 235 | bit = SIC_SYSIRQ(irq) % 32; |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 236 | |
Michael Hennerich | 4a88d0c | 2008-08-05 17:38:41 +0800 | [diff] [blame] | 237 | switch (irq) { |
| 238 | #ifdef IRQ_RTC |
| 239 | case IRQ_RTC: |
| 240 | wakeup |= WAKE; |
| 241 | break; |
| 242 | #endif |
| 243 | #ifdef IRQ_CAN0_RX |
| 244 | case IRQ_CAN0_RX: |
| 245 | wakeup |= CANWE; |
| 246 | break; |
| 247 | #endif |
| 248 | #ifdef IRQ_CAN1_RX |
| 249 | case IRQ_CAN1_RX: |
| 250 | wakeup |= CANWE; |
| 251 | break; |
| 252 | #endif |
| 253 | #ifdef IRQ_USB_INT0 |
| 254 | case IRQ_USB_INT0: |
| 255 | wakeup |= USBWE; |
| 256 | break; |
| 257 | #endif |
Michael Hennerich | d310fb4 | 2008-08-28 17:32:01 +0800 | [diff] [blame] | 258 | #ifdef CONFIG_BF54x |
Michael Hennerich | 4a88d0c | 2008-08-05 17:38:41 +0800 | [diff] [blame] | 259 | case IRQ_CNT: |
| 260 | wakeup |= ROTWE; |
| 261 | break; |
| 262 | #endif |
| 263 | default: |
| 264 | break; |
| 265 | } |
| 266 | |
David Howells | 3b139cd | 2010-10-07 14:08:52 +0100 | [diff] [blame] | 267 | flags = hard_local_irq_save(); |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 268 | |
Michael Hennerich | 4a88d0c | 2008-08-05 17:38:41 +0800 | [diff] [blame] | 269 | if (state) { |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 270 | bfin_sic_iwr[bank] |= (1 << bit); |
Michael Hennerich | 4a88d0c | 2008-08-05 17:38:41 +0800 | [diff] [blame] | 271 | vr_wakeup |= wakeup; |
| 272 | |
| 273 | } else { |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 274 | bfin_sic_iwr[bank] &= ~(1 << bit); |
Michael Hennerich | 4a88d0c | 2008-08-05 17:38:41 +0800 | [diff] [blame] | 275 | vr_wakeup &= ~wakeup; |
| 276 | } |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 277 | |
David Howells | 3b139cd | 2010-10-07 14:08:52 +0100 | [diff] [blame] | 278 | hard_local_irq_restore(flags); |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 279 | |
| 280 | return 0; |
| 281 | } |
| 282 | #endif |
| 283 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 284 | static struct irq_chip bfin_core_irqchip = { |
Graf Yang | 763e63c | 2008-10-08 17:08:15 +0800 | [diff] [blame] | 285 | .name = "CORE", |
Thomas Gleixner | 4f19ea4 | 2011-02-06 18:23:27 +0000 | [diff] [blame^] | 286 | .irq_ack = bfin_ack_noop, |
| 287 | .irq_mask = bfin_core_mask_irq, |
| 288 | .irq_unmask = bfin_core_unmask_irq, |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 289 | }; |
| 290 | |
| 291 | static struct irq_chip bfin_internal_irqchip = { |
Graf Yang | 763e63c | 2008-10-08 17:08:15 +0800 | [diff] [blame] | 292 | .name = "INTN", |
Thomas Gleixner | 4f19ea4 | 2011-02-06 18:23:27 +0000 | [diff] [blame^] | 293 | .irq_ack = bfin_ack_noop, |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 294 | .mask = bfin_internal_mask_irq, |
| 295 | .unmask = bfin_internal_unmask_irq, |
Michael Hennerich | ce3b7bb | 2008-02-25 13:48:47 +0800 | [diff] [blame] | 296 | .mask_ack = bfin_internal_mask_irq, |
| 297 | .disable = bfin_internal_mask_irq, |
| 298 | .enable = bfin_internal_unmask_irq, |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 299 | #ifdef CONFIG_SMP |
| 300 | .set_affinity = bfin_internal_set_affinity, |
| 301 | #endif |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 302 | #ifdef CONFIG_PM |
| 303 | .set_wake = bfin_internal_set_wake, |
| 304 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 305 | }; |
| 306 | |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 307 | static void bfin_handle_irq(unsigned irq) |
| 308 | { |
| 309 | #ifdef CONFIG_IPIPE |
| 310 | struct pt_regs regs; /* Contents not used. */ |
| 311 | ipipe_trace_irq_entry(irq); |
| 312 | __ipipe_handle_irq(irq, ®s); |
| 313 | ipipe_trace_irq_exit(irq); |
| 314 | #else /* !CONFIG_IPIPE */ |
Thomas Gleixner | b10bbbb | 2011-02-06 18:23:25 +0000 | [diff] [blame] | 315 | generic_handle_irq(irq); |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 316 | #endif /* !CONFIG_IPIPE */ |
| 317 | } |
| 318 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 319 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
| 320 | static int error_int_mask; |
| 321 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 322 | static void bfin_generic_error_mask_irq(unsigned int irq) |
| 323 | { |
| 324 | error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR)); |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 325 | if (!error_int_mask) |
| 326 | bfin_internal_mask_irq(IRQ_GENERIC_ERROR); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 327 | } |
| 328 | |
| 329 | static void bfin_generic_error_unmask_irq(unsigned int irq) |
| 330 | { |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 331 | bfin_internal_unmask_irq(IRQ_GENERIC_ERROR); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 332 | error_int_mask |= 1L << (irq - IRQ_PPI_ERROR); |
| 333 | } |
| 334 | |
| 335 | static struct irq_chip bfin_generic_error_irqchip = { |
Graf Yang | 763e63c | 2008-10-08 17:08:15 +0800 | [diff] [blame] | 336 | .name = "ERROR", |
Thomas Gleixner | 4f19ea4 | 2011-02-06 18:23:27 +0000 | [diff] [blame^] | 337 | .irq_ack = bfin_ack_noop, |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 338 | .mask_ack = bfin_generic_error_mask_irq, |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 339 | .mask = bfin_generic_error_mask_irq, |
| 340 | .unmask = bfin_generic_error_unmask_irq, |
| 341 | }; |
| 342 | |
| 343 | static void bfin_demux_error_irq(unsigned int int_err_irq, |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 344 | struct irq_desc *inta_desc) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 345 | { |
| 346 | int irq = 0; |
| 347 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 348 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) |
| 349 | if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK) |
| 350 | irq = IRQ_MAC_ERROR; |
| 351 | else |
| 352 | #endif |
| 353 | if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK) |
| 354 | irq = IRQ_SPORT0_ERROR; |
| 355 | else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK) |
| 356 | irq = IRQ_SPORT1_ERROR; |
| 357 | else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK) |
| 358 | irq = IRQ_PPI_ERROR; |
| 359 | else if (bfin_read_CAN_GIF() & CAN_ERR_MASK) |
| 360 | irq = IRQ_CAN_ERROR; |
| 361 | else if (bfin_read_SPI_STAT() & SPI_ERR_MASK) |
| 362 | irq = IRQ_SPI_ERROR; |
Mike Frysinger | 7eb87fd | 2009-11-03 09:29:50 +0000 | [diff] [blame] | 363 | else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 364 | irq = IRQ_UART0_ERROR; |
Mike Frysinger | 7eb87fd | 2009-11-03 09:29:50 +0000 | [diff] [blame] | 365 | else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 366 | irq = IRQ_UART1_ERROR; |
| 367 | |
| 368 | if (irq) { |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 369 | if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) |
| 370 | bfin_handle_irq(irq); |
| 371 | else { |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 372 | |
| 373 | switch (irq) { |
| 374 | case IRQ_PPI_ERROR: |
| 375 | bfin_write_PPI_STATUS(PPI_ERR_MASK); |
| 376 | break; |
| 377 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) |
| 378 | case IRQ_MAC_ERROR: |
| 379 | bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK); |
| 380 | break; |
| 381 | #endif |
| 382 | case IRQ_SPORT0_ERROR: |
| 383 | bfin_write_SPORT0_STAT(SPORT_ERR_MASK); |
| 384 | break; |
| 385 | |
| 386 | case IRQ_SPORT1_ERROR: |
| 387 | bfin_write_SPORT1_STAT(SPORT_ERR_MASK); |
| 388 | break; |
| 389 | |
| 390 | case IRQ_CAN_ERROR: |
| 391 | bfin_write_CAN_GIS(CAN_ERR_MASK); |
| 392 | break; |
| 393 | |
| 394 | case IRQ_SPI_ERROR: |
| 395 | bfin_write_SPI_STAT(SPI_ERR_MASK); |
| 396 | break; |
| 397 | |
| 398 | default: |
| 399 | break; |
| 400 | } |
| 401 | |
| 402 | pr_debug("IRQ %d:" |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 403 | " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n", |
| 404 | irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 405 | } |
| 406 | } else |
| 407 | printk(KERN_ERR |
| 408 | "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR" |
| 409 | " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n", |
Harvey Harrison | b85d858 | 2008-04-23 09:39:01 +0800 | [diff] [blame] | 410 | __func__, __FILE__, __LINE__); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 411 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 412 | } |
| 413 | #endif /* BF537_GENERIC_ERROR_INT_DEMUX */ |
| 414 | |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 415 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) |
| 416 | static int mac_stat_int_mask; |
| 417 | |
| 418 | static void bfin_mac_status_ack_irq(unsigned int irq) |
| 419 | { |
| 420 | switch (irq) { |
| 421 | case IRQ_MAC_MMCINT: |
| 422 | bfin_write_EMAC_MMC_TIRQS( |
| 423 | bfin_read_EMAC_MMC_TIRQE() & |
| 424 | bfin_read_EMAC_MMC_TIRQS()); |
| 425 | bfin_write_EMAC_MMC_RIRQS( |
| 426 | bfin_read_EMAC_MMC_RIRQE() & |
| 427 | bfin_read_EMAC_MMC_RIRQS()); |
| 428 | break; |
| 429 | case IRQ_MAC_RXFSINT: |
| 430 | bfin_write_EMAC_RX_STKY( |
| 431 | bfin_read_EMAC_RX_IRQE() & |
| 432 | bfin_read_EMAC_RX_STKY()); |
| 433 | break; |
| 434 | case IRQ_MAC_TXFSINT: |
| 435 | bfin_write_EMAC_TX_STKY( |
| 436 | bfin_read_EMAC_TX_IRQE() & |
| 437 | bfin_read_EMAC_TX_STKY()); |
| 438 | break; |
| 439 | case IRQ_MAC_WAKEDET: |
| 440 | bfin_write_EMAC_WKUP_CTL( |
| 441 | bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS); |
| 442 | break; |
| 443 | default: |
| 444 | /* These bits are W1C */ |
| 445 | bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT)); |
| 446 | break; |
| 447 | } |
| 448 | } |
| 449 | |
| 450 | static void bfin_mac_status_mask_irq(unsigned int irq) |
| 451 | { |
| 452 | mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT)); |
| 453 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
| 454 | switch (irq) { |
| 455 | case IRQ_MAC_PHYINT: |
| 456 | bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE); |
| 457 | break; |
| 458 | default: |
| 459 | break; |
| 460 | } |
| 461 | #else |
| 462 | if (!mac_stat_int_mask) |
| 463 | bfin_internal_mask_irq(IRQ_MAC_ERROR); |
| 464 | #endif |
| 465 | bfin_mac_status_ack_irq(irq); |
| 466 | } |
| 467 | |
| 468 | static void bfin_mac_status_unmask_irq(unsigned int irq) |
| 469 | { |
| 470 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
| 471 | switch (irq) { |
| 472 | case IRQ_MAC_PHYINT: |
| 473 | bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE); |
| 474 | break; |
| 475 | default: |
| 476 | break; |
| 477 | } |
| 478 | #else |
| 479 | if (!mac_stat_int_mask) |
| 480 | bfin_internal_unmask_irq(IRQ_MAC_ERROR); |
| 481 | #endif |
| 482 | mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT); |
| 483 | } |
| 484 | |
| 485 | #ifdef CONFIG_PM |
| 486 | int bfin_mac_status_set_wake(unsigned int irq, unsigned int state) |
| 487 | { |
| 488 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
| 489 | return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state); |
| 490 | #else |
| 491 | return bfin_internal_set_wake(IRQ_MAC_ERROR, state); |
| 492 | #endif |
| 493 | } |
| 494 | #endif |
| 495 | |
| 496 | static struct irq_chip bfin_mac_status_irqchip = { |
| 497 | .name = "MACST", |
Thomas Gleixner | 4f19ea4 | 2011-02-06 18:23:27 +0000 | [diff] [blame^] | 498 | .irq_ack = bfin_ack_noop, |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 499 | .mask_ack = bfin_mac_status_mask_irq, |
| 500 | .mask = bfin_mac_status_mask_irq, |
| 501 | .unmask = bfin_mac_status_unmask_irq, |
| 502 | #ifdef CONFIG_PM |
| 503 | .set_wake = bfin_mac_status_set_wake, |
| 504 | #endif |
| 505 | }; |
| 506 | |
| 507 | static void bfin_demux_mac_status_irq(unsigned int int_err_irq, |
| 508 | struct irq_desc *inta_desc) |
| 509 | { |
| 510 | int i, irq = 0; |
| 511 | u32 status = bfin_read_EMAC_SYSTAT(); |
| 512 | |
Michael Hennerich | bedeea6 | 2010-08-20 11:59:27 +0000 | [diff] [blame] | 513 | for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++) |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 514 | if (status & (1L << i)) { |
| 515 | irq = IRQ_MAC_PHYINT + i; |
| 516 | break; |
| 517 | } |
| 518 | |
| 519 | if (irq) { |
| 520 | if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) { |
| 521 | bfin_handle_irq(irq); |
| 522 | } else { |
| 523 | bfin_mac_status_ack_irq(irq); |
| 524 | pr_debug("IRQ %d:" |
| 525 | " MASKED MAC ERROR INTERRUPT ASSERTED\n", |
| 526 | irq); |
| 527 | } |
| 528 | } else |
| 529 | printk(KERN_ERR |
| 530 | "%s : %s : LINE %d :\nIRQ ?: MAC ERROR" |
Michael Hennerich | bedeea6 | 2010-08-20 11:59:27 +0000 | [diff] [blame] | 531 | " INTERRUPT ASSERTED BUT NO SOURCE FOUND" |
| 532 | "(EMAC_SYSTAT=0x%X)\n", |
| 533 | __func__, __FILE__, __LINE__, status); |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 534 | } |
| 535 | #endif |
| 536 | |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 537 | static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle) |
| 538 | { |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 539 | #ifdef CONFIG_IPIPE |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 540 | _set_irq_handler(irq, handle_level_irq); |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 541 | #else |
Thomas Gleixner | b10bbbb | 2011-02-06 18:23:25 +0000 | [diff] [blame] | 542 | __set_irq_handler_unlocked(irq, handle); |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 543 | #endif |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 544 | } |
| 545 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 546 | static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS); |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 547 | extern void bfin_gpio_irq_prepare(unsigned gpio); |
Michael Hennerich | 6fce6a8 | 2007-12-24 16:56:12 +0800 | [diff] [blame] | 548 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 549 | #if !defined(CONFIG_BF54x) |
| 550 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 551 | static void bfin_gpio_ack_irq(unsigned int irq) |
| 552 | { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 553 | /* AFAIK ack_irq in case mask_ack is provided |
| 554 | * get's only called for edge sense irqs |
| 555 | */ |
| 556 | set_gpio_data(irq_to_gpio(irq), 0); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 557 | } |
| 558 | |
| 559 | static void bfin_gpio_mask_ack_irq(unsigned int irq) |
| 560 | { |
Thomas Gleixner | b10bbbb | 2011-02-06 18:23:25 +0000 | [diff] [blame] | 561 | struct irq_desc *desc = irq_to_desc(irq); |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 562 | u32 gpionr = irq_to_gpio(irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 563 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 564 | if (desc->handle_irq == handle_edge_irq) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 565 | set_gpio_data(gpionr, 0); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 566 | |
| 567 | set_gpio_maska(gpionr, 0); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 568 | } |
| 569 | |
| 570 | static void bfin_gpio_mask_irq(unsigned int irq) |
| 571 | { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 572 | set_gpio_maska(irq_to_gpio(irq), 0); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 573 | } |
| 574 | |
| 575 | static void bfin_gpio_unmask_irq(unsigned int irq) |
| 576 | { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 577 | set_gpio_maska(irq_to_gpio(irq), 1); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 578 | } |
| 579 | |
| 580 | static unsigned int bfin_gpio_irq_startup(unsigned int irq) |
| 581 | { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 582 | u32 gpionr = irq_to_gpio(irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 583 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 584 | if (__test_and_set_bit(gpionr, gpio_enabled)) |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 585 | bfin_gpio_irq_prepare(gpionr); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 586 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 587 | bfin_gpio_unmask_irq(irq); |
| 588 | |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 589 | return 0; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 590 | } |
| 591 | |
| 592 | static void bfin_gpio_irq_shutdown(unsigned int irq) |
| 593 | { |
Graf Yang | 30af6d4 | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 594 | u32 gpionr = irq_to_gpio(irq); |
| 595 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 596 | bfin_gpio_mask_irq(irq); |
Graf Yang | 30af6d4 | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 597 | __clear_bit(gpionr, gpio_enabled); |
Graf Yang | 9570ff4 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 598 | bfin_gpio_irq_free(gpionr); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 599 | } |
| 600 | |
| 601 | static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) |
| 602 | { |
Graf Yang | 8eb3e3b | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 603 | int ret; |
| 604 | char buf[16]; |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 605 | u32 gpionr = irq_to_gpio(irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 606 | |
| 607 | if (type == IRQ_TYPE_PROBE) { |
| 608 | /* only probe unenabled GPIO interrupt lines */ |
Mike Frysinger | c369534 | 2009-06-13 10:32:29 -0400 | [diff] [blame] | 609 | if (test_bit(gpionr, gpio_enabled)) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 610 | return 0; |
| 611 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
| 612 | } |
| 613 | |
| 614 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 615 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 616 | |
Graf Yang | 9570ff4 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 617 | snprintf(buf, 16, "gpio-irq%d", irq); |
| 618 | ret = bfin_gpio_irq_request(gpionr, buf); |
| 619 | if (ret) |
| 620 | return ret; |
| 621 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 622 | if (__test_and_set_bit(gpionr, gpio_enabled)) |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 623 | bfin_gpio_irq_prepare(gpionr); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 624 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 625 | } else { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 626 | __clear_bit(gpionr, gpio_enabled); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 627 | return 0; |
| 628 | } |
| 629 | |
Michael Hennerich | f1bceb4 | 2008-02-02 16:17:52 +0800 | [diff] [blame] | 630 | set_gpio_inen(gpionr, 0); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 631 | set_gpio_dir(gpionr, 0); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 632 | |
| 633 | if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
| 634 | == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
| 635 | set_gpio_both(gpionr, 1); |
| 636 | else |
| 637 | set_gpio_both(gpionr, 0); |
| 638 | |
| 639 | if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) |
| 640 | set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */ |
| 641 | else |
| 642 | set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */ |
| 643 | |
Michael Hennerich | f1bceb4 | 2008-02-02 16:17:52 +0800 | [diff] [blame] | 644 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
| 645 | set_gpio_edge(gpionr, 1); |
| 646 | set_gpio_inen(gpionr, 1); |
Michael Hennerich | f1bceb4 | 2008-02-02 16:17:52 +0800 | [diff] [blame] | 647 | set_gpio_data(gpionr, 0); |
| 648 | |
| 649 | } else { |
| 650 | set_gpio_edge(gpionr, 0); |
Michael Hennerich | f1bceb4 | 2008-02-02 16:17:52 +0800 | [diff] [blame] | 651 | set_gpio_inen(gpionr, 1); |
| 652 | } |
| 653 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 654 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 655 | bfin_set_irq_handler(irq, handle_edge_irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 656 | else |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 657 | bfin_set_irq_handler(irq, handle_level_irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 658 | |
| 659 | return 0; |
| 660 | } |
| 661 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 662 | #ifdef CONFIG_PM |
| 663 | int bfin_gpio_set_wake(unsigned int irq, unsigned int state) |
| 664 | { |
Michael Hennerich | bb84dbf | 2010-03-10 14:26:06 +0000 | [diff] [blame] | 665 | return gpio_pm_wakeup_ctrl(irq_to_gpio(irq), state); |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 666 | } |
| 667 | #endif |
| 668 | |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 669 | static void bfin_demux_gpio_irq(unsigned int inta_irq, |
| 670 | struct irq_desc *desc) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 671 | { |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 672 | unsigned int i, gpio, mask, irq, search = 0; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 673 | |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 674 | switch (inta_irq) { |
| 675 | #if defined(CONFIG_BF53x) |
| 676 | case IRQ_PROG_INTA: |
| 677 | irq = IRQ_PF0; |
| 678 | search = 1; |
| 679 | break; |
| 680 | # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) |
| 681 | case IRQ_MAC_RX: |
| 682 | irq = IRQ_PH0; |
| 683 | break; |
| 684 | # endif |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 685 | #elif defined(CONFIG_BF538) || defined(CONFIG_BF539) |
| 686 | case IRQ_PORTF_INTA: |
| 687 | irq = IRQ_PF0; |
| 688 | break; |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 689 | #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 690 | case IRQ_PORTF_INTA: |
| 691 | irq = IRQ_PF0; |
| 692 | break; |
| 693 | case IRQ_PORTG_INTA: |
| 694 | irq = IRQ_PG0; |
| 695 | break; |
| 696 | case IRQ_PORTH_INTA: |
| 697 | irq = IRQ_PH0; |
| 698 | break; |
| 699 | #elif defined(CONFIG_BF561) |
| 700 | case IRQ_PROG0_INTA: |
| 701 | irq = IRQ_PF0; |
| 702 | break; |
| 703 | case IRQ_PROG1_INTA: |
| 704 | irq = IRQ_PF16; |
| 705 | break; |
| 706 | case IRQ_PROG2_INTA: |
| 707 | irq = IRQ_PF32; |
| 708 | break; |
| 709 | #endif |
| 710 | default: |
| 711 | BUG(); |
| 712 | return; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 713 | } |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 714 | |
| 715 | if (search) { |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 716 | for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 717 | irq += i; |
| 718 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 719 | mask = get_gpiop_data(i) & get_gpiop_maska(i); |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 720 | |
| 721 | while (mask) { |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 722 | if (mask & 1) |
| 723 | bfin_handle_irq(irq); |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 724 | irq++; |
| 725 | mask >>= 1; |
| 726 | } |
| 727 | } |
| 728 | } else { |
| 729 | gpio = irq_to_gpio(irq); |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 730 | mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio); |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 731 | |
| 732 | do { |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 733 | if (mask & 1) |
| 734 | bfin_handle_irq(irq); |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 735 | irq++; |
| 736 | mask >>= 1; |
| 737 | } while (mask); |
| 738 | } |
| 739 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 740 | } |
| 741 | |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 742 | #else /* CONFIG_BF54x */ |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 743 | |
| 744 | #define NR_PINT_SYS_IRQS 4 |
| 745 | #define NR_PINT_BITS 32 |
| 746 | #define NR_PINTS 160 |
| 747 | #define IRQ_NOT_AVAIL 0xFF |
| 748 | |
| 749 | #define PINT_2_BANK(x) ((x) >> 5) |
| 750 | #define PINT_2_BIT(x) ((x) & 0x1F) |
| 751 | #define PINT_BIT(x) (1 << (PINT_2_BIT(x))) |
| 752 | |
| 753 | static unsigned char irq2pint_lut[NR_PINTS]; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 754 | static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS]; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 755 | |
| 756 | struct pin_int_t { |
| 757 | unsigned int mask_set; |
| 758 | unsigned int mask_clear; |
| 759 | unsigned int request; |
| 760 | unsigned int assign; |
| 761 | unsigned int edge_set; |
| 762 | unsigned int edge_clear; |
| 763 | unsigned int invert_set; |
| 764 | unsigned int invert_clear; |
| 765 | unsigned int pinstate; |
| 766 | unsigned int latch; |
| 767 | }; |
| 768 | |
| 769 | static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = { |
| 770 | (struct pin_int_t *)PINT0_MASK_SET, |
| 771 | (struct pin_int_t *)PINT1_MASK_SET, |
| 772 | (struct pin_int_t *)PINT2_MASK_SET, |
| 773 | (struct pin_int_t *)PINT3_MASK_SET, |
| 774 | }; |
| 775 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 776 | inline unsigned int get_irq_base(u32 bank, u8 bmap) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 777 | { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 778 | unsigned int irq_base; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 779 | |
| 780 | if (bank < 2) { /*PA-PB */ |
| 781 | irq_base = IRQ_PA0 + bmap * 16; |
| 782 | } else { /*PC-PJ */ |
| 783 | irq_base = IRQ_PC0 + bmap * 16; |
| 784 | } |
| 785 | |
| 786 | return irq_base; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 787 | } |
| 788 | |
| 789 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ |
| 790 | void init_pint_lut(void) |
| 791 | { |
| 792 | u16 bank, bit, irq_base, bit_pos; |
| 793 | u32 pint_assign; |
| 794 | u8 bmap; |
| 795 | |
| 796 | memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut)); |
| 797 | |
| 798 | for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) { |
| 799 | |
| 800 | pint_assign = pint[bank]->assign; |
| 801 | |
| 802 | for (bit = 0; bit < NR_PINT_BITS; bit++) { |
| 803 | |
| 804 | bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF; |
| 805 | |
| 806 | irq_base = get_irq_base(bank, bmap); |
| 807 | |
| 808 | irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0); |
| 809 | bit_pos = bit + bank * NR_PINT_BITS; |
| 810 | |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 811 | pint2irq_lut[bit_pos] = irq_base - SYS_IRQS; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 812 | irq2pint_lut[irq_base - SYS_IRQS] = bit_pos; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 813 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 814 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 815 | } |
| 816 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 817 | static void bfin_gpio_ack_irq(unsigned int irq) |
| 818 | { |
Thomas Gleixner | b10bbbb | 2011-02-06 18:23:25 +0000 | [diff] [blame] | 819 | struct irq_desc *desc = irq_to_desc(irq); |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 820 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 821 | u32 pintbit = PINT_BIT(pint_val); |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 822 | u32 bank = PINT_2_BANK(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 823 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 824 | if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 825 | if (pint[bank]->invert_set & pintbit) |
| 826 | pint[bank]->invert_clear = pintbit; |
| 827 | else |
| 828 | pint[bank]->invert_set = pintbit; |
| 829 | } |
| 830 | pint[bank]->request = pintbit; |
| 831 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 832 | } |
| 833 | |
| 834 | static void bfin_gpio_mask_ack_irq(unsigned int irq) |
| 835 | { |
Thomas Gleixner | b10bbbb | 2011-02-06 18:23:25 +0000 | [diff] [blame] | 836 | struct irq_desc *desc = irq_to_desc(irq); |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 837 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 838 | u32 pintbit = PINT_BIT(pint_val); |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 839 | u32 bank = PINT_2_BANK(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 840 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 841 | if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 842 | if (pint[bank]->invert_set & pintbit) |
| 843 | pint[bank]->invert_clear = pintbit; |
| 844 | else |
| 845 | pint[bank]->invert_set = pintbit; |
| 846 | } |
| 847 | |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 848 | pint[bank]->request = pintbit; |
| 849 | pint[bank]->mask_clear = pintbit; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 850 | } |
| 851 | |
| 852 | static void bfin_gpio_mask_irq(unsigned int irq) |
| 853 | { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 854 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 855 | |
| 856 | pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 857 | } |
| 858 | |
| 859 | static void bfin_gpio_unmask_irq(unsigned int irq) |
| 860 | { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 861 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 862 | u32 pintbit = PINT_BIT(pint_val); |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 863 | u32 bank = PINT_2_BANK(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 864 | |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 865 | pint[bank]->mask_set = pintbit; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 866 | } |
| 867 | |
| 868 | static unsigned int bfin_gpio_irq_startup(unsigned int irq) |
| 869 | { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 870 | u32 gpionr = irq_to_gpio(irq); |
| 871 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 872 | |
Michael Hennerich | 50e163c | 2007-07-24 16:17:28 +0800 | [diff] [blame] | 873 | if (pint_val == IRQ_NOT_AVAIL) { |
| 874 | printk(KERN_ERR |
| 875 | "GPIO IRQ %d :Not in PINT Assign table " |
| 876 | "Reconfigure Interrupt to Port Assignemt\n", irq); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 877 | return -ENODEV; |
Michael Hennerich | 50e163c | 2007-07-24 16:17:28 +0800 | [diff] [blame] | 878 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 879 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 880 | if (__test_and_set_bit(gpionr, gpio_enabled)) |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 881 | bfin_gpio_irq_prepare(gpionr); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 882 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 883 | bfin_gpio_unmask_irq(irq); |
| 884 | |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 885 | return 0; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 886 | } |
| 887 | |
| 888 | static void bfin_gpio_irq_shutdown(unsigned int irq) |
| 889 | { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 890 | u32 gpionr = irq_to_gpio(irq); |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 891 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 892 | bfin_gpio_mask_irq(irq); |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 893 | __clear_bit(gpionr, gpio_enabled); |
Graf Yang | 9570ff4 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 894 | bfin_gpio_irq_free(gpionr); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 895 | } |
| 896 | |
| 897 | static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) |
| 898 | { |
Graf Yang | 8eb3e3b | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 899 | int ret; |
| 900 | char buf[16]; |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 901 | u32 gpionr = irq_to_gpio(irq); |
| 902 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 903 | u32 pintbit = PINT_BIT(pint_val); |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 904 | u32 bank = PINT_2_BANK(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 905 | |
| 906 | if (pint_val == IRQ_NOT_AVAIL) |
| 907 | return -ENODEV; |
| 908 | |
| 909 | if (type == IRQ_TYPE_PROBE) { |
| 910 | /* only probe unenabled GPIO interrupt lines */ |
Mike Frysinger | c369534 | 2009-06-13 10:32:29 -0400 | [diff] [blame] | 911 | if (test_bit(gpionr, gpio_enabled)) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 912 | return 0; |
| 913 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
| 914 | } |
| 915 | |
| 916 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | |
| 917 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { |
Graf Yang | 9570ff4 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 918 | |
| 919 | snprintf(buf, 16, "gpio-irq%d", irq); |
| 920 | ret = bfin_gpio_irq_request(gpionr, buf); |
| 921 | if (ret) |
| 922 | return ret; |
| 923 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 924 | if (__test_and_set_bit(gpionr, gpio_enabled)) |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 925 | bfin_gpio_irq_prepare(gpionr); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 926 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 927 | } else { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 928 | __clear_bit(gpionr, gpio_enabled); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 929 | return 0; |
| 930 | } |
| 931 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 932 | if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 933 | pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */ |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 934 | else |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 935 | pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */ |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 936 | |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 937 | if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
| 938 | == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 939 | if (gpio_get_value(gpionr)) |
| 940 | pint[bank]->invert_set = pintbit; |
| 941 | else |
| 942 | pint[bank]->invert_clear = pintbit; |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 943 | } |
| 944 | |
| 945 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
| 946 | pint[bank]->edge_set = pintbit; |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 947 | bfin_set_irq_handler(irq, handle_edge_irq); |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 948 | } else { |
| 949 | pint[bank]->edge_clear = pintbit; |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 950 | bfin_set_irq_handler(irq, handle_level_irq); |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 951 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 952 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 953 | return 0; |
| 954 | } |
| 955 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 956 | #ifdef CONFIG_PM |
| 957 | u32 pint_saved_masks[NR_PINT_SYS_IRQS]; |
| 958 | u32 pint_wakeup_masks[NR_PINT_SYS_IRQS]; |
| 959 | |
| 960 | int bfin_gpio_set_wake(unsigned int irq, unsigned int state) |
| 961 | { |
| 962 | u32 pint_irq; |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 963 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 964 | u32 bank = PINT_2_BANK(pint_val); |
| 965 | u32 pintbit = PINT_BIT(pint_val); |
| 966 | |
| 967 | switch (bank) { |
| 968 | case 0: |
| 969 | pint_irq = IRQ_PINT0; |
| 970 | break; |
| 971 | case 2: |
| 972 | pint_irq = IRQ_PINT2; |
| 973 | break; |
| 974 | case 3: |
| 975 | pint_irq = IRQ_PINT3; |
| 976 | break; |
| 977 | case 1: |
| 978 | pint_irq = IRQ_PINT1; |
| 979 | break; |
| 980 | default: |
| 981 | return -EINVAL; |
| 982 | } |
| 983 | |
| 984 | bfin_internal_set_wake(pint_irq, state); |
| 985 | |
| 986 | if (state) |
| 987 | pint_wakeup_masks[bank] |= pintbit; |
| 988 | else |
| 989 | pint_wakeup_masks[bank] &= ~pintbit; |
| 990 | |
| 991 | return 0; |
| 992 | } |
| 993 | |
| 994 | u32 bfin_pm_setup(void) |
| 995 | { |
| 996 | u32 val, i; |
| 997 | |
| 998 | for (i = 0; i < NR_PINT_SYS_IRQS; i++) { |
| 999 | val = pint[i]->mask_clear; |
| 1000 | pint_saved_masks[i] = val; |
| 1001 | if (val ^ pint_wakeup_masks[i]) { |
| 1002 | pint[i]->mask_clear = val; |
| 1003 | pint[i]->mask_set = pint_wakeup_masks[i]; |
| 1004 | } |
| 1005 | } |
| 1006 | |
| 1007 | return 0; |
| 1008 | } |
| 1009 | |
| 1010 | void bfin_pm_restore(void) |
| 1011 | { |
| 1012 | u32 i, val; |
| 1013 | |
| 1014 | for (i = 0; i < NR_PINT_SYS_IRQS; i++) { |
| 1015 | val = pint_saved_masks[i]; |
| 1016 | if (val ^ pint_wakeup_masks[i]) { |
| 1017 | pint[i]->mask_clear = pint[i]->mask_clear; |
| 1018 | pint[i]->mask_set = val; |
| 1019 | } |
| 1020 | } |
| 1021 | } |
| 1022 | #endif |
| 1023 | |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 1024 | static void bfin_demux_gpio_irq(unsigned int inta_irq, |
| 1025 | struct irq_desc *desc) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1026 | { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1027 | u32 bank, pint_val; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1028 | u32 request, irq; |
| 1029 | |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 1030 | switch (inta_irq) { |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1031 | case IRQ_PINT0: |
| 1032 | bank = 0; |
| 1033 | break; |
| 1034 | case IRQ_PINT2: |
| 1035 | bank = 2; |
| 1036 | break; |
| 1037 | case IRQ_PINT3: |
| 1038 | bank = 3; |
| 1039 | break; |
| 1040 | case IRQ_PINT1: |
| 1041 | bank = 1; |
| 1042 | break; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 1043 | default: |
| 1044 | return; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1045 | } |
| 1046 | |
| 1047 | pint_val = bank * NR_PINT_BITS; |
| 1048 | |
| 1049 | request = pint[bank]->request; |
| 1050 | |
| 1051 | while (request) { |
| 1052 | if (request & 1) { |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 1053 | irq = pint2irq_lut[pint_val] + SYS_IRQS; |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1054 | bfin_handle_irq(irq); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1055 | } |
| 1056 | pint_val++; |
| 1057 | request >>= 1; |
| 1058 | } |
| 1059 | |
| 1060 | } |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1061 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1062 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1063 | static struct irq_chip bfin_gpio_irqchip = { |
| 1064 | .name = "GPIO", |
| 1065 | .ack = bfin_gpio_ack_irq, |
| 1066 | .mask = bfin_gpio_mask_irq, |
| 1067 | .mask_ack = bfin_gpio_mask_ack_irq, |
| 1068 | .unmask = bfin_gpio_unmask_irq, |
| 1069 | .disable = bfin_gpio_mask_irq, |
| 1070 | .enable = bfin_gpio_unmask_irq, |
| 1071 | .set_type = bfin_gpio_irq_type, |
| 1072 | .startup = bfin_gpio_irq_startup, |
| 1073 | .shutdown = bfin_gpio_irq_shutdown, |
| 1074 | #ifdef CONFIG_PM |
| 1075 | .set_wake = bfin_gpio_set_wake, |
| 1076 | #endif |
| 1077 | }; |
| 1078 | |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1079 | void __cpuinit init_exception_vectors(void) |
Bernd Schmidt | 8be80ed | 2007-07-25 14:44:49 +0800 | [diff] [blame] | 1080 | { |
Mike Frysinger | f0b5d12 | 2007-08-05 17:03:59 +0800 | [diff] [blame] | 1081 | /* cannot program in software: |
| 1082 | * evt0 - emulation (jtag) |
| 1083 | * evt1 - reset |
| 1084 | */ |
| 1085 | bfin_write_EVT2(evt_nmi); |
Bernd Schmidt | 8be80ed | 2007-07-25 14:44:49 +0800 | [diff] [blame] | 1086 | bfin_write_EVT3(trap); |
| 1087 | bfin_write_EVT5(evt_ivhw); |
| 1088 | bfin_write_EVT6(evt_timer); |
| 1089 | bfin_write_EVT7(evt_evt7); |
| 1090 | bfin_write_EVT8(evt_evt8); |
| 1091 | bfin_write_EVT9(evt_evt9); |
| 1092 | bfin_write_EVT10(evt_evt10); |
| 1093 | bfin_write_EVT11(evt_evt11); |
| 1094 | bfin_write_EVT12(evt_evt12); |
| 1095 | bfin_write_EVT13(evt_evt13); |
Philippe Gerum | 9703a73 | 2009-06-22 18:23:48 +0200 | [diff] [blame] | 1096 | bfin_write_EVT14(evt_evt14); |
Bernd Schmidt | 8be80ed | 2007-07-25 14:44:49 +0800 | [diff] [blame] | 1097 | bfin_write_EVT15(evt_system_call); |
| 1098 | CSYNC(); |
| 1099 | } |
| 1100 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1101 | /* |
| 1102 | * This function should be called during kernel startup to initialize |
| 1103 | * the BFin IRQ handling routines. |
| 1104 | */ |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1105 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1106 | int __init init_arch_irq(void) |
| 1107 | { |
| 1108 | int irq; |
| 1109 | unsigned long ilat = 0; |
| 1110 | /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 1111 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \ |
| 1112 | || defined(BF538_FAMILY) || defined(CONFIG_BF51x) |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 1113 | bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); |
| 1114 | bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1115 | # ifdef CONFIG_BF54x |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 1116 | bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1117 | # endif |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1118 | # ifdef CONFIG_SMP |
| 1119 | bfin_write_SICB_IMASK0(SIC_UNMASK_ALL); |
| 1120 | bfin_write_SICB_IMASK1(SIC_UNMASK_ALL); |
| 1121 | # endif |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 1122 | #else |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1123 | bfin_write_SIC_IMASK(SIC_UNMASK_ALL); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 1124 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1125 | |
| 1126 | local_irq_disable(); |
| 1127 | |
Mike Frysinger | d70536e | 2008-08-25 17:37:35 +0800 | [diff] [blame] | 1128 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) |
Mike Frysinger | 95a86b5 | 2008-08-14 15:05:01 +0800 | [diff] [blame] | 1129 | /* Clear EMAC Interrupt Status bits so we can demux it later */ |
| 1130 | bfin_write_EMAC_SYSTAT(-1); |
| 1131 | #endif |
| 1132 | |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1133 | #ifdef CONFIG_BF54x |
| 1134 | # ifdef CONFIG_PINTx_REASSIGN |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1135 | pint[0]->assign = CONFIG_PINT0_ASSIGN; |
| 1136 | pint[1]->assign = CONFIG_PINT1_ASSIGN; |
| 1137 | pint[2]->assign = CONFIG_PINT2_ASSIGN; |
| 1138 | pint[3]->assign = CONFIG_PINT3_ASSIGN; |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1139 | # endif |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1140 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ |
| 1141 | init_pint_lut(); |
| 1142 | #endif |
| 1143 | |
| 1144 | for (irq = 0; irq <= SYS_IRQS; irq++) { |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1145 | if (irq <= IRQ_CORETMR) |
| 1146 | set_irq_chip(irq, &bfin_core_irqchip); |
| 1147 | else |
| 1148 | set_irq_chip(irq, &bfin_internal_irqchip); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1149 | |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1150 | switch (irq) { |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 1151 | #if defined(CONFIG_BF53x) |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1152 | case IRQ_PROG_INTA: |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1153 | # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1154 | case IRQ_MAC_RX: |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1155 | # endif |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 1156 | #elif defined(CONFIG_BF54x) |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1157 | case IRQ_PINT0: |
| 1158 | case IRQ_PINT1: |
| 1159 | case IRQ_PINT2: |
| 1160 | case IRQ_PINT3: |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 1161 | #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1162 | case IRQ_PORTF_INTA: |
| 1163 | case IRQ_PORTG_INTA: |
| 1164 | case IRQ_PORTH_INTA: |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 1165 | #elif defined(CONFIG_BF561) |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1166 | case IRQ_PROG0_INTA: |
| 1167 | case IRQ_PROG1_INTA: |
| 1168 | case IRQ_PROG2_INTA: |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1169 | #elif defined(CONFIG_BF538) || defined(CONFIG_BF539) |
| 1170 | case IRQ_PORTF_INTA: |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 1171 | #endif |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1172 | set_irq_chained_handler(irq, |
| 1173 | bfin_demux_gpio_irq); |
| 1174 | break; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1175 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1176 | case IRQ_GENERIC_ERROR: |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1177 | set_irq_chained_handler(irq, bfin_demux_error_irq); |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1178 | break; |
| 1179 | #endif |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 1180 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) |
| 1181 | case IRQ_MAC_ERROR: |
| 1182 | set_irq_chained_handler(irq, bfin_demux_mac_status_irq); |
| 1183 | break; |
| 1184 | #endif |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1185 | #ifdef CONFIG_SMP |
| 1186 | case IRQ_SUPPLE_0: |
| 1187 | case IRQ_SUPPLE_1: |
| 1188 | set_irq_handler(irq, handle_percpu_irq); |
| 1189 | break; |
| 1190 | #endif |
Graf Yang | 17941314 | 2009-08-18 04:29:33 +0000 | [diff] [blame] | 1191 | |
Yi Li | cb19171 | 2009-12-30 07:12:50 +0000 | [diff] [blame] | 1192 | #ifdef CONFIG_TICKSOURCE_CORETMR |
| 1193 | case IRQ_CORETMR: |
| 1194 | # ifdef CONFIG_SMP |
| 1195 | set_irq_handler(irq, handle_percpu_irq); |
| 1196 | break; |
| 1197 | # else |
| 1198 | set_irq_handler(irq, handle_simple_irq); |
| 1199 | break; |
| 1200 | # endif |
| 1201 | #endif |
| 1202 | |
| 1203 | #ifdef CONFIG_TICKSOURCE_GPTMR0 |
Philippe Gerum | a40494a | 2009-06-16 05:25:42 +0200 | [diff] [blame] | 1204 | case IRQ_TIMER0: |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1205 | set_irq_handler(irq, handle_simple_irq); |
| 1206 | break; |
Graf Yang | 17941314 | 2009-08-18 04:29:33 +0000 | [diff] [blame] | 1207 | #endif |
Yi Li | cb19171 | 2009-12-30 07:12:50 +0000 | [diff] [blame] | 1208 | |
| 1209 | #ifdef CONFIG_IPIPE |
Philippe Gerum | a40494a | 2009-06-16 05:25:42 +0200 | [diff] [blame] | 1210 | default: |
| 1211 | set_irq_handler(irq, handle_level_irq); |
| 1212 | break; |
| 1213 | #else /* !CONFIG_IPIPE */ |
Philippe Gerum | a40494a | 2009-06-16 05:25:42 +0200 | [diff] [blame] | 1214 | default: |
| 1215 | set_irq_handler(irq, handle_simple_irq); |
| 1216 | break; |
Graf Yang | 17941314 | 2009-08-18 04:29:33 +0000 | [diff] [blame] | 1217 | #endif /* !CONFIG_IPIPE */ |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1218 | } |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1219 | } |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1220 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1221 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1222 | for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) |
| 1223 | set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip, |
| 1224 | handle_level_irq); |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 1225 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) |
| 1226 | set_irq_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq); |
| 1227 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1228 | #endif |
| 1229 | |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 1230 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) |
| 1231 | for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++) |
| 1232 | set_irq_chip_and_handler(irq, &bfin_mac_status_irqchip, |
| 1233 | handle_level_irq); |
| 1234 | #endif |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1235 | /* if configured as edge, then will be changed to do_edge_IRQ */ |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 1236 | for (irq = GPIO_IRQ_BASE; |
| 1237 | irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1238 | set_irq_chip_and_handler(irq, &bfin_gpio_irqchip, |
| 1239 | handle_level_irq); |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 1240 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1241 | bfin_write_IMASK(0); |
| 1242 | CSYNC(); |
| 1243 | ilat = bfin_read_ILAT(); |
| 1244 | CSYNC(); |
| 1245 | bfin_write_ILAT(ilat); |
| 1246 | CSYNC(); |
| 1247 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1248 | printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n"); |
Mike Frysinger | 4005978 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1249 | /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx, |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1250 | * local_irq_enable() |
| 1251 | */ |
| 1252 | program_IAR(); |
| 1253 | /* Therefore it's better to setup IARs before interrupts enabled */ |
| 1254 | search_IAR(); |
| 1255 | |
| 1256 | /* Enable interrupts IVG7-15 */ |
Mike Frysinger | 4005978 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1257 | bfin_irq_flags |= IMASK_IVG15 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1258 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1259 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1260 | |
Michael Hennerich | 349ebbc | 2009-04-15 08:48:08 +0000 | [diff] [blame] | 1261 | /* This implicitly covers ANOMALY_05000171 |
| 1262 | * Boot-ROM code modifies SICA_IWRx wakeup registers |
| 1263 | */ |
Mike Frysinger | be1d854 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 1264 | #ifdef SIC_IWR0 |
Michael Hennerich | 56f5f59 | 2008-08-06 17:55:32 +0800 | [diff] [blame] | 1265 | bfin_write_SIC_IWR0(IWR_DISABLE_ALL); |
Mike Frysinger | be1d854 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 1266 | # ifdef SIC_IWR1 |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 1267 | /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which |
Michael Hennerich | 55546ac | 2008-08-13 17:41:13 +0800 | [diff] [blame] | 1268 | * will screw up the bootrom as it relies on MDMA0/1 waking it |
| 1269 | * up from IDLE instructions. See this report for more info: |
| 1270 | * http://blackfin.uclinux.org/gf/tracker/4323 |
| 1271 | */ |
Mike Frysinger | b7e1129 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1272 | if (ANOMALY_05000435) |
| 1273 | bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); |
| 1274 | else |
| 1275 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); |
Mike Frysinger | be1d854 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 1276 | # endif |
| 1277 | # ifdef SIC_IWR2 |
Michael Hennerich | 56f5f59 | 2008-08-06 17:55:32 +0800 | [diff] [blame] | 1278 | bfin_write_SIC_IWR2(IWR_DISABLE_ALL); |
Michael Hennerich | fe9ec9b | 2008-02-25 12:04:57 +0800 | [diff] [blame] | 1279 | # endif |
| 1280 | #else |
Michael Hennerich | 56f5f59 | 2008-08-06 17:55:32 +0800 | [diff] [blame] | 1281 | bfin_write_SIC_IWR(IWR_DISABLE_ALL); |
Michael Hennerich | fe9ec9b | 2008-02-25 12:04:57 +0800 | [diff] [blame] | 1282 | #endif |
| 1283 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1284 | return 0; |
| 1285 | } |
| 1286 | |
| 1287 | #ifdef CONFIG_DO_IRQ_L1 |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1288 | __attribute__((l1_text)) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1289 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1290 | void do_irq(int vec, struct pt_regs *fp) |
| 1291 | { |
| 1292 | if (vec == EVT_IVTMR_P) { |
| 1293 | vec = IRQ_CORETMR; |
| 1294 | } else { |
| 1295 | struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; |
| 1296 | struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; |
Mike Frysinger | 39c9996 | 2010-10-19 18:44:23 +0000 | [diff] [blame] | 1297 | #if defined(SIC_ISR0) |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 1298 | unsigned long sic_status[3]; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1299 | |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1300 | if (smp_processor_id()) { |
Mike Frysinger | 780172b | 2009-06-01 19:43:02 -0400 | [diff] [blame] | 1301 | # ifdef SICB_ISR0 |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1302 | /* This will be optimized out in UP mode. */ |
| 1303 | sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0(); |
| 1304 | sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1(); |
Mike Frysinger | 780172b | 2009-06-01 19:43:02 -0400 | [diff] [blame] | 1305 | # endif |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1306 | } else { |
| 1307 | sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); |
| 1308 | sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1(); |
| 1309 | } |
Mike Frysinger | 780172b | 2009-06-01 19:43:02 -0400 | [diff] [blame] | 1310 | # ifdef SIC_ISR2 |
Michael Hennerich | 4fb4524 | 2007-10-21 16:53:53 +0800 | [diff] [blame] | 1311 | sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2(); |
Mike Frysinger | 780172b | 2009-06-01 19:43:02 -0400 | [diff] [blame] | 1312 | # endif |
Mike Frysinger | 1f83b8f | 2007-07-12 22:58:21 +0800 | [diff] [blame] | 1313 | for (;; ivg++) { |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 1314 | if (ivg >= ivg_stop) { |
| 1315 | atomic_inc(&num_spurious); |
| 1316 | return; |
| 1317 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1318 | if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 1319 | break; |
| 1320 | } |
| 1321 | #else |
| 1322 | unsigned long sic_status; |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1323 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1324 | sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); |
| 1325 | |
| 1326 | for (;; ivg++) { |
| 1327 | if (ivg >= ivg_stop) { |
| 1328 | atomic_inc(&num_spurious); |
| 1329 | return; |
| 1330 | } else if (sic_status & ivg->isrflag) |
| 1331 | break; |
| 1332 | } |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 1333 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1334 | vec = ivg->irqno; |
| 1335 | } |
| 1336 | asm_do_IRQ(vec, fp); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1337 | } |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1338 | |
| 1339 | #ifdef CONFIG_IPIPE |
| 1340 | |
| 1341 | int __ipipe_get_irq_priority(unsigned irq) |
| 1342 | { |
| 1343 | int ient, prio; |
| 1344 | |
| 1345 | if (irq <= IRQ_CORETMR) |
| 1346 | return irq; |
| 1347 | |
| 1348 | for (ient = 0; ient < NR_PERI_INTS; ient++) { |
| 1349 | struct ivgx *ivg = ivg_table + ient; |
| 1350 | if (ivg->irqno == irq) { |
| 1351 | for (prio = 0; prio <= IVG13-IVG7; prio++) { |
| 1352 | if (ivg7_13[prio].ifirst <= ivg && |
| 1353 | ivg7_13[prio].istop > ivg) |
| 1354 | return IVG7 + prio; |
| 1355 | } |
| 1356 | } |
| 1357 | } |
| 1358 | |
| 1359 | return IVG15; |
| 1360 | } |
| 1361 | |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1362 | /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */ |
| 1363 | #ifdef CONFIG_DO_IRQ_L1 |
| 1364 | __attribute__((l1_text)) |
| 1365 | #endif |
| 1366 | asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) |
| 1367 | { |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1368 | struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr(); |
Philippe Gerum | a40494a | 2009-06-16 05:25:42 +0200 | [diff] [blame] | 1369 | struct ipipe_domain *this_domain = __ipipe_current_domain; |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1370 | struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop; |
| 1371 | struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst; |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1372 | int irq, s; |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1373 | |
Philippe Gerum | a40494a | 2009-06-16 05:25:42 +0200 | [diff] [blame] | 1374 | if (likely(vec == EVT_IVTMR_P)) |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1375 | irq = IRQ_CORETMR; |
Philippe Gerum | a40494a | 2009-06-16 05:25:42 +0200 | [diff] [blame] | 1376 | else { |
Mike Frysinger | 39c9996 | 2010-10-19 18:44:23 +0000 | [diff] [blame] | 1377 | #if defined(SIC_ISR0) |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1378 | unsigned long sic_status[3]; |
| 1379 | |
| 1380 | sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); |
| 1381 | sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1(); |
Mike Frysinger | 780172b | 2009-06-01 19:43:02 -0400 | [diff] [blame] | 1382 | # ifdef SIC_ISR2 |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1383 | sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2(); |
Mike Frysinger | 780172b | 2009-06-01 19:43:02 -0400 | [diff] [blame] | 1384 | # endif |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1385 | for (;; ivg++) { |
| 1386 | if (ivg >= ivg_stop) { |
| 1387 | atomic_inc(&num_spurious); |
| 1388 | return 0; |
| 1389 | } |
| 1390 | if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) |
| 1391 | break; |
| 1392 | } |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1393 | #else |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1394 | unsigned long sic_status; |
| 1395 | |
| 1396 | sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); |
| 1397 | |
| 1398 | for (;; ivg++) { |
| 1399 | if (ivg >= ivg_stop) { |
| 1400 | atomic_inc(&num_spurious); |
| 1401 | return 0; |
| 1402 | } else if (sic_status & ivg->isrflag) |
| 1403 | break; |
| 1404 | } |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1405 | #endif |
Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 1406 | irq = ivg->irqno; |
| 1407 | } |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1408 | |
| 1409 | if (irq == IRQ_SYSTMR) { |
Philippe Gerum | a40494a | 2009-06-16 05:25:42 +0200 | [diff] [blame] | 1410 | #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0) |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1411 | bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1412 | #endif |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1413 | /* This is basically what we need from the register frame. */ |
| 1414 | __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend; |
| 1415 | __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc; |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1416 | if (this_domain != ipipe_root_domain) |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1417 | __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10; |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1418 | else |
| 1419 | __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10; |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1420 | } |
| 1421 | |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1422 | if (this_domain == ipipe_root_domain) { |
| 1423 | s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status); |
| 1424 | barrier(); |
| 1425 | } |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1426 | |
| 1427 | ipipe_trace_irq_entry(irq); |
| 1428 | __ipipe_handle_irq(irq, regs); |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1429 | ipipe_trace_irq_exit(irq); |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1430 | |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1431 | if (this_domain == ipipe_root_domain) { |
| 1432 | set_thread_flag(TIF_IRQ_SYNC); |
| 1433 | if (!s) { |
| 1434 | __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status); |
| 1435 | return !test_bit(IPIPE_STALL_FLAG, &p->status); |
| 1436 | } |
| 1437 | } |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1438 | |
Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 1439 | return 0; |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1440 | } |
| 1441 | |
| 1442 | #endif /* CONFIG_IPIPE */ |