Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/video/omap2/dss/dss.c |
| 3 | * |
| 4 | * Copyright (C) 2009 Nokia Corporation |
| 5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> |
| 6 | * |
| 7 | * Some code and ideas taken from drivers/video/omap/ driver |
| 8 | * by Imre Deak. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify it |
| 11 | * under the terms of the GNU General Public License version 2 as published by |
| 12 | * the Free Software Foundation. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 17 | * more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License along with |
| 20 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 21 | */ |
| 22 | |
| 23 | #define DSS_SUBSYS_NAME "DSS" |
| 24 | |
| 25 | #include <linux/kernel.h> |
| 26 | #include <linux/io.h> |
| 27 | #include <linux/err.h> |
| 28 | #include <linux/delay.h> |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 29 | #include <linux/seq_file.h> |
| 30 | #include <linux/clk.h> |
Tomi Valkeinen | 24e6289 | 2011-05-23 11:51:18 +0300 | [diff] [blame] | 31 | #include <linux/platform_device.h> |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 32 | #include <linux/pm_runtime.h> |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 33 | |
Tomi Valkeinen | a0b38cc | 2011-05-11 14:05:07 +0300 | [diff] [blame] | 34 | #include <video/omapdss.h> |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 35 | #include <plat/clock.h> |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 36 | #include "dss.h" |
Tomi Valkeinen | 6ec549e | 2011-02-24 14:18:50 +0200 | [diff] [blame] | 37 | #include "dss_features.h" |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 38 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 39 | #define DSS_SZ_REGS SZ_512 |
| 40 | |
| 41 | struct dss_reg { |
| 42 | u16 idx; |
| 43 | }; |
| 44 | |
| 45 | #define DSS_REG(idx) ((const struct dss_reg) { idx }) |
| 46 | |
| 47 | #define DSS_REVISION DSS_REG(0x0000) |
| 48 | #define DSS_SYSCONFIG DSS_REG(0x0010) |
| 49 | #define DSS_SYSSTATUS DSS_REG(0x0014) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 50 | #define DSS_CONTROL DSS_REG(0x0040) |
| 51 | #define DSS_SDI_CONTROL DSS_REG(0x0044) |
| 52 | #define DSS_PLL_CONTROL DSS_REG(0x0048) |
| 53 | #define DSS_SDI_STATUS DSS_REG(0x005C) |
| 54 | |
| 55 | #define REG_GET(idx, start, end) \ |
| 56 | FLD_GET(dss_read_reg(idx), start, end) |
| 57 | |
| 58 | #define REG_FLD_MOD(idx, val, start, end) \ |
| 59 | dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) |
| 60 | |
| 61 | static struct { |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 62 | struct platform_device *pdev; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 63 | void __iomem *base; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 64 | |
Tomi Valkeinen | aac927c | 2011-05-23 15:46:54 +0300 | [diff] [blame] | 65 | int ctx_loss_cnt; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 66 | |
| 67 | struct clk *dpll4_m4_ck; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 68 | struct clk *dss_clk; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 69 | |
| 70 | unsigned long cache_req_pck; |
| 71 | unsigned long cache_prate; |
| 72 | struct dss_clock_info cache_dss_cinfo; |
| 73 | struct dispc_clock_info cache_dispc_cinfo; |
| 74 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 75 | enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI]; |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 76 | enum omap_dss_clk_source dispc_clk_source; |
| 77 | enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS]; |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 78 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 79 | u32 ctx[DSS_SZ_REGS / sizeof(u32)]; |
| 80 | } dss; |
| 81 | |
Taneja, Archit | 235e7db | 2011-03-14 23:28:21 -0500 | [diff] [blame] | 82 | static const char * const dss_generic_clk_source_names[] = { |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 83 | [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI_PLL_HSDIV_DISPC", |
| 84 | [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI_PLL_HSDIV_DSI", |
| 85 | [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCK", |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 86 | }; |
| 87 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 88 | static inline void dss_write_reg(const struct dss_reg idx, u32 val) |
| 89 | { |
| 90 | __raw_writel(val, dss.base + idx.idx); |
| 91 | } |
| 92 | |
| 93 | static inline u32 dss_read_reg(const struct dss_reg idx) |
| 94 | { |
| 95 | return __raw_readl(dss.base + idx.idx); |
| 96 | } |
| 97 | |
| 98 | #define SR(reg) \ |
| 99 | dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg) |
| 100 | #define RR(reg) \ |
| 101 | dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)]) |
| 102 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 103 | static void dss_save_context(void) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 104 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 105 | DSSDBG("dss_save_context\n"); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 106 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 107 | SR(CONTROL); |
| 108 | |
Tomi Valkeinen | 6ec549e | 2011-02-24 14:18:50 +0200 | [diff] [blame] | 109 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
| 110 | OMAP_DISPLAY_TYPE_SDI) { |
| 111 | SR(SDI_CONTROL); |
| 112 | SR(PLL_CONTROL); |
| 113 | } |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 114 | } |
| 115 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 116 | static void dss_restore_context(void) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 117 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 118 | DSSDBG("dss_restore_context\n"); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 119 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 120 | RR(CONTROL); |
| 121 | |
Tomi Valkeinen | 6ec549e | 2011-02-24 14:18:50 +0200 | [diff] [blame] | 122 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
| 123 | OMAP_DISPLAY_TYPE_SDI) { |
| 124 | RR(SDI_CONTROL); |
| 125 | RR(PLL_CONTROL); |
| 126 | } |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 127 | } |
| 128 | |
| 129 | #undef SR |
| 130 | #undef RR |
| 131 | |
| 132 | void dss_sdi_init(u8 datapairs) |
| 133 | { |
| 134 | u32 l; |
| 135 | |
| 136 | BUG_ON(datapairs > 3 || datapairs < 1); |
| 137 | |
| 138 | l = dss_read_reg(DSS_SDI_CONTROL); |
| 139 | l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ |
| 140 | l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ |
| 141 | l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ |
| 142 | dss_write_reg(DSS_SDI_CONTROL, l); |
| 143 | |
| 144 | l = dss_read_reg(DSS_PLL_CONTROL); |
| 145 | l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ |
| 146 | l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ |
| 147 | l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ |
| 148 | dss_write_reg(DSS_PLL_CONTROL, l); |
| 149 | } |
| 150 | |
| 151 | int dss_sdi_enable(void) |
| 152 | { |
| 153 | unsigned long timeout; |
| 154 | |
| 155 | dispc_pck_free_enable(1); |
| 156 | |
| 157 | /* Reset SDI PLL */ |
| 158 | REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ |
| 159 | udelay(1); /* wait 2x PCLK */ |
| 160 | |
| 161 | /* Lock SDI PLL */ |
| 162 | REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ |
| 163 | |
| 164 | /* Waiting for PLL lock request to complete */ |
| 165 | timeout = jiffies + msecs_to_jiffies(500); |
| 166 | while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) { |
| 167 | if (time_after_eq(jiffies, timeout)) { |
| 168 | DSSERR("PLL lock request timed out\n"); |
| 169 | goto err1; |
| 170 | } |
| 171 | } |
| 172 | |
| 173 | /* Clearing PLL_GO bit */ |
| 174 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); |
| 175 | |
| 176 | /* Waiting for PLL to lock */ |
| 177 | timeout = jiffies + msecs_to_jiffies(500); |
| 178 | while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) { |
| 179 | if (time_after_eq(jiffies, timeout)) { |
| 180 | DSSERR("PLL lock timed out\n"); |
| 181 | goto err1; |
| 182 | } |
| 183 | } |
| 184 | |
| 185 | dispc_lcd_enable_signal(1); |
| 186 | |
| 187 | /* Waiting for SDI reset to complete */ |
| 188 | timeout = jiffies + msecs_to_jiffies(500); |
| 189 | while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) { |
| 190 | if (time_after_eq(jiffies, timeout)) { |
| 191 | DSSERR("SDI reset timed out\n"); |
| 192 | goto err2; |
| 193 | } |
| 194 | } |
| 195 | |
| 196 | return 0; |
| 197 | |
| 198 | err2: |
| 199 | dispc_lcd_enable_signal(0); |
| 200 | err1: |
| 201 | /* Reset SDI PLL */ |
| 202 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ |
| 203 | |
| 204 | dispc_pck_free_enable(0); |
| 205 | |
| 206 | return -ETIMEDOUT; |
| 207 | } |
| 208 | |
| 209 | void dss_sdi_disable(void) |
| 210 | { |
| 211 | dispc_lcd_enable_signal(0); |
| 212 | |
| 213 | dispc_pck_free_enable(0); |
| 214 | |
| 215 | /* Reset SDI PLL */ |
| 216 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ |
| 217 | } |
| 218 | |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 219 | const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src) |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 220 | { |
Taneja, Archit | 235e7db | 2011-03-14 23:28:21 -0500 | [diff] [blame] | 221 | return dss_generic_clk_source_names[clk_src]; |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 222 | } |
| 223 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 224 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 225 | void dss_dump_clocks(struct seq_file *s) |
| 226 | { |
| 227 | unsigned long dpll4_ck_rate; |
| 228 | unsigned long dpll4_m4_ck_rate; |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 229 | const char *fclk_name, *fclk_real_name; |
| 230 | unsigned long fclk_rate; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 231 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 232 | if (dss_runtime_get()) |
| 233 | return; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 234 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 235 | seq_printf(s, "- DSS -\n"); |
| 236 | |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 237 | fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK); |
| 238 | fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 239 | fclk_rate = clk_get_rate(dss.dss_clk); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 240 | |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 241 | if (dss.dpll4_m4_ck) { |
| 242 | dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
| 243 | dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck); |
| 244 | |
| 245 | seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate); |
| 246 | |
Murthy, Raghuveer | 2de1108 | 2011-03-14 07:28:58 -0500 | [diff] [blame] | 247 | if (cpu_is_omap3630() || cpu_is_omap44xx()) |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 248 | seq_printf(s, "%s (%s) = %lu / %lu = %lu\n", |
| 249 | fclk_name, fclk_real_name, |
| 250 | dpll4_ck_rate, |
| 251 | dpll4_ck_rate / dpll4_m4_ck_rate, |
| 252 | fclk_rate); |
| 253 | else |
| 254 | seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n", |
| 255 | fclk_name, fclk_real_name, |
| 256 | dpll4_ck_rate, |
| 257 | dpll4_ck_rate / dpll4_m4_ck_rate, |
| 258 | fclk_rate); |
| 259 | } else { |
| 260 | seq_printf(s, "%s (%s) = %lu\n", |
| 261 | fclk_name, fclk_real_name, |
| 262 | fclk_rate); |
| 263 | } |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 264 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 265 | dss_runtime_put(); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 266 | } |
| 267 | |
| 268 | void dss_dump_regs(struct seq_file *s) |
| 269 | { |
| 270 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) |
| 271 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 272 | if (dss_runtime_get()) |
| 273 | return; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 274 | |
| 275 | DUMPREG(DSS_REVISION); |
| 276 | DUMPREG(DSS_SYSCONFIG); |
| 277 | DUMPREG(DSS_SYSSTATUS); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 278 | DUMPREG(DSS_CONTROL); |
Tomi Valkeinen | 6ec549e | 2011-02-24 14:18:50 +0200 | [diff] [blame] | 279 | |
| 280 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
| 281 | OMAP_DISPLAY_TYPE_SDI) { |
| 282 | DUMPREG(DSS_SDI_CONTROL); |
| 283 | DUMPREG(DSS_PLL_CONTROL); |
| 284 | DUMPREG(DSS_SDI_STATUS); |
| 285 | } |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 286 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 287 | dss_runtime_put(); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 288 | #undef DUMPREG |
| 289 | } |
| 290 | |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 291 | void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 292 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 293 | struct platform_device *dsidev; |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 294 | int b; |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 295 | u8 start, end; |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 296 | |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 297 | switch (clk_src) { |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 298 | case OMAP_DSS_CLK_SRC_FCK: |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 299 | b = 0; |
| 300 | break; |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 301 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 302 | b = 1; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 303 | dsidev = dsi_get_dsidev_from_id(0); |
| 304 | dsi_wait_pll_hsdiv_dispc_active(dsidev); |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 305 | break; |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 306 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: |
| 307 | b = 2; |
| 308 | dsidev = dsi_get_dsidev_from_id(1); |
| 309 | dsi_wait_pll_hsdiv_dispc_active(dsidev); |
| 310 | break; |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 311 | default: |
| 312 | BUG(); |
| 313 | } |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 314 | |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 315 | dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end); |
| 316 | |
| 317 | REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */ |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 318 | |
| 319 | dss.dispc_clk_source = clk_src; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 320 | } |
| 321 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 322 | void dss_select_dsi_clk_source(int dsi_module, |
| 323 | enum omap_dss_clk_source clk_src) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 324 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 325 | struct platform_device *dsidev; |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 326 | int b; |
| 327 | |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 328 | switch (clk_src) { |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 329 | case OMAP_DSS_CLK_SRC_FCK: |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 330 | b = 0; |
| 331 | break; |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 332 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI: |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 333 | BUG_ON(dsi_module != 0); |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 334 | b = 1; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 335 | dsidev = dsi_get_dsidev_from_id(0); |
| 336 | dsi_wait_pll_hsdiv_dsi_active(dsidev); |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 337 | break; |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 338 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI: |
| 339 | BUG_ON(dsi_module != 1); |
| 340 | b = 1; |
| 341 | dsidev = dsi_get_dsidev_from_id(1); |
| 342 | dsi_wait_pll_hsdiv_dsi_active(dsidev); |
| 343 | break; |
Taneja, Archit | 66534e8 | 2011-03-08 05:50:34 -0600 | [diff] [blame] | 344 | default: |
| 345 | BUG(); |
| 346 | } |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 347 | |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 348 | REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */ |
| 349 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 350 | dss.dsi_clk_source[dsi_module] = clk_src; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 351 | } |
| 352 | |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 353 | void dss_select_lcd_clk_source(enum omap_channel channel, |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 354 | enum omap_dss_clk_source clk_src) |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 355 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 356 | struct platform_device *dsidev; |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 357 | int b, ix, pos; |
| 358 | |
| 359 | if (!dss_has_feature(FEAT_LCD_CLK_SRC)) |
| 360 | return; |
| 361 | |
| 362 | switch (clk_src) { |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 363 | case OMAP_DSS_CLK_SRC_FCK: |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 364 | b = 0; |
| 365 | break; |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 366 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 367 | BUG_ON(channel != OMAP_DSS_CHANNEL_LCD); |
| 368 | b = 1; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 369 | dsidev = dsi_get_dsidev_from_id(0); |
| 370 | dsi_wait_pll_hsdiv_dispc_active(dsidev); |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 371 | break; |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 372 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: |
| 373 | BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2); |
| 374 | b = 1; |
| 375 | dsidev = dsi_get_dsidev_from_id(1); |
| 376 | dsi_wait_pll_hsdiv_dispc_active(dsidev); |
| 377 | break; |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 378 | default: |
| 379 | BUG(); |
| 380 | } |
| 381 | |
| 382 | pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 12; |
| 383 | REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */ |
| 384 | |
| 385 | ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1; |
| 386 | dss.lcd_clk_source[ix] = clk_src; |
| 387 | } |
| 388 | |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 389 | enum omap_dss_clk_source dss_get_dispc_clk_source(void) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 390 | { |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 391 | return dss.dispc_clk_source; |
| 392 | } |
| 393 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 394 | enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module) |
Tomi Valkeinen | 2f18c4d | 2010-01-08 18:00:36 +0200 | [diff] [blame] | 395 | { |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 396 | return dss.dsi_clk_source[dsi_module]; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 397 | } |
| 398 | |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 399 | enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel) |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 400 | { |
Archit Taneja | 89976f2 | 2011-03-31 13:23:35 +0530 | [diff] [blame] | 401 | if (dss_has_feature(FEAT_LCD_CLK_SRC)) { |
| 402 | int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1; |
| 403 | return dss.lcd_clk_source[ix]; |
| 404 | } else { |
| 405 | /* LCD_CLK source is the same as DISPC_FCLK source for |
| 406 | * OMAP2 and OMAP3 */ |
| 407 | return dss.dispc_clk_source; |
| 408 | } |
Taneja, Archit | ea75159 | 2011-03-08 05:50:35 -0600 | [diff] [blame] | 409 | } |
| 410 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 411 | /* calculate clock rates using dividers in cinfo */ |
| 412 | int dss_calc_clock_rates(struct dss_clock_info *cinfo) |
| 413 | { |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 414 | if (dss.dpll4_m4_ck) { |
| 415 | unsigned long prate; |
Murthy, Raghuveer | 2de1108 | 2011-03-14 07:28:58 -0500 | [diff] [blame] | 416 | u16 fck_div_max = 16; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 417 | |
Murthy, Raghuveer | 2de1108 | 2011-03-14 07:28:58 -0500 | [diff] [blame] | 418 | if (cpu_is_omap3630() || cpu_is_omap44xx()) |
| 419 | fck_div_max = 32; |
| 420 | |
| 421 | if (cinfo->fck_div > fck_div_max || cinfo->fck_div == 0) |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 422 | return -EINVAL; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 423 | |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 424 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 425 | |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 426 | cinfo->fck = prate / cinfo->fck_div; |
| 427 | } else { |
| 428 | if (cinfo->fck_div != 0) |
| 429 | return -EINVAL; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 430 | cinfo->fck = clk_get_rate(dss.dss_clk); |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 431 | } |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 432 | |
| 433 | return 0; |
| 434 | } |
| 435 | |
| 436 | int dss_set_clock_div(struct dss_clock_info *cinfo) |
| 437 | { |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 438 | if (dss.dpll4_m4_ck) { |
| 439 | unsigned long prate; |
| 440 | int r; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 441 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 442 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
| 443 | DSSDBG("dpll4_m4 = %ld\n", prate); |
| 444 | |
| 445 | r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div); |
| 446 | if (r) |
| 447 | return r; |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 448 | } else { |
| 449 | if (cinfo->fck_div != 0) |
| 450 | return -EINVAL; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 451 | } |
| 452 | |
| 453 | DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div); |
| 454 | |
| 455 | return 0; |
| 456 | } |
| 457 | |
| 458 | int dss_get_clock_div(struct dss_clock_info *cinfo) |
| 459 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 460 | cinfo->fck = clk_get_rate(dss.dss_clk); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 461 | |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 462 | if (dss.dpll4_m4_ck) { |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 463 | unsigned long prate; |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 464 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 465 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 466 | |
Murthy, Raghuveer | 2de1108 | 2011-03-14 07:28:58 -0500 | [diff] [blame] | 467 | if (cpu_is_omap3630() || cpu_is_omap44xx()) |
Kishore Y | ac01bb7 | 2010-04-25 16:27:19 +0530 | [diff] [blame] | 468 | cinfo->fck_div = prate / (cinfo->fck); |
| 469 | else |
| 470 | cinfo->fck_div = prate / (cinfo->fck / 2); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 471 | } else { |
| 472 | cinfo->fck_div = 0; |
| 473 | } |
| 474 | |
| 475 | return 0; |
| 476 | } |
| 477 | |
| 478 | unsigned long dss_get_dpll4_rate(void) |
| 479 | { |
Tomi Valkeinen | 0acf659 | 2011-03-14 07:28:57 -0500 | [diff] [blame] | 480 | if (dss.dpll4_m4_ck) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 481 | return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
| 482 | else |
| 483 | return 0; |
| 484 | } |
| 485 | |
| 486 | int dss_calc_clock_div(bool is_tft, unsigned long req_pck, |
| 487 | struct dss_clock_info *dss_cinfo, |
| 488 | struct dispc_clock_info *dispc_cinfo) |
| 489 | { |
| 490 | unsigned long prate; |
| 491 | struct dss_clock_info best_dss; |
| 492 | struct dispc_clock_info best_dispc; |
| 493 | |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 494 | unsigned long fck, max_dss_fck; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 495 | |
Murthy, Raghuveer | 2de1108 | 2011-03-14 07:28:58 -0500 | [diff] [blame] | 496 | u16 fck_div, fck_div_max = 16; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 497 | |
| 498 | int match = 0; |
| 499 | int min_fck_per_pck; |
| 500 | |
| 501 | prate = dss_get_dpll4_rate(); |
| 502 | |
Taneja, Archit | 31ef823 | 2011-03-14 23:28:22 -0500 | [diff] [blame] | 503 | max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 504 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 505 | fck = clk_get_rate(dss.dss_clk); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 506 | if (req_pck == dss.cache_req_pck && |
| 507 | ((cpu_is_omap34xx() && prate == dss.cache_prate) || |
| 508 | dss.cache_dss_cinfo.fck == fck)) { |
| 509 | DSSDBG("dispc clock info found from cache.\n"); |
| 510 | *dss_cinfo = dss.cache_dss_cinfo; |
| 511 | *dispc_cinfo = dss.cache_dispc_cinfo; |
| 512 | return 0; |
| 513 | } |
| 514 | |
| 515 | min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; |
| 516 | |
| 517 | if (min_fck_per_pck && |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 518 | req_pck * min_fck_per_pck > max_dss_fck) { |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 519 | DSSERR("Requested pixel clock not possible with the current " |
| 520 | "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " |
| 521 | "the constraint off.\n"); |
| 522 | min_fck_per_pck = 0; |
| 523 | } |
| 524 | |
| 525 | retry: |
| 526 | memset(&best_dss, 0, sizeof(best_dss)); |
| 527 | memset(&best_dispc, 0, sizeof(best_dispc)); |
| 528 | |
Murthy, Raghuveer | 2de1108 | 2011-03-14 07:28:58 -0500 | [diff] [blame] | 529 | if (dss.dpll4_m4_ck == NULL) { |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 530 | struct dispc_clock_info cur_dispc; |
| 531 | /* XXX can we change the clock on omap2? */ |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 532 | fck = clk_get_rate(dss.dss_clk); |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 533 | fck_div = 1; |
| 534 | |
| 535 | dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); |
| 536 | match = 1; |
| 537 | |
| 538 | best_dss.fck = fck; |
| 539 | best_dss.fck_div = fck_div; |
| 540 | |
| 541 | best_dispc = cur_dispc; |
| 542 | |
| 543 | goto found; |
Murthy, Raghuveer | 2de1108 | 2011-03-14 07:28:58 -0500 | [diff] [blame] | 544 | } else { |
| 545 | if (cpu_is_omap3630() || cpu_is_omap44xx()) |
| 546 | fck_div_max = 32; |
| 547 | |
| 548 | for (fck_div = fck_div_max; fck_div > 0; --fck_div) { |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 549 | struct dispc_clock_info cur_dispc; |
| 550 | |
Murthy, Raghuveer | 2de1108 | 2011-03-14 07:28:58 -0500 | [diff] [blame] | 551 | if (fck_div_max == 32) |
Kishore Y | ac01bb7 | 2010-04-25 16:27:19 +0530 | [diff] [blame] | 552 | fck = prate / fck_div; |
| 553 | else |
| 554 | fck = prate / fck_div * 2; |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 555 | |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 556 | if (fck > max_dss_fck) |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 557 | continue; |
| 558 | |
| 559 | if (min_fck_per_pck && |
| 560 | fck < req_pck * min_fck_per_pck) |
| 561 | continue; |
| 562 | |
| 563 | match = 1; |
| 564 | |
| 565 | dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); |
| 566 | |
| 567 | if (abs(cur_dispc.pck - req_pck) < |
| 568 | abs(best_dispc.pck - req_pck)) { |
| 569 | |
| 570 | best_dss.fck = fck; |
| 571 | best_dss.fck_div = fck_div; |
| 572 | |
| 573 | best_dispc = cur_dispc; |
| 574 | |
| 575 | if (cur_dispc.pck == req_pck) |
| 576 | goto found; |
| 577 | } |
| 578 | } |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 579 | } |
| 580 | |
| 581 | found: |
| 582 | if (!match) { |
| 583 | if (min_fck_per_pck) { |
| 584 | DSSERR("Could not find suitable clock settings.\n" |
| 585 | "Turning FCK/PCK constraint off and" |
| 586 | "trying again.\n"); |
| 587 | min_fck_per_pck = 0; |
| 588 | goto retry; |
| 589 | } |
| 590 | |
| 591 | DSSERR("Could not find suitable clock settings.\n"); |
| 592 | |
| 593 | return -EINVAL; |
| 594 | } |
| 595 | |
| 596 | if (dss_cinfo) |
| 597 | *dss_cinfo = best_dss; |
| 598 | if (dispc_cinfo) |
| 599 | *dispc_cinfo = best_dispc; |
| 600 | |
| 601 | dss.cache_req_pck = req_pck; |
| 602 | dss.cache_prate = prate; |
| 603 | dss.cache_dss_cinfo = best_dss; |
| 604 | dss.cache_dispc_cinfo = best_dispc; |
| 605 | |
| 606 | return 0; |
| 607 | } |
| 608 | |
Tomi Valkeinen | 559d670 | 2009-11-03 11:23:50 +0200 | [diff] [blame] | 609 | void dss_set_venc_output(enum omap_dss_venc_type type) |
| 610 | { |
| 611 | int l = 0; |
| 612 | |
| 613 | if (type == OMAP_DSS_VENC_TYPE_COMPOSITE) |
| 614 | l = 0; |
| 615 | else if (type == OMAP_DSS_VENC_TYPE_SVIDEO) |
| 616 | l = 1; |
| 617 | else |
| 618 | BUG(); |
| 619 | |
| 620 | /* venc out selection. 0 = comp, 1 = svideo */ |
| 621 | REG_FLD_MOD(DSS_CONTROL, l, 6, 6); |
| 622 | } |
| 623 | |
| 624 | void dss_set_dac_pwrdn_bgz(bool enable) |
| 625 | { |
| 626 | REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ |
| 627 | } |
| 628 | |
Mythri P K | 7ed024a | 2011-03-09 16:31:38 +0530 | [diff] [blame] | 629 | void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi) |
| 630 | { |
| 631 | REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15); /* VENC_HDMI_SWITCH */ |
| 632 | } |
| 633 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 634 | /* CONTEXT */ |
Tomi Valkeinen | aac927c | 2011-05-23 15:46:54 +0300 | [diff] [blame] | 635 | static void dss_init_ctx_loss_count(void) |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 636 | { |
Tomi Valkeinen | aac927c | 2011-05-23 15:46:54 +0300 | [diff] [blame] | 637 | struct device *dev = &dss.pdev->dev; |
| 638 | struct omap_display_platform_data *pdata = dev->platform_data; |
| 639 | struct omap_dss_board_info *board_data = pdata->board_data; |
| 640 | int cnt = 0; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 641 | |
Tomi Valkeinen | aac927c | 2011-05-23 15:46:54 +0300 | [diff] [blame] | 642 | /* |
| 643 | * get_context_loss_count returns negative on error. We'll ignore the |
| 644 | * error and store the error to ctx_loss_cnt, which will cause |
| 645 | * dss_need_ctx_restore() call to return true. |
| 646 | */ |
| 647 | |
| 648 | if (board_data->get_context_loss_count) |
| 649 | cnt = board_data->get_context_loss_count(dev); |
| 650 | |
| 651 | WARN_ON(cnt < 0); |
| 652 | |
| 653 | dss.ctx_loss_cnt = cnt; |
| 654 | |
| 655 | DSSDBG("initial ctx_loss_cnt %u\n", cnt); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 656 | } |
| 657 | |
Tomi Valkeinen | aac927c | 2011-05-23 15:46:54 +0300 | [diff] [blame] | 658 | static bool dss_need_ctx_restore(void) |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 659 | { |
Tomi Valkeinen | aac927c | 2011-05-23 15:46:54 +0300 | [diff] [blame] | 660 | struct device *dev = &dss.pdev->dev; |
| 661 | struct omap_display_platform_data *pdata = dev->platform_data; |
| 662 | struct omap_dss_board_info *board_data = pdata->board_data; |
| 663 | int cnt; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 664 | |
Tomi Valkeinen | aac927c | 2011-05-23 15:46:54 +0300 | [diff] [blame] | 665 | /* |
| 666 | * If get_context_loss_count is not available, assume that we need |
| 667 | * context restore always. |
| 668 | */ |
| 669 | if (!board_data->get_context_loss_count) |
| 670 | return true; |
| 671 | |
| 672 | cnt = board_data->get_context_loss_count(dev); |
| 673 | if (cnt < 0) { |
| 674 | dev_err(dev, "getting context loss count failed, will force " |
| 675 | "context restore\n"); |
| 676 | dss.ctx_loss_cnt = cnt; |
| 677 | return true; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 678 | } |
Tomi Valkeinen | aac927c | 2011-05-23 15:46:54 +0300 | [diff] [blame] | 679 | |
| 680 | if (cnt == dss.ctx_loss_cnt) |
| 681 | return false; |
| 682 | |
| 683 | DSSDBG("ctx_loss_cnt %d -> %d\n", dss.ctx_loss_cnt, cnt); |
| 684 | dss.ctx_loss_cnt = cnt; |
| 685 | |
| 686 | return true; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 687 | } |
| 688 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 689 | static int dss_get_clocks(void) |
| 690 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 691 | struct clk *clk; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 692 | int r; |
| 693 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 694 | clk = clk_get(&dss.pdev->dev, "fck"); |
| 695 | if (IS_ERR(clk)) { |
| 696 | DSSERR("can't get clock fck\n"); |
| 697 | r = PTR_ERR(clk); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 698 | goto err; |
Semwal, Sumit | a1a0dcc | 2011-03-01 02:42:14 -0600 | [diff] [blame] | 699 | } |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 700 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 701 | dss.dss_clk = clk; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 702 | |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 703 | if (cpu_is_omap34xx()) { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 704 | clk = clk_get(NULL, "dpll4_m4_ck"); |
| 705 | if (IS_ERR(clk)) { |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 706 | DSSERR("Failed to get dpll4_m4_ck\n"); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 707 | r = PTR_ERR(clk); |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 708 | goto err; |
| 709 | } |
| 710 | } else if (cpu_is_omap44xx()) { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 711 | clk = clk_get(NULL, "dpll_per_m5x2_ck"); |
| 712 | if (IS_ERR(clk)) { |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 713 | DSSERR("Failed to get dpll_per_m5x2_ck\n"); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 714 | r = PTR_ERR(clk); |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 715 | goto err; |
| 716 | } |
| 717 | } else { /* omap24xx */ |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 718 | clk = NULL; |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 719 | } |
| 720 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 721 | dss.dpll4_m4_ck = clk; |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 722 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 723 | return 0; |
| 724 | |
| 725 | err: |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 726 | if (dss.dss_clk) |
| 727 | clk_put(dss.dss_clk); |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 728 | if (dss.dpll4_m4_ck) |
| 729 | clk_put(dss.dpll4_m4_ck); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 730 | |
| 731 | return r; |
| 732 | } |
| 733 | |
| 734 | static void dss_put_clocks(void) |
| 735 | { |
Tomi Valkeinen | 94c042c | 2011-05-16 13:43:04 +0300 | [diff] [blame] | 736 | if (dss.dpll4_m4_ck) |
| 737 | clk_put(dss.dpll4_m4_ck); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 738 | clk_put(dss.dss_clk); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 739 | } |
| 740 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 741 | int dss_runtime_get(void) |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 742 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 743 | int r; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 744 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 745 | DSSDBG("dss_runtime_get\n"); |
| 746 | |
| 747 | r = pm_runtime_get_sync(&dss.pdev->dev); |
| 748 | WARN_ON(r < 0); |
| 749 | return r < 0 ? r : 0; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 750 | } |
| 751 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 752 | void dss_runtime_put(void) |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 753 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 754 | int r; |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 755 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 756 | DSSDBG("dss_runtime_put\n"); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 757 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 758 | r = pm_runtime_put(&dss.pdev->dev); |
| 759 | WARN_ON(r < 0); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 760 | } |
| 761 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 762 | /* DEBUGFS */ |
| 763 | #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) |
| 764 | void dss_debug_dump_clocks(struct seq_file *s) |
| 765 | { |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 766 | dss_dump_clocks(s); |
| 767 | dispc_dump_clocks(s); |
| 768 | #ifdef CONFIG_OMAP2_DSS_DSI |
| 769 | dsi_dump_clocks(s); |
| 770 | #endif |
| 771 | } |
| 772 | #endif |
| 773 | |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 774 | /* DSS HW IP initialisation */ |
| 775 | static int omap_dsshw_probe(struct platform_device *pdev) |
| 776 | { |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 777 | struct resource *dss_mem; |
| 778 | u32 rev; |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 779 | int r; |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 780 | |
| 781 | dss.pdev = pdev; |
| 782 | |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 783 | dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); |
| 784 | if (!dss_mem) { |
| 785 | DSSERR("can't get IORESOURCE_MEM DSS\n"); |
| 786 | r = -EINVAL; |
| 787 | goto err_ioremap; |
| 788 | } |
| 789 | dss.base = ioremap(dss_mem->start, resource_size(dss_mem)); |
| 790 | if (!dss.base) { |
| 791 | DSSERR("can't ioremap DSS\n"); |
| 792 | r = -ENOMEM; |
| 793 | goto err_ioremap; |
| 794 | } |
| 795 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 796 | r = dss_get_clocks(); |
| 797 | if (r) |
| 798 | goto err_clocks; |
| 799 | |
Tomi Valkeinen | aac927c | 2011-05-23 15:46:54 +0300 | [diff] [blame] | 800 | dss_init_ctx_loss_count(); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 801 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 802 | pm_runtime_enable(&pdev->dev); |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 803 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 804 | r = dss_runtime_get(); |
| 805 | if (r) |
| 806 | goto err_runtime_get; |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 807 | |
| 808 | /* Select DPLL */ |
| 809 | REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); |
| 810 | |
| 811 | #ifdef CONFIG_OMAP2_DSS_VENC |
| 812 | REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ |
| 813 | REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ |
| 814 | REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ |
| 815 | #endif |
| 816 | dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; |
| 817 | dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; |
| 818 | dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK; |
| 819 | dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; |
| 820 | dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 821 | |
Tomi Valkeinen | 587b5e8 | 2011-03-02 12:47:54 +0200 | [diff] [blame] | 822 | r = dpi_init(); |
| 823 | if (r) { |
| 824 | DSSERR("Failed to initialize DPI\n"); |
| 825 | goto err_dpi; |
| 826 | } |
| 827 | |
| 828 | r = sdi_init(); |
| 829 | if (r) { |
| 830 | DSSERR("Failed to initialize SDI\n"); |
| 831 | goto err_sdi; |
| 832 | } |
| 833 | |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 834 | rev = dss_read_reg(DSS_REVISION); |
| 835 | printk(KERN_INFO "OMAP DSS rev %d.%d\n", |
| 836 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
| 837 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 838 | dss_runtime_put(); |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 839 | |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 840 | return 0; |
Tomi Valkeinen | 587b5e8 | 2011-03-02 12:47:54 +0200 | [diff] [blame] | 841 | err_sdi: |
| 842 | dpi_exit(); |
| 843 | err_dpi: |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 844 | dss_runtime_put(); |
| 845 | err_runtime_get: |
| 846 | pm_runtime_disable(&pdev->dev); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 847 | dss_put_clocks(); |
| 848 | err_clocks: |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 849 | iounmap(dss.base); |
| 850 | err_ioremap: |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 851 | return r; |
| 852 | } |
| 853 | |
| 854 | static int omap_dsshw_remove(struct platform_device *pdev) |
| 855 | { |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 856 | dpi_exit(); |
| 857 | sdi_exit(); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 858 | |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 859 | iounmap(dss.base); |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 860 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 861 | pm_runtime_disable(&pdev->dev); |
Senthilvadivu Guruswamy | 8b9cb3a | 2011-01-24 06:21:58 +0000 | [diff] [blame] | 862 | |
| 863 | dss_put_clocks(); |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 864 | |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 865 | return 0; |
| 866 | } |
| 867 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 868 | static int dss_runtime_suspend(struct device *dev) |
| 869 | { |
| 870 | dss_save_context(); |
| 871 | clk_disable(dss.dss_clk); |
| 872 | return 0; |
| 873 | } |
| 874 | |
| 875 | static int dss_runtime_resume(struct device *dev) |
| 876 | { |
| 877 | clk_enable(dss.dss_clk); |
| 878 | if (dss_need_ctx_restore()) |
| 879 | dss_restore_context(); |
| 880 | return 0; |
| 881 | } |
| 882 | |
| 883 | static const struct dev_pm_ops dss_pm_ops = { |
| 884 | .runtime_suspend = dss_runtime_suspend, |
| 885 | .runtime_resume = dss_runtime_resume, |
| 886 | }; |
| 887 | |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 888 | static struct platform_driver omap_dsshw_driver = { |
| 889 | .probe = omap_dsshw_probe, |
| 890 | .remove = omap_dsshw_remove, |
| 891 | .driver = { |
| 892 | .name = "omapdss_dss", |
| 893 | .owner = THIS_MODULE, |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame^] | 894 | .pm = &dss_pm_ops, |
Senthilvadivu Guruswamy | 96c401b | 2011-01-24 06:21:57 +0000 | [diff] [blame] | 895 | }, |
| 896 | }; |
| 897 | |
| 898 | int dss_init_platform_driver(void) |
| 899 | { |
| 900 | return platform_driver_register(&omap_dsshw_driver); |
| 901 | } |
| 902 | |
| 903 | void dss_uninit_platform_driver(void) |
| 904 | { |
| 905 | return platform_driver_unregister(&omap_dsshw_driver); |
| 906 | } |