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Bryan Wu1394f032007-05-06 14:50:22 -07001#
2# For a description of the syntax of this configuration file,
3# see Documentation/kbuild/kconfig-language.txt.
4#
5
Mike Frysinger53f8a252007-11-15 15:48:01 +08006mainmenu "Blackfin Kernel Configuration"
Bryan Wu1394f032007-05-06 14:50:22 -07007
8config MMU
9 bool
10 default n
11
12config FPU
13 bool
14 default n
15
16config RWSEM_GENERIC_SPINLOCK
17 bool
18 default y
19
20config RWSEM_XCHGADD_ALGORITHM
21 bool
22 default n
23
24config BLACKFIN
25 bool
26 default y
Sam Ravnborgec7748b2008-02-09 10:46:40 +010027 select HAVE_IDE
Mathieu Desnoyers42d4b832008-02-02 15:10:34 -050028 select HAVE_OPROFILE
Michael Hennericha4f0b32c2008-11-18 17:48:22 +080029 select ARCH_WANT_OPTIONAL_GPIOLIB
Bryan Wu1394f032007-05-06 14:50:22 -070030
Aubrey Lie3defff2007-05-21 18:09:11 +080031config ZONE_DMA
32 bool
33 default y
34
Bryan Wu1394f032007-05-06 14:50:22 -070035config GENERIC_FIND_NEXT_BIT
36 bool
37 default y
38
39config GENERIC_HWEIGHT
40 bool
41 default y
42
43config GENERIC_HARDIRQS
44 bool
45 default y
46
47config GENERIC_IRQ_PROBE
Mike Frysingere4e9a7a2007-11-15 20:39:34 +080048 bool
Bryan Wu1394f032007-05-06 14:50:22 -070049 default y
50
Michael Hennerichb2d15832007-07-24 15:46:36 +080051config GENERIC_GPIO
Bryan Wu1394f032007-05-06 14:50:22 -070052 bool
53 default y
54
55config FORCE_MAX_ZONEORDER
56 int
57 default "14"
58
59config GENERIC_CALIBRATE_DELAY
60 bool
61 default y
62
Bryan Wu1394f032007-05-06 14:50:22 -070063source "init/Kconfig"
Matt Helsleydc52ddc2008-10-18 20:27:21 -070064
Bryan Wu1394f032007-05-06 14:50:22 -070065source "kernel/Kconfig.preempt"
66
Matt Helsleydc52ddc2008-10-18 20:27:21 -070067source "kernel/Kconfig.freezer"
68
Bryan Wu1394f032007-05-06 14:50:22 -070069menu "Blackfin Processor Options"
70
71comment "Processor and Board Settings"
72
73choice
74 prompt "CPU"
75 default BF533
76
Bryan Wu2f6f4bc2008-11-18 17:48:21 +080077config BF512
78 bool "BF512"
79 help
80 BF512 Processor Support.
81
82config BF514
83 bool "BF514"
84 help
85 BF514 Processor Support.
86
87config BF516
88 bool "BF516"
89 help
90 BF516 Processor Support.
91
92config BF518
93 bool "BF518"
94 help
95 BF518 Processor Support.
96
Michael Hennerich59003142007-10-21 16:54:27 +080097config BF522
98 bool "BF522"
99 help
100 BF522 Processor Support.
101
Mike Frysinger1545a112007-12-24 16:54:48 +0800102config BF523
103 bool "BF523"
104 help
105 BF523 Processor Support.
106
107config BF524
108 bool "BF524"
109 help
110 BF524 Processor Support.
111
Michael Hennerich59003142007-10-21 16:54:27 +0800112config BF525
113 bool "BF525"
114 help
115 BF525 Processor Support.
116
Mike Frysinger1545a112007-12-24 16:54:48 +0800117config BF526
118 bool "BF526"
119 help
120 BF526 Processor Support.
121
Michael Hennerich59003142007-10-21 16:54:27 +0800122config BF527
123 bool "BF527"
124 help
125 BF527 Processor Support.
126
Bryan Wu1394f032007-05-06 14:50:22 -0700127config BF531
128 bool "BF531"
129 help
130 BF531 Processor Support.
131
132config BF532
133 bool "BF532"
134 help
135 BF532 Processor Support.
136
137config BF533
138 bool "BF533"
139 help
140 BF533 Processor Support.
141
142config BF534
143 bool "BF534"
144 help
145 BF534 Processor Support.
146
147config BF536
148 bool "BF536"
149 help
150 BF536 Processor Support.
151
152config BF537
153 bool "BF537"
154 help
155 BF537 Processor Support.
156
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800157config BF538
158 bool "BF538"
159 help
160 BF538 Processor Support.
161
162config BF539
163 bool "BF539"
164 help
165 BF539 Processor Support.
166
Roy Huang24a07a12007-07-12 22:41:45 +0800167config BF542
168 bool "BF542"
169 help
170 BF542 Processor Support.
171
Mike Frysinger2f89c062009-02-04 16:49:45 +0800172config BF542M
173 bool "BF542m"
174 help
175 BF542 Processor Support.
176
Roy Huang24a07a12007-07-12 22:41:45 +0800177config BF544
178 bool "BF544"
179 help
180 BF544 Processor Support.
181
Mike Frysinger2f89c062009-02-04 16:49:45 +0800182config BF544M
183 bool "BF544m"
184 help
185 BF544 Processor Support.
186
Mike Frysinger7c7fd172007-11-15 21:10:21 +0800187config BF547
188 bool "BF547"
189 help
190 BF547 Processor Support.
191
Mike Frysinger2f89c062009-02-04 16:49:45 +0800192config BF547M
193 bool "BF547m"
194 help
195 BF547 Processor Support.
196
Roy Huang24a07a12007-07-12 22:41:45 +0800197config BF548
198 bool "BF548"
199 help
200 BF548 Processor Support.
201
Mike Frysinger2f89c062009-02-04 16:49:45 +0800202config BF548M
203 bool "BF548m"
204 help
205 BF548 Processor Support.
206
Roy Huang24a07a12007-07-12 22:41:45 +0800207config BF549
208 bool "BF549"
209 help
210 BF549 Processor Support.
211
Mike Frysinger2f89c062009-02-04 16:49:45 +0800212config BF549M
213 bool "BF549m"
214 help
215 BF549 Processor Support.
216
Bryan Wu1394f032007-05-06 14:50:22 -0700217config BF561
218 bool "BF561"
219 help
Mike Frysingercd88b4d2008-10-09 12:03:22 +0800220 BF561 Processor Support.
Bryan Wu1394f032007-05-06 14:50:22 -0700221
222endchoice
223
Graf Yang46fa5ee2009-01-07 23:14:39 +0800224config SMP
225 depends on BF561
226 bool "Symmetric multi-processing support"
227 ---help---
228 This enables support for systems with more than one CPU,
229 like the dual core BF561. If you have a system with only one
230 CPU, say N. If you have a system with more than one CPU, say Y.
231
232 If you don't know what to do here, say N.
233
234config NR_CPUS
235 int
236 depends on SMP
237 default 2 if BF561
238
239config IRQ_PER_CPU
240 bool
241 depends on SMP
242 default y
243
Mike Frysinger0c0497c2008-10-09 17:32:28 +0800244config BF_REV_MIN
245 int
Mike Frysinger2f89c062009-02-04 16:49:45 +0800246 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
Mike Frysinger0c0497c2008-10-09 17:32:28 +0800247 default 2 if (BF537 || BF536 || BF534)
Mike Frysinger2f89c062009-02-04 16:49:45 +0800248 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800249 default 4 if (BF538 || BF539)
Mike Frysinger0c0497c2008-10-09 17:32:28 +0800250
251config BF_REV_MAX
252 int
Mike Frysinger2f89c062009-02-04 16:49:45 +0800253 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
254 default 3 if (BF537 || BF536 || BF534 || BF54xM)
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800255 default 5 if (BF561 || BF538 || BF539)
Mike Frysinger0c0497c2008-10-09 17:32:28 +0800256 default 6 if (BF533 || BF532 || BF531)
257
Bryan Wu1394f032007-05-06 14:50:22 -0700258choice
259 prompt "Silicon Rev"
Mike Frysingerf8b55652009-04-13 21:58:34 +0000260 default BF_REV_0_0 if (BF51x || BF52x)
261 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
Mike Frysinger2f89c062009-02-04 16:49:45 +0800262 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
Roy Huang24a07a12007-07-12 22:41:45 +0800263
264config BF_REV_0_0
265 bool "0.0"
Mike Frysinger2f89c062009-02-04 16:49:45 +0800266 depends on (BF51x || BF52x || (BF54x && !BF54xM))
Michael Hennerich59003142007-10-21 16:54:27 +0800267
268config BF_REV_0_1
Mike Frysingerd07f4382007-11-15 15:49:17 +0800269 bool "0.1"
Mike Frysinger2f89c062009-02-04 16:49:45 +0800270 depends on (BF52x || (BF54x && !BF54xM))
Bryan Wu1394f032007-05-06 14:50:22 -0700271
272config BF_REV_0_2
273 bool "0.2"
Mike Frysinger2f89c062009-02-04 16:49:45 +0800274 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
Bryan Wu1394f032007-05-06 14:50:22 -0700275
276config BF_REV_0_3
277 bool "0.3"
Mike Frysinger2f89c062009-02-04 16:49:45 +0800278 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
Bryan Wu1394f032007-05-06 14:50:22 -0700279
280config BF_REV_0_4
281 bool "0.4"
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800282 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
Bryan Wu1394f032007-05-06 14:50:22 -0700283
284config BF_REV_0_5
285 bool "0.5"
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800286 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
Bryan Wu1394f032007-05-06 14:50:22 -0700287
Mike Frysinger49f72532008-10-09 12:06:27 +0800288config BF_REV_0_6
289 bool "0.6"
290 depends on (BF533 || BF532 || BF531)
291
Jie Zhangde3025f2007-06-25 18:04:12 +0800292config BF_REV_ANY
293 bool "any"
294
295config BF_REV_NONE
296 bool "none"
297
Bryan Wu1394f032007-05-06 14:50:22 -0700298endchoice
299
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800300config BF51x
301 bool
302 depends on (BF512 || BF514 || BF516 || BF518)
303 default y
304
Michael Hennerich59003142007-10-21 16:54:27 +0800305config BF52x
306 bool
Mike Frysinger1545a112007-12-24 16:54:48 +0800307 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
Michael Hennerich59003142007-10-21 16:54:27 +0800308 default y
309
Roy Huang24a07a12007-07-12 22:41:45 +0800310config BF53x
311 bool
312 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
313 default y
314
Mike Frysinger2f89c062009-02-04 16:49:45 +0800315config BF54xM
316 bool
317 depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
318 default y
319
Roy Huang24a07a12007-07-12 22:41:45 +0800320config BF54x
321 bool
Mike Frysinger2f89c062009-02-04 16:49:45 +0800322 depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
Roy Huang24a07a12007-07-12 22:41:45 +0800323 default y
324
Bryan Wu1394f032007-05-06 14:50:22 -0700325config MEM_GENERIC_BOARD
326 bool
327 depends on GENERIC_BOARD
328 default y
329
330config MEM_MT48LC64M4A2FB_7E
331 bool
332 depends on (BFIN533_STAMP)
333 default y
334
335config MEM_MT48LC16M16A2TG_75
336 bool
337 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
Javier Herreroab472a02007-10-29 16:14:44 +0800338 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
Michael Hennerich9db144f2008-07-19 17:16:07 +0800339 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
Bryan Wu1394f032007-05-06 14:50:22 -0700340 default y
341
342config MEM_MT48LC32M8A2_75
343 bool
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800344 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
Bryan Wu1394f032007-05-06 14:50:22 -0700345 default y
346
347config MEM_MT48LC8M32B2B5_7
348 bool
349 depends on (BFIN561_BLUETECHNIX_CM)
350 default y
351
Michael Hennerich59003142007-10-21 16:54:27 +0800352config MEM_MT48LC32M16A2TG_75
353 bool
Michael Hennerich8cc71172008-10-13 14:45:06 +0800354 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
Michael Hennerich59003142007-10-21 16:54:27 +0800355 default y
356
Sonic Zhang49345402009-01-07 23:14:38 +0800357config MEM_MT48LC32M8A2_75
358 bool
359 depends on (BFIN518F_EZBRD)
360 default y
361
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800362source "arch/blackfin/mach-bf518/Kconfig"
Michael Hennerich59003142007-10-21 16:54:27 +0800363source "arch/blackfin/mach-bf527/Kconfig"
Bryan Wu1394f032007-05-06 14:50:22 -0700364source "arch/blackfin/mach-bf533/Kconfig"
365source "arch/blackfin/mach-bf561/Kconfig"
366source "arch/blackfin/mach-bf537/Kconfig"
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800367source "arch/blackfin/mach-bf538/Kconfig"
Roy Huang24a07a12007-07-12 22:41:45 +0800368source "arch/blackfin/mach-bf548/Kconfig"
Bryan Wu1394f032007-05-06 14:50:22 -0700369
370menu "Board customizations"
371
372config CMDLINE_BOOL
373 bool "Default bootloader kernel arguments"
374
375config CMDLINE
376 string "Initial kernel command string"
377 depends on CMDLINE_BOOL
378 default "console=ttyBF0,57600"
379 help
380 If you don't have a boot loader capable of passing a command line string
381 to the kernel, you may specify one here. As a minimum, you should specify
382 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
383
Mike Frysinger5f004c22008-04-25 02:11:24 +0800384config BOOT_LOAD
385 hex "Kernel load address for booting"
386 default "0x1000"
387 range 0x1000 0x20000000
388 help
389 This option allows you to set the load address of the kernel.
390 This can be useful if you are on a board which has a small amount
391 of memory or you wish to reserve some memory at the beginning of
392 the address space.
393
394 Note that you need to keep this value above 4k (0x1000) as this
395 memory region is used to capture NULL pointer references as well
396 as some core kernel functions.
397
Michael Hennerich8cc71172008-10-13 14:45:06 +0800398config ROM_BASE
399 hex "Kernel ROM Base"
Mike Frysinger86249912008-11-18 17:48:22 +0800400 depends on ROMKERNEL
Michael Hennerich8cc71172008-10-13 14:45:06 +0800401 default "0x20040000"
402 range 0x20000000 0x20400000 if !(BF54x || BF561)
403 range 0x20000000 0x30000000 if (BF54x || BF561)
404 help
405
Robin Getzf16295e2007-08-03 18:07:17 +0800406comment "Clock/PLL Setup"
Bryan Wu1394f032007-05-06 14:50:22 -0700407
408config CLKIN_HZ
Sonic Zhang2fb6cb42008-04-25 04:39:28 +0800409 int "Frequency of the crystal on the board in Hz"
Bryan Wu1394f032007-05-06 14:50:22 -0700410 default "11059200" if BFIN533_STAMP
411 default "27000000" if BFIN533_EZKIT
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800412 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
Bryan Wu1394f032007-05-06 14:50:22 -0700413 default "30000000" if BFIN561_EZKIT
414 default "24576000" if PNAV10
Mike Frysinger5d1617b2008-04-24 05:03:26 +0800415 default "10000000" if BFIN532_IP0X
Bryan Wu1394f032007-05-06 14:50:22 -0700416 help
417 The frequency of CLKIN crystal oscillator on the board in Hz.
Sonic Zhang2fb6cb42008-04-25 04:39:28 +0800418 Warning: This value should match the crystal on the board. Otherwise,
419 peripherals won't work properly.
Bryan Wu1394f032007-05-06 14:50:22 -0700420
Robin Getzf16295e2007-08-03 18:07:17 +0800421config BFIN_KERNEL_CLOCK
422 bool "Re-program Clocks while Kernel boots?"
423 default n
424 help
425 This option decides if kernel clocks are re-programed from the
426 bootloader settings. If the clocks are not set, the SDRAM settings
427 are also not changed, and the Bootloader does 100% of the hardware
428 configuration.
429
430config PLL_BYPASS
Mike Frysingere4e9a7a2007-11-15 20:39:34 +0800431 bool "Bypass PLL"
432 depends on BFIN_KERNEL_CLOCK
433 default n
Robin Getzf16295e2007-08-03 18:07:17 +0800434
435config CLKIN_HALF
436 bool "Half Clock In"
437 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
438 default n
439 help
440 If this is set the clock will be divided by 2, before it goes to the PLL.
441
442config VCO_MULT
443 int "VCO Multiplier"
444 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
445 range 1 64
446 default "22" if BFIN533_EZKIT
447 default "45" if BFIN533_STAMP
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800448 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
Robin Getzf16295e2007-08-03 18:07:17 +0800449 default "22" if BFIN533_BLUETECHNIX_CM
Michael Hennerich9db144f2008-07-19 17:16:07 +0800450 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
Robin Getzf16295e2007-08-03 18:07:17 +0800451 default "20" if BFIN561_EZKIT
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800452 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
Robin Getzf16295e2007-08-03 18:07:17 +0800453 help
454 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
455 PLL Frequency = (Crystal Frequency) * (this setting)
456
457choice
458 prompt "Core Clock Divider"
459 depends on BFIN_KERNEL_CLOCK
460 default CCLK_DIV_1
461 help
462 This sets the frequency of the core. It can be 1, 2, 4 or 8
463 Core Frequency = (PLL frequency) / (this setting)
464
465config CCLK_DIV_1
466 bool "1"
467
468config CCLK_DIV_2
469 bool "2"
470
471config CCLK_DIV_4
472 bool "4"
473
474config CCLK_DIV_8
475 bool "8"
476endchoice
477
478config SCLK_DIV
479 int "System Clock Divider"
480 depends on BFIN_KERNEL_CLOCK
481 range 1 15
Mike Frysinger5f004c22008-04-25 02:11:24 +0800482 default 5
Robin Getzf16295e2007-08-03 18:07:17 +0800483 help
484 This sets the frequency of the system clock (including SDRAM or DDR).
485 This can be between 1 and 15
486 System Clock = (PLL frequency) / (this setting)
487
Mike Frysinger5f004c22008-04-25 02:11:24 +0800488choice
489 prompt "DDR SDRAM Chip Type"
490 depends on BFIN_KERNEL_CLOCK
491 depends on BF54x
492 default MEM_MT46V32M16_5B
493
494config MEM_MT46V32M16_6T
495 bool "MT46V32M16_6T"
496
497config MEM_MT46V32M16_5B
498 bool "MT46V32M16_5B"
499endchoice
500
Michael Hennerich73feb5c2009-01-07 23:14:39 +0800501choice
502 prompt "DDR/SDRAM Timing"
503 depends on BFIN_KERNEL_CLOCK
504 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
505 help
506 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
507 The calculated SDRAM timing parameters may not be 100%
508 accurate - This option is therefore marked experimental.
509
510config BFIN_KERNEL_CLOCK_MEMINIT_CALC
511 bool "Calculate Timings (EXPERIMENTAL)"
512 depends on EXPERIMENTAL
513
514config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
515 bool "Provide accurate Timings based on target SCLK"
516 help
517 Please consult the Blackfin Hardware Reference Manuals as well
518 as the memory device datasheet.
519 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
520endchoice
521
522menu "Memory Init Control"
523 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
524
525config MEM_DDRCTL0
526 depends on BF54x
527 hex "DDRCTL0"
528 default 0x0
529
530config MEM_DDRCTL1
531 depends on BF54x
532 hex "DDRCTL1"
533 default 0x0
534
535config MEM_DDRCTL2
536 depends on BF54x
537 hex "DDRCTL2"
538 default 0x0
539
540config MEM_EBIU_DDRQUE
541 depends on BF54x
542 hex "DDRQUE"
543 default 0x0
544
545config MEM_SDRRC
546 depends on !BF54x
547 hex "SDRRC"
548 default 0x0
549
550config MEM_SDGCTL
551 depends on !BF54x
552 hex "SDGCTL"
553 default 0x0
554endmenu
555
Robin Getzf16295e2007-08-03 18:07:17 +0800556#
557# Max & Min Speeds for various Chips
558#
559config MAX_VCO_HZ
560 int
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800561 default 400000000 if BF512
562 default 400000000 if BF514
563 default 400000000 if BF516
564 default 400000000 if BF518
Robin Getzf16295e2007-08-03 18:07:17 +0800565 default 600000000 if BF522
Mike Frysinger1545a112007-12-24 16:54:48 +0800566 default 400000000 if BF523
567 default 400000000 if BF524
Robin Getzf16295e2007-08-03 18:07:17 +0800568 default 600000000 if BF525
Mike Frysinger1545a112007-12-24 16:54:48 +0800569 default 400000000 if BF526
Robin Getzf16295e2007-08-03 18:07:17 +0800570 default 600000000 if BF527
571 default 400000000 if BF531
572 default 400000000 if BF532
573 default 750000000 if BF533
574 default 500000000 if BF534
575 default 400000000 if BF536
576 default 600000000 if BF537
Robin Getzf72eecb2007-11-21 16:29:20 +0800577 default 533333333 if BF538
578 default 533333333 if BF539
Robin Getzf16295e2007-08-03 18:07:17 +0800579 default 600000000 if BF542
Robin Getzf72eecb2007-11-21 16:29:20 +0800580 default 533333333 if BF544
Mike Frysinger1545a112007-12-24 16:54:48 +0800581 default 600000000 if BF547
582 default 600000000 if BF548
Robin Getzf72eecb2007-11-21 16:29:20 +0800583 default 533333333 if BF549
Robin Getzf16295e2007-08-03 18:07:17 +0800584 default 600000000 if BF561
585
586config MIN_VCO_HZ
587 int
588 default 50000000
589
590config MAX_SCLK_HZ
591 int
Robin Getzf72eecb2007-11-21 16:29:20 +0800592 default 133333333
Robin Getzf16295e2007-08-03 18:07:17 +0800593
594config MIN_SCLK_HZ
595 int
596 default 27000000
597
598comment "Kernel Timer/Scheduler"
599
600source kernel/Kconfig.hz
601
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800602config GENERIC_TIME
603 bool "Generic time"
604 default y
605
606config GENERIC_CLOCKEVENTS
607 bool "Generic clock events"
608 depends on GENERIC_TIME
609 default y
610
Graf Yang1fa9be72009-05-15 11:01:59 +0000611choice
612 prompt "Kernel Tick Source"
613 depends on GENERIC_CLOCKEVENTS
614 default TICKSOURCE_CORETMR
615
616config TICKSOURCE_GPTMR0
617 bool "Gptimer0 (SCLK domain)"
618 select BFIN_GPTIMERS
619 depends on !IPIPE
620
621config TICKSOURCE_CORETMR
622 bool "Core timer (CCLK domain)"
623
624endchoice
625
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800626config CYCLES_CLOCKSOURCE
Graf Yang1fa9be72009-05-15 11:01:59 +0000627 bool "Use 'CYCLES' as a clocksource"
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800628 depends on GENERIC_CLOCKEVENTS
629 depends on !BFIN_SCRATCH_REG_CYCLES
Graf Yang1fa9be72009-05-15 11:01:59 +0000630 depends on !SMP
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800631 help
632 If you say Y here, you will enable support for using the 'cycles'
633 registers as a clock source. Doing so means you will be unable to
634 safely write to the 'cycles' register during runtime. You will
635 still be able to read it (such as for performance monitoring), but
636 writing the registers will most likely crash the kernel.
637
Graf Yang1fa9be72009-05-15 11:01:59 +0000638config GPTMR0_CLOCKSOURCE
639 bool "Use GPTimer0 as a clocksource (higher rating)"
640 depends on GENERIC_CLOCKEVENTS
641 depends on !TICKSOURCE_GPTMR0
642
Vitja Makarov8b5f79f2008-02-29 12:24:23 +0800643source kernel/time/Kconfig
644
Mike Frysinger5f004c22008-04-25 02:11:24 +0800645comment "Misc"
Sonic Zhang971d5bc2008-01-27 16:32:31 +0800646
Mike Frysingerf0b5d122007-08-05 17:03:59 +0800647choice
648 prompt "Blackfin Exception Scratch Register"
649 default BFIN_SCRATCH_REG_RETN
650 help
651 Select the resource to reserve for the Exception handler:
652 - RETN: Non-Maskable Interrupt (NMI)
653 - RETE: Exception Return (JTAG/ICE)
654 - CYCLES: Performance counter
655
656 If you are unsure, please select "RETN".
657
658config BFIN_SCRATCH_REG_RETN
659 bool "RETN"
660 help
661 Use the RETN register in the Blackfin exception handler
662 as a stack scratch register. This means you cannot
663 safely use NMI on the Blackfin while running Linux, but
664 you can debug the system with a JTAG ICE and use the
665 CYCLES performance registers.
666
667 If you are unsure, please select "RETN".
668
669config BFIN_SCRATCH_REG_RETE
670 bool "RETE"
671 help
672 Use the RETE register in the Blackfin exception handler
673 as a stack scratch register. This means you cannot
674 safely use a JTAG ICE while debugging a Blackfin board,
675 but you can safely use the CYCLES performance registers
676 and the NMI.
677
678 If you are unsure, please select "RETN".
679
680config BFIN_SCRATCH_REG_CYCLES
681 bool "CYCLES"
682 help
683 Use the CYCLES register in the Blackfin exception handler
684 as a stack scratch register. This means you cannot
685 safely use the CYCLES performance registers on a Blackfin
686 board at anytime, but you can debug the system with a JTAG
687 ICE and use the NMI.
688
689 If you are unsure, please select "RETN".
690
691endchoice
692
Bryan Wu1394f032007-05-06 14:50:22 -0700693endmenu
694
695
696menu "Blackfin Kernel Optimizations"
Graf Yang46fa5ee2009-01-07 23:14:39 +0800697 depends on !SMP
Bryan Wu1394f032007-05-06 14:50:22 -0700698
Bryan Wu1394f032007-05-06 14:50:22 -0700699comment "Memory Optimizations"
700
701config I_ENTRY_L1
702 bool "Locate interrupt entry code in L1 Memory"
703 default y
704 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200705 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
706 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700707
708config EXCPT_IRQ_SYSC_L1
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200709 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
Bryan Wu1394f032007-05-06 14:50:22 -0700710 default y
711 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200712 If enabled, the entire ASM lowlevel exception and interrupt entry code
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800713 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200714 (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700715
716config DO_IRQ_L1
717 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
718 default y
719 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200720 If enabled, the frequently called do_irq dispatcher function is linked
721 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700722
723config CORE_TIMER_IRQ_L1
724 bool "Locate frequently called timer_interrupt() function in L1 Memory"
725 default y
726 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200727 If enabled, the frequently called timer_interrupt() function is linked
728 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700729
730config IDLE_L1
731 bool "Locate frequently idle function in L1 Memory"
732 default y
733 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200734 If enabled, the frequently called idle function is linked
735 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700736
737config SCHEDULE_L1
738 bool "Locate kernel schedule function in L1 Memory"
739 default y
740 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200741 If enabled, the frequently called kernel schedule is linked
742 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700743
744config ARITHMETIC_OPS_L1
745 bool "Locate kernel owned arithmetic functions in L1 Memory"
746 default y
747 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200748 If enabled, arithmetic functions are linked
749 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700750
751config ACCESS_OK_L1
752 bool "Locate access_ok function in L1 Memory"
753 default y
754 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200755 If enabled, the access_ok function is linked
756 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700757
758config MEMSET_L1
759 bool "Locate memset function in L1 Memory"
760 default y
761 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200762 If enabled, the memset function is linked
763 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700764
765config MEMCPY_L1
766 bool "Locate memcpy function in L1 Memory"
767 default y
768 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200769 If enabled, the memcpy function is linked
770 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700771
772config SYS_BFIN_SPINLOCK_L1
773 bool "Locate sys_bfin_spinlock function in L1 Memory"
774 default y
775 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200776 If enabled, sys_bfin_spinlock function is linked
777 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700778
779config IP_CHECKSUM_L1
780 bool "Locate IP Checksum function in L1 Memory"
781 default n
782 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200783 If enabled, the IP Checksum function is linked
784 into L1 instruction memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700785
786config CACHELINE_ALIGNED_L1
787 bool "Locate cacheline_aligned data to L1 Data Memory"
Michael Hennerich157cc5a2007-07-12 16:20:21 +0800788 default y if !BF54x
789 default n if BF54x
Bryan Wu1394f032007-05-06 14:50:22 -0700790 depends on !BF531
791 help
Matt LaPlante692105b2009-01-26 11:12:25 +0100792 If enabled, cacheline_aligned data is linked
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200793 into L1 data memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700794
795config SYSCALL_TAB_L1
796 bool "Locate Syscall Table L1 Data Memory"
797 default n
798 depends on !BF531
799 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200800 If enabled, the Syscall LUT is linked
801 into L1 data memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700802
803config CPLB_SWITCH_TAB_L1
804 bool "Locate CPLB Switch Tables L1 Data Memory"
805 default n
806 depends on !BF531
807 help
Matt LaPlante01dd2fb2007-10-20 01:34:40 +0200808 If enabled, the CPLB Switch Tables are linked
809 into L1 data memory. (less latency)
Bryan Wu1394f032007-05-06 14:50:22 -0700810
Graf Yangca87b7a2008-10-08 17:30:01 +0800811config APP_STACK_L1
812 bool "Support locating application stack in L1 Scratch Memory"
813 default y
814 help
815 If enabled the application stack can be located in L1
816 scratch memory (less latency).
817
818 Currently only works with FLAT binaries.
819
Mike Frysinger6ad2b842008-10-28 11:03:09 +0800820config EXCEPTION_L1_SCRATCH
821 bool "Locate exception stack in L1 Scratch Memory"
822 default n
Graf Yangf82e0a02009-04-08 08:30:22 +0000823 depends on !APP_STACK_L1
Mike Frysinger6ad2b842008-10-28 11:03:09 +0800824 help
825 Whenever an exception occurs, use the L1 Scratch memory for
826 stack storage. You cannot place the stacks of FLAT binaries
827 in L1 when using this option.
828
829 If you don't use L1 Scratch, then you should say Y here.
830
Robin Getz251383c2008-08-14 15:12:55 +0800831comment "Speed Optimizations"
832config BFIN_INS_LOWOVERHEAD
833 bool "ins[bwl] low overhead, higher interrupt latency"
834 default y
835 help
836 Reads on the Blackfin are speculative. In Blackfin terms, this means
837 they can be interrupted at any time (even after they have been issued
838 on to the external bus), and re-issued after the interrupt occurs.
839 For memory - this is not a big deal, since memory does not change if
840 it sees a read.
841
842 If a FIFO is sitting on the end of the read, it will see two reads,
843 when the core only sees one since the FIFO receives both the read
844 which is cancelled (and not delivered to the core) and the one which
845 is re-issued (which is delivered to the core).
846
847 To solve this, interrupts are turned off before reads occur to
848 I/O space. This option controls which the overhead/latency of
849 controlling interrupts during this time
850 "n" turns interrupts off every read
851 (higher overhead, but lower interrupt latency)
852 "y" turns interrupts off every loop
853 (low overhead, but longer interrupt latency)
854
855 default behavior is to leave this set to on (type "Y"). If you are experiencing
856 interrupt latency issues, it is safe and OK to turn this off.
857
Bryan Wu1394f032007-05-06 14:50:22 -0700858endmenu
859
Bryan Wu1394f032007-05-06 14:50:22 -0700860choice
861 prompt "Kernel executes from"
862 help
863 Choose the memory type that the kernel will be running in.
864
865config RAMKERNEL
866 bool "RAM"
867 help
868 The kernel will be resident in RAM when running.
869
870config ROMKERNEL
871 bool "ROM"
872 help
873 The kernel will be resident in FLASH/ROM when running.
874
875endchoice
876
877source "mm/Kconfig"
878
Mike Frysinger780431e2007-10-21 23:37:54 +0800879config BFIN_GPTIMERS
880 tristate "Enable Blackfin General Purpose Timers API"
881 default n
882 help
883 Enable support for the General Purpose Timers API. If you
884 are unsure, say N.
885
886 To compile this driver as a module, choose M here: the module
887 will be called gptimers.ko.
888
Bryan Wu1394f032007-05-06 14:50:22 -0700889choice
Mike Frysingerd292b002008-10-28 11:15:36 +0800890 prompt "Uncached DMA region"
Bryan Wu1394f032007-05-06 14:50:22 -0700891 default DMA_UNCACHED_1M
Cliff Cai86ad7932008-05-17 16:36:52 +0800892config DMA_UNCACHED_4M
893 bool "Enable 4M DMA region"
Bryan Wu1394f032007-05-06 14:50:22 -0700894config DMA_UNCACHED_2M
895 bool "Enable 2M DMA region"
896config DMA_UNCACHED_1M
897 bool "Enable 1M DMA region"
898config DMA_UNCACHED_NONE
899 bool "Disable DMA region"
900endchoice
901
902
903comment "Cache Support"
Robin Getz3bebca22007-10-10 23:55:26 +0800904config BFIN_ICACHE
Bryan Wu1394f032007-05-06 14:50:22 -0700905 bool "Enable ICACHE"
Robin Getz3bebca22007-10-10 23:55:26 +0800906config BFIN_DCACHE
Bryan Wu1394f032007-05-06 14:50:22 -0700907 bool "Enable DCACHE"
Robin Getz3bebca22007-10-10 23:55:26 +0800908config BFIN_DCACHE_BANKA
Bryan Wu1394f032007-05-06 14:50:22 -0700909 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
Robin Getz3bebca22007-10-10 23:55:26 +0800910 depends on BFIN_DCACHE && !BF531
Bryan Wu1394f032007-05-06 14:50:22 -0700911 default n
Robin Getz3bebca22007-10-10 23:55:26 +0800912config BFIN_ICACHE_LOCK
913 bool "Enable Instruction Cache Locking"
Bryan Wu1394f032007-05-06 14:50:22 -0700914
915choice
Graf Yang5ba76672009-05-07 04:09:15 +0000916 prompt "External memory cache policy"
Robin Getz3bebca22007-10-10 23:55:26 +0800917 depends on BFIN_DCACHE
Graf Yang46fa5ee2009-01-07 23:14:39 +0800918 default BFIN_WB if !SMP
919 default BFIN_WT if SMP
Robin Getz3bebca22007-10-10 23:55:26 +0800920config BFIN_WB
Bryan Wu1394f032007-05-06 14:50:22 -0700921 bool "Write back"
Graf Yang46fa5ee2009-01-07 23:14:39 +0800922 depends on !SMP
Bryan Wu1394f032007-05-06 14:50:22 -0700923 help
924 Write Back Policy:
925 Cached data will be written back to SDRAM only when needed.
926 This can give a nice increase in performance, but beware of
927 broken drivers that do not properly invalidate/flush their
928 cache.
929
930 Write Through Policy:
931 Cached data will always be written back to SDRAM when the
932 cache is updated. This is a completely safe setting, but
933 performance is worse than Write Back.
934
935 If you are unsure of the options and you want to be safe,
936 then go with Write Through.
937
Robin Getz3bebca22007-10-10 23:55:26 +0800938config BFIN_WT
Bryan Wu1394f032007-05-06 14:50:22 -0700939 bool "Write through"
940 help
941 Write Back Policy:
942 Cached data will be written back to SDRAM only when needed.
943 This can give a nice increase in performance, but beware of
944 broken drivers that do not properly invalidate/flush their
945 cache.
946
947 Write Through Policy:
948 Cached data will always be written back to SDRAM when the
949 cache is updated. This is a completely safe setting, but
950 performance is worse than Write Back.
951
952 If you are unsure of the options and you want to be safe,
953 then go with Write Through.
954
955endchoice
956
Graf Yang5ba76672009-05-07 04:09:15 +0000957choice
958 prompt "L2 SRAM cache policy"
959 depends on (BF54x || BF561)
960 default BFIN_L2_WT
961config BFIN_L2_WB
962 bool "Write back"
963 depends on !SMP
964
965config BFIN_L2_WT
966 bool "Write through"
967 depends on !SMP
968
969config BFIN_L2_NOT_CACHED
970 bool "Not cached"
971
972endchoice
Sonic Zhangf099f392008-10-09 14:11:57 +0800973
Bernd Schmidtb97b8a92008-01-27 18:39:16 +0800974config MPU
975 bool "Enable the memory protection unit (EXPERIMENTAL)"
976 default n
977 help
978 Use the processor's MPU to protect applications from accessing
979 memory they do not own. This comes at a performance penalty
980 and is recommended only for debugging.
981
Matt LaPlante692105b2009-01-26 11:12:25 +0100982comment "Asynchronous Memory Configuration"
Bryan Wu1394f032007-05-06 14:50:22 -0700983
Mike Frysingerddf416b2007-10-10 18:06:47 +0800984menu "EBIU_AMGCTL Global Control"
Bryan Wu1394f032007-05-06 14:50:22 -0700985config C_AMCKEN
986 bool "Enable CLKOUT"
987 default y
988
989config C_CDPRIO
990 bool "DMA has priority over core for ext. accesses"
991 default n
992
993config C_B0PEN
994 depends on BF561
995 bool "Bank 0 16 bit packing enable"
996 default y
997
998config C_B1PEN
999 depends on BF561
1000 bool "Bank 1 16 bit packing enable"
1001 default y
1002
1003config C_B2PEN
1004 depends on BF561
1005 bool "Bank 2 16 bit packing enable"
1006 default y
1007
1008config C_B3PEN
1009 depends on BF561
1010 bool "Bank 3 16 bit packing enable"
1011 default n
1012
1013choice
Matt LaPlante692105b2009-01-26 11:12:25 +01001014 prompt "Enable Asynchronous Memory Banks"
Bryan Wu1394f032007-05-06 14:50:22 -07001015 default C_AMBEN_ALL
1016
1017config C_AMBEN
1018 bool "Disable All Banks"
1019
1020config C_AMBEN_B0
1021 bool "Enable Bank 0"
1022
1023config C_AMBEN_B0_B1
1024 bool "Enable Bank 0 & 1"
1025
1026config C_AMBEN_B0_B1_B2
1027 bool "Enable Bank 0 & 1 & 2"
1028
1029config C_AMBEN_ALL
1030 bool "Enable All Banks"
1031endchoice
1032endmenu
1033
1034menu "EBIU_AMBCTL Control"
1035config BANK_0
Mike Frysingerc8342f82009-03-31 00:18:35 +00001036 hex "Bank 0 (AMBCTL0.L)"
Bryan Wu1394f032007-05-06 14:50:22 -07001037 default 0x7BB0
Mike Frysingerc8342f82009-03-31 00:18:35 +00001038 help
1039 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1040 used to control the Asynchronous Memory Bank 0 settings.
Bryan Wu1394f032007-05-06 14:50:22 -07001041
1042config BANK_1
Mike Frysingerc8342f82009-03-31 00:18:35 +00001043 hex "Bank 1 (AMBCTL0.H)"
Bryan Wu1394f032007-05-06 14:50:22 -07001044 default 0x7BB0
Michael Hennerich197fba52008-05-07 17:03:27 +08001045 default 0x5558 if BF54x
Mike Frysingerc8342f82009-03-31 00:18:35 +00001046 help
1047 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1048 used to control the Asynchronous Memory Bank 1 settings.
Bryan Wu1394f032007-05-06 14:50:22 -07001049
1050config BANK_2
Mike Frysingerc8342f82009-03-31 00:18:35 +00001051 hex "Bank 2 (AMBCTL1.L)"
Bryan Wu1394f032007-05-06 14:50:22 -07001052 default 0x7BB0
Mike Frysingerc8342f82009-03-31 00:18:35 +00001053 help
1054 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1055 used to control the Asynchronous Memory Bank 2 settings.
Bryan Wu1394f032007-05-06 14:50:22 -07001056
1057config BANK_3
Mike Frysingerc8342f82009-03-31 00:18:35 +00001058 hex "Bank 3 (AMBCTL1.H)"
Bryan Wu1394f032007-05-06 14:50:22 -07001059 default 0x99B3
Mike Frysingerc8342f82009-03-31 00:18:35 +00001060 help
1061 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1062 used to control the Asynchronous Memory Bank 3 settings.
1063
Bryan Wu1394f032007-05-06 14:50:22 -07001064endmenu
1065
Sonic Zhange40540b2007-11-21 23:49:52 +08001066config EBIU_MBSCTLVAL
1067 hex "EBIU Bank Select Control Register"
1068 depends on BF54x
1069 default 0
1070
1071config EBIU_MODEVAL
1072 hex "Flash Memory Mode Control Register"
1073 depends on BF54x
1074 default 1
1075
1076config EBIU_FCTLVAL
1077 hex "Flash Memory Bank Control Register"
1078 depends on BF54x
1079 default 6
Bryan Wu1394f032007-05-06 14:50:22 -07001080endmenu
1081
1082#############################################################################
1083menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1084
1085config PCI
1086 bool "PCI support"
Adrian Bunka95ca3b2008-08-27 10:55:05 +08001087 depends on BROKEN
Bryan Wu1394f032007-05-06 14:50:22 -07001088 help
1089 Support for PCI bus.
1090
1091source "drivers/pci/Kconfig"
1092
1093config HOTPLUG
1094 bool "Support for hot-pluggable device"
1095 help
1096 Say Y here if you want to plug devices into your computer while
1097 the system is running, and be able to use them quickly. In many
1098 cases, the devices can likewise be unplugged at any time too.
1099
1100 One well known example of this is PCMCIA- or PC-cards, credit-card
1101 size devices such as network cards, modems or hard drives which are
1102 plugged into slots found on all modern laptop computers. Another
1103 example, used on modern desktops as well as laptops, is USB.
1104
Johannes Berga81792f2008-07-08 19:00:25 +02001105 Enable HOTPLUG and build a modular kernel. Get agent software
1106 (from <http://linux-hotplug.sourceforge.net/>) and install it.
Bryan Wu1394f032007-05-06 14:50:22 -07001107 Then your kernel will automatically call out to a user mode "policy
1108 agent" (/sbin/hotplug) to load modules and set up software needed
1109 to use devices as you hotplug them.
1110
1111source "drivers/pcmcia/Kconfig"
1112
1113source "drivers/pci/hotplug/Kconfig"
1114
1115endmenu
1116
1117menu "Executable file formats"
1118
1119source "fs/Kconfig.binfmt"
1120
1121endmenu
1122
1123menu "Power management options"
1124source "kernel/power/Kconfig"
1125
Johannes Bergf4cb5702007-12-08 02:14:00 +01001126config ARCH_SUSPEND_POSSIBLE
1127 def_bool y
1128 depends on !SMP
1129
Bryan Wu1394f032007-05-06 14:50:22 -07001130choice
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001131 prompt "Standby Power Saving Mode"
Bryan Wu1394f032007-05-06 14:50:22 -07001132 depends on PM
Michael Hennerichcfefe3c2008-02-09 04:12:37 +08001133 default PM_BFIN_SLEEP_DEEPER
1134config PM_BFIN_SLEEP_DEEPER
1135 bool "Sleep Deeper"
Bryan Wu1394f032007-05-06 14:50:22 -07001136 help
Michael Hennerichcfefe3c2008-02-09 04:12:37 +08001137 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1138 power dissipation by disabling the clock to the processor core (CCLK).
1139 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1140 to 0.85 V to provide the greatest power savings, while preserving the
1141 processor state.
1142 The PLL and system clock (SCLK) continue to operate at a very low
1143 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1144 the SDRAM is put into Self Refresh Mode. Typically an external event
1145 such as GPIO interrupt or RTC activity wakes up the processor.
1146 Various Peripherals such as UART, SPORT, PPI may not function as
1147 normal during Sleep Deeper, due to the reduced SCLK frequency.
1148 When in the sleep mode, system DMA access to L1 memory is not supported.
Bryan Wu1394f032007-05-06 14:50:22 -07001149
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001150 If unsure, select "Sleep Deeper".
1151
Michael Hennerichcfefe3c2008-02-09 04:12:37 +08001152config PM_BFIN_SLEEP
1153 bool "Sleep"
1154 help
1155 Sleep Mode (High Power Savings) - The sleep mode reduces power
1156 dissipation by disabling the clock to the processor core (CCLK).
1157 The PLL and system clock (SCLK), however, continue to operate in
1158 this mode. Typically an external event or RTC activity will wake
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001159 up the processor. When in the sleep mode, system DMA access to L1
1160 memory is not supported.
1161
1162 If unsure, select "Sleep Deeper".
Bryan Wu1394f032007-05-06 14:50:22 -07001163endchoice
1164
Michael Hennerichcfefe3c2008-02-09 04:12:37 +08001165config PM_WAKEUP_BY_GPIO
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001166 bool "Allow Wakeup from Standby by GPIO"
Michael Hennerichff19fed2009-03-04 17:35:51 +08001167 depends on PM && !BF54x
Bryan Wu1394f032007-05-06 14:50:22 -07001168
1169config PM_WAKEUP_GPIO_NUMBER
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001170 int "GPIO number"
Bryan Wu1394f032007-05-06 14:50:22 -07001171 range 0 47
1172 depends on PM_WAKEUP_BY_GPIO
Mike Frysingerd1a33362008-11-18 17:48:22 +08001173 default 2
Bryan Wu1394f032007-05-06 14:50:22 -07001174
1175choice
1176 prompt "GPIO Polarity"
1177 depends on PM_WAKEUP_BY_GPIO
1178 default PM_WAKEUP_GPIO_POLAR_H
1179config PM_WAKEUP_GPIO_POLAR_H
1180 bool "Active High"
1181config PM_WAKEUP_GPIO_POLAR_L
1182 bool "Active Low"
1183config PM_WAKEUP_GPIO_POLAR_EDGE_F
1184 bool "Falling EDGE"
1185config PM_WAKEUP_GPIO_POLAR_EDGE_R
1186 bool "Rising EDGE"
1187config PM_WAKEUP_GPIO_POLAR_EDGE_B
1188 bool "Both EDGE"
1189endchoice
1190
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001191comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1192 depends on PM
1193
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001194config PM_BFIN_WAKE_PH6
1195 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
Bryan Wu2f6f4bc2008-11-18 17:48:21 +08001196 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001197 default n
1198 help
1199 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1200
Michael Hennerich1efc80b2008-07-19 16:57:32 +08001201config PM_BFIN_WAKE_GP
1202 bool "Allow Wake-Up from GPIOs"
1203 depends on PM && BF54x
1204 default n
1205 help
1206 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
Michael Hennerich19986282009-03-05 16:45:55 +08001207 (all processors, except ADSP-BF549). This option sets
1208 the general-purpose wake-up enable (GPWE) control bit to enable
1209 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1210 On ADSP-BF549 this option enables the the same functionality on the
1211 /MRXON pin also PH7.
1212
Bryan Wu1394f032007-05-06 14:50:22 -07001213endmenu
1214
Bryan Wu1394f032007-05-06 14:50:22 -07001215menu "CPU Frequency scaling"
1216
1217source "drivers/cpufreq/Kconfig"
1218
Michael Hennerich5ad2ca52008-11-18 17:48:22 +08001219config BFIN_CPU_FREQ
1220 bool
1221 depends on CPU_FREQ
1222 select CPU_FREQ_TABLE
1223 default y
1224
Michael Hennerich14b03202008-05-07 11:41:26 +08001225config CPU_VOLTAGE
1226 bool "CPU Voltage scaling"
Michael Hennerich73feb5c2009-01-07 23:14:39 +08001227 depends on EXPERIMENTAL
Michael Hennerich14b03202008-05-07 11:41:26 +08001228 depends on CPU_FREQ
1229 default n
1230 help
1231 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1232 This option violates the PLL BYPASS recommendation in the Blackfin Processor
Michael Hennerich73feb5c2009-01-07 23:14:39 +08001233 manuals. There is a theoretical risk that during VDDINT transitions
Michael Hennerich14b03202008-05-07 11:41:26 +08001234 the PLL may unlock.
1235
Bryan Wu1394f032007-05-06 14:50:22 -07001236endmenu
1237
Bryan Wu1394f032007-05-06 14:50:22 -07001238source "net/Kconfig"
1239
1240source "drivers/Kconfig"
1241
1242source "fs/Kconfig"
1243
Mike Frysinger74ce8322007-11-21 23:50:49 +08001244source "arch/blackfin/Kconfig.debug"
Bryan Wu1394f032007-05-06 14:50:22 -07001245
1246source "security/Kconfig"
1247
1248source "crypto/Kconfig"
1249
1250source "lib/Kconfig"